Porous silicon carbide (SIC) semiconductor device

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

All-silica nanofluidic devices for DNA-analysis fabricated by imprint of sol-gel silica with silicon stamp

DEFF Research Database (Denmark)

Mikkelsen, Morten Bo Lindholm; Letailleur, Alban A; Søndergård, Elin

2011-01-01

We present a simple and cheap method for fabrication of silica nanofluidic devices for single-molecule studies. By imprinting sol-gel materials with a multi-level stamp comprising micro- and nanofeatures, channels of different depth are produced in a single process step. Calcination of the imprin......We present a simple and cheap method for fabrication of silica nanofluidic devices for single-molecule studies. By imprinting sol-gel materials with a multi-level stamp comprising micro- and nanofeatures, channels of different depth are produced in a single process step. Calcination...... of the imprinted hybrid sol-gel material produces purely inorganic silica, which has very low autofluorescence and can be fusion bonded to a glass lid. Compared to top-down processing of fused silica or silicon substrates, imprint of sol-gel silica enables fabrication of high-quality nanofluidic devices without...

Method of fabricating porous silicon carbide (SiC)

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Fabrication and optical characterization of light trapping silicon nanopore and nanoscrew devices

International Nuclear Information System (INIS)

Jin, Hyunjong; Logan Liu, G

2012-01-01

We have fabricated nanotextured Si substrates that exhibit controllable optical reflection intensities and colors. Si nanopore has a photon trapping nanostructure but has abrupt changes in the index of refraction displaying a darkened specular reflection. Nanoscrew Si shows graded refractive-index photon trapping structures that enable diffuse reflection to be as low as 2.2% over the visible wavelengths. By tuning the 3D nanoscale silicon structure, the optical reflection peak wavelength and intensity are changed in the wavelength range of 300–800 nm, making the surface have different reflectivity and apparent colors. The relation between the surface optical properties with the spatial features of the photon trapping nanostructures is examined. Integration of photon trapping structures with planar Si structure on the same substrate is also demonstrated. The tunable photon trapping silicon structures have potential applications in enhancing the performance of semiconductor photoelectric devices. (paper)

Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

International Nuclear Information System (INIS)

Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

2013-01-01

Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

Energy Technology Data Exchange (ETDEWEB)

Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

2009-06-10

We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

Micro-fabricated silicon devices for advanced thermal management and integration of particle tracking detectors

CERN Document Server

Romagnoli, Giulia; Gambaro, Carla

Since their first studies targeting the cooling of high-power computing chips, micro-channel devices are proven to provide a very efficient cooling system. In the last years micro-channel cooling has been successfully applied to the cooling of particle detectors at CERN. Thanks to their high thermal efficiency, they can guarantee a good heat sink for the cooling of silicon trackers, fundamental for the reduction of the radiation damage caused by the beam interactions. The radiation damage on the silicon detector is increasing with temperature and furthermore the detectors are producing heat that should be dissipated in the supporting structure. Micro-channels guarantee a distributed and uniform thermal exchange, thanks to the high flexibility of the micro-fabrication process that allows a large variety of channel designs. The thin nature of the micro-channels etched inside silicon wafers, is fulfilling the physics requirement of minimization of the material crossed by the particle beam. Furthermore micro-chan...

Solid state MEMS devices on flexible and semi-transparent silicon (100) platform

KAUST Repository

Ahmed, Sally; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2014-01-01

We report fabrication of MEMS thermal actuators on flexible and semi-transparent silicon fabric released from bulk silicon (100). We fabricated the devices first and then released the top portion of the silicon (≈ 19 μm) which is flexible and semi-transparent. We also performed chemical mechanical polishing to reuse the remaining wafer. A tested thermal actuator with 3 μm wide 240 μm hot arm and 10 μm wide 185 μm long cold arm deflected by 1.7 μm at 1 V. The fabricated thermal actuators exhibit similar performance before and after bending. We believe the demonstrated process will expand the horizon of flexible electronics into MEMS world devices. © 2014 IEEE.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-02-12

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Synthesis and properties of silicon nanowire devices

Science.gov (United States)

Byon, Kumhyo

Silicon nanowire (SiNW) is a very attractive one-dimensional material for future nanoelectronic applications. Reliable control of key field effect transistor (FET) parameters such as conductance, mobility, threshold voltage and on/off ratio is crucial to the applications of SiNW to working logic devices and integrated circuits. In this thesis, we fabricated silicon nanowire field effect transistors (SiNW FETs) and studied the dependence of their electrical transport properties upon various parameters including SiNW growth conditions, post-growth doping, and contact annealing. From these studies, we found how different processes control important FET characteristics. Key accomplishments of this thesis include p-channel enhancement mode FETs, n-channel FETs by post-growth vapor doping and high performance ambipolar devices. In the first part of this work, single crystalline SiNWs were synthesized by thermal evaporation without gold catalysts. FETs were fabricated using both as-grown SiNWs and post-growth n-doped SiNWs. FET from p-type source materials behaves as a p-channel enhancement mode FET which is predominant in logic devices due to its fast operation and low power consumption. Using bismuth vapor, the as-grown SiNWs were doped into n-type materials. The majority carriers in SiNWs can therefore be controlled by proper choice of the vapor phase dopant species. Post-growth doping using vapor phase is applicable to other nanowire systems. In the second part, high performance ambipolar FETs were fabricated. A two step annealing process was used to control the Schottky barrier between SiNW and metal contacts in order to enhance device performance. Initial p-channel SiNW FETs were converted into ambipolar SiNW FETs after contact annealing. Furthermore, significant increases in both on/off ratio and channel mobilities were achieved after contact annealing. Promising device structures to implement ambipolar devices into large scale integrated circuits were proposed

Proton irradiation effects in silicon devices

Energy Technology Data Exchange (ETDEWEB)

Simoen, E; Vanhellemont, J; Alaerts, A [IMEC, Leuven (Belgium); and others

1997-03-01

Proton irradiation effects in silicon devices are studied for components fabricated in various substrates in order to reveal possible hardening effects. The degradation of p-n junction diodes increases in first order proportionally with the fluence, when submitted to 10 MeV proton irradiations in the range 5x10{sup 9} cm{sup -2} to 5x10{sup 11} cm{sup -2}. The damage coefficients for both p- and n-type Czochralski, Float-Zone and epitaxial wafers are reported. Charge-Coupled Devices fabricated in a 1.2 {mu}m CCD-CMOS technology are shown to be quite resistant to 59 MeV H{sup +} irradiations, irrespective of the substrate type. (author)

Flexible Thermoelectric Generators on Silicon Fabric

KAUST Repository

Sevilla, Galo T.

2012-11-01

In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

Symmetrical waveguide devices fabricated by direct UV writing

DEFF Research Database (Denmark)

Færch, Kjartan Ullitz; Svalgaard, Mikael

2002-01-01

Power splitters and directional couplers fabricated by direct UV writing in index matched silica-on-silicon samples can suffer from an asymmetrical device performance, even though the UV writing is carried out in a symmetrical fashion. This effect originates from a reduced photosensitivity...

The design and investigation of hybrid ferromagnetic/silicon spin electronic devices

International Nuclear Information System (INIS)

Pugh, D.I.

2001-01-01

The focus of this study concerns the design and investigation of ferromagnetic/silicon hybrid spin electronic devices as part of a wider project to design a novel spin valve transistor. The key issue to obtain a room temperature spin electronic device is the electrical injection of a spin polarised current from a ferromagnetic contact into a semiconductor. Despite many attempts concentrating on GaAs and InAs only small (< 1%) effects have been observed, making it difficult to confirm spin injection. Lateral devices were designed and fabricated using standard device fabrication procedures to produce arrays of Co/Si/So junctions. Subsequent designs aimed to reduce the number of junctions and improve device isolation. Evidence for spin dependent MR of up to 0.56% was observed in Co/p-Si/Co junctions with silicon gaps up to 16 μm in length. The maximum MR was observed when the first Co/Si Schottky barrier was reverse biased forming a high resistance interface. Vertical devices were designed in an attempt to eliminate any alternative current paths by using a well defined, 1 μm thick silicon membrane. Despite attempts to include oxide barriers, no spin dependent MR was observed in these devices. However, a novel vertical silicon based design has been made which should facilitate further advanced studies of spin injection and transport. The spin diffusion length in n-type silicon has been calculated as a function of doping concentration and temperature by considering the spin relaxation mechanisms in the semiconductor. Discussion has been made concerning p-type silicon and comparisons made with GaAs, indicating that n-Si should show longer spin diffusion lengths. The key design criteria for designing room temperature spin electronic devices have been highlighted. These include the use of a high leakage Schottky barrier or tunnel barrier between the ferromagnet and p-Si and a contact to the silicon to enable appropriate biasing to each FM/Si interface. (author)

Self-assembled peptide nanotubes as an etching material for the rapid fabrication of silicon wires

DEFF Research Database (Denmark)

Larsen, Martin Benjamin Barbour Spanget; Andersen, Karsten Brandt; Svendsen, Winnie Edith

2011-01-01

This study has evaluated self-assembled peptide nanotubes (PNTS) and nanowires (PNWS) as etching mask materials for the rapid and low-cost fabrication of silicon wires using reactive ion etching (RIE). The self-assembled peptide structures were fabricated under mild conditions and positioned on c...... characterization by SEM and I-V measurements. Additionally, the fabricated silicon structures were functionalized with fluorescent molecules via a biotin-streptavidin interaction in order to probe their potential in the development of biosensing devices....

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film

International Nuclear Information System (INIS)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-01-01

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices’ applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H 2 O 2 /HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing. (paper)

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film.

Science.gov (United States)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-04-17

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices' applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H2O2/HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing.

Design Procedure and Fabrication of Reproducible Silicon Vernier Devices for High-Performance Refractive Index Sensing.

Science.gov (United States)

Troia, Benedetto; Khokhar, Ali Z; Nedeljkovic, Milos; Reynolds, Scott A; Hu, Youfang; Mashanovich, Goran Z; Passaro, Vittorio M N

2015-06-10

In this paper, we propose a generalized procedure for the design of integrated Vernier devices for high performance chemical and biochemical sensing. In particular, we demonstrate the accurate control of the most critical design and fabrication parameters of silicon-on-insulator cascade-coupled racetrack resonators operating in the second regime of the Vernier effect, around 1.55 μm. The experimental implementation of our design strategies has allowed a rigorous and reliable investigation of the influence of racetrack resonator and directional coupler dimensions as well as of waveguide process variability on the operation of Vernier devices. Figures of merit of our Vernier architectures have been measured experimentally, evidencing a high reproducibility and a very good agreement with the theoretical predictions, as also confirmed by relative errors even lower than 1%. Finally, a Vernier gain as high as 30.3, average insertion loss of 2.1 dB and extinction ratio up to 30 dB have been achieved.

Silicone nanocomposite coatings for fabrics

Science.gov (United States)

Eberts, Kenneth (Inventor); Lee, Stein S. (Inventor); Singhal, Amit (Inventor); Ou, Runqing (Inventor)

2011-01-01

A silicone based coating for fabrics utilizing dual nanocomposite fillers providing enhanced mechanical and thermal properties to the silicone base. The first filler includes nanoclusters of polydimethylsiloxane (PDMS) and a metal oxide and a second filler of exfoliated clay nanoparticles. The coating is particularly suitable for inflatable fabrics used in several space, military, and consumer applications, including airbags, parachutes, rafts, boat sails, and inflatable shelters.

Technology of fabrication of silicon-lithium detector with superficial junction

International Nuclear Information System (INIS)

Cabal Rodriguez, A.E.; Diaz Garcia, A.; Noriega Scull, C.

1997-01-01

The Silicon nuclear radiation detectors transform the charge produced within the semiconductor crystal, product of the impinges of particles and X rays, in pulses of voltage at the output of the preamplifier. The planar Silicon-Lithium (Si(Li)) detector with superficial junction is basically a Pin structure diode. By mean of the diffusion and drift of Lithium in the Silicon a compensated or depletion region was created. There the incident radiation interacts with the Silicon, producing an electric signal proportional to the detector's energy deposited in the semiconductor. The technological process of fabrication this kind of detectors comprises several stages, some of them complex and of long duration. They also demand a systematic control. The technological process of Si(Li) detector's fabrication was carried out. The detector's fabrication electric characteristics were measured in some steps. An obtained device was mounted in the holder within a cryostat, in order to work to temperature of the liquid nitrogen. The energy resolution of the detector was measured and the value was 180 eV for the line of 5.9 KeV of an Fe-55 source. This value has allowed to work with the detector in energy disperse X-rays fluorescence. (author) [es

Silicon oxide nanoimprint stamp fabrication by edge lithography reinforced with silicon nitride

NARCIS (Netherlands)

Zhao, Yiping; Berenschot, Johan W.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

2007-01-01

The fabrication of silicon oxide nanoimprint stamp employing edge lithography in combination with silicon nitride deposition is presented. The fabrication process is based on conventional photolithography an weg etching methods. Nanoridges with width dimension of sub-20 nm were fabricated by edge

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Design, fabrication and transportation of Si rotating device

International Nuclear Information System (INIS)

Kimura, Nobuaki; Imaizumi, Tomomi; Takemoto, Noriyuki; Tanimoto, Masataka; Saito, Takashi; Hori, Naohiko; Tsuchiya, Kunihiko; Romanova, Nataliya; Gizatulin, Shamil; Martyushov, Alexandr; Nakipov, Darkhan; Chakrov, Petr; Tanaka, Futoshi; Nakajima, Takeshi

2012-06-01

Si semiconductor production by Neutron Transmutation Doping (NTD) method using the Japan Materials Testing Reactor (JMTR) has been investigated in Neutron Irradiation and Testing Reactor Center, Japan Atomic Energy Agency (JAEA) in order to expand industry use. As a part of investigations, irradiation test of silicon ingot for development of NTD-Si with high quality was planned using WWR-K in Institute of Nuclear Physics (INP), National Nuclear Center of Republic of Kazakhstan (NNC-RK) based on one of specific topics of cooperation (STC), Irradiation Technology for NTD-Si (STC No.II-4), on the implementing arrangement between NNC-RK and the JAEA for 'Nuclear Technology on Testing/Research Reactors' in cooperation in research and development in nuclear energy and technology. As for the irradiation test, Si rotating device was fabricated in JAEA, and the fabricated device was transported with irradiation specimens from JAEA to INP-NNC-RK. This report described the design, the fabrication, the performance test of the Si rotating device and transportation procedures. (author)

3D printing for health & wealth: Fabrication of custom-made medical devices through additive manufacturing

Science.gov (United States)

Colpani, Alessandro; Fiorentino, Antonio; Ceretti, Elisabetta

2018-05-01

Additive Manufacturing (AM) differs from traditional manufacturing technologies by its ability to handle complex shapes with great design flexibility. These features make the technique suitable to fabricate customized components, particularly answering specific custom needs. Although AM mainly referred to prototyping, nowadays the interest in direct manufacturing of actual parts is growing. This article shows the application of AM within the project 3DP-4H&W (3D Printing for Health & Wealth) which involves engineers and physicians for developing pediatric custom-made medical devices to enhance the fulfilling of the patients specific needs. In the project, two types of devices made of a two-component biocompatible silicone are considered. The first application (dental field) consists in a device for cleft lip and palate. The second one (audiological field) consists in an acoustic prosthesis. The geometries of the devices are based on the anatomy of the patient that is obtained through a 3D body scan process. For both devices, two different approaches were planned, namely direct AM and indirect Rapid Tooling (RT). In particular, direct AM consists in the FDM processing of silicone, while RT consists in molds FDM fabrication followed by silicone casting. This paper presents the results of the RT method that is articulated in different phases: the acquisition of the geometry to be realized, the design of the molds taking into account the casting feasibility (as casting channel, vents, part extraction), the realization of molds produced through AM, molds surface chemical finishing, pouring and curing of the silicone. The fabricated devices were evaluated by the physicians team that confirmed the effectiveness of the proposed procedure in fabricating the desired devices. Moreover, the procedure can be used as a general method to extend the range of applications to any custom-made device for anatomic districts, especially where complex shapes are present (as tracheal or

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

Fabrication of wear-resistant silicon microprobe tips for high-speed surface roughness scanning devices

Science.gov (United States)

Wasisto, Hutomo Suryo; Yu, Feng; Doering, Lutz; Völlmeke, Stefan; Brand, Uwe; Bakin, Andrey; Waag, Andreas; Peiner, Erwin

2015-05-01

Silicon microprobe tips are fabricated and integrated with piezoresistive cantilever sensors for high-speed surface roughness scanning systems. The fabrication steps of the high-aspect-ratio silicon microprobe tips were started with photolithography and wet etching of potassium hydroxide (KOH) resulting in crystal-dependent micropyramids. Subsequently, thin conformal wear-resistant layer coating of aluminum oxide (Al2O3) was demonstrated on the backside of the piezoresistive cantilever free end using atomic layer deposition (ALD) method in a binary reaction sequence with a low thermal process and precursors of trimethyl aluminum and water. The deposited Al2O3 layer had a thickness of 14 nm. The captured atomic force microscopy (AFM) image exhibits a root mean square deviation of 0.65 nm confirming the deposited Al2O3 surface quality. Furthermore, vacuum-evaporated 30-nm/200-nm-thick Au/Cr layers were patterned by lift-off and served as an etch mask for Al2O3 wet etching and in ICP cryogenic dry etching. By using SF6/O2 plasma during inductively coupled plasma (ICP) cryogenic dry etching, micropillar tips were obtained. From the preliminary friction and wear data, the developed silicon cantilever sensor has been successfully used in 100 fast measurements of 5- mm-long standard artifact surface with a speed of 15 mm/s and forces of 60-100 μN. Moreover, the results yielded by the fabricated silicon cantilever sensor are in very good agreement with those of calibrated profilometer. These tactile sensors are targeted for use in high-aspect-ratio microform metrology.

Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

DEFF Research Database (Denmark)

Strobel, S.; Albert, E.; Csaba, G.

2009-01-01

We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

Hemispherical cavities on silicon substrates: an overview of micro fabrication techniques

Science.gov (United States)

Poncelet, O.; Rasson, J.; Tuyaerts, R.; Coulombier, M.; Kotipalli, R.; Raskin, J.-P.; Francis, L. A.

2018-04-01

Hemispherical photonic crystals found in species like Papilio blumei and Cicendella chinensis have inspired new applications like anti-counterfeiting devices and gas sensors. In this work, we investigate and compare four different ways to micro fabricate such hemispherical cavities: using colloids as template, by wet (HNA) or dry (XeF2) isotropic etching of silicon and by electrochemical etching of silicon. The shape and the roughness of the obtained cavities have been discussed and the pros/cons for each method are highlighted.

Design and characterization of ultra-stretchable monolithic silicon fabric

KAUST Repository

Rojas, Jhonathan Prieto

2014-10-13

Stretchable electronic systems can play instrumental role for reconfigurable macro-electronics such as distributed sensor networks for wearable and bio-integrated electronics. Typically, polymer composite based materials and its deterministic design as interconnects are used to achieve such systems. Nonetheless, non-polymeric inorganic silicon is the predominant material for 90% of electronics. Therefore, we report the design and fabrication of an all silicon based network of hexagonal islands connected through spiral springs to form an ultra-stretchable arrangement for complete compliance to highly asymmetric shapes. Several design parameters are considered and their validation is carried out through finite element analysis. The fabrication process is based on conventional microfabrication techniques and the measured stretchability is more than 1000% for single spirals and area expansions as high as 30 folds in arrays. The reported method can provide ultra-stretchable and adaptable electronic systems for distributed network of high-performance macro-electronics especially useful for wearable electronics and bio-integrated devices.

Design and characterization of ultra-stretchable monolithic silicon fabric

KAUST Repository

Rojas, Jhonathan Prieto; Carreno, Armando Arpys Arevalo; Foulds, I. G.; Hussain, Muhammad Mustafa

2014-01-01

Stretchable electronic systems can play instrumental role for reconfigurable macro-electronics such as distributed sensor networks for wearable and bio-integrated electronics. Typically, polymer composite based materials and its deterministic design as interconnects are used to achieve such systems. Nonetheless, non-polymeric inorganic silicon is the predominant material for 90% of electronics. Therefore, we report the design and fabrication of an all silicon based network of hexagonal islands connected through spiral springs to form an ultra-stretchable arrangement for complete compliance to highly asymmetric shapes. Several design parameters are considered and their validation is carried out through finite element analysis. The fabrication process is based on conventional microfabrication techniques and the measured stretchability is more than 1000% for single spirals and area expansions as high as 30 folds in arrays. The reported method can provide ultra-stretchable and adaptable electronic systems for distributed network of high-performance macro-electronics especially useful for wearable electronics and bio-integrated devices.

Strain-Induced Spin-Resonance Shifts in Silicon Devices

Science.gov (United States)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

Science.gov (United States)

Balpande, Suresh S.; Pande, Rajesh S.

2016-04-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Fabrication of 3D Silicon Sensors

Energy Technology Data Exchange (ETDEWEB)

Kok, A.; Hansen, T.E.; Hansen, T.A.; Lietaer, N.; Summanwar, A.; /SINTEF, Oslo; Kenney, C.; Hasi, J.; /SLAC; Da Via, C.; /Manchester U.; Parker, S.I.; /Hawaii U.

2012-06-06

Silicon sensors with a three-dimensional (3-D) architecture, in which the n and p electrodes penetrate through the entire substrate, have many advantages over planar silicon sensors including radiation hardness, fast time response, active edge and dual readout capabilities. The fabrication of 3D sensors is however rather complex. In recent years, there have been worldwide activities on 3D fabrication. SINTEF in collaboration with Stanford Nanofabrication Facility have successfully fabricated the original (single sided double column type) 3D detectors in two prototype runs and the third run is now on-going. This paper reports the status of this fabrication work and the resulted yield. The work of other groups such as the development of double sided 3D detectors is also briefly reported.

Flexible Thermoelectric Generators on Silicon Fabric

KAUST Repository

Sevilla, Galo T.

2012-01-01

In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart

Piezoresistive effect in top-down fabricated silicon nanowires

DEFF Research Database (Denmark)

Reck, Kasper; Richter, Jacob; Hansen, Ole

2008-01-01

We have designed and fabricated silicon test chips to investigate the piezoresistive properties of both crystalline and polycrystalline nanowires using a top-down approach, in order to comply with conventional fabrication techniques. The test chip consists of 5 silicon nanowires and a reference...

Integrated porous-silicon light-emitting diodes: A fabrication process using graded doping profiles

International Nuclear Information System (INIS)

Barillaro, G.; Diligenti, A.; Pieri, F.; Fuso, F.; Allegrini, M.

2001-01-01

A fabrication process, compatible with an industrial bipolar+complementary metal - oxide - semiconductor (MOS)+diffusion MOS technology, has been developed for the fabrication of efficient porous-silicon-based light-emitting diodes. The electrical contact is fabricated with a double n + /p doping, achieving a high current injection efficiency and thus lower biasing voltages. The anodization is performed as the last step of the process, thus reducing potential incompatibilities with industrial processes. The fabricated devices show yellow-orange electroluminescence, visible with the naked eye in room lighting. A spectral characterization of light emission is presented and briefly discussed. [copyright] 2001 American Institute of Physics

Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

NARCIS (Netherlands)

Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

2005-01-01

A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

Science.gov (United States)

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Athermal Photonic Devices and Circuits on a Silicon Platform

Science.gov (United States)

Raghunathan, Vivek

In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for

Customizable in situ TEM devices fabricated in freestanding membranes by focused ion beam milling

International Nuclear Information System (INIS)

Lei, Anders; Petersen, Dirch Hjorth; Booth, Timothy John; Homann, Lasse Vinther; Kallesoe, Christian; Sukas, Ozlem Sardan; Molhave, Kristian; Boggild, Peter; Gyrsting, Yvonne

2010-01-01

Nano- and microelectromechanical structures for in situ operation in a transmission electron microscope (TEM) were fabricated with a turnaround time of 20 min and a resolution better than 100 nm. The structures are defined by focused ion beam (FIB) milling in 135 nm thin membranes of single crystalline silicon extending over the edge of a pre-fabricated silicon microchip. Four-terminal resistance measurements of FIB-defined nanowires showed at least two orders of magnitude increase in resistivity compared to bulk. We show that the initial high resistance is due to amorphization of silicon, and that current annealing recrystallizes the structure, causing the electrical properties to partly recover to the pristine bulk resistivity. In situ imaging of the annealing process revealed both continuous and abrupt changes in the crystal structure, accompanied by instant changes of the electrical conductivity. The membrane structures provide a simple way to design electron-transparent nanodevices with high local temperature gradients within the field of view of the TEM, allowing detailed studies of surface diffusion processes. We show two examples of heat-induced coarsening of gold on a narrow freestanding bridge, where local temperature gradients are controlled via the electrical current paths. The separation of device processing into a one-time batch-level fabrication of identical, generic membrane templates, and subsequent device-specific customization by FIB milling, provides unparalleled freedom in device layout combined with very short effective fabrication time. This approach significantly speeds up prototyping of nanodevices such as resonators, actuators, sensors and scanning probes with state-of-art resolution.

Customizable in situ TEM devices fabricated in freestanding membranes by focused ion beam milling

Energy Technology Data Exchange (ETDEWEB)

Lei, Anders; Petersen, Dirch Hjorth; Booth, Timothy John; Homann, Lasse Vinther; Kallesoe, Christian; Sukas, Ozlem Sardan; Molhave, Kristian; Boggild, Peter [DTU Nanotech, Department of Nano- and Microtechnology, Technical University of Denmark, DK-2800 Kongens Lyngby (Denmark); Gyrsting, Yvonne, E-mail: Anders.Lei@nanotech.dtu.dk [DTU Danchip, National Center for Micro- and Nanofabrication, Technical University of Denmark, DK-2800 Kongens Lyngby (Denmark)

2010-10-08

Nano- and microelectromechanical structures for in situ operation in a transmission electron microscope (TEM) were fabricated with a turnaround time of 20 min and a resolution better than 100 nm. The structures are defined by focused ion beam (FIB) milling in 135 nm thin membranes of single crystalline silicon extending over the edge of a pre-fabricated silicon microchip. Four-terminal resistance measurements of FIB-defined nanowires showed at least two orders of magnitude increase in resistivity compared to bulk. We show that the initial high resistance is due to amorphization of silicon, and that current annealing recrystallizes the structure, causing the electrical properties to partly recover to the pristine bulk resistivity. In situ imaging of the annealing process revealed both continuous and abrupt changes in the crystal structure, accompanied by instant changes of the electrical conductivity. The membrane structures provide a simple way to design electron-transparent nanodevices with high local temperature gradients within the field of view of the TEM, allowing detailed studies of surface diffusion processes. We show two examples of heat-induced coarsening of gold on a narrow freestanding bridge, where local temperature gradients are controlled via the electrical current paths. The separation of device processing into a one-time batch-level fabrication of identical, generic membrane templates, and subsequent device-specific customization by FIB milling, provides unparalleled freedom in device layout combined with very short effective fabrication time. This approach significantly speeds up prototyping of nanodevices such as resonators, actuators, sensors and scanning probes with state-of-art resolution.

Neuron-inspired flexible memristive device on silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2017-06-18

Comprehensive understanding of the world\\'s most energy efficient powerful computer, the human brain, is an elusive scientific issue. Still, already gained knowledge indicates memristors can be used as a building block to model the brain. At the same time, brain cortex is folded allowing trillions of neurons to be integrated in a compact volume. Therefore, we report flexible aluminium oxide based memristive devices fabricated and then derived from widely used bulk mono-crystalline silicon (100). We use complementary metal oxide semiconductor based processes to layout the foundation for ultra large scale integration (ULSI) of such memory devices to advance the task of comprehending a physical model of human brain.

Fabrication of amorphous silicon nanoribbons by atomic force microscope tip-induced local oxidation for thin film device applications

International Nuclear Information System (INIS)

Pichon, L; Rogel, R; Demami, F

2010-01-01

We demonstrate the feasibility of induced local oxidation of amorphous silicon by atomic force microscopy. The resulting local oxide is used as a mask for the elaboration of a thin film silicon resistor. A thin amorphous silicon layer deposited on a glass substrate is locally oxidized following narrow continuous lines. The corresponding oxide line is then used as a mask during plasma etching of the amorphous layer leading to the formation of a nanoribbon. Such an amorphous silicon nanoribbon is used for the fabrication of the resistor

Comparison of silicon pin diode detector fabrication processes using ion implantation and thermal doping

International Nuclear Information System (INIS)

Zhou, C.Z.; Warburton, W.K.

1996-01-01

Two processes for the fabrication of silicon p-i-n diode radiation detectors are described and compared. Both processes are compatible with conventional integrated-circuit fabrication techniques and yield very low leakage currents. Devices made from the process using boron thermal doping have about a factor of 2 lower leakage current than those using boron ion implantation. However, the boron thermal doping process requires additional process steps to remove boron skins. (orig.)

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

Energy Technology Data Exchange (ETDEWEB)

Balpande, Suresh S., E-mail: balpandes@rknec.edu [Ph.D.. Scholar, Department of Electronics Engineering Shri Ramdeobaba College of Engineering & Management, Nagpur-13, (M.S.) (India); Pande, Rajesh S. [Professor, Department of Electronics Engineering Shri Ramdeobaba College of Engineering & Management, Nagpur-13, (M.S.) (India)

2016-04-13

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

International Nuclear Information System (INIS)

Balpande, Suresh S.; Pande, Rajesh S.

2016-01-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Silicon based light-emitting materials and devices

International Nuclear Information System (INIS)

Chen Weide

1999-01-01

Silicon based light-emitting materials and devices are the key to optoelectronic integration. Recently, there has been significant progress in materials engineering methods. The author reviews the latest developments in this area including erbium doped silicon, porous silicon, nanocrystalline silicon and Si/SiO 2 superlattice structures. The incorporation of these different materials into devices is described and future device prospects are assessed

Single-Event Effects in Silicon and Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

Electronic spectrum of a deterministic single-donor device in silicon

International Nuclear Information System (INIS)

Fuechsle, Martin; Miwa, Jill A.; Mahapatra, Suddhasatta; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.

2013-01-01

We report the fabrication of a single-electron transistor (SET) based on an individual phosphorus dopant that is deterministically positioned between the dopant-based electrodes of a transport device in silicon. Electronic characterization at mK-temperatures reveals a charging energy that is very similar to the value expected for isolated P donors in a bulk Si environment. Furthermore, we find indications for bulk-like one-electron excited states in the co-tunneling spectrum of the device, in sharp contrast to previous reports on transport through single dopants

Flexible high-κ/Metal gate metal/insulator/metal capacitors on silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-10-01

Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 {\\ m cm}2 and thickness: 25 \\\\mu{\\ m m}) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections. © 1963-2012 IEEE.

Fabrication of functional structures on thin silicon nitride membranes

NARCIS (Netherlands)

Ekkels, P.; Tjerkstra, R.W.; Krijnen, Gijsbertus J.M.; Berenschot, Johan W.; Brugger, J.P.; Elwenspoek, Michael Curt

A process to fabricate functional polysilicon structures above large (4×4 mm2) thin (200 nm), very flat LPCVD silicon rich nitride membranes was developed. Key features of this fabrication process are the use of low-stress LPCVD silicon nitride, sacrificial layer etching, and minimization of

David Adler Lectureship Award Talk: III-V Semiconductor Nanowires on Silicon for Future Devices

Science.gov (United States)

Riel, Heike

Bottom-up grown nanowires are very attractive materials for direct integration of III-V semiconductors on silicon thus opening up new possibilities for the design and fabrication of nanoscale devices for electronic, optoelectronic as well as quantum information applications. Template-Assisted Selective Epitaxy (TASE) allows the well-defined and monolithic integration of complex III-V nanostructures and devices on silicon. Achieving atomically abrupt heterointerfaces, high crystal quality and control of dimension down to 1D nanowires enabled the demonstration of FETs and tunnel devices based on In(Ga)As and GaSb. Furthermore, the strong influence of strain on nanowires as well as results on quantum transport studies of InAs nanowires with well-defined geometry will be presented.

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

Science.gov (United States)

Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih

2018-04-01

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-06-09

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect to breakdown voltage and leakage current of the devices. We also report the effect of continuous mechanical stress on the breakdown voltage over extended periods of times.

Conformal coating of amorphous silicon and germanium by high pressure chemical vapor deposition for photovoltaic fabrics

Science.gov (United States)

Ji, Xiaoyu; Cheng, Hiu Yan; Grede, Alex J.; Molina, Alex; Talreja, Disha; Mohney, Suzanne E.; Giebink, Noel C.; Badding, John V.; Gopalan, Venkatraman

2018-04-01

Conformally coating textured, high surface area substrates with high quality semiconductors is challenging. Here, we show that a high pressure chemical vapor deposition process can be employed to conformally coat the individual fibers of several types of flexible fabrics (cotton, carbon, steel) with electronically or optoelectronically active materials. The high pressure (˜30 MPa) significantly increases the deposition rate at low temperatures. As a result, it becomes possible to deposit technologically important hydrogenated amorphous silicon (a-Si:H) from silane by a simple and very practical pyrolysis process without the use of plasma, photochemical, hot-wire, or other forms of activation. By confining gas phase reactions in microscale reactors, we show that the formation of undesired particles is inhibited within the microscale spaces between the individual wires in the fabric structures. Such a conformal coating approach enables the direct fabrication of hydrogenated amorphous silicon-based Schottky junction devices on a stainless steel fabric functioning as a solar fabric.

Fabrication of porous silicon based tunable distributed Bragg reflectors by anodic etching of irradiated silicon

International Nuclear Information System (INIS)

Vendamani, V.S.; Dang, Z.Y.; Ramana, P.; Pathak, A.P.; Ravi Kanth Kumar, V.V.; Breese, M.B.H.; Nageswara Rao, S.V.S.

2015-01-01

Highlights: • Fabrication of tunable distributed Bragg reflectors (DBRs) by gamma/ion irradiation of Si and subsequent formation of porous silicon multilayers has been described. • The central wavelength and the width of the stop band are found to decrease with increase in irradiation fluence. • The Si samples irradiated with highest fluence of 2 × 10 13 ions/cm 2 (100 MeV Ag ions) and 60 kGy (gamma) showed a central reflection at λ = 476 nm and 544 nm respectively, in contrast to un-irradiated sample, where λ = 635 nm. • The observed changes in the central wavelengths are attributed to the density of defects generated by gamma and ion irradiation in c-Si. • This study is expected to provide useful information for fabricating tunable wave reflectors for optical communication and other device applications. - Abstract: We report a study on the fabrication of tunable distributed Bragg reflectors (DBRs) by gamma/ion irradiation of Si and subsequent formation of porous silicon multilayers. Porous Si multilayers with 50 bilayers were designed to achieve high intensity of reflection. The reflection spectra appear to have a broad continuous band between 400 and 800 nm with a distinct central wavelength corresponding to different wave reflectors. The central wavelength and the width of the stop band are found to decrease with increase in irradiation fluence. The Si samples irradiated with highest fluence of 2 × 10 13 ions/cm 2 (100 MeV Ag ions) and 60 kGy (gamma) showed a central reflection at λ = 476 nm and 544 nm respectively, in contrast to un-irradiated sample, where λ = 635 nm. The observed changes are attributed to the density of defects generated by gamma and ion irradiation in c-Si. These results suggest that the gamma irradiation is a convenient and alternative method to tune the central wavelength of reflection without creating high density of defects by high energy ion implantation. This study is expected to provide useful information for

Fabrication of integrated metallic MEMS devices

DEFF Research Database (Denmark)

Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

2002-01-01

A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators are characteri......A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

Directory of Open Access Journals (Sweden)

Kuen-Hsien Wu

2015-09-01

Full Text Available Porous-silicon (PS multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells.

Simple fabrication of closed-packed IR microlens arrays on silicon by femtosecond laser wet etching

Science.gov (United States)

Meng, Xiangwei; Chen, Feng; Yang, Qing; Bian, Hao; Du, Guangqing; Hou, Xun

2015-10-01

We demonstrate a simple route to fabricate closed-packed infrared (IR) silicon microlens arrays (MLAs) based on femtosecond laser irradiation assisted by wet etching method. The fabricated MLAs show high fill factor, smooth surface and good uniformity. They can be used as optical devices for IR applications. The exposure and etching parameters are optimized to obtain reproducible microlens with hexagonal and rectangular arrangements. The surface roughness of the concave MLAs is only 56 nm. This presented method is a maskless process and can flexibly change the size, shape and the fill factor of the MLAs by controlling the experimental parameters. The concave MLAs on silicon can work in IR region and can be used for IR sensors and imaging applications.

Electron beam fabrication of a microfluidic device for studying submicron-scale bacteria

Science.gov (United States)

2013-01-01

Background Controlled restriction of cellular movement using microfluidics allows one to study individual cells to gain insight into aspects of their physiology and behaviour. For example, the use of micron-sized growth channels that confine individual Escherichia coli has yielded novel insights into cell growth and death. To extend this approach to other species of bacteria, many of whom have dimensions in the sub-micron range, or to a larger range of growth conditions, a readily-fabricated device containing sub-micron features is required. Results Here we detail the fabrication of a versatile device with growth channels whose widths range from 0.3 μm to 0.8 μm. The device is fabricated using electron beam lithography, which provides excellent control over the shape and size of different growth channels and facilitates the rapid-prototyping of new designs. Features are successfully transferred first into silicon, and subsequently into the polydimethylsiloxane that forms the basis of the working microfluidic device. We demonstrate that the growth of sub-micron scale bacteria such as Lactococcus lactis or Escherichia coli cultured in minimal medium can be followed in such a device over several generations. Conclusions We have presented a detailed protocol based on electron beam fabrication together with specific dry etching procedures for the fabrication of a microfluidic device suited to study submicron-sized bacteria. We have demonstrated that both Gram-positive and Gram-negative bacteria can be successfully loaded and imaged over a number of generations in this device. Similar devices could potentially be used to study other submicron-sized organisms under conditions in which the height and shape of the growth channels are crucial to the experimental design. PMID:23575419

Fabrication and characterization of active nanostructures

Science.gov (United States)

Opondo, Noah F.

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface. A micro-vacuum electron device based on silicon field emitters for cold cathode emission is also presented. The presented work utilizes vertical Si nanowires fabricated by means of self-assembly, standard lithography and etching techniques as field emitters in this dissertation. To obtain a high nanowire density, hence a high current density, a simple and inexpensive Langmuir Blodgett technique

Fabrication and characterization of porous silicon for photonic applications

Directory of Open Access Journals (Sweden)

Arvin I. Mabilangan

2013-06-01

Full Text Available Porous silicon (PSi thin films from p-type silicon (100 substrates were fabricated using a simple table top electrochemical etching setup with a 1:1 HF:EtOh electrolyte solution. Porous silicon f ilms with different morphologies and optical properties were achieved by varying the etching parameters, such as HF concentration, etching time andanodization current. It was observed that the f ilm thickness of the fabricated PSi increased with etch time and HF concentration. The etch rate increased with the applied anodization current. Reflection spectroscopy at normal incidence was used to determine the refractive indices of the fabricated f ilms. Using the Sellmeier equation, the chromatic dispersion of the f ilms was obtained for different HF concentrations and anodization currents.

White-light emission from porous-silicon-aluminium Schottky junctions

International Nuclear Information System (INIS)

Masini, G.; La Monica, S.; Maiello, G.

1996-01-01

Porous-silicon-based white-light-emitting devices are presented. The fabrication process on different substrates is described. The peculiarities of technological steps for device fabrication (porous-silicon formation and aluminium treatment) are underlined. Doping profile of the porous layer, current-voltage characteristics, time response, lifetime tests and electroluminescence emission spectrum of the device are presented. A model for electrical behaviour of Al/porous silicon Schottky junction is presented. Electroluminescence spectrum of the presented devices showed strong similarities with white emission from crystalline silicon junctions in the breakdown region

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

Science.gov (United States)

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Fabrication of Ge nanocrystals doped silica-on-silicon waveguides and observation of their strong quantum confinement effect

DEFF Research Database (Denmark)

Ou, Haiyan; Rottwitt, Karsten

2009-01-01

Germanium (Ge) nanocrystals embedded in silica matrix is an interesting material for new optoelectronic devices. In this paper, standard silica-on-silicon waveguides with a core doped by Ge nanocrystals were fabricated using plasma enhanced chemical vapour deposition and reactive ion etching...

Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

NARCIS (Netherlands)

Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

2008-01-01

The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

Silicon solid state devices and radiation detection

CERN Document Server

Leroy, Claude

2012-01-01

This book addresses the fundamental principles of interaction between radiation and matter, the principles of working and the operation of particle detectors based on silicon solid state devices. It covers a broad scope with respect to the fields of application of radiation detectors based on silicon solid state devices from low to high energy physics experiments including in outer space and in the medical environment. This book covers stateof- the-art detection techniques in the use of radiation detectors based on silicon solid state devices and their readout electronics, including the latest developments on pixelated silicon radiation detector and their application.

Dual-side and three-dimensional microelectrode arrays fabricated from ultra-thin silicon substrates

International Nuclear Information System (INIS)

Du, Jiangang; Masmanidis, Sotiris C; Roukes, Michael L

2009-01-01

A method for fabricating planar implantable microelectrode arrays was demonstrated using a process that relied on ultra-thin silicon substrates, which ranged in thickness from 25 to 50 µm. The challenge of handling these fragile materials was met via a temporary substrate support mechanism. In order to compensate for putative electrical shielding of extracellular neuronal fields, separately addressable electrode arrays were defined on each side of the silicon device. Deep reactive ion etching was employed to create sharp implantable shafts with lengths of up to 5 mm. The devices were flip-chip bonded onto printed circuit boards (PCBs) by means of an anisotropic conductive adhesive film. This scalable assembly technique enabled three-dimensional (3D) integration through formation of stacks of multiple silicon and PCB layers. Simulations and measurements of microelectrode noise appear to suggest that low impedance surfaces, which could be formed by electrodeposition of gold or other materials, are required to ensure an optimal signal-to-noise ratio as well a low level of interchannel crosstalk

Optimized optical devices for edge-coupling-enabled silicon photonics platform

Science.gov (United States)

Png, Ching Eng; Ang, Thomas Y. L.; Ong, Jun Rong; Lim, Soon Thor; Sahin, Ezgi; Chen, G. F. R.; Tan, D. T. H.; Guo, Tina X.; Wang, Hong

2018-02-01

We present a library of high-performance passive and active silicon photonic devices at the C-band that is specifically designed and optimized for edge-coupling-enabled silicon photonics platform. These devices meet the broadband (100 nm), low-loss (= 25 Gb/s), and polarization diversity requirements (TE and TM polarization extinction ratio beam splitters (PBSs), and high-speed modulators are some of the devices within our library. In particular, we have designed and fabricated inverse taper fiber-to-waveguide edge couplers of tip widths ranging from 120 nm to 200 nm, and we obtained a low coupling loss of 1.80+/-0.28 dB for 160 nm tip width. To achieve polarization diversity operation for inverse tapers, we have experimentally realized different designs of polarization beam splitters (PBS). Our optimized PBS has a measured extinction ratio of <= 25 dB for both the quasiTE modes, and quasi-TM modes. Additionally, a broadband (100 nm) directional coupler with a 50/50 power splitting ratio was experimentally realized on a small footprint of 20×3 μm2 . Last but not least, high-speed silicon modulators with a range of carrier doping concentrations and offset of the PN junction can be used to optimise the modulation efficiency, and insertion losses for operation at 25 GHz.

Dopant atoms as quantum components in silicon nanoscale devices

Science.gov (United States)

Zhao, Xiaosong; Han, Weihua; Wang, Hao; Ma, Liuhong; Li, Xiaoming; Zhang, Wang; Yan, Wei; Yang, Fuhua

2018-06-01

Recent progress in nanoscale fabrication allows many fundamental studies of the few dopant atoms in various semiconductor nanostructures. Since the size of nanoscale devices has touched the limit of the nature, a single dopant atom may dominate the performance of the device. Besides, the quantum computing considered as a future choice beyond Moore's law also utilizes dopant atoms as functional units. Therefore, the dopant atoms will play a significant role in the future novel nanoscale devices. This review focuses on the study of few dopant atoms as quantum components in silicon nanoscale device. The control of the number of dopant atoms and unique quantum transport characteristics induced by dopant atoms are presented. It can be predicted that the development of nanoelectronics based on dopant atoms will pave the way for new possibilities in quantum electronics. Project supported by National Key R&D Program of China (No. 2016YFA0200503).

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2014-12-01

Today\\'s mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Kutbee, Arwa T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Today's mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

Fabrication of the GLAST Silicon Tracker Readout Electronics

Energy Technology Data Exchange (ETDEWEB)

Baldini, Luca; Brez, Alessandro; Himel, Thomas; Johnson, R.P.; Latronico, Luca; Minuti, Massimo; Nelson, David; Sadrozinski, H.F.-W.; Sgro, Carmelo; Spandre, Gloria; Sugizaki, Mutsumi; Tajima, Hiro; Cohen Tanugi, Johann; Young, Charles; Ziegler, Marcus; /Pisa U. /INFN, Pisa /SLAC /UC, Santa Cruz

2006-03-03

A unique electronics system has been built and tested for reading signals from the silicon-strip detectors of the Gamma-ray Large Area Space Telescope mission. The system amplifies and processes signals from 884,736 36-cm long silicon strips in a 4 x 4 array of tower modules. An aggressive mechanical design fits the readout electronics in narrow spaces between the tower modules, to minimize dead area. This design and the resulting departures from conventional electronics packaging led to several fabrication challenges and lessons learned. This paper describes the fabrication processes and how the problems peculiar to this design were overcome.

Advanced Silicone-based Coatings for Flexible Fabric Applications, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — High performance silicone coatings are desired for flexible fabrics used in several space and consumer applications. For instance, the total weight of silicone...

Nanowire-integrated microporous silicon membrane for continuous fluid transport in micro cooling device

International Nuclear Information System (INIS)

So, Hongyun; Pisano, Albert P.; Cheng, Jim C.

2013-01-01

We report an efficient passive micro pump system combining the physical properties of nanowires and micropores. This nanowire-integrated microporous silicon membrane was created to feed coolant continuously onto the surface of the wick in a micro cooling device to ensure it remains hydrated and in case of dryout, allow for regeneration of the system. The membrane was fabricated by photoelectrochemical etching to form micropores followed by hydrothermal growth of nanowires. This study shows a promising approach to address thermal management challenges for next generation electronic devices with absence of external power

Silicon-based photonic crystals fabricated using proton beam writing combined with electrochemical etching method.

Science.gov (United States)

Dang, Zhiya; Breese, Mark Bh; Recio-Sánchez, Gonzalo; Azimi, Sara; Song, Jiao; Liang, Haidong; Banas, Agnieszka; Torres-Costa, Vicente; Martín-Palma, Raúl José

2012-07-23

A method for fabrication of three-dimensional (3D) silicon nanostructures based on selective formation of porous silicon using ion beam irradiation of bulk p-type silicon followed by electrochemical etching is shown. It opens a route towards the fabrication of two-dimensional (2D) and 3D silicon-based photonic crystals with high flexibility and industrial compatibility. In this work, we present the fabrication of 2D photonic lattice and photonic slab structures and propose a process for the fabrication of 3D woodpile photonic crystals based on this approach. Simulated results of photonic band structures for the fabricated 2D photonic crystals show the presence of TE or TM gap in mid-infrared range.

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

Science.gov (United States)

Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

2015-11-19

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

2007-07-25

A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

Nanoscale phosphorus atom arrays created using STM for the fabrication of a silicon based quantum computer.

Energy Technology Data Exchange (ETDEWEB)

O' Brien, J. L. (Jeremy L.); Schofield, S. R. (Steven R.); Simmons, M. Y. (Michelle Y.); Clark, R. G. (Robert G.); Dzurak, A. S. (Andrew S.); Curson, N. J. (Neil J.); Kane, B. E. (Bruce E.); McAlpine, N. S. (Neal S.); Hawley, M. E. (Marilyn E.); Brown, G. W. (Geoffrey W.)

2001-01-01

Quantum computers offer the promise of formidable computational power for certain tasks. Of the various possible physical implementations of such a device, silicon based architectures are attractive for their scalability and ease of integration with existing silicon technology. These designs use either the electron or nuclear spin state of single donor atoms to store quantum information. Here we describe a strategy to fabricate an array of single phosphorus atoms in silicon for the construction of such a silicon based quantum computer. We demonstrate the controlled placement of single phosphorus bearing molecules on a silicon surface. This has been achieved by patterning a hydrogen mono-layer 'resist' with a scanning tunneling microscope (STM) tip and exposing the patterned surface to phosphine (PH3) molecules. We also describe preliminary studies into a process to incorporate these surface phosphorus atoms into the silicon crystal at the array sites. Keywords: Quantum computing, nanotechriology scanning turincling microscopy, hydrogen lithography

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

Science.gov (United States)

Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Chattopadhyay, Goutam (Inventor); Perez, Jose Vicente Siles (Inventor); Lin, Robert H. (Inventor); Mehdi, Imran (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

International Nuclear Information System (INIS)

Strobel, Sebastian; Hernandez, Rocio Murcia; Hansen, Allan G; Tornow, Marc

2008-01-01

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10 -18 farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian; Hernandez, Rocio Murcia [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall 3, 85748 Garching (Germany); Hansen, Allan G; Tornow, Marc [Institut fuer Halbleitertechnik, Technische Universitaet Braunschweig, Hans-Sommer-Strasse 66, 38106 Braunschweig (Germany)], E-mail: m.tornow@tu-bs.de

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10{sup -18} farad and asymmetric resistances of 30 and 300 M{omega}, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

Science.gov (United States)

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Mass production compatible fabrication techniques of single-crystalline silver metamaterials and plasmonics devices

Science.gov (United States)

Rodionov, Ilya A.; Baburin, Alexander S.; Zverev, Alexander V.; Philippov, Ivan A.; Gabidulin, Aidar R.; Dobronosova, Alina A.; Ryzhova, Elena V.; Vinogradov, Alexey P.; Ivanov, Anton I.; Maklakov, Sergey S.; Baryshev, Alexander V.; Trofimov, Igor V.; Merzlikin, Alexander M.; Orlikovsky, Nikolay A.; Rizhikov, Ilya A.

2017-08-01

During last 20 years, great results in metamaterials and plasmonic nanostructures fabrication were obtained. However, large ohmic losses in metals and mass production compatibility still represent the most serious challenge that obstruct progress in the fields of metamaterials and plasmonics. Many recent research are primarily focused on developing low-loss alternative materials, such as nitrides, II-VI semiconductor oxides, high-doped semiconductors, or two-dimensional materials. In this work, we demonstrate that our perfectly fabricated silver films can be an effective low-loss material system, as theoretically well-known. We present a fabrication technology of plasmonic and metamaterial nanodevices on transparent (quartz, mica) and non-transparent (silicon) substrates by means of e-beam lithography and ICP dry etch instead of a commonly-used focused ion beam (FIB) technology. We eliminate negative influence of litho-etch steps on silver films quality and fabricate square millimeter area devices with different topologies and perfect sub-100 nm dimensions reproducibility. Our silver non-damage fabrication scheme is tested on trial manufacture of spasers, plasmonic sensors and waveguides, metasurfaces, etc. These results can be used as a flexible device manufacture platform for a broad range of practical applications in optoelectronics, communications, photovoltaics and biotechnology.

Improving Mechanical Properties of Molded Silicone Rubber for Soft Robotics Through Fabric Compositing.

Science.gov (United States)

Wang, Yue; Gregory, Cherry; Minor, Mark A

2018-06-01

Molded silicone rubbers are common in manufacturing of soft robotic parts, but they are often prone to tears, punctures, and tensile failures when strained. In this article, we present a fabric compositing method for improving the mechanical properties of soft robotic parts by creating a fabric/rubber composite that increases the strength and durability of the molded rubber. Comprehensive ASTM material tests evaluating the strength, tear resistance, and puncture resistance are conducted on multiple composites embedded with different fabrics, including polyester, nylon, silk, cotton, rayon, and several blended fabrics. Results show that strong fabrics increase the strength and durability of the composite, valuable in pneumatic soft robotic applications, while elastic fabrics maintain elasticity and enhance tear strength, suitable for robotic skins or soft strain sensors. Two case studies then validate the proposed benefits of the fabric compositing for soft robotic pressure vessel applications and soft strain sensor applications. Evaluations of the fabric/rubber composite samples and devices indicate that such methods are effective for improving mechanical properties of soft robotic parts, resulting in parts that can have customized stiffness, strength, and vastly improved durability.

From silicon to organic nanoparticle memory devices.

Science.gov (United States)

Tsoukalas, D

2009-10-28

After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

Solvent Bonding for Fabrication of PMMA and COP Microfluidic Devices.

Science.gov (United States)

Wan, Alwin M D; Moore, Thomas A; Young, Edmond W K

2017-01-17

Thermoplastic microfluidic devices offer many advantages over those made from silicone elastomers, but bonding procedures must be developed for each thermoplastic of interest. Solvent bonding is a simple and versatile method that can be used to fabricate devices from a variety of plastics. An appropriate solvent is added between two device layers to be bonded, and heat and pressure are applied to the device to facilitate the bonding. By using an appropriate combination of solvent, plastic, heat, and pressure, the device can be sealed with a high quality bond, characterized as having high bond coverage, bond strength, optical clarity, durability over time, and low deformation or damage to microfeature geometry. We describe the procedure for bonding devices made from two popular thermoplastics, poly(methyl-methacrylate) (PMMA), and cyclo-olefin polymer (COP), as well as a variety of methods to characterize the quality of the resulting bonds, and strategies to troubleshoot low quality bonds. These methods can be used to develop new solvent bonding protocols for other plastic-solvent systems.

Luneburg lens in silicon photonics.

Science.gov (United States)

Di Falco, Andrea; Kehr, Susanne C; Leonhardt, Ulf

2011-03-14

The Luneburg lens is an aberration-free lens that focuses light from all directions equally well. We fabricated and tested a Luneburg lens in silicon photonics. Such fully-integrated lenses may become the building blocks of compact Fourier optics on chips. Furthermore, our fabrication technique is sufficiently versatile for making perfect imaging devices on silicon platforms.

Silicon Web Process Development. [for solar cell fabrication

Science.gov (United States)

Duncan, C. S.; Seidensticker, R. G.; Hopkins, R. H.; Mchugh, J. P.; Hill, F. E.; Heimlich, M. E.; Driggers, J. M.

1979-01-01

Silicon dendritic web, ribbon form of silicon and capable of fabrication into solar cells with greater than 15% AMl conversion efficiency, was produced from the melt without die shaping. Improvements were made both in the width of the web ribbons grown and in the techniques to replenish the liquid silicon as it is transformed to web. Through means of improved thermal shielding stress was reduced sufficiently so that web crystals nearly 4.5 cm wide were grown. The development of two subsystems, a silicon feeder and a melt level sensor, necessary to achieve an operational melt replenishment system, is described. A gas flow management technique is discussed and a laser reflection method to sense and control the melt level as silicon is replenished is examined.

A fabrication guide for planar silicon quantum dot heterostructures

Science.gov (United States)

Spruijtenburg, Paul C.; Amitonov, Sergey V.; van der Wiel, Wilfred G.; Zwanenburg, Floris A.

2018-04-01

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

Strained Silicon Photonics

Directory of Open Access Journals (Sweden)

Ralf B. Wehrspohn

2012-05-01

Full Text Available A review of recent progress in the field of strained silicon photonics is presented. The application of strain to waveguide and photonic crystal structures can be used to alter the linear and nonlinear optical properties of these devices. Here, methods for the fabrication of strained devices are summarized and recent examples of linear and nonlinear optical devices are discussed. Furthermore, the relation between strain and the enhancement of the second order nonlinear susceptibility is investigated, which may enable the construction of optically active photonic devices made of silicon.

Fabrication and Analysis of Tapered Tip Silicon Microneedles for MEMS based Drug Delivery System

Directory of Open Access Journals (Sweden)

Muhammad Waseem Ashraf

2010-11-01

Full Text Available In this paper, a novel design of transdermal drug delivery (TDD system is presented. The proposed system consists of controlled electronic circuit and microelectromechanical system (MEMS based devices like microneedles, micropump, flow sensor, and blood pressure sensor. The aim of this project is to develop a system that can eliminate the limitations associated with oral therapy. In this phase tapered tip silicon microneedles have been fabricated using inductively coupled plasma (ICP etching technology. Using ANSYS, simulation of microneedles has been conducted before the fabrication process to test the design suitability for TDD. More over multifield analysis of reservoir integrated with microneedle array using piezoelectric actuator has also been performed. The effects of frequency and voltage on actuator and fluid flow rate through 6×6 microneedle array have been investigated. This work provides envisage data to design suitable devices for TDD.

Silicon light-emitting diodes and lasers photon breeding devices using dressed photons

CERN Document Server

Ohtsu, Motoichi

2016-01-01

This book focuses on a novel phenomenon named photon breeding. It is applied to realizing light-emitting diodes and lasers made of indirect-transition-type silicon bulk crystals in which the light-emission principle is based on dressed photons. After presenting physical pictures of dressed photons and dressed-photon phonons, the principle of light emission by using dressed-photon phonons is reviewed. A novel phenomenon named photon breeding is also reviewed. Next, the fabrication and operation of light emitting diodes and lasers are described The role of coherent phonons in these devices is discussed. Finally, light-emitting diodes using other relevant crystals are described and other relevant devices are also reviewed.

Fabrication and Characterization of Nanopillars for Silicon-Based Thermoelectrics

Science.gov (United States)

Stranz, A.; Sökmen, Ü.; Wehmann, H.-H.; Waag, A.; Peiner, E.

2010-09-01

Si-based nanopillars of various sizes were fabricated by lateral structuring using anisotropic etching and thermal oxidation. We obtained pillars of diameter <500 nm, about 25 μm in height, with an aspect ratio of more than 50. The distance between pillars was varied from 500 nm to 10 μm. Besides the fabrication and structural characterization of silicon nanopillars, implementation of adequate metrology for measuring single pillars is described. Commercial tungsten probes, self-made gold probes, and piezoresistive silicon cantilever probes were used for measurements of nanopillars in a scanning electron microscope (SEM) equipped with nanomanipulators.

Fabrication and evaluation of series-triple quantum dots by thermal oxidation of silicon nanowire

International Nuclear Information System (INIS)

Uchida, Takafumi; Jo, Mingyu; Tsurumaki-Fukuchi, Atsushi; Arita, Masashi; Takahashi, Yasuo; Fujiwara, Akira

2015-01-01

Series-connected triple quantum dots were fabricated by a simple two-step oxidation technique using the pattern-dependent oxidation of a silicon nanowire and an additional oxidation of the nanowire through the gap of the fine gates attached to the nanowire. The characteristics of multi-dot single-electron devices are obtained. The formation of each quantum dot beneath an attached gate is confirmed by analyzing the electrical characteristics and by evaluating the gate capacitances between all pairings of gates and quantum dots. Because the gate electrode is automatically attached to each dot, the device structure benefits from scalability. This technique promises integrability of multiple quantum dots with individual control gates

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

Science.gov (United States)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Fabrication of High-Frequency pMUT Arrays on Silicon Substrates

DEFF Research Database (Denmark)

Pedersen, Thomas; Zawada, Tomasz; Hansen, Karsten

2010-01-01

A novel technique based on silicon micromachining for fabrication of linear arrays of high-frequency piezoelectric micromachined ultrasound transducers (pMUT) is presented. Piezoelectric elements are formed by deposition of lead zirconia titanate into etched features of a silicon substrate...

All-solid-state supercapacitors on silicon using graphene from silicon carbide

Energy Technology Data Exchange (ETDEWEB)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au [Environmental Futures Research Institute, Griffith University, Nathan 4111 (Australia); Wood, Barry [Centre for Microscopy and Microanalysis, The University of Queensland, St. Lucia 4072 (Australia)

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

International Nuclear Information System (INIS)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca; Wood, Barry

2016-01-01

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm"−"2 with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

Single-Event Effects in Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Flow-through polymerase chain reaction inside a seamless 3D helical microreactor fabricated utilizing a silicone tube and a paraffin mold.

Science.gov (United States)

Wu, Wenming; Trinh, Kieu The Loan; Lee, Nae Yoon

2015-03-07

We introduce a new strategy for fabricating a seamless three-dimensional (3D) helical microreactor utilizing a silicone tube and a paraffin mold. With this method, various shapes and sizes of 3D helical microreactors were fabricated, and a complicated and laborious photolithographic process, or 3D printing, was eliminated. With dramatically enhanced portability at a significantly reduced fabrication cost, such a device can be considered to be the simplest microreactor, developed to date, for performing the flow-through polymerase chain reaction (PCR).

Fabrication of silicon molds for polymer optics

DEFF Research Database (Denmark)

Nilsson, Daniel; Jensen, Søren; Menon, Aric Kumaran

2003-01-01

A silicon mold used for structuring polymer microcavities for optical applications is fabricated, using a combination of DRIE (deep reactive ion etching) and anisotropic chemical wet etching with KOH + IPA. For polymer optical microcavities, low surface roughness and vertical sidewalls are often ...... and KOH + IPA etch have been optimized. To reduce stiction between the silicon mold and the polymers used for molding, the mold is coated with a teflon-like material using the DRIE system. Released polymer microstructures characterized with AFM and SEM are also presented....

Magneto-optical non-reciprocal devices in silicon photonics

Directory of Open Access Journals (Sweden)

Yuya Shoji

2014-01-01

Full Text Available Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm.

A Mechanochemical Approach to Porous Silicon Nanoparticles Fabrication

Directory of Open Access Journals (Sweden)

Luca De Stefano

2011-06-01

Full Text Available Porous silicon samples have been reduced in nanometric particles by a well known industrial mechanical process, the ball grinding in a planetary mill; the process has been extended to crystalline silicon for comparison purposes. The silicon nanoparticles have been studied by X-ray diffraction, infrared spectroscopy, gas porosimetry and transmission electron microscopy. We have estimated crystallites size from about 50 nm for silicon to 12 nm for porous silicon. The specific surface area of the powders analyzed ranges between 100 m2/g to 29 m2/g depending on the milling time, ranging from 1 to 20 h. Electron microscopy confirms the nanometric size of the particles and reveals a porous structure in the powders obtained by porous silicon samples which has been preserved by the fabrication conditions. Chemical functionalization during the milling process by a siloxane compound has also been demonstrated.

Fabrication and Doping Methods for Silicon Nano- and Micropillar Arrays for Solar-Cell Applications: A Review.

Science.gov (United States)

Elbersen, Rick; Vijselaar, Wouter; Tiggelaar, Roald M; Gardeniers, Han; Huskens, Jurriaan

2015-11-18

Silicon is one of the main components of commercial solar cells and is used in many other solar-light-harvesting devices. The overall efficiency of these devices can be increased by the use of structured surfaces that contain nanometer- to micrometer-sized pillars with radial p/n junctions. High densities of such structures greatly enhance the light-absorbing properties of the device, whereas the 3D p/n junction geometry shortens the diffusion length of minority carriers and diminishes recombination. Due to the vast silicon nano- and microfabrication toolbox that exists nowadays, many versatile methods for the preparation of such highly structured samples are available. Furthermore, the formation of p/n junctions on structured surfaces is possible by a variety of doping techniques, in large part transferred from microelectronic circuit technology. The right choice of doping method, to achieve good control of junction depth and doping level, can contribute to an improvement of the overall efficiency that can be obtained in devices for energy applications. A review of the state-of-the-art of the fabrication and doping of silicon micro and nanopillars is presented here, as well as of the analysis of the properties and geometry of thus-formed 3D-structured p/n junctions. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

RFID and Memory Devices Fabricated Integrally on Substrates

Science.gov (United States)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

Science.gov (United States)

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

Additive advantage in characteristics of MIMCAPs on flexible silicon (100) fabric with release-first process

KAUST Repository

Ghoneim, Mohamed T.

2013-11-20

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show that our approach to transform bulk silicon (100) into a flexible fabric adds an inherent advantage of enabling higher integration density dynamic random access memory (DRAM) on the same chip area. Our approach is to release an ultra-thin silicon (100) fabric (25 μm thick) from the bulk silicon wafer, then build MIMCAPs using sputtered aluminium electrodes and successive atomic layer depositions (ALD) without break-ing the vacuum of a high-κ aluminium oxide sandwiched between two tantalum nitride layers. This result shows that we can obtain flexible electronics on silicon without sacrificing the high density integration aspects and also utilize the non-planar geometry associated with fabrication process to obtain a higher integration density compared to bulk silicon integration due to an increased normalized capacitance per unit planar area. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Surface wave photonic device based on porous silicon multilayers

International Nuclear Information System (INIS)

Guillermain, E.; Lysenko, V.; Benyattou, T.

2006-01-01

Porous silicon is widely studied in the field of photonics due to its interesting optical properties. In this work, we present theoretical and first experimental studies of a new kind of porous silicon photonic device based on optical surface wave. A theoretical analysis of the device is presented using plane-wave approximation. The porous silicon multilayered structures are realized using electrochemical etching of p + -type silicon. Morphological and optical characterizations of the realized structures are reported

Space and military radiation effects in silicon-on-insulator devices

International Nuclear Information System (INIS)

Schwank, J.R.

1996-09-01

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Science.gov (United States)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Silicon spintronics with ferromagnetic tunnel devices

International Nuclear Information System (INIS)

Jansen, R; Sharma, S; Dash, S P; Min, B C

2012-01-01

In silicon spintronics, the unique qualities of ferromagnetic materials are combined with those of silicon, aiming at creating an alternative, energy-efficient information technology in which digital data are represented by the orientation of the electron spin. Here we review the cornerstones of silicon spintronics, namely the creation, detection and manipulation of spin polarization in silicon. Ferromagnetic tunnel contacts are the key elements and provide a robust and viable approach to induce and probe spins in silicon, at room temperature. We describe the basic physics of spin tunneling into silicon, the spin-transport devices, the materials aspects and engineering of the magnetic tunnel contacts, and discuss important quantities such as the magnitude of the spin accumulation and the spin lifetime in the silicon. We highlight key experimental achievements and recent progress in the development of a spin-based information technology. (topical review)

SILICON COMPATIBLE ACOUSTIC WAVE RESONATORS: DESIGN, FABRICATION AND PERFORMANCE

Directory of Open Access Journals (Sweden)

Aliza Aini Md Ralib

2014-12-01

Full Text Available ABSTRACT: Continuous advancement in wireless technology and silicon microfabrication has fueled exciting growth in wireless products. The bulky size of discrete vibrating mechanical devices such as quartz crystals and surface acoustic wave resonators impedes the ultimate miniaturization of single-chip transceivers. Fabrication of acoustic wave resonators on silicon allows complete integration of a resonator with its accompanying circuitry.  Integration leads to enhanced performance, better functionality with reduced cost at large volume production. This paper compiles the state-of-the-art technology of silicon compatible acoustic resonators, which can be integrated with interface circuitry. Typical acoustic wave resonators are surface acoustic wave (SAW and bulk acoustic wave (BAW resonators.  Performance of the resonator is measured in terms of quality factor, resonance frequency and insertion loss. Selection of appropriate piezoelectric material is significant to ensure sufficient electromechanical coupling coefficient is produced to reduce the insertion loss. The insulating passive SiO2 layer acts as a low loss material and aims to increase the quality factor and temperature stability of the design. The integration technique also is influenced by the fabrication process and packaging.  Packageless structure using AlN as the additional isolation layer is proposed to protect the SAW device from the environment for high reliability. Advancement in miniaturization technology of silicon compatible acoustic wave resonators to realize a single chip transceiver system is still needed. ABSTRAK: Kemajuan yang berterusan dalam teknologi tanpa wayar dan silikon telah menguatkan pertumbuhan yang menarik dalam produk tanpa wayar. Saiz yang besar bagi peralatan mekanikal bergetar seperti kristal kuarza menghalang pengecilan untuk merealisasikan peranti cip. Silikon serasi  gelombang akustik resonator mempunyai potensi yang besar untuk menggantikan unsur

Flexible Bragg reflection waveguide devices fabricated on a plastic substrate

Science.gov (United States)

Kim, Kyung-Jo; Yi, Jeong-Ah; Oh, Min-Cheol; Noh, Young-Ouk; Lee, Hyung-Jong

2007-09-01

Bragg reflecting waveguide devices are fabricated on a flexible substrate by using a post lift-off process in order to provide highly uniform grating patterns on a wide range. In this process, the flexible substrate spin-coated on silicon wafer is released after the final fabrication process of chip dicing. The fabricated flexible Bragg reflector shows very sharp transmission spectrum with 3-dB bandwidth of 0.1 nm and 10-dB bandwidth of 0.4 nm, which proves the Bragg reflector has excellent uniformity. To achieve athermal operation of the flexible Bragg reflector, thermal expansion property of the plastic substrate is controlled by the thickness of two polymer materials constructing the plastic substrate. The flexible substrate with 0.7-μm SU-8 layers sandwiching 100-μm NOA61 layer provides an optimized thermal expansion property to compensate the thermo-optic effect of the waveguide made of ZPU polymer. The temperature dependence of the Bragg reflector is decreased to -0.011 nm/°C through the incorporation of the plastic substrate.

Semiconductors and semimetals oxygen in silicon

CERN Document Server

Willardson, Robert K; Beer, Albert C; Shimura, Fumio

1994-01-01

This volume reviews the latest understanding of the behavior and roles of oxygen in silicon, which will carry the field into the ULSI era from the experimental and theoretical points of view. The fourteen chapters, written by recognized authorities representing industrial and academic institutions, cover thoroughly the oxygen related phenomena from the crystal growth to device fabrication processes, as well as indispensable diagnostic techniques for oxygen.Key Features* Comprehensive study of the behavior of oxygen in silicon* Discusses silicon crystals for VLSI and ULSI applications* Thorough coverage from crystal growth to device fabrication* Edited by technical experts in the field* Written by recognized authorities from industrial and academic institutions* Useful to graduate students, scientists in other disciplines, and active participants in the arena of silicon-based microelectronics research* 297 original line drawings

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

International Nuclear Information System (INIS)

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

2014-01-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

Fabrication and Modification of Nanoporous Silicon Particles

Science.gov (United States)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

Fabrication of silicon based glass fibres for optical communication

Indian Academy of Sciences (India)

Silicon based glass fibres are fabricated by conventional fibre drawing process. First, preform fabrication is carried out by means of conventional MCVD technique by using various dopants such as SiCl4, GeCl4, POCl3, and FeCl3. The chemicals are used in such a way that step index single mode fibre can be drawn.

Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

International Nuclear Information System (INIS)

Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

2006-01-01

Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

Epitaxy - a new technology for fabrication of advanced silicon radiation detectors

International Nuclear Information System (INIS)

Kemmer, J.; Wiest, F.; Pahlke, A.; Boslau, O.; Goldstrass, P.; Eggert, T.; Schindler, M.; Eisele, I.

2005-01-01

Twenty five years after the introduction of the planar process to the fabrication of silicon radiation detectors a new technology, which replaces the ion implantation doping by silicon epitaxy is presented. The power of this new technique is demonstrated by fabrication of silicon drift detectors (SDDs), whereby both the n-type and p-type implants are replaced by n-type and p-type epi-layers. The very first SDDs ever produced with this technique show energy resolutions of 150 eV for 55 Fe at -35 deg C. The area of the detectors is 10 mm 2 and the thickness 300 μm. The high potential of epitaxy for future detectors with integrated complex electronics is described

Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

Energy Technology Data Exchange (ETDEWEB)

Kumar, A.; Ravi, K. V.

2011-06-01

In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

Thin film silicon by a microwave plasma deposition technique: Growth and devices, and, interface effects in amorphous silicon/crystalline silicon solar cells

Science.gov (United States)

Jagannathan, Basanth

Thin film silicon (Si) was deposited by a microwave plasma CVD technique, employing double dilution of silane, for the growth of low hydrogen content Si films with a controllable microstructure on amorphous substrates at low temperatures (prepared by this technique. Such films showed a dark conductivity ˜10sp{-6} S/cm, with a conduction activation energy of 0.49 eV. Film growth and properties have been compared for deposition in Ar and He carrier systems and growth models have been proposed. Low temperature junction formation by undoped thin film silicon was examined through a thin film silicon/p-type crystalline silicon heterojunctions. The thin film silicon layers were deposited by rf glow discharge, dc magnetron sputtering and microwave plasma CVD. The hetero-interface was identified by current transport analysis and high frequency capacitance methods as the key parameter controlling the photovoltaic (PV) response. The effect of the interface on the device properties (PV, junction, and carrier transport) was examined with respect to modifications created by chemical treatment, type of plasma species, their energy and film microstructure interacting with the substrate. Thermally stimulated capacitance was used to determine the interfacial trap parameters. Plasma deposition of thin film silicon on chemically clean c-Si created electron trapping sites while hole traps were seen when a thin oxide was present at the interface. Under optimized conditions, a 10.6% efficient cell (11.5% with SiOsb2 A/R) with an open circuit voltage of 0.55 volts and a short circuit current density of 30 mA/cmsp2 was fabricated.

Integrated silicon optoelectronics

CERN Document Server

Zimmermann, Horst

2000-01-01

'Integrated Silicon Optoelectronics'assembles optoelectronics and microelectronics The book concentrates on silicon as the major basis of modern semiconductor devices and circuits Starting from the basics of optical emission and absorption and from the device physics of photodetectors, the aspects of the integration of photodetectors in modern bipolar, CMOS, and BiCMOS technologies are discussed Detailed descriptions of fabrication technologies and applications of optoelectronic integrated circuits are included The book, furthermore, contains a review of the state of research on eagerly expected silicon light emitters In order to cover the topic of the book comprehensively, integrated waveguides, gratings, and optoelectronic power devices are included in addition Numerous elaborate illustrations promote an easy comprehension 'Integrated Silicon Optoelectronics'will be of value to engineers, physicists, and scientists in industry and at universities The book is also recommendable for graduate students speciali...

MicroElectroMechanical devices and fabrication technologies for radio-frequency analog signal processing

Science.gov (United States)

Young, Darrin Jun

The proliferation of wireless services creates a pressing need for compact and low cost RF transceivers. Modern sub-micron technologies provide the active components needed for miniaturization but fail to deliver high quality passives needed in oscillators and filters. This dissertation demonstrates procedures for adding high quality inductors and tunable capacitors to a standard silicon integrated circuits. Several voltage-controlled oscillators operating in the low Giga-Hertz range demonstrate the suitability of these components for high performance RF building blocks. Two low-temperature processes are described to add inductors and capacitors to silicon ICs. A 3-D coil geometry is used for the inductors rather than the conventional planar spiral to substantially reduce substrate loss and hence improve the quality factor and self-resonant frequency. Measured Q-factors at 1 GHz are 30 for a 4.8 nH device, 16 for 8.2 nH and 13.8 nH inductors. Several enhancements are proposed that are expected to result in a further improvement of the achievable Q-factor. This research investigates the design and fabrication of silicon-based IC-compatible high-Q tunable capacitors and inductors. The goal of this investigation is to develop a monolithic low phase noise radio-frequency voltage-controlled oscillator using these high-performance passive components for wireless communication applications. Monolithic VCOs will help the miniaturization of current radio transceivers, which offers a potential solution to achieve a single hand-held wireless phone with multistandard capabilities. IC-compatible micromachining fabrication technologies have been developed to realize on-chip high-Q RF tunable capacitors and 3-D coil inductors. The capacitors achieve a nominal capacitance value of 2 pF and can be tuned over 15% with 3 V. A quality factor over 60 has been measured at 1 GHz. 3-D coil inductors obtain values of 4.8 nH, 8.2 nH and 13.8 nH. At 1 GHz a Q factor of 30 has been achieved

Fabrication of multi-functional silicon surface by direct laser writing

Science.gov (United States)

Verma, Ashwani Kumar; Soni, R. K.

2018-05-01

We present a simple, quick and one-step methodology based on nano-second laser direct writing for the fabrication of micro-nanostructures on silicon surface. The fabricated surfaces suppress the optical reflection by multiple reflection due to light trapping effect to a much lower value than polished silicon surface. These textured surfaces offer high enhancement ability after gold nanoparticle deposition and then explored for Surface Enhanced Raman Scattering (SERS) for specific molecular detection. The effect of laser scanning line interval on optical reflection and SERS signal enhancement ability was also investigated. Our results indicate that low optical reflection substrates exhibit uniform SERS enhancement with enhancement factor of the order of 106. Furthermore, this methodology provide an alternative approach for cost-effective large area fabrication with good control over feature size.

Process for forming a porous silicon member in a crystalline silicon member

Science.gov (United States)

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Highly Flexible and Efficient Fabric-Based Organic Light-Emitting Devices for Clothing-Shaped Wearable Displays.

Science.gov (United States)

Choi, Seungyeop; Kwon, Seonil; Kim, Hyuncheol; Kim, Woohyun; Kwon, Jung Hyun; Lim, Myung Sub; Lee, Ho Seung; Choi, Kyung Cheol

2017-07-25

Recently, the role of clothing has evolved from merely body protection, maintaining the body temperature, and fashion, to advanced functions such as various types of information delivery, communication, and even augmented reality. With a wireless internet connection, the integration of circuits and sensors, and a portable power supply, clothes become a novel electronic device. Currently, the information display is the most intuitive interface using visualized communication methods and the simultaneous concurrent processing of inputs and outputs between a wearer and functional clothes. The important aspect in this case is to maintain the characteristic softness of the fabrics even when electronic devices are added to the flexible clothes. Silicone-based light-emitting diode (LED) jackets, shirts, and stage costumes have started to appear, but the intrinsic stiffness of inorganic semiconductors causes wearers to feel discomfort; thus, it is difficult to use such devices for everyday purposes. To address this problem, a method of fabricating a thin and flexible emitting fabric utilizing organic light-emitting diodes (OLEDs) was developed in this work. Its flexibility was evaluated, and an analysis of its mechanical bending characteristics and tests of its long-term reliability were carried out.

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

International Nuclear Information System (INIS)

Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

2010-01-01

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

Fabrication of heterojunction solar cells by using microcrystalline hydrogenated silicon oxide film as an emitter

International Nuclear Information System (INIS)

Banerjee, Chandan; Sritharathikhun, Jaran; Konagai, Makoto; Yamada, Akira

2008-01-01

Wide gap, highly conducting n-type hydrogenated microcrystalline silicon oxide (μc-SiO : H) films were prepared by very high frequency plasma enhanced chemical vapour deposition at a very low substrate temperature (170 deg. C) as an alternative to amorphous silicon (a-Si : H) for use as an emitter layer of heterojunction solar cells. The optoelectronic properties of n-μc-SiO : H films prepared for the emitter layer are dark conductivity = 0.51 S cm -1 at 20 nm thin film, activation energy = 23 meV and E 04 = 2.3 eV. Czochralski-grown 380 μm thick p-type (1 0 0) oriented polished silicon wafers with a resistivity of 1-10 Ω cm were used for the fabrication of heterojunction solar cells. Photovoltaic parameters of the device were found to be V oc = 620 mV, J sc = 32.1 mA cm -2 , FF = 0.77, η = 15.32% (active area efficiency)

Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

NARCIS (Netherlands)

Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

Silicon Nano fabrication by Atomic Force Microscopy-Based Mechanical Processing

International Nuclear Information System (INIS)

Miyake, Sh.; Wang, M.; Kim, J.

2014-01-01

This paper reviews silicon nano fabrication processes using atomic force microscopy (AFM). In particular, it summarizes recent results obtained in our research group regarding AFM-based silicon nano fabrication through mechanochemical local oxidation by diamond tip sliding, as well as mechanical, electrical, and electromechanical processing using an electrically conductive diamond tip. Microscopic three-dimensional manufacturing mainly relies on etching, deposition, and lithography. Therefore, a special emphasis was placed on nano mechanical processes, mechanochemical reaction by potassium hydroxide solution etching, and mechanical and electrical approaches. Several important surface characterization techniques consisting of scanning tunneling microscopy and related techniques, such as scanning probe microscopy and AFM, were also discussed.

Sub-micron silicon nitride waveguide fabrication using conventional optical lithography.

Science.gov (United States)

Huang, Yuewang; Zhao, Qiancheng; Kamyab, Lobna; Rostami, Ali; Capolino, Filippo; Boyraz, Ozdal

2015-03-09

We demonstrate a novel technique to fabricate sub-micron silicon nitride waveguides using conventional contact lithography with MEMS-grade photomasks. Potassium hydroxide anisotropic etching of silicon facilitates line reduction and roughness smoothing and is key to the technique. The fabricated waveguides is measured to have a propagation loss of 0.8dB/cm and nonlinear coefficient of γ = 0.3/W/m. A low anomalous dispersion of <100ps/nm/km is also predicted. This type of waveguide is highly suitable for nonlinear optics. The channels naturally formed on top of the waveguide also make it promising for plasmonics and quantum efficiency enhancement in sensing applications.

Fabrication and Characterization of High-Sensitivity Underwater Acoustic Multimedia Communication Devices with Thick Composite PZT Films

Directory of Open Access Journals (Sweden)

Jeng-Cheng Liu

2017-01-01

Full Text Available This paper presents a high-sensitivity hydrophone fabricated with a Microelectromechanical Systems (MEMS process using epitaxial thin films grown on silicon wafers. The evaluated resonant frequency was calculated through finite-element analysis (FEA. The hydrophone was designed, fabricated, and characterized by different measurements performed in a water tank, by using a pulsed sound technique with a sensitivity of −190 dB ± 2 dB for frequencies in the range 50–500 Hz. These results indicate the high-performance miniaturized acoustic devices, which can impact a variety of technological applications.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

Science.gov (United States)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Science.gov (United States)

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Enhanced Electroluminescence from Silicon Quantum Dots Embedded in Silicon Nitride Thin Films Coupled with Gold Nanoparticles in Light Emitting Devices

Directory of Open Access Journals (Sweden)

Ana Luz Muñoz-Rosas

2018-03-01

Full Text Available Nowadays, the use of plasmonic metal layers to improve the photonic emission characteristics of several semiconductor quantum dots is a booming tool. In this work, we report the use of silicon quantum dots (SiQDs embedded in a silicon nitride thin film coupled with an ultra-thin gold film (AuNPs to fabricate light emitting devices. We used the remote plasma enhanced chemical vapor deposition technique (RPECVD in order to grow two types of silicon nitride thin films. One with an almost stoichiometric composition, acting as non-radiative spacer; the other one, with a silicon excess in its chemical composition, which causes the formation of silicon quantum dots imbibed in the silicon nitride thin film. The ultra-thin gold film was deposited by the direct current (DC-sputtering technique, and an aluminum doped zinc oxide thin film (AZO which was deposited by means of ultrasonic spray pyrolysis, plays the role of the ohmic metal-like electrode. We found that there is a maximum electroluminescence (EL enhancement when the appropriate AuNPs-spacer-SiQDs configuration is used. This EL is achieved at a moderate turn-on voltage of 11 V, and the EL enhancement is around four times bigger than the photoluminescence (PL enhancement of the same AuNPs-spacer-SiQDs configuration. From our experimental results, we surmise that EL enhancement may indeed be due to a plasmonic coupling. This kind of silicon-based LEDs has the potential for technology transfer.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

Science.gov (United States)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Tin (Sn) - An Unlikely Ally to Extend Moore's Law for Silicon CMOS?

KAUST Repository

Hussain, Aftab M.

2012-12-01

There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

The fabrication of nitrogen detector porous silicon nanostructures

Science.gov (United States)

Husairi, F. S.; Othman, N.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

2018-05-01

In this study the porous silicon nanostructure used as a the nitrogen detector was fabricated by using anodization method because of simple and easy to handle. This method using 20 mA/ cm2 of current density and the etching time is from 10 - 40 minutes. The properties of the porous silicon nanostructure analyzed using I-V testing (electrical properties) and photoluminescence spectroscopy. From the I-V testing, sample PsiE40 where the sensitivity is 25.4% is a sensitivity of PSiE40 at 10 seconds exposure time.

Silicon Nanowire Fabrication Using Edge and Corner Lithography

NARCIS (Netherlands)

Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

2010-01-01

This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

Solar cell fabricated on welded thin flexible silicon

Directory of Open Access Journals (Sweden)

Hessmann Maik Thomas

2015-01-01

Full Text Available We present a thin-film crystalline silicon solar cell with an AM1.5 efficiency of 11.5% fabricated on welded 50 μm thin silicon foils. The aperture area of the cell is 1.00 cm2. The cell has an open-circuit voltage of 570 mV, a short-circuit current density of 29.9 mA cm-2 and a fill factor of 67.6%. These are the first results ever presented for solar cells on welded silicon foils. The foils were welded together in order to create the first thin flexible monocrystalline band substrate. A flexible band substrate offers the possibility to overcome the area restriction of ingot-based monocrystalline silicon wafers and the feasibility of a roll-to-roll manufacturing. In combination with an epitaxial and layer transfer process a decrease in production costs can be achieved.

Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

KAUST Repository

Zhai, Yujia

2012-11-26

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

KAUST Repository

Zhai, Yujia; Palard, Marylene; Mathew, Leo; Hussain, Muhammad Mustafa; Willson, Grant Grant; Tutuc, Emanuel; Banerjee, Sanjay Kumar

2012-01-01

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

Design, fabrication and characterization of a two-step released silicon dioxide piezoresistive microcantilever immunosensor

International Nuclear Information System (INIS)

Zhou, Youzheng; Wang, Zheyao; Wang, Chaonan; Ruan, Wenzhou; Liu, Litian

2009-01-01

This paper presents the design, fabrication and characterization of a silicon dioxide piezoresistive microcantilever immunosensor fabricated on silicon-on-insulator (SOI) wafers. The microcantilever consists of two strips of single crystalline silicon piezoresistors sandwiched in between two silicon dioxide layers. A theoretical model for the laminated microcantilever with a discontinuous layer is deduced using classic laminated beam theory. A two-step release method combining anisotropic and isotropic etching is developed to suspend the microcantilever, and the fabrication results show an excellent yield. The residual stress-induced free bending of the microcantilever and the stress caused by self-heating of the piezoresistors are discussed. The microcantilever sensor is characterized as an immunosensor using specific binding of antigen and antibody. These methods and some conclusions are also applicable to the development of other piezoresistive sensors that use laminated structures

A simple and cost-effective method for fabrication of integrated electronic-microfluidic devices using a laser-patterned PDMS layer

KAUST Repository

Li, Ming

2011-12-03

We report a simple and cost-effective method for fabricating integrated electronic-microfluidic devices with multilayer configurations. A CO 2 laser plotter was employed to directly write patterns on a transferred polydimethylsiloxane (PDMS) layer, which served as both a bonding and a working layer. The integration of electronics in microfluidic devices was achieved by an alignment bonding of top and bottom electrode-patterned substrates fabricated with conventional lithography, sputtering and lift-off techniques. Processes of the developed fabrication method were illustrated. Major issues associated with this method as PDMS surface treatment and characterization, thickness-control of the transferred PDMS layer, and laser parameters optimization were discussed, along with the examination and testing of bonding with two representative materials (glass and silicon). The capability of this method was further demonstrated by fabricating a microfluidic chip with sputter-coated electrodes on the top and bottom substrates. The device functioning as a microparticle focusing and trapping chip was experimentally verified. It is confirmed that the proposed method has many advantages, including simple and fast fabrication process, low cost, easy integration of electronics, strong bonding strength, chemical and biological compatibility, etc. © Springer-Verlag 2011.

Fabrication of the similar porous alumina silicon template for soft UV nanoimprint lithography

Energy Technology Data Exchange (ETDEWEB)

Sun, Tangyou [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Xu, Zhimou, E-mail: xuzhimou@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Zhao, Wenning; Wu, Xinghui; Liu, Sisi; Zhang, Zheng; Wang, Shuangbao; Liu, Wen [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Liu, Shiyuan [State Key Laboratory of Digital Manufacturing Equipment and Technology, Huazhong University of Science and Technology, Wuhan 430074 (China); Peng, Jing [College of Sciences, Wuhan University of Science and Technology, Wuhan 430081 (China)

2013-07-01

High density honeycombed nanostructures of porous alumina template (PAT) have been widely used to the fabrication of various electronic, optoelectronic, magnetic, and energy storage devices. However, patterning structures at sub-100 nm feature size with large area and low cost is of great importance and hardness on which semiconductor manufacture technology depends. In this paper, soft UV nanoimprint lithography (SUNIL) by using PAT as the initial mold is studied in detail. The results reveal a significant incompatibility between these two candidates. The native nonflatness of the PAT surface is about 100 nm in the range of 2–5 μm. Resist detaches from the substrate because of the mold deformation in the nonflat SUNIL. A two-inch similar porous alumina silicon (Si) template with nanopore size of 50–100 nm is fabricated. I–t curve conducted anodization and subsequent inductive coupled plasma (ICP) dry etching are applied to ensure the uniformity of the fabricated template. The surface flatness of the similar porous alumina Si template is the same as the polished Si wafer, which perfectly matches NIL.

Fabricating 40 µm-thin silicon solar cells with different orientations by using SLiM-cut method

Science.gov (United States)

Wang, Teng-Yu; Chen, Chien-Hsun; Shiao, Jui-Chung; Chen, Sung-Yu; Du, Chen-Hsun

2017-10-01

Thin silicon foils with different crystal orientations were fabricated using the stress induced lift-off (SLiM-cut) method. The thickness of the silicon foils was approximately 40 µm. The ≤ft foil had a smoother surface than the ≤ft foil. With surface passivation, the minority carrier lifetimes of the ≤ft and ≤ft silicon foil were 1.0 µs and 1.6 µs, respectively. In this study, 4 cm2-thin silicon solar cells with heterojunction structures were fabricated. The energy conversion efficiencies were determined to be 10.74% and 14.74% for the ≤ft and ≤ft solar cells, respectively. The surface quality of the silicon foils was determined to affect the solar cell character. This study demonstrated that fabricating the solar cell by using silicon foil obtained from the SLiM-cut method is feasible.

Electrical effects of transient neutron irradiation of silicon devices

International Nuclear Information System (INIS)

Hjalmarson, H.P.; Pease, R.L.; Van Ginhoven, R.M.; Schultz, P.A.; Modine, N.A.

2007-01-01

The key effects of combined transient neutron and ionizing radiation on silicon diodes and bipolar junctions transistors are described. The results show that interstitial defect reactions dominate the annealing effects in the first stage of annealing for certain devices. Furthermore, the results show that oxide trapped charge can influence the effects of bulk silicon displacement damage for particular devices

Tin (Sn) for enhancing performance in silicon CMOS

KAUST Repository

Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

2013-01-01

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

Tin (Sn) for enhancing performance in silicon CMOS

KAUST Repository

Hussain, Aftab M.

2013-10-01

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

Science.gov (United States)

2016-08-19

limiters, MEMS, NEMS, field emission, cold cathodes (Some figures may appear in colour only in the online journal) 1. Introduction Dense arrays of silicon... attention has been given to densely packed, highly ordered, top-down fabricated, single crystal vertical silicon nanowire devices that are embedded

Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

International Nuclear Information System (INIS)

Moslehi, M.M.; Davis, C.

1989-01-01

Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

Silicon photonics design from devices to systems

CERN Document Server

Chrostowski, Lukas

2015-01-01

From design and simulation through to testing and fabrication, this hands-on introduction to silicon photonics engineering equips students with everything they need to begin creating foundry-ready designs. In-depth discussion of real-world issues and fabrication challenges ensures that students are fully equipped for careers in industry. Step-by-step tutorials, straightforward examples, and illustrative source code fragments guide students through every aspect of the design process, providing a practical framework for developing and refining key skills. Offering industry-ready expertise, the text supports existing PDKs for CMOS UV-lithography foundry services (OpSIS, ePIXfab, imec, LETI, IME and CMC) and the development of new kits for proprietary processes and clean-room based research. Accompanied by additional online resources to support students, this is the perfect learning package for senior undergraduate and graduate students studying silicon photonics design, and academic and industrial researchers in...

Nonlinear silicon photonics

Science.gov (United States)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology.

Science.gov (United States)

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-12-03

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm(2), and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p(+-)n homojunction through the formation of re-grown crystalline silicon layer (~5-10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method.

Advanced Silicone-based Coatings for Flexible Fabric Applications, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Silicone coatings are the system of choice for inflatable fabrics used in several space, military, and consumer applications, including airbags, parachutes, rafts,...

Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

International Nuclear Information System (INIS)

Olsen, Sarah H.

2002-01-01

Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

Fabrication of optical devices in poly(dimethylsiloxane) by proton microbeam

International Nuclear Information System (INIS)

Huszank, R.; Szilasi, S.Z.; Rajta, I.; Csik, A.

2009-01-01

Complete text of publication follows. Optical diffraction grating and micro Fresnel zone plate type structures were fabricated in relatively thin poly(dimethylsiloxane) (PDMS) layers using proton beam writing technique and the performance of these optical devices was tested. Micro-optics is a key technology in many fields of common applications like, for example, data communication, lighting technology, industrial automation, display technology, sensing applications and data storage. It enables new functionalities and applications previously inaccessible and improves performance of the already available products with reduced cost, volume and weight. There are a few different fabrication techniques to produce refractive or diffractive micro-optical devices such as X-ray lithography, UV-lithography, e-beam lithography, laser writing, plasma etching, proton beam writing. In general, three different kinds of materials are used for micro-optics, such as glass, polymers and crystal. PDMS is a commonly used silicon-based organic polymer, optically clear, generally considered to be inert, non-toxic and biocompatible and it has been used as a resist material for direct write techniques only in very few cases. In this work, PDMS was used as a resist material; the structures were irradiated directly into the polymer. We were looking for a biocompatible, micropatternable polymer in which the chemical structure changes significantly due to proton beam exposure making the polymer capable of proton beam writing. We demonstrated that the change in the structure of the polymer is so significant that there is no need to perform any development processes. The proton irradiation causes refractive index change in the polymer, so diffraction gratings and other optical devices like Fresnel zone plates can be fabricated in this way. The observed high order diffraction patterns prove the high quality of the created optical devices [1]. This technique may be a useful tool for designing

Fabricating a silicon nanowire by using the proximity effect in electron beam lithography for investigation of the Coulomb blockade effect

International Nuclear Information System (INIS)

Zhang Xiangao; Fang Zhonghui; Chen Kunji; Xu Jun; Huang Xinfan

2011-01-01

We present an approach to fabricate a silicon nanowire relying on the proximity effect in electron beam lithography with a low acceleration voltage system by designing the exposure patterns with a rhombus sandwiched between two symmetric wedges. The reproducibility is investigated by changing the number of rhombuses. A device with a silicon nanowire is constructed on a highly doped silicon-on-insulator wafer to measure the electronic transport characteristics. Significant nonlinear behavior of current-voltage curves is observed at up to 150 K. The dependence of current on the drain voltage and back-gate voltage shows Coulomb blockade oscillations at 5.4 K, revealing a Coulomb island naturally formed in the nanowire. The mechanism of formation of the Coulomb island is discussed.

Silicon Carbide Power Devices and Integrated Circuits

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

Science.gov (United States)

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

Assessment on thermoelectric power factor in silicon nanowire networks

Energy Technology Data Exchange (ETDEWEB)

Lohn, Andrew J.; Kobayashi, Nobuhiko P. [Baskin School of Engineering, University of California Santa Cruz, CA (United States); Nanostructured Energy Conversion Technology and Research (NECTAR), Advanced Studies Laboratories, University of California Santa Cruz, NASA Ames Research Center, Moffett Field, CA (United States); Coleman, Elane; Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

2012-01-15

Thermoelectric devices based on three-dimensional networks of highly interconnected silicon nanowires were fabricated and the parameters that contribute to the power factor, namely the Seebeck coefficient and electrical conductivity were assessed. The large area (2 cm x 2 cm) devices were fabricated at low cost utilizing a highly scalable process involving silicon nanowires grown on steel substrates. Temperature dependence of the Seebeck coefficient was found to be weak over the range of 20-80 C at approximately -400 {mu}V/K for unintentionally doped devices and {+-}50 {mu}V/K for p-type and n-type devices, respectively. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Compact integrated optical devices for optical sensor and switching applications

NARCIS (Netherlands)

Kauppinen, L.J.

2010-01-01

This thesis describes the design, fabrication, and characterization of compact optical devices for sensing and switching applications. Our focus has been to realize the devices using CMOS-compatible fabrication processes. Particularly the silicon photonics fabrication platform, ePIXfab, has been

Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

International Nuclear Information System (INIS)

Neamen, D.; Shedd, W.; Buchanan, B.

1975-01-01

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

MOS structures containing silicon nanoparticles for memory device applications

International Nuclear Information System (INIS)

Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

2008-01-01

Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

Friction-induced nanofabrication on monocrystalline silicon

International Nuclear Information System (INIS)

Yu Bingjun; Qian Linmao; Yu Jiaxin; Zhou Zhongrong; Dong Hanshan; Chen Yunfei

2009-01-01

Fabrication of nanostructures has become a major concern as the scaling of device dimensions continues. In this paper, a friction-induced nanofabrication method is proposed to fabricate protrusive nanostructures on silicon. Without applying any voltage, the nanofabrication is completed by sliding an AFM diamond tip on a sample surface under a given normal load. Nanostructured patterns, such as linear nanostructures, nanodots or nanowords, can be fabricated on the target surface. The height of these nanostructures increases rapidly at first and then levels off with the increasing normal load or number of scratching cycles. TEM analyses suggest that the friction-induced hillock is composed of silicon oxide, amorphous silicon and deformed silicon structures. Compared to the tribochemical reaction, the amorphization and crystal defects induced by the mechanical interaction may have played a dominating role in the formation of the hillocks. Similar to other proximal probe methods, the proposed method enables fabrication at specified locations and facilitates measuring the dimensions of nanostructures with high precision. It is highlighted that the fabrication can also be realized on electrical insulators or oxide surfaces, such as quartz and glass. Therefore, the friction-induced method points out a new route in fabricating nanostructures on demand.

Fabrication of biopolymer cantilevers using nanoimprint lithography

DEFF Research Database (Denmark)

Keller, Stephan Sylvest; Feidenhans'l, Nikolaj Agentoft; Fisker-Bødker, Nis

2011-01-01

The biodegradable polymer poly(l-lactide) (PLLA) was introduced for the fabrication of micromechanical devices. For this purpose, thin biopolymer films with thickness around 10 μm were spin-coated on silicon substrates. Patterning of microcantilevers is achieved by nanoimprint lithography. A major...... challenge was the high adhesion between PLLA and silicon stamp. Optimized stamp fabrication and the deposition of a 125 nm thick fluorocarbon anti-stiction coating on the PLLA allowed the fabrication of biopolymer cantilevers. Resonance frequency measurements were used to estimate the Young’s modulus...

Nonlinear electrical properties of Si three-terminal junction devices

DEFF Research Database (Denmark)

Fantao, Meng; Jie, Sun; Graczyk, Mariusz

2010-01-01

This letter reports on the realization and characterization of silicon three-terminal junction devices made in a silicon-on-insulator wafer. Room temperature electrical measurements show that the fabricated devices exhibit pronounced nonlinear electrical properties inherent to ballistic electron...... transport in a three-terminal ballistic junction (TBJ) device. The results show that room temperature functional TBJ devices can be realized in a semiconductor material other than high-mobility III-V semiconductor heterostructures and provide a simple design principle for compact silicon devices...

Imprinted silicon-based nanophotonics

DEFF Research Database (Denmark)

Borel, Peter Ingo; Olsen, Brian Bilenberg; Frandsen, Lars Hagedorn

2007-01-01

We demonstrate and optically characterize silicon-on-insulator based nanophotonic devices fabricated by nanoimprint lithography. In our demonstration, we have realized ordinary and topology-optimized photonic crystal waveguide structures. The topology-optimized structures require lateral pattern ...

Electroless porous silicon formation applied to fabrication of boron–silica–glass cantilevers

International Nuclear Information System (INIS)

Teva, J; Davis, Z J; Hansen, O

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5–1 mm 3 ) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing the etching rate and reproducibility of the etching. In addition to that, a study of the morphology of the pore that is obtained by this technique is presented. The results from the characterization of the process are applied to the fabrication of boron–silica–glass cantilevers that serve as a platform for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH solution

Particle interaction and displacement damage in silicon devices operated in radiation environments

International Nuclear Information System (INIS)

Leroy, Claude; Rancoita, Pier-Giorgio

2007-01-01

Silicon is used in radiation detectors and electronic devices. Nowadays, these devices achieving submicron technology are parts of integrated circuits of large to very large scale integration (VLSI). Silicon and silicon-based devices are commonly operated in many fields including particle physics experiments, nuclear medicine and space. Some of these fields present adverse radiation environments that may affect the operation of the devices. The particle energy deposition mechanisms by ionization and non-ionization processes are reviewed as well as the radiation-induced damage and its effect on device parameters evolution, depending on particle type, energy and fluence. The temporary or permanent damage inflicted by a single particle (single event effect) to electronic devices or integrated circuits is treated separately from the total ionizing dose (TID) effect for which the accumulated fluence causes degradation and from the displacement damage induced by the non-ionizing energy-loss (NIEL) deposition. Understanding of radiation effects on silicon devices has an impact on their design and allows the prediction of a specific device behaviour when exposed to a radiation field of interest

A novel fabrication method of silicon nano-needles using MEMS TMAH etching techniques

International Nuclear Information System (INIS)

Yan Sheping; Xu Yang; Yang Junyi; Wang Huiquan; Jin Zhonghe; Wang Yuelin

2011-01-01

Nano-needles play important roles in nanoscale operations. However, current nano-needle fabrication is usually expensive and controling the sizes and angles is complicated. We have developed a simple and low cost silicon nano-needle fabrication method using traditional microelectromechanical system (MEMS) tetramethyl ammonium hydroxide (TMAH) etching techniques. We take advantage of the fact that the decrease of the silicon etch rate in TMAH solutions exhibits an inverse fourth power dependence on the boron doping concentration in our nano-needle fabrication. Silicon nano-needles, with high aspect ratio and sharp angles θ as small as 2.9 deg., are obtained, which could be used for bio-sensors and nano-handling procedures, such as penetrating living cells. An analytic model is proposed to explain the etching evolution of the experimental results, which is used to predict the needle angle, length, and etching time. Based on our method, nano-needles with small acute angle θ can be obtained.

Device Fabrication and Probing of Discrete Carbon Nanostructures

KAUST Repository

Batra, Nitin M

2015-05-06

Device fabrication on multi walled carbon nanotubes (MWCNTs) using electrical beam lithography (EBL), electron beam induced deposition (EBID), ion beam induced deposition (IBID) methods was carried out, followed by device electrical characterization using a conventional probe station. A four-probe configuration was utilized to measure accurately the electrical resistivity of MWCNTs with similar results obtained from devices fabricated by different methods. In order to reduce the contact resistance of the beam deposited platinum electrodes, single step vacuum thermal annealing was performed. Microscopy and spectroscopy were carried out on the beam deposited electrodes to follow the structural and chemical changes occurring during the vacuum thermal annealing. For the first time, a core-shell type structure was identified on EBID Pt and IBID Pt annealed electrodes and analogous free standing nanorods previously exposed to high temperature. We believe this observation has important implications for transport properties studies of carbon materials. Apart from that, contamination of carbon nanostructure, originating from the device fabrication methods, was also studied. Finally, based on the observations of faster processing time together with higher yield and flexibility for device preparation, we investigated EBID to fabricate devices for other discrete carbon nanostructures.

Novel fabrication of silicon carbide based ceramics for nuclear applications

Science.gov (United States)

Singh, Abhishek Kumar

Advances in nuclear reactor technology and the use of gas-cooled fast reactors require the development of new materials that can operate at the higher temperatures expected in these systems. These materials include refractory alloys based on Nb, Zr, Ta, Mo, W, and Re; ceramics and composites such as SiC--SiCf; carbon--carbon composites; and advanced coatings. Besides the ability to handle higher expected temperatures, effective heat transfer between reactor components is necessary for improved efficiency. Improving thermal conductivity of the fuel can lower the center-line temperature and, thereby, enhance power production capabilities and reduce the risk of premature fuel pellet failure. Crystalline silicon carbide has superior characteristics as a structural material from the viewpoint of its thermal and mechanical properties, thermal shock resistance, chemical stability, and low radioactivation. Therefore, there have been many efforts to develop SiC based composites in various forms for use in advanced energy systems. In recent years, with the development of high yield preceramic precursors, the polymer infiltration and pyrolysis (PIP) method has aroused interest for the fabrication of ceramic based materials, for various applications ranging from disc brakes to nuclear reactor fuels. The pyrolysis of preceramic polymers allow new types of ceramic materials to be processed at relatively low temperatures. The raw materials are element-organic polymers whose composition and architecture can be tailored and varied. The primary focus of this study is to use a pyrolysis based process to fabricate a host of novel silicon carbide-metal carbide or oxide composites, and to synthesize new materials based on mixed-metal silicocarbides that cannot be processed using conventional techniques. Allylhydridopolycarbosilane (AHPCS), which is an organometal polymer, was used as the precursor for silicon carbide. Inert gas pyrolysis of AHPCS produces near-stoichiometric amorphous

Fundamental understanding and development of low-cost, high-efficiency silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

ROHATGI,A.; NARASIMHA,S.; MOSCHER,J.; EBONG,A.; KAMRA,S.; KRYGOWSKI,T.; DOSHI,P.; RISTOW,A.; YELUNDUR,V.; RUBY,DOUGLAS S.

2000-05-01

The overall objectives of this program are (1) to develop rapid and low-cost processes for manufacturing that can improve yield, throughput, and performance of silicon photovoltaic devices, (2) to design and fabricate high-efficiency solar cells on promising low-cost materials, and (3) to improve the fundamental understanding of advanced photovoltaic devices. Several rapid and potentially low-cost technologies are described in this report that were developed and applied toward the fabrication of high-efficiency silicon solar cells.

Thermoelectric characteristics of Pt-silicide/silicon multi-layer structured p-type silicon

International Nuclear Information System (INIS)

Choi, Wonchul; Jun, Dongseok; Kim, Soojung; Shin, Mincheol; Jang, Moongyu

2015-01-01

Electric and thermoelectric properties of silicide/silicon multi-layer structured devices were investigated with the variation of silicide/silicon heterojunction numbers from 3 to 12 layers. For the fabrication of silicide/silicon multi-layered structure, platinum and silicon layers are repeatedly sputtered on the (100) silicon bulk substrate and rapid thermal annealing is carried out for the silicidation. The manufactured devices show ohmic current–voltage (I–V) characteristics. The Seebeck coefficient of bulk Si is evaluated as 195.8 ± 15.3 μV/K at 300 K, whereas the 12 layered silicide/silicon multi-layer structured device is evaluated as 201.8 ± 9.1 μV/K. As the temperature increases to 400 K, the Seebeck coefficient increases to 237.2 ± 4.7 μV/K and 277.0 ± 1.1 μV/K for bulk and 12 layered devices, respectively. The increase of Seebeck coefficient in multi-layered structure is mainly attributed to the electron filtering effect due to the Schottky barrier at Pt-silicide/silicon interface. At 400 K, the thermal conductivity is reduced by about half of magnitude compared to bulk in multi-layered device which shows the efficient suppression of phonon propagation by using Pt-silicide/silicon hetero-junctions. - Highlights: • Silicide/silicon multi-layer structured is proposed for thermoelectric devices. • Electric and thermoelectric properties with the number of layer are investigated. • An increase of Seebeck coefficient is mainly attributed the Schottky barrier. • Phonon propagation is suppressed with the existence of Schottky barrier. • Thermal conductivity is reduced due to the suppression of phonon propagation

Formation of array microstructures on silicon by multibeam interfered femtosecond laser pulses

International Nuclear Information System (INIS)

Zhao Quanzhong; Qiu Jianrong; Zhao Chongjun; Jiang Xiongwei; Zhu Congshan

2005-01-01

We report on an optical interference method to fabricate array microstructures on the surface of silicon wafers by means of five-beam interference of femtosecond laser pulses. Optical microscope and scanning electron microscope observations revealed microstructures with micrometer-order were fabricated. The diffraction characteristics of the fabricated structures were evaluated. The present technique allows one-step realization of functional optoelectronic devices on silicon surface

An improved fabrication process for Si-detector-compatible JFETs

International Nuclear Information System (INIS)

Piemonte, Claudio; Dalla Betta, Gian-Franco; Boscardin, Maurizio; Gregori, Paolo; Zorzi, Nicola; Ratti, Lodovico

2006-01-01

We report on JFET devices fabricated on high-resistivity silicon with a radiation detector technology. The problems affecting previous versions of these devices have been thoroughly investigated and solved by developing an improved fabrication process, which allows for a sizeable enhancement in the JFET performance. In this paper, the main features of the fabrication technology are presented and selected results from the electrical and noise characterization of transistors are discussed

Integration of lateral porous silicon membranes into planar microfluidics.

Science.gov (United States)

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Fabrication and optical characteristics of silicon-based two-dimensional wavelength division multiplexing splitter with photonic crystal directional waveguide couplers

International Nuclear Information System (INIS)

Liu, Cheng-Yang

2011-01-01

Photonic crystals have many potential applications because of their ability to control lightwave propagation. We report on the fabrication and optical properties of quasi-two-dimensional photonic crystals with triangular lattice of dielectric rods in air. Rod-type photonic crystal structures were fabricated in silicon by electron beam lithography and dry-etching techniques. Wavelength division multiplexing splitters were fabricated from two-dimensional photonic crystal directional waveguide couplers. Transmission spectra were measured and device operation was shown to be in agreement with theoretical calculations. The splitters can be used in visible light region. Such an approach to photonic element systems should enable new applications for designing components in photonic integrated circuits. -- Highlights: → We report the fabrication and optical properties of rod-type photonic crystal. → The splitter was fabricated by electron beam lithography and dry-etching techniques. → The splitter was composed of directional waveguide couplers. → Measured transmission spectra are in agreement with theoretical calculations. → The splitters can be used in visible light region.

Porous-shaped silicon carbide ultraviolet photodetectors on porous silicon substrates

Energy Technology Data Exchange (ETDEWEB)

Naderi, N., E-mail: naderi.phd@gmail.com [Nano-Optoelectronics Research Laboratory, School of Physics, Universiti Sains Malaysia, 11800 USM, Penang (Malaysia); Hashim, M.R. [Nano-Optoelectronics Research Laboratory, School of Physics, Universiti Sains Malaysia, 11800 USM, Penang (Malaysia)

2013-03-05

Highlights: ► Porous-shaped silicon carbide thin film was deposited on porous silicon substrate. ► Thermal annealing was followed to enhance the physical properties of samples. ► Metal–semiconductor-metal ultraviolet detectors were fabricated on samples. ► The effect of annealing temperature on electrical performance of devices was studied. ► The efficiency of photodetectors was enhanced by annealing at elevated temperatures. -- Abstract: A metal–semiconductor-metal (MSM) ultraviolet photodetector was fabricated based on a porous-shaped structure of silicon carbide (SiC). For increasing the surface roughness of SiC and hence enhancing the light absorption effect in fabricated devices, porous silicon (PS) was chosen as a template; SiC was deposited on PS substrates via radio frequency magnetron sputtering. Therefore, the deposited layers followed the structural pattern of PS skeleton and formed a porous-shaped SiC layer on PS substrate. The structural properties of samples showed that the as-deposited SiC was amorphous. Thus, a post-deposition annealing process with elevated temperatures was required to convert its amorphous phase to crystalline phase. The morphology of the sputtered samples was examined via scanning electron and atomic force microscopies. The grain size and roughness of the deposited layers clearly increased upon an increase in the annealing temperature. The optical properties of sputtered SiC were enhanced due to applying high temperatures. The most intense photoluminescence peak was observed for the sample with 1200 °C of annealing temperature. For the metallization of the SiC substrates to fabricate MSM photodetectors, two interdigitated Schottky contacts of Ni with four fingers for each electrode were deposited onto all the porous substrates. The optoelectronic characteristics of MSM UV photodetectors with porous-shaped SiC substrates were studied in the dark and under UV illumination. The electrical characteristics of fabricated

Porous-shaped silicon carbide ultraviolet photodetectors on porous silicon substrates

International Nuclear Information System (INIS)

Naderi, N.; Hashim, M.R.

2013-01-01

Highlights: ► Porous-shaped silicon carbide thin film was deposited on porous silicon substrate. ► Thermal annealing was followed to enhance the physical properties of samples. ► Metal–semiconductor-metal ultraviolet detectors were fabricated on samples. ► The effect of annealing temperature on electrical performance of devices was studied. ► The efficiency of photodetectors was enhanced by annealing at elevated temperatures. -- Abstract: A metal–semiconductor-metal (MSM) ultraviolet photodetector was fabricated based on a porous-shaped structure of silicon carbide (SiC). For increasing the surface roughness of SiC and hence enhancing the light absorption effect in fabricated devices, porous silicon (PS) was chosen as a template; SiC was deposited on PS substrates via radio frequency magnetron sputtering. Therefore, the deposited layers followed the structural pattern of PS skeleton and formed a porous-shaped SiC layer on PS substrate. The structural properties of samples showed that the as-deposited SiC was amorphous. Thus, a post-deposition annealing process with elevated temperatures was required to convert its amorphous phase to crystalline phase. The morphology of the sputtered samples was examined via scanning electron and atomic force microscopies. The grain size and roughness of the deposited layers clearly increased upon an increase in the annealing temperature. The optical properties of sputtered SiC were enhanced due to applying high temperatures. The most intense photoluminescence peak was observed for the sample with 1200 °C of annealing temperature. For the metallization of the SiC substrates to fabricate MSM photodetectors, two interdigitated Schottky contacts of Ni with four fingers for each electrode were deposited onto all the porous substrates. The optoelectronic characteristics of MSM UV photodetectors with porous-shaped SiC substrates were studied in the dark and under UV illumination. The electrical characteristics of fabricated

Small area silicon diffused junction x-ray detectors

International Nuclear Information System (INIS)

Walton, J.T.; Pehl, R.H.; Larsh, A.E.

1981-10-01

The low temperature performance of silicon diffused junction detectors in the measurement of low energy x-rays is reported. The detectors have an area of 0.04 cm 2 and a thickness of 100 μm. The spectral resolutions of these detectors were found to be in close agreement with expected values indicating that the defects introduced by the high temperature processing required in the device fabrication were not deleteriously affecting the detection of low energy x-rays. Device performance over a temperature range of 77 to 150 0 K is given. These detectors were designed to detect low energy x-rays in the presence of minimum ionizing electrons. The successful application of silicon diffused junction technology to x-ray detector fabrication may facilitate the development of other novel silicon x-ray detector designs

Small area silicon diffused junction X-ray detectors

Science.gov (United States)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

Fabrication of silicon condenser microphones using single wafer technology

NARCIS (Netherlands)

Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

1992-01-01

A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

A radiation detector fabricated from silicon photodiode.

Science.gov (United States)

Yamamoto, H; Hatakeyama, S; Norimura, T; Tsuchiya, T

1984-12-01

A silicon photodiode is converted to a low energy charged particle radiation detector. The window thickness of the fabricated detector is evaluated to be 50 micrograms/cm2. The area of the depletion region is 13.2 mm2 and the depth of it is estimated to be about 100 microns. The energy resolution (FWHM) is 14.5 ke V for alpha-particles from 241Am and 2.5 ke V for conversion electrons from 109Cd, respectively.

High-performance RF coil inductors on silicon

Energy Technology Data Exchange (ETDEWEB)

Malba, V.; Young, D.; Ou, J.J.; Bernhardt, A.F.; Boser, B.E.

1998-03-01

Strong demand for wireless communication devices has motivated research directed toward monolithic integration of transceivers. The fundamental electronic component least compatible with silicon integrated circuits is the inductor, although a number of inductors are required to implement oscillators, filters and matching networks in cellular devices. Spiral inductors have been integrated into the silicon IC metallization sequence but have not performed adequately due to coupling to the silicon which results in parasitic capacitance and loss. We have, for the first time, fabricated three dimensional coil inductors on silicon which have significantly lower capacitive coupling and loss and which now exceed the requirements of potential applications. Quality factors of 30 at 1 GHz have been measured in single turn devices and Q > 16 in 2 and 4 turn devices. The reduced Q for multiturn devices appears to be related to eddy currents in outer turns generated by magnetic fields from current in neighboring turns. Higher Q values significantly in excess of 30 are anticipated using modified coil designs.

Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

Science.gov (United States)

Yoo, H. I.; Iles, P. A.; Tanner, D. P.

1979-01-01

Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance.

Solar cell structure incorporating a novel single crystal silicon material

Science.gov (United States)

Pankove, Jacques I.; Wu, Chung P.

1983-01-01

A novel hydrogen rich single crystal silicon material having a band gap energy greater than 1.1 eV can be fabricated by forming an amorphous region of graded crystallinity in a body of single crystalline silicon and thereafter contacting the region with atomic hydrogen followed by pulsed laser annealing at a sufficient power and for a sufficient duration to recrystallize the region into single crystal silicon without out-gassing the hydrogen. The new material can be used to fabricate semiconductor devices such as single crystal silicon solar cells with surface window regions having a greater band gap energy than that of single crystal silicon without hydrogen.

Electrical and optical characteristics of heterojunction devices composed of silicon nanowires and mercury selenide nanoparticle films on flexible plastics.

Science.gov (United States)

Yeo, Minje; Yun, Junggwon; Kim, Sangsig

2013-09-01

A pn heterojunction device based on p-type silicon (Si) nanowires (NWs) prepared by top-down method and n-type mercury selenide (HgSe) nanoparticles (NPs) synthesized by the colloidal method have been fabricated on a flexible plastic substrate. The synthesized HgSe NPs were analyzed through the effective mass approximation. The characteristics of the heterojunction device were examined and studied with the energy band diagram. The device showed typical diode characteristics with a turn-on voltage of 1.5 V and exhibited a high rectification ratio of 10(3) under relatively low forward bias. Under illumination of 633-nm-wavelength light, the device presented photocurrent efficiency of 117.5 and 20.1 nA/W under forward bias and reverse bias conditions, respectively. Moreover, the photocurrent characteristics of the device have been determined by bending of the plastic substrate upward and downward with strain of 0.8%. Even though the photocurrent efficiency has fluctuations during the bending cycles, the values are roughly maintained for 10(4) bending cycles. This result indicates that the fabricated heterojunction device has the potential to be applied as fundamental elements of flexible nanoelectronics.

Fabricating Zr-Based Bulk Metallic Glass Microcomponent by Suction Casting Using Silicon Micromold

Directory of Open Access Journals (Sweden)

Zhijing Zhu

2014-08-01

Full Text Available A suction casting process for fabricating Zr55Cu30Al10Ni5 bulk metallic glass microcomponent using silicon micromold has been studied. A complicated BMG microgear with 50 μm in module has been cast successfully. Observed by scanning electron microscopy and laser scanning confocal microscopy, we find that the cast microgear duplicates the silicon micromold including the microstructure on the surface. The amorphous state of the microgear is confirmed by transmission election microscopy. The nanoindentation hardness and elasticity modulus of the microgear reach 6.5 GPa and 94.5 GPa. The simulation and experimental results prove that the suction casting process with the silicon micromold is a promising one-step method to fabricate bulk metallic glass microcomponents with high performance for applications in microelectromechanical system.

Porous Microfluidic Devices - Fabrication adn Applications

NARCIS (Netherlands)

de Jong, J.; Geerken, M.J.; Lammertink, Rob G.H.; Wessling, Matthias

2007-01-01

The major part of microfluidic devices nowadays consists of a dense material that defines the fluidic structure. A generic fabrication method enabling the production of completely porous micro devices with user-defined channel networks is developed. The channel walls can be used as a (selective)

Fabrication of Up-Conversion Phosphor Films on Flexible Substrates Using a Nanostructured Organo-Silicon.

Science.gov (United States)

Jeon, Young-Sun; Kim, Tae-Un; Kim, Seon-Hoon; Lee, Young-Hwan; Choi, Pil-Son; Hwang, Kyu-Seog

2018-03-01

Up-conversion phosphors have attracted considerable attention because of their applications in solid-state lasers, optical communications, flat-panel displays, photovoltaic cells, and biological labels. Among them, NaYF4 is reported as one of the most efficient hosts for infrared to visible photon up-conversion of Yb3+ and Er3+ ions. However, a low-temperature method is required for industrial scale fabrication of photonic and optoelectronic devices on flexible organic substrates. In this study, hexagonal β-NaYF4: 3 mol% Yb3+, 3 mol% Er3+ up-conversion phosphor using Ca2+ was prepared by chemical solution method. Then, we synthesized a nanostructured organo-silicon compound from methyl tri-methoxysilane and 3-glycidoxy-propyl-trimethoxy-silane. The transmittance of the organo-silicon compound was found to be over 90% in the wavelength range of 400~1500 nm. Then we prepared a fluoride-based phosphor paste by mixing the organo-silicon compound with Na(Ca)YF4:Yb3+, Er3+. Subsequently, this paste was coated on polyethylene terephthalate, followed by heat-treatment at 120 °C. The visible emission of the infrared detection card was found to be at 655 nm and 661 nm an excitation wavelength of 980 nm.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

Science.gov (United States)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

STM imaging of buried P atoms in hydrogen-terminated Si for the fabrication of a Si:P quantum computer

Energy Technology Data Exchange (ETDEWEB)

Oberbeck, L.; Curson, N.J.; Hallam, T.; Simmons, M.Y.; Clark, R.G

2004-10-01

The fabrication of atomic-scale devices in silicon requires the encapsulation of dopant atoms which have been incorporated into the silicon surface at atomically precise positions using scanning tunnelling microscopy (STM) lithography. During silicon encapsulation, it is important to minimise segregation and diffusion of dopant atoms in order to retain the lithography defined device structure. Buried dopant imaging using STM is capable of imaging dopant atoms such as phosphorus after encapsulation in silicon several monolayers below the silicon surface, thus making it possible to check the integrity of the device structure. To fabricate buried phosphorus-doped samples, we use phosphine gas as a source of phosphorus atoms and incorporate the phosphorus atoms into a Si(001) surface during an annealing step. Molecular beam epitaxy is used to encapsulate the dopant atoms with several monolayers of silicon. After encapsulation, we hydrogen terminate the silicon surface in order to image the buried phosphorus dopants using STM. We show that a buried phosphorus atom appears as a bright glow superimposed on the silicon dimer structure in empty state STM images, whereas filled state images only show a very faint protrusion in the vicinity of the phosphorus atom. We highlight the importance of our results for the fabrication of atomic-scale devices.

STM imaging of buried P atoms in hydrogen-terminated Si for the fabrication of a Si:P quantum computer

International Nuclear Information System (INIS)

Oberbeck, L.; Curson, N.J.; Hallam, T.; Simmons, M.Y.; Clark, R.G.

2004-01-01

The fabrication of atomic-scale devices in silicon requires the encapsulation of dopant atoms which have been incorporated into the silicon surface at atomically precise positions using scanning tunnelling microscopy (STM) lithography. During silicon encapsulation, it is important to minimise segregation and diffusion of dopant atoms in order to retain the lithography defined device structure. Buried dopant imaging using STM is capable of imaging dopant atoms such as phosphorus after encapsulation in silicon several monolayers below the silicon surface, thus making it possible to check the integrity of the device structure. To fabricate buried phosphorus-doped samples, we use phosphine gas as a source of phosphorus atoms and incorporate the phosphorus atoms into a Si(001) surface during an annealing step. Molecular beam epitaxy is used to encapsulate the dopant atoms with several monolayers of silicon. After encapsulation, we hydrogen terminate the silicon surface in order to image the buried phosphorus dopants using STM. We show that a buried phosphorus atom appears as a bright glow superimposed on the silicon dimer structure in empty state STM images, whereas filled state images only show a very faint protrusion in the vicinity of the phosphorus atom. We highlight the importance of our results for the fabrication of atomic-scale devices

Fabrication of micromirrors with pyramidal shape using anisotropic etching of silicon

OpenAIRE

Moktadir, Z.; Vijaya Prakash, G.; Trupke, M.; Koukharenko, E.; Kraft, M.; Baumberg, J.J.; Eriksson, S.; Hinds, E.A.

2005-01-01

Gold micro-mirrors have been formed in silicon in an inverted pyramidal shape. The pyramidal structures are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micro-mirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into MOEMS systems.

Selective etching of n-type silicon in pn junction structure in hydrofluoric acid and its application in silicon nanowire fabrication

International Nuclear Information System (INIS)

Wang Huiquan; Jin Zhonghe; Zheng Yangming; Ma Huilian; Wang Yuelin; Li Tie

2008-01-01

Boron is selectively implanted on the surface of an n-type silicon wafer to form a p-type area surrounded by an n-type area. The wafer is then put into a buffered oxide etch solution. It is found that the n-type area can be selectively etched without illumination, with an etching rate lower than 1 nm min -1 , while the p-type area can be selectively etched under illumination with a much higher etching rate. The possible mechanism of the etching phenomenon is discussed. A simple fabrication process of silicon nanowires is proposed according to the above phenomenon. In this process only traditional micro-electromechanical system technology is used. Dimensions of the fabricated nanowire can be controlled well. A 50 nm wide and 50 nm thick silicon nanowire has been formed using this method

Fabrication and electrical characterization of polyaniline-silicon heterojunction for gamma radiation dosimetry application

International Nuclear Information System (INIS)

Laranjeira, Jane Maria Goncalves

2004-08-01

In this work a technique has been developed to fabricate high quality polyaniline-silicon heterojunction diodes for use as gas and/or ionizing radiation sensors. Polyaniline thin films (40 nm thick) produced by spin-coating on silicon substrates, were the active part of the junction structure. The devices presented excellent reproducibility of their electrical characteristics with high rectification ratio, 60,000 at ±1.0 V, and typical reverse current at - 1.0 V of 3 nA at 295 K. A G/I x G plot has been used to analyze the current-voltage characteristics, yielding typical series resistance of 4 kΩ ± 5% and ideality factor in a range of 1,9 ± 0.5%. The heterojunction diode presents high sensitivity to gamma radiation in the dose range of 3 x 10 -2 to 7 kGy with a linear response in the forward and reverse bias. The excellent electrical characteristics together with the linear response with the dose, strongly suggest the application of this device for spectrometry or dosimetry of high doses of gamma radiation. These devices presented high sensitivity to gas moistures such as ammonia, nitric acid and trichloroethylene. In both cases the sensitivity was observed through shifts of the current-voltage curves, which can be easily monitored to provide a calibration curve of the sensor either as a radiation dosimeter or as a gas sensor for use in applications for gas monitoring or radiation dosimetry. Several aspects of the reliability physics of silicon-polyaniline heterojunction, such as degradation effects induced by local heating, charge trapping and temperature changes, have been discussed. These results further confirm the quality of the devices electrical characteristics and their suitability for radiation and gas sensors applications. Another interesting results presented in this work was the use of polyemeraldine nanofilms (thickness in the range 30-50 nm) deposited by 'spin coating' on glass substrates as an optical dosimeter for gamma radiation based on the

Fabrication of quantum-dot devices in graphene

Directory of Open Access Journals (Sweden)

Satoshi Moriyama, Yoshifumi Morita, Eiichiro Watanabe, Daiju Tsuya, Shinya Uji, Maki Shimizu and Koji Ishibashi

2010-01-01

Full Text Available We describe our recent experimental results on the fabrication of quantum-dot devices in a graphene-based two-dimensional system. Graphene samples were prepared by micromechanical cleavage of graphite crystals on a SiO2/Si substrate. We performed micro-Raman spectroscopy measurements to determine the number of layers of graphene flakes during the device fabrication process. By applying a nanofabrication process to the identified graphene flakes, we prepared a double-quantum-dot device structure comprising two lateral quantum dots coupled in series. Measurements of low-temperature electrical transport show the device to be a series-coupled double-dot system with varied interdot tunnel coupling, the strength of which changes continuously and non-monotonically as a function of gate voltage.

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

Science.gov (United States)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

Fabrication and study of sol-gel ZnO films for use in Si-based heterojunction photovoltaic devices

Directory of Open Access Journals (Sweden)

Daniya Mukhamedshina

2017-12-01

Full Text Available This paper considers the use of zinc oxide thin films prepared via the sol-gel route as an n-type layer in heterojunction ZnO/Si solar cells. The ZnO films were prepared via a simple spin-coating technique using zinc acetate dihydrate as a zinc precursor, isopropanol as a solvent and monoethanolamine as a stabilizing agent. Optical, structural and morphological properties of ZnO were investigated for thin films grown from sol-gel solutions with different concentrations both on glass and silicon substrates. As such, a distribution of crystallite sizes and surface topology parameters corresponding to various zinc acetate dihydrate concentrations were obtained to elucidate optimal film deposition conditions. Correlation between thin film morphology and structural characteristics of ZnO thin films was made based on atomic-force microscopy studies. Finally, our results on fabrication, characterization and simulation of ZnO/Si heterojunctions for use as photovoltaic devices are presented. Although noticeable rectifying and photovoltaic properties were observed for Al/Si/ZnO/Ti/Au devices, there appears to exist a considerable room for device improvement with simulation studies suggesting that efficiencies of the order of 24% may be obtained for devices with optimal silicon wafer passivation, i.e. with lifetimes of the order of 1000 μs.

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

Science.gov (United States)

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Crystalline Silicon Interconnected Strips (XIS). Introduction to a New, Integrated Device and Module Concept

Energy Technology Data Exchange (ETDEWEB)

Van Roosmalen, J.; Bronsveld, P.; Mewe, A.; Janssen, G.; Stodolny, M.; Cobussen-Pool, E.; Bennett, I.; Weeber, A.; Geerligs, B. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG, Petten (Netherlands)

2012-06-15

A new device concept for high efficiency, low cost, wafer based silicon solar cells is introduced. To significantly lower the costs of Si photovoltaics, high efficiencies and large reductions of metals and silicon costs are required. To enable this, the device architecture was adapted into low current devices by applying thin silicon strips, to which a special high efficiency back-contact heterojunction cell design was applied. Standard industrial production processes can be used for our fully integrated cell and module design, with a cost reduction potential below 0.5 euro/Wp. First devices have been realized demonstrating the principle of a series connected back contact hybrid silicon heterojunction module concept.

Site-controlled fabrication of silicon nanotips by indentation-induced selective etching

Science.gov (United States)

Jin, Chenning; Yu, Bingjun; Liu, Xiaoxiao; Xiao, Chen; Wang, Hongbo; Jiang, Shulan; Wu, Jiang; Liu, Huiyun; Qian, Linmao

2017-12-01

In the present study, the indentation-induced selective etching approach is proposed to fabricate site-controlled pyramidal nanotips on Si(100) surface. Without any masks, the site-controlled nanofabrication can be realized by nanoindentation and post etching in potassium hydroxide (KOH) solution. The effect of indentation force and etching time on the formation of pyramidal nanotips was investigated. It is found that the height and radius of the pyramidal nanotips increase with the indentation force or etching time, while long-time etching can lead to the collapse of the tips. The formation of pyramidal tips is ascribed to the anisotropic etching of silicon and etching stop of (111) crystal planes in KOH aqueous solution. The capability of this fabrication method was further demonstrated by producing various tip arrays on silicon surface by selective etching of the site-controlled indent patterns, and the maximum height difference of these tips is less than 10 nm. The indentation-induced selective etching provides a new strategy to fabricate well site-controlled tip arrays for multi-probe SPM system, Si nanostructure-based sensors and high-quality information storage.

Fabrication and characterization of reaction bonded silicon carbide/carbon nanotube composites

International Nuclear Information System (INIS)

Thostenson, Erik T; Karandikar, Prashant G; Chou, T.-W.

2005-01-01

Carbon nanotubes have generated considerable excitement in the scientific and engineering communities because of their exceptional mechanical and physical properties observed at the nanoscale. Carbon nanotubes possess exceptionally high stiffness and strength combined with high electrical and thermal conductivities. These novel material properties have stimulated considerable research in the development of nanotube-reinforced composites (Thostenson et al 2001 Compos. Sci. Technol. 61 1899, Thostenson et al 2005 Compos. Sci. Technol. 65 491). In this research, novel reaction bonded silicon carbide nanocomposites were fabricated using melt infiltration of silicon. A series of multi-walled carbon nanotube-reinforced ceramic matrix composites (NT-CMCs) were fabricated and the structure and properties were characterized. Here we show that carbon nanotubes are present in the as-fabricated NT-CMCs after reaction bonding at temperatures above 1400 deg. C. Characterization results reveal that a very small volume content of carbon nanotubes, as low as 0.3 volume %, results in a 75% reduction in electrical resistivity of the ceramic composites. A 96% decrease in electrical resistivity was observed for the ceramics with the highest nanotube volume fraction of 2.1%

Aligned carbon nanotubes. Physics, concepts, fabrication and devices

Energy Technology Data Exchange (ETDEWEB)

Ren, Zhifeng; Lan, Yucheng [Boston College, Chestnut Hill, MA (United States). Dept. of Physics; Wang, Yang [South China Normal Univ. Guangzhou (China). Inst. for Advanced Materials

2013-07-01

This book gives a survey of the physics and fabrication of carbon nanotubes and their applications in optics, electronics, chemistry and biotechnology. It focuses on the structural characterization of various carbon nanotubes, fabrication of vertically or parallel aligned carbon nanotubes on substrates or in composites, physical properties for their alignment, and applications of aligned carbon nanotubes in field emission, optical antennas, light transmission, solar cells, chemical devices, bio-devices, and many others. Major fabrication methods are illustrated in detail, particularly the most widely used PECVD growth technique on which various device integration schemes are based, followed by applications such as electrical interconnects, nanodiodes, optical antennas, and nanocoax solar cells, whereas current limitations and challenges are also be discussed to lay the foundation for future developments.

Nanostructured Porous Silicon Photonic Crystal for Applications in the Infrared

Directory of Open Access Journals (Sweden)

G. Recio-Sánchez

2012-01-01

Full Text Available In the last decades great interest has been devoted to photonic crystals aiming at the creation of novel devices which can control light propagation. In the present work, two-dimensional (2D and three-dimensional (3D devices based on nanostructured porous silicon have been fabricated. 2D devices consist of a square mesh of 2 μm wide porous silicon veins, leaving 5×5 μm square air holes. 3D structures share the same design although multilayer porous silicon veins are used instead, providing an additional degree of modulation. These devices are fabricated from porous silicon single layers (for 2D structures or multilayers (for 3D structures, opening air holes in them by means of 1 KeV argon ion bombardment through the appropriate copper grids. For 2D structures, a complete photonic band gap for TE polarization is found in the thermal infrared range. For 3D structures, there are no complete band gaps, although several new partial gaps do exist in different high-symmetry directions. The simulation results suggest that these structures are very promising candidates for the development of low-cost photonic devices for their use in the thermal infrared range.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

Science.gov (United States)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

A Fabrication Technique for Nano-gap Electrodes by Atomic Force Microscopy Nano lithography

International Nuclear Information System (INIS)

Jalal Rouhi; Shahrom Mahmud; Hutagalung, S.D.; Kakooei, S.

2011-01-01

A simple technique is introduced for fabrication of nano-gap electrodes by using nano-oxidation atomic force microscopy (AFM) lithography with a Cr/ Pt coated silicon tip. AFM local anodic oxidation was performed on silicon-on-insulator (SOI) surfaces by optimization of desired conditions to control process in contact mode. Silicon electrodes with gaps of sub 31 nm were fabricated by nano-oxidation method. This technique which is simple, controllable, inexpensive and fast is capable of fabricating nano-gap structures. The current-voltage measurements (I-V) of the electrodes demonstrated very good insulating characteristics. The results show that silicon electrodes have a great potential for fabrication of single molecule transistors (SMT), single electron transistors (SET) and the other nano electronic devices. (author)

Development of an oxidized porous silicon vacuum microtriode

Energy Technology Data Exchange (ETDEWEB)

Smith, II, Don Deewayne [Texas A & M Univ., College Station, TX (United States)

1994-05-01

In order to realize a high-power microwave amplifier design known as a gigatron, a gated field emission array must be developed that can deliver a high-intensity electron beam at gigahertz frequencies. No existing field emission device meets the requirements for a gigatron cathode. In the present work, a porous silicon-based approach is evaluated. The use of porous silicon reduces the size of a single emitter to the nanometer scale, and a true two-dimensional array geometry can be approached. A wide number of applications for such a device exist in various disciplines. Oxidized porous silicon vacuum diodes were first developed in 1990. No systematic study had been done to characterize the performance of these devices as a function of the process parameters. The author has done the first such study, fabricating diodes from p<100>, p<111>, and n<100> silicon substrates. Anodization current densities from 11 mA/cm² to 151 mA/cm² were used, and Fowler-Nordheim behavior was observed in over 80% of the samples. In order to effectively adapt this technology to mainstream vacuum microelectronic applications, a means of creating a gated triodic structure must be found. No previous attempts had successfully yielded such a device. The author has succeeded in utilizing a novel metallization method to fabricate the first operational oxidized porous silicon vacuum microtriodes, and results are encouraging.

Fabrication of combined-scale nano- and microfluidic polymer systems using a multilevel dry etching, electroplating and molding process

DEFF Research Database (Denmark)

Tanzi, Simone; Østergaard, Peter Friis; Matteucci, Marco

2012-01-01

Microfabricated single-cell capture and DNA stretching devices have been produced by injection molding. The fabrication scheme employed deep reactive ion etching in a silicon substrate, electroplating in nickel and molding in cyclic olefin polymer. This work proposes technical solutions to fabric......Microfabricated single-cell capture and DNA stretching devices have been produced by injection molding. The fabrication scheme employed deep reactive ion etching in a silicon substrate, electroplating in nickel and molding in cyclic olefin polymer. This work proposes technical solutions...

Customizable in situ TEM devices fabricated in freestanding membranes by focused ion beam milling

DEFF Research Database (Denmark)

Lei, Anders; Petersen, Dirch Hjorth; Booth, Tim

2010-01-01

crystalline silicon extending over the edge of a pre-fabricated silicon microchip. Four-terminal resistance measurements of FIB-defined nanowires showed at least two orders of magnitude increase in resistivity compared to bulk. We show that the initial high resistance is due to amorphization of silicon...

Self-consistent modeling of amorphous silicon devices

International Nuclear Information System (INIS)

Hack, M.

1987-01-01

The authors developed a computer model to describe the steady-state behaviour of a range of amorphous silicon devices. It is based on the complete set of transport equations and takes into account the important role played by the continuous distribution of localized states in the mobility gap of amorphous silicon. Using one set of parameters they have been able to self-consistently simulate the current-voltage characteristics of p-i-n (or n-i-p) solar cells under illumination, the dark behaviour of field-effect transistors, p-i-n diodes and n-i-n diodes in both the ohmic and space charge limited regimes. This model also describes the steady-state photoconductivity of amorphous silicon, in particular, its dependence on temperature, doping and illumination intensity

Low-Cost, Silicon Carbide Replication Technique for LWIR Mirror Fabrication, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — SSG proposes an innovative optical manufacturing approach that will enable the low-cost fabrication of lightweighted, Long Wave Infrared (LWIR) Silicon Carbide (SiC)...

Ultra-thin alumina and silicon nitride MEMS fabricated membranes for the electron multiplication

Science.gov (United States)

Prodanović, V.; Chan, H. W.; Graaf, H. V. D.; Sarro, P. M.

2018-04-01

In this paper we demonstrate the fabrication of large arrays of ultrathin freestanding membranes (tynodes) for application in a timed photon counter (TiPC), a novel photomultiplier for single electron detection. Low pressure chemical vapour deposited silicon nitride (Si x N y ) and atomic layer deposited alumina (Al2O3) with thicknesses down to only 5 nm are employed for the membrane fabrication. Detailed characterization of structural, mechanical and chemical properties of the utilized films is carried out for different process conditions and thicknesses. Furthermore, the performance of the tynodes is investigated in terms of secondary electron emission, a fundamental attribute that determines their applicability in TiPC. Studied features and presented fabrication methods may be of interest for other MEMS application of alumina and silicon nitride as well, in particular where strong ultra-thin membranes are required.

SOI silicon on glass for optical MEMS

DEFF Research Database (Denmark)

Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

2003-01-01

and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

Electroless porous silicon formation applied to fabrication of boron-silica-glass cantilevers

DEFF Research Database (Denmark)

Teva, Jordi; Davis, Zachary James; Hansen, Ole

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5-1 mm3) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases...... where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing...... for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH...

Neuron Stimulation Device Integrated with Silicon Nanowire-Based Photodetection Circuit on a Flexible Substrate

Directory of Open Access Journals (Sweden)

Suk Won Jung

2016-12-01

Full Text Available This paper proposes a neural stimulation device integrated with a silicon nanowire (SiNW-based photodetection circuit for the activation of neurons with light. The proposed device is comprised of a voltage divider and a current driver in which SiNWs are used as photodetector and field-effect transistors; it has the functions of detecting light, generating a stimulation signal in proportion to the light intensity, and transmitting the signal to a micro electrode. To show the applicability of the proposed neural stimulation device as a high-resolution retinal prosthesis system, a high-density neural stimulation device with a unit cell size of 110 × 110 μ m and a resolution of 32 × 32 was fabricated on a flexible film with a thickness of approximately 50 μm. Its effectiveness as a retinal stimulation device was then evaluated using a unit cell in an in vitro animal experiment involving the retinal tissue of retinal Degeneration 1 (rd1 mice. Experiments wherein stimulation pulses were applied to the retinal tissues successfully demonstrate that the number of spikes in neural response signals increases in proportion to light intensity.

High-gain bipolar detector on float-zone silicon

Science.gov (United States)

Han, D. J.; Batignani, G.; Del Guerra, A.; Dalla Betta, G.-F.; Boscardin, M.; Bosisio, L.; Giorgi, M.; Forti, F.

2003-10-01

Since the float-zone (FZ) silicon has lower contaminations and longer minority-carrier lifetime than those in Czochralski silicon and other semiconductor materials, it has potential advantages to fabricate bipolar detectors on the high-purity FZ silicon substrate to achieve a high gain at ultra-low-signal levels. The authors present preliminary experimental results on a bipolar detector fabricated on an unusual high-purity FZ silicon substrate. A backside gettering layer of phosphorus-doped polysilicon was employed to preserve the long carrier lifetime of the high-purity FZ silicon. The device has been investigated in the detection of a continuous flux of X-ray and infrared light. The bipolar detector with a circular emitter of 2 mm diameter has demonstrated high gains up to 3820 for 22 keV X-ray from a 1 mCi Cd radioactive source (the X-ray photon flux, received by the detector is estimated to be ˜7.77×10 4/s). High gain up to 4400 for 0.17 nW light with a wavelength of 0.83 μm has been observed for the same device.

High-gain bipolar detector on float-zone silicon

International Nuclear Information System (INIS)

Han, D.J.; Batignani, G.; Guerra, A.D.A. Del; Dalla Betta, G.-F.; Boscardin, M.; Bosisio, L.; Giorgi, M.; Forti, F.

2003-01-01

Since the float-zone (FZ) silicon has lower contaminations and longer minority-carrier lifetime than those in Czochralski silicon and other semiconductor materials, it has potential advantages to fabricate bipolar detectors on the high-purity FZ silicon substrate to achieve a high gain at ultra-low-signal levels. The authors present preliminary experimental results on a bipolar detector fabricated on an unusual high-purity FZ silicon substrate. A backside gettering layer of phosphorus-doped polysilicon was employed to preserve the long carrier lifetime of the high-purity FZ silicon. The device has been investigated in the detection of a continuous flux of X-ray and infrared light. The bipolar detector with a circular emitter of 2 mm diameter has demonstrated high gains up to 3820 for 22 keV X-ray from a 1 mCi Cd radioactive source (the X-ray photon flux, received by the detector is estimated to be ∼7.77x10 4 /s). High gain up to 4400 for 0.17 nW light with a wavelength of 0.83 μm has been observed for the same device

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

International Nuclear Information System (INIS)

Destefanis, V; Huguenin, J L; Samson, M P; Morand, Y; Arvet, C; Monfray, S; Skotnicki, T; Hartmann, J M; Delaye, V; Boulitreau, P; Brianceau, P; Gautier, P

2010-01-01

The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea; Paviet-Salomon, Bertrand; Jeangros, Quentin; Haschke, Jan; Christmann, Gabriel; Barraud, Loris; Descoeudres, Antoine; Seif, Johannes Peter; Nicolay, Sylvain; Despeisse, Matthieu; De Wolf, Stefaan; Ballif, Christophe

2017-01-01

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea

2017-04-24

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Silicon-based metallic micro grid for electron field emission

International Nuclear Information System (INIS)

Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

2012-01-01

A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

Magnet-assisted device-level alignment for the fabrication of membrane-sandwiched polydimethylsiloxane microfluidic devices

International Nuclear Information System (INIS)

Lu, J-C; Liao, W-H; Tung, Y-C

2012-01-01

Polydimethylsiloxane (PDMS) microfluidic device is one of the most essential techniques that advance microfluidics research in recent decades. PDMS is broadly exploited to construct microfluidic devices due to its unique and advantageous material properties. To realize more functionalities, PDMS microfluidic devices with multi-layer architectures, especially those with sandwiched membranes, have been developed for various applications. However, existing alignment methods for device fabrication are mainly based on manual observations, which are time consuming, inaccurate and inconsistent. This paper develops a magnet-assisted alignment method to enhance device-level alignment accuracy and precision without complicated fabrication processes. In the developed alignment method, magnets are embedded into PDMS layers at the corners of the device. The paired magnets are arranged in symmetric positions at each PDMS layer, and the magnetic attraction force automatically pulls the PDMS layers into the aligned position during assembly. This paper also applies the method to construct a practical microfluidic device, a tunable chaotic micromixer. The results demonstrate the successful operation of the device without failure, which suggests the accurate alignment and reliable bonding achieved by the method. Consequently, the fabrication method developed in this paper is promising to be exploited to construct various membrane-sandwiched PDMS microfluidic devices with more integrated functionalities to advance microfluidics research. (paper)

Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

Directory of Open Access Journals (Sweden)

Di Di

2014-01-01

Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

Effects of radiation on MOS structures and silicon devices

International Nuclear Information System (INIS)

Braeunig, D.; Fahrner, W.

1983-02-01

A comprehensive view of radiation effects on MOS structures and silicon devices is given. In the introduction, the interaction of radiation with semiconductor material is presented. In the next section, the electrical degradation of semiconductor devices due to this interaction is discussed. The commonly used hardening techniques are shown. The last section deals with testing of radiation hardness of devices. (orig.) [de

Fabrication of disposable topographic silicon oxide from sawtoothed patterns: control of arrays of gold nanoparticles.

Science.gov (United States)

Cho, Heesook; Yoo, Hana; Park, Soojin

2010-05-18

Disposable topographic silicon oxide patterns were fabricated from polymeric replicas of sawtoothed glass surfaces, spin-coating of poly(dimethylsiloxane) (PDMS) thin films, and thermal annealing at certain temperature and followed by oxygen plasma treatment of the thin PDMS layer. A simple imprinting process was used to fabricate the replicated PDMS and PS patterns from sawtoothed glass surfaces. Next, thin layers of PDMS films having different thicknesses were spin-coated onto the sawtoothed PS surfaces and annealed at 60 degrees C to be drawn the PDMS into the valley of the sawtoothed PS surfaces, followed by oxygen plasma treatment to fabricate topographic silicon oxide patterns. By control of the thickness of PDMS layers, silicon oxide patterns having various line widths were fabricated. The silicon oxide topographic patterns were used to direct the self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) block copolymer thin films via solvent annealing process. A highly ordered PS-b-P2VP micellar structure was used to let gold precursor complex with P2VP chains, and followed by oxygen plasma treatment. When the PS-b-P2VP thin films containing gold salts were exposed to oxygen plasma environments, gold salts were reduced to pure gold nanoparticles without changing high degree of lateral order, while polymers were completely degraded. As the width of trough and crest in topographic patterns increases, the number of gold arrays and size of gold nanoparticles are tuned. In the final step, the silicon oxide topographic patterns were selectively removed by wet etching process without changing the arrays of gold nanoparticles.

Epitaxial III-V nanowires on silicon for vertical devices

NARCIS (Netherlands)

Bakkers, E.P.A.M.; Borgström, M.T.; Einden, Van Den W.; Weert, van M.H.M.; Helman, A.; Verheijen, M.A.

2006-01-01

We show the epitaxial integration of III-V semiconductor nanowires with silicon technology. The wires are grown by the Vapor-Liquid-Solid (VLS) mechanism with laser ablation as well as metal organic vapor phase epitaxy. The VLS growth enables the fabrication of complex axial and radial

Noise and degradation of amorphous silicon devices

NARCIS (Netherlands)

Bakker, J.P.R.

2003-01-01

Electrical noise measurements are reported on two devices of the disordered semiconductor hydrogenated amorphous silicon (a-Si:H). The material is applied in sandwich structures and in thin-film transistors (TFTs). In a sandwich configuration of an intrinsic layer and two thin doped layers, the

Silicide/Silicon Heterointerfaces, Reaction Kinetics and Ultra-short Channel Devices

Science.gov (United States)

Tang, Wei

Nickel silicide is one of the electrical contact materials widely used on very large scale integration (VLSI) of Si devices in microelectronic industry. This is because the silicide/silicon interface can be formed in a highly controlled manner to ensure reproducibility of optimal structural and electrical properties of the metal-Si contacts. These advantages can be inherited to Si nanowire (NW) field-effect transistors (FET) device. Due to the technological importance of nickel silicides, fundamental materials science of nickel silicides formation (Ni-Si reaction), especially in nanoscale, has raised wide interest and stimulate new insights and understandings. In this dissertation, in-situ transmission electron microscopy (TEM) in combination with FET device characterization will be demonstrated as useful tools in nano-device fabrication as well as in gaining insights into the process of nickel silicide formation. The shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) has been demonstrated by controlled reaction with Ni leads on an in-situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 ºC. NiSi2 is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (microA/microm) and a maximum transconductance of 430 (microS/microm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of (17 nm -- 3.6 microm). Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs

Comparison of Six Different Silicones In Vitro for Application as Glaucoma Drainage Device

Directory of Open Access Journals (Sweden)

Claudia Windhövel

2018-02-01

Full Text Available Silicones are widely used in medical applications. In ophthalmology, glaucoma drainage devices are utilized if conservative therapies are not applicable or have failed. Long-term success of these devices is limited by failure to control intraocular pressure due to fibrous encapsulation. Therefore, different medical approved silicones were tested in vitro for cell adhesion, cell proliferation and viability of human Sclera (hSF and human Tenon fibroblasts (hTF. The silicones were analysed also depending on the sample preparation according to the manufacturer’s instructions. The surface quality was characterized with environmental scanning electron microscope (ESEM and water contact angle measurements. All silicones showed homogeneous smooth and hydrophobic surfaces. Cell adhesion was significantly reduced on all silicones compared to the negative control. Proliferation index and cell viability were not influenced much. For development of a new glaucoma drainage device, the silicones Silbione LSR 4330 and Silbione LSR 4350, in this study, with low cell counts for hTF and low proliferation indices for hSF, and silicone Silastic MDX4-4210, with low cell counts for hSF and low proliferation indices for hTF, have shown the best results in vitro. Due to the high cell adhesion shown on Silicone LSR 40, 40,026, this material is unsuitable.

Porous silicon photonic devices using pulsed anodic etching of lightly doped silicon

International Nuclear Information System (INIS)

Escorcia-Garcia, J; Sarracino MartInez, O; Agarwal, V; Gracia-Jimenez, J M

2009-01-01

The fabrication of porous silicon photonic structures using lightly doped, p-type, silicon wafers (resistivity: 14-22 Ω cm) by pulsed anodic etching is reported. The optical properties have been found to be strongly dependent on the duty cycle and frequency of the applied current. All the interfaces of the single layered samples were digitally analysed by calculating the mean interface roughness (R m ). The interface roughness was found to be maximum for the sample with direct current. The use of a duty cycle above 50%, in a certain range of frequencies, is found to reduce the interface roughness. The optical properties of some microcavities and rugate filters are investigated from the optimized parameters of the duty cycle and frequency, using the current densities of 10, 90 and 150 mA cm -2 .

Additive advantage in characteristics of MIMCAPs on flexible silicon (100) fabric with release-first process

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show

Effect of fabrication parameters on morphological and optical properties of highly doped p-porous silicon

Energy Technology Data Exchange (ETDEWEB)

Zare, Maryam, E-mail: mar.zare@gmail.com [Young Researchers Club, Khomeinishahr Branch, Islamic Azad University, Khomeinishahr (Iran, Islamic Republic of); Shokrollahi, Abbas [Young Researchers Club, Khomeinishahr Branch, Islamic Azad University, Khomeinishahr (Iran, Islamic Republic of); Seraji, Faramarz E. [Optical Communication Group, Iran Telecom Research Center, Tehran (Iran, Islamic Republic of)

2011-09-01

Porous silicon (PS) layers were fabricated by anodization of low resistive (highly doped) p-type silicon in HF/ethanol solution, by varying current density, etching time and HF concentration. Atomic force microscopy (AFM) and field emission scanning electron microscope (FESEM) analyses were used to investigate the physical properties and reflection spectrum was used to investigate the optical behavior of PS layers in different fabrication conditions. Vertically aligned mesoporous morphology is observed in fabricated films and with HF concentration higher than 20%. The dependence of porosity, layer thickness and rms roughness of the PS layer on current density, etching time and composition of electrolyte is also observed in obtained results. Correlation between reflectivity and fabrication parameters was also explored. Thermal oxidation was performed on some mesoporous layers that resulted in changes of surface roughness, mean height and reflectivity of the layers.

Polarization-independent all-silicon dielectric metasurfaces in the terahertz regime

KAUST Repository

Zhang, Huifang

2017-12-11

Dielectric metasurfaces have achieved great success in realizing high-efficiency wavefront control in the optical and infrared ranges. Here, we experimentally demonstrate several efficient, polarization-independent, all-silicon dielectric metasurfaces in the terahertz regime. The metasurfaces are composed of cylindrical silicon pillars on a silicon substrate, which can be easily fabricated using etching technology for semiconductors. By locally tailoring the diameter of the pillars, full control over abrupt phase changes can be achieved. To show the controlling ability of the metasurfaces, an anomalous deflector, three Bessel beam generators, and three vortex beam generators are fabricated and characterized. We also show that the proposed metasurfaces can be easily combined to form composite devices with extended functionalities. The proposed controlling method has promising applications in developing low-loss, ultra-compact spatial terahertz modulation devices. (C) 2017 Chinese Laser Press

Polarization-independent all-silicon dielectric metasurfaces in the terahertz regime

KAUST Repository

Zhang, Huifang; Zhang, Xueqian; Xu, Quan; Wang, Qiu; Xu, Yuehong; Wei, Minggui; Li, Yanfeng; Gu, Jianqiang; Tian, Zhen; Ouyang, Chunmei; Zhang, Xixiang; Hu, Cong; Han, Jiaguang; Zhang, Weili

2017-01-01

Dielectric metasurfaces have achieved great success in realizing high-efficiency wavefront control in the optical and infrared ranges. Here, we experimentally demonstrate several efficient, polarization-independent, all-silicon dielectric metasurfaces in the terahertz regime. The metasurfaces are composed of cylindrical silicon pillars on a silicon substrate, which can be easily fabricated using etching technology for semiconductors. By locally tailoring the diameter of the pillars, full control over abrupt phase changes can be achieved. To show the controlling ability of the metasurfaces, an anomalous deflector, three Bessel beam generators, and three vortex beam generators are fabricated and characterized. We also show that the proposed metasurfaces can be easily combined to form composite devices with extended functionalities. The proposed controlling method has promising applications in developing low-loss, ultra-compact spatial terahertz modulation devices. (C) 2017 Chinese Laser Press

The fabrication of highly ordered block copolymer micellar arrays: control of the separation distances of silicon oxide dots

Science.gov (United States)

Yoo, Hana; Park, Soojin

2010-06-01

We demonstrate the fabrication of highly ordered silicon oxide dotted arrays prepared from polydimethylsiloxane (PDMS) filled nanoporous block copolymer (BCP) films and the preparation of nanoporous, flexible Teflon or polyimide films. Polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) films were annealed in toluene vapor to enhance the lateral order of micellar arrays and were subsequently immersed in alcohol to produce nano-sized pores, which can be used as templates for filling a thin layer of PDMS. When a thin layer of PDMS was spin-coated onto nanoporous BCP films and thermally annealed at a certain temperature, the PDMS was drawn into the pores by capillary action. PDMS filled BCP templates were exposed to oxygen plasma environments in order to fabricate silicon oxide dotted arrays. By addition of PS homopolymer to PS-b-P2VP copolymer, the separation distances of micellar arrays were tuned. As-prepared silicon oxide dotted arrays were used as a hard master for fabricating nanoporous Teflon or polyimide films by spin-coating polymer precursor solutions onto silicon patterns and peeling off. This simple process enables us to fabricate highly ordered nanoporous BCP templates, silicon oxide dots, and flexible nanoporous polymer patterns with feature size of sub-20 nm over 5 cm × 5 cm.

The fabrication of highly ordered block copolymer micellar arrays: control of the separation distances of silicon oxide dots

Energy Technology Data Exchange (ETDEWEB)

Yoo, Hana; Park, Soojin, E-mail: spark@unist.ac.kr [Interdisciplinary School of Green Energy, Ulsan National Institute of Science and Technology, Banyeon-ri 100, Ulsan 689-798 (Korea, Republic of)

2010-06-18

We demonstrate the fabrication of highly ordered silicon oxide dotted arrays prepared from polydimethylsiloxane (PDMS) filled nanoporous block copolymer (BCP) films and the preparation of nanoporous, flexible Teflon or polyimide films. Polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) films were annealed in toluene vapor to enhance the lateral order of micellar arrays and were subsequently immersed in alcohol to produce nano-sized pores, which can be used as templates for filling a thin layer of PDMS. When a thin layer of PDMS was spin-coated onto nanoporous BCP films and thermally annealed at a certain temperature, the PDMS was drawn into the pores by capillary action. PDMS filled BCP templates were exposed to oxygen plasma environments in order to fabricate silicon oxide dotted arrays. By addition of PS homopolymer to PS-b-P2VP copolymer, the separation distances of micellar arrays were tuned. As-prepared silicon oxide dotted arrays were used as a hard master for fabricating nanoporous Teflon or polyimide films by spin-coating polymer precursor solutions onto silicon patterns and peeling off. This simple process enables us to fabricate highly ordered nanoporous BCP templates, silicon oxide dots, and flexible nanoporous polymer patterns with feature size of sub-20 nm over 5 cm x 5 cm.

High-efficiency power transfer for silicon-based photonic devices

Science.gov (United States)

Son, Gyeongho; Yu, Kyoungsik

2018-02-01

We demonstrate an efficient coupling of guided light of 1550 nm from a standard single-mode optical fiber to a silicon waveguide using the finite-difference time-domain method and propose a fabrication method of tapered optical fibers for efficient power transfer to silicon-based photonic integrated circuits. Adiabatically-varying fiber core diameters with a small tapering angle can be obtained using the tube etching method with hydrofluoric acid and standard single-mode fibers covered by plastic jackets. The optical power transmission of the fundamental HE11 and TE-like modes between the fiber tapers and the inversely-tapered silicon waveguides was calculated with the finite-difference time-domain method to be more than 99% at a wavelength of 1550 nm. The proposed method for adiabatic fiber tapering can be applied in quantum optics, silicon-based photonic integrated circuits, and nanophotonics. Furthermore, efficient coupling within the telecommunication C-band is a promising approach for quantum networks in the future.

Design and fabrication of ultrathin silicon-nitride membranes for use in UV-visible airgap-based MEMS optical filters

International Nuclear Information System (INIS)

Ghaderi, Mohammadamir; Wolffenbuttel, Reinoud F.

2016-01-01

MEMS-based airgap optical filters are composed of quarter-wave thick high-index dielectric membranes that are separated by airgaps. The main challenge in the fabrication of these filters is the intertwined optical and mechanical requirements. The thickness of the layers decreases with design wavelength, which makes the optical performance in the UV more susceptible to fabrication tolerances, such as thickness and composition of the deposited layers, while the ability to sustain a certain level of residual stress by the structural strength becomes more critical. Silicon-nitride has a comparatively high Young's modulus and good optical properties, which makes it a suitable candidate as the membrane material. However, both the mechanical and optical properties in a silicon-nitride film strongly depend on the specifics of the deposition process. A design trade-off is required between the mechanical strength and the index of refraction, by tuning the silicon content in the silicon-nitride film. However, also the benefit of a high index of refraction in a silicon-rich film should be weighed against the increased UV optical absorption. This work presents the design, fabrication, and preliminary characterization of one and three quarter-wave thick silicon-nitride membranes with a one-quarter airgap and designed to give a spectral reflectance at 400 nm. The PECVD silicon-nitride layers were initially characterized, and the data was used for the optical and mechanical design of the airgap filters. A CMOS compatible process based on polysilicon sacrificial layers was used for the fabrication of the membranes. Optical characterization results are presented. (paper)

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Fabrication and characterization of an integrated ionic device from suspended polypyrrole and alamethicin-reconstituted lipid bilayer membranes

International Nuclear Information System (INIS)

Northcutt, Robert; Sundaresan, Vishnu-Baba

2012-01-01

Conducting polymers are electroactive materials that undergo conformal relaxation of the polymer backbone in the presence of an electrical field through ion exchange with solid or aqueous electrolytes. This conformal relaxation and the associated morphological changes make conducting polymers highly suitable for actuation and sensing applications. Among smart materials, bioderived active materials also use ion transport for sensing and actuation functions via selective ion transport. The transporter proteins extracted from biological cell membranes and reconstituted into a bilayer lipid membrane in bioderived active materials regulate ion transport for engineering functions. The protein transporter reconstituted in the bilayer lipid membrane is referred to as the bioderived membrane and serves as the active component in bioderived active materials. Inspired by the similarities in the physics of transduction in conducting polymers and bioderived active materials, an integrated ionic device is formed from the bioderived membrane and the conducting polymer membrane. This ionic device is fabricated into a laminated thin-film membrane and a common ion that can be processed by the bioderived and the conducting polymer membranes couple the ionic function of these two membranes. An integrated ionic device, fabricated from polypyrrole (PPy) doped with sodium dodecylbenzenesulfonate (NaDBS) and an alamethicin-reconstituted DPhPC bilayer lipid membrane, is presented in this paper. A voltage-gated sodium current regulates the electrochemical response in the PPy(DBS) layer. The integrated device is fabricated on silicon-based substrates through microfabrication, electropolymerization, and vesicle fusion, and ionic activity is characterized through electrochemical measurements. (paper)

Silicon fiber with p-n junction

International Nuclear Information System (INIS)

Homa, D.; Cito, A.; Pickrell, G.; Hill, C.; Scott, B.

2014-01-01

In this study, we fabricated a p-n junction in a fiber with a phosphorous doped silicon core and fused silica cladding. The fibers were fabricated via a hybrid process of the core-suction and melt-draw techniques and maintained overall diameters ranging from 200 to 900 μm and core diameters of 20–800 μm. The p-n junction was formed by doping the fiber with boron and confirmed via the current-voltage characteristic. The demonstration of a p-n junction in a melt-drawn silicon core fiber paves the way for the seamless integration of optical and electronic devices in fibers.

Fabrication of double-dot single-electron transistor in silicon nanowire

International Nuclear Information System (INIS)

Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

2010-01-01

We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

Device Fabrication and Probing of Discrete Carbon Nanostructures

KAUST Repository

Batra, Nitin M

2015-01-01

Device fabrication on multi walled carbon nanotubes (MWCNTs) using electrical beam lithography (EBL), electron beam induced deposition (EBID), ion beam induced deposition (IBID) methods was carried out, followed by device electrical characterization

Structural and optical properties of silicon rich oxide films in graded-stoichiometric multilayers for optoelectronic devices

Energy Technology Data Exchange (ETDEWEB)

Palacios-Huerta, L.; Aceves-Mijares, M. [Electronics Department, INAOE, Apdo. 51, Puebla, Pue. 72000, México (Mexico); Cabañas-Tay, S. A.; Cardona-Castro, M. A.; Morales-Sánchez, A., E-mail: alfredo.morales@cimav.edu.mx [Centro de Investigación en Materiales Avanzados S.C., Unidad Monterrey-PIIT, Apodaca, NL 66628, México (Mexico); Domínguez-Horna, C. [Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC), Bellaterra 08193, Barcelona (Spain)

2016-07-18

Silicon nanocrystals (Si-ncs) are excellent candidates for the development of optoelectronic devices. Nevertheless, different strategies are still necessary to enhance their photo and electroluminescent properties by controlling their structural and compositional properties. In this work, the effect of the stoichiometry and structure on the optical properties of silicon rich oxide (SRO) films in a multilayered (ML) structure is studied. SRO MLs with silicon excess gradually increased towards the top and bottom and towards the center of the ML produced through the variation of the stoichiometry in each SRO layer were fabricated and confirmed by X-ray photoelectron spectroscopy. Si-ncs with three main sizes were observed by a transmission electron microscope, in agreement with the stoichiometric profile of each SRO layer. The presence of the three sized Si-ncs and some oxygen related defects enhances intense violet/blue and red photoluminescence (PL) bands. The SRO MLs were super-enriched with additional excess silicon by Si{sup +} implantation, which enhanced the PL intensity. Oxygen-related defects and small Si-ncs (<2 nm) are mostly generated during ion implantation enhancing the violet/blue band to become comparable to the red band. The structural, compositional, and luminescent characteristics of the multilayers are the result of the contribution of the individual characteristics of each layer.

The bipolar silicon microstrip detector: A proposal for a novel precision tracking device

International Nuclear Information System (INIS)

Horisberger, R.

1990-01-01

It is proposed to combine the technology of fully depleted microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. The resulting structure has amplifying properties and is referred to as bipaolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking. (orig.)

Micromechanical Structures Fabrication; FINAL

International Nuclear Information System (INIS)

Rajic, S

2001-01-01

Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continually vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon micro-devices and the second impediment is communicating with these novel devices. We have implemented an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We also implemented a mechanical, electrical, and optical self-aligning hybridization technique for these alternate-material MEMS substrates

Selective laser etching or ablation for fabrication of devices

KAUST Repository

Buttner, Ulrich

2017-01-12

Methods of fabricating devices vial selective laser etching are provided. The methods can include selective laser etching of a portion of a metal layer, e.g. using a laser light source having a wavelength of 1,000 nm to 1,500 nm. The methods can be used to fabricate a variety of features, including an electrode, an interconnect, a channel, a reservoir, a contact hole, a trench, a pad, or a combination thereof. A variety of devices fabricated according to the methods are also provided. In some aspects, capacitive humidity sensors are provided that can be fabricated according to the provided methods. The capacitive humidity sensors can be fabricated with intricate electrodes, e.g. having a fractal pattern such as a Peano curve, a Hilbert curve, a Moore curve, or a combination thereof.

Silicon Nanowires for All-Optical Signal Processing in Optical Communication

DEFF Research Database (Denmark)

Pu, Minhao; Hu, Hao; Ji, Hua

2012-01-01

Silicon (Si), the second most abundant element on earth, has dominated in microelectronics for many decades. It can also be used for photonic devices due to its transparency in the range of optical telecom wavelengths which will enable a platform for a monolithic integration of optics...... and microelectronics. Silicon photonic nanowire waveguides fabricated on silicon-on-insulator (SOI) substrates are crucial elements in nano-photonic integrated circuits. The strong light confinement in nanowires induced by high index contrast SOI material enhances the nonlinear effects in the silicon nanowire core...... such as four-wave mixing (FWM) which is an imperative process for optical signal processing. Since the current mature silicon fabrication technology enables a precise dimension control on nanowires, dispersion engineering can be performed by tailoring nanowire dimensions to realize an efficient nonlinear...

Selective growth of carbon nanotube on silicon substrates

Institute of Scientific and Technical Information of China (English)

ZOU Xiao-ping; H. ABE; T. SHIMIZU; A. ANDO; H. TOKUMOT; ZHU Shen-ming; ZHOU Hao-shen

2006-01-01

The carbon nanotube (CNT) growth of iron oxide-deposited trench-patterns and the locally-ordered CNT arrays on silicon substrate were achieved by simple thermal chemical vapor deposition(STCVD) of ethanol vapor. The CNTs were uniformly synthesized with good selectivity on trench-patterned silicon substrates. This fabrication process is compatible with currently used semiconductor-processing technologies,and the carbon-nanotube fabrication process can be widely applied for the development of electronic devices using carbon-nanotube field emitters as cold cathodes and can revolutionize the area of field-emitting electronic devices. The site-selective growth of CNT from an iron oxide nanoparticle catalyst patterned were also achieved by drying-mediated self-assembly technique. The present method offers a simple and cost-effective method to grow carbon nanotubes with self-assembled patterns.

Travelling wave resonators fabricated with low-loss hydrogenated amorphous silicon

Science.gov (United States)

Lipka, Timo; Amthor, Julia; Trieu, Hoc Khiem; Müller, Jörg

2013-05-01

Low-loss hydrogenated amorphous silicon is employed for the fabrication of various planar integrated travelling wave resonators. Microring, racetrack, and disk resonators of different dimensions were fabricated with CMOS-compatible processes and systematically investigated. The key properties of notch filter ring resonators as extinction ratio, Q-factor, free spectral range, and the group refractive index were determined for resonators of varying radius, thereby achieving critically coupled photonic systems with high extinction ratios of about 20 dB for both polarizations. Racetrack resonators that are arranged in add/drop configuration and high quality factor microdisk resonators were optically characterized, with the microdisks exhibiting Q-factors of greater than 100000. Four-channel add/drop wavelength-division multiplexing filters that are based on cascaded racetrack resonators are studied. The design, the fabrication, and the optical characterization are presented.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

Science.gov (United States)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

Porous silicon structures with high surface area/specific pore size

Science.gov (United States)

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

Towards nanometer-spaced silicon contacts to proteins

Science.gov (United States)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Towards nanometer-spaced silicon contacts to proteins

International Nuclear Information System (INIS)

Schukfeh, Muhammed I; Behr, Pascal; Tornow, Marc; Sepunaru, Lior; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David

2016-01-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO_2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p"+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current–voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si–protein–Si configuration. (paper)

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.; Kutbee, Arwa T.; Ghodsi Nasseri, Seyed Faizelldin; Bersuker, G.; Hussain, Muhammad Mustafa

2014-01-01

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect

Design, Fabrication, and Characterization of Carbon Nanotube Field Emission Devices for Advanced Applications

Science.gov (United States)

Radauscher, Erich Justin

Carbon nanotubes (CNTs) have recently emerged as promising candidates for electron field emission (FE) cathodes in integrated FE devices. These nanostructured carbon materials possess exceptional properties and their synthesis can be thoroughly controlled. Their integration into advanced electronic devices, including not only FE cathodes, but sensors, energy storage devices, and circuit components, has seen rapid growth in recent years. The results of the studies presented here demonstrate that the CNT field emitter is an excellent candidate for next generation vacuum microelectronics and related electron emission devices in several advanced applications. The work presented in this study addresses determining factors that currently confine the performance and application of CNT-FE devices. Characterization studies and improvements to the FE properties of CNTs, along with Micro-Electro-Mechanical Systems (MEMS) design and fabrication, were utilized in achieving these goals. Important performance limiting parameters, including emitter lifetime and failure from poor substrate adhesion, are examined. The compatibility and integration of CNT emitters with the governing MEMS substrate (i.e., polycrystalline silicon), and its impact on these performance limiting parameters, are reported. CNT growth mechanisms and kinetics were investigated and compared to silicon (100) to improve the design of CNT emitter integrated MEMS based electronic devices, specifically in vacuum microelectronic device (VMD) applications. Improved growth allowed for design and development of novel cold-cathode FE devices utilizing CNT field emitters. A chemical ionization (CI) source based on a CNT-FE electron source was developed and evaluated in a commercial desktop mass spectrometer for explosives trace detection. This work demonstrated the first reported use of a CNT-based ion source capable of collecting CI mass spectra. The CNT-FE source demonstrated low power requirements, pulsing

Spike-Timing Dependent Plasticity in Unipolar Silicon Oxide RRAM Devices.

Science.gov (United States)

Zarudnyi, Konstantin; Mehonic, Adnan; Montesi, Luca; Buckwell, Mark; Hudziak, Stephen; Kenyon, Anthony J

2018-01-01

Resistance switching, or Resistive RAM (RRAM) devices show considerable potential for application in hardware spiking neural networks (neuro-inspired computing) by mimicking some of the behavior of biological synapses, and hence enabling non-von Neumann computer architectures. Spike-timing dependent plasticity (STDP) is one such behavior, and one example of several classes of plasticity that are being examined with the aim of finding suitable algorithms for application in many computing tasks such as coincidence detection, classification and image recognition. In previous work we have demonstrated that the neuromorphic capabilities of silicon-rich silicon oxide (SiO x ) resistance switching devices extend beyond plasticity to include thresholding, spiking, and integration. We previously demonstrated such behaviors in devices operated in the unipolar mode, opening up the question of whether we could add plasticity to the list of features exhibited by our devices. Here we demonstrate clear STDP in unipolar devices. Significantly, we show that the response of our devices is broadly similar to that of biological synapses. This work further reinforces the potential of simple two-terminal RRAM devices to mimic neuronal functionality in hardware spiking neural networks.

Suppression of irradiation effects in gold-doped silicon detectors

International Nuclear Information System (INIS)

McPherson, M.; Sloan, T.; Jones, B.K.

1997-01-01

Two sets of silicon detectors were irradiated with 1 MeV neutrons to different fluences and then characterized. The first batch were ordinary p-i-n photodiodes fabricated from high-resistivity (400 Ω cm) silicon, while the second batch were gold-doped powder diodes fabricated from silicon material initially of low resistivity (20 Ω cm). The increase in reverse leakage current after irradiation was found to be more in the former case than in the latter. The fluence dependence of the capacitance was much more pronounced in the p-i-n diodes than in the gold-doped diodes. Furthermore, photo current generation by optical means was less in the gold doped devices. All these results suggest that gold doping in silicon somewhat suppresses the effects of neutron irradiation. (author)

Graphene devices based on laser scribing technology

Science.gov (United States)

Qiao, Yan-Cong; Wei, Yu-Hong; Pang, Yu; Li, Yu-Xing; Wang, Dan-Yang; Li, Yu-Tao; Deng, Ning-Qin; Wang, Xue-Feng; Zhang, Hai-Nan; Wang, Qian; Yang, Zhen; Tao, Lu-Qi; Tian, He; Yang, Yi; Ren, Tian-Ling

2018-04-01

Graphene with excellent electronic, thermal, optical, and mechanical properties has great potential applications. The current devices based on graphene grown by micromechanical exfoliation, chemical vapor deposition (CVD), and thermal decomposition of silicon carbide are still expensive and inefficient. Laser scribing technology, a low-cost and time-efficient method of fabricating graphene, is introduced in this review. The patterning of graphene can be directly performed on solid and flexible substrates. Therefore, many novel devices such as strain sensors, acoustic devices, memory devices based on laser scribing graphene are fabricated. The outlook and challenges of laser scribing technology have also been discussed. Laser scribing may be a potential way of fabricating wearable and integrated graphene systems in the future.

Fabrication of coplanar HF analog devices

International Nuclear Information System (INIS)

Schulz, G.; Kratz, H.

1993-01-01

A thin film technology has to be built up, which allows the reliable and reproducible production of such devices. This technology has to fulfill some general requirements and many specific ones due to the difference of the devices. The general requirements concern the suitability of the technology for industrial production. That means, that the production processes should be reliable, they should allow a high trough-put, and up-scaling should be possible. Processes as passivation or cryo-packaging of the devices belong to this group of requirements as well. The technology for fabrication of the devices splits up into three well distinguishable techniques: deposition of thin films, control of the quality of the deposited layers and patterning of the device structures and contacts. (orig.)

Full-color OLED on silicon microdisplay

Science.gov (United States)

Ghosh, Amalkumar P.

2002-02-01

eMagin has developed numerous enhancements to organic light emitting diode (OLED) technology, including a unique, up- emitting structure for OLED-on-silicon microdisplay devices. Recently, eMagin has fabricated full color SVGA+ resolution OLED microdisplays on silicon, with over 1.5 million color elements. The display is based on white light emission from OLED followed by LCD-type red, green and blue color filters. The color filters are patterned directly on OLED devices following suitable thin film encapsulation and the drive circuits are built directly on single crystal silicon. The resultant color OLED technology, with hits high efficiency, high brightness, and low power consumption, is ideally suited for near to the eye applications such as wearable PCS, wireless Internet applications and mobile phone, portable DVD viewers, digital cameras and other emerging applications.

Nonlinear Silicon Photonic Signal Processing Devices for Future Optical Networks

Directory of Open Access Journals (Sweden)

Cosimo Lacava

2017-01-01

Full Text Available In this paper, we present a review on silicon-based nonlinear devices for all optical nonlinear processing of complex telecommunication signals. We discuss some recent developments achieved by our research group, through extensive collaborations with academic partners across Europe, on optical signal processing using silicon-germanium and amorphous silicon based waveguides as well as novel materials such as silicon rich silicon nitride and tantalum pentoxide. We review the performance of four wave mixing wavelength conversion applied on complex signals such as Differential Phase Shift Keying (DPSK, Quadrature Phase Shift Keying (QPSK, 16-Quadrature Amplitude Modulation (QAM and 64-QAM that dramatically enhance the telecom signal spectral efficiency, paving the way to next generation terabit all-optical networks.

Organization of silicon nanocrystals by localized electrochemical etching

International Nuclear Information System (INIS)

Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

2009-01-01

An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

Design and Fabrication of Piezoresistive Based Encapsulated Poly-Si Cantilevers for Bio/chemical Sensing

Science.gov (United States)

Krishna, N. P. Vamsi; Murthy, T. R. Srinivasa; Reddy, K. Jayaprakash; Sangeeth, K.; Hegde, G. M.

Cantilever-based sensing is a growing research field not only within micro regime but also in nano technology. The technology offers a method for rapid, on-line and in-situ monitoring of specific bio/chemical substances by detecting the nanomechanical responses of a cantilever sensor. Cantilever with piezoresistive based detection scheme is more attractive because of its electronics compatibility. Majority of commercially available micromachined piezoresistive sensors are bulk micromachined devices and are fabricated using single crystal silicon wafers. As substrate properties are not important in surface micromachining, the expensive silicon wafers can be replaced by cheaper substrates, such as poly-silicon, glass or plastic. Here we have designed SU-8 based bio/chemical compatible micro electro mechanical device that includes an encapsulated polysilicon piezoresistor for bio/chemical sensing. In this paper we report the design, fabrication and analysis of the encapsulated poly-Si cantilevers. Design and theoretical analysis are carried out using Finite Element Analysis software. For fabrication of poly-silicon piezoresistive cantilevers we followed the surface micromachining process steps. Preliminary characterization of the cantilevers is presented.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Fabrication and Mechanical Properties of Silicon Carbide Micropillars

International Nuclear Information System (INIS)

Shin, Chan Sun; Jin, Hyung Ha; Kwon, Jun Hyun; Kim, Don Jin

2011-01-01

Silicon carbide (SiC) has outstanding thermal and mechanical properties under high temperature and high neutron irradiation. SiC and SiC/SiC composites have been proposed as a promising candidate material for structural components in fusion reactors. Characterization of the mechanical properties such as fracture strength is important in ensuring the reliability of these ceramic structures. This study demonstrates a micro-compression test of SiC micropillars which are fabricated by mask and dryetching technique. Our fabrication method involves lithographic pattering of spun and baked photoresist on chemically vapor-deposited (CVD) polycrystalline beta-SiC substrates, followed by lift-off process of electroplated metal into the prescribed photoresist template. This metal works as an etch cap for inductively coupled plasma (ICP) etching. Our fabrication method enables the production of more than a few hundred micropillars under an identical fabrication condition, which is a great benefit for the statistical analysis of the fracture properties of brittle ceramic materials. The diameters of fabricated SiC micropillars range from 6 down to 0.5 μm. The ratio of micropillar diameter to height is set to 1:3 ∼ 1:4. Uniaxial compression tests have been conducted using flat punch nanoindentation at room temperature. We observed the specimen size effect on the measured fracture stress of SiC micropillars. In this paper we present the results of the micro-compression tests of SiC micropillars with the diameters of 0.8 and 2.6 μm

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-12-01

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

Science.gov (United States)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Fabrication of coupled graphene–nanotube quantum devices

International Nuclear Information System (INIS)

Engels, S; Weber, P; Terrés, B; Dauber, J; Volk, C; Wichmann, U; Stampfer, C; Meyer, C; Trellenkamp, S

2013-01-01

We report on the fabrication and characterization of all-carbon hybrid quantum devices based on graphene and single-walled carbon nanotubes. We discuss both carbon nanotube quantum dot devices with graphene charge detectors and nanotube quantum dots with graphene leads. The devices are fabricated by chemical vapor deposition growth of carbon nanotubes and subsequent structuring of mechanically exfoliated graphene. We study the detection of individual charging events in the carbon nanotube quantum dot by a nearby graphene nanoribbon and show that they lead to changes of up to 20% of the conductance maxima in the graphene nanoribbon, acting as a well performing charge detector. Moreover, we discuss an electrically coupled graphene–nanotube junction, which exhibits a tunneling barrier with tunneling rates in the low GHz regime. This allows us to observe Coulomb blockade on a carbon nanotube quantum dot with graphene source and drain leads. (paper)

Transfer-last suspended graphene fabrication on gold, graphite and silicon nanostructures

OpenAIRE

Reynolds, J.; Boodhoo, L.; Huang, C.C.; Hewak, D.W.; Saito, S.; Tsuchiya, Y.; Mizuta, H.

2015-01-01

While most graphene devices fabricated so far have been by transferring graphene onto flat substrates first, an interesting approach would be to transfer graphene onto patterned substrates to suspend graphene for future graphene nanoelectromechanical device applications. This novel "transfer-last" fabrication is beneficial for reducing possible damage of the suspended graphene caused by subsequent undercutting processes and typical substrate interactions. On the other hand, reduction of conta...

Influence of polarized bias and porous silicon morphology on the electrical behavior of Au-porous silicon contacts*

Science.gov (United States)

Zhao, Yue; Li, Dong-sheng; Xing, Shou-xiang; Yang, De-ren; Jiang, Min-hua

2005-01-01

This paper reports the surface morphology and I-V curves of porous silicon (PS) samples and related devices. The observed fabrics on the PS surface were found to affect the electrical property of PS devices. When the devices were operated under different external bias (10 V or 3 V) for 10 min, their observed obvious differences in electrical properties may be due to the different control mechanisms in the Al/PS interface and PS matrix morphology. PMID:16252350

Systems and methods for scalable perovskite device fabrication

Science.gov (United States)

Huang, Jinsong; Dong, Qingfeng; Sao, Yuchuan

2017-02-28

Continuous processes for fabricating a perovskite device are described that include using a doctor blade for continuously forming a perovskite layer and using a conductive tape lamination process to form an anode or a cathode layer on the perovskite device.

Modeling and fabrication of 4H-SiC Schottky junction

Science.gov (United States)

Martychowiec, A.; Pedryc, A.; Kociubiński, A.

2017-08-01

The rapidly growing demand for electronic devices requires using of alternative semiconductor materials, which could replace conventional silicon. Silicon carbide has been proposed for these harsh environment applications (high temperature, high voltage, high power conditions) because of its wide bandgap, its high temperature operation ability, its excellent thermal and chemical stability, and its high breakdown electric field strength. The Schottky barrier diode (SBD) is known as one of the best refined SiC devices. This paper presents prepared model, simulations and description of technology of 4H-SiC Schottky junction as well as characterization of fabricated structures. The future aim of the application of the structures is an optical detection of an ultraviolet radiation. The model section contains a comparison of two different solutions of SBD's construction. Simulations - as a crucial process of designing electronic devices - have been performed using the ATLAS device of Silvaco TCAD software. As a final result the paper shows I-V characteristics of fabricated diodes.

Active phase correction of high resolution silicon photonic arrayed waveguide gratings.

Science.gov (United States)

Gehl, M; Trotter, D; Starbuck, A; Pomerene, A; Lentine, A L; DeRose, C

2017-03-20

Arrayed waveguide gratings provide flexible spectral filtering functionality for integrated photonic applications. Achieving narrow channel spacing requires long optical path lengths which can greatly increase the footprint of devices. High index contrast waveguides, such as those fabricated in silicon-on-insulator wafers, allow tight waveguide bends which can be used to create much more compact designs. Both the long optical path lengths and the high index contrast contribute to significant optical phase error as light propagates through the device. Therefore, silicon photonic arrayed waveguide gratings require active or passive phase correction following fabrication. Here we present the design and fabrication of compact silicon photonic arrayed waveguide gratings with channel spacings of 50, 10 and 1 GHz. The largest device, with 11 channels of 1 GHz spacing, has a footprint of only 1.1 cm2. Using integrated thermo-optic phase shifters, the phase error is actively corrected. We present two methods of phase error correction and demonstrate state-of-the-art cross-talk performance for high index contrast arrayed waveguide gratings. As a demonstration of possible applications, we perform RF channelization with 1 GHz resolution. Additionally, we generate unique spectral filters by applying non-zero phase offsets calculated by the Gerchberg Saxton algorithm.

Fabrication of tunnel junction-based molecular electronics and spintronics devices

International Nuclear Information System (INIS)

Tyagi, Pawan

2012-01-01

Tunnel junction-based molecular devices (TJMDs) are highly promising for realizing futuristic electronics and spintronics devices for advanced logic and memory operations. Under this approach, ∼2.5 nm molecular device elements bridge across the ∼2-nm thick insulator of a tunnel junction along the exposed side edge(s). This paper details the efforts and insights for producing a variety of TJMDs by resolving multiple device fabrication and characterization issues. This study specifically discusses (i) compatibility between tunnel junction test bed and molecular solutions, (ii) optimization of the exposed side edge profile and insulator thickness for enhancing the probability of molecular bridging, (iii) effect of fabrication process-induced mechanical stresses, and (iv) minimizing electrical bias-induced instability after the device fabrication. This research will benefit other researchers interested in producing TJMDs efficiently. TJMD approach offers an open platform to test virtually any combination of magnetic and nonmagnetic electrodes, and promising molecules such as single molecular magnets, porphyrin, DNA, and molecular complexes.

Defects in silicon effect on device performance and relationship to crystal growth conditions

Science.gov (United States)

Jastrzebski, L.

1985-01-01

A relationship between material defects in silicon and the performance of electronic devices will be described. A role which oxygen and carbon in silicon play during the defects generation process will be discussed. The electronic properties of silicon are a strong function of the oxygen state in the silicon. This state controls mechanical properties of silicon efficiency for internal gettering and formation of defects in the device's active area. In addition, to temperature, time, ambience, and the cooling/heating rates of high temperature treatments, the oxygen state is a function of the crystal growth process. The incorporation of carbon and oxygen into silicon crystal is controlled by geometry and rotation rates applied to crystal and crucible during crystal growths. Also, formation of nucleation centers for oxygen precipitation is influenced by the growth process, although there is still a controversy which parameters play a major role. All these factors will be reviewed with special emphasis on areas which are still ambiguous and controversial.

Dielectrophoretic trapping of DNA-coated gold nanoparticles on silicon based vertical nanogap devices.

Science.gov (United States)

Strobel, Sebastian; Sperling, Ralph A; Fenk, Bernhard; Parak, Wolfgang J; Tornow, Marc

2011-06-07

We report on the successful dielectrophoretic trapping and electrical characterization of DNA-coated gold nanoparticles on vertical nanogap devices (VNDs). The nanogap devices with an electrode distance of 13 nm were fabricated from Silicon-on-Insulator (SOI) material using a combination of anisotropic reactive ion etching (RIE), selective wet chemical etching and metal thin-film deposition. Au nanoparticles (diameter 40 nm) coated with a monolayer of dithiolated 8 base pairs double stranded DNA were dielectrophoretically trapped into the nanogap from electrolyte buffer solution at MHz frequencies as verified by scanning and transmission electron microscopy (SEM/TEM) analysis. First electrical transport measurements through the formed DNA-Au-DNA junctions partially revealed an approximately linear current-voltage characteristic with resistance in the range of 2-4 GΩ when measured in solution. Our findings point to the importance of strong covalent bonding to the electrodes in order to observe DNA conductance, both in solution and in the dry state. We propose our setup for novel applications in biosensing, addressing the direct interaction of biomolecular species with DNA in aqueous electrolyte media.

Clear Castable Polyurethane Elastomer for Fabrication of Microfluidic Devices

Science.gov (United States)

Domansky, Karel; Leslie, Daniel C.; McKinney, James; Fraser, Jacob P.; Sliz, Josiah D.; Hamkins-Indik, Tiama; Hamilton, Geraldine A.; Bahinski, Anthony; Ingber, Donald E.

2013-01-01

Polydimethylsiloxane (PDMS) has numerous desirable properties for fabricating microfluidic devices, including optical transparency, flexibility, biocompatibility, and fabrication by casting; however, partitioning of small hydrophobic molecules into the bulk of PDMS hinders industrial acceptance of PDMS microfluidic devices for chemical processing and drug development applications. Here we describe an attractive alternative material that is similar to PDMS in terms of optical transparency, flexibility and castability, but that is also resistant to absorption of small hydrophobic molecules. PMID:23954953

Quantum Bridge Fabrication Using Photolithography

International Nuclear Information System (INIS)

Quinones, R.

2001-01-01

The need for high-speed performance electronics in computers integrated circuits and sensors, require the fabrication of low energy consumption diodes. Nano fabrication methods require new techniques and equipment. We are currently developing a procedure to fabricate a diode based on quantum-effects. The device will act like a traditional diode, but the nanometer scale will allow it to reach high speeds without over heating. This new diode will be on a nano-bridge so it can be attenuated by an electromagnetic wave. The goal is to obtain similar current vs voltage response as in a silicon diode

Silicon-germanium (Sige) nanostructures production, properties and applications in electronics

CERN Document Server

Usami, N

2011-01-01

Nanostructured silicon-germanium (SiGe) provides the prospect of novel and enhanced electronic device performance. This book reviews the materials science and technology of SiGe nanostructures, including crystal growth, fabrication of nanostructures, material properties and applications in electronics.$bNanostructured silicon-germanium (SiGe) opens up the prospects of novel and enhanced electronic device performance, especially for semiconductor devices. Silicon-germanium (SiGe) nanostructures reviews the materials science of nanostructures and their properties and applications in different electronic devices. The introductory part one covers the structural properties of SiGe nanostructures, with a further chapter discussing electronic band structures of SiGe alloys. Part two concentrates on the formation of SiGe nanostructures, with chapters on different methods of crystal growth such as molecular beam epitaxy and chemical vapour deposition. This part also includes chapters covering strain engineering and mo...

The first results of siliconization on SWIP-RFP device

International Nuclear Information System (INIS)

Zhang Peng; Li Qiang; Luo Cuiwen; Li Jieping; Qian Shangjie; Fang Shuiquan; Yi Ping; Xue Jun; Li Kehua; Luo Junlin; Hong Wenyu; Cao Zeng; Zhang Nianman; Wang Quanming; Li Jie; Huang Ming; Zhong Yunze; Zhang Qingchun; Luo Cuixian

1997-01-01

The first results of reversed field pinch (RFP) and ultra low safety factor (ULQ) plasma experiments with siliconization on SWIP-RFP device are presented in this paper. The siliconization decreases the impurity concentrations in the plasma and increases the configuration sustainment time. Ion temperature has been estimated with the CV line of the visible light spectra and the broadening of CIII lines in vacuum ultraviolet (VUV) region. The anomalous ion heating as well as the anomalous resistance were observed. (orig.)

Development of thin pixel detectors on epitaxial silicon for HEP experiments

International Nuclear Information System (INIS)

Boscardin, Maurizio; Calvo, Daniela; Giacomini, Gabriele; Wheadon, Richard; Ronchin, Sabina; Zorzi, Nicola

2013-01-01

The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10 16 n eq /cm 2 . Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics

Development of thin pixel detectors on epitaxial silicon for HEP experiments

Energy Technology Data Exchange (ETDEWEB)

Boscardin, Maurizio, E-mail: boscardi@fbk.eu [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Calvo, Daniela [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Giacomini, Gabriele [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Wheadon, Richard [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Ronchin, Sabina; Zorzi, Nicola [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy)

2013-08-01

The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10{sup 16} n{sub eq}/cm{sup 2}. Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics.

Fabrication of amorphous silica nanowires via oxygen plasma treatment of polymers on silicon

Science.gov (United States)

Chen, Zhuojie; She, Didi; Chen, Qinghua; Li, Yanmei; Wu, Wengang

2018-02-01

We demonstrate a facile non-catalytic method of fabricating silica nanowires at room temperature. Different polymers including photoresists, parylene C and polystyrene are patterned into pedestals on the silicon substrates. The silica nanowires are obtained via the oxygen plasma treatment on those pedestals. Compared to traditional strategies of silica nanowire fabrication, this method is much simpler and low-cost. Through designing the proper initial patterns and plasma process parameters, the method can be used to fabricate various regiment nano-scale silica structure arrays in any laboratory with a regular oxygen-plasma-based cleaner or reactive-ion-etching equipment.

Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices.

Science.gov (United States)

Aurang, Pantea; Turan, Rasit; Unalan, Husnu Emrah

2017-10-06

Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

Glass-embedded two-dimensional silicon photonic crystal devices with a broad bandwidth waveguide and a high quality nanocavity.

Science.gov (United States)

Jeon, Seung-Woo; Han, Jin-Kyu; Song, Bong-Shik; Noda, Susumu

2010-08-30

To enhance the mechanical stability of a two-dimensional photonic crystal slab structure and maintain its excellent performance, we designed a glass-embedded silicon photonic crystal device consisting of a broad bandwidth waveguide and a nanocavity with a high quality (Q) factor, and then fabricated the structure using spin-on glass (SOG). Furthermore, we showed that the refractive index of the SOG could be tuned from 1.37 to 1.57 by varying the curing temperature of the SOG. Finally, we demonstrated a glass-embedded heterostructured cavity with an ultrahigh Q factor of 160,000 by adjusting the refractive index of the SOG.

Scaling of ion implanted Si:P single electron devices

International Nuclear Information System (INIS)

Escott, C C; Hudson, F E; Chan, V C; Petersson, K D; Clark, R G; Dzurak, A S

2007-01-01

We present a modelling study on the scaling prospects for phosphorus in silicon (Si:P) single electron devices using readily available commercial and free-to-use software. The devices comprise phosphorus ion implanted, metallically doped (n + ) dots (size range 50-500 nm) with source and drain reservoirs. Modelling results are compared to measurements on fabricated devices and discussed in the context of scaling down to few-electron structures. Given current fabrication constraints, we find that devices with 70-75 donors per dot should be realizable. We comment on methods for further reducing this number

Scaling of ion implanted Si:P single electron devices

Energy Technology Data Exchange (ETDEWEB)

Escott, C C [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Hudson, F E [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Chan, V C [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Petersson, K D [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Clark, R G [Centre for Quantum Computer Technology, School of Physics, UNSW, Sydney, 2052 (Australia); Dzurak, A S [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia)

2007-06-13

We present a modelling study on the scaling prospects for phosphorus in silicon (Si:P) single electron devices using readily available commercial and free-to-use software. The devices comprise phosphorus ion implanted, metallically doped (n{sup +}) dots (size range 50-500 nm) with source and drain reservoirs. Modelling results are compared to measurements on fabricated devices and discussed in the context of scaling down to few-electron structures. Given current fabrication constraints, we find that devices with 70-75 donors per dot should be realizable. We comment on methods for further reducing this number.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Science.gov (United States)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Development and applications of monocrystalline silicon radiation sensors fabricated at Comision Nacional de Energia Atomica (CNEA)

International Nuclear Information System (INIS)

Bolzi, C; Bruno, C; Duran, J; Godfrin, E; Martinez Bogado, M; Pla, J; Tamasi, M

2005-01-01

The development of silicon photovoltaic sensors at CNEA has begun in 1998.These sensors, fabricated in the Photovoltaic Laboratory of the Solar Energy Group at Constituyentes Atomic Center, have been used to build low cost radiometers as well as solar angular position sensors on board of artificial satellites.The design, fabrication and calibration of these sensors have been made in different prototypes in order to analyze its performance and to evaluate its limitations.Nowadays, several commercial prototypes have been distributed in different laboratories of our country in order to evaluate them in real work conditions.Particularly, the first experiment of argentine solar cells on space performed on board of SAC-A satellite, included the fabrication of position sensors of this satellite as part of the alignment system of the solar array respect to the sun.In this article, the state of the art of monocrystalline silicon photovoltaic sensors fabricated at CNEA for terrestrial and space applications is presented

Making Porous Luminescent Regions In Silicon Wafers

Science.gov (United States)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fabricating a multi-level barrier-integrated microfluidic device using grey-scale photolithography

International Nuclear Information System (INIS)

Nam, Yoonkwang; Kim, Minseok; Kim, Taesung

2013-01-01

Most polymer-replica-based microfluidic devices are mainly fabricated by using standard soft-lithography technology so that multi-level masters (MLMs) require multiple spin-coatings, mask alignments, exposures, developments, and bakings. In this paper, we describe a simple method for fabricating MLMs for planar microfluidic channels with multi-level barriers (MLBs). A single photomask is necessary for standard photolithography technology to create a polydimethylsiloxane grey-scale photomask (PGSP), which adjusts the total amount of UV absorption in a negative-tone photoresist via a wide range of dye concentrations. Since the PGSP in turn adjusts the degree of cross-linking of the photoresist, this method enables the fabrication of MLMs for an MLB-integrated microfluidic device. Since the PGSP-based soft-lithography technology provides a simple but powerful fabrication method for MLBs in a microfluidic device, we believe that the fabrication method can be widely used for micro total analysis systems that benefit from MLBs. We demonstrate an MLB-integrated microfluidic device that can separate microparticles. (paper)

A Novel Silicon-based Wideband RF Nano Switch Matrix Cell and the Fabrication of RF Nano Switch Structures

Directory of Open Access Journals (Sweden)

Yi Xiu YANG

2011-12-01

Full Text Available This paper presents the concept of RF nano switch matrix cell and the fabrication of RF nano switch. The nano switch matrix cell can be implemented into complex switch matrix for signal routing. RF nano switch is the decision unit for the matrix cell; in this research, it is fabricated on a tri-layer high-resistivity-silicon substrate using surface micromachining approach. Electron beam lithography is introduced to define the pattern and IC compatible deposition process is used to construct the metal layers. Silicon-based nano switch fabricated by IC compatible process can lead to a high potential of system integration to perform a cost effective system-on-a-chip solution. In this paper, simulation results of the designed matrix cell are presented; followed by the details of the nano structure fabrication and fabrication challenges optimizations; finally, measurements of the fabricated nano structure along with analytical discussions are also discussed.

Aluminum-catalyzed silicon nanowires: Growth methods, properties, and applications

Energy Technology Data Exchange (ETDEWEB)

Hainey, Mel F.; Redwing, Joan M. [Department of Materials Science and Engineering, Materials Research Institute, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

2016-12-15

Metal-mediated vapor-liquid-solid (VLS) growth is a promising approach for the fabrication of silicon nanowires, although residual metal incorporation into the nanowires during growth can adversely impact electronic properties particularly when metals such as gold and copper are utilized. Aluminum, which acts as a shallow acceptor in silicon, is therefore of significant interest for the growth of p-type silicon nanowires but has presented challenges due to its propensity for oxidation. This paper summarizes the key aspects of aluminum-catalyzed nanowire growth along with wire properties and device results. In the first section, aluminum-catalyzed nanowire growth is discussed with a specific emphasis on methods to mitigate aluminum oxide formation. Next, the influence of growth parameters such as growth temperature, precursor partial pressure, and hydrogen partial pressure on nanowire morphology is discussed, followed by a brief review of the growth of templated and patterned arrays of nanowires. Aluminum incorporation into the nanowires is then discussed in detail, including measurements of the aluminum concentration within wires using atom probe tomography and assessment of electrical properties by four point resistance measurements. Finally, the use of aluminum-catalyzed VLS growth for device fabrication is reviewed including results on single-wire radial p-n junction solar cells and planar solar cells fabricated with nanowire/nanopyramid texturing.

Silicon integrated circuits advances in materials and device research

CERN Document Server

Kahng, Dawon

1981-01-01

Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

Synthesis of silicon nanocomposite for printable photovoltaic devices on flexible substrate

Science.gov (United States)

Odo, E. A.; Faremi, A. A.

2017-06-01

Renewed interest has been established in the preparation of silicon nanoparticles for electronic device applications. In this work, we report on the production of silicon powders using a simple ball mill and of silicon nanocomposite ink for screen-printable photovoltaic device on a flexible substrate. Bulk single crystalline silicon was milled for 25 h in the ball mill. The structural properties of the produced silicon nanoparticles were investigated using X-ray diffraction (XRD) and transmission electron microscopy. The results show that the particles remained highly crystalline, though transformed from their original single crystalline state to polycrystalline. The elemental composition using energy dispersive X-ray florescence spectroscopy (EDXRF) revealed that contamination from iron (Fe) and chromium (Cr) of the milling media and oxygen from the atmosphere were insignificant. The size distribution of the nanoparticles follows a lognormal pattern that ranges from 60 nm to about 1.2 μm and a mean particle size of about 103 nm. Electrical characterization of screen-printed PN structures of the nanocomposite formed by embedding the powder into a suitable water-soluble polymer on Kapton sheet reveals an enhanced photocurrent transport resulting from photo-induced carrier generation in the depletion region with energy greater that the Schottky barrier height at the metal-composite interface.

Electrical characterization of MIS devices using PECVD SiN{sub x}:H films for application of silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Yoo, Jin-Su; Cho, Jun-Sik; Park, Joo-Hyung; Ahn, Seung-Kyu; Shin, Kee-Shik; Yoon, Kyung-Hoon [Korea Institute of Energy Research, Daejeon (Korea, Republic of); Yi, Jun-Sin [Sungkyunkwan University, Suwon (Korea, Republic of)

2012-07-15

The surface passivation of crystalline silicon solar cells using plasma enhanced chemical vapor deposition (PECVD), hydrogenated, silicon-nitride (SiN{sub x}:H) thin films has become significant due to a low-temperature, low-cost and very effective defect passivation process. Also, a good quality antireflection coating can be formed. In this work, SiN{sub x}:H thin films were deposited by varying the gas ratio R (=NH{sub 3}/SiH{sub 4}+NH{sub 3}) and were annealed by rapid thermal processing (RTP). Metal-insulator- semiconductor (MIS) devices were fabricated using SiN{sub x}:H thin films as insulator layers and they were analyzed in the temperature range of 100 - 400 K by using capacitance-voltage (C-V) and current-voltage (I-V) measurements. The annealed SiN{sub x}:H thin films were evaluated by using the electrical properties at different temperature to determine the effect of surface passivation. We achieved an energy conversion efficiency of 18.1% under one-sun standard testing conditions for large-area (156 mm x 156 mm) crystalline-silicon solar cells.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

Science.gov (United States)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Silicon solar cell - from R and D to production

International Nuclear Information System (INIS)

Akhter, P.

1995-01-01

During last 30 years tremendous research and development efforts have concluded that tech-economically silicon is the most suitable material for the manufacturing of solar cells and a number of achievements have been made in the processing of both the materials nd devices. A number of novel structure have been designed and fabricated. The crystalline silicon technology has now become mature enough and is ready to take off from R/D laboratories to large scale fabrication. At laboratory scale the performance of monocrystalline silicon cells have already reached very close to the theoretical value. However the processing cost and efficiency being complimentary, the commercial cells, as a trade off, have to compromise at rather lower efficiencies. Further efforts of lowering the processing cost of both the material and devices are in progress. At the same time attempts are being made to understand the physics of all those factors that limit the efficiency; develop the technologies to eliminate or optimize such effects to reach limiting efficiency with lowest possible cost. All such factors, along with the development will be discussed. (author)

Transformation optics on a silicon platform

International Nuclear Information System (INIS)

Gabrielli, Lucas H; Lipson, Michal

2011-01-01

Transformation optics allows the creation of innovative devices; however, its implementation in the optical domain remains challenging. We describe here our process to design and fabricate such devices using silicon as a platform for broad band operation in the optical domain. We discuss the approximations and methods employed to overcome the challenges of using dielectric materials as a platform for transformation optics, such as the anisotropy and gradient refractive index implementation. These encompass conformal and quasi-conformal mappings, and a dithering process to discretize and quantize the continuously inhomogeneous index function. We show examples of devices that we fabricated and tested, including the carpet invisibility cloak, a broad bandwidth light concentrator, and a perfect imaging device, known as Maxwell's fish eye lens. Finally, we touch on future directions under investigation to further develop transformation optics based on dielectric materials

Doping of silicon carbide by ion implantation

International Nuclear Information System (INIS)

Gimbert, J.

1999-01-01

It appeared that in some fields, as the hostile environments (high temperature or irradiation), the silicon compounds showed limitations resulting from the electrical and mechanical properties. Doping of 4H and 6H silicon carbide by ion implantation is studied from a physicochemical and electrical point of view. It is necessary to obtain n-type and p-type material to realize high power and/or high frequency devices, such as MESFETs and Schottky diodes. First, physical and electrical properties of silicon carbide are presented and the interest of developing a process technology on this material is emphasised. Then, physical characteristics of ion implantation and particularly classical dopant implantation, such as nitrogen, for n-type doping, and aluminium and boron, for p-type doping are described. Results with these dopants are presented and analysed. Optimal conditions are extracted from these experiences so as to obtain a good crystal quality and a surface state allowing device fabrication. Electrical conduction is then described in the 4H and 6H-SiC polytypes. Freezing of free carriers and scattering processes are described. Electrical measurements are carried out using Hall effect on Van der Panw test patterns, and 4 point probe method are used to draw the type of the material, free carrier concentrations, resistivity and mobility of the implanted doped layers. These results are commented and compared to the theoretical analysis. The influence of the technological process on electrical conduction is studied in view of fabricating implanted silicon carbide devices. (author)

One-step Maskless Fabrication and Optical Characterization of Silicon Surfaces with Antireflective Properties and a White Color Appearance

DEFF Research Database (Denmark)

Sun, Ling; Feidenhans'l, Nikolaj Agentoft; Telecka, Agnieszka

2016-01-01

We report a simple one-step maskless fabrication of inverted pyramids on silicon wafers by reactive ion etching. The fabricated surface structures exhibit excellent anti-reflective properties: The total reflectance of the nano inverted pyramids fabricated by our method can be as low as 12% withou...... milky white color....

SEM and HRTEM study of porous silicon--relationship between fabrication, morphology and optical properties

International Nuclear Information System (INIS)

Dian, J.; Macek, A.; Niznansky, D.; Nemec, I.; Vrkoslav, V.; Chvojka, T.; Jelinek, I.

2004-01-01

We studied the dependence of porous silicon (PS) morphology on fabrication conditions and the link between morphology, porosity and optical properties. P-type (1 0 0) silicon wafers with resistivity of 10 Ω cm were electrochemically etched in a HF:ethanol:water mixture at various HF concentrations and current densities. Porosity and thickness of the samples were determined gravimetrically. Detailed information about evolution of porous silicon layer morphology with variation of preparation conditions was obtained by scanning electron microscope (SEM), the presence of silicon nanoparticles was confirmed by high resolution transmission electron microscopy. Decrease of the mean size of silicon nanoparticles with increasing porous silicon porosity was revealed in a monotonous blue shift of photoluminescence (PL) maximum in room temperature photoluminescence spectra of studied samples. This blue shift is consistent with quantum confinement model of photoluminescence mechanism. We observed that total porosity of porous films cannot fully explain observed photoluminescence behavior and correct interpretation of the blue shift of photoluminescence spectra requires detailed knowledge of porous silicon morphology

Fabrication of nanopores in multi-layered silicon-based membranes using focused electron beam induced etching with XeF_2 gas

International Nuclear Information System (INIS)

Liebes-Peer, Yael; Bandalo, Vedran; Sökmen, Ünsal; Tornow, Marc; Ashkenasy, Nurit

2016-01-01

The emergent technology of using nanopores for stochastic sensing of biomolecules introduces a demand for the development of simple fabrication methodologies of nanopores in solid state membranes. This process becomes particularly challenging when membranes of composite layer architecture are involved. To overcome this challenge we have employed a focused electron beam induced chemical etching process. We present here the fabrication of nanopores in silicon-on-insulator based membranes in a single step process. In this process, chemical etching of the membrane materials by XeF_2 gas is locally accelerated by an electron beam, resulting in local etching, with a top membrane oxide layer preventing delocalized etching of the silicon underneath. Nanopores with a funnel or conical, 3-dimensional (3D) shape can be fabricated, depending on the duration of exposure to XeF_2, and their diameter is dominated by the time of exposure to the electron beam. The demonstrated ability to form high-aspect ratio nanopores in comparably thick, multi-layered silicon based membranes allows for an easy integration into current silicon process technology and hence is attractive for implementation in biosensing lab-on-chip fabrication technologies. (author)

Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

International Nuclear Information System (INIS)

Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

2002-01-01

Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

Porous silicon technology for integrated microsystems

Science.gov (United States)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

DEFF Research Database (Denmark)

Li, Helong; Munk-Nielsen, Stig; Wang, Xiongfei

2016-01-01

This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influ......This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then......, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance...... of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed...

Mechanical engineering and design of silicon-based particle tracking devices

International Nuclear Information System (INIS)

Miller, W.O.; Thompson, T.C.; Gamble, M.T.; Reid, R.S.; Woloshun, K.A.; Dransfield, G.D.; Ziock, H.J.

1990-01-01

The Mechanical Engineering and Electronics Division of the Los Alamos National Laboratory has been investigating silicon-based particle tracking device technology as part of the Superconducting Super Collider-sponsored silicon subsystem collaboration. Structural, thermal, and materials issues have been addressed. This paper discussed detector structural integrity and stability, including detailed finite element models of the silicon chip support and predictive methods used in designing with advanced composite materials. Electronic thermal loading and efficient dissipation of such energy using heat pipe technology has been investigated. The use of materials whose coefficients of thermal expansion are engineered to match silicon or to be near zero, as appropriate, have been explored. Material analysis and test results from radiation, chemical, and static loading are compared with analytical predictions and discussed. 1 ref., 2 figs., 1 tab

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem

2016-09-26

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem; Seif, Johannes Peter; Riesen, Yannick; Tomasi, Andrea; Jeangros, Quentin; Wyrsch, Nicolas; Haug, Franz-Josef; De Wolf, Stefaan; Ballif, Christophe

2016-01-01

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Directory of Open Access Journals (Sweden)

Zahra Bisadi

2018-02-01

Full Text Available A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Fabrication of polyimide based microfluidic channels for biosensor devices

Science.gov (United States)

Zulfiqar, Azeem; Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2015-03-01

The ever-increasing complexity of the fabrication process of Point-of-care (POC) devices, due to high demand of functional versatility, compact size and ease-of-use, emphasizes the need of multifunctional materials that can be used to simplify this process. Polymers, currently in use for the fabrication of the often needed microfluidic channels, have limitations in terms of their physicochemical properties. Therefore, the use of a multipurpose biocompatible material with better resistance to the chemical, thermal and electrical environment, along with capability of forming closed channel microfluidics is inevitable. This paper demonstrates a novel technique of fabricating microfluidic devices using polyimide (PI) which fulfills the aforementioned properties criteria. A fabrication process to pattern microfluidic channels, using partially cured PI, has been developed by using a dry etching method. The etching parameters are optimized and compared to those used for fully cured PI. Moreover, the formation of closed microfluidic channel on wafer level by bonding two partially cured PI layers or a partially cured PI to glass with high bond strength has been demonstrated. The reproducibility in uniformity of PI is also compared to the most commonly used SU8 polymer, which is a near UV sensitive epoxy resin. The potential applications of PI processing are POC and biosensor devices integrated with microelectronics.

Multichannel silicon WDM ring filters fabricated with DUV lithography

Science.gov (United States)

Lee, Jong-Moo; Park, Sahnggi; Kim, Gyungock

2008-09-01

We have fabricated 9-channel silicon wavelength-division-multiplexing (WDM) ring filters using 193 nm deep-ultraviolet (DUV) lithography and investigated the spectral properties of the ring filters by comparing the transmission spectra with and without an upper cladding. The average channel-spacing of the 9-channel WDM ring filter with a polymeric upper cladding is measured about 1.86 nm with the standard deviation of the channel-spacing about 0.34 nm. The channel crosstalk is about -30 dB, and the minimal drop loss is about 2 dB.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

Energy Technology Data Exchange (ETDEWEB)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan [Photovoltaics and Thin-Film Electronics Laboratory, Institute of Microengineering (IMT), Ecole Polytechnique Fédérale de Lausanne (EPFL), Rue de la Maladière 71b, CH-2002 Neuchâtel (Switzerland); Menda, Deneb; Özdemir, Orhan [Department of Physics, Yıldız Technical University, Davutpasa Campus, TR-34210 Esenler, Istanbul (Turkey); Descoeudres, Antoine; Barraud, Loris [CSEM, PV-Center, Jaquet-Droz 1, CH-2002 Neuchâtel (Switzerland)

2016-08-07

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation of such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.

Effects of size and defects on the elasticity of silicon nanocantilevers

International Nuclear Information System (INIS)

Sadeghian, Hamed; Goosen, Johannes F L; Van Keulen, Fred; Yang, Chung-Kai; Bossche, Andre; French, Paddy J; Staufer, Urs

2010-01-01

The size-dependent elastic behavior of silicon nanocantilevers and nanowires, specifically the effective Young's modulus, has been determined by experimental measurements and theoretical investigations. The size dependence becomes more significant as the devices scale down from micro- to nano-dimensions, which has mainly been attributed to surface effects. However, discrepancies between experimental measurements and computational investigations show that there could be other influences besides surface effects. In this paper, we try to determine to what extent the surface effects, such as surface stress, surface elasticity, surface contamination and native oxide layers, influence the effective Young's modulus of silicon nanocantilevers. For this purpose, silicon cantilevers were fabricated in the top device layer of silicon on insulator (SOI) wafers, which were thinned down to 14 nm. The effective Young's modulus was extracted with the electrostatic pull-in instability method, recently developed by the authors (H Sadeghian et al 2009 Appl. Phys. Lett. 94 221903). In this work, the drop in the effective Young's modulus was measured to be significant at around 150 nm thick cantilevers. The comparison between theoretical models and experimental measurements demonstrates that, although the surface effects influence the effective Young's modulus of silicon to some extent, they alone are insufficient to explain why the effective Young's modulus decreases prematurely. It was observed that the fabrication-induced defects abruptly increased when the device layer was thinned to below 100 nm. These defects became visible as pinholes during HF-etching. It is speculated that they could be the origin of the reduced effective Young's modulus experimentally observed in ultra-thin silicon cantilevers.

Design & Fabrication of a High-Voltage Photovoltaic Cell

Energy Technology Data Exchange (ETDEWEB)

Felder, Jennifer; /North Carolina State U. /SLAC

2012-09-05

Silicon photovoltaic (PV) cells are alternative energy sources that are important in sustainable power generation. Currently, applications of PV cells are limited by the low output voltage and somewhat low efficiency of such devices. In light of this fact, this project investigates the possibility of fabricating high-voltage PV cells on float-zone silicon wafers having output voltages ranging from 50 V to 2000 V. Three designs with different geometries of diffusion layers were simulated and compared in terms of metal coverage, recombination, built-in potential, and conduction current density. One design was then chosen and optimized to be implemented in the final device design. The results of the simulation serve as a feasibility test for the design concept and provide supportive evidence of the effectiveness of silicon PV cells as high-voltage power supplies.

Molecular monolayers for electrical passivation and functionalization of silicon-based solar energy devices

NARCIS (Netherlands)

Veerbeek, Janneke; Firet, Nienke J.; Vijselaar, Wouter; Elbersen, R.; Gardeniers, Han; Huskens, Jurriaan

2017-01-01

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based

Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

International Nuclear Information System (INIS)

Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

2008-01-01

Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

Nanofluidic channels of arbitrary shapes fabricated by tip-based nanofabrication

International Nuclear Information System (INIS)

Hu, Huan; Cunningham, Brian T; King, William P; Zhuo, Yue; Oruc, Muhammed E

2014-01-01

Nanofluidic channels have promising applications in biomolecule manipulation and sensing. While several different methods of fabrication have been demonstrated for nanofluidic channels, a rapid, low-cost fabrication method that can fabricate arbitrary shapes of nanofluidic channels is still in demand. Here, we report a tip-based nanofabrication (TBN) method for fabricating nanofluidic channels using a heated atomic force microscopy (AFM) tip. The heated AFM tip deposits polymer nanowires where needed to serve as etch mask to fabricate silicon molds through one step of etching. PDMS nanofluidic channels are easily fabricated through replicate molding using the silicon molds. Various shapes of nanofluidic channels with either straight or curvilinear features are demonstrated. The width of the nanofluidic channels is 500 nm, and is determined by the deposited polymer nanowire width. The height of the channel is 400 nm determined by the silicon etching time. Ion conductance measurement on one single curvy shaped nanofluidic channel exhibits the typical ion conductance saturation phenomenon as the ion concentration decreases. Moreover, fluorescence imaging of fluid flowing through a fabricated nanofluidic channel demonstrates the channel integrity. This TBN process is seamlessly compatible with existing nanofabrication processes and can be used to achieve new types of nanofluidic devices. (paper)

Emerging Trends in Phosphorene Fabrication towards Next Generation Devices.

Science.gov (United States)

Dhanabalan, Sathish Chander; Ponraj, Joice Sophia; Guo, Zhinan; Li, Shaojuan; Bao, Qiaoliang; Zhang, Han

2017-06-01

The challenge of science and technology is to design and make materials that will dominate the future of our society. In this context, black phosphorus has emerged as a new, intriguing two-dimensional (2D) material, together with its monolayer, which is referred to as phosphorene. The exploration of this new 2D material demands various fabrication methods to achieve potential applications- this demand motivated this review. This article is aimed at supplementing the concrete understanding of existing phosphorene fabrication techniques, which forms the foundation for a variety of applications. Here, the major issue of the degradation encountered in realizing devices based on few-layered black phosphorus and phosphorene is reviewed. The prospects of phosphorene in future research are also described by discussing its significance and explaining ways to advance state-of-art of phosphorene-based devices. In addition, a detailed presentation on the demand for future studies to promote well-systemized fabrication methods towards large-area, high-yield and perfectly protected phosphorene for the development of reliable devices in optoelectronic applications and other areas is offered.

Ion-implantation and analysis for doped silicon slot waveguides

Directory of Open Access Journals (Sweden)

McCallum J. C.

2012-10-01

Full Text Available We have utilised ion implantation to fabricate silicon nanocrystal sensitised erbium-doped slot waveguide structures in a Si/SiO2/Si layered configuration and photoluminescence (PL and Rutherford backscattering spectrometry (RBS to analyse these structures. Slot waveguide structures in which light is confined to a nanometre-scale low-index region between two high-index regions potentially offer significant advantages for realisation of electrically-pumped Si devices with optical gain and possibly quantum optical devices. We are currently investigating an alternative pathway in which high quality thermal oxides are grown on silicon and ion implantation is used to introduce the Er and Si-ncs into the SiO2 layer. This approach provides considerable control over the Er and Si-nc concentrations and depth profiles which is important for exploring the available parameter space and developing optimised structures. RBS is well-suited to compositional analysis of these layered structures. To improve the depth sensitivity we have used a 1 MeV α beam and results indicate that a layered silicon-Er:SiO2/silicon structure has been fabricated as desired. In this paper structural results will be compared to Er photoluminescence profiles for samples processed under a range of conditions.

FABRICATION, MORPHOLOGICAL AND OPTOELECTRONIC PROPERTIES OF ANTIMONY ON POROUS SILICON AS MSM PHOTODETECTOR

Directory of Open Access Journals (Sweden)

H. A. Hadi

2015-07-01

Full Text Available We report on the fabrication and characterization of MSM photodetector. We investigated the surface morphological and the structural properties of the porous silicon by optical microscopy, atomic force microscope (AFM and X-ray diffraction. The metal–semiconductor–metal photodetector were fabricated by using Sb as Schottky contact metal.The junction exhibits good rectification ratio of 105 at bias of 2V. A large photocurrent to dark-current contrast ratio higher than 55 orders of magnitude and low dark currents below 0.89 nA .High   responsivity of 0.225A/W at 400 nm and 0.15 A/W at 400 and 700nm were observed at an operating bias of less than -2 V, corresponding quantum efficiency of 70% and 26% respectively. The lifetimes are evaluated using OCVD method and the carrier life time is 100 μs. The results show that Sb on porous silicon (PS structures will act as good candidates for making highly efficient photodiodes.

FABRICATION, MORPHOLOGICAL AND OPTOELECTRONIC PROPERTIES OF ANTIMONY ON POROUS SILICON AS MSM PHOTODETECTOR

Directory of Open Access Journals (Sweden)

H. A. Hadi

2014-12-01

Full Text Available We report on the fabrication and characterization of MSM photodetector. We investigated the surface morphological and the structural properties of the porous silicon by optical microscopy, atomic force microscope (AFM and X-ray diffraction. The metal–semiconductor–metal photodetector were fabricated by using Sb as Schottky contact metal.The junction exhibits good rectification ratio of 105 at bias of 2V. A large photocurrent to dark-current contrast ratio higher than 55 orders of magnitude and low dark currents below 0.89 nA .High responsivity of 0.225A/W at 400 nm and 0.15 A/W at 400 and 700nm were observed at an operating bias of less than -2 V, corresponding quantum efficiency of 70% and 26% respectively. The lifetimes are evaluated using OCVD method and the carrier life time is 100 μs. The results show that Sb on porous silicon (PS structures will act as good candidates for making highly efficient photodiodes.

Durable Superomniphobic Surface on Cotton Fabrics via Coating of Silicone Rubber and Fluoropolymers

Directory of Open Access Journals (Sweden)

Arsheen Moiz

2018-03-01

Full Text Available Performance textiles that protect human from different threats and dangers from environment are in high demand, and the advancement in functionalization technology together with employing advanced materials have made this an area of research focus. In this work, silicone rubber and environmentally friendly fluoropolymers have been employed to explore superomniphobic surface on cotton fabrics without compromising comfort much. It has been found that a cross-linked network between the rubber membrane and the fluoropolymers has been formed. The surface appearance, morphology, handle, thickness and chemical components of the surface of cotton fabrics have been changed. The coated fabrics showed resistance to water, aqueous liquid, oil, chemicals and soil. The comfort of the coated fabrics is different to uncoated cotton fabrics due to the existence of coated layers on the surface of cotton fabrics. This work would benefit the development and design of the next generation of performance textiles with balanced performance and comfort.

Micro fabrication of biodegradable polymer drug delivery devices

DEFF Research Database (Denmark)

Nagstrup, Johan

The pharmaceutical industry is presently facing several obstacles in developing oral drug delivery systems. This is primarily due to the nature of the discovered drug candidates. The discovered drugs often have poor solubility and low permeability across the gastro intestinal epithelium. Furtherm......The pharmaceutical industry is presently facing several obstacles in developing oral drug delivery systems. This is primarily due to the nature of the discovered drug candidates. The discovered drugs often have poor solubility and low permeability across the gastro intestinal epithelium...... permeability and degradation. These systems are for the majority based on traditional materials used in micro technology, such as SU-8, silicon, poly(methyl methacrylate). The next step in developing these new drug delivery systems is to replace classical micro fabrication materials with biodegradable polymers....... In order to successfully do this, methods for fabricating micro structures in biodegradable polymers need to be developed. The goal of this project has been to develop methods for micro fabrication in biodegradable polymers and to use these methods to produce micro systems for oral drug delivery. This has...

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.

2018-01-15

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent, with Kaneka setting the world\\'s silicon solar cell efficiency record of 26.63% using silicon heterojunction contacts in an interdigitated configuration. Although passivating-contact solar cells are remarkably efficient, their underlying device physics is not yet completely understood, not in the least because they are constructed from diverse materials that may introduce electronic barriers in the current flow. To bridge this gap in understanding, we explore the device physics of passivating contact silicon heterojunction (SHJ) solar cells. Here, we identify the key properties of heterojunctions that affect cell efficiency, analyze the dependence of key heterojunction properties on carrier transport under light and dark conditions, provide a self-consistent multiprobe approach to extract heterojunction parameters using several characterization techniques (including dark J-V, light J-V, C-V, admittance spectroscopy, and Suns-Voc), propose design guidelines to address bottlenecks in energy production in SHJ cells, and develop a process-to-module modeling framework to establish the module\\'s performance limits. We expect that our proposed guidelines resulting from this multiscale and self-consistent framework will improve the performance of future SHJ cells as well as other passivating contact-based solar cells.

Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

Science.gov (United States)

Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

2017-04-03

We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

Friction and dynamically dissipated energy dependence on temperature in polycrystalline silicon MEMS devices

NARCIS (Netherlands)

Gkouzou, A.; Kokorian, J.; Janssen, G.C.A.M.; van Spengen, W.M.

2017-01-01

In this paper, we report on the influence of capillary condensation on the sliding friction of sidewall surfaces in polycrystalline silicon micro-electromechanical
systems (MEMS). We developed a polycrystalline silicon MEMS tribometer, which is a microscale test device with two components

Enhancing the Efficiency of Silicon-Based Solar Cells by the Piezo-Phototronic Effect.

Science.gov (United States)

Zhu, Laipan; Wang, Longfei; Pan, Caofeng; Chen, Libo; Xue, Fei; Chen, Baodong; Yang, Leijing; Su, Li; Wang, Zhong Lin

2017-02-28

Although there are numerous approaches for fabricating solar cells, the silicon-based photovoltaics are still the most widely used in industry and around the world. A small increase in the efficiency of silicon-based solar cells has a huge economic impact and practical importance. We fabricate a silicon-based nanoheterostructure (p + -Si/p-Si/n + -Si (and n-Si)/n-ZnO nanowire (NW) array) photovoltaic device and demonstrate the enhanced device performance through significantly enhanced light absorption by NW array and effective charge carrier separation by the piezo-phototronic effect. The strain-induced piezoelectric polarization charges created at n-doped Si-ZnO interfaces can effectively modulate the corresponding band structure and electron gas trapped in the n + -Si/n-ZnO NW nanoheterostructure and thus enhance the transport process of local charge carriers. The efficiency of the solar cell was improved from 8.97% to 9.51% by simply applying a static compress strain. This study indicates that the piezo-phototronic effect can enhance the performance of a large-scale silicon-based solar cell, with great potential for industrial applications.

Inkjet 3D printing of UV and thermal cure silicone elastomers for dielectric elastomer actuators

Science.gov (United States)

McCoul, David; Rosset, Samuel; Schlatter, Samuel; Shea, Herbert

2017-12-01

Dielectric elastomer actuators (DEAs) are an attractive form of electromechanical transducer, possessing high energy densities, an efficient design, mechanical compliance, high speed, and noiseless operation. They have been incorporated into a wide variety of devices, such as microfluidic systems, cell bioreactors, tunable optics, haptic displays, and actuators for soft robotics. Fabrication of DEA devices is complex, and the majority are inefficiently made by hand. 3D printing offers an automated and flexible manufacturing alternative that can fabricate complex, multi-material, integrated devices consistently and in high resolution. We present a novel additive manufacturing approach to DEA devices in which five commercially available, thermal and UV-cure DEA silicone rubber materials have been 3D printed with a drop-on-demand, piezoelectric inkjet system. Using this process, 3D structures and high-quality silicone dielectric elastomer membranes as thin as 2 μm have been printed that exhibit mechanical and actuation performance at least as good as conventionally blade-cast membranes. Printed silicone membranes exhibited maximum tensile strains of up to 727%, and DEAs with printed silicone dielectrics were actuated up to 6.1% area strain at a breakdown strength of 84 V μm-1 and also up to 130 V μm-1 at 2.4% strain. This approach holds great potential to manufacture reliable, high-performance DEA devices with high throughput.

Fabrication and Characterization of Silicon Micro-Funnels and Tapered Micro-Channels for Stochastic Sensing Applications

Directory of Open Access Journals (Sweden)

Frances S. Ligler

2008-06-01

Full Text Available We present a simplified, highly reproducible process to fabricate arrays of tapered silicon micro-funnels and micro-channels using a single lithographic step with a silicon oxide (SiO2 hard mask on at a wafer scale. Two approaches were used for the fabrication. The first one involves a single wet anisotropic etch step in concentrated potassium hydroxide (KOH and the second one is a combined approach comprising Deep Reactive Ion Etch (DRIE followed by wet anisotropic etching. The etching is performed through a 500 mm thick silicon wafer, and the resulting structures are characterized by sharp tapered ends with a sub-micron cross-sectional area at the tip. We discuss the influence of various parameters involved in the fabrication such as the size and thickness variability of the substrate, dry and wet anisotropic etching conditions, the etchant composition, temperature, diffusion and micro-masking effects, the quality of the hard mask in the uniformity and reproducibility of the structures, and the importance of a complete removal of debris and precipitates. The presence of apertures at the tip of the structures is corroborated through current voltage measurements and by the translocation of DNA through the apertures. The relevance of the results obtained in this report is discussed in terms of the potential use of these structures for stochastic sensing.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Controlling the flow of light with silicon nanostructures

International Nuclear Information System (INIS)

Park, W

2010-01-01

Silicon is an important material for integrated photonics applications. High refractive index and transparency in the infrared region makes it an ideal platform to implement nanostructures for novel optical devices. We fabricated silicon photonic crystals and experimentally demonstrated negative refraction and self-collimation. We also used heterodyne near-field scanning optical microscope to directly visualize the anomalous wavefronts. When the periodicity is much smaller than wavelength, silicon photonic crystal can be described by the effective medium theory. By engineering effective refractive index with silicon nanorod size, we demonstrated an all-dielectric cloak structure which can hide objects in front of a highly reflecting plane. The work discussed in this review shows the powerful design flexibility and versatility of silicon nanostructures

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Fabrication of microfluidic architectures for optimal flow rate and concentration measurement for lab on chip application

Science.gov (United States)

Adam, Tijjani; Hashim, U.

2017-03-01

Optimum flow in micro channel for sensing purpose is challenging. In this study, The optimizations of the fluid sample flows are made through the design and characterization of the novel microfluidics' architectures to achieve the optimal flow rate in the micro channels. The biocompatibility of the Polydimetylsiloxane (Sylgard 184 silicon elastomer) polymer used to fabricate the device offers avenue for the device to be implemented as the universal fluidic delivery system for bio-molecules sensing in various bio-medical applications. The study uses the following methodological approaches, designing a novel microfluidics' architectures by integrating the devices on a single 4 inches silicon substrate, fabricating the designed microfluidic devices using low-cost solution soft lithography technique, characterizing and validating the flow throughput of urine samples in the micro channels by generating pressure gradients through the devices' inlets. The characterization on the urine samples flow in the micro channels have witnessed the constant flow throughout the devices.

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.; De Wolf, Stefaan; Alam, Muhammad A.

2018-01-01

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent

Integrating nanosphere lithography in device fabrication

Science.gov (United States)

Laurvick, Tod V.; Coutu, Ronald A.; Lake, Robert A.

2016-03-01

This paper discusses the integration of nanosphere lithography (NSL) with other fabrication techniques, allowing for nano-scaled features to be realized within larger microelectromechanical system (MEMS) based devices. Nanosphere self-patterning methods have been researched for over three decades, but typically not for use as a lithography process. Only recently has progress been made towards integrating many of the best practices from these publications and determining a process that yields large areas of coverage, with repeatability and enabled a process for precise placement of nanospheres relative to other features. Discussed are two of the more common self-patterning methods used in NSL (i.e. spin-coating and dip coating) as well as a more recently conceived variation of dip coating. Recent work has suggested the repeatability of any method depends on a number of variables, so to better understand how these variables affect the process a series of test vessels were developed and fabricated. Commercially available 3-D printing technology was used to incrementally alter the test vessels allowing for each variable to be investigated individually. With these deposition vessels, NSL can now be used in conjunction with other fabrication steps to integrate features otherwise unattainable through current methods, within the overall fabrication process of larger MEMS devices. Patterned regions in 1800 series photoresist with a thickness of ~700nm are used to capture regions of self-assembled nanospheres. These regions are roughly 2-5 microns in width, and are able to control the placement of 500nm polystyrene spheres by controlling where monolayer self-assembly occurs. The resulting combination of photoresist and nanospheres can then be used with traditional deposition or etch methods to utilize these fine scale features in the overall design.

Development of a Multi-User Polyimide-MEMS Fabrication Process and its Application to MicroHotplates

KAUST Repository

Lizardo, Ernesto B.

2013-05-08

Micro-electro-mechanical systems (MEMS) became possible thanks to the silicon based technology used to fabricate integrated circuits. Originally, MEMS fabrication was limited to silicon based techniques and materials, but the expansion of MEMS applications brought the need of a wider catalog of materials, including polymers, now being used to fabricate MEMS. Polyimide is a very attractive polymer for MEMS fabrication due to its high temperature stability compared to other polymers, low coefficient of thermal expansion, low film stress and low cost. The goal of this thesis is to expand the Polyimide usage as structural material for MEMS by the development of a multi-user fabrication process for the integration of this polymer along with multiple metal layers on a silicon substrate. The process also integrates amorphous silicon as sacrificial layer to create free-standing structures. Dry etching is used to release the devices and avoid stiction phenomena. The developed process is used to fabricate platforms for micro-hotplate gas sensors. The fabrication steps for the platforms are described in detail, explaining the process specifics and capabilities. An initial testing of the micro-hotplate is presented. As the process was also used as educational tool, some designs made by students and fabricated with the Polyimide-MEMS process are also presented.

Role of the inversion layer on the charge injection in silicon nanocrystal multilayered light emitting devices

Energy Technology Data Exchange (ETDEWEB)

Tondini, S. [Nanoscience Laboratory, Department of Physics, University of Trento, Via Sommarive 14, 38123 Trento (Italy); Dipartimento di Fisica, Informatica e Matematica, Università di Modena e Reggio Emilia, Via Campi 213/a, 41125 Modena (Italy); Pucker, G. [Advanced Photonics and Photovoltaics Group, Bruno Kessler Foundation, Via Sommarive 18, 38123 Trento (Italy); Pavesi, L. [Nanoscience Laboratory, Department of Physics, University of Trento, Via Sommarive 14, 38123 Trento (Italy)

2016-09-07

The role of the inversion layer on injection and recombination phenomena in light emitting diodes (LEDs) is here studied on a multilayer (ML) structure of silicon nanocrystals (Si-NCs) embedded in SiO{sub 2}. Two Si-NC LEDs, which are similar for the active material but different in the fabrication process, elucidate the role of the non-radiative recombination rates at the ML/substrate interface. By studying current- and capacitance-voltage characteristics as well as electroluminescence spectra and time-resolved electroluminescence under pulsed and alternating bias pumping scheme in both the devices, we are able to ascribe the different experimental results to an efficient or inefficient minority carrier (electron) supply by the p-type substrate in the metal oxide semiconductor LEDs.

ZnO nanocoral reef grown on porous silicon substrates without catalyst

International Nuclear Information System (INIS)

Abdulgafour, H.I.; Yam, F.K.; Hassan, Z.; AL-Heuseen, K.; Jawad, M.J.

2011-01-01

Research highlights: → Porous silicon (PS) technology is utilized to grow coral reef-like ZnO nanostructures on the surface of Si substrates. → Flower-like aligned ZnO nanorods are fabricated directly onto the silicon substrates through zinc powder evaporation using a simple thermal evaporation method without a catalyst for comparison. → The PL spectra show that for ZnO nanocoral reefs the UV emission shifts slightly towards lower frequency. → This non-catalyst growth technique on the rough surface of substrates may have potential applications in the fabrication of nanoelectronic and nanooptical devices. - Abstract: Porous silicon (PS) technology is utilized to grow coral reef-like ZnO nanostructures on the surface of Si substrates with rough morphology. Flower-like aligned ZnO nanorods are also fabricated directly onto the silicon substrates through zinc powder evaporation using a simple thermal evaporation method without a catalyst for comparison. The characteristics of these nanostructures are investigated using field-emission scanning electron microscopy, grazing-angle X-ray diffraction (XRD), and photoluminescence (PL) measurements of structures grown on both Si and porous Si substrates. The texture coefficient obtained from the XRD spectra indicates that the coral reef-like nanostructures are highly oriented on the porous silicon substrate with decreasing nanorods length and diameter from 800-900 nm to 3.5-5.5 μm and from 217-229 nm to 0.6-0.7 μm, respectively. The PL spectra show that for ZnO nanocoral reefs the UV emission shifts slightly towards lower frequency and the intensity increase with the improvement of ZnO crystallization. This non-catalyst growth technique on the rough surface of substrates may have potential applications in the fabrication of nanoelectronic and nanooptical devices.

ZnO nanocoral reef grown on porous silicon substrates without catalyst

Energy Technology Data Exchange (ETDEWEB)

Abdulgafour, H.I., E-mail: hind_alshaikh@yahoo.com [School of Physics, University Sains Malaysia 11800 Penang (Malaysia); Yam, F.K.; Hassan, Z.; AL-Heuseen, K.; Jawad, M.J. [School of Physics, University Sains Malaysia 11800 Penang (Malaysia)

2011-05-05

Research highlights: > Porous silicon (PS) technology is utilized to grow coral reef-like ZnO nanostructures on the surface of Si substrates. > Flower-like aligned ZnO nanorods are fabricated directly onto the silicon substrates through zinc powder evaporation using a simple thermal evaporation method without a catalyst for comparison. > The PL spectra show that for ZnO nanocoral reefs the UV emission shifts slightly towards lower frequency. > This non-catalyst growth technique on the rough surface of substrates may have potential applications in the fabrication of nanoelectronic and nanooptical devices. - Abstract: Porous silicon (PS) technology is utilized to grow coral reef-like ZnO nanostructures on the surface of Si substrates with rough morphology. Flower-like aligned ZnO nanorods are also fabricated directly onto the silicon substrates through zinc powder evaporation using a simple thermal evaporation method without a catalyst for comparison. The characteristics of these nanostructures are investigated using field-emission scanning electron microscopy, grazing-angle X-ray diffraction (XRD), and photoluminescence (PL) measurements of structures grown on both Si and porous Si substrates. The texture coefficient obtained from the XRD spectra indicates that the coral reef-like nanostructures are highly oriented on the porous silicon substrate with decreasing nanorods length and diameter from 800-900 nm to 3.5-5.5 {mu}m and from 217-229 nm to 0.6-0.7 {mu}m, respectively. The PL spectra show that for ZnO nanocoral reefs the UV emission shifts slightly towards lower frequency and the intensity increase with the improvement of ZnO crystallization. This non-catalyst growth technique on the rough surface of substrates may have potential applications in the fabrication of nanoelectronic and nanooptical devices.

Micromachined silicon seismic accelerometer development

Energy Technology Data Exchange (ETDEWEB)

Barron, C.C.; Fleming, J.G.; Montague, S. [and others

1996-08-01

Batch-fabricated silicon seismic transducers could revolutionize the discipline of seismic monitoring by providing inexpensive, easily deployable sensor arrays. Our ultimate goal is to fabricate seismic sensors with sensitivity and noise performance comparable to short-period seismometers in common use. We expect several phases of development will be required to accomplish that level of performance. Traditional silicon micromachining techniques are not ideally suited to the simultaneous fabrication of a large proof mass and soft suspension, such as one needs to achieve the extreme sensitivities required for seismic measurements. We have therefore developed a novel {open_quotes}mold{close_quotes} micromachining technology that promises to make larger proof masses (in the 1-10 mg range) possible. We have successfully integrated this micromolding capability with our surface-micromachining process, which enables the formation of soft suspension springs. Our calculations indicate that devices made in this new integrated technology will resolve down to at least sub-{mu}G signals, and may even approach the 10{sup -10} G/{radical}Hz acceleration levels found in the low-earth-noise model.

Mesoporous silicon particles as intravascular drug delivery vectors: fabrication, in-vitro, and in-vivo assessments

International Nuclear Information System (INIS)

Chiappini, Ciro; Tasciotti, Ennio; Serda, Rita E.; Brousseau, Lou; Liu, Xuewu; Ferrari, M.

2011-01-01

Porous silicon is an attractive biomaterial for drug delivery thanks to its biocompatibility, biodegradability, ease of fabrication, tunable nanostructure, and porous network. Herein we briefly present the development of a multi-stage delivery vector that leverages these advantages to enhance delivery of systemically administered therapeutic agents. We illustrate the rational design, objective-oriented fabrication and geometric control of first stage porous silicon microparticles. We describe how geometry affects the biodistribution of first stage vectors and how their porous structure affects the loading and release of second stage theranostic payloads. We describe the mechanism of cellular internalization and intracellular trafficking of particles. Finally we present two multi-stage vector prototypes for the delivery of magnetic resonance imaging contrast agents and small interfering RNA (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Mesoporous silicon particles as intravascular drug delivery vectors: fabrication, in-vitro, and in-vivo assessments

Energy Technology Data Exchange (ETDEWEB)

Chiappini, Ciro [Department of Biomedical Engineering, University of Texas at Austin, 1 University Station, Austin, TX, 78712 (United States); Tasciotti, Ennio; Serda, Rita E.; Brousseau, Lou; Liu, Xuewu [Department of Nanomedicine and Biomedical Engineering, Mehtodist Hospital Research Institute, 6565 Fannin Street, Houston, TX, 77030 (United States); Ferrari, M. [Department of Biomedical Engineering, University of Texas at Austin, 1 University Station, Austin, TX, 78712 (United States); Department of Nanomedicine and Biomedical Engineering, Mehtodist Hospital Research Institute, 6565 Fannin Street, Houston, TX, 77030 (United States); Department of Experimental Therapeutics, University of Texas MD Anderson Cancer Center, Houston, TX (United States); Department of Bioengineering, Rice University, Houston, TX (United States)

2011-06-15

Porous silicon is an attractive biomaterial for drug delivery thanks to its biocompatibility, biodegradability, ease of fabrication, tunable nanostructure, and porous network. Herein we briefly present the development of a multi-stage delivery vector that leverages these advantages to enhance delivery of systemically administered therapeutic agents. We illustrate the rational design, objective-oriented fabrication and geometric control of first stage porous silicon microparticles. We describe how geometry affects the biodistribution of first stage vectors and how their porous structure affects the loading and release of second stage theranostic payloads. We describe the mechanism of cellular internalization and intracellular trafficking of particles. Finally we present two multi-stage vector prototypes for the delivery of magnetic resonance imaging contrast agents and small interfering RNA (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Quantitative measurements of C-reactive protein using silicon nanowire arrays

Directory of Open Access Journals (Sweden)

Min-Ho Lee

2008-03-01

Full Text Available Min-Ho Lee, Kuk-Nyung Lee, Suk-Won Jung, Won-Hyo Kim, Kyu-Sik Shin, Woo-Kyeong SeongKorea Electronics Technology Institute, Gyeonggi, KoreaAbstract: A silicon nanowire-based sensor for biological application showed highly desirable electrical responses to either pH changes or receptor-ligand interactions such as protein disease markers, viruses, and DNA hybridization. Furthermore, because the silicon nanowire can display results in real-time, it may possess superior characteristics for biosensing than those demonstrated in previously studied methods. However, despite its promising potential and advantages, certain process-related limitations of the device, due to its size and material characteristics, need to be addressed. In this article, we suggest possible solutions. We fabricated silicon nanowire using a top-down and low cost micromachining method, and evaluate the sensing of molecules after transfer and surface modifications. Our newly designed method can be used to attach highly ordered nanowires to various substrates, to form a nanowire array device, which needs to follow a series of repetitive steps in conventional fabrication technology based on a vapor-liquid-solid (VLS method. For evaluation, we demonstrated that our newly fabricated silicon nanowire arrays could detect pH changes as well as streptavidin-biotin binding events. As well as the initial proof-of-principle studies, C-reactive protein binding was measured: electrical signals were changed in a linear fashion with the concentration (1 fM to 1 nM in PBS containing 1.37 mM of salts. Finally, to address the effects of Debye length, silicon nanowires coupled with antigen proteins underwent electrical signal changes as the salt concentration changed.Keywords: silicon nanowire array, C-reactive protein, vapor-liquid-solid method

Facile fabrication of a silicon nanowire sensor by two size reduction steps for detection of alpha-fetoprotein biomarker of liver cancer

International Nuclear Information System (INIS)

Pham, Van Binh; Pham, Xuan ThanhTung; Phan, Thanh Nhat Khoa; Le, Thi Thanh Tuyen; Dang, Mau Chien

2015-01-01

We present a facile technique that only uses conventional micro-techniques and two size-reduction steps to fabricate wafer-scale silicon nanowire (SiNW) with widths of 200 nm. Initially, conventional lithography was used to pattern SiNW with 2 μm width. Then the nanowire width was decreased to 200 nm by two size-reduction steps with isotropic wet etching. The fabricated SiNW was further investigated when used with nanowire field-effect sensors. The electrical characteristics of the fabricated SiNW devices were characterized and pH sensitivity was investigated. Then a simple and effective surface modification process was carried out to modify SiNW for subsequent binding of a desired receptor. The complete SiNW-based biosensor was then used to detect alpha-fetoprotein (AFP), one of the medically approved biomarkers for liver cancer diagnosis. Electrical measurements showed that the developed SiNW biosensor could detect AFP with concentrations of about 100 ng mL"−"1. This concentration is lower than the necessary AFP concentration for liver cancer diagnosis. (paper)

Facile fabrication of a silicon nanowire sensor by two size reduction steps for detection of alpha-fetoprotein biomarker of liver cancer

Science.gov (United States)

Binh Pham, Van; ThanhTung Pham, Xuan; Nhat Khoa Phan, Thanh; Thanh Tuyen Le, Thi; Chien Dang, Mau

2015-12-01

We present a facile technique that only uses conventional micro-techniques and two size-reduction steps to fabricate wafer-scale silicon nanowire (SiNW) with widths of 200 nm. Initially, conventional lithography was used to pattern SiNW with 2 μm width. Then the nanowire width was decreased to 200 nm by two size-reduction steps with isotropic wet etching. The fabricated SiNW was further investigated when used with nanowire field-effect sensors. The electrical characteristics of the fabricated SiNW devices were characterized and pH sensitivity was investigated. Then a simple and effective surface modification process was carried out to modify SiNW for subsequent binding of a desired receptor. The complete SiNW-based biosensor was then used to detect alpha-fetoprotein (AFP), one of the medically approved biomarkers for liver cancer diagnosis. Electrical measurements showed that the developed SiNW biosensor could detect AFP with concentrations of about 100 ng mL-1. This concentration is lower than the necessary AFP concentration for liver cancer diagnosis.

Flash μ-fluidics: a rapid prototyping method for fabricating microfluidic devices

KAUST Repository

Buttner, Ulrich

2016-08-01

Microfluidics has advanced in terms of design and structures; however, fabrication methods are time-consuming or expensive relative to facility costs and equipment needed. This work demonstrates a fast and economically viable 2D/3D maskless digital light-projection method based on a stereolithography process. Unlike other fabrication methods, one exposure step is used to form the whole device. Flash microfluidics is achieved by incorporating bonding and channel fabrication of complex structures in just 2.5 s to 4 s and by fabricating channel heights between 25 μm and 150 μm with photopolymer resin. The features of this fabrication technique, such as time and cost saving and easy fabrication, are used to build devices that are mostly needed in microfluidic/lab-on-chip systems. Due to the fast production method and low initial setup costs, the process could be used for point of care applications. © 2016 The Royal Society of Chemistry.

Flash μ-fluidics: a rapid prototyping method for fabricating microfluidic devices

KAUST Repository

Buttner, Ulrich; Sivashankar, Shilpa; Agambayev, Sumeyra; Mashraei, Yousof; Salama, Khaled N.

2016-01-01

Microfluidics has advanced in terms of design and structures; however, fabrication methods are time-consuming or expensive relative to facility costs and equipment needed. This work demonstrates a fast and economically viable 2D/3D maskless digital light-projection method based on a stereolithography process. Unlike other fabrication methods, one exposure step is used to form the whole device. Flash microfluidics is achieved by incorporating bonding and channel fabrication of complex structures in just 2.5 s to 4 s and by fabricating channel heights between 25 μm and 150 μm with photopolymer resin. The features of this fabrication technique, such as time and cost saving and easy fabrication, are used to build devices that are mostly needed in microfluidic/lab-on-chip systems. Due to the fast production method and low initial setup costs, the process could be used for point of care applications. © 2016 The Royal Society of Chemistry.

Angle-resolved diffraction grating biosensor based on porous silicon

Energy Technology Data Exchange (ETDEWEB)

Lv, Changwu; Li, Peng [School of Physical Science and Technology, Xinjiang University, Urumqi 830046 (China); Jia, Zhenhong, E-mail: jzhh@xju.edu.cn; Liu, Yajun; Mo, Jiaqing; Lv, Xiaoyi [College of Information Science and Engineering, Xinjiang University, Urumqi 830046 (China)

2016-03-07

In this study, an optical biosensor based on a porous silicon composite structure was fabricated using a simple method. This structure consists of a thin, porous silicon surface diffraction grating and a one-dimensional porous silicon photonic crystal. An angle-resolved diffraction efficiency spectrum was obtained by measuring the diffraction efficiency at a range of incident angles. The angle-resolved diffraction efficiency of the 2nd and 3rd orders was studied experimentally and theoretically. The device was sensitive to the change of refractive index in the presence of a biomolecule indicated by the shift of the diffraction efficiency spectrum. The sensitivity of this sensor was investigated through use of an 8 base pair antifreeze protein DNA hybridization. The shifts of the angle-resolved diffraction efficiency spectrum showed a relationship with the change of the refractive index, and the detection limit of the biosensor reached 41.7 nM. This optical device is highly sensitive, inexpensive, and simple to fabricate. Using shifts in diffraction efficiency spectrum to detect biological molecules has not yet been explored, so this study establishes a foundation for future work.

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

Science.gov (United States)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were

Fabrication of a Microfluidic Device with Boron-doped Diamond Electrodes for Electrochemical Analysis

International Nuclear Information System (INIS)

Watanabe, Takeshi; Shibano, Shuhei; Maeda, Hideto; Sugitani, Ai; Katayama, Michinobu; Matsumoto, Yoshinori; Einaga, Yasuaki

2016-01-01

A prototype microfluidic device using boron-doped diamond (BDD) electrodes patterned on an alumina chip was designed and fabricated. Electrochemical microfluidic devices have advantages in that the amount of sample required is small, the measurement throughput is high, different functions can be integrated on a single device, and they are highly durable. In using the device for the flow injection analysis of oxalic acid, the application of a brief conditioning step ensured that the reproducibility of the current signal was excellent. Furthermore, the fabricated system also performed as a prototype of “elimination-detection flow system”, in which interfering species are eliminated using “elimination electrodes” prior to the species reaching the “detection electrode”. The fabricated device reduced the current due to interfering species by 78%. Designs of devices to improve this efficiency are also discussed.

Direct spraying method for fabrication of paper-based microfluidic devices

International Nuclear Information System (INIS)

Liu, Ning; An, Hong-Jie; Lew, Wen Siang; Xu, Jing; Phan, Dinh-Tuan; Hashimoto, Michinao

2017-01-01

Direct spraying of hydrophobic materials is an affordable, easy-to-use and equipment-free method for fabrication of flexible microsensors, albeit not yet widely adopted. To explore its application potential, in this paper, we propose and demonstrate two novel hybrid methods to fabricate paper-based components. Firstly, through combing direct spraying with Parafilm embedding, a leak-free paper-based sample preconcentrator for fluorescence sensing was fabricated. The leak-free device worked on the principle of ion concentration polarization (ICP) effect, and achieved enhancement of fluorescent tracer by 220 folds on a paper substrate. Secondly, by using the sprayed hydrophobic patterns, paper-based microsized supercapacitors (mSCs) were fabricated. Vacuum filtration was used to deposit multi-wall carbon nanotubes (MWCNT)-dispersed solution on a porous substrate to form electrodes. A volumetric capacitance of 42.5 mF cm −3 at a current density of 2 mA cm −3 was obtained on the paper-based mSC. Our demonstrations have shown the versatility of direct spraying for the fabrication of integrative paper-based microfluidic devices. (paper)

Interaction of Light with Metallized Ultrathin Silicon Membrane

Science.gov (United States)

Shome, Krishanu

Freestanding metallized structures, a few tens of nanometer thick, show promise in creating flow-through sensors, single molecule detectors and novel solar cells. In this thesis we study test structures that are a step towards creating such devices. Finite- difference time-domain simulations have been used to understand and predict the interaction of light with such devices. Porous nanocrystalline silicon membrane is a novel freestanding layer structure that has been used as a platform to fabricate and study sensors and novel slot nanohole devices. Optical mode studies of the sensing structures, together with the method of fabrication inspired the creation of ultrathin freestanding hydrogenated amorphous silicon p-i-n junctions solar cells. All the freestanding structures used in this thesis are just a few tens of nanometers in thicknesses. In the first part of the thesis the sensing properties of the metallized porous nanocrystalline structure are studied. The surprising blueshift associated with the sensing peak is observed experimentally and predicted theoretically with the help of simulations. Polarization dependence of the membranes is predicted and confirmed for angled deposition of metal on the membranes. In the next part, a novel slot structure is fabricated and modeled to study the slot effect in nanohole metal-insulator-metal structures. Atomic layer deposition of alumina is used to conformally deposit alumina within the nanohole to create the slot structure. Simulation models were used to calculate the lowest modal volume of 4x10-5 mum3 for an optimized structure. In the last part of the thesis, freestanding solar cells are fabricated by effectively replacing the porous nanocrystalline silicon layer of the membranes with a hydrogenated amorphous silicon p-i-n junction with metal layers on both sides of the p-i-n junction. The metal layers act both as electrical contacts as well as mirrors for a Fabry Perot cavity resonator. This helps in tuning the

Fabrication of Extrinsically Conductive Silicone Rubbers with High Elasticity and Analysis of Their Mechanical and Electrical Characteristics

Directory of Open Access Journals (Sweden)

Anjum Saleem

2010-08-01

Full Text Available Conductive plastics are attracting more and more interest in electronics due to their light weight and inability to rust, which are common problems associated with metals. The field of conducting plastics is not new. Much work has been done to impart electrical conductivity to mechanically strong polymers such as polypropylene, polycarbonate and epoxies, etc. However there is a need to fabricate more flexible and elastic conductive polymers such as conducting silicone rubbers for use in various applications. In this work silicone rubbers reinforced with conductive fillers have been fabricated for use as sensors in textiles to detect the resistance change produced by stretching or relaxing. The variations of electrical resistance have been investigated by stretching and releasing the strands of conductive rubbers as a function of time. Two types of silicone rubbers—addition cured and condensation cured—were compounded with different electrically conductive fillers, among which carbon fibers have shown the best results. The carbon fibers improved the electrical conductance of the rubbers, even in very low weight percentages. The increasing concentration of fillers decreases the elasticity of the rubber. In order to keep the original properties of silicones, the filler concentration was kept as low as possible to produce a significantly detectable signal. The fabricated compounds were analyzed for their mechanical properties by stress strain curves. Such materials find their applications in electronics, antistatic applications, sports and the automotive industry where they can be used as deformation sensors.

Assessing the potential roles of silicon and germanium phthalocyanines in planar heterojunction organic photovoltaic devices and how pentafluoro phenoxylation can enhance π-π interactions and device performance.

Science.gov (United States)

Lessard, Benoît H; White, Robin T; Al-Amar, Mohammad; Plint, Trevor; Castrucci, Jeffrey S; Josey, David S; Lu, Zheng-Hong; Bender, Timothy P

2015-03-11

In this study, we have assessed the potential application of dichloro silicon phthalocyanine (Cl2-SiPc) and dichloro germanium phthalocyanine (Cl2-GePc) in modern planar heterojunction organic photovoltaic (PHJ OPV) devices. We have determined that Cl2-SiPc can act as an electron donating material when paired with C60 and that Cl2-SiPc or Cl2-GePc can also act as an electron acceptor material when paired with pentacene. These two materials enabled the harvesting of triplet energy resulting from the singlet fission process in pentacene. However, contributions to the generation of photocurrent were observed for Cl2-SiPc with no evidence of photocurrent contribution from Cl2-GePc. The result of our initial assessment established the potential for the application of SiPc and GePc in PHJ OPV devices. Thereafter, bis(pentafluoro phenoxy) silicon phthalocyanine (F10-SiPc) and bis(pentafluoro phenoxy) germanium phthalocyanine (F10-GePc) were synthesized and characterized. During thermal processing, it was discovered that F10-SiPc and F10-GePc underwent a reaction forming small amounts of difluoro SiPc (F2-SiPc) and difluoro GePc (F2-GePc). This undesirable reaction could be circumvented for F10-SiPc but not for F10-GePc. Using single crystal X-ray diffraction, it was determined that F10-SiPc has significantly enhanced π-π interactions compared with that of Cl2-SiPc, which had little to none. Unoptimized PHJ OPV devices based on F10-SiPc were fabricated and directly compared to those constructed from Cl2-SiPc, and in all cases, PHJ OPV devices based on F10-SiPc had significantly improved device characteristics compared to Cl2-SiPc.

Fabrication of a Miniature Paper-Based Electroosmotic Actuator

Directory of Open Access Journals (Sweden)

Deepa Sritharan

2016-11-01

Full Text Available A voltage-controlled hydraulic actuator is presented that employs electroosmotic fluid flow (EOF in paper microchannels within an elastomeric structure. The microfluidic device was fabricated using a new benchtop lamination process. Flexible embedded electrodes were formed from a conductive carbon-silicone composite. The pores in the layer of paper placed between the electrodes served as the microchannels for EOF, and the pumping fluid was propylene carbonate. A sealed fluid-filled chamber was formed by film-casting silicone to lay an actuating membrane over the pumping liquid. Hydraulic force generated by EOF caused the membrane to bulge by hundreds of micrometers within fractions of a second. Potential applications of these actuators include soft robots and biomedical devices.

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics

Directory of Open Access Journals (Sweden)

Sandro Rao

2016-01-01

Full Text Available Hydrogenated amorphous silicon (a-Si:H shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34–40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

Development of a fabrication technology for double-sided AC-coupled silicon microstrip detectors

International Nuclear Information System (INIS)

Dalla Betta, G.-F.; Boscardin, M.; Bosisio, L.; Rachevskaia, I.; Zen, M.; Zorzi, N.

2001-01-01

We report on the development of a fabrication technology for double-sided, AC-coupled silicon microstrip detectors for tracking applications. Two batches of detectors with good electrical figures and a low defect rate were successfully manufactured at IRST Laboratory. The processing techniques and the experimental results obtained from these detector prototypes are presented and discussed

GaN Nanowire Devices: Fabrication and Characterization

Science.gov (United States)

Scott, Reum

The development of microelectronics in the last 25 years has been characterized by an exponential increase of the bit density in integrated circuits (ICs) with time. Scaling solid-state devices improves cost, performance, and power; as such, it is of particular interest for companies, who gain a market advantage with the latest technology. As a result, the microelectronics industry has driven transistor feature size scaling from 10 μm to ~30 nm during the past 40 years. This trend has persisted for 40 years due to optimization, new processing techniques, device structures, and materials. But when noting processor speeds from the 1970's to 2009 and then again in 2010, the implication would be that the trend has ceased. To address the challenge of shrinking the integrated circuit (IC), current research is centered on identifying new materials and devices that can supplement and/or potentially supplant it. Bottom-up methods tailor nanoscale building blocks---atoms, molecules, quantum dots, and nanowires (NWs)---to be used to overcome these limitations. The Group IIIA nitrides (InN, AlN, and GaN) possess appealing properties such as a direct band gap spanning the whole solar spectrum, high saturation velocity, and high breakdown electric field. As a result nanostructures and nanodevices made from GaN and related nitrides are suitable candidates for efficient nanoscale UV/ visible light emitters, detectors, and gas sensors. To produce devices with such small structures new fabrication methods must be implemented. Devices composed of GaN nanowires were fabricated using photolithography and electron beam lithography. The IV characteristics of these devices were noted under different illuminations and the current tripled from 4.8*10-7 A to 1.59*10 -6 A under UV light which persisted for at least 5hrs.

Fabrication of SU-8 microstructures for analytical microfluidic applications

OpenAIRE

Tuomikoski, Santeri

2007-01-01

Miniaturization of analytical devices has been an ongoing trend to improve performance of analytical tools. These systems have been microfabricated originally of silicon and glass, but polymers have become increasingly popular as alternative materials. Polymers are mostly used because the material costs are lower and fabrication processes are easier. However, those facts depend heavily on the fabrication method and particular polymer. In this thesis the usability of epoxy-polymer SU-8 has bee...

Large-Scale Fabrication of Silicon Nanowires for Solar Energy Applications.

Science.gov (United States)

Zhang, Bingchang; Jie, Jiansheng; Zhang, Xiujuan; Ou, Xuemei; Zhang, Xiaohong

2017-10-11

The development of silicon (Si) materials during past decades has boosted up the prosperity of the modern semiconductor industry. In comparison with the bulk-Si materials, Si nanowires (SiNWs) possess superior structural, optical, and electrical properties and have attracted increasing attention in solar energy applications. To achieve the practical applications of SiNWs, both large-scale synthesis of SiNWs at low cost and rational design of energy conversion devices with high efficiency are the prerequisite. This review focuses on the recent progresses in large-scale production of SiNWs, as well as the construction of high-efficiency SiNW-based solar energy conversion devices, including photovoltaic devices and photo-electrochemical cells. Finally, the outlook and challenges in this emerging field are presented.

Quantum effects in ion implanted devices

International Nuclear Information System (INIS)

Jamieson, D.N.; Chan, V.; Hudson, F.E.; Andresen, S.E.; Yang, C.; Hopf, T.; Hearne, S.M.; Pakes, C.I.; Prawer, S.; Gauja, E.; Dzurak, A.S.; Clark, R.G.

2006-01-01

Fabrication of nanoscale devices that exploit the rules of quantum mechanics to process information presents formidable technical challenges because of the need to control quantum states at the level of individual atoms, electrons or photons. We have used ion implantation to fabricate devices on the scale of 10 nm that have allowed the development and test of nanocircuitry for the control of charge transport at the level of single electrons. This fabrication method is compatible with the construction of devices that employ counted P dopants in Si by employing the technique of ion beam induced charge (IBIC) in which single 14 keV P ions can be implanted into ultra-pure silicon substrates by monitoring on-substrate detector electrodes. We have used IBIC with a MeV nuclear microprobe to map and measure the charge collection efficiency in the development of the electrode structure and show that 100% charge collection efficiency can be achieved. Prototype devices fabricated by this method have been used to investigate quantum effects in the control and transport of single electrons with potential applications to solid state quantum information processing devices

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang

2014-01-01

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Bomben, M., E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Bagolini, A.; Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, L. [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, Pisa (Italy); INFN Sez. di Pisa, Pisa (Italy); Chauveau, J. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

2013-12-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

International Nuclear Information System (INIS)

Bomben, M.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

2013-01-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown