WorldWideScience

Sample records for si-based cmos devices

  1. Applications of Si/SiGe heterostructures to CMOS devices

    International Nuclear Information System (INIS)

    Sidek, R.M.

    1999-03-01

    For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

  2. A new method of preventing bulk-Si CMOS devices from latchup

    International Nuclear Information System (INIS)

    Xu Xianguo; Xu Xi

    2004-01-01

    A new method, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After we study the design of pseudo-latchup path method in detail, a practice and the corresponding simulation result by computer are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but it cannot be used to eliminate the dose rate upset of bulk-Si CMOS devices. (authors)

  3. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  4. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    Science.gov (United States)

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  6. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  7. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

    Science.gov (United States)

    Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

    2014-05-21

    We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

  8. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  9. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  10. Nano-electromechanical switch-CMOS hybrid technology and its applications.

    Science.gov (United States)

    Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

    2011-01-01

    Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

  11. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  12. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  13. A new CMOS SiGeC avalanche photo-diode pixel for IR sensing

    Science.gov (United States)

    Augusto, Carlos; Forester, Lynn; Diniz, Pedro C.

    2009-05-01

    Near-infra-red sensing with silicon is limited by the bandgap of silicon, corresponding to a maximum wavelength of absorption of 1.1 μm. A new type of CMOS sensor is presented, which uses a SiGeC epitaxial film in conjunction with novel device architecture to extend absorption into the infra-red. The SiGeC film composition and thickness determine the spectrum of absorption; in particular for SiGeC superlattices, the layer ordering to create pseudo direct bandgaps is the critical parameter. In this new device architecture, the p-type SiGeC film is grown on an active region surrounded by STI, linked to the S/D region of an adjacent NMOS, under the STI by a floating N-Well. On a n-type active, a P-I-N device is formed, and on a p-type active, a P-I-P device is formed, each sensing different regions of the spectrum. The SiGeC films can be biased for avalanche operation, as the required vertical electric field is confined to the region near the heterojunction interface, thereby not affecting the gate oxide of the adjacent NMOS. With suitable heterojunction and doping profiles, the avalanche region can also be bandgap engineered, allowing for avalanche breakdown voltages that are compatible with CMOS devices.

  14. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  15. CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

    Science.gov (United States)

    Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

  16. Traceable working standards with SI units of radiance for characterizing the measurement performance of investigational clinical NIRF imaging devices

    Science.gov (United States)

    Zhu, Banghe; Rasmussen, John C.; Litorja, Maritoni; Sevick-Muraca, Eva M.

    2017-03-01

    All medical devices for Food and Drug market approval require specifications of performance based upon International System of Units (SI) or units derived from SI for reasons of traceability. Recently, near-infrared fluorescence (NIRF) imaging devices of a variety of designs have emerged on the market and in investigational clinical studies. Yet the design of devices used in the clinical studies vary widely, suggesting variable device performance. Device performance depends upon optimal excitation of NIRF imaging agents, rejection of backscattered excitation and ambient light, and selective collection of fluorescence emanating from the fluorophore. There remains no traceable working standards with SI units of radiance to enable prediction that a given molecular imaging agent can be detected in humans by a given NIRF imaging device. Furthermore, as technologies evolve and as NIRF imaging device components change, there remains no standardized means to track device improvements over time and establish clinical performance without involving clinical trials, often costly. In this study, we deployed a methodology to calibrate luminescent radiance of a stable, solid phantom in SI units of mW/cm2/sr for characterizing the measurement performance of ICCD and IsCMOS camera based NIRF imaging devices, such as signal-to-noise ratio (SNR) and contrast. The methodology allowed determination of superior SNR of the ICCD over the IsCMOS system; comparable contrast of ICCD and IsCMOS depending upon binning strategies.

  17. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    Science.gov (United States)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  18. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  19. Poly-Si gate engineering for advanced CMOS transistors by germanium implantation

    International Nuclear Information System (INIS)

    Bourdon, H.; Juhel, M.; Oudet, B.; Breil, N.; Lenoble, D.

    2005-01-01

    Standard gate materials are compared to Ge implanted poly-Si and deposited poly-SiGe. It is demonstrated in this paper that the electrical resistance of the gate is significantly reduced via the use of poly-SiGe (from 30% to 40% decrease in resistance). Similarly, we show via specific optimization that localized Ge implantation is also suitable to reduce gate resistance. Physical characterizations are performed to determine the 'root' causes at the origin of these improvements. In line with future publications showing strong benefits on CMOS device performance, grain size effects seem to be the main mechanisms explaining the measured improvement

  20. First principle leakage current reduction technique for CMOS devices

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-12-01

    Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

  1. Radiation-hardened bulk Si-gate CMOS microprocessor family

    International Nuclear Information System (INIS)

    Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

    1979-01-01

    RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

  2. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  3. Strain distribution analysis in Si/SiGe line structures for CMOS technology using Raman spectroscopy

    International Nuclear Information System (INIS)

    Hecker, M; Roelke, M; Hermann, P; Zschech, E; Vartanian, V

    2010-01-01

    Strained silicon underneath the field-effect transistor gate increases significantly the charge carrier mobility and thus improves the performance of leading-edge Complementary Metal Oxide Semiconductor (CMOS) devices. For better understanding of the structure-strain relationship on the nanoscale and for optimization of device structures, the measurement of the local strain state has become essential. Raman spectroscopy is used in the present investigation to analyze the strain distribution in and close to silicon/embedded silicon-germanium (SiGe) line structures in conjunction with strain modeling applying finite element analysis. Both experimental results and modeling indicate the impact of geometry on the stress state. An increase of compressive stress within the Si lines is obtained for increasing SiGe line widths and decreasing Si line widths. The stress state within the Si lines is shown to be a mixed one deviating from a pure uniaxial state. Underneath the SiGe cavities, the presence of a tensile stress was observed. To investigate a procedure to scale down the spatial resolution of the Raman measurements, tip-enhanced Raman scattering experiments have been performed on free-standing SiGe lines with 100nm line width and line distance. The results show superior resolution and strain information not attainable in conventional Raman scans.

  4. Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

    Science.gov (United States)

    Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

    2003-05-01

    Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

  5. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Directory of Open Access Journals (Sweden)

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  6. Advanced Optoelectronic Devices based on Si Quantum Dots/Si Nanowires Hetero-structures

    International Nuclear Information System (INIS)

    Xu, J; Zhai, Y Y; Cao, Y Q; Chen, K J

    2017-01-01

    Si quantum dots are currently extensively studied since they can be used to develop many kinds of optoelectronic devices. In this report, we review the fabrication of Si quantum dots (Si QD) /Si nanowires (Si NWs) hetero-structures by deposition of Si QDs/SiO 2 or Si QDs/SiC multilayers on Si NWs arrays. The electroluminescence and photovoltaic devices based on the formed hetero-structures have been prepared and the improved performance is confirmed. It is also found that the surface recombination via the surface defects states on the Si NWs, especially the ones obtained by the long-time etching, may deteriorate the device properties though they exhibit the better anti-reflection characteristics. The possible surface passivation approaches are briefly discussed. (paper)

  7. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  8. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  9. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  10. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  11. SiGe BiCMOS manufacturing platform for mmWave applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

    2010-10-01

    TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

  12. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  13. Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit.

    Science.gov (United States)

    Kwon, Min-Woo; Baek, Myung-Hyun; Hwang, Sungmin; Kim, Sungjun; Park, Byung-Gook

    2018-09-01

    We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

  14. Selective Epitaxy of InP on Si and Rectification in Graphene/InP/Si Hybrid Structure.

    Science.gov (United States)

    Niu, Gang; Capellini, Giovanni; Hatami, Fariba; Di Bartolomeo, Antonio; Niermann, Tore; Hussein, Emad Hameed; Schubert, Markus Andreas; Krause, Hans-Michael; Zaumseil, Peter; Skibitzki, Oliver; Lupina, Grzegorz; Masselink, William Ted; Lehmann, Michael; Xie, Ya-Hong; Schroeder, Thomas

    2016-10-12

    The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO 2 matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

  15. Effect of the gate scaling on the analogue performance of s-Si CMOS devices

    International Nuclear Information System (INIS)

    Fobelets, K; Calvo-Gallego, J; Velázquez-Pérez, J E

    2011-01-01

    In this contribution, we present a detailed study of the analogue performance of deep submicron strained n-channel Si/SiGe (s-Si) MOSFETs. The study was carried out using a 2D device simulator based on the hydrodynamic model and the impedance field method to self-consistently obtain the current noise at the device's terminals. The analysis focused on the possible benefits of the gate scaling on the ac and noise performance of the transistor for low-power applications while keeping constant the oxide thickness equal to 2 nm to guarantee negligible level of the gate tunnel current. For a drain to source bias of 50 mV, it was found that a pure scaling of the transistor's gate length under 32 nm is detrimental for subthreshold operation in terms of the subthreshold slope (S) and transconductance (g m ) but would lead to reasonably low values of the minimum noise figure (NF min ). For the sake of comparison, SOI MOSFETs with the same layout and operating under the same conditions were simulated. The SOI MOSFETs showed better immunity against the gate scaling in terms of S than the s-Si MOSFETs, but lower values of g m and a higher value of NF min at the same level of the drain current. Finally, the devices have been studied in the saturation region for a drain to source bias of 1 V. In this region, it was found that the dependence of the current level SOI or s-Si MOSFET may outperform its counterparts

  16. Above-CMOS a-Si and CIGS Solar Cells for Powering Autonomous Microsystems

    NARCIS (Netherlands)

    Lu, J.; Liu, W.; van der Werf, C.H.M.; Kovalgin, A.Y.; Sun, Y.; Schropp, R.E.I.; Schmitz, J.

    2010-01-01

    Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copperindium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal

  17. Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

    Directory of Open Access Journals (Sweden)

    Kwang-Jow Gan

    2016-06-01

    Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

  18. FEM Analysis of Sezawa Mode SAW Sensor for VOC Based on CMOS Compatible AlN/SiO2/Si Multilayer Structure

    Directory of Open Access Journals (Sweden)

    Muhammad Zubair Aslam

    2018-05-01

    Full Text Available A Finite Element Method (FEM simulation study is conducted, aiming to scrutinize the sensitivity of Sezawa wave mode in a multilayer AlN/SiO2/Si Surface Acoustic Wave (SAW sensor to low concentrations of Volatile Organic Compounds (VOCs, that is, trichloromethane, trichloroethylene, carbon tetrachloride and tetrachloroethene. A Complimentary Metal-Oxide Semiconductor (CMOS compatible AlN/SiO2/Si based multilayer SAW resonator structure is taken into account for this purpose. In this study, first, the influence of AlN and SiO2 layers’ thicknesses over phase velocities and electromechanical coupling coefficients (k2 of two SAW modes (i.e., Rayleigh and Sezawa is analyzed and the optimal thicknesses of AlN and SiO2 layers are opted for best propagation characteristics. Next, the study is further extended to analyze the mass loading effect on resonance frequencies of SAW modes by coating a thin Polyisobutylene (PIB polymer film over the AlN surface. Finally, the sensitivity of the two SAW modes is examined for VOCs. This study concluded that the sensitivity of Sezawa wave mode for 1 ppm of selected volatile organic gases is twice that of the Rayleigh wave mode.

  19. Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications

    OpenAIRE

    Pan, Chenyun; Naeemi, Azad

    2017-01-01

    The latest results of benchmarking research are presented for a variety of beyond-CMOS charge- and spin-based devices. In addition to improving the device-level models, several new device proposals and a few majorly modified devices are investigated. Deep pipelining circuits are employed to boost the throughput of low-power devices. Furthermore, the benchmarking methodology is extended to interconnect-centric analyses and non-Boolean logic applications. In contrast to Boolean circuits, non-Bo...

  20. Ge quantum dot arrays grown by ultrahigh vacuum molecular-beam epitaxy on the Si(001) surface: nucleation, morphology, and CMOS compatibility.

    Science.gov (United States)

    Yuryev, Vladimir A; Arapkina, Larisa V

    2011-09-05

    Issues of morphology, nucleation, and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (≲600°C) and high (≳600°C) temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts--pyramids and wedges-- are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001) surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001) quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.

  1. Ge quantum dot arrays grown by ultrahigh vacuum molecular-beam epitaxy on the Si(001 surface: nucleation, morphology, and CMOS compatibility

    Directory of Open Access Journals (Sweden)

    Yuryev Vladimir

    2011-01-01

    Full Text Available Abstract Issues of morphology, nucleation, and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001 surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (≲600°C and high (≳600°C temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts--pyramids and wedges-- are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001 surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001 quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.

  2. Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

    Science.gov (United States)

    León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

    2018-05-01

    We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

  3. Electric-field-controlled interface dipole modulation for Si-based memory devices.

    Science.gov (United States)

    Miyata, Noriyuki

    2018-05-31

    Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

  4. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  5. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  6. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  7. Using of the Modern Semiconductor Devices Based on the SiC

    Directory of Open Access Journals (Sweden)

    Pavel Drabek

    2008-01-01

    Full Text Available This paper deals with possibility of application of the semiconductor devices based on the SiC (Silicon Carbide inthe power electronics. Basic synopsis of SiC based materials problems are presented, appreciation of their properties incomparison with current using power semiconductor devices ((IGBT, MOSFET, CoolFET transistors.

  8. Total dose hardness of a commercial SiGe BiCMOS technology

    International Nuclear Information System (INIS)

    Van Vonno, N.; Lucas, R.; Thornberry, D.

    1999-01-01

    Over the past decade SiGe HBT technology has progress from the laboratory to actual commercial applications. When integrated into a BiMOS process, this technology has applications in low-cost space systems. In this paper, we report results of total dose testing of a SiGe/CMOS process accessible through a commercial foundry. (authors)

  9. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

  10. High efficiency grating couplers based on shared process with CMOS MOSFETs

    International Nuclear Information System (INIS)

    Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  11. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Science.gov (United States)

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  12. Tin (Sn) - An Unlikely Ally to Extend Moore's Law for Silicon CMOS?

    KAUST Repository

    Hussain, Aftab M.

    2012-12-01

    There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

  13. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  14. Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

    Science.gov (United States)

    Guichard, Alex Richard

    Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores

  15. First result on biased CMOS MAPs-on-diamond devices

    Energy Technology Data Exchange (ETDEWEB)

    Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  16. 270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

    Science.gov (United States)

    Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

    2011-11-01

    TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

  17. Si-Based Germanium Tin Semiconductor Lasers for Optoelectronic Applications

    Science.gov (United States)

    Al-Kabi, Sattar H. Sweilim

    Silicon-based materials and optoelectronic devices are of great interest as they could be monolithically integrated in the current Si complementary metal-oxide-semiconductor (CMOS) processes. The integration of optoelectronic components on the CMOS platform has long been limited due to the unavailability of Si-based laser sources. A Si-based monolithic laser is highly desirable for full integration of Si photonics chip. In this work, Si-based germanium-tin (GeSn) lasers have been demonstrated as direct bandgap group-IV laser sources. This opens a completely new avenue from the traditional III-V integration approach. In this work, the material and optical properties of GeSn alloys were comprehensively studied. The GeSn films were grown on Ge-buffered Si substrates in a reduced pressure chemical vapor deposition system with low-cost SnCl4 and GeH4 precursors. A systematic study was done for thin GeSn films (thickness 400 nm) with Sn composition 5 to 17.5%. The room temperature photoluminescence (PL) spectra were measured that showed a gradual shift of emission peaks towards longer wavelength as Sn composition increases. Strong PL intensity and low defect density indicated high material quality. Moreover, the PL study of n-doped samples showed bandgap narrowing compared to the unintentionally p-doped (boron) thin films with similar Sn compositions. Finally, optically pumped GeSn lasers on Si with broad wavelength coverage from 2 to 3 mum were demonstrated using high-quality GeSn films with Sn compositions up to 17.5%. The achieved maximum Sn composition of 17.5% broke the acknowledged Sn incorporation limit using similar deposition chemistry. The highest lasing temperature was measured at 180 K with an active layer thickness as thin as 270 nm. The unprecedented lasing performance is due to the achievement of high material quality and a robust fabrication process. The results reported in this work show a major advancement towards Si-based electrically pumped mid

  18. Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

    International Nuclear Information System (INIS)

    Walther, S.; Lenoble, D.; Lallement, F.; Grouillet, A.; Erokhin, Y.; Singh, V.; Testoni, A.

    2005-01-01

    For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5x higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p + /n ultra-shallow junctions formed with BF 3 plasma doping have superior X j /R s characteristics to beamline implants and yield up to 30% lower R s for 20 nm X j while using standard spike anneal with ramp-up rate of 75 deg. C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior V t roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving V t roll-off and I on -I off performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity

  19. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  20. CMOS image sensor-based immunodetection by refractive-index change.

    Science.gov (United States)

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

  1. Gas-source molecular beam epitaxy of Si(111) on Si(110) substrates by insertion of 3C-SiC(111) interlayer for hybrid orientation technology

    Energy Technology Data Exchange (ETDEWEB)

    Bantaculo, Rolando, E-mail: rolandobantaculo@yahoo.com; Saitoh, Eiji; Miyamoto, Yu; Handa, Hiroyuki; Suemitsu, Maki

    2011-11-01

    A method to realize a novel hybrid orientations of Si surfaces, Si(111) on Si(110), has been developed by use of a Si(111)/3C-SiC(111)/Si(110) trilayer structure. This technology allows us to use the Si(111) portion for the n-type and the Si(110) portion for the p-type channels, providing a solution to the current drive imbalance between the two channels confronted in Si(100)-based complementary metal oxide semiconductor (CMOS) technology. The central idea is to use a rotated heteroepitaxy of 3C-SiC(111) on Si(110) substrate, which occurs when a 3C-SiC film is grown under certain growth conditions. Monomethylsilane (SiH{sub 3}-CH{sub 3}) gas-source molecular beam epitaxy (GSMBE) is used for this 3C-SiC interlayer formation while disilane (Si{sub 2}H{sub 6}) is used for the top Si(111) layer formation. Though the film quality of the Si epilayer leaves a lot of room for betterment, the present results may suffice to prove its potential as a new technology to be used in the next generation CMOS devices.

  2. Large Format CMOS-based Detectors for Diffraction Studies

    Science.gov (United States)

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  3. Large Format CMOS-based Detectors for Diffraction Studies

    International Nuclear Information System (INIS)

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  4. Inverse spin-valve effect in nanoscale Si-based spin-valve devices

    Science.gov (United States)

    Hiep, Duong Dinh; Tanaka, Masaaki; Hai, Pham Nam

    2017-12-01

    We investigated the spin-valve effect in nano-scale silicon (Si)-based spin-valve devices using a Fe/MgO/Ge spin injector/detector deposited on Si by molecular beam epitaxy. For a device with a 20 nm Si channel, we observed clear magnetoresistance up to 3% at low temperature when a magnetic field was applied in the film plane along the Si channel transport direction. A large spin-dependent output voltage of 20 mV was observed at a bias voltage of 0.9 V at 15 K, which is among the highest values in lateral spin-valve devices reported so far. Furthermore, we observed that the sign of the spin-valve effect is reversed at low temperatures, suggesting the possibility of a spin-blockade effect of defect states in the MgO/Ge tunneling barrier.

  5. High-speed Si/GeSi hetero-structure Electro Absorption Modulator.

    Science.gov (United States)

    Mastronardi, L; Banakar, M; Khokhar, A Z; Hattasan, N; Rutirawut, T; Bucio, T Domínguez; Grabska, K M; Littlejohns, C; Bazin, A; Mashanovich, G; Gardes, F Y

    2018-03-19

    The ever-increasing demand for integrated, low power interconnect systems is pushing the bandwidth density of CMOS photonic devices. Taking advantage of the strong Franz-Keldysh effect in the C and L communication bands, electro-absorption modulators in Ge and GeSi are setting a new standard in terms of device footprint and power consumption for next generation photonics interconnect arrays. In this paper, we present a compact, low power electro-absorption modulator (EAM) Si/GeSi hetero-structure based on an 800 nm SOI overlayer with a modulation bandwidth of 56 GHz. The device design and fabrication tolerant process are presented, followed by the measurement analysis. Eye diagram measurements show a dynamic ER of 5.2 dB at a data rate of 56 Gb/s at 1566 nm, and calculated modulator power is 44 fJ/bit.

  6. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  7. Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

    KAUST Repository

    Chen, Min Cheng; Lin, Chia Yi; Li, Kai Hsin; Li, Lain-Jong; Chen, Chang Hsiao; Chuang, Cheng Hao; Lee, Ming Dao; Chen, Yi Ju; Hou, Yun Fang; Lin, Chang Hsien; Chen, Chun Chi; Wu, Bo Wei; Wu, Cheng San; Yang, Ivy; Lee, Yao Jen; Yeh, Wen Kuan; Wang, Tahui; Yang, Fu Liang; Hu, Chenming

    2014-01-01

    Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

  8. Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

    KAUST Repository

    Chen, Min Cheng

    2014-12-01

    Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

  9. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  10. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    Science.gov (United States)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  11. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.

    2016-05-18

    We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

  12. Physical characteristics modification of a SiGe-HBT semiconductor device for performance improvement in a terahertz detecting system

    Science.gov (United States)

    Ghodsi, Hamed; Kaatuzian, Hassan

    2015-05-01

    In order to improve the performance of a pre-designed direct conversion terahertz detector which is implemented in a 0.25 μm-SiGe-BiCMOS process, we propose some slight modifications in the bipolar section of the SiGe device physical design. Comparison of our new proposed device and the previously reported device is done by SILVACO TCAD software simulation and we have used previous experimentally reported data to confirm our software simulations. Our proposed modifications in device structural design show a present device responsivity improvement of about 10% from 1 to 1.1 A/W while the bandwidth improvement is about 218 GHz. The minimum noise equivalent power at detector output is increased by about 14.3% and finally power consumption per pixel at the maximum responsivity is decreased by about 5%.

  13. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  14. Integrated X-band FMCW front-end in SiGe BiCMOS

    NARCIS (Netherlands)

    Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

    2010-01-01

    An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

  15. Sensitivity Enhancement of a Vertical-Type CMOS Hall Device for a Magnetic Sensor

    Directory of Open Access Journals (Sweden)

    Sein Oh

    2018-01-01

    Full Text Available This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of 16 μm and a height of 2 μm is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

  16. 3D integration of planar crossbar memristive devices with CMOS substrate

    International Nuclear Information System (INIS)

    Lin, Peng; Pi, Shuang; Xia, Qiangfei

    2014-01-01

    Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. (paper)

  17. Physical characteristics modification of a SiGe-HBT semiconductor device for performance improvement in a terahertz detecting system

    International Nuclear Information System (INIS)

    Ghodsi, Hamed; Kaatuzian, Hassan

    2015-01-01

    In order to improve the performance of a pre-designed direct conversion terahertz detector which is implemented in a 0.25 μm-SiGe-BiCMOS process, we propose some slight modifications in the bipolar section of the SiGe device physical design. Comparison of our new proposed device and the previously reported device is done by SILVACO TCAD software simulation and we have used previous experimentally reported data to confirm our software simulations. Our proposed modifications in device structural design show a present device responsivity improvement of about 10% from 1 to 1.1 A/W while the bandwidth improvement is about 218 GHz. The minimum noise equivalent power at detector output is increased by about 14.3% and finally power consumption per pixel at the maximum responsivity is decreased by about 5%. (paper)

  18. Dielectric strength of SiO2 in a CMOS transistor structure

    International Nuclear Information System (INIS)

    Soden, J.M.

    1979-01-01

    The distribution of experimental dielectric strengths of SiO 2 gate dielectric in a CMOS transistor structure is shown to be composed of a primary, statistically-normal distribution of high dielectric strength and a secondary distribution spread through the lower dielectric strength region. The dielectric strength was not significantly affected by high level (1 x 10 6 RADS (Si)) gamma radiation or high temperature (200 0 C) stress. The primary distribution breakdowns occurred at topographical edges, mainly at the gate/field oxide interface, and the secondary distribution breakdowns occurred at random locations in the central region of the gate

  19. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    International Nuclear Information System (INIS)

    Sawadsaringkarn, Y; Kimura, H; Maezawa, Y; Nakajima, A; Kobayashi, T; Sasagawa, K; Noda, T; Tokuda, T; Ohta, J

    2012-01-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  20. Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

    Science.gov (United States)

    Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

    2014-12-01

    We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

  1. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  2. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

    International Nuclear Information System (INIS)

    Bonacini, S.

    2007-11-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

  3. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  4. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  5. Effect of hydrogen ion beam treatment on Si nanocrystal/SiO_2 superlattice-based memory devices

    International Nuclear Information System (INIS)

    Fu, Sheng-Wen; Chen, Hui-Ju; Wu, Hsuan-Ta; Chuang, Bing-Ru; Shih, Chuan-Feng

    2016-01-01

    Graphical abstract: - Highlights: • Memory window and retention properties are improved employing HIBAS technique. • The O/Si ratio and radiative recombination are changed by HIBAS. • Memory properties are affected not only by Si NCs and O/Si ratio but also the RDCs. • The mechanism of hydrogen ion beam alters the memory properties is investigated. - Abstract: This study presents a novel route for synthesizing silicon-rich oxide (SRO)/SiO_2 superlattice-based memory devices with an improved memory window and retention properties. The SiO_2 and SRO superlattices are deposited by reactive sputtering. Specifically, the hydrogen ion beam is used to irradiate the SRO layer immediately after its deposition in the vacuum chamber. The use of the hydrogen ion beam was determined to increase oxygen content and the density of the Si nanocrystals. The memory window increased from 16 to 25.6 V, and the leakage current decreased significantly by two orders, to under ±20 V, for the hydrogen ion beam-prepared devices. This study investigates the mechanism into how hydrogen ion beam treatment alters SRO films and influences memory properties.

  6. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    International Nuclear Information System (INIS)

    Hu Rongbin; Wang Yuxin; Lu Wu

    2014-01-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  7. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    Science.gov (United States)

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

  8. A Baseband Ultra-Low Noise SiGe:C BiCMOS 0.25 µm Amplifier And Its Application For An On-Chip Phase-Noise Measurement Circuit

    OpenAIRE

    Godet , Sylvain; Tournier , Éric; Llopis , Olivier; Cathelin , Andreia; Juyon , Julien

    2009-01-01

    4 pages; International audience; The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on-chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This ...

  9. A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

    Science.gov (United States)

    Fulkerson, David E.

    2010-02-01

    This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

  10. An improved standard total dose test for CMOS space electronics

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Winokur, P.S.; Riewe, L.C.; Pease, R.L.

    1989-01-01

    The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at ≅ 200 rad(SiO 2 )/s followed by a 1-week 100 degrees C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space surviability of CMOS circuits: a Co-60 irradiation and test to screen against oxide-trapped charge related failures, and an additional rebound test to screen against interface-trap related failures. Testing implications for bipolar technologies are also discussed

  11. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Science.gov (United States)

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  12. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  13. Silicon Based Mid Infrared SiGeSn Heterostructure Emitters and Detectors

    Science.gov (United States)

    2016-05-16

    AFRL-AFOSR-JP-TR-2016-0054 Silicon based mid infrared SiGeSn heterostrcture emitters and detectors Greg Sun UNIVERSITY OF MASSACHUSETTS Final Report... Silicon Based Mid Infrared SiGeSn Heterostructure Emitters and Detectors ” February 10, 2016 Principal Investigator: Greg Sun Engineering...diodes are incompatible with the CMOS process and therefore cannot be easily integrated with Si electronics . The GeSn mid IR detectors developed in

  14. Switching Performance Evaluation of Commercial SiC Power Devices (SiC JFET and SiC MOSFET) in Relation to the Gate Driver Complexity

    DEFF Research Database (Denmark)

    Pittini, Riccardo; Zhang, Zhe; Andersen, Michael A. E.

    2013-01-01

    and JFETs. The recent introduction of SiC MOSFET has proved that it is possible to have highly performing SiC devices with a minimum gate driver complexity; this made SiC power devices even more attractive despite their device cost. This paper presents an analysis based on experimental results...... of the switching losses of various commercially available Si and SiC power devices rated at 1200 V (Si IGBTs, SiC JFETs and SiC MOSFETs). The comparison evaluates the reduction of the switching losses which is achievable with the introduction of SiC power devices; this includes analysis and considerations...

  15. Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

    Science.gov (United States)

    Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

    2010-01-01

    Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

  16. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    International Nuclear Information System (INIS)

    Kim, Y; Pham, C; Chang, J P

    2015-01-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  17. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Science.gov (United States)

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  18. Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates.

    Science.gov (United States)

    Huang, Kai; Jia, Qi; You, Tiangui; Zhang, Runchun; Lin, Jiajie; Zhang, Shibin; Zhou, Min; Zhang, Bo; Yu, Wenjie; Ou, Xin; Wang, Xi

    2017-11-08

    Die-to-wafer heterogeneous integration of single-crystalline GaN film with CMOS compatible Si(100) substrate using the ion-cutting technique has been demonstrated. The thermodynamics of GaN surface blistering is in-situ investigated via a thermal-stage optical microscopy, which indicates that the large activation energy (2.5 eV) and low H ions utilization ratio (~6%) might result in the extremely high H fluence required for the ion-slicing of GaN. The crystalline quality, surface topography and the microstructure of the GaN films are characterized in detail. The full width at half maximum (FWHM) for GaN (002) X-ray rocking curves is as low as 163 arcsec, corresponding to a density of threading dislocation of 5 × 10 7  cm -2 . Different evolution of the implantation-induced damage was observed and a relationship between the damage evolution and implantation-induced damage is demonstrated. This work would be beneficial to understand the mechanism of ion-slicing of GaN and to provide a platform for the hybrid integration of GaN devices with standard Si CMOS process.

  19. Development of Smartphone based Optical Device

    Science.gov (United States)

    Jung, Youngkee

    Due to the economy of scale, smartphones are becoming more affordable while their computing powers are increasing dramatically every year. Here we propose a ubiquitous and portable instrument for analyte quantitation by utilizing the characteristics of typical smartphone imaging system and specific design of transducers for different applications. Three testbeds included in this work are: quantitative colorimetric analysis, ultra-low radiant flux detection, and portable spectrometer. As a proof-of-principle for each device, 3-D printed cradle and theoretical simulation with MATLAB have been implemented. First example utilizes the native CMOS camera with their respective RGB channel data and perform an analyte quantitation for typical lateral flow devices (LFD). Histogram analysis method has been employed to detect the analyte concentration and calibration results show good correlation between perceived color change and analyte concentration. The second example shows the possibility of using a conventional CMOS camera for pico Watt level photon flux detection. Since most of consumer grade CMOS cameras cannot detect this level of light intensity and their dark current are relatively higher, a new algorithm called NREA (Noise Reduction by Ensemble Averaging) algorithm was developed to effectively reduce the noise level and increase the SNR (signal to noise ratio). This technique is effective for bioanalytical assays that has lower flux intensity such as fluorescence and luminescence. As a proof-of-principle, we tested the device with Pseudomonas fluorescens M3A and achieved a limit of detection of high 10? CFU/ml. In addition to basic schematic of detection model, another experiment with a silicon photomultiplier (SiPM) has been studied for more sensitive light detectability. Based on both the laser experiment and tw bioluminescent experiments, named Pseudomonas fluorescens M3A and NanoLuc, we found that the miniSM based device has a superior ability than the

  20. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  1. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  2. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  3. Characterisation of a CMOS charge transfer device for TDI imaging

    International Nuclear Information System (INIS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-01-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques

  4. Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

    Science.gov (United States)

    Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

    2016-09-01

    Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

  5. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  6. Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

    Science.gov (United States)

    Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

    2018-04-01

    We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

  7. Loss Model and Efficiency Analysis of Tram Auxiliary Converter Based on a SiC Device

    Directory of Open Access Journals (Sweden)

    Hao Liu

    2017-12-01

    Full Text Available Currently, the auxiliary converter in the auxiliary power supply system of a modern tram adopts Si IGBT as its switching device and with the 1700 V/225 A SiC MOSFET module commercially available from Cree, an auxiliary converter using all SiC devices is now possible. A SiC auxiliary converter prototype is developed during this study. The author(s derive the loss calculation formula of the SiC auxiliary converter according to the system topology and principle and each part loss in this system can be calculated based on the device datasheet. Then, the static and dynamic characteristics of the SiC MOSFET module used in the system are tested, which aids in fully understanding the performance of the SiC devices and provides data support for the establishment of the PLECS loss simulation model. Additionally, according to the actual circuit parameters, the PLECS loss simulation model is set up. This simulation model can simulate the actual operating conditions of the auxiliary converter system and calculate the loss of each switching device. Finally, the loss of the SiC auxiliary converter prototype is measured and through comparison it is found that the loss calculation theory and PLECS loss simulation model is valuable. Furthermore, the thermal images of the system can prove the conclusion about loss distribution to some extent. Moreover, these two methods have the advantages of less variables and fast calculation for high power applications. The loss models may aid in optimizing the switching frequency and improving the efficiency of the system.

  8. Radiation-hardened CMOS/SOS LSI circuits

    International Nuclear Information System (INIS)

    Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.

    1976-01-01

    The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology

  9. Betavoltaic device in por-SiC/Si C-Nuclear Energy Converter

    Directory of Open Access Journals (Sweden)

    Akimchenko Alina

    2017-01-01

    Full Text Available The miniature and low-power devices with long service life in hard operating conditions like the Carbon-14 beta-decay energy converters indeed as eternal resource for integrated MEMS and NEMS are considered. Authors discuss how to create the power supply for MEMS/NEMS devices, based on porous SiC/Si structure, which are tested to be used as the beta-decay energy converters of radioactive C-14 into electrical energy. This is based on the silicon carbide obtaining by self-organizing mono 3C-SiC endotaxy on the Si substrate. The new idea is the C-14 atoms including in molecules in the silicon carbide porous structure by this technology, which will increase the efficiency of the converter due to the greater intensity of electron-hole pairs generation rate in the space charge region. The synthesis of C-14 can be also performed by using the electronically controlled magneto-optic chamber.

  10. Highly uniform and reliable resistive switching characteristics of a Ni/WOx/p+-Si memory device

    Science.gov (United States)

    Kim, Tae-Hyeon; Kim, Sungjun; Kim, Hyungjin; Kim, Min-Hwi; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

    2018-02-01

    In this paper, we investigate the resistive switching behavior of a bipolar resistive random-access memory (RRAM) in a Ni/WOx/p+-Si RRAM with CMOS compatibility. Highly unifrom and reliable bipolar resistive switching characteristics are observed by a DC voltage sweeping and its switching mechanism can be explained by SCLC model. As a result, the possibility of metal-insulator-silicon (MIS) structural WOx-based RRAM's application to Si-based 1D (diode)-1R (RRAM) or 1T (transistor)-1R (RRAM) structure is demonstrated.

  11. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    International Nuclear Information System (INIS)

    Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

    2011-01-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

  13. Germanium CMOS potential from material and process perspectives: Be more positive about germanium

    Science.gov (United States)

    Toriumi, Akira; Nishimura, Tomonori

    2018-01-01

    CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices

  14. Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

    International Nuclear Information System (INIS)

    Holland, S.

    1991-11-01

    A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

  15. Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

    Directory of Open Access Journals (Sweden)

    Sylvain Barraud

    2016-03-01

    Full Text Available The definition of the ampere will change in the next few years. This electrical base unit of the S.I. will be redefined by fixing the value of the charge quantum, i.e., the electron charge e. As a result electron pumps will become the natural device for the mise en pratique of this new ampere. In the last years semiconductor electron pumps have emerged as the most advanced systems, both in terms of speed and precision. Another figure of merit for a metrological device would be its ability to be predictible and shared. For that reason a mature fabrication process would certainly be an advantage. In this article we present electron pumps made within a CMOS (Complementary Metal Oxide Semiconductor research facility on 300 mm silicon-on-insulator wafers, using advanced microelectronics tools and processes. We give an overview of the whole integration scheme and emphasize the fabrication steps which differ from the normal CMOS route.

  16. CMOS/SOS 4k Rams hardened to 100 Krads (s:)

    International Nuclear Information System (INIS)

    Napoli, L.S.; Heagerty, W.F.; Smeltzer, R.K.; Yeh, J.L.

    1982-01-01

    Two CMOS/SOS 4K memories were fabricated with a recently developed, hardened SOS process. Memory functionality after radiation doses well in excess of 100 Krads(Si) was demonstrated. The critical device processing steps were identified. The radiationinduced failure mode of the memories is understood in terms of the circuit organization and the radiation behavior of the individual transistors in the memories

  17. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  18. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  19. Surface-micromachined Bragg Reflectors Based on Multiple Airgap/SiO2 Layers for CMOS-compatible Fabry-perot Filters in the UV-visible Spectral Range

    NARCIS (Netherlands)

    Ghaderi, M.; Ayerden, N.P.; De Graaf, G.; Wolffenbuttel, R.F.

    2014-01-01

    In CMOS-compatible optical filter designs, SiO2 is often used as the low-index material, limiting the optical contrast (nHi/nLo) to about 2. Using the air as low-index material improves the optical contrast by about 50%, thus increasing the reflectivity and bandwidth at a given design complexity.

  20. Monolithically Integrated Ge-on-Si Active Photonics

    Directory of Open Access Journals (Sweden)

    Jifeng Liu

    2014-07-01

    Full Text Available Monolithically integrated, active photonic devices on Si are key components in Si-based large-scale electronic-photonic integration for future generations of high-performance, low-power computation and communication systems. Ge has become an interesting candidate for active photonic devices in Si photonics due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS processing. In this paper, we present a review of the recent progress in Ge-on-Si active photonics materials and devices for photon detection, modulation, and generation. We first discuss the band engineering of Ge using tensile strain, n-type doping, Sn alloying, and separate confinement of Γ vs. L electrons in quantum well (QW structures to transform the material towards a direct band gap semiconductor for enhancing optoelectronic properties. We then give a brief overview of epitaxial Ge-on-Si materials growth, followed by a summary of recent investigations towards low-temperature, direct growth of high crystallinity Ge and GeSn alloys on dielectric layers for 3D photonic integration. Finally, we review the most recent studies on waveguide-integrated Ge-on-Si photodetectors (PDs, electroabsorption modulators (EAMs, and laser diodes (LDs, and suggest possible future research directions for large-scale monolithic electronic-photonic integrated circuits on a Si platform.

  1. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  2. Micro- and nanoelectronics emerging device challenges and solutions

    CERN Document Server

    Brozek, Tomasz

    2014-01-01

    Micro- and Nanoelectronics: Emerging Device Challenges and Solutions presents a comprehensive overview of the current state of the art of micro- and nanoelectronics, covering the field from fundamental science and material properties to novel ways of making nanodevices. Containing contributions from experts in both industry and academia, this cutting-edge text:Discusses emerging silicon devices for CMOS technologies, fully depleted device architectures, characteristics, and scalingExplains the specifics of silicon compound devices (SiGe, SiC) and their unique propertiesExplores various options

  3. Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

    KAUST Repository

    Hussain, Aftab M.

    2014-12-14

    We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well as experimentally by fabricating MOSFETs. Our study suggests that the alloy offers interesting possibilities in the realm of silicon band gap tuning. We have explored diffusion of tin (Sn) into the industry\\'s most widely used substrate, silicon (100), as it is the most cost effective, scalable and CMOS compatible way of obtaining SiSn. Our theoretical model predicts a higher mobility for p-channel SiSn MOSFETs, due to a lower effective mass of the holes, which has been experimentally validated using the fabricated MOSFETs. We report an increase of 13.6% in the average field effect hole mobility for SiSn devices compared to silicon control devices.

  4. Design, fabrication and transportation of Si rotating device

    International Nuclear Information System (INIS)

    Kimura, Nobuaki; Imaizumi, Tomomi; Takemoto, Noriyuki; Tanimoto, Masataka; Saito, Takashi; Hori, Naohiko; Tsuchiya, Kunihiko; Romanova, Nataliya; Gizatulin, Shamil; Martyushov, Alexandr; Nakipov, Darkhan; Chakrov, Petr; Tanaka, Futoshi; Nakajima, Takeshi

    2012-06-01

    Si semiconductor production by Neutron Transmutation Doping (NTD) method using the Japan Materials Testing Reactor (JMTR) has been investigated in Neutron Irradiation and Testing Reactor Center, Japan Atomic Energy Agency (JAEA) in order to expand industry use. As a part of investigations, irradiation test of silicon ingot for development of NTD-Si with high quality was planned using WWR-K in Institute of Nuclear Physics (INP), National Nuclear Center of Republic of Kazakhstan (NNC-RK) based on one of specific topics of cooperation (STC), Irradiation Technology for NTD-Si (STC No.II-4), on the implementing arrangement between NNC-RK and the JAEA for 'Nuclear Technology on Testing/Research Reactors' in cooperation in research and development in nuclear energy and technology. As for the irradiation test, Si rotating device was fabricated in JAEA, and the fabricated device was transported with irradiation specimens from JAEA to INP-NNC-RK. This report described the design, the fabrication, the performance test of the Si rotating device and transportation procedures. (author)

  5. Surface acoustic wave devices on AlN/3C–SiC/Si multilayer structures

    International Nuclear Information System (INIS)

    Lin, Chih-Ming; Lien, Wei-Cheng; Riekkinen, Tommi; Senesky, Debbie G; Pisano, Albert P; Chen, Yung-Yu; Felmetsger, Valery V

    2013-01-01

    Surface acoustic wave (SAW) propagation characteristics in a multilayer structure including a piezoelectric aluminum nitride (AlN) thin film and an epitaxial cubic silicon carbide (3C–SiC) layer on a silicon (Si) substrate are investigated by theoretical calculation in this work. Alternating current (ac) reactive magnetron sputtering was used to deposit highly c-axis-oriented AlN thin films, showing the full width at half maximum (FWHM) of the rocking curve of 1.36° on epitaxial 3C–SiC layers on Si substrates. In addition, conventional two-port SAW devices were fabricated on the AlN/3C–SiC/Si multilayer structure and SAW propagation properties in the multilayer structure were experimentally investigated. The surface wave in the AlN/3C–SiC/Si multilayer structure exhibits a phase velocity of 5528 m s −1 and an electromechanical coupling coefficient of 0.42%. The results demonstrate the potential of AlN thin films grown on epitaxial 3C–SiC layers to create layered SAW devices with higher phase velocities and larger electromechanical coupling coefficients than SAW devices on an AlN/Si multilayer structure. Moreover, the FWHM values of rocking curves of the AlN thin film and 3C–SiC layer remained constant after annealing for 500 h at 540 °C in air atmosphere. Accordingly, the layered SAW devices based on AlN thin films and 3C–SiC layers are applicable to timing and sensing applications in harsh environments. (paper)

  6. Electron transport in all-Heusler Co2CrSi/Cu2CrAl/Co2CrSi device, based on ab-initio NEGF calculations

    Science.gov (United States)

    Mikaeilzadeh, L.; Pirgholi, M.; Tavana, A.

    2018-05-01

    Based on the ab-initio non-equilibrium Green's function (NEGF) formalism based on the density functional theory (DFT), we have studied the electron transport in the all-Heusler device Co2CrSi/Cu2CrAl/Co2CrSi. Results show that the calculated transmission spectra is very sensitive to the structural parameters and the interface. Also, we obtain a range for the thickness of the spacer layer for which the MR effect is optimum. Calculations also show a perfect GMR effect in this device.

  7. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  8. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  9. Nonvolatile field effect transistors based on protons and Si/SiO2Si structures

    International Nuclear Information System (INIS)

    Warren, W.L.; Vanheusden, K.; Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Knoll, M.G.; Devine, R.A.B.

    1997-01-01

    Recently, the authors have demonstrated that annealing Si/SiO 2 /Si structures in a hydrogen containing ambient introduces mobile H + ions into the buried SiO 2 layer. Changes in the H + spatial distribution within the SiO 2 layer were electrically monitored by current-voltage (I-V) measurements. The ability to directly probe reversible protonic motion in Si/SiO 2 /Si structures makes this an exemplar system to explore the physics and chemistry of hydrogen in the technologically relevant Si/SiO 2 structure. In this work, they illustrate that this effect can be used as the basis for a programmable nonvolatile field effect transistor (NVFET) memory that may compete with other Si-based memory devices. The power of this novel device is its simplicity; it is based upon standard Si/SiO 2 /Si technology and forming gas annealing, a common treatment used in integrated circuit processing. They also briefly discuss the effects of radiation on its retention properties

  10. An optically controlled SiC lateral power transistor based on SiC/SiCGe super junction structure

    International Nuclear Information System (INIS)

    Pu Hongbin; Cao Lin; Ren Jie; Chen Zhiming; Nan Yagong

    2010-01-01

    An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively. (semiconductor devices)

  11. An optically controlled SiC lateral power transistor based on SiC/SiCGe super junction structure

    Energy Technology Data Exchange (ETDEWEB)

    Pu Hongbin; Cao Lin; Ren Jie; Chen Zhiming; Nan Yagong, E-mail: puhongbin@xaut.edu.c [Xi' an University of Technology, Xi' an 710048 (China)

    2010-04-15

    An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 {mu}m and 0.7 {mu}m are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively. (semiconductor devices)

  12. Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

    Science.gov (United States)

    Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

    2008-08-01

    The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

  13. Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

    Science.gov (United States)

    Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2012-04-01

    In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

  14. Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

    OpenAIRE

    Tanaka, Masahiro; Omura, Ichiro

    2012-01-01

    Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables t...

  15. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  16. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  17. Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics

    Directory of Open Access Journals (Sweden)

    Sandro Rao

    2016-01-01

    Full Text Available Hydrogenated amorphous silicon (a-Si:H shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34–40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

  18. Silicon, germanium, and III-V-based tunneling devices for low-power applications

    Science.gov (United States)

    Smith, Joshua T.

    While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit---the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the

  19. Si Interface Barrier Modification on Memristor for Brain-Inspired Computing

    Science.gov (United States)

    Wu, Wei; Wu, Huaqiang; Gao, Bin; Qian, He

    2017-06-01

    Memristor is an emerging technology aimed at implementing neuromorphic computing in hardware system. Resistive random access memory (RRAM) is a kind of memristor with excellent performance, but abrupt switching in the set process influences the efficiency of neuromorphic system. In this study, we present an interface switching memristor device based on TiN/Si/TaOx/TiN stack and CMOS compatible fabrication process to achieve gradually resistive switching both in set and reset processes. The devices show a more than 10 switching window. The related switching mechanism is discussed.

  20. Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

    International Nuclear Information System (INIS)

    Jiang Yuxi; Li Jiao; Ran Feng; Cao Jialin; Yang Dianxiong

    2009-01-01

    Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented. (semiconductor devices)

  1. NIMROD Simulations of the HIT-SI and HIT-SI3 Devices

    Science.gov (United States)

    Morgan, Kyle; Jarboe, Tom; Hossack, Aaron; Chandra, Rian; Everson, Chris

    2017-10-01

    The Helicity Injected Torus with Steady Inductive helicity injection (HIT-SI) experiment uses a set of inductively driven helicity injectors to apply non-axisymmetric current drive on the edge of the plasma, driving an axisymmetric spheromak equilibrium in a central confinement volume. Significant improvements have been made to extended MHD modeling of HIT-SI, with both the resolution of disagreement at high injector frequencies in HIT-SI in addition to successes with the new upgraded HIT-SI3 device. Previous numerical studies of HIT-SI, using a zero-beta eMHD model, focused on operations with a drive frequency of 14.5 kHz, and found reduced agreement with both the magnetic profile and current amplification at higher frequencies (30-70 kHz). HIT-SI3 has three helicity injectors which are able to operate with different mode structures of perturbations through the different relative temporal phasing of the injectors. Simulations that allow for pressure gradients have been performed in the parameter regimes of both devices using the NIMROD code and show improved agreement with experimental results, most notably capturing the observed Shafranov-shift due to increased beta observed at higher finj in HIT-SI and the variety of toroidal perturbation spectra available in HIT-SI3. This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of Fusion Energy Sciences under Award Number DE-FG02- 96ER54361.

  2. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  3. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  4. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  5. Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

    CERN Document Server

    Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

    2010-01-01

    We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

  6. A comprehensive model on field-effect pnpn devices (Z2-FET)

    Science.gov (United States)

    Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

    2017-08-01

    A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

  7. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  8. A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications

    Directory of Open Access Journals (Sweden)

    Taeho Oh

    2017-12-01

    Full Text Available Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS and two p-channel MOSFETs (PMOS devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process.

  9. Low-temperature mobility measurements on CMOS devices

    International Nuclear Information System (INIS)

    Hairpetian, A.; Gitlin, D.; Viswanathan, C.R.

    1989-01-01

    The surface channel mobility of carriers in eta- and rho-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 Κ. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP), which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appears to have different temperature dependence for eta- and rho-channel devices. The electron mobility increases with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibits a different temperature behavior depending upon whether the gate voltage corresponds to strong inversion or is near threshold

  10. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  11. An innovation for prevention of radiation induced latchup

    International Nuclear Information System (INIS)

    Xu Xianguo; Hu Jiandong; Xu Xi

    2006-01-01

    An innovation for prevention latchup, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After the design of pseudo-latchup path method is studied in detail, a practice and the corresponding simulation and experiment validation result are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but not to eliminate the dose rate upset in bulk-Si CMOS devices. An innovation for prevention latchup, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After the design of pseudo-latchup path method is studied in detail, a practice and the corresponding simulation and experiment validation result are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but not to eliminate the dose rate upset in bulk-Si CMOS devices. (authors)

  12. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  13. Mechanism and modelling of source/drain asymmetry variation in 65 nm CMOS devices for SRAM and logic applications

    International Nuclear Information System (INIS)

    Lee, T H; Fang, Y K; Chiang, Y T; Lin, C T; Chen, M S; Cheng, O

    2008-01-01

    The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM

  14. Si/SiGe heterointerfaces in one-, two-, and three-dimensional nanostructures: their impact on SiGe light emission

    Science.gov (United States)

    Lockwood, David; Wu, Xiaohua; Baribeau, Jean-Marc; Mala, Selina; Wang, Xialou; Tsybeskov, Leonid

    2016-03-01

    Fast optical interconnects together with an associated light emitter that are both compatible with conventional Si-based complementary metal-oxide- semiconductor (CMOS) integrated circuit technology is an unavoidable requirement for the next-generation microprocessors and computers. Self-assembled Si/Si1-xGex nanostructures, which can emit light at wavelengths within the important optical communication wavelength range of 1.3 - 1.55 μm, are already compatible with standard CMOS practices. However, the expected long carrier radiative lifetimes observed to date in Si and Si/Si1-xGex nanostructures have prevented the attainment of efficient light-emitting devices including the desired lasers. Thus, the engineering of Si/Si1-xGex heterostructures having a controlled composition and sharp interfaces is crucial for producing the requisite fast and efficient photoluminescence (PL) at energies in the range 0.8-0.9 eV. In this paper we assess how the nature of the interfaces between SiGe nanostructures and Si in heterostructures strongly affects carrier mobility and recombination for physical confinement in three dimensions (corresponding to the case of quantum dots), two dimensions (corresponding to quantum wires), and one dimension (corresponding to quantum wells). The interface sharpness is influenced by many factors such as growth conditions, strain, and thermal processing, which in practice can make it difficult to attain the ideal structures required. This is certainly the case for nanostructure confinement in one dimension. However, we demonstrate that axial Si/Ge nanowire (NW) heterojunctions (HJs) with a Si/Ge NW diameter in the range 50 - 120 nm produce a clear PL signal associated with band-to-band electron-hole recombination at the NW HJ that is attributed to a specific interfacial SiGe alloy composition. For three-dimensional confinement, the experiments outlined here show that two quite different Si1-xGex nanostructures incorporated into a Si0.6Ge0.4 wavy

  15. Molecular beam epitaxy grown Ge/Si pin layer sequence for photonic devices

    International Nuclear Information System (INIS)

    Schulze, J.; Oehme, M.; Werner, J.

    2012-01-01

    A key challenge to obtain a convergence of classical Si-based microelectronics and optoelectronics is the manufacturing of photonic integrated circuits integrable into classical Si-based integrated circuits. This integration would be greatly enhanced if similar facilities and technologies could be used. Therefore one approach is the development of optoelectronic components and devices made from group-IV-based materials such as SiGe, Ge or Ge:Sn. In this paper the optoelectronic performances of a pin diode made from a Ge/Si heterostructure pin layer sequence grown by molecular beam epitaxy are discussed. After a detailed description of the layer sequence growth and the device manufacturing process it will be shown that – depending on the chosen operating point and device design – the diode serves as a broadband high speed photo detector, Franz–Keldysh effect modulator or light emitting diode.

  16. Molecular beam epitaxy grown Ge/Si pin layer sequence for photonic devices

    Energy Technology Data Exchange (ETDEWEB)

    Schulze, J., E-mail: schulze@iht.uni-stuttgart.de; Oehme, M.; Werner, J.

    2012-02-01

    A key challenge to obtain a convergence of classical Si-based microelectronics and optoelectronics is the manufacturing of photonic integrated circuits integrable into classical Si-based integrated circuits. This integration would be greatly enhanced if similar facilities and technologies could be used. Therefore one approach is the development of optoelectronic components and devices made from group-IV-based materials such as SiGe, Ge or Ge:Sn. In this paper the optoelectronic performances of a pin diode made from a Ge/Si heterostructure pin layer sequence grown by molecular beam epitaxy are discussed. After a detailed description of the layer sequence growth and the device manufacturing process it will be shown that - depending on the chosen operating point and device design - the diode serves as a broadband high speed photo detector, Franz-Keldysh effect modulator or light emitting diode.

  17. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  18. Flexible-CMOS and biocompatible piezoelectric AlN material for MEMS applications

    International Nuclear Information System (INIS)

    Jackson, Nathan; Keeney, Lynette; Mathewson, Alan

    2013-01-01

    The development of a CMOS compatible flexible piezoelectric material is desired for numerous applications and in particular for biomedical MEMS devices. Aluminum nitride (AlN) is the most commonly used CMOS compatible piezoelectric material, which is typically deposited on Si in order to enhance the c-axis (002) crystal orientation which gives AlN its high piezoelectric properties. This paper reports on the successful deposition of AlN on polyimide (PI-2611) material. The AlN deposited has a FWHM (002) value of 5.1° and a piezoelectric d 33 value of 1.12 pm V −1 , and SEM images show high quality columnar grains. The highly crystalline AlN material is due to the semi-crystalline properties of the polyimide film used. Cytotoxicity testing showed the AlN/polyimide material to be non-toxic to 3T3 cells and primary neurons. Surface properties of the AlN/polyimide film were evaluated as they have a significant effect on the adhesion of cells to the film. The results show neurons adhering to the AlN surface. The results of this paper show the characterization of a new flexible-CMOS and biocompatible AlN/polyimide material for MEMS devices with improved crystallinity and piezoelectric properties. (paper)

  19. Electrical characterisation of SiGe heterojunction bipolar transistors and Si pseudo-HBTS

    Science.gov (United States)

    De Barros, O.; Le Tron, B.; Woods, R. C.; Giroult-Matlakowski, G.; Vincent, G.; Brémond, G.

    1996-08-01

    This paper reports an electrical characterisation of the emitter-base junction of Si pseudo-HBTs and SiGe HBTs fabricated in a CMOS compatible single polysilicon self-aligned process. From the reverse characteristics it appears that the definition of the emitter-base junction by plasma etching induces peripheral defects that increase the base current of the transistors. Deep level transient spectroscopy measurements show a deep level in the case of SiGe base, whose spatial origin is not fully determinate up to now.

  20. The performance of the anthraquinone/p-Si and the pyridine/p-Si rectifying device under X-ray irradiation

    International Nuclear Information System (INIS)

    Şahin, Yılmaz; Aydoğan, Şakir; Ekinci, Duygu; Turut, Abdulmecit

    2016-01-01

    Some X-ray irradiation-induced electrical characteristics of the Au/anthraquinone/p-Si and the Au/pyridine/p-Si junction devices have been investigated. The experimental ideality factors increased for both devices with increasing irradiation dose from 25 Gy to 150 Gy. These values ranged from 1.10 to 1.52 for Au/anthraquinone/p-Si and from 1.46 to 1.77 for Au/pyridine/p-Si, respectively. Furthermore, the barrier height of Au/anthraquinone/p-Si increased with increasing irradiation dose from 0.75 to 0.91 eV, whereas it displayed about a constant value for Au/pyridine/p-Si. In addition, the series resistance of both devices increased with x-ray dose too. The increase in the series resistance with x-ray irradiation has been attributed to the decrease in the active dopant densities. It was seen that the ionization damage is effective on most of the junction characteristics. The leakage current of the Au/anthraquinone/p-Si device decreased with x-ray irradiation since the irradiation induced the formation of electron-hole pairs and hydroquinone structure, and thus some of them are trapped by the interface states. The degradation of the I-V curves of Au/pyridine/p-Si/Al device is attributed to the variation of the surface or interface states distribution for the devices. The reverse and forward bias currents relatively increased after x-ray irradiation because of the decrease in bulk lifetime. In addition, ATR-FTIR spectra of anthraquinone and pyridine films showed that pyridine is more stable than anthraquinone under x-ray irradiation. - Highlights: • Two junction devices based on organic materials were fabricated. • The effect of the x-ray irradiation on devices were examined. • Both devices showed x-irradiation-dependence.

  1. The performance of the anthraquinone/p-Si and the pyridine/p-Si rectifying device under X-ray irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Şahin, Yılmaz [Department of Physics, Faculty of Sciences, University of Atatürk, 25240 Erzurum (Turkey); Aydoğan, Şakir, E-mail: saydogan@atauni.edu.tr [Department of Physics, Faculty of Sciences, University of Atatürk, 25240 Erzurum (Turkey); Ekinci, Duygu [Department of Chemistry, Faculty of Sciences, University of Atatürk, 25240 Erzurum (Turkey); Turut, Abdulmecit [Department of Engineering Physics, Faculty of Sciences, Istanbul Medeniyet University (Turkey)

    2016-11-01

    Some X-ray irradiation-induced electrical characteristics of the Au/anthraquinone/p-Si and the Au/pyridine/p-Si junction devices have been investigated. The experimental ideality factors increased for both devices with increasing irradiation dose from 25 Gy to 150 Gy. These values ranged from 1.10 to 1.52 for Au/anthraquinone/p-Si and from 1.46 to 1.77 for Au/pyridine/p-Si, respectively. Furthermore, the barrier height of Au/anthraquinone/p-Si increased with increasing irradiation dose from 0.75 to 0.91 eV, whereas it displayed about a constant value for Au/pyridine/p-Si. In addition, the series resistance of both devices increased with x-ray dose too. The increase in the series resistance with x-ray irradiation has been attributed to the decrease in the active dopant densities. It was seen that the ionization damage is effective on most of the junction characteristics. The leakage current of the Au/anthraquinone/p-Si device decreased with x-ray irradiation since the irradiation induced the formation of electron-hole pairs and hydroquinone structure, and thus some of them are trapped by the interface states. The degradation of the I-V curves of Au/pyridine/p-Si/Al device is attributed to the variation of the surface or interface states distribution for the devices. The reverse and forward bias currents relatively increased after x-ray irradiation because of the decrease in bulk lifetime. In addition, ATR-FTIR spectra of anthraquinone and pyridine films showed that pyridine is more stable than anthraquinone under x-ray irradiation. - Highlights: • Two junction devices based on organic materials were fabricated. • The effect of the x-ray irradiation on devices were examined. • Both devices showed x-irradiation-dependence.

  2. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  3. Application of CMOS Technology to Silicon Photomultiplier Sensors

    Science.gov (United States)

    D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

    2017-01-01

    We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

  4. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  5. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  6. Development of Simulink-Based SiC MOSFET Modeling Platform for Series Connected Devices

    DEFF Research Database (Denmark)

    Tsolaridis, Georgios; Ilves, Kalle; Reigosa, Paula Diaz

    2016-01-01

    A new MATLAB/Simulink-based modeling platform has been developed for SiC MOSFET power modules. The modeling platform describes the electrical behavior f a single 1.2 kV/ 350 A SiC MOSFET power module, as well as the series connection of two of them. A fast parameter initialization is followed...... by an optimization process to facilitate the extraction of the model’s parameters in a more automated way relying on a small number of experimental waveforms. Through extensive experimental work, it is shown that the model accurately predicts both static and dynamic performances. The series connection of two Si......C power modules has been investigated through the validation of the static and dynamic conditions. Thanks to the developed model, a better understanding of the challenges introduced by uneven voltage balance sharing among series connected devices is possible....

  7. Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

    Science.gov (United States)

    Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

    2018-01-01

    Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

  8. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  9. Influence of oxygen doping on resistive-switching characteristic of a-Si/c-Si device

    Science.gov (United States)

    Zhang, Jiahua; Chen, Da; Huang, Shihua

    2017-12-01

    The influence of oxygen doping on resistive-switching characteristics of Ag/a-Si/p+-c-Si device was investigated. By oxygen doping in the growth process of amorphous silicon, the device resistive-switching performances, such as the ON/OFF resistance ratios, yield and stability were improved, which may be ascribed to the significant reduction of defect density because of oxygen incorporation. The device I-V characteristics are strongly dependent on the oxygen doping concentration. As the oxygen doping concentration increases, the Si-rich device gradually transforms to an oxygen-rich device, and the device yield, switching characteristics, and stability may be improved for silver/oxygen-doped a-Si/p+-c-Si device. Finally, the device resistive-switching mechanism was analyzed. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LY17F040001), the Open Project Program of Surface Physics Laboratory (National Key Laboratory) of Fudan University (No. KF2015_02), the Open Project Program of National Laboratory for Infrared Physics, Chinese Academy of Sciences (No. M201503), the Zhejiang Provincial Science and Technology Key Innovation Team (No. 2011R50012), and the Zhejiang Provincial Key Laboratory (No. 2013E10022).

  10. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  11. Monolithic Ge-on-Si lasers for large-scale electronic-photonic integration

    Science.gov (United States)

    Liu, Jifeng; Kimerling, Lionel C.; Michel, Jurgen

    2012-09-01

    A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic-photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500-1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

  12. Monolithic Ge-on-Si lasers for large-scale electronic–photonic integration

    International Nuclear Information System (INIS)

    Liu, Jifeng; Kimerling, Lionel C; Michel, Jurgen

    2012-01-01

    A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic–photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500–1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

  13. A planar Al-Si Schottky barrier metal–oxide–semiconductor field effect transistor operated at cryogenic temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Purches, W. E. [School of Physics, UNSW, Sydney 2052 (Australia); Rossi, A.; Zhao, R. [School of Electrical Engineering and Telecommunications, UNSW, Sydney 2052 (Australia); Kafanov, S.; Duty, T. L. [School of Physics, UNSW, Sydney 2052 (Australia); Centre for Engineered Quantum Systems (EQuS), School of Physics, UNSW, Sydney 2052 (Australia); Dzurak, A. S. [School of Electrical Engineering and Telecommunications, UNSW, Sydney 2052 (Australia); Australian Centre of Excellence for Quantum Computation and Communication Technology (CQC2T), UNSW, Sydney 2052 (Australia); Rogge, S.; Tettamanzi, G. C., E-mail: g.tettamanzi@unsw.edu.au [School of Physics, UNSW, Sydney 2052 (Australia); Australian Centre of Excellence for Quantum Computation and Communication Technology (CQC2T), UNSW, Sydney 2052 (Australia)

    2015-08-10

    Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

  14. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  15. Irradiation damage of SiC semiconductor device (I)

    International Nuclear Information System (INIS)

    Park, Ji Yeon; Kim, Weon Ju

    2000-09-01

    This report reviewed the irradiation damage of SiC semiconductor devices and examined a irradiation behavior of SiC single crystal as a pre-examination for evaluation of irradiation behavior of SiC semiconductor devices. The SiC single was crystal irradiated by gamma-beam, N+ ion and electron beam. Annealing examinations of the irradiated specimens also were performed at 500 deg C. N-type 6H-SiC dopped with N+ ion was used and irradiation doses of gamma-beam, N+ion and electron beam were up to 200 Mrad, 1x10 16 N + ions/cm 2 and 3.6 x 10 17 e/cm 2 and 1.08 x 10 18 e/cm 2 , respectively. Irradiation damages were analyzed by the EPR method. Additionally, properties of SiC, information about commercial SiC single crystals and the list of web sites with related to the SiC device were described in the appendix

  16. Irradiation damage of SiC semiconductor device (I)

    Energy Technology Data Exchange (ETDEWEB)

    Park, Ji Yeon; Kim, Weon Ju

    2000-09-01

    This report reviewed the irradiation damage of SiC semiconductor devices and examined a irradiation behavior of SiC single crystal as a pre-examination for evaluation of irradiation behavior of SiC semiconductor devices. The SiC single was crystal irradiated by gamma-beam, N+ ion and electron beam. Annealing examinations of the irradiated specimens also were performed at 500 deg C. N-type 6H-SiC dopped with N+ ion was used and irradiation doses of gamma-beam, N+ion and electron beam were up to 200 Mrad, 1x10{sup 16} N{sup +} ions/cm{sup 2} and 3.6 x 10{sup 17} e/cm{sup 2} and 1.08 x 10{sup 18} e/cm{sup 2} , respectively. Irradiation damages were analyzed by the EPR method. Additionally, properties of SiC, information about commercial SiC single crystals and the list of web sites with related to the SiC device were described in the appendix.

  17. Radiation hardening of CMOS-based circuitry in SMART transmitters

    International Nuclear Information System (INIS)

    Loescher, D.H.

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term ''SMART'' denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection

  18. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  19. Two-dimensional optical simulation on a visible ray passing through inter-metal dielectric layers of CMOS image sensor device

    International Nuclear Information System (INIS)

    Lee, Wan-Gyu; Kim, Jun-Seok; Kim, Hee-Jeen; Kim, Sang-Young; Hwang, Sung-Bo; Lee, Jeong-Gun

    2005-01-01

    Two-dimensional optical simulation has been performed for investigating light propagation through a micro lens and inter-metal dielectric (IMD) layers in an Al and Cu back-end of line (BEOL) onto a Si photodiode, and its effects on the wave power, as well as optical carriers generated by a visible ray in the silicon substrate area, i.e. photodiode of a CMOS image sensor pixel. The number of optically generated carriers in an Al-BEOL has been compared to a Cu-BEOL. It is shown that more optical carriers are generated in the Cu-BEOL for the red color because a higher permittivity dielectric material like SiC is used in the Cu-BEOL to prevent Cu from diffusing into the dielectric material, resulting in higher optical loss in the higher- permittivity dielectric layers. Thus, the optical power density arriving in the silicon substrate is higher in the Al-BEOL than in the Cu-BEOL when the wavelength is blue (470 nm) or green (550 nm) in the visible ray spectrum. In conclusion, the structure of a Cu-BEOL in a CMOS image sensor has to be optimized for generating more optical carriers through lower-permittivity IMD materials or by reducing the permittivity difference between SiC (or SiN) and IMD materials, without deteriorating the capability as a barrier to Cu diffusion.

  20. Device Innovation and Material Challenges at the Limits of CMOS Technology

    Science.gov (United States)

    Solomon, P. M.

    2000-08-01

    Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

  1. Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

    International Nuclear Information System (INIS)

    Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

    1984-01-01

    The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

  2. Internal transmission coefficient in charges carrier generation layer of graphene/Si based solar cell device

    International Nuclear Information System (INIS)

    Rosikhin, Ahmad; Winata, Toto

    2016-01-01

    Internal transmission profile in charges carrier generation layer of graphene/Si based solar cell has been explored theoretically. Photovoltaic device was constructed from graphene/Si heterojunction forming a multilayer stuck with Si as generation layer. The graphene/Si sheet was layered on ITO/glass wafer then coated by Al forming Ohmic contact with Si. Photon incident propagate from glass substrate to metal electrode and assumed that there is no transmission in Al layer. The wavelength range spectra used in this calculation was 200 – 1000 nm. It found that transmission intensity in the generation layer show non-linear behavior and partitioned by few areas which related with excitation process. According to this information, it may to optimize the photons absorption to create more excitation process by inserting appropriate material to enhance optical properties in certain wavelength spectra because of the exciton generation is strongly influenced by photon absorption.

  3. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  4. Toward CMOS image sensor based glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2012-09-07

    Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

  5. Characterization of Chemical Vapor Deposited Tetraethyl Orthosilicate based SiO2 Films for Photonic Devices

    Directory of Open Access Journals (Sweden)

    Jhansirani KOTCHARLAKOTA

    2016-05-01

    Full Text Available Silicon has been the choice for photonics technology because of its cost, compatibility with mass production and availability. Silicon based photonic devices are very significant from commercial point of view and are much compatible with established technology. This paper deals with deposition and characterization of SiO2 films prepared by indigenously developed chemical vapor deposition system. Ellipsometry study of prepared films showed an increase in refractive index and film thickness with the increment in deposition temperature. The deposition temperature has a significant role for stoichiometric SiO2 films, FTIR measurement has shown the three characteristics peaks of Si-O-Si through three samples prepared at temperatures 700, 750 and 800 °C while Si-O-Si stretching peak positions were observed to be shifted to lower wavenumber in accordance to the temperature. FESEM analysis has confirmed the smooth surface without any crack or disorder while EDX analysis showed the corresponding peaks of compositional SiO2 films.DOI: http://dx.doi.org/10.5755/j01.ms.22.1.7245

  6. A low-power CMOS readout IC design for bolometer applications

    Science.gov (United States)

    Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

    2017-02-01

    A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

  7. Fabrication of reproducible, integration-compatible hybrid molecular/si electronics.

    Science.gov (United States)

    Yu, Xi; Lovrinčić, Robert; Kraynis, Olga; Man, Gabriel; Ely, Tal; Zohar, Arava; Toledano, Tal; Cahen, David; Vilan, Ayelet

    2014-12-29

    Reproducible molecular junctions can be integrated within standard CMOS technology. Metal-molecule-semiconductor junctions are fabricated by direct Si-C binding of hexadecane or methyl-styrene onto oxide-free H-Si(111) surfaces, with the lateral size of the junctions defined by an etched SiO2 well and with evaporated Pb as the top contact. The current density, J, is highly reproducible with a standard deviation in log(J) of 0.2 over a junction diameter change from 3 to 100 μm. Reproducibility over such a large range indicates that transport is truly across the molecules and does not result from artifacts like edge effects or defects in the molecular monolayer. Device fabrication is tested for two n-Si doping levels. With highly doped Si, transport is dominated by tunneling and reveals sharp conductance onsets at room temperature. Using the temperature dependence of current across medium-doped n-Si, the molecular tunneling barrier can be separated from the Si-Schottky one, which is a 0.47 eV, in agreement with the molecular-modified surface dipole and quite different from the bare Si-H junction. This indicates that Pb evaporation does not cause significant chemical changes to the molecules. The ability to manufacture reliable devices constitutes important progress toward possible future hybrid Si-based molecular electronics. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  9. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  10. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  11. Technological parameter and experimental set-up influences on latch-up triggering level in bulk CMOS device

    International Nuclear Information System (INIS)

    Dubuc, J.P.; Azais, B.; Murcia, M. de

    1994-01-01

    This paper deals with experimental and simulation results on latch-up triggered by an electrical or X-rays pulse in CMOS/bulk devices. Test condition influences as well as the great importance of process parameters on latch-up immunity are emphasized. (author). 10 refs., 19 figs., 1 tab

  12. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  13. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Science.gov (United States)

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  14. Fabrication and study of sol-gel ZnO films for use in Si-based heterojunction photovoltaic devices

    Directory of Open Access Journals (Sweden)

    Daniya Mukhamedshina

    2017-12-01

    Full Text Available This paper considers the use of zinc oxide thin films prepared via the sol-gel route as an n-type layer in heterojunction ZnO/Si solar cells. The ZnO films were prepared via a simple spin-coating technique using zinc acetate dihydrate as a zinc precursor, isopropanol as a solvent and monoethanolamine as a stabilizing agent. Optical, structural and morphological properties of ZnO were investigated for thin films grown from sol-gel solutions with different concentrations both on glass and silicon substrates. As such, a distribution of crystallite sizes and surface topology parameters corresponding to various zinc acetate dihydrate concentrations were obtained to elucidate optimal film deposition conditions. Correlation between thin film morphology and structural characteristics of ZnO thin films was made based on atomic-force microscopy studies. Finally, our results on fabrication, characterization and simulation of ZnO/Si heterojunctions for use as photovoltaic devices are presented. Although noticeable rectifying and photovoltaic properties were observed for Al/Si/ZnO/Ti/Au devices, there appears to exist a considerable room for device improvement with simulation studies suggesting that efficiencies of the order of 24% may be obtained for devices with optimal silicon wafer passivation, i.e. with lifetimes of the order of 1000 μs.

  15. Non-Micropipe Dislocations in 4H-SiC Devices: Electrical Properties and Device Technology Implications

    Science.gov (United States)

    Neudeck, Philip G.; Huang, Wei; Dudley, Michael; Fazi, Christian

    1998-01-01

    It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vectors greater than or equal to 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = 1c with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has recently been demonstrated that elementary screw dislocations somewhat degrade the reverse leakage and breakdown properties of 4H-SiC p(+)n diodes. Diodes containing elementary screw dislocations exhibited a 5% to 35% reduction in breakdown voltage, higher pre-breakdown reverse leakage current, softer reverse breakdown I-V knee, and microplasmic breakdown current filaments that were non-catastrophic as measured under high series resistance biasing. This paper details continuing experimental and theoretical investigations into the electrical properties of 4H-SiC elementary screw dislocations. The nonuniform breakdown behavior of 4H-SiC p'n junctions containing elementary screw dislocations exhibits interesting physical parallels with nonuniform breakdown phenomena previously observed in other semiconductor materials. Based upon experimentally observed dislocation-assisted breakdown, a re-assessment of well-known physical models relating power device reliability to junction breakdown has been undertaken for 4H-SiC. The potential impact of these elementary screw dislocation defects on the performance and reliability of various 4H-SiC device technologies being developed for high-power applications will be discussed.

  16. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  17. Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

    Science.gov (United States)

    Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

    2017-07-01

    As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

  18. Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

    International Nuclear Information System (INIS)

    Moreau, Y.; Gasiot, J.; Duzellier, S.

    1995-01-01

    Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined

  19. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    International Nuclear Information System (INIS)

    Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

    2015-01-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

  20. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  1. Flicker noise comparison of direct conversion mixers using Schottky and HBT dioderings in SiGe:C BiCMOS technology

    DEFF Research Database (Denmark)

    Michaelsen, Rasmus Schandorph; Johansen, Tom Keinicke; Tamborg, Kjeld

    2015-01-01

    In this paper, we present flicker noise measurements of two X-band direct conversion mixers implemented in a SiGe:C BiCMOS technology. Both mixers use a ring structure with either Schottky diodes or diode-connected HBTs for double balanced operation. The mixers are packaged in a metal casing on a...... circuit demonstrates a 1/f noise corner frequency around 10 kHz....

  2. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  3. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  4. Process controls for radiation hardened aluminum gate bulk silicon CMOS

    International Nuclear Information System (INIS)

    Gregory, B.L.

    1975-01-01

    Optimized dry oxides have recently yielded notable improvements in CMOS radiation-hardness. By following the proper procedures and recipes, it is now possible to produce devices which will function satisfactorily after exposure to a total ionizing dose in excess of 10 6 RADS (Si). This paper is concerned with the controls required on processing parameters once the optimized process is defined. In this process, the pre-irradiation electrical parameters must be closely controlled to insure that devices will function after irradiation. In particular, the specifications on n- and p-channel threshold voltages require tight control of fixed oxide charge, surface-state density, oxide thickness, and substrate and p-well surface concentrations. In order to achieve the above level of radiation hardness, certain processing procedures and parameters must also be closely controlled. Higher levels of cleanliness are required in the hardened process than are commonly required for commercial CMOS since, for hardened dry oxides, no impurity gettering can be employed during or after oxidation. Without such gettering, an unclean oxide is unacceptable due to bias-temperature instability. Correct pre-oxidation cleaning, residual surface damage removal, proper oxidation and annealing temperatures and times, and the correct metal sintering cycle are all important in determining device hardness. In a reproducible, hardened process, each of these processing steps must be closely controlled. (U.S.)

  5. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  6. Fabrication of Si/ZnS radial nanowire heterojunction arrays for white light emitting devices on Si substrates.

    Science.gov (United States)

    Katiyar, Ajit K; Sinha, Arun Kumar; Manna, Santanu; Ray, Samit K

    2014-09-10

    Well-separated Si/ZnS radial nanowire heterojunction-based light-emitting devices have been fabricated on large-area substrates by depositing n-ZnS film on p-type nanoporous Si nanowire templates. Vertically oriented porous Si nanowires on p-Si substrates have been grown by metal-assisted chemical etching catalyzed using Au nanoparticles. Isolated Si nanowires with needle-shaped arrays have been made by KOH treatment before ZnS deposition. Electrically driven efficient white light emission from radial heterojunction arrays has been achieved under a low forward bias condition. The observed white light emission is attributed to blue and green emission from the defect-related radiative transition of ZnS and Si/ZnS interface, respectively, while the red arises from the porous surface of the Si nanowire core. The observed white light emission from the Si/ZnS nanowire heterojunction could open up the new possibility to integrate Si-based optical sources on a large scale.

  7. Thermoelectric infrared microsensors based on a periodically suspended thermopile integrating nanostructured Ge/SiGe quantum dots superlattice

    Energy Technology Data Exchange (ETDEWEB)

    Ziouche, K., E-mail: katir.ziouche@iemn.univ-lille1.fr, E-mail: Zahia.bougrioua@iemn.univ-lille1.fr; Bougrioua, Z., E-mail: katir.ziouche@iemn.univ-lille1.fr, E-mail: Zahia.bougrioua@iemn.univ-lille1.fr; Lejeune, P.; Lasri, T.; Leclercq, D. [IEMN, Institute of Electronics, Microelectronics and Nanotechnology, CNRS and Lille 1 University, F-59652 Villeneuve d' Ascq (France); Savelli, G.; Hauser, D.; Michon, P.-M. [CEA, LITEN, Thermoelectricity Laboratory, F-38054 Grenoble (France)

    2014-07-28

    This paper presents an original integration of polycrystalline SiGe-based quantum dots superlattices (QDSL) into Thermoelectric (TE) planar infrared microsensors (μSIR) fabricated using a CMOS technology. The nanostructuration in QDSL results into a considerably reduced thermal conductivity by a factor up to 10 compared to the one of standard polysilicon layers that are usually used for IR sensor applications. A presentation of several TE layers, QDSL and polysilicon, is given before to describe the fabrication of the thermopile-based sensors. The theoretical values of the sensitivity to irradiance of μSIR can be predicted thanks to an analytical model. These findings are used to interpret the experimental measurements versus the nature of the TE layer exploited in the devices. The use of nanostructured QDSL as the main material in μSIR thermopile has brought a sensitivity improvement of about 28% consistent with theoretical predictions. The impact of QDSL low thermal conductivity is damped by the contribution of the thermal conductivity of all the other sub-layers that build up the device.

  8. Growth dynamics of SiGe nanowires by the Vapour Liquid Solid method and its impact on SiGe/Si axial heterojunction abruptness.

    Science.gov (United States)

    Pura, Jose Luis; Periwal, Priyanka; Baron, Thierry; Jimenez, Juan

    2018-06-05

    The Vapour Liquid Solid (VLS) method is by far the most extended procedure for bottom-up nanowire growth. This method also allows for the manufacture of nanowire axial heterojunctions in a straightforward way. To do this, during the growth process the precursor gases are switched on/off to obtain the desired change in the nanowire composition. Using this technique axially heterostructured nanowires can be grown, which are crucial for the fabrication of electronic and optoelectronic devices. SiGe/Si nanowires are compatible with Complementary Metal Oxide Semiconductor (CMOS) technology, this improves their versatility and the possibility of integration with the current electronic technologies. Abrupt heterointerfaces are fundamental for the development and correct operation of electronic and optoelectronic devices. Unfortunately, VLS growth of SiGe/Si heterojunctions does not provide abrupt transitions because of the high solubility of group IV semiconductors in Au, with the corresponding reservoir effect that precludes the growth of sharp interfaces. In this work, we studied the growth dynamics of SiGe/Si heterojunctions based on already developed models for VLS growth. A composition map of the Si-Ge-Au liquid alloy is proposed to better understand the impact of the growing conditions on the nanowire growth process and the heterojunction formation. The solution of our model provides heterojunction profiles in good agreement with experimental measurements. Finally, the in-depth study of the composition map provides a practical approach to reduce drastically the heterojunction abruptness by reducing the Si and Ge concentrations in the catalyst droplet. This converges with previous approaches that use catalysts aiming to reduce the solubility of the atomic species. This analysis opens new paths to reduce the heterojunction abruptness using Au catalysts, but the model can be naturally extended to other catalysts and semiconductors. © 2018 IOP Publishing Ltd.

  9. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    Directory of Open Access Journals (Sweden)

    Mohammad Reza Shokrani

    2014-01-01

    Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  10. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  11. Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO2 thin films

    International Nuclear Information System (INIS)

    Yurchuk, Ekaterina

    2015-01-01

    Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO 2 ) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO 2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO 2 -based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

  12. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

  13. Signal processing circuitry for CMOS-based SAW gas sensors with low power and area

    International Nuclear Information System (INIS)

    Mohd-Yasin, F.; Tye, K.F.; Reaz, M.B.I.

    2009-06-01

    The design and development of interface circuitries for CMOS-based SAW gas sensor is presented in this paper. The SAW gas sensor devices typically run at RF, requiring most designs to have complex signal conditioning circuitry. The proposed approach attempts to design a simple architecture with reduced power consumption. The SAW gas sensors operate at 354MHz. Simulation data show that the interface circuitries are ten times smaller with lower power supply, comparing to existing work. (author)

  14. JPL CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  15. SiC Discrete Power Devices

    National Research Council Canada - National Science Library

    Baliga, B

    2000-01-01

    .... The investigation of the poor performance of the 4H-SiC ACCUFETs provided insights for changes in device design and process flow, for improving their breakdown voltage and specific on-resistance...

  16. Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO{sub 2} thin films

    Energy Technology Data Exchange (ETDEWEB)

    Yurchuk, Ekaterina

    2015-02-06

    Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO{sub 2}) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO{sub 2} thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO{sub 2}-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

  17. Future challenges in single event effects for advanced CMOS technologies

    International Nuclear Information System (INIS)

    Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

    2010-01-01

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  18. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  19. CMOS cassette for digital upgrade of film-based mammography systems

    Science.gov (United States)

    Baysal, Mehmet A.; Toker, Emre

    2006-03-01

    While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

  20. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  1. Silicon based light-emitting materials and devices

    International Nuclear Information System (INIS)

    Chen Weide

    1999-01-01

    Silicon based light-emitting materials and devices are the key to optoelectronic integration. Recently, there has been significant progress in materials engineering methods. The author reviews the latest developments in this area including erbium doped silicon, porous silicon, nanocrystalline silicon and Si/SiO 2 superlattice structures. The incorporation of these different materials into devices is described and future device prospects are assessed

  2. Mobility-limiting mechanisms in single and dual channel strained Si/SiGe MOSFETs

    International Nuclear Information System (INIS)

    Olsen, S.H.; Dobrosz, P.; Escobedo-Cousin, E.; Bull, S.J.; O'Neill, A.G.

    2005-01-01

    Dual channel strained Si/SiGe CMOS architectures currently receive great attention due to maximum performance benefits being predicted for both n- and p-channel MOSFETs. Epitaxial growth of a compressively strained SiGe layer followed by tensile strained Si can create a high mobility buried hole channel and a high mobility surface electron channel on a single relaxed SiGe virtual substrate. However, dual channel n-MOSFETs fabricated using a high thermal budget exhibit compromised mobility enhancements compared with single channel devices, in which both electron and hole channels form in strained Si. This paper investigates the mobility-limiting mechanisms of dual channel structures. The first evidence of increased interface roughness due to the introduction of compressively strained SiGe below the tensile strained Si channel is presented. Interface corrugations degrade electron mobility in the strained Si. Roughness measurements have been carried out using AFM and TEM. Filtering AFM images allowed roughness at wavelengths pertinent to carrier transport to be studied and the results are in agreement with electrical data. Furthermore, the first comparison of strain measurements in the surface channels of single and dual channel architectures is presented. Raman spectroscopy has been used to study channel strain both before and after processing and indicates that there is no impact of the buried SiGe layer on surface macrostrain. The results provide further evidence that the improved performance of the single channel devices fabricated using a high thermal budget arises from improved surface roughness and reduced Ge diffusion into the Si channel

  3. Superconducting single electron transistor for charge sensing in Si/SiGe-based quantum dots

    Science.gov (United States)

    Yang, Zhen

    Si-based quantum devices, including Si/SiGe quantum dots (QD), are promising candidates for spin-based quantum bits (quits), which are a potential platform for quantum information processing. Meanwhile, qubit readout remains a challenging task related to semiconductor-based quantum computation. This thesis describes two readout devices for Si/SiGe QDs and the techniques for developing them from a traditional single electron transistor (SET). By embedding an SET in a tank circuit and operating it in the radio-frequency (RF) regime, a superconducting RF-SET has quick response as well as ultra high charge sensitivity and can be an excellent charge sensor for the QDs. We demonstrate such RF-SETs for QDs in a Si/SiGe heterostructure. Characterization of the SET in magnetic fields is studied for future exploration of advanced techniques such as spin detection and spin state manipulation. By replacing the tank circuit with a high-quality-factor microwave cavity, the embedded SET will be operated in the supercurrent regime as a single Cooper pair transistor (CPT) to further increase the charge sensitivity and reduce any dissipation. The operating principle and implementation of the cavity-embedded CPT (cCPT) will be introduced.

  4. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  5. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    Science.gov (United States)

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-07

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

  6. E-Beam Effects on CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

    2011-01-01

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  7. Digital characteristics of CMOS devices at cryogenic temperatures

    International Nuclear Information System (INIS)

    Deen, M.J.

    1989-01-01

    This paper presents the results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and a supply voltage between 3 and 20 V. Using a fixed supply of 5 V, the low noise margin (NM L decreased from 2.54 to 2.11 V, but the high noise margin NM H ) increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V 1L and V 1H increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity, V H - V L , and V 1H - V 1L all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained as due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β N /β rho ratio as the temperature is lowered

  8. Very low drift and high sensitivity of nanocrystal-TiO2 sensing membrane on pH-ISFET fabricated by CMOS compatible process

    International Nuclear Information System (INIS)

    Bunjongpru, W.; Sungthong, A.; Porntheeraphat, S.; Rayanasukha, Y.; Pankiew, A.; Jeamsaksiri, W.; Srisuwan, A.; Chaisriratanakul, W.; Chaowicharat, E.; Klunngien, N.; Hruanun, C.; Poyai, A.; Nukeaw, J.

    2013-01-01

    High sensitivity and very low drift rate pH sensors are successfully prepared by using nanocrystal-TiO 2 as sensing membrane of ion sensitive field effect transistor (ISFET) device fabricated via CMOS process. This paper describes the physical properties and sensing characteristics of the TiO 2 membrane prepared by annealing Ti and TiN thin films that deposited on SiO 2 /p-Si substrates through reactive DC magnetron sputtering system. The X-ray diffraction, scanning electron microscopy and Auger electron spectroscopy were used to investigate the structural and morphological features of deposited films after they had been subjected to annealing at various temperatures. The experimental results are interpreted in terms of the effects of amorphous-to-crystalline phase transition and subsequent oxidation of the annealed films. The electrolyte–insulator–semiconductor (EIS) device incorporating Ti-O-N membrane that had been obtained by annealing of TiN thin film at 850 °C exhibited a higher sensitivity (57 mV/pH), a higher linearity (1), a lower hysteresis voltage (1 mV in the pH cycle of 7 → 4 → 7 → 10 → 7), and a smaller drift rate (0.246 mV/h) than did those devices prepared at the other annealing temperatures. Furthermore, this pH-sensing device fabrication process is fully compatible with CMOS fabrication process technology.

  9. CMOS latch-up analysis and prevention

    International Nuclear Information System (INIS)

    Shafer, B.D.

    1975-06-01

    An analytical model is presented which develops relationships between ionization rates, minority carrier lifetimes, and latch-up in bulk CMOS integrated circuits. The basic mechanism for latch-up is the SCR action reported by Gregory and Shafer. The SCR is composed of a vertical NPN transistor formed by the N-channel source diffusion, the P-Well, and the N-substrate. The second part of the SCR is the lateral PNP transistor made up of the P-channel source diffusion, the N-substrate, and P-Well. It is shown that the NPN transistor turns on due to photocurrent-induced lateral voltage drops in the base of the transistor. The gain of this double diffused transistor has been shown to be as high as 100. Therefore, the transistor action of this device produces a much larger current flow in the substrate. This transistor current adds to that produced by the P-Well diode photocurrent in the substrate. It is found that the combined flow of current in the substrate forward biases the base emitter junction of the PNP device long before this could occur due to the P-Well photocurrent alone. The analysis indicated that a CD4007A CMOS device biased in the normal mode of operation should latch at about 2 . 10 8 rads/sec. Experimental results produced latch-up at 1 to 3 . 10 8 rads/sec. (U.S.)

  10. Si-based optical I/O for optical memory interface

    Science.gov (United States)

    Ha, Kyoungho; Shin, Dongjae; Byun, Hyunil; Cho, Kwansik; Na, Kyoungwon; Ji, Hochul; Pyo, Junghyung; Hong, Seokyong; Lee, Kwanghyun; Lee, Beomseok; Shin, Yong-hwack; Kim, Junghye; Kim, Seong-gu; Joe, Insung; Suh, Sungdong; Choi, Sanghoon; Han, Sangdeok; Park, Yoondong; Choi, Hanmei; Kuh, Bongjin; Kim, Kichul; Choi, Jinwoo; Park, Sujin; Kim, Hyeunsu; Kim, Kiho; Choi, Jinyong; Lee, Hyunjoo; Yang, Sujin; Park, Sungho; Lee, Minwoo; Cho, Minchang; Kim, Saebyeol; Jeong, Taejin; Hyun, Seokhun; Cho, Cheongryong; Kim, Jeong-kyoum; Yoon, Hong-gu; Nam, Jeongsik; Kwon, Hyukjoon; Lee, Hocheol; Choi, Junghwan; Jang, Sungjin; Choi, Joosun; Chung, Chilhee

    2012-01-01

    Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

  11. Materials and devices for quantum information processing in Si/SiGe

    Energy Technology Data Exchange (ETDEWEB)

    Sailer, Juergen

    2010-12-15

    In this thesis, we cover and discuss the complete way from material science, the fabrication of two-dimensional electron systems (2DES) in Si/SiGe heterostructures in molecular beam epitaxy (MBE), to quantum effects in few-electron devices based on these samples. We applied and compared two different approaches for the creation of pseudo-substrates that are as smooth, relaxed and defect free as possible. In the 'graded buffer' concept, starting from pure Si, the Ge content of the SiGe alloy is slowly and linearly increased until the desired Ge content is reached. In contrast, in the so-called 'low-temperature Si' concept, the SiGe alloy is deposited directly with the final Ge content, but onto a layer of highly defective Si. In terms of crystal defects, the 'graded buffer' turned out to be superior in comparison to the 'low-temperature Si' concept at the expense of a significantly higher material consumption. By continued optimization of the growth process, aiming at reducing the influence of the impurity, it nevertheless became possible to improve the charge carrier mobility from a mere 2000 cm{sup 2}/(Vs) to a record mobility exceeding 100 000 cm{sup 2}/(Vs). Within this work, we extended our MBE system with an electron beam evaporator for nuclear spin free {sup 28}Si. Together with the already existing effusion cell for {sup 70}Ge we were able to realize first 2DES in a nuclear spin free environment after successfully putting it to operation. The highest mobility 2DES in a nuclear spin free environment which have been realized in this thesis exhibited electron mobilities of up to 55 000 cm{sup 2}/(Vs). Quantum effects in Si/SiGe have been investigated in two- and zero-dimensional nanostructures. A remarkable phenomenon in the regime of the integer quantum Hall effect in Si/SiGe 2DES has been discovered and researched. For applications in quantum information processing and for the creation of qubits it is mandatory to

  12. Increasing cell-device adherence using cultured insect cells for receptor-based biosensors

    Science.gov (United States)

    Terutsuki, Daigo; Mitsuno, Hidefumi; Sakurai, Takeshi; Okamoto, Yuki; Tixier-Mita, Agnès; Toshiyoshi, Hiroshi; Mita, Yoshio; Kanzaki, Ryohei

    2018-03-01

    Field-effect transistor (FET)-based biosensors have a wide range of applications, and a bio-FET odorant sensor, based on insect (Sf21) cells expressing insect odorant receptors (ORs) with sensitivity and selectivity, has emerged. To fully realize the practical application of bio-FET odorant sensors, knowledge of the cell-device interface for efficient signal transfer, and a reliable and low-cost measurement system using the commercial complementary metal-oxide semiconductor (CMOS) foundry process, will be indispensable. However, the interfaces between Sf21 cells and sensor devices are largely unknown, and electrode materials used in the commercial CMOS foundry process are generally limited to aluminium, which is reportedly toxic to cells. In this study, we investigated Sf21 cell-device interfaces by developing cross-sectional specimens. Calcium imaging of Sf21 cells expressing insect ORs was used to verify the functions of Sf21 cells as odorant sensor elements on the electrode materials. We found that the cell-device interface was approximately 10 nm wide on average, suggesting that the adhesion mechanism of Sf21 cells may differ from that of other cells. These results will help to construct accurate signal detection from expressed insect ORs using FETs.

  13. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  14. Performance evaluation of a high power DC-DC boost converter for PV applications using SiC power devices

    Science.gov (United States)

    Almasoudi, Fahad M.; Alatawi, Khaled S.; Matin, Mohammad

    2016-09-01

    The development of Wide band gap (WBG) power devices has been attracted by many commercial companies to be available in the market because of their enormous advantages over the traditional Si power devices. An example of WBG material is SiC, which offers a number of advantages over Si material. For example, SiC has the ability of blocking higher voltages, reducing switching and conduction losses and supports high switching frequency. Consequently, SiC power devices have become the affordable choice for high frequency and power application. The goal of this paper is to study the performance of 4.5 kW, 200 kHz, 600V DC-DC boost converter operating in continuous conduction mode (CCM) for PV applications. The switching behavior and turn on and turn off losses of different switching power devices such as SiC MOSFET, SiC normally ON JFET and Si MOSFET are investigated and analyzed. Moreover, a detailed comparison is provided to show the overall efficiency of the DC-DC boost converter with different switching power devices. It is found that the efficiency of SiC power switching devices are higher than the efficiency of Si-based switching devices due to low switching and conduction losses when operating at high frequencies. According to the result, the performance of SiC switching power devices dominate the conventional Si power devices in terms of low losses, high efficiency and high power density. Accordingly, SiC power switching devices are more appropriate for PV applications where a converter of smaller size with high efficiency, and cost effective is required.

  15. Optical and electrical properties of Si-nanocrystals ion beam synthesized in SiO{sub 2}

    Energy Technology Data Exchange (ETDEWEB)

    Garrido, B. E-mail: blas@el.ub.es; Lopez, M.; Perez-Rodriguez, A.; Garcia, C.; Pellegrino, P.; Ferre, R.; Moreno, J.A.; Morante, J.R.; Bonafos, C.; Carrada, M.; Claverie, A.; Torre, J. de la; Souifi, A

    2004-02-01

    We review in this paper our recent results on the correlation between the structural and the optoelectronic properties of Si nano crystals (Si-nc) embedded in SiO{sub 2}. We describe as well the development of both materials and technology approaches that have allowed us to successfully produce efficient and reliable LEDs by using only CMOS processes. Si-nc were synthesised in SiO{sub 2} by ion implantation plus annealing and display average diameters from 2.5 to 6 nm, as measured by electron microscopy. By varying the annealing time in a large scale we have been able to track the nucleation, pure growth and Ostwald ripening stages of the nanocrystal population. The most efficient structures have Si-ncs with average size of 3 nm and densities of about 10{sup 19} cm{sup -3}. We have estimated band-gap energies, lifetimes (20-200 {mu}s) and absorption cross-sections (10{sup -15}-10{sup -16} cm{sup 2}) as a function of size and surface passivation. Based on these results, we propose a mechanism for exciton recombination based on the strong coupling of excitons with the heterointerfaces. From highly luminescent Si-nc, LEDs consisting of MOS capacitors were fabricated. Stable red electroluminescence has been obtained at room temperature and the I-V characteristics prove that the current is related to a pure tunnelling process. Fowler-Nordheim injection is not observed during light emission for electric fields below 5 MV/cm. Thus, hot carrier injection is avoided and efficient and reliable devices are obtained.

  16. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  17. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    International Nuclear Information System (INIS)

    Barnaby, Hugh J.; Mclain, Michael; Esqueda, Ivan Sanchez

    2007-01-01

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits

  18. Long term ionization response of several BiCMOS VLSIC technologies

    International Nuclear Information System (INIS)

    Pease, R.L.; Combs, W.; Clark, S.

    1992-01-01

    BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

  19. An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

    Science.gov (United States)

    Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

    2012-12-17

    An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

  20. Si micro photonics for optical interconnection

    International Nuclear Information System (INIS)

    Wada, K.; Ahn, D.H.; Lim, D.R.; Michel, J.; Kimerling, L.C.

    2006-01-01

    This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated

  1. Spectroscopic Studies of Semiconductor Materials for Aggressive-scaled Micro- and Opto-electronic Devices: nc-SiO2, GeO2; ng-Si, Ge and ng-Transition metal (TM) oxides

    Science.gov (United States)

    Cheng, Cheng

    transitions. Intra-d states are observed in all high-K dielectrics regardless of morphology, e.g. ng-TiO2, nc- Ti silicate , c-LaTiO3, nc-HfSiON334. This dissertation also discussed spectroscopic studies of: (i) nc-SiO 2, nc-GeO2 and (ii) nc-(SiO2)x(GeO2) 1-x pseudo-binary alloys. These studies, and the interpretation of these spectra and those in Chapter 3 in the This dissertation also discussed spectroscopic studies of: (i) nc-SiO2, nc-GeO2 and (ii) nc-(SiO 2)x(GeO2)1-x pseudo-binary alloys. These studies, and the interpretation of these spectra and those in Chapter 3 in the context of ab-initio theory provide a science base for the implementation of nc-oxides onto Germaniumsubstrates for aggressively scaled CMOS FETs, imaging devices as well as photovoltaics. X-Ray photoelectron spectroscopy(XPS) and Auger electron spectroscopy(AES) were used to determine SiO2 and GeO2 concentration in (SiO2)x(GeO2)1-x alloys. A linear trend in chemical shifts with compositions is observed and explained with charge-potential model, which incorporates the results of calculated partial charge from an empirical model for ionicity. The compositional linear relationships between binding energies nc-SiO 2, nc-GeO2, and (SiO2)x(GeO2)1-x alloy concentration agrees with the calculated results in charge potential model. SE and XAS spectral results show relatively strong O-vacancy in nc-GeO 2. O-vacancy defects in c-SiO2 are weaker. This is due to differences between Ge-O and Si-O bond (657.5kJ/mol and 799.6kJ/mol respectively). SE data shows a strong defect feature in GeO2, while SiO2 has no significant and distinct defect signature. Percolation theory describes the interconnection of bonds, e.g. Si-O and Ge-O in an otherwise nc-material, a (SiO2)x(GeO2)1-x pseudo-binary alloy. Changes in the band-gap energy of binary Si-Ge alloys occur at 0%Si (or 100% Ge), and the band gap energy increases from ˜ 0.6 eV to ˜0.87 eV as the Si concentration increases. A inflection point is at the percolation

  2. Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

    Science.gov (United States)

    Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

    2016-06-09

    We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

  3. Processing of poly-Si electrodes for charge-coupled devices

    Energy Technology Data Exchange (ETDEWEB)

    Sherohman, J.W.; Cook, F.D.

    1978-12-06

    A technique has been developed to fabricate poly-Si electrodes for charge-coupled devices. By controlling the microstructure of a poly-Si film, an anisotropic etchant was selected to provide essentially uniform electrode width dimensions. The electrode widths have only a 6% variation for the majority of the devices over the area of a 2 inch silicon wafer.

  4. Light-activated resistance switching in SiOx RRAM devices

    Science.gov (United States)

    Mehonic, A.; Gerard, T.; Kenyon, A. J.

    2017-12-01

    We report a study of light-activated resistance switching in silicon oxide (SiOx) resistive random access memory (RRAM) devices. Our devices had an indium tin oxide/SiOx/p-Si Metal/Oxide/Semiconductor structure, with resistance switching taking place in a 35 nm thick SiOx layer. The optical activity of the devices was investigated by characterising them in a range of voltage and light conditions. Devices respond to illumination at wavelengths in the range of 410-650 nm but are unresponsive at 1152 nm, suggesting that photons are absorbed by the bottom p-type silicon electrode and that generation of free carriers underpins optical activity. Applied light causes charging of devices in the high resistance state (HRS), photocurrent in the low resistance state (LRS), and lowering of the set voltage (required to go from the HRS to LRS) and can be used in conjunction with a voltage bias to trigger switching from the HRS to the LRS. We demonstrate negative correlation between set voltage and applied laser power using a 632.8 nm laser source. We propose that, under illumination, increased electron injection and hence a higher rate of creation of Frenkel pairs in the oxide—precursors for the formation of conductive oxygen vacancy filaments—reduce switching voltages. Our results open up the possibility of light-triggered RRAM devices.

  5. InP-based photonic integrated circuit platform on SiC wafer.

    Science.gov (United States)

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  6. Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

    CERN Document Server

    Gonella, L; Silvestri, M; Gerardin, S; Pantano, D; Re, V; Manghisoni, M; Ratti, L; Ranieri, A

    2007-01-01

    The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of th...

  7. Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

    Science.gov (United States)

    Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

    2018-04-01

    Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

  8. Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

    Science.gov (United States)

    Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

    2017-02-01

    The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

  9. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  10. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

    Institute of Scientific and Technical Information of China (English)

    Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

    2012-01-01

    Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

  11. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  12. Recent developments with CMOS SSPM photodetectors

    Energy Technology Data Exchange (ETDEWEB)

    Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

    2009-10-21

    Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

  13. Transmission electron microscopy assessment of conductive-filament formation in Ni-HfO2-Si resistive-switching operational devices

    Science.gov (United States)

    Martín, Gemma; González, Mireia B.; Campabadal, Francesca; Peiró, Francesca; Cornet, Albert; Estradé, Sònia

    2018-01-01

    Resistive random-access memory (ReRAM) devices are currently the object of extensive research to replace flash non-volatile memory. However, elucidation of the conductive-filament formation mechanisms in ReRAM devices at nanoscale is mandatory. In this study, the different states created under real operation conditions of HfO2-based ReRAM devices are characterized through transmission electron microscopy and electron energy-loss spectroscopy. The physical mechanism behind the conductive-filament formation in Ni/HfO2/Si ReRAM devices based on the diffusion of Ni from the electrode to the Si substrate and of Si from the substrate to the electrode through the HfO2 layer is demonstrated.

  14. Timing resolution performance comparison of different SiPM devices

    Energy Technology Data Exchange (ETDEWEB)

    Dolinsky, Sergei, E-mail: dolinsky@ge.com; Fu, Geng; Ivan, Adrian

    2015-11-21

    Silicon photomultiplier (SiPM) devices with improved parameters were recently introduced by several vendors. In addition to published manufacturer performance specifications, different research groups have reported on measurements of the available SiPMs in different operating conditions and using different test setups. In this work we performed a consistent set of test procedures for SiPM devices from various vendors, with focus on Time-of-Flight (TOF) PET detectors applications. SiPMs from Hamamatsu (HPK), SensL, Ketek, and Excelitas were tested. The same experimental setup and procedures were used for comparison of timing resolution for small (3×3 mm{sup 2}) and large (6×6 mm{sup 2} or 4×6 mm{sup 2}) devices coupled to short (3×3×10 mm{sup 3}) and long (4×4×25 mm{sup 3}) LYSO crystals. The potential opportunities for TOF PET detectors are also evaluated.

  15. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    Directory of Open Access Journals (Sweden)

    Z N Khan

    Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  16. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  17. Post-CMOS FinFET integration of bismuth telluride and antimony telluride thin-film-based thermoelectric devices on SoI substrate

    KAUST Repository

    Aktakka, Ethem Erkan

    2013-10-01

    This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb 2Te3) thin-film-based thermoelectric ffect transistors) via a characterized TE-film coevaporationand shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μ W from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers. © 2013 IEEE.

  18. Resistive switching of organic–inorganic hybrid devices of conductive polymer and permeable ultra-thin SiO2 films

    Science.gov (United States)

    Yamamoto, Shunsuke; Kitanaka, Takahisa; Miyashita, Tokuji; Mitsuishi, Masaya

    2018-06-01

    We propose a resistive switching device composed of conductive polymer (PEDOT:PSS) and SiO2 ultra-thin films. The SiO2 film was fabricated from silsesquioxane polymer nanosheets as a resistive switching layer. Devices with metal (Ag or Au)∣SiO2∣PEDOT:PSS architecture show good resistive switching performance with set–reset voltages as low as several hundred millivolts. The device properties and the working mechanism were investigated by varying the electrode material, surrounding atmosphere, and SiO2 film thickness. Results show that resistive switching is based on water and ion migration at the PEDOT:PSS∣SiO2 interface.

  19. Practical silicon Light emitting devices fabricated by standard IC technology

    International Nuclear Information System (INIS)

    Aharoni, H.; Monuko du Plessis; Snyman, L.W.

    2004-01-01

    Full Text:Research activities are described with regard to the development of a comprehensive approach for the practical realization of single crystal Silicon Light Emitting Devices (Si-LEDs). Several interesting suggestions for the fabrication of such devices were made in the literature but they were not adopted by the semiconductor industry because they involve non-standard fabrication schemes, requiring special production lines. Our work presents an alternative approach, proposed and realized in practice by us, permitting the fabrication of Si-LEDs using the standard conventional fully industrialized IC technology ''as is'' without any adaptation. It enables their fabrication in the same production lines of the presently existing IC industry. This means that Si-LEDs can now be fabricated simultaneously with other components, such as transistors, on the same silicon chip, using the same masks and processing procedures. The result is that the yield, reliability, and price of the above Si-LEDs are the same as the other Si devices integrated on the same chip. In this work some structural details of several practical Si-LED's designed by us, as well as experimental results describing their performance are presented. These Si-LED's were fabricated to our specifications utilizing standard CMOS/BiCMOS technology, a fact which comprises an achievement by itself. The structure of the Si-LED's, is designed according to specifications such as the required operating voltage, overall light output intensity, its dependence(linear, or non-linear) on the input signal (voltage or current), light generations location (bulk, or near-surface), the emission pattern and uniformity. Such structural design present a problem since the designer can not use any structural parameters (such as doping levels and junction depths for example) but only those which already exist in the production lines. Since the fabrication procedures in these lines are originally designed for processing of

  20. Total dose effects on the shallow-trench isolation leakage current characteristics in a 0.35microm SiGe BiCMOS technology

    International Nuclear Information System (INIS)

    Niu, G.; Mathew, S.J.; Banerjee, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Subbanna, S.

    1999-01-01

    The effects of gamma irradiation on the Shallow-Trench Isolation (STI) leakage currents in a SiGe BiCMOS technology are investigated for the first time, and shown to be strongly dependent on the irradiation gate bias and operating substrate bias. A positive irradiation gate bias significantly enhances the STI leakage, suggesting a strong field assisted nature of the charge buildup process in the STI. Numerical simulations also suggest the existence of fixed positive charges deep in the bulk along the STI/Si interface. A negative substrate bias, however, effectively suppresses the STI leakage, and can be used to eliminate the leakage produced by the charges deep in the bulk under irradiation

  1. Growth of Si nanocrystals on alumina and integration in memory devices

    Science.gov (United States)

    Baron, T.; Fernandes, A.; Damlencourt, J. F.; De Salvo, B.; Martin, F.; Mazen, F.; Haukka, S.

    2003-06-01

    We present a detailed study of the growth of Si quantum dots (Si QDs) by low pressure chemical vapor deposition on alumina dielectric deposited by atomic layer deposition. The Si QDs density is very high, 1012 cm-2, for a mean diameter between 5 and 10 nm. Al2O3/Si QD stacks have been integrated in memory devices as granular floating gate. The devices demonstrate good charge storage and data retention characteristics.

  2. Next Generation, Si-Compatible Materials and Devices in the Si-Ge-Sn System

    Science.gov (United States)

    2015-10-09

    and conclusions The work initially focused on growth of next generation Ge1-ySny alloys on Ge buffered Si wafers via UHV CVD depositions of Ge3H8...Abstract The work initially focused on growth of next generation Ge1-ySny alloys on Ge buffered Si wafers via UHV CVD depositions of Ge3H8, SnD4. The...AFRL-AFOSR-VA-TR-2016-0044 Next generation, Si -compatible materials and devices in the Si - Ge -Sn system John Kouvetakis ARIZONA STATE UNIVERSITY Final

  3. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  4. Si Complies with GaN to Overcome Thermal Mismatches for the Heteroepitaxy of Thick GaN on Si.

    Science.gov (United States)

    Tanaka, Atsunori; Choi, Woojin; Chen, Renjie; Dayeh, Shadi A

    2017-10-01

    Heteroepitaxial growth of lattice mismatched materials has advanced through the epitaxy of thin coherently strained layers, the strain sharing in virtual and nanoscale substrates, and the growth of thick films with intermediate strain-relaxed buffer layers. However, the thermal mismatch is not completely resolved in highly mismatched systems such as in GaN-on-Si. Here, geometrical effects and surface faceting to dilate thermal stresses at the surface of selectively grown epitaxial GaN layers on Si are exploited. The growth of thick (19 µm), crack-free, and pure GaN layers on Si with the lowest threading dislocation density of 1.1 × 10 7 cm -2 achieved to date in GaN-on-Si is demonstrated. With these advances, the first vertical GaN metal-insulator-semiconductor field-effect transistors on Si substrates with low leakage currents and high on/off ratios paving the way for a cost-effective high power device paradigm on an Si CMOS platform are demonstrated. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  6. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  7. Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

    Science.gov (United States)

    Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

    2018-05-01

    Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

  8. Experimental research on transient ionizing radiation effects of CMOS microcontroller

    International Nuclear Information System (INIS)

    Jin Xiaoming; Fan Ruyu; Chen Wei; Wang Guizhen; Lin Dongsheng; Yang Shanchao; Bai Xiaoyan

    2010-01-01

    This paper presents an experimental test system of CMOS microcontroller EE80C196KC20. Based on this system, the transient ionizing radiation effects on microcontroller were investigated using 'Qiangguang-I' accelerator. The gamma pulse width was 20 ns and the dose rate (for the Si atom) was in the range of 6.7 x 10 6 to 2.0 x 10 8 Gy/s in the experimental study. The disturbance and latchup effects were observed at different dose rate levels. Latchup threshold of the microcontroller was obtained. Disturbance interval and the system power supply current have a relationship with the dose rate level. The transient ionizing radiation induces photocurrent in the PN junctions that are inherent in CMOS circuits. The photocurrent is responsible for the electrical and functional degradation. (authors)

  9. CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel.

    Science.gov (United States)

    Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

    2014-11-01

    A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

  10. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

    2016-01-01

    . The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

  11. Extremely high magnetic-field sensitivity of charge transport in the Mn/SiO2/p-Si hybrid structure

    Directory of Open Access Journals (Sweden)

    N. V. Volkov

    2017-01-01

    Full Text Available We report on abrupt changes in dc resistance and impedance of a diode with the Schottky barrier based on the Mn/SiO2/p-Si structure in a magnetic field. It was observed that at low temperatures the dc and ac resistances of the device change by a factor of more than 106 with an increase in a magnetic field to 200 mT. The strong effect of the magnetic field is observed only above the threshold forward bias across the diode. The ratios between ac and dc magnetoresistances can be tuned from almost zero to 108% by varying the bias. To explain the diversity of magnetotransport phenomena observed in the Mn/SiO2/p-Si structure, it is necessary to attract several mechanisms, which possibly work in different regions of the structure. The anomalously strong magnetotransport effects are attributed to the magnetic-field-dependent impact ionization in the bulk of a Si substrate. At the same time, the conditions for this process are specified by structure composition, which, in turn, affects the current through each structure region. The effect of magnetic field attributed to suppression of impact ionization via two mechanisms leads to an increase in the carrier energy required for initiation of impact ionization. The first mechanism is related to displacement of acceptor levels toward higher energies relative to the top of the valence band and the other mechanism is associated with the Lorentz forces affecting carrier trajectories between scatterings events. The estimated contributions of these two mechanisms are similar. The proposed structure is a good candidate for application in CMOS technology-compatible magnetic- and electric-field sensors and switching devices.

  12. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, Mohamed N.; Alshareef, Husam N.

    2015-01-01

    , which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin

  13. A synaptic device built in one diode-one resistor (1D-1R) architecture with intrinsic SiOx-based resistive switching memory

    Science.gov (United States)

    Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Pan, Chih-Hung; Chang, Kuan-Chang; Tsai, Tsung-Ming; Chang, Ting-Chang; Sze, Simon M.; Lee, Jack C.

    2016-04-01

    We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO2-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)2 defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology.

  14. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  15. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    Science.gov (United States)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  16. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

    2012-01-01

    . The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

  17. High-temperature complementary metal oxide semiconductors (CMOS)

    International Nuclear Information System (INIS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  18. Nanotube devices based crossbar architecture: toward neuromorphic computing

    International Nuclear Information System (INIS)

    Zhao, W S; Gamrat, C; Agnus, G; Derycke, V; Filoramo, A; Bourgoin, J-P

    2010-01-01

    Nanoscale devices such as carbon nanotube and nanowires based transistors, memristors and molecular devices are expected to play an important role in the development of new computing architectures. While their size represents a decisive advantage in terms of integration density, it also raises the critical question of how to efficiently address large numbers of densely integrated nanodevices without the need for complex multi-layer interconnection topologies similar to those used in CMOS technology. Two-terminal programmable devices in crossbar geometry seem particularly attractive, but suffer from severe addressing difficulties due to cross-talk, which implies complex programming procedures. Three-terminal devices can be easily addressed individually, but with limited gain in terms of interconnect integration. We show how optically gated carbon nanotube devices enable efficient individual addressing when arranged in a crossbar geometry with shared gate electrodes. This topology is particularly well suited for parallel programming or learning in the context of neuromorphic computing architectures.

  19. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  20. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications

    KAUST Repository

    Hussain, Aftab M.

    2015-11-26

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today\\'s digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. FY 1999 report on the research and development project of industrial scientific technology - quantum functional devices. Systematical arrangement of the development technology (FY 1991 - 1999); 1999 nendo ryoshika kino soshi no kenkyu kaihatsu. Kaihatsu sareta gijutsu no keitoteki seiri (1991 nendo kara 1999 nendo)

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The FY 1991 to 1999 R and D results of quantum functional devices are systematically summarized. The basic action of the MIM-based single electron tunneling devices is succeeded for the first time in the world. The quantum fine-wire device transistor is realized. The surface tunnel transistor is proposed, application to action demonstration and memories is suggested, and possibility of applicability to multi-value logic circuits is suggested. The multi-emitter RHET is developed to have one device provided with memory and multi-input logic functions, and increase integration 10 times. The TSR quantum dot HEMT memory is developed on a trial basis, to demonstrate 150 K action. The principle of a tera-bit class high-capacity memory is demonstrated using the InAs dot memory. Integration of the quantum band-bonded multi-functional device is described. Possibility is demonstrated for the Si insulation film tunnel device multi-value memory, working on the principle of tunneling between bands via the Si insulation film. The integrated quantum dot functional memory and polariton switch are also described. The single electron logic circuit works for the first time in the world. The integrated CMOS/SET device, which uses high driving force of CMOS, is proposed. (NEDO)

  2. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

  3. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  4. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  5. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  6. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  7. CMOS based capacitance to digital converter circuit for MEMS sensor

    Science.gov (United States)

    Rotake, D. R.; Darji, A. D.

    2018-02-01

    Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

  8. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    International Nuclear Information System (INIS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

    2016-01-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  9. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  10. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  11. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  12. Ge{sub 1−x}Si{sub x} on Ge-based n-type metal–oxide semiconductor field-effect transistors by device simulation combined with high-order stress–piezoresistive relationships

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Chang-Chun, E-mail: changchunlee@cycu.edu.tw [Department of Mechanical Engineering, Chung Yuan Christian University 200, Chung Pei Rd., Chungli City, Taoyuan County 32023, Taiwan, ROC (China); Hsieh, Chia-Ping [Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan, ROC (China); Huang, Pei-Chen; Cheng, Sen-Wen [Department of Mechanical Engineering, Chung Yuan Christian University 200, Chung Pei Rd., Chungli City, Taoyuan County 32023, Taiwan, ROC (China); Liao, Ming-Han [Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan, ROC (China)

    2016-03-01

    The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge{sub 1−x}Si{sub x} alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20 nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge{sub 1−x}Si{sub x} alloys, namely, Ge{sub 0.96}Si{sub 0.04}, Ge{sub 0.93}Si{sub 0.07}, and Ge{sub 0.86}Si{sub 0.14}, are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0 GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30 nm to 4 μm are examined. Results show a significant change in stress when the width is < 300 nm. This phenomenon becomes notable when the Si in the Ge{sub 1−x}Si{sub x} alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge{sub 0.86}Si{sub 0.14} stressor within the device channel. Furthermore, the stresses (S{sub yy}) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge{sub 1−x}Si{sub x} alloys are used, a maximum mobility gain of 28.6% occurs with an ~ 70 nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0 GPa CESL is loaded. However, results indicate that gate width is extended to 200 nm at this point. - Highlights: • A 20 nm Ge-based n

  13. Effects of plasma-deposited silicon nitride passivation on the radiation hardness of CMOS integrated circuits

    International Nuclear Information System (INIS)

    Clement, J.J.

    1980-01-01

    The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point

  14. Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2012-01-01

    We present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si 3N4) based spacer formation via reactive ion etching. Control of Si3N4 thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control. © 2012 IEEE.

  15. Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing

    KAUST Repository

    Rojas, Jhonathan Prieto

    2012-08-01

    We present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si 3N4) based spacer formation via reactive ion etching. Control of Si3N4 thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control. © 2012 IEEE.

  16. Nanosecond-laser induced crosstalk of CMOS image sensor

    Science.gov (United States)

    Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

    2018-02-01

    The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

  17. Influence of Cu diffusion conditions on the switching of Cu-SiO2-based resistive memory devices

    International Nuclear Information System (INIS)

    Thermadam, S. Puthen; Bhagat, S.K.; Alford, T.L.; Sakaguchi, Y.; Kozicki, M.N.; Mitkova, M.

    2010-01-01

    This paper presents a study of Cu diffusion at various temperatures in thin SiO 2 films and the influence of diffusion conditions on the switching of Programmable Metallization Cell (PMC) devices formed from such Cu-doped films. Film composition and diffusion products were analyzed using secondary ion mass spectroscopy, Rutherford backscattering spectrometry, X-ray diffraction and Raman spectroscopy methods. We found a strong dependence of the diffused Cu concentration, which varied between 0.8 at.% and 10 -3 at.%, on the annealing temperature. X-ray diffraction and Raman studies revealed that Cu does not react with the SiO 2 network and remains in elemental form after diffusion for the annealing conditions used. PMC resistive memory cells were fabricated with such Cu-diffused SiO 2 films and device performance, including the stability of the switching voltage, is discussed in the context of the material characteristics.

  18. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  19. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  20. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  1. Impact of surface morphology of Si substrate on performance of Si/ZnO heterojunction devices grown by atomic layer deposition technique

    Energy Technology Data Exchange (ETDEWEB)

    Hazra, Purnima; Singh, Satyendra Kumar [Department of Electronics and Communication Engineering, Motilal Neheru National Institute of Technology, Allahabad 211004 (India); Jit, Satyabrata, E-mail: sjit.ece@itbhu.ac.in [Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi 221005 (India)

    2015-01-01

    In this paper, the authors have investigated the structural, optical, and electrical characteristics of silicon nanowire (SiNW)/zinc oxide (ZnO) core–shell nanostructure heterojunctions and compared their characteristics with Si/ZnO planar heterojunctions to investigate the effect of surface morphology of Si substrate in the characteristics of Si/ZnO heterojunction devices. In this work, ZnO thin film was conformally deposited on both p-type 〈100〉 planar Si substrate and substrate with vertically aligned SiNW arrays by atomic layer deposition (ALD) method. The x-ray diffraction spectra show that the crystalline structures of Si/ZnO heterojunctions are having (101) preferred orientation, whereas vertically oriented SiNW/ZnO core–shell heterojunctions are having (002)-oriented wurtzite crystalline structures. The photoluminescence (PL) spectra of Si/ZnO heterojunctions show a very sharp single peak at 377 nm, corresponding to the bandgap of ZnO material with no other defect peaks in visible region; hence, these devices can have applications only in UV region. On the other hand, SiNW/ZnO heterojunctions are having band-edge peak at 378 nm along with a broad emission band, spreading almost throughout the entire visible region with a peak around 550 nm. Therefore, ALD-grown SiNW/ZnO heterojunctions can emit green and red light simultaneously. Reflectivity measurement of the heterojunctions further confirms the enhancement of visible region peak in the PL spectra of SiNW/ZnO heterojunctions, as the surface of the SiNW/ZnO heterojunctions exhibits extremely low reflectance (<3%) in the visible wavelength region compared to Si/ZnO heterojunctions (>20%). The current–voltage characteristics of both Si/ZnO and SiNW/ZnO heterojunctions are measured with large area ohmic contacts on top and bottom of the structure to compare the electrical characteristics of the devices. Due to large surface to-volume ratio of SiNW/ZnO core–shell heterojunction devices, the

  2. CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

    Science.gov (United States)

    Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

    2011-09-01

    Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

  3. Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

    Science.gov (United States)

    Sahay, Shubham; Suri, Manan

    2017-12-01

    This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

  4. Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

    Science.gov (United States)

    Nagaiah, Padmaja

    As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

  5. Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices

    Science.gov (United States)

    Liao, P. H.; Peng, K. P.; Lin, H. C.; George, T.; Li, P. W.

    2018-05-01

    We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1‑x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1‑x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core ‘building block’ required for the fabrication of Ge-based MOS devices.

  6. The impact of non-uniform channel layer growth on device characteristics in state of the Art Si/SiGe/Si p-metal oxide semiconductor field effect transistors

    International Nuclear Information System (INIS)

    Chang, A.C.K.; Ross, I.M.; Norris, D.J.; Cullis, A.G.; Tang, Y.T.; Cerrina, C.; Evans, A.G.R.

    2006-01-01

    In this study we have highlighted the effect of non-uniform channel layer growth by the direct correlation of the microstructure and electrical characteristics in state-of-the-art pseudomorphic Si/SiGe p-channel metal oxide semiconductor field effect transistor devices fabricated on Si. Two nominally identical sets of devices from adjacent locations of the same wafer were found to have radically different distributions in gate threshold voltages. Due to the close proximity and narrow gate length of the devices, focused ion beam milling was used to prepare a number of thin cross-sections from each of the two regions for subsequent analysis using transmission electron microscopy. It was found that devices from the region giving a very narrow range of gate threshold voltages exhibited a uniform microstructure in general agreement with the intended growth parameters. However, in the second region, which showed a large spread in the gate threshold voltages, profound anomalies in the microstructure were observed. These anomalies consisted of fluctuations in the quality and thickness of the SiGe strained layers. The non-uniform growth of the strained SiGe layer clearly accounted for the poorly controlled threshold voltages of these devices. The results emphasize the importance of good layer growth uniformity to ensure optimum device yield

  7. Impact of surface morphology of Si substrate on performance of Si/ZnO heterojunction devices grown by atomic layer deposition technique

    International Nuclear Information System (INIS)

    Hazra, Purnima; Singh, Satyendra Kumar; Jit, Satyabrata

    2015-01-01

    In this paper, the authors have investigated the structural, optical, and electrical characteristics of silicon nanowire (SiNW)/zinc oxide (ZnO) core–shell nanostructure heterojunctions and compared their characteristics with Si/ZnO planar heterojunctions to investigate the effect of surface morphology of Si substrate in the characteristics of Si/ZnO heterojunction devices. In this work, ZnO thin film was conformally deposited on both p-type 〈100〉 planar Si substrate and substrate with vertically aligned SiNW arrays by atomic layer deposition (ALD) method. The x-ray diffraction spectra show that the crystalline structures of Si/ZnO heterojunctions are having (101) preferred orientation, whereas vertically oriented SiNW/ZnO core–shell heterojunctions are having (002)-oriented wurtzite crystalline structures. The photoluminescence (PL) spectra of Si/ZnO heterojunctions show a very sharp single peak at 377 nm, corresponding to the bandgap of ZnO material with no other defect peaks in visible region; hence, these devices can have applications only in UV region. On the other hand, SiNW/ZnO heterojunctions are having band-edge peak at 378 nm along with a broad emission band, spreading almost throughout the entire visible region with a peak around 550 nm. Therefore, ALD-grown SiNW/ZnO heterojunctions can emit green and red light simultaneously. Reflectivity measurement of the heterojunctions further confirms the enhancement of visible region peak in the PL spectra of SiNW/ZnO heterojunctions, as the surface of the SiNW/ZnO heterojunctions exhibits extremely low reflectance ( 20%). The current–voltage characteristics of both Si/ZnO and SiNW/ZnO heterojunctions are measured with large area ohmic contacts on top and bottom of the structure to compare the electrical characteristics of the devices. Due to large surface to-volume ratio of SiNW/ZnO core–shell heterojunction devices, the output current rating is about 130 times larger compared to their planar

  8. Low Thermal Budget Fabrication of III-V Quantum Nanostructures on Si Substrates

    International Nuclear Information System (INIS)

    Bietti, S; Somaschini, C; Sanguinetti, S; Koguchi, N; Isella, G; Chrastina, D; Fedorov, A

    2010-01-01

    We show the possibility to integrate high quality III-V quantum nanostructures tunable in shape and emission energy on Si-Ge Virtual Substrate. Strong photoemission is observed, also at room temperature, from two different kind of GaAs quantum nanostructures fabricated on Silicon substrate. Due to the low thermal budget of the procedure used for the fabrication of the active layer, Droplet Epitaxy is to be considered an excellent candidate for implementation of optoelectronic devices on CMOS circuits.

  9. Unified model of damage annealing in CMOS, from freeze-in to transient annealing

    International Nuclear Information System (INIS)

    Sander, H.H.; Gregory, B.L.

    Results of an experimental study at 76 0 K, are presented showing that radiation-produced holes in SiO 2 are immobile at this temperature. If an electric field is present in the SiO 2 during low temperature (76 0 K) irradiation to sweep out the mobile electrons, the holes will virtually all be trapped where created and produce a uniform positive charge density in the oxide. These results are the basis for concluding that if a complimentary p,n metal-oxide semiconductor (CMOS) device is irradiated for sufficient time at 76 0 K to build-in an appreciable field, further irradiation with gate bias removed will produce very little additional change in V/sub th/, since the field in the oxide tends to keep all generated electrons in the oxide where they recombine with trapped holes. Hence the hole trapping rate = the hole annihilation rate. The room-temperature annealing following a pulsed gamma exposure occurs in two regimes. The first recovery of V/sub th/ occurs prior to 10 -4 seconds. The magnitude of this very early-time recovery, at room temperature, is oxide-dependent, and oxide process dependent. The rate-of-annealing is what is truly different between a rad-hard and a rad-soft device, since annealing in the hardest devices occurs very quickly at room temperature. (U.S.)

  10. Taking SiC Power Devices to the Final Frontier: Addressing Challenges of the Space Radiation Environment

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan

    2017-01-01

    Silicon carbide power device technology has the potential to enable a new generation of aerospace power systems that demand high efficiency, rapid switching, and reduced mass and volume in order to expand space-based capabilities. For this potential to be realized, SiC devices must be capable of withstanding the harsh space radiation environment. Commercial SiC components exhibit high tolerance to total ionizing dose but to date, have not performed well under exposure to heavy ion radiation representative of the on-orbit galactic cosmic rays. Insertion of SiC power device technology into space applications to achieve breakthrough performance gains will require intentional development of components hardened to the effects of these highly-energetic heavy ions. This work presents heavy-ion test data obtained by the authors over the past several years for discrete SiC power MOSFETs, JFETs, and diodes in order to increase the body of knowledge and understanding that will facilitate hardening of this technology to space radiation effects. Specifically, heavy-ion irradiation data taken under different bias, temperature, and ion beam conditions is presented for devices from different manufacturers, and the emerging patterns discussed.

  11. Light-Triggered Ternary Device and Inverter Based on Heterojunction of van der Waals Materials.

    Science.gov (United States)

    Shim, Jaewoo; Jo, Seo-Hyeon; Kim, Minwoo; Song, Young Jae; Kim, Jeehwan; Park, Jin-Hong

    2017-06-27

    Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (V TH s). Here, we report a finding: the photoinduced drain current in graphene/WSe 2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe 2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe 2 -based MVL logic circuits by using the I D -V G characteristics with two distinctive V TH s. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔV out of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.

  12. Stochastic process variation in deep-submicron CMOS circuits and algorithms

    CERN Document Server

    Zjajo, Amir

    2014-01-01

    One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

  13. A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

    Science.gov (United States)

    Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

    2012-08-01

    We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

  14. Total integrated dose testing of solid-state scientific CD4011, CD4013, and CD4060 devices by irradiation with CO-60 gamma rays

    Science.gov (United States)

    Dantas, A. R. V.; Gauthier, M. K.; Coss, J. R.

    1985-01-01

    The total integrated dose response of three CMOS devices manufactured by Solid State Scientific has been measured using CO-60 gamma rays. Key parameter measurements were made and compared for each device type. The data show that the CD4011, CD4013, and CD4060 produced by this manufacturers should not be used in any environments where radiation levels might exceed 1,000 rad(Si).

  15. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  16. Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor.

    Science.gov (United States)

    Dennis, John Ojur; Ahmad, Farooq; Khir, M Haris Bin Md; Bin Hamid, Nor Hisham

    2015-07-27

    Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

  17. Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, M.

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

  18. Recent developments using TowerJazz SiGe BiCMOS platform for mmWave and THz applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Preisler, Edward J.; Racanelli, Marco

    2013-05-01

    In this paper, we report on the highest speed 240GHz/340GHz FT/FMAX NPN which is now available for product designs in the SBC18H4 process variant of TowerJazz's mature 0.18μm SBC18 silicon germanium (SiGe) BiCMOS technology platform. NFMIN of ~2dB at 50GHz has been obtained with these NPNs. We also describe the integration of earlier generation NPNs with FT/FMAX of 240GHz/280GHz into SBC13H3, a 0.13μm SiGe BiCMOS technology platform. Next, we detail the integration of the deep silicon via (DSV), through silicon via (TSV), high-resistivity substrate, sub-field stitching and hybrid-stitching capability into the 0.18μm SBC18 technology platform to enable higher performance and highly integrated product designs. The integration of SBC18H3 into a thick-film SOI substrate, with essentially unchanged FT and FMAX, is also described. We also report on recent circuit demonstrations using the SBC18H3 platform: (1) a 4-element phased-array 70-100GHz broadband transmit and receive chip with flat saturated power greater than 5dBm and conversion gain of 33dB; (2) a fully integrated W-band 9-element phase-controllable array with responsivity of 800MV/W and receiver NETD is 0.45K with 20ms integration time; (3) a 16-element 4x4 phased-array transmitter with scanning in both the E- and H-planes with maximum EIRP of 23-25 dBm at 100-110GHz; (4) a power efficient 200GHz VCO with -7.25dBm output power and tuning range of 3.5%; and (5) a 320GHz 16-element imaging receiver array with responsivity of 18KV/W at 315GHz, a 3dB bandwidth of 25GHz and a low NEP of 34pW/Hz1/2. Wafer-scale large-die implementation of the phased-arrays and mmWave imagers using stitching in TowerJazz SBC18 process are also discussed.

  19. A 24 GHz CMOS oscillator transmitter with an inkjet printed on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2016-08-15

    CMOS based RF circuits have demonstrated efficient performance over the decades. However, one bottle neck with this technology is its lossy nature for passive components such as inductors, antennas etc. Due to this drawback, passives are either implemented off chip or the designers work with the inefficient passives. This problem can be alleviated by using inkjet printing as a post process on CMOS chip. In this work, we demonstrate inkjet printing of a patterned polymer (SU8) layer on a 24 GHz oscillator chip to isolate the lossy Si substrate from the passives which are inkjet printed on top of the SU8 layer. As a proof of concept, a monopole antenna is printed on top of the SU8 layer integrating it with the oscillator through the exposed RF pads to realize an oscillator transmitter. The proposed hybrid fabrication technique can be extended to multiple dielectric and conductive printed layers to demonstrate complete RF systems on CMOS chips which are efficient, cost-effective and above all small in size. © 2016 IEEE.

  20. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  1. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

    Science.gov (United States)

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-06-17

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

  2. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  3. Development of a 750x750 pixels CMOS imager sensor for tracking applications

    Science.gov (United States)

    Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

    2017-11-01

    Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on

  4. The Pr 2O 3/Si(0 0 1) interface studied by synchrotron radiation photo-electron spectroscopy

    Science.gov (United States)

    Schmeißer, D.; Müssig, H.-J.

    2003-10-01

    Pr 2O 3 is currently under consideration as a potential replacement for SiO 2 as the gate-dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. We studied the Pr 2O 3/Si(0 0 1) interface by a non-destructive depth profiling using synchrotron radiation photoelectron spectroscopy. Our data suggests that there is no silicide formation at the interface. Based on reported results, a chemical reactive interface exists, consisting of a mixed Si-Pr oxide such as (Pr 2O 3) x(SiO 2) 1- x, i.e. as a silicate phase with variable silicon content. This pseudo-binary alloy at the interface offers large flexibility toward successful integration of Pr 2O 3 into future CMOS technologies.

  5. Silicon nano crystal-based non-volatile memory devices

    International Nuclear Information System (INIS)

    Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

    2006-01-01

    In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

  6. Effects of DD and DT neutron irradiation on some Si devices for fusion diagnostics

    International Nuclear Information System (INIS)

    Tanimura, Y.; Iida, T.

    1998-01-01

    In order to examine the difference in the irradiation effects on Si devices between DT and DD neutrons, CCD image sensors, memory ICs and a Si detector were irradiated with neutrons from a deuteron accelerator. The transient effects (i.e. neutron-induced background noises) and permanent effects (i.e. neutron damage) on them were in situ measured during irradiation. Regarding the transient effects, brightening spot noises, soft-error upsets and induced-charge noises were measured for the CCDs, memory ICs and Si detector, respectively. As for the permanent effect, the number of damaged cells of the CCDs and the leakage current of the Si detector increased with neutron fluence. Also we developed a Monte-Carlo code with the TRIM code to evaluate the correlation of DT and DD neutron effects on Si devices. The calculated correlation factor of DT and DD neutron damage for Si devices agreed approximately with the correlation factor obtained from the irradiation experiments on the CCDs and Si detector. (orig.)

  7. Effects of DD and DT neutron irradiation on some Si devices for fusion diagnostics

    Science.gov (United States)

    Tanimura, Yoshihiko; Iida, Toshiyuki

    1998-10-01

    In order to examine the difference in the irradiation effects on Si devices between DT and DD neutrons, CCD image sensors, memory ICs and a Si detector were irradiated with neutrons from a deuteron accelerator. The transient effects (i.e. neutron-induced background noises) and permanent effects (i.e. neutron damage) on them were in situ measured during irradiation. Regarding the transient effects, brightening spot noises, soft-error upsets and induced-charge noises were measured for the CCDs, memory ICs and Si detector, respectively. As for the permanent effect, the number of damaged cells of the CCDs and the leakage current of the Si detector increased with neutron fluence. Also we developed a Monte-Carlo code with the TRIM code to evaluate the correlation of DT and DD neutron effects on Si devices. The calculated correlation factor of DT and DD neutron damage for Si devices agreed approximately with the correlation factor obtained from the irradiation experiments on the CCDs and Si detector.

  8. Optimization of ultra-low-power CMOS transistors

    International Nuclear Information System (INIS)

    Stockinger, M.

    2000-01-01

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  9. Studying the impact of carbon on device performance for strained-Si MOSFETs

    International Nuclear Information System (INIS)

    Lee, M.H.; Chang, S.T.; Peng, C.-Y.; Hsieh, B.-F.; Maikap, S.; Liao, S.-H.

    2008-01-01

    The strained-Si:C long channel MOSFET on a relaxed SiGe buffer is demonstrated in this study. The extracted electron mobility showed an enhancement of ∼40% with the incorporation of 0.25% carbon in strained-Si long channel NMOSFETs. However, no improvement was seen in the output characteristics of the strained-Si:C PMOSFET. The performance enhancement seen is less than the theoretical prediction for increasing carbon content; this is due to the high alloy scattering potential with carbon incorporation, high interface state density (D it ) at the oxide/strained-Si:C interface and interstitial carbon induced Coulomb scattering. However, increased amounts of C may result in degraded device performance. Therefore, a balance must be struck to minimize C-induced extra Coulomb and alloy scattering rates in the fabrication of these devices

  10. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  11. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  12. Modulation of the electroluminescence emission from ZnO/Si NCs/p-Si light-emitting devices via pulsed excitation

    Science.gov (United States)

    López-Vidrier, J.; Gutsch, S.; Blázquez, O.; Hiller, D.; Laube, J.; Kaur, R.; Hernández, S.; Garrido, B.; Zacharias, M.

    2017-05-01

    In this work, the electroluminescence (EL) emission of zinc oxide (ZnO)/Si nanocrystals (NCs)-based light-emitting devices was studied under pulsed electrical excitation. Both Si NCs and deep-level ZnO defects were found to contribute to the observed EL. Symmetric square voltage pulses (50-μs period) were found to notably enhance EL emission by about one order of magnitude. In addition, the control of the pulse parameters (accumulation and inversion times) was found to modify the emission lineshape, long inversion times (i.e., short accumulation times) suppressing ZnO defects contribution. The EL results were discussed in terms of the recombination dynamics taking place within the ZnO/Si NCs heterostructure, suggesting the excitation mechanism of the luminescent centers via a combination of electron impact, bipolar injection, and sequential carrier injection within their respective conduction regimes.

  13. Using a novel spectroscopic reflectometer to optimize a radiation-hardened submicron silicon-on-sapphire CMOS process; Utilisation d'une nouvelle reflectometrie spectroscopique pour optimiser un procede de fabrication CMOS/SOS durci aux radiations

    Energy Technology Data Exchange (ETDEWEB)

    Do, N.T.; Zawaideh, E.; Vu, T.Q.; Warren, G.; Mead, D. [Raytheon Systems company, Microelectronics Div., Newport Beach, California (United States); Li, G.P.; Tsai, C.S. [California Univ., School of Engineering, Newport Beach, CA (United States)

    1999-07-01

    A radiation-hardened sub-micron silicon-on-sapphire CMOS process is monitored and optimized using a novel optical technique based on spectroscopic reflectometry. Quantitative measurements of the crystal quality, surface roughness, and device radiation hardness show excellent correlation between this technique and the Atomic Force Microscopy. (authors)

  14. Scaling of ion implanted Si:P single electron devices

    International Nuclear Information System (INIS)

    Escott, C C; Hudson, F E; Chan, V C; Petersson, K D; Clark, R G; Dzurak, A S

    2007-01-01

    We present a modelling study on the scaling prospects for phosphorus in silicon (Si:P) single electron devices using readily available commercial and free-to-use software. The devices comprise phosphorus ion implanted, metallically doped (n + ) dots (size range 50-500 nm) with source and drain reservoirs. Modelling results are compared to measurements on fabricated devices and discussed in the context of scaling down to few-electron structures. Given current fabrication constraints, we find that devices with 70-75 donors per dot should be realizable. We comment on methods for further reducing this number

  15. Scaling of ion implanted Si:P single electron devices

    Energy Technology Data Exchange (ETDEWEB)

    Escott, C C [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Hudson, F E [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Chan, V C [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Petersson, K D [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia); Clark, R G [Centre for Quantum Computer Technology, School of Physics, UNSW, Sydney, 2052 (Australia); Dzurak, A S [Centre for Quantum Computer Technology, School of Electrical Engineering and Telecommunications, UNSW, Sydney, NSW 2052 (Australia)

    2007-06-13

    We present a modelling study on the scaling prospects for phosphorus in silicon (Si:P) single electron devices using readily available commercial and free-to-use software. The devices comprise phosphorus ion implanted, metallically doped (n{sup +}) dots (size range 50-500 nm) with source and drain reservoirs. Modelling results are compared to measurements on fabricated devices and discussed in the context of scaling down to few-electron structures. Given current fabrication constraints, we find that devices with 70-75 donors per dot should be realizable. We comment on methods for further reducing this number.

  16. MBE-grown Si and Si1−xGex quantum dots embedded within epitaxial Gd2O3 on Si(111) substrate for floating gate memory device

    International Nuclear Information System (INIS)

    Manna, S; Aluguri, R; Katiyar, A; Ray, S K; Das, S; Laha, A; Osten, H J

    2013-01-01

    Si and Si 1−x Ge x quantum dots embedded within epitaxial Gd 2 O 3 grown by molecular beam epitaxy have been studied for application in floating gate memory devices. The effect of interface traps and the role of quantum dots on the memory properties have been studied using frequency-dependent capacitance–voltage and conductance–voltage measurements. Multilayer quantum dot memory comprising four and five layers of Si quantum dots exhibits a superior memory window to that of single-layer quantum dot memory devices. It has also been observed that single-layer Si 1−x Ge x quantum dots show better memory characteristics than single-layer Si quantum dots. (paper)

  17. Fabrication of integrated metallic MEMS devices

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

    2002-01-01

    A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators are characteri......A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

  18. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  19. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  20. Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

    Science.gov (United States)

    Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

    2013-01-01

    The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

  1. Degradation of SiGe devices by proton irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Ohyama, Hidenori; Hayama, Kiyoteru [Kumamoto National Coll. of Technology, Nishigoshi (Japan); Vanhellemont, J; Takami, Yasukiyo; Sunaga, Hiromi; Nashiyama, Isamu; Uwatoko, Yoshiya; Poortmans, J; Caymax, M

    1997-03-01

    The degradation and recovery behavior of strained Si{sub 1-x}Ge{sub x} diodes and heterojunction bipolar transistors (HBTs) by irradiated by protons are studied. The degradation of device performance and the generation of lattice defects are reported as a function of fluence and germanium content and also compared extensively with previous results obtained on electron and neutron irradiated devices. In order to study the recovery behavior of the irradiated devices, isochronal annealing is performed. The radiation source dependence of the degradation is discussed taking into account the number of knock-on atoms and the nonionizing energy loss (NIEL). (author)

  2. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  3. CMOS and BiCMOS process integration and device characterization

    CERN Document Server

    El-Kareh, Badih

    2009-01-01

    Covers both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. This book also covers silicon devices and integrated process technologies. It discusses modern silicon devices, their characteristics, and interactions with process parameters.

  4. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

    Energy Technology Data Exchange (ETDEWEB)

    Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  5. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

    Science.gov (United States)

    Li, Shu; Zhang, Tong

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  6. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

    International Nuclear Information System (INIS)

    Li Shu; Zhang Tong

    2008-01-01

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

  7. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    International Nuclear Information System (INIS)

    Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

  8. Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

    International Nuclear Information System (INIS)

    Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

    2010-01-01

    The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

  9. SiGe Integrated Circuit Developments for SQUID/TES Readout

    Science.gov (United States)

    Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

    2018-03-01

    SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

  10. First-principles calculations of orientation dependence of Si thermal oxidation based on Si emission model

    Science.gov (United States)

    Nagura, Takuya; Kawachi, Shingo; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Kageshima, Hiroyuki; Endoh, Tetsuo; Shiraishi, Kenji

    2018-04-01

    It is expected that the off-state leakage current of MOSFETs can be reduced by employing vertical body channel MOSFETs (V-MOSFETs). However, in fabricating these devices, the structure of the Si pillars sometimes cannot be maintained during oxidation, since Si atoms sometimes disappear from the Si/oxide interface (Si missing). Thus, in this study, we used first-principles calculations based on the density functional theory, and investigated the Si emission behavior at the various interfaces on the basis of the Si emission model including its atomistic structure and dependence on Si crystal orientation. The results show that the order in which Si atoms are more likely to be emitted during thermal oxidation is (111) > (110) > (310) > (100). Moreover, the emission of Si atoms is enhanced as the compressive strain increases. Therefore, the emission of Si atoms occurs more easily in V-MOSFETs than in planar MOSFETs. To reduce Si missing in V-MOSFETs, oxidation processes that induce less strain, such as wet or pyrogenic oxidation, are necessary.

  11. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  12. Single-photon sensitive fast ebCMOS camera system for multiple-target tracking of single fluorophores: application to nano-biophotonics

    Science.gov (United States)

    Cajgfinger, Thomas; Chabanat, Eric; Dominjon, Agnes; Doan, Quang T.; Guerin, Cyrille; Houles, Julien; Barbier, Remi

    2011-03-01

    Nano-biophotonics applications will benefit from new fluorescent microscopy methods based essentially on super-resolution techniques (beyond the diffraction limit) on large biological structures (membranes) with fast frame rate (1000 Hz). This trend tends to push the photon detectors to the single-photon counting regime and the camera acquisition system to real time dynamic multiple-target tracing. The LUSIPHER prototype presented in this paper aims to give a different approach than those of Electron Multiplied CCD (EMCCD) technology and try to answer to the stringent demands of the new nano-biophotonics imaging techniques. The electron bombarded CMOS (ebCMOS) device has the potential to respond to this challenge, thanks to the linear gain of the accelerating high voltage of the photo-cathode, to the possible ultra fast frame rate of CMOS sensors and to the single-photon sensitivity. We produced a camera system based on a 640 kPixels ebCMOS with its acquisition system. The proof of concept for single-photon based tracking for multiple single-emitters is the main result of this paper.

  13. Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

    International Nuclear Information System (INIS)

    Brucker, G.J.; Heagerty, W.

    1976-01-01

    This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

  14. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

  15. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    Science.gov (United States)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  16. Nanoelectronic device applications handbook

    CERN Document Server

    Morris, James E

    2013-01-01

    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that range from nano-scaled complementary metal-oxide-semiconductor (CMOS) devices through recent developments in nano capacitors and AlGaAs/GaAs devices. The contributors are world-renowned experts from academia and industry from around the globe. The handbook explores current research into potentially disruptive technologies for a post-CMOS world.These include: Nanoscale advance

  17. CMOS SPDT switch for WLAN applications

    International Nuclear Information System (INIS)

    Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

    2015-01-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

  18. Cmos spdt switch for wlan applications

    Science.gov (United States)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  19. DICE based flip-flop with SET pulse discriminator on a 90 nm bulk CMOS process

    International Nuclear Information System (INIS)

    Maru, A.; Kuboyama, S.; Shindou, H.; Ebihara, T.; Tamura, T.; Makihara, A.; Hirao, Toshio

    2010-01-01

    In recent years, due to the demand for increased integration and device scaling, integrated circuits have been designed with the design rule less than 100 nm. In such integrated circuits, SEUs and SETs are serious problems because their supply voltage and the threshold voltage of the transistors are decreased. A DICE-based flip-flop with a SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated. Its improved performance was demonstrated through radiation testing and discussion. SEU sensitivity for the angled irradiation was measured and discussed in this study. The test of edge-on irradiation was performed for the first time. The importance of the angled irradiation for the memory cells that have redundant memory nodes was demonstrated. (author)

  20. Using a novel spectroscopic reflectometer to optimize a radiation-hardened submicron silicon-on-sapphire CMOS process

    International Nuclear Information System (INIS)

    Do, N.T.; Zawaideh, E.; Vu, T.Q.; Warren, G.; Mead, D.; Do, N.T.; Li, G.P.; Tsai, C.S.

    1999-01-01

    A radiation-hardened sub-micron silicon-on-sapphire CMOS process is monitored and optimized using a novel optical technique based on spectroscopic reflectometry. Quantitative measurements of the crystal quality, surface roughness, and device radiation hardness show excellent correlation between this technique and the Atomic Force Microscopy. (authors)

  1. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, J.

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

  2. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  3. Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET

    Science.gov (United States)

    2016-02-04

    AFRL-AFOSR-JP-TR-2016-0037 Device Performance and Reliablity Improvements of AlGaBN/GaN/Si MOSFET Robert Wallace UNIVERSITY OF TEXAS AT DALLAS Final...GaN/Si MOSFET 5a.  CONTRACT NUMBER 5b.  GRANT NUMBER FA2386-14-1-4069 5c.  PROGRAM ELEMENT NUMBER 61102F 6. AUTHOR(S) Robert Wallace 5d.  PROJECT...AOARD Grant FA2386-14-1-4069 Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET US 12 month extension (2014 – 2015) for current

  4. Radiation effects on custom MOS devices

    International Nuclear Information System (INIS)

    Harris, R.

    1999-05-01

    This Thesis consists of four chapters: The first is primarily for background information on the effects of radiation on MOS devices and the theory of wafer bonding; the second gives a full discussion of all practical work carried out for manufacture of Field Effect test Capacitors, the third discusses manufacture of vacuum insulator Field Effect Transistors (FET's) and the fourth discusses the testing of these devices. Using a thermally bonded field effect capacitor structure, a vacuum dielectric was studied for use in high radiation environments with a view to manufacturing a CMOS compatible, micro machined transistor. Results are given in the form of high frequency C-V curves before and after a 120 kGy(Si), 12 MRad(Si), dose from a Co 60 source showing a 1 Volt shift. The work is then extended to the design and manufacture of a micro machined, under-etch technique, Field Effect Transistor for use in high radiation areas. Results are shown for Threshold, Subthreshold and Transfer characteristics before and after irradiation up to a total dose of 100kGy or 10MRad. The conclusion from this work is that it should be possible to commercially manufacture practical vacuum dielectric field effect transistors which are radiation hard to at least 120 kGy(Si). (author)

  5. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  6. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-06

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  7. Thermosonic wire bonding of IC devices using palladium wire

    International Nuclear Information System (INIS)

    Shze, J.H.; Poh, M.T.; Tan, R.M.

    1996-01-01

    The feasibility of replacing gold wire by palladium wire in thermosonic wire bonding of CMOS and bipolar devices are studied in terms of the manufacturability, physical, electrical and assembly performance. The results that palladium wire is a viable option for bonding the bipolar devices but not the CMOS devices

  8. InP on SOI devices for optical communication and optical network on chip

    Science.gov (United States)

    Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

    2011-01-01

    For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

  9. Noise and its reduction in graphene based nanopore devices

    International Nuclear Information System (INIS)

    Kumar, Ashvani; Park, Kyeong-Beom; Kim, Hyun-Mi; Kim, Ki-Bum

    2013-01-01

    Ionic current fluctuations in graphene nanopore devices are a ubiquitous phenomenon and are responsible for degraded spatial and temporal resolution. Here, we descriptively investigate the impact of different substrate materials (Si and quartz) and membrane thicknesses on noise characteristics of graphene nanopore devices. To mitigate the membrane fluctuations and pin-hole defects, a SiN x membrane is transferred onto the substrate and a pore of approximately 70 nm in diameter is perforated prior to the graphene transfer. Comprehensive noise study reveals that the few layer graphene transferred onto the quartz substrate possesses low noise level and higher signal to noise ratio as compared to single layer graphene, without deteriorating the spatial resolution. The findings here point to improvement of graphene based nanopore devices for exciting opportunities in future single-molecule genomic screening devices. (paper)

  10. Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

    Science.gov (United States)

    Bischoff, Paul

    The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

  11. Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

    Science.gov (United States)

    Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

    2015-08-01

    This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

  12. Design and simulation of Gaussian shaping amplifier made only with CMOS FET for FEE of particle detector

    International Nuclear Information System (INIS)

    Wembe Tafo Evariste; Su Hong; Qian Yi; Kong Jie; Wang Tongxi

    2010-01-01

    The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip, Si (Li), CdZnTe and CsI detectors, etc., which can be further integrated the whole system and adopted to develop CMOS-based application, specific integrated circuit for Front End Electronics (FEE) of read-out system of nuclear physics, particle physics and astrophysics research, etc. It's why we used only CMOS transistor to develop the entire system. A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC 4 filter, we perform shaping time in the range, 465 ns to 2.76μs with a low output resistance and the linearity almost good. (authors)

  13. Advances in CMOS solid-state photomultipliers for scintillation detector applications

    Energy Technology Data Exchange (ETDEWEB)

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric [Radiation Monitoring Devices, 44 Hunt Street, Watertownm, MA 02472 (United States); Augustine, Frank L., E-mail: JChristian@RMDInc.co [Augustine Engineering, 2115 Park Dale Ln, Encinitas, CA 92024 (United States)

    2010-12-11

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

  14. Modeling and evaluation of a high-resolution CMOS detector for cone-beam CT of the extremities.

    Science.gov (United States)

    Cao, Qian; Sisniega, Alejandro; Brehler, Michael; Stayman, J Webster; Yorkston, John; Siewerdsen, Jeffrey H; Zbijewski, Wojciech

    2018-01-01

    Quantitative assessment of trabecular bone microarchitecture in extremity cone-beam CT (CBCT) would benefit from the high spatial resolution, low electronic noise, and fast scan time provided by complementary metal-oxide semiconductor (CMOS) x-ray detectors. We investigate the performance of CMOS sensors in extremity CBCT, in particular with respect to potential advantages of thin (CMOS x-ray detector incorporating the effects of CsI:Tl scintillator thickness was developed. Simulation studies were performed using nominal extremity CBCT acquisition protocols (90 kVp, 0.126 mAs/projection). A range of scintillator thickness (0.35-0.75 mm), pixel size (0.05-0.4 mm), focal spot size (0.05-0.7 mm), magnification (1.1-2.1), and dose (15-40 mGy) was considered. The detectability index was evaluated for both CMOS and a-Si:H flat-panel detector (FPD) configurations for a range of imaging tasks emphasizing spatial frequencies associated with feature size aobj. Experimental validation was performed on a CBCT test bench in the geometry of a compact orthopedic CBCT system (SAD = 43.1 cm, SDD = 56.0 cm, matching that of the Carestream OnSight 3D system). The test-bench studies involved a 0.3 mm focal spot x-ray source and two CMOS detectors (Dalsa Xineos-3030HR, 0.099 mm pixel pitch) - one with the standard CsI:Tl thickness of 0.7 mm (C700) and one with a custom 0.4 mm thick scintillator (C400). Measurements of modulation transfer function (MTF), detective quantum efficiency (DQE), and CBCT scans of a cadaveric knee (15 mGy) were obtained for each detector. Optimal detectability for high-frequency tasks (feature size of ~0.06 mm, consistent with the size of trabeculae) was ~4× for the C700 CMOS detector compared to the a-Si:H FPD at nominal system geometry of extremity CBCT. This is due to ~5× lower electronic noise of a CMOS sensor, which enables input quantum-limited imaging at smaller pixel size. Optimal pixel size for high-frequency tasks was CMOS

  15. Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

    Science.gov (United States)

    Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

    2018-05-01

    Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

  16. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  17. Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

    Science.gov (United States)

    Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

    2013-05-06

    In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

  18. Prospects for charge sensitive amplifiers in scaled CMOS

    Science.gov (United States)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-03-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

  19. Prospects for charge sensitive amplifiers in scaled CMOS

    International Nuclear Information System (INIS)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-01-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

  20. Pt silicide/poly-Si Schottky diodes as temperature sensors for bolometers

    Energy Technology Data Exchange (ETDEWEB)

    Yuryev, V. A., E-mail: vyuryev@kapella.gpi.ru; Chizh, K. V.; Chapnin, V. A.; Mironov, S. A.; Dubkov, V. P.; Uvarov, O. V.; Kalinushkin, V. P. [A. M. Prokhorov General Physics Institute of the Russian Academy of Sciences, 38 Vavilov Street, Moscow 119991 (Russian Federation); Senkov, V. M. [P. N. Lebedev Physical Institute of the Russian Academy of Sciences, 53 Leninskiy Avenue, Moscow 119991 (Russian Federation); Nalivaiko, O. Y. [JSC “Integral” – “Integral” Holding Management Company, 121A, Kazintsa I. P. Street, Minsk 220108 (Belarus); Novikau, A. G.; Gaiduk, P. I. [Belarusian State University, 4 Nezavisimosti Avenue, 220030 Minsk (Belarus)

    2015-05-28

    Platinum silicide Schottky diodes formed on films of polycrystalline Si doped by phosphorus are demonstrated to be efficient and manufacturable CMOS-compatible temperature sensors for microbolometer detectors of radiation. Thin-film platinum silicide/poly-Si diodes have been produced by a CMOS-compatible process on artificial Si{sub 3}N{sub 4}/SiO{sub 2}/Si(001) substrates simulating the bolometer cells. Layer structure and phase composition of the original Pt/poly-Si films and the Pt silicide/poly-Si films synthesized by a low-temperature process have been studied by means of the scanning transmission electron microscopy; they have also been explored by means of the two-wavelength X-ray structural phase analysis and the X-ray photoelectron spectroscopy. Temperature coefficient of voltage for the forward current of a single diode is shown to reach the value of about −2%/ °C in the temperature interval from 25 to 50 °C.

  1. Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies.

    Science.gov (United States)

    Horie, Yu; Han, Seunghoon; Lee, Jeong-Yub; Kim, Jaekwan; Kim, Yongsung; Arbabi, Amir; Shin, Changgyun; Shi, Lilong; Arbabi, Ehsan; Kamali, Seyedeh Mahsa; Lee, Hong-Seok; Hwang, Sungwoo; Faraon, Andrei

    2017-05-10

    We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated CMOS image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO 2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 60-80%, and have an almost insensitive response over a ± 20° angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

  2. Research on design and firing performance of Si-based detonator

    Directory of Open Access Journals (Sweden)

    Rui-zhen Xie

    2014-03-01

    Full Text Available For the chip integration of MEMS (micro-electromechanical system safety and arming device, a miniature detonator needs to be developed to reduce the weight and volume of explosive train. A Si-based micro-detonator is designed and fabricated, which meets the requirement of MEMS safety and arming device. The firing sensitivity of micro-detonator is tested according to GJB/z377A-94 sensitivity test methods: Langlie. The function time of micro-detonator is measured using wire probe and photoelectric transducer. The result shows the average firing voltage is 6.4 V when the discharge capacitance of firing electro-circuit is 33 μF. And the average function time is 5.48 μs. The firing energy actually utilized by Si-based micro-detonator is explored.

  3. Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.

    Science.gov (United States)

    Yongsu Lee; Hyeonwoo Lee; Seunghyup Yoo; Hoi-Jun Yoo

    2016-08-01

    The sticker-type sensor system is proposed targeting ECG/PPG concurrent monitoring for cardiovascular diseases. The stickers are composed of two types: Hub and Sensor-node (SN) sticker. Low-power CMOS SoC for measuring ECG and PPG signal is hybrid integrated with organic light emitting diodes (OLEDs) and organic photo detector (OPD). The sticker has only 2g weight and only consumes 141μW. The optical calibration loop is adopted for maintaining SNR of PPG signal higher than 30dB. The pulse arrival time (PAT) and SpO2 value can be extracted from various body parts and verified comparing with the reference device from 20 people in-vivo experiments.

  4. Athermal Photonic Devices and Circuits on a Silicon Platform

    Science.gov (United States)

    Raghunathan, Vivek

    In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for

  5. Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

    2017-07-15

    A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  6. Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

    Science.gov (United States)

    Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

    2009-09-07

    We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

  7. Gun muzzle flash detection using a CMOS single photon avalanche diode

    Science.gov (United States)

    Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

    2013-10-01

    Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

  8. Effect of boron-doping on the luminescent and electrical properties of a CdS/Si heterostructure based on Si nanoporous pillar array

    Energy Technology Data Exchange (ETDEWEB)

    Yan, Ling Ling [Department of Physics and Laboratory of Material Physics, Zhengzhou University, Zhengzhou 450052 (China); College of Physics and Chemistry, Henan Polytechnic University, Jiaozuo 454000 (China); Wang, Xiao Bo [Department of Physics and Laboratory of Material Physics, Zhengzhou University, Zhengzhou 450052 (China); College of Physics and Electrical Engineering, Anyang Normal University, Anyang 455000 (China); Cai, Xiao Jun [Department of Physics and Laboratory of Material Physics, Zhengzhou University, Zhengzhou 450052 (China); Li, Xin Jian, E-mail: lixj@zzu.edu.cn [Department of Physics and Laboratory of Material Physics, Zhengzhou University, Zhengzhou 450052 (China)

    2015-05-25

    Highlights: • B-doped CdS/Si-NPA heterostructure was prepared by a CBD method. • B-doping does not affect the crystal structure and surface morphology of CdS/Si-NPA. • The optical/electrical properties of CdS/Si-NPA could be tuned by changing [B]/[Cd] ratio. • CdS/Si-NPA with optimal physical properties could be prepared with [B]/[Cd] = 0.01. • The method may find applications in preparing CdS/Si-NPA devices with high device performances. - Abstract: Using silicon nanoporous pillar array (Si-NPA) as substrates and boric acid as dopant source, a series of CdS/Si nanoheterostructures were prepared by growing B-doped CdS thin films on Si-NPA via a chemical bath deposition (CBD) method. The structural, optical and electrical properties of CdS/Si-NPA were studied as a function of the [B]/[Cd] ratio of the initial CBD solutions. Our results disclosed that B concentration could be tuned effectively through changing the ratio of [B]/[Cd], which would bring large variation on the optical and electrical properties of CdS/Si-NPA without affecting its crystal structure and surface morphology. The samples with optimal optical and electrical properties were prepared with [B]/[Cd] = 0.01, in which the physical properties of relatively strong light absorption, small electrical resistivity, low turn-on voltage, small leakage current density and high breakdown voltage could be obtained. These results indicated that B-doping might be an effective path for promoting the performance of the optoelectronic devices based on CdS/Si-NPA.

  9. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  10. Selective ablation of photovoltaic materials with UV laser sources for monolithic interconnection of devices based on a-Si:H

    Energy Technology Data Exchange (ETDEWEB)

    Molpeceres, C. [Centro Laser UPM, Univ. Politecnica de Madrid, Crta. de Valencia Km 7.3, 28031 Madrid (Spain)], E-mail: carlos.molpeceres@upm.es; Lauzurica, S.; Garcia-Ballesteros, J.J.; Morales, M.; Guadano, G.; Ocana, J.L. [Centro Laser UPM, Univ. Politecnica de Madrid, Crta. de Valencia Km 7.3, 28031 Madrid (Spain); Fernandez, S.; Gandia, J.J. [Dept. de Energias Renovables, Energia Solar Fotovoltaica, CIEMAT, Avda, Complutense 22, 28040 Madrid (Spain); Villar, F.; Nos, O.; Bertomeu, J. [CeRMAE Dept. Fisica Aplicada i Optica, Universitat de Barcelona, Av. Diagonal 647, 08028 Barcelona (Spain)

    2009-03-15

    Lasers are essential tools for cell isolation and monolithic interconnection in thin-film-silicon photovoltaic technologies. Laser ablation of transparent conductive oxides (TCOs), amorphous silicon structures and back contact removal are standard processes in industry for monolithic device interconnection. However, material ablation with minimum debris and small heat affected zone is one of the main difficulty is to achieve, to reduce costs and to improve device efficiency. In this paper we present recent results in laser ablation of photovoltaic materials using excimer and UV wavelengths of diode-pumped solid-state (DPSS) laser sources. We discuss results concerning UV ablation of different TCO and thin-film silicon (a-Si:H and nc-Si:H), focussing our study on ablation threshold measurements and process-quality assessment using advanced optical microscopy techniques. In that way we show the advantages of using UV wavelengths for minimizing the characteristic material thermal affection of laser irradiation in the ns regime at higher wavelengths. Additionally we include preliminary results of selective ablation of film on film structures irradiating from the film side (direct writing configuration) including the problem of selective ablation of ZnO films on a-Si:H layers. In that way we demonstrate the potential use of UV wavelengths of fully commercial laser sources as an alternative to standard backscribing process in device fabrication.

  11. Selective ablation of photovoltaic materials with UV laser sources for monolithic interconnection of devices based on a-Si:H

    International Nuclear Information System (INIS)

    Molpeceres, C.; Lauzurica, S.; Garcia-Ballesteros, J.J.; Morales, M.; Guadano, G.; Ocana, J.L.; Fernandez, S.; Gandia, J.J.; Villar, F.; Nos, O.; Bertomeu, J.

    2009-01-01

    Lasers are essential tools for cell isolation and monolithic interconnection in thin-film-silicon photovoltaic technologies. Laser ablation of transparent conductive oxides (TCOs), amorphous silicon structures and back contact removal are standard processes in industry for monolithic device interconnection. However, material ablation with minimum debris and small heat affected zone is one of the main difficulty is to achieve, to reduce costs and to improve device efficiency. In this paper we present recent results in laser ablation of photovoltaic materials using excimer and UV wavelengths of diode-pumped solid-state (DPSS) laser sources. We discuss results concerning UV ablation of different TCO and thin-film silicon (a-Si:H and nc-Si:H), focussing our study on ablation threshold measurements and process-quality assessment using advanced optical microscopy techniques. In that way we show the advantages of using UV wavelengths for minimizing the characteristic material thermal affection of laser irradiation in the ns regime at higher wavelengths. Additionally we include preliminary results of selective ablation of film on film structures irradiating from the film side (direct writing configuration) including the problem of selective ablation of ZnO films on a-Si:H layers. In that way we demonstrate the potential use of UV wavelengths of fully commercial laser sources as an alternative to standard backscribing process in device fabrication.

  12. Design and Investigation of SST/nc-Si:H/M (M = Ag, Au, Ni and M/nc-Si:H/M Multifunctional Devices

    Directory of Open Access Journals (Sweden)

    A. F. Qasrawi

    2013-01-01

    Full Text Available Hydrogenated nanocrystalline Silicon thin films prepared by the very high frequency chemical vapor deposition technique (VHF-CVD on stainless steel (SST substrates are used to design Schottky point contact barriers for the purpose of solar energy conversion and passive electronic component applications. In this process, the contact performance between SST and M (M = Ag, Au, and Ni and between Ag, Au, and Ni electrodes was characterized by means of current-voltage, capacitance-voltage, and light intensity dependence of short circuit ( current and open circuit voltage ( of the contacts. Particularly, the devices ideality factors, barrier heights were evaluated by the Schottky method and compared to the Cheung's. Best Schottky device performance with lowest ideality factor suitable for electronic applications was observed in the SST/nc-Si:H/Ag structure. This device reflects a of 229 mV with an of 1.6 mA/cm2 under an illumination intensity of ~40 klux. On the other hand, the highest being 9.0 mA/cm2 and the of 53.1 mV were observed for Ni/nc-Si:H/Au structure. As these voltages represent the maximum biasing voltage for some of the designed devices, the SST/nc-Si:H/M and M/nc-Si:H/M can be regarded as multifunctional self-energy that provided electronic devices suitable for active or passive applications.

  13. Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

    Science.gov (United States)

    Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

    2009-05-01

    This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

  14. BCB Bonding Technology of Back-Side Illuminated COMS Device

    Science.gov (United States)

    Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

    2018-03-01

    Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

  15. A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

    Science.gov (United States)

    Fu, Guoqing; Sonkusale, Sameer R

    2018-06-01

    Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

  16. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

    Science.gov (United States)

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2011-10-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

  17. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  18. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  19. Ion beam synthesis of semiconductor nanoparticles for Si based optoelectronic devices

    International Nuclear Information System (INIS)

    Gonzalez-Varona, O.; Perez-Rodriguez, A.; Garrido, B.; Bonafos, C.; Lopez, M.; Morante, J.R.; Montserrat, J.; Rodriguez, R.

    2000-01-01

    Intense white (to the eye) luminescence has been obtained by multiple implantation of Si + and C + ions into thermal SiO 2 and a post-implantation annealing process. This white emission is a consequence of the convolution of three luminescence peaks centred at about 1.45 eV (infrared with a long tail in the red), 2.1 eV (yellow) and 2.8 eV (blue). These emissions have been correlated to the synthesis of nanocrystals of Si and SiC, and the existence of C-rich precipitates. Cross section TEM shows a buried layer with dark contrast, which correlates with the maximum of the C implanted profile, and likely with a high density of C-rich amorphous domains. Besides, two kinds of nanocrystalline precipitates are found, which have been identified as Si and hexagonal 6H-SiC by electron diffraction experiments. To our knowledge, these data provide the first experimental evidence on the ion beam synthesis of nanocrystalline 6H-SiC embedded in SiO 2 . Correlation with previous data gives support to the assignment of the infrared, yellow and blue peaks with the Si, C-rich and SiC precipitate phases and/or its interfaces with SiO 2

  20. Ion beam synthesis of semiconductor nanoparticles for Si based optoelectronic devices

    Energy Technology Data Exchange (ETDEWEB)

    Gonzalez-Varona, O.; Perez-Rodriguez, A.; Garrido, B.; Bonafos, C.; Lopez, M.; Morante, J.R.; Montserrat, J.; Rodriguez, R

    2000-03-01

    Intense white (to the eye) luminescence has been obtained by multiple implantation of Si{sup +} and C{sup +} ions into thermal SiO{sub 2} and a post-implantation annealing process. This white emission is a consequence of the convolution of three luminescence peaks centred at about 1.45 eV (infrared with a long tail in the red), 2.1 eV (yellow) and 2.8 eV (blue). These emissions have been correlated to the synthesis of nanocrystals of Si and SiC, and the existence of C-rich precipitates. Cross section TEM shows a buried layer with dark contrast, which correlates with the maximum of the C implanted profile, and likely with a high density of C-rich amorphous domains. Besides, two kinds of nanocrystalline precipitates are found, which have been identified as Si and hexagonal 6H-SiC by electron diffraction experiments. To our knowledge, these data provide the first experimental evidence on the ion beam synthesis of nanocrystalline 6H-SiC embedded in SiO{sub 2}. Correlation with previous data gives support to the assignment of the infrared, yellow and blue peaks with the Si, C-rich and SiC precipitate phases and/or its interfaces with SiO{sub 2}.

  1. Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

    Science.gov (United States)

    Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

    2017-10-02

    Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

  2. Radiation response of high speed CMOS integrated circuits

    International Nuclear Information System (INIS)

    Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

  3. Effective Passivation and Tunneling Hybrid a-SiOx(In) Layer in ITO/n-Si Heterojunction Photovoltaic Device.

    Science.gov (United States)

    Gao, Ming; Wan, Yazhou; Li, Yong; Han, Baichao; Song, Wenlei; Xu, Fei; Zhao, Lei; Ma, Zhongquan

    2017-05-24

    In this article, using controllable magnetron sputtering of indium tin oxide (ITO) materials on single crystal silicon at 100 °C, the optoelectronic heterojunction frame of ITO/a-SiO x (In)/n-Si is simply fabricated for the purpose of realizing passivation contact and hole tunneling. It is found that the gradation profile of indium (In) element together with silicon oxide (SiO x /In) within the ultrathin boundary zone between ITO and n-Si occurs and is characterized by X-ray photoelectron spectroscopy with the ion milling technique. The atomistic morphology and physical phase of the interfacial layer has been observed with a high-resolution transmission electron microscope. X-ray diffraction, Hall effect measurement, and optical transmittance with Tauc plot have been applied to the microstructure and property analyses of ITO thin films, respectively. The polycrystalline and amorphous phases have been verified for ITO films and SiO x (In) hybrid layer, respectively. For the quantum transport, both direct and defect-assisted tunneling of photogenerated holes through the a-SiO x (In) layer is confirmed. Besides, there is a gap state correlative to the indium composition and located at E v + 4.60 eV in the ternary hybrid a-SiO x (In) layer that is predicted by density functional theory of first-principles calculation, which acts as an "extended delocalized state" for direct tunneling of the photogenerated holes. The reasonable built-in potential (V bi = 0.66 V) and optimally controlled ternary hybrid a-SiO x (In) layer (about 1.4 nm) result in that the device exhibits excellent PV performance, with an open-circuit voltage of 0.540 V, a short-circuit current density of 30.5 mA/cm 2 , a high fill factor of 74.2%, and a conversion efficiency of 12.2%, under the AM 1.5 illumination. The work function difference between ITO (5.06 eV) and n-Si (4.31 eV) is determined by ultraviolet photoemission spectroscopy and ascribed to the essence of the built-in-field of the PV device

  4. Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

    Science.gov (United States)

    Utagawa, Akira; Asai, Tetsuya; Hirose, Tetsuya; Amemiya, Yoshihito

    We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1], [2]. We regard neural oscillators as independent clock sources on LSIs; i. e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

  5. Ge-rich graded-index Si1-xGex devices for MID-IR integrated photonics

    Science.gov (United States)

    Ramirez, J. M.; Vakarin, V.; Liu, Q.; Frigerio, J.; Ballabio, A.; Le Roux, X.; Benedikovic, D.; Alonso-Ramos, C.; Isella, G.; Vivien, L.; Marris-Morini, D.

    2018-02-01

    Mid-infrared (mid-IR) silicon photonics is becoming a prominent research with remarkable potential in several applications such as in early medical diagnosis, safe communications, imaging, food safety and many more. In the quest for the best material platform to develop new photonic systems, Si and Ge depart with a notable advantage over other materials due to the high processing maturity accomplished during the last part of the 20th century through the deployment of the CMOS technology. From an optical viewpoint, combining Si with Ge to obtain SiGe alloys with controlled stoichiometry is also of interest for the photonic community since permits to increase the effective refractive index and the nonlinear parameter, providing a fascinating playground to exploit nonlinear effects. Furthermore, using Ge-rich SiGe gives access to a range of deep mid-IR wavelengths otherwise inaccessible (λ 2-20 μm). In this paper, we explore for the first time the limits of this approach by measuring the spectral loss characteristic over a broadband wavelength range spanning from λ = 5.5 μm to 8.5 μm. Three different SiGe waveguide platforms are compared, each one showing higher compactness than the preceding through the engineering of the vertical Ge profile, giving rise to different confinement characteristics to the propagating modes. A flat propagation loss characteristic of 2-3 dB/cm over the entire wavelength span is demonstrated in Ge-rich graded-index SiGe waveguides of only 6 μm thick. Also, the role of the overlap fraction of the confined optical mode with the Si-rich area at the bottom side of the epitaxial SiGe waveguide is put in perspective, revealing a lossy characteristic compared to the other designs were the optical mode is located in the Ge-rich area at the top of the waveguide uniquely. These Ge-rich graded-index SiGe waveguides may pave the way towards a new generation of photonic integrated circuits operating at deep mid-IR wavelengths.

  6. SiC-VJFETs power switching devices: an improved model and parameter optimization technique

    Science.gov (United States)

    Ben Salah, T.; Lahbib, Y.; Morel, H.

    2009-12-01

    Silicon carbide junction field effect transistor (SiC-JFETs) is a mature power switch newly applied in several industrial applications. SiC-JFETs are often simulated by Spice model in order to predict their electrical behaviour. Although such a model provides sufficient accuracy for some applications, this paper shows that it presents serious shortcomings in terms of the neglect of the body diode model, among many others in circuit model topology. Simulation correction is then mandatory and a new model should be proposed. Moreover, this paper gives an enhanced model based on experimental dc and ac data. New devices are added to the conventional circuit model giving accurate static and dynamic behaviour, an effect not accounted in the Spice model. The improved model is implemented into VHDL-AMS language and steady-state dynamic and transient responses are simulated for many SiC-VJFETs samples. Very simple and reliable optimization algorithm based on the optimization of a cost function is proposed to extract the JFET model parameters. The obtained parameters are verified by comparing errors between simulations results and experimental data.

  7. Simulation of SEU transients in CMOS ICs

    International Nuclear Information System (INIS)

    Kaul, N.; Bhuva, B.L.; Kerns, S.E.

    1991-01-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE

  8. Ionizing Radiation Effects on the Noise of 65 nm CMOS Transistors for Pixel Sensor Readout at Extreme Total Dose Levels

    CERN Document Server

    Re, V.; Manghisoni, M.; Riceputi, E.; Traversi, G.; Ratti, L.

    2018-01-01

    This paper is focused on the study of the noise performance of 65 nm CMOS transistors at extremely high total ionizing dose (TID) levels of the order of several hundreds of Mrad(SiO2). Noise measurements are reported and discussed, analyzing radiation effects on 1/ f noise and channel thermal noise. In nMOSFETs, up to 10 Mrad(SiO2), the experimental behavior is consistent with a damage mechanism mainly associ- ated with lateral isolation oxides, and can be modeled by parasitic transistors turning on after irradiation and contributing to the total noise of the device. At very high dose, these parasitic transistors tend to be turned off by negative charge accumulating in interface states and compensating radiation-induced positive charge building up inside thick isolation oxides. Effects associated with ionization and hydrogen transport in spacer oxides may become dominant at 600 Mrad(SiO2) and may explain the observed noise behavior at extremely high TID. The results of this analysis provide an understanding o...

  9. CMOS-MEMS prestress vertical cantilever resonator with electrostatic driving and piezoresistive sensing

    Energy Technology Data Exchange (ETDEWEB)

    Chiou, J-C; Shieh, L-J; Lin, Y-J [Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan (China)], E-mail: chiou@mail.nctu.edu.tw, E-mail: ljs.ece93g@nctu.edu.tw, E-mail: yjlin@mail.nctu.edu.tw

    2008-10-21

    This paper presents a CMOS-MEMS prestress vertical comb-drive resonator with a piezoresistive sensor to detect its static and dynamic response. The proposed resonator consists of a set of comb fingers fabricated along with a composite beam. One end of the composite beam is clamped to the anchor, while the other is elevated by residual stress. Actuation occurs when the electrostatic force, induced by the fringe effect, pulls the composite beam downwards to the substrate. The initial tip height at the free end of the resonator due to residual stress is approximately 60 {mu}m. A piezoresistor is designed to sense the vertical deflection and vibration of the resonator. The relative change in the resistance of the piezoresistor ({delta}R/R) is about 0.52% when a voltage of 100 V is applied in static mode. The first resonant frequency of the device is 14.5 kHz, and the quality factor is around 36 in air. The device is fabricated through TSMC 0.35 {mu}m 2p4m CMOS process and post-CMOS process.

  10. CMOS-MEMS prestress vertical cantilever resonator with electrostatic driving and piezoresistive sensing

    International Nuclear Information System (INIS)

    Chiou, J-C; Shieh, L-J; Lin, Y-J

    2008-01-01

    This paper presents a CMOS-MEMS prestress vertical comb-drive resonator with a piezoresistive sensor to detect its static and dynamic response. The proposed resonator consists of a set of comb fingers fabricated along with a composite beam. One end of the composite beam is clamped to the anchor, while the other is elevated by residual stress. Actuation occurs when the electrostatic force, induced by the fringe effect, pulls the composite beam downwards to the substrate. The initial tip height at the free end of the resonator due to residual stress is approximately 60 μm. A piezoresistor is designed to sense the vertical deflection and vibration of the resonator. The relative change in the resistance of the piezoresistor (ΔR/R) is about 0.52% when a voltage of 100 V is applied in static mode. The first resonant frequency of the device is 14.5 kHz, and the quality factor is around 36 in air. The device is fabricated through TSMC 0.35 μm 2p4m CMOS process and post-CMOS process.

  11. Boron diffusion in strained and strain-relaxed SiGe

    International Nuclear Information System (INIS)

    Wang, C.C.; Sheu, Y.M.; Liu, Sally; Duffy, R.; Heringa, A.; Cowern, N.E.B.; Griffin, P.B.

    2005-01-01

    SiGe has been utilized for aggressive CMOS technologies development recently and there are many references [M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, S. Nakamura, Symposium on VLSI Technology Technical Digest, 2002, pp. 94-95; T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, M. Bohr, International Electron Devices Meeting Technical Digest, December 2003, pp. 978-980; P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, M. Bohr, International Electron Devices Meeting Technical Digest, December 2004, pp. 657-660] presenting the advantages brought by it. A better understanding regarding the boron diffusion behavior within and in the vicinity of SiGe is necessary to optimize the extension and the source/drain in pMOSFET. In order to achieve the goal, both effects from mechanical strain and Ge doping on boron diffusion have been investigated. However, only a few publications discuss the impacts of both. Furthermore, most researches investigate these two effects under the conditions of low boron concentration [P. Kuo, J.L. Hoyt, J.F. Gibbons, J.E. Turner, D. Lefforge, Appl. Phys. Lett. 66 (January (5)) (1995) 580-582; N.R. Zangenberg, J. Fage-Pedersen, J. Lundsgaard Hansen, A. Nylandsted Larsen, J. Appl. Phys. 94 (September (6)) (2003) 3883-3890] and high thermal budget anneal [P. Kuo, J.L. Hoyt, J.F. Gibbons, J.E. Turner, D. Lefforge, Appl. Phys. Lett. 66 (January (5)) (1995) 580-582; N.R. Zangenberg, J. Fage-Pedersen, J. Lundsgaard Hansen, A. Nylandsted Larsen, J. Appl

  12. The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

    Science.gov (United States)

    Liang, Hengmao; Liu, Mifeng; Liu, Song; Xu, Dehui; Xiong, Bin

    2018-01-01

    KOH etching and Au/Si eutectic bonding are cost-efficient technologies for 3D device fabrication. Aimed at investigating the process compatibility of KOH etching and Au/Si bonding, KOH etching tests have been carried out for Au/bulk Si and Au/amorphous Si (a-Si) bonding wafers in this paper. For the Au/bulk Si bonding wafer, a serious underetch phenomenon occurring on the damage layer in KOH etching definitely results in packaging failure. In the microstructure analysis, it is found that the formation of the damage layer between the bonded layer and bulk Si is attributed to the destruction of crystal Si lattices in Au/bulk Si eutectic reaction. Considering the occurrence of underetch for Au/Si bonding must meet two requirements: the superfluous Si and the defective layer near the bonded layer, the Au/a-Si bonding by regulating the a-Si/Au thickness ratio is presented in this study. Only when the a-Si/Au thickness ratio is relatively low are there not underetch phenomena, of which the reason is the full reaction of the a-Si layer avoiding the formation of the damage layer for easy underetch. Obviously, the Au/a-Si bonding via choosing a moderate a-Si/Au thickness ratio (⩽1.5:1 is suggested) could be reliably compatible with KOH etching, which provides an available and low-cost approach for 3D device fabrication. More importantly, the theory of the damage layer proposed in this study can be naturally applied to relevant analyses on the eutectic reaction of other metals and single crystal materials.

  13. Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

    Science.gov (United States)

    Cansizoglu, Hilal; Gao, Yang; Ghandiparsi, Soroush; Kaya, Ahmet; Perez, Cesar Bartolo; Mayet, Ahmed; Ponizovskaya Devine, Ekaterina; Cansizoglu, Mehmet F.; Yamada, Toshishige; Elrefaie, Aly F.; Wang, Shih-Yuan; Islam, M. Saif

    2017-08-01

    Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

  14. CMOS Cell Sensors for Point-of-Care Diagnostics

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  15. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...... for integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  16. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  17. Verification of Fowler–Nordheim electron tunneling mechanism in Ni/SiO{sub 2}/n-4H SiC and n{sup +} poly-Si/SiO{sub 2}/n-4H SiC MOS devices by different models

    Energy Technology Data Exchange (ETDEWEB)

    Kodigala, Subba Ramaiah, E-mail: kodigala@gmail.com [Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208 (United States); Department of Physics and Astronomy, Department of Electrical and Computer Engineering, California State University, Northridge, CA 91330 (United States)

    2016-11-01

    This article emphasizes verification of Fowler–Nordheim electron tunneling mechanism in the Ni/SiO{sub 2}/n-4H SiC MOS devices by developing three different kinds of models. The standard semiconductor equations are categorically solved to obtain the change in Fermi energy level of semiconductor with effect of temperature and field that extend support to determine sustainable and accurate tunneling current through the oxide layer. The forward and reverse bias currents with variation of electric field are simulated with help of different models developed by us for MOS devices by applying adequate conditions. The latter is quite different from former in terms of tunneling mechanism in the MOS devices. The variation of barrier height with effect of quantum mechanical, temperature, and fields is considered as effective barrier height for the generation of current–field (J–F) curves under forward and reverse biases but quantum mechanical effect is void in the latter. In addition, the J–F curves are also simulated with variation of carrier concentration in the n-type 4H SiC semiconductor of MOS devices and the relation between them is established.

  18. Recent progress of ultrahigh voltage SiC devices for particle accelerator

    International Nuclear Information System (INIS)

    Fukuda, Kenji; Tsuji, Takashi; Shiomi, Hiromu; Mizushima, Tomonori; Yonezawa, Yoshiyuki; Kondo, Chikara; Otake, Yuji

    2016-01-01

    Silicon carbide (SiC) is the promising material for next power electronics technology used in the field such as HEV, EV, and railway, electric power infrastructure. SiC enables power devices with low loss to easily operate in an ultrahigh-voltage region because of the high breakdown electric field of SiC. In this paper, we report static and dynamic electric performances of 3300 V class SiC SBDs, IE-MOSFETs, >10 kV PiN diodes and IE-IGBTs. Especially, the electrical characteristics of IE-IGBT with the blocking voltage of 16.5 kV indicate the sufficient ability to convert the thyratron in high power RF system of an accelerator. (author)

  19. Strained Si/SiGe MOS transistor model

    Directory of Open Access Journals (Sweden)

    Tatjana Pešić-Brđanin

    2009-06-01

    Full Text Available In this paper we describe a new model of surfacechannel strained-Si/SiGe MOSFET based on the extension of non-quasi-static (NQS circuit model previously derived for bulk-Si devices. Basic equations of the NQS model have been modified to account for the new physical parameters of strained-Si and relaxed-SiGe layers. From the comparisons with measurements, it is shown that a modified NQS MOS including steady-state self heating can accurately predict DC characteristics of Strained Silicon MOSFETs.

  20. SiC epitaxy growth using chloride-based CVD

    International Nuclear Information System (INIS)

    Henry, Anne; Leone, Stefano; Beyer, Franziska C.; Pedersen, Henrik; Kordina, Olof; Andersson, Sven; Janzén, Erik

    2012-01-01

    The growth of thick epitaxial SiC layers needed for high-voltage, high-power devices is investigated with the chloride-based chemical vapor deposition. High growth rates exceeding 100 μm/h can be obtained, however to obtain device quality epilayers adjustments of the process parameters should be carried out appropriately for the chemistry used. Two different chemistry approaches are compared: addition of hydrogen chloride to the standard precursors or using methyltrichlorosilane, a molecule that contains silicon, carbon and chlorine. Optical and electrical techniques are used to characterize the layers.

  1. Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

    Science.gov (United States)

    Asaithambi, Sasikumar; Rajappa, Muthaiah

    2018-05-01

    In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

  2. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  3. Mid-infrared materials and devices on a Si platform for optical sensing

    Science.gov (United States)

    Singh, Vivek; Lin, Pao Tai; Patel, Neil; Lin, Hongtao; Li, Lan; Zou, Yi; Deng, Fei; Ni, Chaoying; Hu, Juejun; Giammarco, James; Soliani, Anna Paola; Zdyrko, Bogdan; Luzinov, Igor; Novak, Spencer; Novak, Jackie; Wachtel, Peter; Danto, Sylvain; Musgraves, J David; Richardson, Kathleen; Kimerling, Lionel C; Agarwal, Anuradha M

    2014-01-01

    In this article, we review our recent work on mid-infrared (mid-IR) photonic materials and devices fabricated on silicon for on-chip sensing applications. Pedestal waveguides based on silicon are demonstrated as broadband mid-IR sensors. Our low-loss mid-IR directional couplers demonstrated in SiNx waveguides are useful in differential sensing applications. Photonic crystal cavities and microdisk resonators based on chalcogenide glasses for high sensitivity are also demonstrated as effective mid-IR sensors. Polymer-based functionalization layers, to enhance the sensitivity and selectivity of our sensor devices, are also presented. We discuss the design of mid-IR chalcogenide waveguides integrated with polycrystalline PbTe detectors on a monolithic silicon platform for optical sensing, wherein the use of a low-index spacer layer enables the evanescent coupling of mid-IR light from the waveguides to the detector. Finally, we show the successful fabrication processing of our first prototype mid-IR waveguide-integrated detectors. PMID:27877641

  4. CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

    Directory of Open Access Journals (Sweden)

    Ekavut Kritchanchai

    2015-08-01

    Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

  5. Power cycling test of a 650 V discrete GaN-on-Si power device with a laminated packaging embedding technology

    DEFF Research Database (Denmark)

    Song, Sungyoung; Munk-Nielsen, Stig; Uhrenfeldt, Christian

    2017-01-01

    A GaN-on-Si power device is a strong candidate to replace power components based on silicon in high-end market for low-voltage applications, thanks to its electrical characteristics. To maximize opportunities of the GaN device in field applications, a package technology plays an important role...... in a discrete GaN power device. A few specialized package technologies having very lower stray inductance and higher thermal conductivity have been proposed for discrete GaN-on-Si power devices. Despite their superior performance, there has been little discussion of their reliability. The paper presents a power...... cycling test of a discrete GaN power device employing a laminated embedded packaging technology subjected to 125 degrees Celsius junction temperature swing. Failure modes are described with collected electrical characteristics and measured temperature data under the test. In conclusion, physical...

  6. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  7. CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

    International Nuclear Information System (INIS)

    Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

    2009-01-01

    CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

  8. Effect of hydrogen on the device performance and stability characteristics of amorphous InGaZnO thin-film transistors with a SiO2/SiNx/SiO2 buffer

    Science.gov (United States)

    Han, Ki-Lim; Ok, Kyung-Chul; Cho, Hyeon-Su; Oh, Saeroonter; Park, Jin-Seong

    2017-08-01

    We investigate the influence of the multi-layered buffer consisting of SiO2/SiNx/SiO2 on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The multi-layered buffer inhibits permeation of water from flexible plastic substrates and prevents degradation of overlying organic layers. The a-IGZO TFTs with a multi-layered buffer suffer less positive bias temperature stress instability compared to the device with a single SiO2 buffer layer after annealing at 250 °C. Hydrogen from the SiNx layer diffuses into the active layer and reduces electron trapping at loosely bound oxygen defects near the SiO2/a-IGZO interface. Quantitative analysis shows that a hydrogen density of 1.85 × 1021 cm-3 is beneficial to reliability. However, the multi-layered buffer device annealed at 350 °C resulted in conductive characteristics due to the excess carrier concentration from the higher hydrogen density of 2.12 × 1021 cm-3.

  9. Tunable Schottky barrier and high responsivity in graphene/Si-nanotip optoelectronic device

    Science.gov (United States)

    Di Bartolomeo, Antonio; Giubileo, Filippo; Luongo, Giuseppe; Iemmo, Laura; Martucciello, Nadia; Niu, Gang; Fraschke, Mirko; Skibitzki, Oliver; Schroeder, Thomas; Lupina, Grzegorz

    2017-03-01

    We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 {{A}} {{{W}}}-1 for white LED light at 3 {{mW}} {{{cm}}}-2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters, and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. We also introduce a new phenomenological graphene/semiconductor diode equation, which well describes the experimental I-V characteristics both in forward and reverse bias.

  10. Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

    Science.gov (United States)

    Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

    2016-12-21

    One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

  11. Device-based local delivery of siRNA against mammalian target of rapamycin (mTOR) in a murine subcutaneous implant model to inhibit fibrous encapsulation.

    Science.gov (United States)

    Takahashi, Hironobu; Wang, Yuwei; Grainger, David W

    2010-11-01

    Fibrous encapsulation of surgically implanted devices is associated with elevated proliferation and activation of fibroblasts in tissues surrounding these implants, frequently causing foreign body complications. Here we test the hypothesis that inhibition of the expression of mammalian target of rapamycin (mTOR) in fibroblasts can mitigate the soft tissue implant foreign body response by suppressing fibrotic responses around implants. In this study, mTOR was knocked down using small interfering RNA (siRNA) conjugated with branched polyethylenimine (bPEI) in fibroblastic lineage cells in serum-based cell culture as shown by both gene and protein analysis. This mTOR knock-down led to an inhibition in fibroblast proliferation by 70% and simultaneous down-regulation in the expression of type I collagen in fibroblasts in vitro. These siRNA/bPEI complexes were released from poly(ethylene glycol) (PEG)-based hydrogel coatings surrounding model polymer implants in a subcutaneous rodent model in vivo. No significant reduction in fibrous capsule thickness and mTOR expression in the foreign body capsules were observed. The siRNA inefficacy in this in vivo implant model was attributed to siRNA dosing limitations in the gel delivery system, and lack of targeting ability of the siRNA complex specifically to fibroblasts. While in vitro data supported mTOR knock-down in fibroblast cultures, in vivo siRNA delivery must be further improved to produce clinically relevant effects on fibrotic encapsulation around implants. Copyright © 2010 Elsevier B.V. All rights reserved.

  12. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  13. Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

    OpenAIRE

    Hassan Jassim Motlak

    2015-01-01

    A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

  14. First steps towards the realization of a double layer perceptron based on organic memristive devices

    Science.gov (United States)

    Emelyanov, A. V.; Lapkin, D. A.; Demin, V. A.; Erokhin, V. V.; Battistoni, S.; Baldi, G.; Dimonte, A.; Korovin, A. N.; Iannotta, S.; Kashkarov, P. K.; Kovalchuk, M. V.

    2016-11-01

    Memristors are widely considered as promising elements for the efficient implementation of synaptic weights in artificial neural networks (ANNs) since they are resistors that keep memory of their previous conductive state. Whereas demonstrations of simple neural networks (e.g., a single-layer perceptron) based on memristors already exist, the implementation of more complicated networks is more challenging and has yet to be reported. In this study, we demonstrate linearly nonseparable combinational logic classification (XOR logic task) using a network implemented with CMOS-based neurons and organic memrisitive devices that constitutes the first step toward the realization of a double layer perceptron. We also show numerically the ability of such network to solve a principally analogue task which cannot be realized by digital devices. The obtained results prove the possibility to create a multilayer ANN based on memristive devices that paves the way for designing a more complex network such as the double layer perceptron.

  15. First steps towards the realization of a double layer perceptron based on organic memristive devices

    Directory of Open Access Journals (Sweden)

    A. V. Emelyanov

    2016-11-01

    Full Text Available Memristors are widely considered as promising elements for the efficient implementation of synaptic weights in artificial neural networks (ANNs since they are resistors that keep memory of their previous conductive state. Whereas demonstrations of simple neural networks (e.g., a single-layer perceptron based on memristors already exist, the implementation of more complicated networks is more challenging and has yet to be reported. In this study, we demonstrate linearly nonseparable combinational logic classification (XOR logic task using a network implemented with CMOS-based neurons and organic memrisitive devices that constitutes the first step toward the realization of a double layer perceptron. We also show numerically the ability of such network to solve a principally analogue task which cannot be realized by digital devices. The obtained results prove the possibility to create a multilayer ANN based on memristive devices that paves the way for designing a more complex network such as the double layer perceptron.

  16. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  17. Design and fabrication of a CMOS-compatible MHP gas sensor

    Directory of Open Access Journals (Sweden)

    Ying Li

    2014-03-01

    Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  18. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Directory of Open Access Journals (Sweden)

    Preethi Padmanabhan

    2018-02-01

    Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  19. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

    Science.gov (United States)

    Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

    2018-02-03

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  20. Ab initio assisted process modeling for Si-based nanoelectronic devices

    International Nuclear Information System (INIS)

    Windl, Wolfgang

    2005-01-01

    In this paper, we discuss concepts and examples of ab initio calculations assisting physics-based process simulation. We focus on how to determine diffusion and reaction constants, where modern methods such as the nudged elastic band method allow a systematic and reliable search for the minimum energy migration path and barrier. We show that once the saddle point is determined, the underlying harmonic transition state theory also allows to calculate the prefactors. The discussed examples include nitrogen diffusion, boron deactivation and boron interface segregation. Finally, some concepts are discussed for future device technologies such as molecular devices, where the currently prevalent multiscale approach (kinetic parameters used in higher level models like diffusion-reaction or kinetic Monte Carlo modeling) would not be sensible anymore. As an example, we described the ab initio temperature-accelerated dynamics modeling of contact formation in carbon nanotube devices

  1. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  2. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  3. A CMOS transconductance-C filter technique for very high frequencies

    NARCIS (Netherlands)

    Nauta, Bram

    1992-01-01

    CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

  4. An All-Solution-Based Hybrid CMOS-Like Quantum Dot/Carbon Nanotube Inverter.

    Science.gov (United States)

    Shulga, Artem G; Derenskyi, Vladimir; Salazar-Rios, Jorge Mario; Dirin, Dmitry N; Fritsch, Martin; Kovalenko, Maksym V; Scherf, Ullrich; Loi, Maria A

    2017-09-01

    The development of low-cost, flexible electronic devices is subordinated to the advancement in solution-based and low-temperature-processable semiconducting materials, such as colloidal quantum dots (QDs) and single-walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high-performance complementary metal-oxide-semiconductor (CMOS)-like inverters is demonstrated. The n-type field effect transistors (FETs) based on I - capped PbS QDs (V th = 0.2 V, on/off = 10 5 , S S-th = 114 mV dec -1 , µ e = 0.22 cm 2 V -1 s -1 ) and the p-type FETs with tailored parameters based on low-density random network of SWCNTs (V th = -0.2 V, on/off > 10 5 , S S-th = 63 mV dec -1 , µ h = 0.04 cm 2 V -1 s -1 ) are integrated on the same substrate in order to obtain high-performance hybrid inverters. The inverters operate in the sub-1 V range (0.9 V) and have high gain (76 V/V), large maximum-equal-criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV). © 2017 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. 25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

    Science.gov (United States)

    Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-10-10

    We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint.

  6. A novel multi-actuation CMOS RF MEMS switch

    Science.gov (United States)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  7. Comparative study of SiC- and Si-based photovoltaic inverters

    Science.gov (United States)

    Ando, Yuji; Oku, Takeo; Yasuda, Masashi; Shirahata, Yasuhiro; Ushijima, Kazufumi; Murozono, Mikio

    2017-01-01

    This article reports comparative study of 150-300 W class photovoltaic inverters (Si inverter, SiC inverter 1, and SiC inverter 2). In these sub-kW class inverters, the ON-resistance was considered to have little influence on the efficiency. The developed SiC inverters, however, have exhibited an approximately 3% higher direct current (DC)-alternating current (AC) conversion efficiency as compared to the Si inverter. Power loss analysis indicated a reduction in the switching and reverse recovery losses of SiC metal-oxide-semiconductor field-effect transistors used for the DC-AC converter is responsible for this improvement. In the SiC inverter 2, an increase of the switching frequency up to 100 kHz achieved a state-of-the-art combination of the weight (1.25 kg) and the volume (1260 cm3) as a 150-250 W class inverter. Even though the increased switching frequency should cause the increase of the switching losses, the SiC inverter 2 exhibited an efficiency comparable to the SiC inverter 1 with a switching frequency of 20 kHz. The power loss analysis also indicated a decreased loss of the DC-DC converter built with SiC Schottky barrier diodes led to the high efficiency for its increased switching frequency. These results clearly indicated feasibility of SiC devices even for sub-kW photovoltaic inverters, which will be available for the applications where compactness and efficiency are of tremendous importance.

  8. Thermal detection mechanism of SiC based hydrogen resistive gas sensors

    Science.gov (United States)

    Fawcett, Timothy J.; Wolan, John T.; Lloyd Spetz, Anita; Reyes, Meralys; Saddow, Stephen E.

    2006-10-01

    Silicon carbide (SiC) resistive hydrogen gas sensors have been fabricated and tested. Planar NiCr contacts were deposited on a thin 3C-SiC epitaxial film grown on thin Si wafers bonded to polycrystalline SiC substrates. At 673K, up to a 51.75±0.04% change in sensor output current and a change in the device temperature of up to 163.1±0.4K were demonstrated in response to 100% H2 in N2. Changes in device temperature are shown to be driven by the transfer of heat from the device to the gas, giving rise to a thermal detection mechanism.

  9. Fabrication of miniaturised Si-based electrocatalytic membranes

    International Nuclear Information System (INIS)

    D'Arrigo, G.; Spinella, C.; Arena, G.; Lorenti, S.

    2003-01-01

    The increasing interest for light and movable electronic systems, cell phones and small digital devices, drives the technological research toward integrated regenerating power sources with small dimensions and great autonomy. Conventional batteries are already unable to deliver power in more and more shrunk volumes maintaining the requirements of long duration and light weight. A possible solution to overcome these limits is the use of miniaturised fuel cell. The fuel cell offers a greater gravimetric energy density compared to conventional batteries. The micromachining technology of silicon is an important tool to reduce the fuel cell structure to micrometer sizes. The use of silicon also gives the opportunity to integrate the power source and the electronic circuits controlling the fuel cell on the same structure. This paper reports preliminary results concerning the micromachining procedure for fabricating a Si-based electrocatalytic membrane for miniaturised Si-based proton exchange membrane fuel cells (PEMFC)

  10. Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

    Science.gov (United States)

    Nassiopoulou, Androula G.

    2018-05-01

    This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included papers on advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.).

  11. Analysis and Comparison of Si and SiC Power Devices on a Grid-Tie Fuel Cell Energy Storage System

    DEFF Research Database (Denmark)

    Pittini, Riccardo; Anthon, Alexander; Zhang, Zhe

    2014-01-01

    In renewable energy applications power conversion efficiency is major concern. This is especially true for grid-tie energy storage systems based on bidirectional dc-dc and dc-ac converters where power flows through these system components. Latest developments in power semiconductors technology......-tie energy storage systems. Results highlight dc-dc conversion efficiencies up to 98.2% with an isolated topology and dc-ac conversion efficiencies up to 97.7%. Overall system efficiency improvements above 1% are achieved compared to traditional Si devices. Results on efficiency improvement are analyzed...

  12. Transformational Electronics: Towards Flexible Low-Cost High Mobility Channel Materials

    KAUST Repository

    Nassar, Joanna M.

    2014-05-01

    For the last four decades, Si CMOS technology has been advancing with Moore’s law prediction, working itself down to the sub-20 nm regime. However, fundamental problems and limitations arise with the down-scaling of transistors and thus new innovations needed to be discovered in order to further improve device performance without compromising power consumption and size. Thus, a lot of studies have focused on the development of new CMOS compatible architectures as well as the discovery of new high mobility channel materials that will allow further miniaturization of CMOS transistors and improvement of device performance. Pushing the limits even further, flexible and foldable electronics seem to be the new attractive topic. By being able to make our devices flexible through a CMOS compatible process, one will be able to integrate hundreds of billions of more transistors in a small volumetric space, allowing to increase the performance and speed of our electronics all together with making things thinner, lighter, smaller and even interactive with the human skin. Thus, in this thesis, we introduce for the first time a cost-effective CMOS compatible approach to make high-k/metal gate devices on flexible Germanium (Ge) and Silicon-Germanium (SiGe) platforms. In the first part, we will look at the various approaches in the literature that has been developed to get flexible platforms, as well as we will give a brief overview about epitaxial growth of Si1-xGex films. We will also examine the electrical properties of the Si1-xGex alloys up to Ge (x=1) and discuss how strain affects the band structure diagram, and thus the mobility of the material. We will also review the material growth properties as well as the state-of-the-art results on high mobility metal-oxide semiconductor capacitors (MOSCAPs) using strained SiGe films. Then, we will introduce the flexible process that we have developed, based on a cost-effective “trench-protect-release-reuse” approach, utilizing

  13. Technology computer aided design for Si, SiGe and GaAs integrated circuits

    CERN Document Server

    Armstrong, GA

    2007-01-01

    The first book to deal with a broad spectrum of process and device design, and modelling issues related to semiconductor devices, bridging the gap between device modelling and process design using TCAD. Examples for types of Si-, SiGe-, GaAs- and InP-based heterostructure MOS and bipolar transistors are compared with experimental data from state-of-the-art devices. With various aspects of silicon heterostructures, this book presents a comprehensive perspective of emerging fields and covers topics ranging from materials to fabrication, devices, modelling and applications. Aimed at research-and-

  14. Energy efficient hybrid computing systems using spin devices

    Science.gov (United States)

    Sharad, Mrigank

    Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

  15. Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

    International Nuclear Information System (INIS)

    Liao, Shu-Hui; Chang, Shu-Tong

    2010-01-01

    This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

  16. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  17. A vertex detector for the International Linear Collider based on CMOS sensors

    Energy Technology Data Exchange (ETDEWEB)

    Besson, Auguste [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: abesson@in2p3.fr; Claus, Gilles [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Colledani, Claude [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Degerli, Yavuz [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Deptuch, Grzegorz [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Deveaux, Michael [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France) and GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Dulinski, Wojciech [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Fourches, Nicolas [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Goffe, Mathieu [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Grandjean, Damien [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Guilloux, Fabrice [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Heini, Sebastien [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]|[GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Himmi, Abdelkader; Hu, Christine; Jaaskelainen, Kimmo [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Li, Yan; Lutz, Pierre; Orsini, Fabienne [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Pellicioli, Michel; Scopelliti, Emanuele; Shabetai, Alexandre; Szelezniak, Michal; Valin, Isabelle [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Winter, Marc [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: marc.winter@ires.in2p3.f

    2006-11-30

    The physics programme at the International Linear Collider (ILC) calls for a vertex detector (VD) providing unprecedented flavour tagging performances, especially for c-quarks and {tau} leptons. This requirement makes a very granular, thin and multi-layer VD installed very close to the interaction region mandatory. Additional constraints, mainly on read-out speed and radiation tolerance, originate from the beam background, which governs the occupancy and the radiation level the detector should be able to cope with. CMOS sensors are being developed to fulfil these requirements. This report addresses the ILC requirements (highly related to beamstrahlung), the main advantages and features of CMOS sensors, the demonstrated performances and the specific aspects of a VD based on this technology. The status of the main R and D directions (radiation tolerance, thinning procedure and read-out speed) are also presented.

  18. Spin injection, transport, and read/write operation in spin-based MOSFET

    International Nuclear Information System (INIS)

    Saito, Yoshiaki; Marukame, Takao; Inokuchi, Tomoaki; Ishikawa, Mizue; Sugiyama, Hideyuki; Tanamoto, Tetsufumi

    2011-01-01

    We proposed a novel spin-based MOSFET 'Spin-Transfer-torque-Switching MOSFET (STS-MOSFET)' that offers non-volatile memory and transistor functions with complementary metal-oxide-semiconductor (CMOS) compatibility, high endurance and fast write time using STS. The STS-MOSFETs with Heusler alloy (Co 2 Fe 1 Al 0.5 Si 0.5 ) were prepared and reconfigurability of a novel spintronics-based MOSFET, STS-MOSFET, was successfully realized for the transport properties owing to reduction of the contact resistance in ferromagnetic metal/thin insulator tunnel barrier/Si junctions. The device showed magnetocurrent (MC) and write characteristics with the endurance of over 10 5 cycles. It was also clarified that the read characteristic can be improved in terms of MC ratio, however, is deteriorated in terms of the mobility by choosing connection configurations of the source and the drain in the STS-MOSFETs.

  19. CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

    Science.gov (United States)

    Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

    2010-12-01

    We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

  20. A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Anelli, Giovanni; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2 ) without any degradation in the performance

  1. A high-speed low-noise transimpedance amplifier in a 0.25 {mu}m CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Anelli, Giovanni E-mail: giovanni.anelli@cern.ch; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-10-11

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k{omega}, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO{sub 2}) without any degradation in the performance.

  2. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  3. Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

    Science.gov (United States)

    Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

    2008-09-01

    In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

  4. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    International Nuclear Information System (INIS)

    Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

    2011-01-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  5. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

    Science.gov (United States)

    Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

    2018-04-05

    Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  6. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

    Directory of Open Access Journals (Sweden)

    Kuei-Chi Tsao

    2018-04-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA. The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  7. A CMOS front-end for SiPM devices aimed to TOF applications with adjustable threshold and high dynamical range

    International Nuclear Information System (INIS)

    Badoni, D.; Gonnella, F.; Messi, R.; Moricciani, D.; Archilli, F.; Iafolla, L.

    2010-01-01

    In recent works we presented the results of the characterization and the study of performance of several Silicon Photomultipliers delivered from MEPHI (Moscow Engineering and Physics Institute) and we proposed an electrical model of the SiPM to be used in analog simulations for the VLSI design of the pilot chip with 0.35μm technology produced. The results of the simulations was also presented. In this work we present the results of several test performed on the SiPM connected to the pilot chip. We also describe the prototype board with a micro-controller designed to adjust the parameters of the chip and to provide an adjustable and temperature controlled power supply to the SiPM. The results of the tests obtained allow us to refine the circuits design for the next chip. This chip has been developed inside the ALTCRISS and KLOE collaboration.

  8. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  9. CMOS-sensors for energy-resolved X-ray imaging

    International Nuclear Information System (INIS)

    Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

  10. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  11. Add/drop filters based on SiC technology for optical interconnects

    International Nuclear Information System (INIS)

    Vieira, M; Vieira, M A; Louro, P; Fantoni, A; Silva, V

    2014-01-01

    In this paper we demonstrate an add/drop filter based on SiC technology. Tailoring of the channel bandwidth and wavelength is experimentally demonstrated. The concept is extended to implement a 1 by 4 wavelength division multiplexer with channel separation in the visible range. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructure. Several monochromatic pulsed lights, separately or in a polychromatic mixture illuminated the device. Independent tuning of each channel is performed by steady state violet bias superimposed either from the front and back sides. Results show that, front background enhances the light-to-dark sensitivity of the long and medium wavelength channels and quench strongly the others. Back violet background has the opposite behaviour. This nonlinearity provides the possibility for selective removal or addition of wavelengths. An optoelectronic model is presented and explains the light filtering properties of the add/drop filter, under different optical bias conditions

  12. Fast determination of the current loss mechanisms in textured crystalline Si-based solar cells

    Science.gov (United States)

    Nakane, Akihiro; Fujimoto, Shohei; Fujiwara, Hiroyuki

    2017-11-01

    A quite general device analysis method that allows the direct evaluation of optical and recombination losses in crystalline silicon (c-Si)-based solar cells has been developed. By applying this technique, the current loss mechanisms of the state-of-the-art solar cells with ˜20% efficiencies have been revealed. In the established method, the optical and electrical losses are characterized from the analysis of an experimental external quantum efficiency (EQE) spectrum with very low computational cost. In particular, we have performed the EQE analyses of textured c-Si solar cells by employing the experimental reflectance spectra obtained directly from the actual devices while using flat optical models without any fitting parameters. We find that the developed method provides almost perfect fitting to EQE spectra reported for various textured c-Si solar cells, including c-Si heterojunction solar cells, a dopant-free c-Si solar cell with a MoOx layer, and an n-type passivated emitter with rear locally diffused solar cell. The modeling of the recombination loss further allows the extraction of the minority carrier diffusion length and surface recombination velocity from the EQE analysis. Based on the EQE analysis results, the current loss mechanisms in different types of c-Si solar cells are discussed.

  13. Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

    CERN Document Server

    Bonacini, Sandro; Kloukinas, Kostas

    2007-01-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

  14. Forming-free performance of a-SiN x :H-based resistive switching memory obtained by oxygen plasma treatment

    Science.gov (United States)

    Zhang, Xinxin; Ma, Zhongyuan; Zhang, Hui; Liu, Jian; Yang, Huafeng; Sun, Yang; Tan, Dinwen; Li, Wei; Xu, Ling; Chen, Kuiji; Feng, Duan

    2018-06-01

    An a-SiN x -based resistive random access memory (RRAM) device with a forming-free characteristic has significant potentials for the industrialization of the next-generation memories. We demonstrate that a forming-free a-SiN x O y RRAM device can be achieved by an oxygen plasma treatment of ultra-thin a-SiN x :H films. Electron spin resonance spectroscopy reveals that Si dangling bonds with a high density (1019 cm‑3) are distributed in the initial state, which exist in the forms of Si2N≡Si·, SiO2≡Si·, O3≡Si·, and N3≡Si·. X-ray photoelectron spectroscopy and temperature-dependent current analyses reveal that the silicon dangling bonds induced by the oxygen plasma treatment and external electric field contribute to the low resistance state (LRS). For the high resistance state (HRS), the rupture of the silicon dangling bond pathway is attributed to the partial passivation of Si dangling bonds by H+ and O2‑. Both LRS and HRS transmissions obey the hopping conduction model. The proposed oxygen plasma treatment, introduced to generate a high density of Si dangling bonds in the SiN x O y :H films, provides a new approach to forming-free RRAM devices.

  15. Enhanced thermal conductivity of nano-SiC dispersed water based ...

    Indian Academy of Sciences (India)

    Silicon carbide (SiC) nanoparticle dispersed water based nanofluids were prepared using up to 0.1 vol% of nanoparticles. Use of suitable stirring routine ensured uniformity and stability of dispersion. Thermal conductivity ratio of nanofluid measured using transient hot wire device shows a significant increase of up to 12% ...

  16. The Leakage Current Improvement of a Ni-Silicided SiGe/Si Junction Using a Si Cap Layer and the PAI Technique

    International Nuclear Information System (INIS)

    Chang Jian-Guang; Wu Chun-Bo; Ji Xiao-Li; Ma Hao-Wen; Yan Feng; Shi Yi; Zhang Rong

    2012-01-01

    We investigate the leakage current of ultra-shallow Ni-silicided SiGe/Si junctions for 45 nm CMOS technology using a Si cap layer and the pre-amorphization implantation (PAI) process. It is found that with the conventional Ni silicide method, the leakage current of a p + (SiGe)—n(Si) junction is large and attributed to band-to-band tunneling and the generation-recombination process. The two leakage contributors can be suppressed quite effectively when a Si cap layer is added in the Ni silicide method. The leakage reduction is about one order of magnitude and could be associated with the suppression of the agglomeration of the Ni germano-silicide film. In addition, the PAI process after the application of a Si cap layer has little effect on improving the junction leakage but reduces the sheet resistance of the silicide film. As a result, the novel Ni silicide method using a Si cap combined with PAI is a promising choice for SiGe junctions in advanced technology. (cross-disciplinary physics and related areas of science and technology)

  17. Simulation of design dependent failure exposure levels for CMOS ICs

    International Nuclear Information System (INIS)

    Kaul, N.; Bhuva, B.L.; Rangavajjhala, V.; van der Molen, H.; Kerns, S.E.

    1990-01-01

    The total dose exposure of CMOS ICs introduces bias-dependent parameter shifts in individual devices. The bias dependency of individual parameter shifts of devices cause different designs to behave differently under identical testing conditions. This paper studies the effect of design and bias on the radiation tolerance of ICs and presents an automated design tool that produces different designs for a logic function, and presents important parameters of each design to circuit designer for trade off analysis

  18. Ultra-broadband Nonlinear Microwave Monolithic Integrated Circuits in SiGe, GaAs and InP

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten

    2006-01-01

    .5 GHz and ≫ 10 GHz for SiGe BiCMOS and GaAs MMIC, respectively. Analysis of the frequency behaviour of frequency converting devices is presented for improved mixer design. Millimeter-wave front-end components for advanced microwave imaging and communications purposes have also been demonstrated......Analog MMIC circuits with ultra-wideband operation are discussed in view of their frequency limitation and different circuit topologies. Results for designed and fabricated frequency converters in SiGe, GaAs, and InP technologies are presented in the paper. RF type circuit topologies exhibit a flat...... conversion gain with a 3 dB bandwidth of 10 GHz for SiGe and in excess of 20 GHz for GaAs processes. The concurrent LO-IF isolation is better than -25 dB, without including the improvement due to the combiner circuit. The converter circuits exhibit similar instantaneous bandwidth at IF and RF ports of ≫ 7...

  19. Three-Dimensional Hetero-Integration of Faceted GaN on Si Pillars for Efficient Light Energy Conversion Devices.

    Science.gov (United States)

    Kim, Dong Rip; Lee, Chi Hwan; Cho, In Sun; Jang, Hanmin; Jeon, Min Soo; Zheng, Xiaolin

    2017-07-25

    An important pathway for cost-effective light energy conversion devices, such as solar cells and light emitting diodes, is to integrate III-V (e.g., GaN) materials on Si substrates. Such integration first necessitates growth of high crystalline III-V materials on Si, which has been the focus of many studies. However, the integration also requires that the final III-V/Si structure has a high light energy conversion efficiency. To accomplish these twin goals, we use single-crystalline microsized Si pillars as a seed layer to first grow faceted Si structures, which are then used for the heteroepitaxial growth of faceted GaN films. These faceted GaN films on Si have high crystallinity, and their threading dislocation density is similar to that of GaN grown on sapphire. In addition, the final faceted GaN/Si structure has great light absorption and extraction characteristics, leading to improved performance for GaN-on-Si light energy conversion devices.

  20. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  1. 3D Silicon Coincidence Avalanche Detector (3D-SiCAD) for charged particle detection

    Science.gov (United States)

    Vignetti, M. M.; Calmon, F.; Pittet, P.; Pares, G.; Cellier, R.; Quiquerez, L.; Chaves de Albuquerque, T.; Bechetoille, E.; Testa, E.; Lopez, J.-P.; Dauvergne, D.; Savoy-Navarro, A.

    2018-02-01

    Single-Photon Avalanche Diodes (SPADs) are p-n junctions operated in Geiger Mode by applying a reverse bias above the breakdown voltage. SPADs have the advantage of featuring single photon sensitivity with timing resolution in the picoseconds range. Nevertheless, their relatively high Dark Count Rate (DCR) is a major issue for charged particle detection, especially when it is much higher than the incoming particle rate. To tackle this issue, we have developed a 3D Silicon Coincidence Avalanche Detector (3D-SiCAD). This novel device implements two vertically aligned SPADs featuring on-chip electronics for the detection of coincident avalanche events occurring on both SPADs. Such a coincidence detection mode allows an efficient discrimination of events related to an incoming charged particle (producing a quasi-simultaneous activation of both SPADs) from dark counts occurring independently on each SPAD. A 3D-SiCAD detector prototype has been fabricated in CMOS technology adopting a 3D flip-chip integration technique, and the main results of its characterization are reported in this work. The particle detection efficiency and noise rejection capability for this novel device have been evaluated by means of a β- strontium-90 radioactive source. Moreover the impact of the main operating parameters (i.e. the hold-off time, the coincidence window duration, the SPAD excess bias voltage) over the particle detection efficiency has been studied. Measurements have been performed with different β- particles rates and show that a 3D-SiCAD device outperforms single SPAD detectors: the former is indeed capable to detect particle rates much lower than the individual DCR observed in a single SPAD-based detectors (i.e. 2 to 3 orders of magnitudes lower).

  2. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  3. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

    Science.gov (United States)

    Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

    2018-01-01

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

  4. Reliability characterization of SiON and MGHK MOSFETs using flicker noise and its correlation with the bias temperature instability

    Science.gov (United States)

    Samnakay, Rameez; Balandin, Alexander A.; Srinivasan, Purushothaman

    2017-09-01

    Bias temperature instability (BTI) is one of the critical device degradation mechanisms in poly-Si/SiON and metal gate/high-k complementary metal-oxide-semiconductor (CMOS) technologies. Using the pre- and post-BTI flicker noise measurements, we investigated the bulk trap density, Nt, in both of these technologies. The low-frequency noise spectra were predominantly of 1/fγ type with γ engineering team at Globalfoundries, Inc. during the summer of 2014. He has currently authored or co-authored 10 journal publications and numerous conference presentations. His current research interests include 1/f noise in high-k dielectrics and fabricated 2D van der Waal thin-film devices Mr. Samnakay's awards and honors include the Dean's Distinguished Fellowship Award (University of California-Riverside) and induction into the IEEE-HKN honors society. He also serves as a reviewer for 6 journals including Applied Physics Letters, Journal of Physics: Condensed Matter and Nanotechnology journals.

  5. Low-cost high-quality crystalline germanium based flexible devices

    KAUST Repository

    Nassar, Joanna M.

    2014-06-16

    High performance flexible electronics promise innovative future technology for various interactive applications for the pursuit of low-cost, light-weight, and multi-functional devices. Thus, here we show a complementary metal oxide semiconductor (CMOS) compatible fabrication of flexible metal-oxide-semiconductor capacitors (MOSCAPs) with high-κ/metal gate stack, using a physical vapor deposition (PVD) cost-effective technique to obtain a high-quality Ge channel. We report outstanding bending radius ~1.25 mm and semi-transparency of 30%.

  6. Low-cost high-quality crystalline germanium based flexible devices

    KAUST Repository

    Nassar, Joanna M.; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2014-01-01

    High performance flexible electronics promise innovative future technology for various interactive applications for the pursuit of low-cost, light-weight, and multi-functional devices. Thus, here we show a complementary metal oxide semiconductor (CMOS) compatible fabrication of flexible metal-oxide-semiconductor capacitors (MOSCAPs) with high-κ/metal gate stack, using a physical vapor deposition (PVD) cost-effective technique to obtain a high-quality Ge channel. We report outstanding bending radius ~1.25 mm and semi-transparency of 30%.

  7. A fully integrated optical detector with a-Si:H based color photodiodes

    Energy Technology Data Exchange (ETDEWEB)

    Watty, Krystian; Merfort, Christian; Seibel, Konstantin; Schoeler, Lars; Boehm, Markus [Institute for Microsystem Technologies (IMT), University of Siegen, Hoelderlinstr. 3, 57076 Siegen (Germany)

    2010-03-15

    The fabrication of an electrophoresis separation microchip with monolithic integrated excitation light source and variospectral photodiodes for absorption detection is presented in this paper. Microchip based separation techniques are essential elements in the development of fully integrated micro-total analysis systems ({mu}-TAS). An integrated microfluidic device, like an application specific lab-on-microchip (ALM) (Seibel et al., in: MRS Spring Meeting, San Francisco, USA, 2005 1), includes all components, necessary to perform a chemical analysis on chip and it can be used as a stand-alone unit directly at the point of sampling. Variospectral diodes based on hydrogenated amorphous silicon (a-Si:H) technology allow for advanced optical detection schemes, because the spectral sensitivity of the devices can be tailored to fit the emission of specific fluorescent markers. Important features of a-Si:H variospectral photodiodes are a high dynamic range, a bias-tunable spectral sensitivity and a very good linearity for the separation of mixed color signals. Principle of ALM device. (Abstract Copyright [2010], Wiley Periodicals, Inc.)

  8. Electrical properties of SiO{sub 2}/SiC interfaces on 2°-off axis 4H-SiC epilayers

    Energy Technology Data Exchange (ETDEWEB)

    Vivona, M., E-mail: marilena.vivona@imm.cnr.it [CNR-IMM, Strada VIII, n. 5 – Zona Industriale, I-95121 Catania (Italy); Fiorenza, P. [CNR-IMM, Strada VIII, n. 5 – Zona Industriale, I-95121 Catania (Italy); Sledziewski, T.; Krieger, M. [Friedrich-Alexander-University (FAU) Erlangen-Nuremberg, Department of Physics, Staudtstrasse 7/Bld. A3, D-91058 Erlangen (Germany); Chassagne, T.; Zielinski, M. [NOVASiC, Savoie Technolac, BP267, F-73375 Le Bourget-du-Lac Cedex (France); Roccaforte, F. [CNR-IMM, Strada VIII, n. 5 – Zona Industriale, I-95121 Catania (Italy)

    2016-02-28

    Graphical abstract: - Highlights: • Processing and electrical characterization of MOS capacitors fabricated on 4H-SiC epilayers grown on 2°-off axis heavily doped substrates. • Excellent characteristics of the SiO{sub 2}/4H-SiC interface in terms of flatness, interface state density and oxide reliability. • Electrical behavior of the MOS devices comparable with that obtained for the state-of-the-art of 4°-off axis 4H-SiC material. • Demonstration of the maturity of the 2°-off axis material for application in 4H-SiC MOSFET device technology. - Abstract: In this paper, the electrical properties of the SiO{sub 2}/SiC interface on silicon carbide (4H-SiC) epilayers grown on 2°-off axis substrates were studied. After epilayer growth, chemical mechanical polishing (CMP) allowed to obtain an atomically flat surface with a roughness of 0.14 nm. Metal-oxide-semiconductor (MOS) capacitors, fabricated on this surface, showed an interface state density of ∼1 × 10{sup 12} eV{sup −1} cm{sup −2} below the conduction band, a value which is comparable to the standard 4°-off-axis material commonly used for 4H-SiC MOS-based device fabrication. Moreover, the Fowler–Nordheim and time-zero-dielectric breakdown analyses confirmed an almost ideal behavior of the interface. The results demonstrate the maturity of the 2°-off axis material for 4H-SiC MOSFET device fabrication.

  9. Post-irradiation effects in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

    1988-01-01

    The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

  10. Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors

    International Nuclear Information System (INIS)

    Manfredi, P.F.; Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.

    2003-01-01

    During the past 15 years, the CMOS technologies have provided the most widely followed approach to signal processing with microstrip detectors. In more recent times, CMOS front-end systems have been developed to acquire and process signals from pixel detectors. During the past few years, the favor toward CMOS processes in their applications in the broad area of detector signal processing has been enhanced by the technological advancement known as device scaling and by two aspects connected to it. One is the shrinking in channel length L into the deep submicron region. The second one is the related reduction in the gate-oxide thickness t ox to a few nm. The reduction in t ox has, as a consequence of primary importance, a decreased 1/f-noise contribution to the equivalent noise charge (ENC). The thinner gate-oxide and the shrinking in gate length, in some regions of operations, concur to increase the transconductance of the device, which results in a smaller ENC contribution from channel thermal noise. The goal of the present paper is to address the question of whether or not the most advanced CMOS processes may meet the requirements set by high resolution, high dynamic range applications like the energy-dispersive photon analysis with solid-state detectors of comparatively large capacitance

  11. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  12. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  13. Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

    Directory of Open Access Journals (Sweden)

    Kuen-Hsien Wu

    2015-09-01

    Full Text Available Porous-silicon (PS multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells.

  14. Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

    International Nuclear Information System (INIS)

    An, M.; Zhang, W.; Xiao, L.; Gao, C.; Chen, C.; Huang, G.; Ji, R.; Liu, J.; Pei, H.; Sun, X.; Wang, K.; Yang, P.; Zhou, W.; Han, M.; Mei, Y.; Li, X.; Sun, Q.

    2017-01-01

    We present the detailed study of the digital readout of Topmetal-II - CMOS pixel direct charge sensor. Topmetal-II - is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

  15. A research on radiation calibration of high dynamic range based on the dual channel CMOS

    Science.gov (United States)

    Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

    2017-10-01

    The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

  16. A SiPM-based scintillator prototype for the upgrade of the Pierre Auger Observatory

    Energy Technology Data Exchange (ETDEWEB)

    Schumacher, Johannes; Bretz, Thomas; Hebbeker, Thomas; Kemp, Julian; Meissner, Rebecca; Middendorf, Lukas; Niggemann, Tim; Peters, Christine [III. Physikalisches Institut A, RWTH Aachen University (Germany); Collaboration: Pierre-Auger-Collaboration

    2016-07-01

    Plastic scintillator-based detectors are simple and yet powerful instruments, commonly used in particle physics experiments. These detectors are also planned to be installed at the Pierre Auger Observatory as part of the upgrade called AugerPrime. Here, a single detector module will consist of several large-sized scintillator bars. Embedded wavelength shifting fibres read out the scintillation light and are coupled to a single photo-sensitive device. We investigate the application of silicon photomultipliers (SiPMs) in this scope, which benefits from high photon detection efficiency and stability. We show the performance of a SiPM-based prototype device installed in the 2 m{sup 2} detector ASCII - an early prototype of the scintillating detector planned for AugerPrime. We focus on the electronics, the optical coupling and the in situ calibration. As ASCII has been operating with SiPMs for several months now, we also highlight first high-energy events seen in coincidence with the Surface Detector of the Pierre Auger Observatory.

  17. High-efficiency terahertz polarization devices based on the dielectric metasurface

    Science.gov (United States)

    Zhou, Jian; Wang, JingJing; Guo, Kai; Shen, Fei; Zhou, Qingfeng; Zhiping yin; Guo, Zhongyi

    2018-02-01

    Metasurfaces are composed of the subwavelength structures, which can be used to manipulate the amplitude, phase, and polarization of incident electromagnetic waves efficiently. Here, we propose a novel type of dielectric metasurface based on crystal Si for realizing to manipulate the terahertz wave, in which by varying the geometric sizes of the Si micro-bricks, the transmitting phase of the terahertz wave can almost span over the entire 2π range for both of the x-polarization and y-polarization simultaneously, while keeping the similarly high-transmission amplitudes (over 90%). At the frequency of 1.0 THz, we have successfully designed a series of controllable THz devices, such as the polarization-dependent beam splitter, polarization-independent beam deflector and the focusing lenses based on the designed metasurfaces. Our designs are easy to fabricate and can be promising in developing high-efficiency THz functional devices.

  18. Simulations of depleted CMOS sensors for high-radiation environments

    CERN Document Server

    Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

    2017-01-01

    After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

  19. Utilization of photoconductive gain in a-Si:H devices for radiation detection

    International Nuclear Information System (INIS)

    Lee, H.K.; Drewery, J.S.; Hong, W.S.; Jing, T.; Kaplan, S.N.; Perez-Mendez, V.

    1995-05-01

    The photoconductive gain mechanism in a-Si:H was investigated in connection with applications to radiation detection. Various device types such as p-i-n, n-i-n and n-i-p-i-n structures were fabricated and tested. Photoconductive gain was measured in two time scales: one for short pulses of visible light ( 2 . Various gain results are discussed in terms of the device structure, applied bias and dark current

  20. Enhanced photocurrent density in graphene/Si based solar cell (GSSC) by optimizing active layer thickness

    International Nuclear Information System (INIS)

    Rosikhin, Ahmad; Hidayat, Aulia Fikri; Syuhada, Ibnu; Winata, Toto

    2015-01-01

    Thickness dependent photocurrent density in active layer of graphene/Si based solar cell has been investigated via analytical – simulation study. This report is a preliminary comparison of experimental and analytical investigation of graphene/Si based solar cell. Graphene sheet was interfaced with Si thin film forming heterojunction solar cell that was treated as a device model for photocurrent generator. Such current can be enhanced by optimizing active layer thickness and involving metal oxide as supporting layer to shift photons absorption. In this case there are two type of devices model with and without TiO 2 in which the silicon thickness varied at 20 – 100 nm. All of them have examined and also compared with each other to obtain an optimum value. From this calculation it found that generated currents almost linear with thickness but there are saturated conditions that no more enhancements will be achieved. Furthermore TiO 2 layer is effectively increases photon absorption but reducing device stability, maximum current is fluctuates enough. This may caused by the disturbance of excitons diffusion and resistivity inside each layer. Finally by controlling active layer thickness, it is quite useful to estimate optimization in order to develop the next solar cell devices