Synthesizing genetic sequential logic circuit with clock pulse generator.
Chuang, Chia-Hua; Lin, Chun-Liang
2014-05-28
Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.
Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.
Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi
2010-01-01
Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.
Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Bergstra, J.A.; Ponse, A.
2010-01-01
Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of
International Nuclear Information System (INIS)
Khitun, Alexander; Bao Mingqiang; Wang, Kang L
2010-01-01
We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.
Energy Technology Data Exchange (ETDEWEB)
Yun, Gil Jung; Yang, Hong Young
2011-03-15
This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.
Gibson, J
2013-01-01
Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate
Sequential logic analysis and synthesis
Cavanagh, Joseph
2007-01-01
Until now, there was no single resource for actual digital system design. Using both basic and advanced concepts, Sequential Logic: Analysis and Synthesis offers a thorough exposition of the analysis and synthesis of both synchronous and asynchronous sequential machines. With 25 years of experience in designing computing equipment, the author stresses the practical design of state machines. He clearly delineates each step of the structured and rigorous design principles that can be applied to practical applications. The book begins by reviewing the analysis of combinatorial logic and Boolean a
Sequential circuit design for radiation hardened multiple voltage integrated circuits
Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.
2009-11-24
The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.
Optically controllable molecular logic circuits
International Nuclear Information System (INIS)
Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun
2015-01-01
Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals
Asynchronous Operators of Sequential Logic Venjunction & Sequention
Vasyukevich, Vadim
2011-01-01
This book is dedicated to new mathematical instruments assigned for logical modeling of the memory of digital devices. The case in point is logic-dynamical operation named venjunction and venjunctive function as well as sequention and sequentional function. Venjunction and sequention operate within the framework of sequential logic. In a form of the corresponding equations, they organically fit analytical expressions of Boolean algebra. Thus, a sort of symbiosis is formed using elements of asynchronous sequential logic on the one hand and combinational logic on the other hand. So, asynchronous
Miniaturization of Josephson logic circuits
International Nuclear Information System (INIS)
Ko, H.; Van Duzer, T.
1985-01-01
The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements
Logic circuits from zero forcing.
Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael
We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.
Design of synthetic biological logic circuits based on evolutionary algorithm.
Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei
2013-08-01
The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.
International Nuclear Information System (INIS)
Carnet, Bernard; Delhumeau, Michel
1971-06-01
The principles of binary analysis applied to the investigation of sequential circuits were used to design a two way coincidence circuit whose input may be, random or periodic variables of constant or variable duration. The output signal strictly reproduces the characteristics of the input signal triggering the coincidence. A coincidence between input signals does not produce any output signal if one of the signals has already triggered the output signal. The characteristics of the output signal in relation to those of the input signal are: minimum time jitter, excellent duration reproducibility and maximum efficiency. Some rules are given for achieving these results. The symmetry, transitivity and non-transitivity characteristics of the edges on the primitive graph are analyzed and lead to some rules for positioning the states on a secondary graph. It is from this graph that the equations of the circuits can be calculated. The development of the circuit and its dynamic testing are discussed. For this testing, the functioning of the circuit is simulated by feeding into the input randomly generated signals
Testing Superconductor Logic Integrated Circuits
Arun, A.J.; Kerkhoff, Hans G.
2005-01-01
Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these
Logic circuits based on molecular spider systems.
Mo, Dandan; Lakin, Matthew R; Stefanovic, Darko
2016-08-01
Spatial locality brings the advantages of computation speed-up and sequence reuse to molecular computing. In particular, molecular walkers that undergo localized reactions are of interest for implementing logic computations at the nanoscale. We use molecular spider walkers to implement logic circuits. We develop an extended multi-spider model with a dynamic environment wherein signal transmission is triggered via localized reactions, and use this model to implement three basic gates (AND, OR, NOT) and a cascading mechanism. We develop an algorithm to automatically generate the layout of the circuit. We use a kinetic Monte Carlo algorithm to simulate circuit computations, and we analyze circuit complexity: our design scales linearly with formula size and has a logarithmic time complexity. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.
Experimental Device for Learning of Logical Circuit Design using Integrated Circuits
石橋, 孝昭
2012-01-01
This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.
Synthesis of logic circuits with evolutionary algorithms
Energy Technology Data Exchange (ETDEWEB)
JONES,JAKE S.; DAVIDSON,GEORGE S.
2000-01-26
In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.
Pass-transistor asynchronous sequential circuits
Whitaker, Sterling R.; Maki, Gary K.
1989-01-01
Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.
An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic
Foster, D. L.
2012-01-01
For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…
Nonlinear dynamics based digital logic and circuits.
Kia, Behnam; Lindner, John F; Ditto, William L
2015-01-01
We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.
Nanoeletromechanical switch and logic circuits formed therefrom
Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM
2010-05-18
A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
Explicit logic circuits discriminate neural states.
Directory of Open Access Journals (Sweden)
Lane Yoder
Full Text Available The magnitude and apparent complexity of the brain's connectivity have left explicit networks largely unexplored. As a result, the relationship between the organization of synaptic connections and how the brain processes information is poorly understood. A recently proposed retinal network that produces neural correlates of color vision is refined and extended here to a family of general logic circuits. For any combination of high and low activity in any set of neurons, one of the logic circuits can receive input from the neurons and activate a single output neuron whenever the input neurons have the given activity state. The strength of the output neuron's response is a measure of the difference between the smallest of the high inputs and the largest of the low inputs. The networks generate correlates of known psychophysical phenomena. These results follow directly from the most cost-effective architectures for specific logic circuits and the minimal cellular capabilities of excitation and inhibition. The networks function dynamically, making their operation consistent with the speed of most brain functions. The networks show that well-known psychophysical phenomena do not require extraordinarily complex brain structures, and that a single network architecture can produce apparently disparate phenomena in different sensory systems.
Sequential Logic Model Deciphers Dynamic Transcriptional Control of Gene Expressions
Yeo, Zhen Xuan; Wong, Sum Thai; Arjunan, Satya Nanda Vel; Piras, Vincent; Tomita, Masaru; Selvarajoo, Kumar; Giuliani, Alessandro; Tsuchiya, Masa
2007-01-01
Background Cellular signaling involves a sequence of events from ligand binding to membrane receptors through transcription factors activation and the induction of mRNA expression. The transcriptional-regulatory system plays a pivotal role in the control of gene expression. A novel computational approach to the study of gene regulation circuits is presented here. Methodology Based on the concept of finite state machine, which provides a discrete view of gene regulation, a novel sequential logic model (SLM) is developed to decipher control mechanisms of dynamic transcriptional regulation of gene expressions. The SLM technique is also used to systematically analyze the dynamic function of transcriptional inputs, the dependency and cooperativity, such as synergy effect, among the binding sites with respect to when, how much and how fast the gene of interest is expressed. Principal Findings SLM is verified by a set of well studied expression data on endo16 of Strongylocentrotus purpuratus (sea urchin) during the embryonic midgut development. A dynamic regulatory mechanism for endo16 expression controlled by three binding sites, UI, R and Otx is identified and demonstrated to be consistent with experimental findings. Furthermore, we show that during transition from specification to differentiation in wild type endo16 expression profile, SLM reveals three binary activities are not sufficient to explain the transcriptional regulation of endo16 expression and additional activities of binding sites are required. Further analyses suggest detailed mechanism of R switch activity where indirect dependency occurs in between UI activity and R switch during specification to differentiation stage. Conclusions/Significance The sequential logic formalism allows for a simplification of regulation network dynamics going from a continuous to a discrete representation of gene activation in time. In effect our SLM is non-parametric and model-independent, yet providing rich biological
Sequential logic model deciphers dynamic transcriptional control of gene expressions.
Directory of Open Access Journals (Sweden)
Zhen Xuan Yeo
Full Text Available BACKGROUND: Cellular signaling involves a sequence of events from ligand binding to membrane receptors through transcription factors activation and the induction of mRNA expression. The transcriptional-regulatory system plays a pivotal role in the control of gene expression. A novel computational approach to the study of gene regulation circuits is presented here. METHODOLOGY: Based on the concept of finite state machine, which provides a discrete view of gene regulation, a novel sequential logic model (SLM is developed to decipher control mechanisms of dynamic transcriptional regulation of gene expressions. The SLM technique is also used to systematically analyze the dynamic function of transcriptional inputs, the dependency and cooperativity, such as synergy effect, among the binding sites with respect to when, how much and how fast the gene of interest is expressed. PRINCIPAL FINDINGS: SLM is verified by a set of well studied expression data on endo16 of Strongylocentrotus purpuratus (sea urchin during the embryonic midgut development. A dynamic regulatory mechanism for endo16 expression controlled by three binding sites, UI, R and Otx is identified and demonstrated to be consistent with experimental findings. Furthermore, we show that during transition from specification to differentiation in wild type endo16 expression profile, SLM reveals three binary activities are not sufficient to explain the transcriptional regulation of endo16 expression and additional activities of binding sites are required. Further analyses suggest detailed mechanism of R switch activity where indirect dependency occurs in between UI activity and R switch during specification to differentiation stage. CONCLUSIONS/SIGNIFICANCE: The sequential logic formalism allows for a simplification of regulation network dynamics going from a continuous to a discrete representation of gene activation in time. In effect our SLM is non-parametric and model-independent, yet
A parity checker circuit based on microelectromechanical resonator logic elements
Energy Technology Data Exchange (ETDEWEB)
Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)
2017-03-03
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.
Complex logic functions implemented with quantum dot bionanophotonic circuits.
Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L
2014-03-26
We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.
On Multiplicative Linear Logic, Modality and Quantum Circuits
Directory of Open Access Journals (Sweden)
Ugo Dal Lago
2012-10-01
Full Text Available A logical system derived from linear logic and called QMLL is introduced and shown able to capture all unitary quantum circuits. Conversely, any proof is shown to compute, through a concrete GoI interpretation, some quantum circuits. The system QMLL, which enjoys cut-elimination, is obtained by endowing multiplicative linear logic with a quantum modality.
Simulation Approach for Timing Analysis of Genetic Logic Circuits
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
2017-01-01
in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior...... of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits...
Relaxation oscillation logic in Josephson junction circuits
International Nuclear Information System (INIS)
Fulton, T.A.
1981-01-01
A dc powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the dc bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed
A parity checker circuit based on microelectromechanical resonator logic elements
Hafiz, Md Abdullah Al
2017-01-11
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
A parity checker circuit based on microelectromechanical resonator logic elements
Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein
2017-01-01
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
A logic circuit for solving linear function by digital method
International Nuclear Information System (INIS)
Ma Yonghe
1986-01-01
A mathematical method for determining the linear relation of physical quantity with rediation intensity is described. A logic circuit has been designed for solving linear function by digital method. Some applications and the circuit function are discussed
Circuit Simulation of All-Spin Logic
Alawein, Meshal
2016-05-01
With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall
MOS Current Mode Logic Near Threshold Circuits
Directory of Open Access Journals (Sweden)
Alexander Shapiro
2014-06-01
Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.
Fluid logic control circuit operates nutator actuator motor
1966-01-01
Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.
Circuit of synchronous logic for the transmission of safety commands
International Nuclear Information System (INIS)
Uberschlag, J.
1969-01-01
The author reports the development of a control-command circuit for the transmission of binary commands related to the safety of nuclear reactors. He presents the main design criteria (operation safety, provided safety level, flexibility, technical adaptation), the definition of the operation principle (inputs, logical outputs), the properties of a logic system. He evokes redundancy issues, and presents the system structure, proposes a possible sketch of the logic circuit. He describes the possible options for intermediate circuits and logic outputs, and tests to be performed
Design, Analysis and Test of Logic Circuits Under Uncertainty
Krishnaswamy, Smita; Hayes, John P
2013-01-01
Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for: • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework; • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...
Analysis and synthesis of a logic control circuit by binary analysis methods
International Nuclear Information System (INIS)
Chicheportiche, Armand
1974-06-01
The analytical study of the logic circuits described in this report clearly shows the fruitful efficiency of the methods proposed by Binary Analysis. This study is a very new approach in logic and these mathematical methods are systematically precise in their applications. The detailed operations of an automatic system are to be studied in a way which cannot be reached by other methods. The definition and utilization of transition equations allow the determination of the different commutations in the auxiliary switch functions of a sequential system. This new way of analysis digital circuits will certainly develop in a very near future [fr
Logic analysis and verification of n-input genetic logic circuits
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
2017-01-01
. In this paper, we present an approach to analyze and verify the Boolean logic of a genetic circuit from the data obtained through stochastic analog circuit simulations. The usefulness of this analysis is demonstrated through different case studies illustrating how our approach can be used to verify the expected......Nature is using genetic logic circuits to regulate the fundamental processes of life. These genetic logic circuits are triggered by a combination of external signals, such as chemicals, proteins, light and temperature, to emit signals to control other gene expressions or metabolic pathways...... accordingly. As compared to electronic circuits, genetic circuits exhibit stochastic behavior and do not always behave as intended. Therefore, there is a growing interest in being able to analyze and verify the logical behavior of a genetic circuit model, prior to its physical implementation in a laboratory...
Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access
Massad, Mohamed El; Garg, Siddharth; Tripunitara, Mahesh
2017-01-01
Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and obser...
Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin
2016-06-22
In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.
Timing Analysis of Genetic Logic Circuits using D-VASim
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...... delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing...... behavior of geneticlogic circuits but also to analyze the timing constraints of cascaded genetic logic circuits....
Logic-type Schmitt circuit using multi-valued gates
Wakui, M.; Tanaka, M.
Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.
A transition calculus for Boolean functions. [logic circuit analysis
Tucker, J. H.; Bennett, A. W.
1974-01-01
A transition calculus is presented for analyzing the effect of input changes on the output of logic circuits. The method is closely related to the Boolean difference, but it is more powerful. Both differentiation and integration are considered.
Magnetic Logic Circuits for Extreme Environments, Phase I
National Aeronautics and Space Administration — The program aims to demonstrate a new genre of all-magnetic logic circuits which are radiation-tolerant and capable of reliable operation in extreme environmental...
Reconfigurable chaotic logic gates based on novel chaotic circuit
International Nuclear Information System (INIS)
Behnia, S.; Pazhotan, Z.; Ezzati, N.; Akhshani, A.
2014-01-01
Highlights: • A novel method for implementing logic gates based on chaotic maps is introduced. • The logic gates can be implemented without any changes in the threshold voltage. • The chaos-based logic gates may serve as basic components of future computing devices. - Abstract: The logical operations are one of the key issues in today’s computer architecture. Nowadays, there is a great interest in developing alternative ways to get the logic operations by chaos computing. In this paper, a novel implementation method of reconfigurable logic gates based on one-parameter families of chaotic maps is introduced. The special behavior of these chaotic maps can be utilized to provide same threshold voltage for all logic gates. However, there is a wide interval for choosing a control parameter for all reconfigurable logic gates. Furthermore, an experimental implementation of this nonlinear system is presented to demonstrate the robustness of computing capability of chaotic circuits
Superconducting push-pull flux quantum logic circuits
International Nuclear Information System (INIS)
Murphy, J.H.; Daniel, M.R.; Przybysz, J.X.
1993-01-01
A superconducting digital logic circuit is described comprising: a first circuit branch including first and second Josephson junctions electrically connected in series with each other; means for applying a positive bias voltage to a first end of said circuit branch; means for applying a negative bias voltage to a second end of said circuit branch; means for applying a first dual polarity input voltage signal to a first node in said circuit branch; and means for extracting a first output voltage signal from said first node in said circuit branch
Digital logic circuit design with ALTERA MAX+PLUS II
International Nuclear Information System (INIS)
Lee, Seung Ho; Park, Yong Su; Lee, Ju Heon
2006-03-01
Contents of this book are the kinds of integrated circuit, design process of integrated circuit, introduction of ALTERA MAX+PLUS II, designing logic circuit with VHDL of ALTERA MAX+PLUS II, grammar and practice of VHDL of ALTERA MAX+PLUS II, design for adder, subtractor, parallel binary subtractor, BCD design, CLA design, code converter design, ALU design, register design, counter design, accumulator design, state machine design, frequency divider design, circuit design with TENMILLION counter, LCD module, circuit design for control the outside RAM in training kit and introduction for HEB-DTK-20K-240/HBE-DTK-IOK.
Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.
Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou
2017-11-20
A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.
Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.
Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon
2016-10-20
Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.
Fast frequency divider circuit using combinational logic
Helinski, Ryan
2017-05-30
The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.
Digital logic circuit design with ALTERA MAX+PLUS II
International Nuclear Information System (INIS)
Lee, Seung Ho; Park, Yong Su; Park, Gun Jong; Lee, Ju Heon
2006-09-01
This book is composed of five parts. The first part has introduction of ALTERA MAX+PLUS II and graphic editor, text editor, compiler, waveform editor simulator and timing analyzer of it. The second part is about direction of digital logic circuit design with training kit. The third part has grammar and practice of VHDL in ALTERA MAX+PLUS II including example and history of VHDL. The fourth part shows the design example of digital logic circuit by VHDL of ALTERA MAX+PLUS II which lists designs of adder and subtractor, code converter, counter, state machine and LCD module. The last part explains design example of digital logic circuit by graphic editor in ALTERA MAX+PLUS II.
Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig
2013-05-01
ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.
A novel ternary logic circuit using Josephson junction
International Nuclear Information System (INIS)
Morisue, M.; Oochi, K.; Nishizawa, M.
1989-01-01
This paper describes a novel Josephson complementary ternary logic circuit named as JCTL. This fundamental circuit is constructed by combination of two SQUIDs, one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. The results of the simulation show that the reliable operations of these circuits can be achieved with a high performance
Practical design of digital circuits basic logic to microprocessors
Kampel, Ian
1983-01-01
Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio
Logic designer's handbook circuits and systems
Parr, E A
2013-01-01
Easy-to-read, but nonetheless thorough, this book on digital circuits is for use by students and engineers, and is a readily accessible source of data on devices in the TTL and CMOS families. The book is written to be used as a Designer's Handbook and will spend its days on the designer's bench rather than their bookshelf. The basic theory is explained and then supported with specific practical examples.* Revised, enlarged, reduced price edition * Easy-to-read, jargon free book suitable for professionals and students * Plenty of basic theory and practical information * Based on authors practi
Prospects of luminescence based molecular scale logic gates and logic circuits
Energy Technology Data Exchange (ETDEWEB)
Speiser, Shammai, E-mail: speiser@technion.ac.il
2016-01-15
In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder.
Prospects of luminescence based molecular scale logic gates and logic circuits
International Nuclear Information System (INIS)
Speiser, Shammai
2016-01-01
In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder
Magnonic interferometric switch for multi-valued logic circuits
Balynsky, Michael; Kozhevnikov, Alexander; Khivintsev, Yuri; Bhowmick, Tonmoy; Gutierrez, David; Chiang, Howard; Dudko, Galina; Filimonov, Yuri; Liu, Guanxiong; Jiang, Chenglong; Balandin, Alexander A.; Lake, Roger; Khitun, Alexander
2017-01-01
We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-scale logic gates, and minimize energy per operation, which is limited only by the noise margin. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. We describe possible implementation of the three-value logic circuits based on the magnonic interferometric switches. The advantages and shortcomings inherent in interferometric switches are also discussed.
Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al
2018-03-01
One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.
G(sup 4)FET Implementations of Some Logic Circuits
Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan
2009-01-01
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration
On the origin of reproducible sequential activity in neural circuits
Afraimovich, V. S.; Zhigulin, V. P.; Rabinovich, M. I.
2004-12-01
Robustness and reproducibility of sequential spatio-temporal responses is an essential feature of many neural circuits in sensory and motor systems of animals. The most common mathematical images of dynamical regimes in neural systems are fixed points, limit cycles, chaotic attractors, and continuous attractors (attractive manifolds of neutrally stable fixed points). These are not suitable for the description of reproducible transient sequential neural dynamics. In this paper we present the concept of a stable heteroclinic sequence (SHS), which is not an attractor. SHS opens the way for understanding and modeling of transient sequential activity in neural circuits. We show that this new mathematical object can be used to describe robust and reproducible sequential neural dynamics. Using the framework of a generalized high-dimensional Lotka-Volterra model, that describes the dynamics of firing rates in an inhibitory network, we present analytical results on the existence of the SHS in the phase space of the network. With the help of numerical simulations we confirm its robustness in presence of noise in spite of the transient nature of the corresponding trajectories. Finally, by referring to several recent neurobiological experiments, we discuss possible applications of this new concept to several problems in neuroscience.
Integrated digital superconducting logic circuits for the quantum synthesizer. Report
International Nuclear Information System (INIS)
Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.
2006-11-01
This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-Al x O y /Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ
Digital logic circuit design with ALTERA Quartus II
International Nuclear Information System (INIS)
Lee, Seung Ho
2009-09-01
This book consists 31 chapters about digital logic circuit with ALTERA Quartus II. It includes the introduction of ALTERA Quartus II, ALTERA Quartus II schematic editor, ALTERA Quartus II compiler, ALTERA Quartus II simulator, ALTERA Quartus II timing analyzer, how to use HBE-COMBO II training and HBE-COMBO II training kit with schematic editor, VHDL grammar and practice of ALTERA Quartus II and HBE-COMBO II training kit with VHDL.
Synthesis of Ternary Quantum Logic Circuits by Decomposition
Khan, Faisal Shah; Perkowski, Marek
2005-01-01
Recent research in multi-valued logic for quantum computing has shown practical advantages for scaling up a quantum computer. Multivalued quantum systems have also been used in the framework of quantum cryptography, and the concept of a qudit cluster state has been proposed by generalizing the qubit cluster state. An evolutionary algorithm based synthesizer for ternary quantum circuits has recently been presented, as well as a synthesis method based on matrix factorization.In this paper, a re...
International Nuclear Information System (INIS)
Mistri, Tarun; Bhowmick, Rahul; Katarkar, Atul; Chaudhuri, Keya; Ali, Mahammad
2017-01-01
Methodological synthesis of a new biocompatible bi-compartmental rhodamine based probe (L 3 ) provides a multi-inputs and multi-outputs molecular logic circuit based on simple chemosensing phenomena. Spectroscopic responses of Cu 2+ and Hg 2+ towards L 3 together with reversible binding of S 2- with L 3 -Cu 2+ and L 3 -Hg 2+ complexes help us to construct a thee-input molecular circuit on their control and sequential addition to a solution of L 3 in a mixed organo-aqueous medium. We have further successfully encoded binary digits out of these inputs and outputs which may convert a three-digit input string into a two-digit output string resulting a simple monomolecular logic circuit. Such a molecular ‘Boolean’ logic operation may improve the complexity of logic gate circuitry and computational speed and may be useful to employ in potential biocompatible molecular logic platforms. - Graphical abstract: A new bi-compartmental molecular system equipped with Rhodamine fluorophore unit provides a Multi-inputs and Multi-outputs Molecular Logic Circuit based on a very simple observation of chemosensing activities.
Energy Technology Data Exchange (ETDEWEB)
Mistri, Tarun; Bhowmick, Rahul [Department of Chemistry, Jadavpur University, 188 Raja S.C. Mullick Road, Kolkata 700032 (India); Katarkar, Atul; Chaudhuri, Keya [Molecular & Human Genetics Division, CSIR-Indian Institute of Chemical Biology, 4 Raja S.C. Mullick Road, Kolkata 700032 (India); Ali, Mahammad, E-mail: mali@chemistry.jdvu.ac.in [Department of Chemistry, Jadavpur University, 188 Raja S.C. Mullick Road, Kolkata 700032 (India)
2017-05-15
Methodological synthesis of a new biocompatible bi-compartmental rhodamine based probe (L{sup 3}) provides a multi-inputs and multi-outputs molecular logic circuit based on simple chemosensing phenomena. Spectroscopic responses of Cu{sup 2+} and Hg{sup 2+} towards L{sup 3} together with reversible binding of S{sup 2-} with L{sup 3}-Cu{sup 2+} and L{sup 3}-Hg{sup 2+} complexes help us to construct a thee-input molecular circuit on their control and sequential addition to a solution of L{sup 3} in a mixed organo-aqueous medium. We have further successfully encoded binary digits out of these inputs and outputs which may convert a three-digit input string into a two-digit output string resulting a simple monomolecular logic circuit. Such a molecular ‘Boolean’ logic operation may improve the complexity of logic gate circuitry and computational speed and may be useful to employ in potential biocompatible molecular logic platforms. - Graphical abstract: A new bi-compartmental molecular system equipped with Rhodamine fluorophore unit provides a Multi-inputs and Multi-outputs Molecular Logic Circuit based on a very simple observation of chemosensing activities.
Reversible logic gates on Physarum Polycephalum
International Nuclear Information System (INIS)
Schumann, Andrew
2015-01-01
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum
Design automation for integrated nonlinear logic circuits (Conference Presentation)
Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.
2016-05-01
A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite
International Nuclear Information System (INIS)
Lefebvre, Claude; Therond, J.P.
1974-01-01
The present invention relates to a self-powered 'AND' logic circuit of dynamic type with positive safety, which delivers on duty operation an output signal equal to the logic product of the input logic signals. The invention relates also to the use of said 'AND' logic circuits in developing n/m logics also of dynamic types with positive safety, delivering on duty operation a zero valued signal when, at least n of the m input signals have the value zero. This type of logics can be inserted in nuclear reactor protection systems; when the value of the reactor operating physical characteristics go out of the safety margins, or true trouble affects 'AND' circuits the value of the output signal is zero, that triggers off the safety absorber drap, for instance [fr
Geometrical considerations in the transient ionization testing of digital logic circuits
International Nuclear Information System (INIS)
Johnston, A.
1982-01-01
Mechanisms are identified that can cause the transient response of digital logic circuits to depend on the logic state in which they are irradiated. Several of these mechanisms depend on surface topology, and for these cases the sensitive logic states can be determined by examining the topology. General approaches for transient radiation testing are also discussed for several MSI and LSI device technologies
Designable DNA-binding domains enable construction of logic circuits in mammalian cells.
Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman
2014-03-01
Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.
International Nuclear Information System (INIS)
Inoue, Kenta; Narama, Tatsuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki; Takeuchi, Naoki
2015-01-01
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells. (paper)
Explicit logic circuits predict local properties of the neocortex's physiology and anatomy.
Directory of Open Access Journals (Sweden)
Lane Yoder
Full Text Available BACKGROUND: Two previous articles proposed an explicit model of how the brain processes information by its organization of synaptic connections. The family of logic circuits was shown to generate neural correlates of complex psychophysical phenomena in different sensory systems. METHODOLOGY/PRINCIPAL FINDINGS: Here it is shown that the most cost-effective architectures for these networks produce correlates of electrophysiological brain phenomena and predict major aspects of the anatomical structure and physiological organization of the neocortex. The logic circuits are markedly efficient in several respects and provide the foundation for all of the brain's combinational processing of information. CONCLUSIONS/SIGNIFICANCE: At the local level, these networks account for much of the physical structure of the neocortex as well its organization of synaptic connections. Electronic implementations of the logic circuits may be more efficient than current electronic logic arrays in generating both Boolean and fuzzy logic.
Methods and Tools for the Analysis, Verification and Synthesis of Genetic Logic Circuits,
DEFF Research Database (Denmark)
Baig, Hasan
2017-01-01
. This usually requires simulating the mathematical models of these genetic circuits and perceive whether or not the circuit behaves appropriately. Furthermore, synthetic biology utilizes the concepts from electronic design automation (EDA) of abstraction and automated construction to generate genetic circuits...... that the proposed approach is eﬀective to determine the variation in the behavior of genetic circuits when the circuit’s parameters are changed. In addition, the thesis also attempts to propose a synthesis and technology mapping tool, called GeneTech, for genetic circuits. It allows users to construct a genetic...... important design characteristics. This thesis also introduces an automated approach to analyze the behavior of genetic logic circuits from the simulation data. With this capability, the boolean logic of complex genetic circuits can be analyzed and/or veriﬁed automatically. It is also shown in this thesis...
Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage
2017-03-01
camouflage; obfuscation; SAT; key extraction; reverse engineering ; security; trusted electronics Introduction Integrated Circuit (IC) designs are... Circuit camouflage is hardware obfuscation technology that prevents reverse engineering of a fabricated device by utilizing a relatively small...obfuscated with circuit camouflage technology, this type of attack becomes much more difficult because a reverse engineer cannot extract a gate- level
Synthesis of multivalued quantum logic circuits by elementary gates
Di, Yao-Min; Wei, Hai-Rui
2013-01-01
We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.
Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits
International Nuclear Information System (INIS)
Lashin, A. V.; Kozyrev, A. V.
2015-01-01
One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits
Study of the computer aided design of combinatory logical circuits
International Nuclear Information System (INIS)
Sisso, Robert
1969-01-01
This survey aims at obtaining, automatically, low costs circuits in NOR and NAND technology for completely and incompletely specified functions. Two methods are proposed; the first one (chain fusion and element combination method) aims at obtaining directly the circuits by applying synthesis algorithms, the automation of which is provided by a new notation which binds bi-univocally circuit and function. The second one (decomposition method) uses the principle of the simple disjoined decomposition and enables to determine within this scope the upper boundary evolution of the circuit minimum cost. (author) [fr
Integrated circuits and logic operations based on single-layer MoS2.
Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras
2011-12-27
Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.
Time-space modal logic for verification of bit-slice circuits
Hiraishi, Hiromi
1996-03-01
The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.
Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.
Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai
2017-08-02
Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.
Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool
2017-12-01
Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-27
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.
2016-01-01
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Hafiz, M. A. A.
2016-08-18
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Experimental investigation of a four-qubit linear-optical quantum logic circuit.
Stárek, R; Mičuda, M; Miková, M; Straka, I; Dušek, M; Ježek, M; Fiurášek, J
2016-09-20
We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and several two-qubit and single-qubit gates. The C(3)Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.
International Nuclear Information System (INIS)
Scott, W.A.; Turner, R.M.; McCammon, R.B.
1981-01-01
Integrated logic circuits were described as a means of formally representing genetic-geologic models for estimating undiscovered uranium resources. The logic circuits are logical combinations of selected geologic characteristics judged to be associated with particular types of uranium deposits. Each combination takes on a value which corresponds to the combined presence, absence, or don't know states of the selected characteristic within a specified geographic cell. Within each cell, the output of the logic circuit is taken as a measure of the favorability of occurrence of an undiscovered deposit of the type being considered. In this way, geological, geochemical, and geophysical data are incorporated explicitly into potential uranium resource estimates. The present report describes how integrated logic circuits are constructed by use of a computer graphics program. A user's guide is also included
CMOS-based carbon nanotube pass-transistor logic integrated circuits
Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao
2012-01-01
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080
Logic circuits based on individual semiconducting and metallic carbon-nanotube devices
International Nuclear Information System (INIS)
Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G
2010-01-01
Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.
A hybrid nanomemristor/transistor logic circuit capable of self-programming.
Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley
2009-02-10
Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.
Single-flux-quantum logic circuits exploiting collision-based fusion gates
International Nuclear Information System (INIS)
Asai, T.; Yamada, K.; Amemiya, Y.
2008-01-01
We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock
Designing reversible arithmetic, logic circuit to implement micro-operation in quantum computation
International Nuclear Information System (INIS)
Kalita, Gunajit; Saikia, Navajit
2016-01-01
The futuristic computing is desired to be more power full with low-power consumption. That is why quantum computing has been a key area of research for quite some time and is getting more and more attention. Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times. Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance. In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer. The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations. The quantum costs of these designs are comparable. Many of the implemented micro-operations are not seen in previous literatures. The performances of the proposed circuits are compared with existing designs wherever available. (paper)
Boolean Reasoning and Informed Search in the Minimization of Logic Circuits
1992-03-01
between a symbolic representation of a PLA using Os and is and the physical layout of the function. 2. Computer-aided design (CAD) tools have made it easy...Svoboda, Antonin and Donnamaie White. Advanced Logical Circuit Design Tech- niques. New York: Garland STPM Press, 1979. [Tison 67] Tison, Pierre
Multi-purpose logical device with integrated circuit for the automation of mine water disposal
Energy Technology Data Exchange (ETDEWEB)
Pop, E.; Pasculescu, M.
1980-06-01
After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)
Radiation Hardened NULL Convention Logic Asynchronous Circuit Design
Directory of Open Access Journals (Sweden)
Liang Zhou
2015-10-01
Full Text Available This paper proposes a radiation hardened NULL Convention Logic (NCL architecture that can recover from a single event latchup (SEL or single event upset (SEU fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.
International Nuclear Information System (INIS)
Yamanashi, Yuki; Masubuchi, Kota; Yoshikawa, Nobuyuki
2016-01-01
The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.
Energy Technology Data Exchange (ETDEWEB)
Yamanashi, Yuki, E-mail: yamanasi@ynu.ac.jp [Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501 (Japan); Masubuchi, Kota; Yoshikawa, Nobuyuki [Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501 (Japan)
2016-11-15
The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.
Graphene-based non-Boolean logic circuits
Liu, Guanxiong; Ahsan, Sonia; Khitun, Alexander G.; Lake, Roger K.; Balandin, Alexander A.
2013-10-01
Graphene revealed a number of unique properties beneficial for electronics. However, graphene does not have an energy band-gap, which presents a serious hurdle for its applications in digital logic gates. The efforts to induce a band-gap in graphene via quantum confinement or surface functionalization have not resulted in a breakthrough. Here we show that the negative differential resistance experimentally observed in graphene field-effect transistors of "conventional" design allows for construction of viable non-Boolean computational architectures with the gapless graphene. The negative differential resistance—observed under certain biasing schemes—is an intrinsic property of graphene, resulting from its symmetric band structure. Our atomistic modeling shows that the negative differential resistance appears not only in the drift-diffusion regime but also in the ballistic regime at the nanometer-scale—although the physics changes. The obtained results present a conceptual change in graphene research and indicate an alternative route for graphene's applications in information processing.
Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios
Directory of Open Access Journals (Sweden)
Garcia-Leyva Lancelot
2016-01-01
In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other robust technique approaches. The methodology is totally different from the Von Neumann approaches, because element are not replicated N times, but instead, they check the coherence of redundant input data no allowing data propagation in case of discrepancy. This mechanism does not require voting devices.
Abdullah-Al-Shafi, Md; Bahar, Ali Newaz; Bhuiyan, Mohammad Maksudur Rahman; Shamim, S M; Ahmed, Kawser
2018-08-01
Quantum-dot cellular automata (QCA) as nanotechnology is a pledging contestant that has incredible prospective to substitute complementary metal-oxide-semiconductor (CMOS) because of its superior structures such as intensely high device thickness, minimal power depletion with rapid operation momentum. In this study, the dataset of average output polarization (AOP) for fundamental reversible logic circuits is organized as presented in (Abdullah-Al-Shafi and Bahar, 2017; Bahar et al., 2016; Abdullah-Al-Shafi et al., 2015; Abdullah-Al-Shafi, 2016) [1-4]. QCADesigner version 2.0.3 has been utilized to survey the AOP of reversible circuits at separate temperature point in Kelvin (K) unit.
Shin, SeungJun; Yu, YunSeop; Choi, JungBum
2008-10-01
New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.
Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits
International Nuclear Information System (INIS)
Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.
2005-01-01
We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps
Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits
Directory of Open Access Journals (Sweden)
Kwang-Jow Gan
2016-06-01
Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.
Calculation of the soft error rate of submicron CMOS logic circuits
International Nuclear Information System (INIS)
Juhnke, T.; Klar, H.
1995-01-01
A method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described. This method takes into account charge collection by drift and diffusion. The method is verified by comparison of calculated SER's to measurement results. Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 microm, 0.3 microm, and 0.12 microm technology, respectively. It has been found that the SER of such highly pipelined submicron CMOS circuits may become too high so that countermeasures have to be taken. Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs
Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc
2016-01-01
Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit’s complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588
Single OR molecule and OR atomic circuit logic gates interconnected on a Si(100)H surface
International Nuclear Information System (INIS)
Ample, F; Joachim, C; Duchemin, I; Hliwa, M
2011-01-01
Electron transport calculations were carried out for three terminal OR logic gates constructed either with a single molecule or with a surface dangling bond circuit interconnected on a Si(100)H surface. The corresponding multi-electrode multi-channel scattering matrix (where the central three terminal junction OR gate is the scattering center) was calculated, taking into account the electronic structure of the supporting Si(100)H surface, the metallic interconnection nano-pads, the surface atomic wires and the molecule. Well interconnected, an optimized OR molecule can only run at a maximum of 10 nA output current intensity for a 0.5 V bias voltage. For the same voltage and with no molecule in the circuit, the output current of an OR surface atomic scale circuit can reach 4 μA.
Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates
Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda
2012-01-01
One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039
Energy Technology Data Exchange (ETDEWEB)
Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu
2008-05-07
Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.
Li, Shu; Zhang, Tong
2008-05-07
Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.
International Nuclear Information System (INIS)
Li Shu; Zhang Tong
2008-01-01
Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
Energy Technology Data Exchange (ETDEWEB)
Mitra, Kalyan Yoti, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Martínez-Domingo, Carme [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra, Spain and Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Ramon, Eloi, E-mail: eloi.ramon@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Carrabina, Jordi, E-mail: jordi.carrabina@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Gomes, Henrique Leonel, E-mail: hgomes@ualg.pt [Universidade do Algarve, Institute of Telecommunications, Faro (Portugal); Baumann, Reinhard R., E-mail: reinhard.baumann@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Fraunhofer Institute for Electronic Nano Systems (ENAS), Department of Printed Functionalities, Chemnitz (Germany)
2015-02-17
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
International Nuclear Information System (INIS)
Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.
2015-01-01
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit
Yuan, Shoucai; Liu, Yamei
2016-08-01
This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.
A molecular-sized optical logic circuit for digital modulation of a fluorescence signal
Nishimura, Takahiro; Tsuchida, Karin; Ogura, Yusuke; Tanida, Jun
2018-03-01
Fluorescence measurement allows simultaneous detection of multiple molecular species by using spectrally distinct fluorescence probes. However, due to the broad spectra of fluorescence emission, the multiplicity of fluorescence measurement is generally limited. To overcome this limitation, we propose a method to digitally modulate fluorescence output signals with a molecular-sized optical logic circuit by using optical control of fluorescence resonance energy transfer (FRET). The circuit receives a set of optical inputs represented with different light wavelengths, and then it switches high and low fluorescence intensity from a reporting molecule according to the result of the logic operation. By using combinational optical inputs in readout of fluorescence signals, the number of biomolecular species that can be identified is increased. To implement the FRET-based circuits, we designed two types of basic elements, YES and NOT switches. An YES switch produces a high-level output intensity when receiving a designated light wavelength input and a low-level intensity without the light irradiation. A NOT switch operates inversely to the YES switch. In experiments, we investigated the operation of the YES and NOT switches that receive a 532-nm light input and modulate the fluorescence intensity of Alexa Fluor 488. The experimental result demonstrates that the switches can modulate fluorescence signals according to the optical input.
DEFF Research Database (Denmark)
Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid
As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...
K-maps: a vehicle to an optimal solution in combinational logic ...
African Journals Online (AJOL)
K-maps: a vehicle to an optimal solution in combinational logic design problems using digital multiplexers. ... Abstract. Application of Karnaugh maps (K-Maps) for the design of combinational logic circuits and sequential logic circuits is a subject that has been widely discussed. However, the use of K-Maps in the design of ...
High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.
Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried
2017-09-01
As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.
High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes
Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried
2017-09-01
As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.
Materials Integration and Doping of Carbon Nanotube-based Logic Circuits
Geier, Michael
Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and
Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)
Karmakar, Supriya
2014-10-01
This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.
Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber
Routh, D. E.; Sharma, G. C. (Inventor)
1984-01-01
An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.
Wide operating window spin-torque majority gate towards large-scale integration of logic circuits
Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.
2018-05-01
Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-01-01
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-04-13
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.
Bhowmik, Panchatapa; Roy, Jitendra Nath; Chattopadhyay, Tanay
2014-11-01
This paper presents a generalized all optical circuit of two-input logical operation (both binary and multi-valued), using an optical nonlinear material (OPNLM) based switch. The inputs of the logic gates are represented by different polarization states of light. This model is simple, practical and very much useful for future all optical information processing. Proposed scheme can work for different wavelengths and for different materials. The simulation result with the nonlinear material gold nanoparticle embedded in optically transparent matrices alumina (Al2O3) is also presented in the paper.
Mansouri, S.; Coskun, B.; El Mir, L.; Al-Sehemi, Abdullah G.; Al-Ghamdi, Ahmed; Yakuphanoglu, F.
2018-04-01
Graphene is a sheet-structured material that lacks a forbidden band, being a good candidate for use in radiofrequency applications. We have elaborated graphene-oxide-doped poly(3-hexylthiophene) nanocomposite to increase the interlayer distance and thereby open a large bandgap for use in the field of logic circuits. Graphene oxide/poly(3-hexylthiophene) (GO/P3HT) nanocomposite thin-film transistors (TFTs) were fabricated on silicon oxide substrate by spin coating method. The current-voltage ( I- V) characteristics of TFTs with various P3HT compositions were studied in the dark and under light illumination. The photocurrent, charge carrier mobility, subthreshold voltage, density of interface states, density of occupied states, and I ON/ I OFF ratio of the devices strongly depended on the P3HT weight ratio in the composite. The effects of white-light illumination on the electrical parameters of the transistors were investigated. The results indicated that GO/P3HT nanocomposite thin-film transistors have high potential for use in radiofrequency applications, and their feasibility for use in digital applications has been demonstrated.
Digital Circuit Analysis Using an 8080 Processor.
Greco, John; Stern, Kenneth
1983-01-01
Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)
Energy Technology Data Exchange (ETDEWEB)
Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.
1984-01-01
Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.
International Nuclear Information System (INIS)
Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu
2001-01-01
A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events
Circuits design of action logics of the protection system of nuclear reactor IAN-R1 of Colombia
International Nuclear Information System (INIS)
Gonzalez M, J. L.; Rivero G, T.; Sainz M, E.
2014-10-01
Due to the obsolescence of the instrumentation and control system of the nuclear research reactor IAN-R1, the Institute of Geology and Mining of Colombia, IngeoMinas, launched an international convoking for renewal it which was won by the Instituto Nacional de Investigaciones Nucleares (ININ). Within systems to design, the reactor protection system is described as important for safety, because this carried out, among others two primary functions: 1) ensuring the reactor shutdown safely, and 2) controlling the interlocks to protect against operational errors if defined conditions have not been met. To fulfill these functions, the various subsystems related to the safety report the state in which they are using binary signals and are connected to the inputs of two redundant logic wiring circuits called action logics (Al) that are part of the reactor protection system. These Al also serve as logical interface to indicate at all times the status of subsystems, both the operator and other systems. In the event that any of the subsystems indicates a state of insecurity in the reactor, the Al generate signals off (or scram) of the reactor, maintaining the interlock until the operator sends a reset signal. In this paper the design, implementation, verification and testing of circuits that make up the Al 1 and 2 of IAN-R1 reactor is described, considering the fulfillment of the requirements that the different international standards imposed on this type of design. (Author)
Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.
Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl
2010-09-13
Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-05-09
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.
Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu
2017-01-01
Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits
Directory of Open Access Journals (Sweden)
Apangshu Das
2016-01-01
Full Text Available The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP based logic minimization.
On Using Current Steering Logic in Mixed Analogue-digital Circuits
DEFF Research Database (Denmark)
Lehmann, Torsten
1998-01-01
The authors investigate power supply noise in mixed analogue-digital circuits, arising from communication between the analogue and digital parts of the circuit. Current steering techniques and proper buffering are used to show which noise currents can be reduced and which cannot. In addition......, a high-swing current steering buffer for driving analogue switches or external digital signals is proposed....
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-05-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.
International Nuclear Information System (INIS)
Bandyopadhyay, Supriyo; Cahay, Marc
2009-01-01
In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information processing device invariably causes current flow and an associated dissipation. Replacing 'charge' with the 'spin' of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient 'green electronics'. This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation. (topical review)
From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits
International Nuclear Information System (INIS)
Register, L.F.; Basu, D.; Reddy, D.
2011-01-01
Colleagues and we recently proposed a new type of transistor, a Bilayer Pseudo Spin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineer able device parameters on the formation and gating of interlayer coherent state.
From Boolean logic to switching circuits and automata. Towards modern information technology
Energy Technology Data Exchange (ETDEWEB)
Stankovic, Radomir S. [Nis Univ. (RS). Dept. of Computer Science; Astola, Jaakko [Tampere Univ. of Technology (Finland). Dept. of Signal Processing
2011-07-01
Logic networks and automata are facets of digital systems. The change of the design of logic networks from skills and art into a scientific discipline was possible by the development of the underlying mathematical theory called the Switching Theory. The fundamentals of this theory come from the attempts towards an algebraic description of laws of thoughts presented in the works by George J. Boole and the works on logic by Augustus De Morgan. As often the case in engineering, when the importance of a problem and the need for solving it reach certain limits, the solutions are searched by many scholars in different parts of the word, simultaneously or at about the same time, however, quite independently and often unaware of the work by other scholars. The formulation and rise of Switching Theory is such an example. This book presents a brief account of the developments of Switching Theory and highlights some less known facts in the history of it. The readers will find the book a fresh look into the development of the field revealing how difficult it has been to arrive at many of the concepts that we now consider obvious. Researchers in the history or philosophy of computing will find this book a valuable source of information that complements the standard presentations of the topic. (orig.)
Generating and checking control logic in the HDL-based design of reversible circuits
DEFF Research Database (Denmark)
Wille, Robert; Keszocze, Oliver; Othmer, Lars
2017-01-01
Although different from the conventional computing paradigm, reversible computation received significant interest due to its applications in various (emerging) technologies. Here, computations can be executed not only from the inputs to the outputs, but also in the reverse direction. This leads...... solution constitutes the first automatic method for these important designs steps in the domain of reversible circuit design....
Logical diagnosis model turbojet engine including double-circuit intermittent flow of his injuries
Directory of Open Access Journals (Sweden)
О.П. Стьопушкіна
2007-01-01
Full Text Available In this article is considered question of the change quantitative and qualitative factors of the technical condition constructive element running part of jet engine. As a result called on experimental studies diagnostic sign were definite sign with provision for intermittent damages and on base this is built expert model of the turbojet double-circuit engine.
Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations
Slaughter, D. W.
1977-01-01
A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.
Directory of Open Access Journals (Sweden)
Mohammed Alawad
2015-03-01
Full Text Available This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit’s overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon.
Programme for test generation for combinatorial and sequential systems
International Nuclear Information System (INIS)
Tran Huy Hoan
1973-01-01
This research thesis reports the computer-assisted search for tests aimed at failure detection in combinatorial and sequential logic circuits. As he wants to deal with complex circuits with many modules such as those met in large scale integrated circuits (LSI), the author used propagation paths. He reports the development of a method which is valid for combinatorial systems and for several sequential circuits comprising elementary logic modules and JK and RS flip-flops. This method is developed on an IBM 360/91 computer in PL/1 language. The used memory space is limited and adjustable with respect to circuit dimension. Computing time is short when compared to that needed by other programmes. The solution is practical and efficient for failure test and localisation
All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits
International Nuclear Information System (INIS)
Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.
2014-01-01
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials
All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits
Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.
2014-01-01
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.
All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits
Energy Technology Data Exchange (ETDEWEB)
Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)
2014-01-21
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.
Multiple atomic scale solid surface interconnects for atom circuits and molecule logic gates
International Nuclear Information System (INIS)
Joachim, C; Martrou, D; Gauthier, S; Rezeq, M; Troadec, C; Jie Deng; Chandrasekhar, N
2010-01-01
The scientific and technical challenges involved in building the planar electrical connection of an atomic scale circuit to N electrodes (N > 2) are discussed. The practical, laboratory scale approach explored today to assemble a multi-access atomic scale precision interconnection machine is presented. Depending on the surface electronic properties of the targeted substrates, two types of machines are considered: on moderate surface band gap materials, scanning tunneling microscopy can be combined with scanning electron microscopy to provide an efficient navigation system, while on wide surface band gap materials, atomic force microscopy can be used in conjunction with optical microscopy. The size of the planar part of the circuit should be minimized on moderate band gap surfaces to avoid current leakage, while this requirement does not apply to wide band gap surfaces. These constraints impose different methods of connection, which are thoroughly discussed, in particular regarding the recent progress in single atom and molecule manipulations on a surface.
Reversible logic synthesis methodologies with application to quantum computing
Taha, Saleem Mohammed Ridha
2016-01-01
This book opens the door to a new interesting and ambitious world of reversible and quantum computing research. It presents the state of the art required to travel around that world safely. Top world universities, companies and government institutions are in a race of developing new methodologies, algorithms and circuits on reversible logic, quantum logic, reversible and quantum computing and nano-technologies. In this book, twelve reversible logic synthesis methodologies are presented for the first time in a single literature with some new proposals. Also, the sequential reversible logic circuitries are discussed for the first time in a book. Reversible logic plays an important role in quantum computing. Any progress in the domain of reversible logic can be directly applied to quantum logic. One of the goals of this book is to show the application of reversible logic in quantum computing. A new implementation of wavelet and multiwavelet transforms using quantum computing is performed for this purpose. Rese...
10-Qubit Entanglement and Parallel Logic Operations with a Superconducting Circuit
Song, Chao; Xu, Kai; Liu, Wuxin; Yang, Chui-ping; Zheng, Shi-Biao; Deng, Hui; Xie, Qiwei; Huang, Keqiang; Guo, Qiujiang; Zhang, Libo; Zhang, Pengfei; Xu, Da; Zheng, Dongning; Zhu, Xiaobo; Wang, H.; Chen, Y.-A.; Lu, C.-Y.; Han, Siyuan; Pan, Jian-Wei
2017-11-01
Here we report on the production and tomography of genuinely entangled Greenberger-Horne-Zeilinger states with up to ten qubits connecting to a bus resonator in a superconducting circuit, where the resonator-mediated qubit-qubit interactions are used to controllably entangle multiple qubits and to operate on different pairs of qubits in parallel. The resulting 10-qubit density matrix is probed by quantum state tomography, with a fidelity of 0.668 ±0.025 . Our results demonstrate the largest entanglement created so far in solid-state architectures and pave the way to large-scale quantum computation.
A liquid-crystal-on-silicon color sequential display using frame buffer pixel circuits
Lee, Sangrok
Next generation liquid-crystal-on-silicon (LCOS) high definition (HD) televisions and image projection displays will need to be low-cost and high quality to compete with existing systems based on digital micromirror devices (DMDs), plasma displays, and direct view liquid crystal displays. In this thesis, a novel frame buffer pixel architecture that buffers data for the next image frame while displaying the current frame, offers such a competitive solution is presented. The primary goal of the thesis is to demonstrate the LCOS microdisplay architecture for high quality image projection displays and at potentially low cost. The thesis covers four main research areas: new frame buffer pixel circuits to improve the LCOS performance, backplane architecture design and testing, liquid crystal modes for the LCOS microdisplay, and system integration and demonstration. The design requirements for the LCOS backplane with a 64 x 32 pixel array are addressed and measured electrical characteristics matches to computer simulation results. Various liquid crystal (LC) modes applicable for LCOS microdisplays and their physical properties are discussed. One- and two-dimensional director simulations are performed for the selected LC modes. Test liquid crystal cells with the selected LC modes are made and their electro-optic effects are characterized. The 64 x 32 LCOS microdisplays fabricated with the best LC mode are optically tested with interface circuitry. The characteristics of the LCOS microdisplays are summarized with the successful demonstration.
Flexible logic circuits composed of chalcogenide-nanocrystal-based thin film transistors
International Nuclear Information System (INIS)
Yun, Junggwon; Cho, Kyoungah; Kim, Sangsig
2010-01-01
Complementary NAND and NOR gates composed of p-channel HgTe-nanocrystal (NC) films and n-channel HgSe-NC films were constructed on back-gate patterned plastic substrates. The NAND gate was made of two HgTe-p-channel thin film transistors (TFTs) in parallel and two HgSe-n-channel TFTs in series. The NOR gate was built up with both two HgSe-n-channel TFTs in parallel and two HgTe-p-channel TFTs in series. The mobility and on/off ratio for the p-channel TFTs were estimated to be 0.9 cm 2 V -1 s -1 and 10, respectively, and those for the n-channel TFTs were measured to be 1.8 cm 2 V -1 s -1 and 10 2 , respectively. The NAND and NOR gates were operated with gains of 1.45 and 1.63 and transition widths of 7.8 and 6.2 V, respectively, at room temperature in air. In addition, the operations of the NAND and NOR logics are reproducible for up to 1000 strain cycles.
A circuit design for multi-inputs stateful OR gate
Energy Technology Data Exchange (ETDEWEB)
Chen, Qiao; Wang, Xiaoping, E-mail: wangxiaoping@hust.edu.cn; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-09-07
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
A circuit design for multi-inputs stateful OR gate
International Nuclear Information System (INIS)
Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-01-01
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE
COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS
Directory of Open Access Journals (Sweden)
Selami KESLER
2009-01-01
Full Text Available The power flow of the rotor circuit is controlled by different methods in induction machines used for producing high torque in applications involved great power and constant output power with constant frequency in wind turbines. The voltage with slip frequency can be applied on rotor windings to produce controlled high torque and obtain optimal power factor and speed control. In this study, firstly, the dynamic effects of the voltage applying on rotor windings through the rings in slip-ring induction machines are researched and undesirable aspects of the method are exposed with simulations supported by experiments. Afterwards, a fuzzy logic based inverter model on rotor side is proposed with a view to improving the dynamic effects, controlling high torque producing and adjusting machine speed in instantaneous forced conditions. For the simulation model of the system in which the stator side is directly connected to the grid in steady state operation, a C/C++ algorithm is developed and the results obtained for different load conditions are discussed.
Directory of Open Access Journals (Sweden)
Ankur Khare
2016-05-01
Full Text Available Delays added by the encryption process represent an overhead for smart computing devices in ad-hoc and ubiquitous computing intelligent systems. Digital Logic Circuits are faster than other computing techniques, so these can be used for fast encryption to minimize processing delays. Chaotic Encryption is more attack-resilient than other encryption techniques. One of the most attractive properties of cryptography is known as an avalanche effect, in which two different keys produce distinct cipher text for the same information. Important properties of chaotic systems are sensitivity to initial conditions and nonlinearity, which makes two similar keys that generate different cipher text a source of confusion. In this paper a novel fast and secure Chaotic Map-based encryption technique using 2’s Compliment (CET-2C has been proposed, which uses a logistic map which implies that a negligible difference in parameters of the map generates different cipher text. Cryptanalysis of the proposed algorithm shows the strength and security of algorithm and keys. Performance of the proposed algorithm has been analyzed in terms of running time, throughput and power consumption. It is to be shown in comparison graphs that the proposed algorithm gave better results compare to different algorithms like AES and some others.
Anticoincidence logic using PALs
International Nuclear Information System (INIS)
Bolanos, L.; Arista Romeu, E.
1997-01-01
This paper describes the functioning principle of an anticoincidence logic and a design of this based on programing logic. The circuit was included in a discriminator of an equipment for single-photon absorptiometry
Low latency asynchronous interface circuits
Sadowski, Greg
2017-06-20
In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.
A novel water-soluble 1,8-naphthalimide as a fluorescent pH-probe and a molecular logic circuit
International Nuclear Information System (INIS)
Georgiev, Nikolai I.; Dimitrova, Margarita D.; Krasteva, Paoleta V.; Bojinov, Vladimir B.
2017-01-01
A novel highly water-soluble fluorescence sensing 1,8-naphthalimide is synthesized and investigated. The novel compound is designed on the “fluorophore-receptor 1 -spacer-receptor 2 ” model as a molecular fluorescence probe for determination of ions in 100% aqueous media. The novel probe comprising hydrazide and N-methylpiperazine substituents is capable of operating simultaneously via ICT and PET signaling mechanism and of recognizing selectively protons and hydroxyl anions over the representative metal ions and anions. Due to the remarkable fluorescence changes as a function of pH the system is able to act as a three output combinatorial logic circuit with two chemical inputs. Two INHIBIT gates in fluorescence and absorption mode as well as an IMPLICATION logic gate are obtained. Because of the parallel action of both INHIBIT gates a magnitude digital comparator is achieved for the first time in this way.
International Nuclear Information System (INIS)
Celestino M, E.
2016-01-01
The Instituto Nacional de Investigaciones Nucleares (ININ) in Mexico has a nuclear reactor type TRIGA Mark III, which was put into operation in 1968. The reactor is used for staff training, radioisotope production, and for research projects of different areas. Over time and due to advances constantly has the electronics industry, maintenance of electronic systems is complicated because basically sometimes components that are no longer manufactured or no longer exist in the market, making it necessary to create projects required modernization. This is the case of the TRIGA reactor of ININ, so the Department of Automation and Instrumentation ININ is undertaking a new project to update the reactor control console. Systems that make up a nuclear reactor protection system (Ps) is relevant, since it is responsible for generating the necessary steps to shut down the reactor to an event of uncertainty which could affect the operators or the installation own actions. As part of the renovation project, this study design is presented to update the Logic of Action (La) of the Ps, whose final design must meet the requirements or specifications set by users and or regulations applicable to nuclear research reactors. One of the requirements established for the proposed new design La, is that it must be implemented with components and devices manufactured with latest technologies, and readily available on the market. The design which is operating currently uses TTL logic whose components are no longer available in the market, so for the new design you decide to use programmable circuits, and specifically, the CPLDs called (by the acronym Complex Programmable Logic Device). These CPLDs are electronic devices that solve complex logic equations and meeting the requirements of functionality and modernity for the new design of the La. In this work the criteria used for the selection of the CPLDs considering the availability and ease of software and hardware to use, and the design and
Energy Technology Data Exchange (ETDEWEB)
Dietze, P [Siemens A.G., Erlangen (Germany, F.R.). Abt. ESTE
1978-01-01
For the evaluation of the effects of switching operations or simulation of line, transformer, and generator outages the influence of interconnected neighbor networks is modelled by network equivalents in the process computer. The basic passive conductivity model is produced by sequential reduction and adapted to fit the active network behavior. The reduction routine uses the admittance matrix, sparse technique and optimal ordering; it is applicable to process computer applications.
Yu, Xue; Lian, Wenjing; Zhang, Jiannan; Liu, Hongyun
2016-06-15
Herein, poly(N-isopropylacrylamide-co-N,N'-dimethylaminoethylmethacrylate) copolymer films were polymerized on electrode surface with a simple one-step method, and the enzyme horseradish peroxidase (HRP) was embedded in the films simultaneously, which were designated as P(NiPAAm-co-DMEM)-HRP. The films exhibited a reversible structure change with the external stimuli, such as pH, CO2, temperature and SO4(2-), causing the cyclic voltammetric (CV) response of electroactive K3Fe(CN)6 at the film electrodes to display the corresponding multi-stimuli sensitive ON-OFF behavior. Based on the switchable CV property of the system and the electrochemical reduction of H2O2 catalyzed by HRP in the films and mediated by Fe(CN)6(3-) in solution, a 5-input/3-output logic gate was established. To further increase the complexity of the logic system, another enzyme glucose oxidase (GOD) was added into the films, designated as P(NiPAAm-co-DMEM)-HRP-GOD. In the presence of oxygen, the oxidation of glucose in the solution was catalyzed by GOD in the films, and the produced H2O2 in situ was recognized and electrocatalytically reduced by HRP and mediated by Fe(CN)6(3-). Based on the bienzyme films, a cascaded or concatenated 4-input/3-output logic gate system was proposed. The present work combined the multi-responsive interface with bioelectrocatalysis to construct cascaded logic circuits, which might open a new avenue to develop biocomputing elements with more sophisticated functions and design novel glucose biosensors. Copyright © 2016 Elsevier B.V. All rights reserved.
Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2015-04-01
Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test
Directory of Open Access Journals (Sweden)
C. Wu
2011-06-01
Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.
Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng
2018-01-03
Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.
Chen, Junhua; Zhou, Shungui; Wen, Junlin
2015-01-07
Concatenated logic circuits operating as a biocomputing keypad-lock security system with an automatic reset function have been successfully constructed on the basis of toehold-mediated strand displacement and three-way-DNA-junction architecture. In comparison with previously reported keypad locks, the distinctive advantage of the proposed security system is that it can be reset and cycled spontaneously a large number of times without an external stimulus, thus making practical applications possible. By the use of a split-G-quadruplex DNAzyme as the signal reporter, the output of the keypad lock can be recognized readily by the naked eye. The "lock" is opened only when the inputs are introduced in an exact order. This requirement provides defense against illegal invasion to protect information at the molecular scale. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Energy Technology Data Exchange (ETDEWEB)
Bonacini, S
2007-11-15
The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.
Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil
2015-10-14
Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.
W. van der Hoek (Wiebe); J.O.M. Jaspars; E. Thijsse
1995-01-01
textabstractWe propose an epistemic logic in which knowledge is fully introspective and implies truth, although truth need not imply epistemic possibility. The logic is presented in sequential format and is interpreted in a natural class of partial models, called balloon models. We examine the
Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing
2017-10-11
The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.
Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu
2017-08-01
The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Directory of Open Access Journals (Sweden)
Mikhail N. Yokhin
2017-12-01
Full Text Available The paper contains an analysis of perspective structures of software and hardware equipment of universal digital design laboratories with the purpose of enabling laboratory classes of digital circuit design to be taken remotely. Implementation characteristics and usage experience of some of those structures applied to labs on several hardware related courses of « Computer science and computer engineering» program in NRNU MEPhI are presented. The paper also considers different aspects of usage of remote access enabled laboratory which should be taken into account to substantiate laboratory configuration from technical and economical standpoints. To increase equipment usage efficiency an approach to group several distinct projects to place them on a single FPGA chip is proposed. The paper shows advisability and gives an example of parametrizable virtual stand for remote debugging of FPGA projects.
Collective of mechatronics circuit
International Nuclear Information System (INIS)
1987-02-01
This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.
Collective of mechatronics circuit
Energy Technology Data Exchange (ETDEWEB)
NONE
1987-02-15
This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.
Synthesis of energy-efficient FSMs implemented in PLD circuits
Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz
2017-11-01
The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.
DEFF Research Database (Denmark)
Nilsson, Jørgen Fischer
A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...
Optical programmable Boolean logic unit.
Chattopadhyay, Tanay
2011-11-10
Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.
Carlton, David Bryan
The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly
Amplifying genetic logic gates.
Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew
2013-05-03
Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.
Logic functions and equations examples and exercises
Steinbach, Bernd
2009-01-01
With a free, downloadable software package available to help solve the exercises, this book focuses on practical and relevant problems that arise in the field of binary logics, with its two main applications - digital circuit design, and propositional logics.
Energy Technology Data Exchange (ETDEWEB)
Gonzalez M, J. L.; Rivero G, T.; Sainz M, E., E-mail: joseluis.gonzalez@inin.gob.mx [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)
2014-10-15
Due to the obsolescence of the instrumentation and control system of the nuclear research reactor IAN-R1, the Institute of Geology and Mining of Colombia, IngeoMinas, launched an international convoking for renewal it which was won by the Instituto Nacional de Investigaciones Nucleares (ININ). Within systems to design, the reactor protection system is described as important for safety, because this carried out, among others two primary functions: 1) ensuring the reactor shutdown safely, and 2) controlling the interlocks to protect against operational errors if defined conditions have not been met. To fulfill these functions, the various subsystems related to the safety report the state in which they are using binary signals and are connected to the inputs of two redundant logic wiring circuits called action logics (Al) that are part of the reactor protection system. These Al also serve as logical interface to indicate at all times the status of subsystems, both the operator and other systems. In the event that any of the subsystems indicates a state of insecurity in the reactor, the Al generate signals off (or scram) of the reactor, maintaining the interlock until the operator sends a reset signal. In this paper the design, implementation, verification and testing of circuits that make up the Al 1 and 2 of IAN-R1 reactor is described, considering the fulfillment of the requirements that the different international standards imposed on this type of design. (Author)
Methods in Logic Based Control
DEFF Research Database (Denmark)
Christensen, Georg Kronborg
1999-01-01
Desing and theory of Logic Based Control systems.Boolean Algebra, Karnaugh Map, Quine McClusky's algorithm. Sequential control design. Logic Based Control Method, Cascade Control Method. Implementation techniques: relay, pneumatic, TTL/CMOS,PAL and PLC- and Soft_PLC implementation. PLC...
Adaptive sequential controller
Energy Technology Data Exchange (ETDEWEB)
El-Sharkawi, Mohamed A. (Renton, WA); Xing, Jian (Seattle, WA); Butler, Nicholas G. (Newberg, OR); Rodriguez, Alonso (Pasadena, CA)
1994-01-01
An adaptive sequential controller (50/50') for controlling a circuit breaker (52) or other switching device to substantially eliminate transients on a distribution line caused by closing and opening the circuit breaker. The device adaptively compensates for changes in the response time of the circuit breaker due to aging and environmental effects. A potential transformer (70) provides a reference signal corresponding to the zero crossing of the voltage waveform, and a phase shift comparator circuit (96) compares the reference signal to the time at which any transient was produced when the circuit breaker closed, producing a signal indicative of the adaptive adjustment that should be made. Similarly, in controlling the opening of the circuit breaker, a current transformer (88) provides a reference signal that is compared against the time at which any transient is detected when the circuit breaker last opened. An adaptive adjustment circuit (102) produces a compensation time that is appropriately modified to account for changes in the circuit breaker response, including the effect of ambient conditions and aging. When next opened or closed, the circuit breaker is activated at an appropriately compensated time, so that it closes when the voltage crosses zero and opens when the current crosses zero, minimizing any transients on the distribution line. Phase angle can be used to control the opening of the circuit breaker relative to the reference signal provided by the potential transformer.
Adaptive sequential controller
El-Sharkawi, Mohamed A.; Xing, Jian; Butler, Nicholas G.; Rodriguez, Alonso
1994-01-01
An adaptive sequential controller (50/50') for controlling a circuit breaker (52) or other switching device to substantially eliminate transients on a distribution line caused by closing and opening the circuit breaker. The device adaptively compensates for changes in the response time of the circuit breaker due to aging and environmental effects. A potential transformer (70) provides a reference signal corresponding to the zero crossing of the voltage waveform, and a phase shift comparator circuit (96) compares the reference signal to the time at which any transient was produced when the circuit breaker closed, producing a signal indicative of the adaptive adjustment that should be made. Similarly, in controlling the opening of the circuit breaker, a current transformer (88) provides a reference signal that is compared against the time at which any transient is detected when the circuit breaker last opened. An adaptive adjustment circuit (102) produces a compensation time that is appropriately modified to account for changes in the circuit breaker response, including the effect of ambient conditions and aging. When next opened or closed, the circuit breaker is activated at an appropriately compensated time, so that it closes when the voltage crosses zero and opens when the current crosses zero, minimizing any transients on the distribution line. Phase angle can be used to control the opening of the circuit breaker relative to the reference signal provided by the potential transformer.
Fuzzy Logic vs. Neutrosophic Logic: Operations Logic
Directory of Open Access Journals (Sweden)
Salah Bouzina
2016-12-01
Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.
Timed Safety Automata and Logic Conformance
National Research Council Canada - National Science Library
Young, Frank
1999-01-01
Timed Logic Conformance (TLC) is used to verify the behavioral and timing properties of detailed digital circuits against abstract circuit specifications when both are modeled as Timed Safety Automata (TSA...
Microelectromechanical resonator based digital logic elements
Hafiz, Md Abdullah Al
2016-10-20
Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.
Microelectromechanical resonator based digital logic elements
Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.; Fariborzi, Hossein
2016-01-01
Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.
Wolfendale, E
2013-01-01
MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi
PM 3655 PHILIPS Logic analyzer
A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.
Lu, Jiao Yang; Zhang, Xin Xing; Huang, Wei Tao; Zhu, Qiu Yan; Ding, Xue Zhi; Xia, Li Qiu; Luo, Hong Qun; Li, Nian Bing
2017-09-19
The most serious and yet unsolved problems of molecular logic computing consist in how to connect molecular events in complex systems into a usable device with specific functions and how to selectively control branchy logic processes from the cascading logic systems. This report demonstrates that a Boolean logic tree is utilized to organize and connect "plug and play" chemical events DNA, nanomaterials, organic dye, biomolecule, and denaturant for developing the dual-signal electrochemical evolution aptasensor system with good resettability for amplification detection of thrombin, controllable and selectable three-state logic computation, and keypad lock security operation. The aptasensor system combines the merits of DNA-functionalized nanoamplification architecture and simple dual-signal electroactive dye brilliant cresyl blue for sensitive and selective detection of thrombin with a wide linear response range of 0.02-100 nM and a detection limit of 1.92 pM. By using these aforementioned chemical events as inputs and the differential pulse voltammetry current changes at different voltages as dual outputs, a resettable three-input biomolecular keypad lock based on sequential logic is established. Moreover, the first example of controllable and selectable three-state molecular logic computation with active-high and active-low logic functions can be implemented and allows the output ports to assume a high impediment or nothing (Z) state in addition to the 0 and 1 logic levels, effectively controlling subsequent branchy logic computation processes. Our approach is helpful in developing the advanced controllable and selectable logic computing and sensing system in large-scale integration circuits for application in biomedical engineering, intelligent sensing, and control.
Electronic devices and circuits
Pridham, Gordon John
1972-01-01
Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of
Surface confined assemblies and polymers for sensing and molecular logic
de Ruiter, Graham; Altman, Marc; Motiei, Leila; Lahav, Michal; van der Boom, Milko E.
2013-05-01
Since the development of molecule-based sensors and the introduction of molecules mimicking the behavior of the AND gate in solution by de Silva in 1993, molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. The molecular approach toward Boolean logic resulted in intriguing proofs of concepts in solution including logic gates, half-adders, multiplexers, and flip-flop logic circuits. Molecular assemblies can perform diverse logic tasks by reconfiguring their inputs. Our recent research activities focus on MBLC with electrochromic polymers and immobilized polypyridyl complexes on solid support. We have designed a series of coordination-based thin films that are formed linearly by stepwise wet-chemical deposition or by self-propagating molecular assembly. The electrochromic properties of these films can be used for (i) detecting various analytes in solution and in the air, (ii) MBLC, (iii) electron-transfer studies, and (iv) interlayers for efficient inverted bulk-heterojunction solar cells. Our concept toward MBLC with functionalized surfaces is applicable to electrochemical and chemical inputs coupled with optical readout. Using this approach, we demonstrated various logic architectures with redox-active functionalized surfaces. Electrochemically operated sequential logic systems (e.g., flip-flops), multi-valued logic, and multi-state memory have been designed, which can improve computational power without increasing spatial requirements. Applying multi-valued digits in data storage and information processing could exponentially increase memory capacity. Our approach is applicable to highly diverse electrochromic thin films that operate at practical voltages (< 1.5 V).
Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits
Directory of Open Access Journals (Sweden)
Ruiping Cao
2014-01-01
Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.
Radiation tolerant combinational logic cell
Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)
2009-01-01
A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.
Embedding Logics into Product Logic
Czech Academy of Sciences Publication Activity Database
Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David
1998-01-01
Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics
A functional language for describing reversible logic
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal
2012-01-01
Reversible logic is a computational model where all gates are logically reversible and combined in circuits such that no values are lost or duplicated. This paper presents a novel functional language that is designed to describe only reversible logic circuits. The language includes high....... Reversibility of descriptions is guaranteed with a type system based on linear types. The language is applied to three examples of reversible computations (ALU, linear cosine transformation, and binary adder). The paper also outlines a design flow that ensures garbage- free translation to reversible logic...... circuits. The flow relies on a reversible combinator language as an intermediate language....
Logical safety system for triggering off the protection action of a safety actuator
International Nuclear Information System (INIS)
Plaige, Yves.
1982-01-01
This invention applies in particular to the emergency triggering of safety actuators controlling the shutdown of a nuclear reactor. This logical safety system includes four redundant lines each composed, inter alia, of a logical circuit for controlling the triggering of a protection action, a logical alarm circuit connected to the control circuit and a logical inhibiting circuit making it impossible to inhibit several alarm circuits simultaneously [fr
Smullyan, Raymond
2008-01-01
This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T
Automatic circuit analysis based on mask information
International Nuclear Information System (INIS)
Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.
1976-01-01
The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
Russinoff, David M.
1995-01-01
We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.
Claude Ziad Bayeh
2015-01-01
The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...
Programmable Array Logic Design
International Nuclear Information System (INIS)
Demon Handoyo; Djen Djen Djainal
2007-01-01
Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)
Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong
2014-07-01
DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of
Marston, R M
2013-01-01
Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com
'Speedy' superconducting circuits
International Nuclear Information System (INIS)
Holst, T.
1994-01-01
The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)
Kleene, Stephen Cole
1967-01-01
Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.
Meyer, J.J.Ch.; Broersen, J.M.; Herzig, A.
2015-01-01
This paper presents an overview of so-called BDI logics, logics where the notion of Beliefs, Desires and Intentions play a central role. Starting out from the basic ideas about BDI by Bratman, we consider various formalizations in logic, such as the approach of Cohen and Levesque, slightly
Ni, Xin-long; Zeng, Xi; Redshaw, Carl; Yamato, Takehiko
2011-07-15
A ratiometric fluorescent receptor with a C(3) symmetric structure based on a pyrene-linked triazole-modified homooxacalix[3]arene (L) was synthesized and characterized. This system exhibited an interesting ratiometric detection signal output for targeting cations and anions through switching the excimer emission of pyrene from the "on-off" to the "off-on" type in neutral solution. (1)H NMR titration results suggested that the Zn(2+) center of receptor L·Zn(2+) provided an excellent pathway of organizing anion binding groups for optimal host-guest interactions. It is thus believed that this receptor has potential application in sensing, detection, and recognition of both Zn(2+) and H(2)PO(4)(-) ions with different optical signals. In addition, the fluorescence emission changes by the inputs of Zn(2+) and H(2)PO(4)(-) ions can be viewed as a combinational R-S latch logic circuit at the molecular level.
Energy efficient circuit design using nanoelectromechanical relays
Venkatasubramanian, Ramakrishnan
Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS
Rapid single flux quantum logic in high temperature superconductor technology
Shunmugavel, K.
2006-01-01
A Josephson junction is the basic element of rapid single flux quantum logic (RSFQ) circuits. A high operating speed and low power consumption are the main advantages of RSFQ logic over semiconductor electronic circuits. To realize complex RSFQ circuits in HTS technology one needs a reproducible
Flexible programmable logic module
Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.
2001-01-01
The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.
All optical programmable logic array (PLA)
Hiluf, Dawit
2018-03-01
A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.
International Nuclear Information System (INIS)
Mukhanov, O.A.; Rylov, S.V.; Semenov, V.K.; Vyshenskii, S.V.
1989-01-01
Several ways of local timing of the Josephson-junction RSFQ (Rapid Single Flux Quantum) logic elements are proposed, and their peculiarities are discussed. Several examples of serial and parallel pipelined arithmetic blocks using various types of timing are suggested and their possible performance is discussed. Serial devices enable one to perform n-bit functions relatively slowly but using integrated circuits of a moderate integration scale, while parallel pipelined devices are more hardware-wasteful but promise extremely high productivity
Rushton, Andrew
2011-01-01
Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types. This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features. Features to this edition include: * a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies...
Design and experimentation of BSFQ logic devices
International Nuclear Information System (INIS)
Hosoki, T.; Kodaka, H.; Kitagawa, M.; Okabe, Y.
1999-01-01
Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic 'Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported. (author)
Le Balleur, J. C.
1988-01-01
The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.
Short circuit protection for a power distribution system
Owen, J. R., III
1969-01-01
Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.
Superconducting digital logic amplifier
International Nuclear Information System (INIS)
Przybysz, J.X.
1989-01-01
This paper describes a superconducting digital logic amplifier for interfacing between a Josephson junction logic circuit having output current and a higher voltage semiconductor circuit input. The amplifier comprising: an input terminal for connection to a; an output terminal for connection to a semiconductor circuit input; an input, lower critical current, Josephson junction having first and second terminals; a first series string of at least three lower critical current Josephson junctions. The first series string being connected to the first terminal of the input Josephson junction such that the first series string is in series with the input Josephson junction to provide a series combination. The input terminal being connected to the first terminal of the input Josephson junction, and with the critical current of the lower critical current Josephson junctions of the input Josephson junction and the first series Josephson junctions being less than the output current of the low voltage Josephson junction circuit; a second series string of at least four higher critical current Josephson junctions. The second string being connected in parallel with the series combination to provide parallel strings having an upper common connection and a lower common connection. The lower common connection being connected to the second terminal of the input Josephson junction and the upper common connection being connected to the output terminal; and a pulsed DC current source connected the parallel strings at the upper common connection. The DC current source having a current at least equal to the critical current of the higher critical current Josephson junctions
Marston, R M
1995-01-01
CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu
Hybdrid integral circuit for proportional chambers
International Nuclear Information System (INIS)
Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.
1978-01-01
Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture
Logical foundation of quantum mechanics
International Nuclear Information System (INIS)
Stachow, E.W.
1980-01-01
The subject of this article is the reconstruction of quantum mechanics on the basis of a formal language of quantum mechanical propositions. During recent years, research in the foundations of the language of science has given rise to a dialogic semantics that is adequate in the case of a formal language for quantum physics. The system of sequential logic which is comprised by the language is more general than classical logic; it includes the classical system as a special case. Although the system of sequential logic can be founded without reference to the empirical content of quantum physical propositions, it establishes an essential part of the structure of the mathematical formalism used in quantum mechanics. It is the purpose of this paper to demonstrate the connection between the formal language of quantum physics and its representation by mathematical structures in a self-contained way. (author)
Tugué, Tosiyuki; Slaman, Theodore
1989-01-01
These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.
Generator of combined logical signals
International Nuclear Information System (INIS)
Laviron, Andre; Berard, Claude.
1982-01-01
The invention concerns a generator of combined logical signals to form combinations of two outputs at logical level 1 and N-2 outputs at logical level 0, among N generator outputs. This generator is characterized in that it includes a set of N means for storing combinations. Means enable the N storage means to be loaded with the logical levels corresponding to a pre-set starting combination, to control the operations for shifting the contents of the storage means and to control, by transfer facilities, the transfers of contents between these storage means. Controls enable the storage means to be actuated in order to obtain combinations of logical levels 1 and 0. The generation of combinations can be stopped after another pre-set combination. Application is for testing of safety circuits for nuclear power stations [fr
Orthogonal Algorithm of Logic Probability and Syndrome-Testable Analysis
Institute of Scientific and Technical Information of China (English)
无
1990-01-01
A new method,orthogonal algoritm,is presented to compute the logic probabilities(i.e.signal probabilities)accurately,The transfer properties of logic probabilities are studied first,which are useful for the calculation of logic probability of the circuit with random independent inputs.Then the orthogonal algoritm is described to compute the logic probability of Boolean function realized by a combinational circuit.This algorithm can make Boolean function “ORTHOGONAL”so that the logic probabilities can be easily calculated by summing up the logic probabilities of all orthogonal terms of the Booleam function.
All-optical symmetric ternary logic gate
Chattopadhyay, Tanay
2010-09-01
Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.
Logical design for computers and control
Dodd, Kenneth N
1972-01-01
Logical Design for Computers and Control Logical Design for Computers and Control gives an introduction to the concepts and principles, applications, and advancements in the field of control logic. The text covers topics such as logic elements; high and low logic; kinds of flip-flops; binary counting and arithmetic; and Boolean algebra, Boolean laws, and De Morgan's theorem. Also covered are topics such as electrostatics and atomic theory; the integrated circuit and simple control systems; the conversion of analog to digital systems; and computer applications and control. The book is recommend
Transistor and integrated circuit manufacture
International Nuclear Information System (INIS)
Colman, D.
1978-01-01
This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)
Transistor and integrated circuit manufacture
Energy Technology Data Exchange (ETDEWEB)
Colman, D
1978-09-27
This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.
Fan, Daoqing; Shang, Changshuai; Gu, Wenling; Wang, Erkang; Dong, Shaojun
2017-08-09
Glutathione (GSH) plays crucial roles in various biological functions, the level alterations of which have been linked to varieties of diseases. Herein, we for the first time expanded the application of oxidase-like property of MnO 2 nanosheet (MnO 2 NS) to fluorescent substrates of peroxidase. Different from previously reported fluorescent quenching phenomena, we found that MnO 2 NS could not only largely quench the fluorescence of highly fluorescent Scopoletin (SC) but also surprisingly enhance that of nonfluorescent Amplex Red (AR) via oxidation reaction. If MnO 2 NS is premixed with GSH, it will be reduced to Mn 2+ and lose the oxidase-like property, accompanied by subsequent increase in SC's fluorescence and decrease in AR's. On the basis of the above mechanism, we construct the first MnO 2 NS-based ratiometric fluorescent sensor for ultrasensitive and selective detection of GSH. Notably, this ratiometric sensor is programmed by the cascade logic circuit (an INHIBIT gate cascade with a 1 to 2 decoder). And a linear relationship between ratiometric fluorescent intensities of the two substrates and logarithmic values of GSH's concentrations is obtained. The detection limit of GSH is as low as 6.7 nM, which is much lower than previous ratiometric fluorescent sensors, and the lowest MnO 2 NS-based fluorescent GSH sensor reported so far. Furthermore, this sensor is simple, label-free, and low-cost; it also presents excellent applicability in human serum samples.
Digital circuit boards mach 1 GHz
Morrison, Ralph
2012-01-01
A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove
Development of RPS trip logic based on PLD technology
International Nuclear Information System (INIS)
Choi, Jong Gyun; Lee, Dong Young
2012-01-01
The majority of instrumentation and control (I and C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I and C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I and C systems. Therefore, existing NPPs are replacing the obsolete analog I and C systems with advanced digital systems. New NPPs are also adopting digital I and C systems because the economic efficiencies and usability of the systems are higher than the analog I and C systems. Digital I and C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.
Fundamental physics issues of multilevel logic in developing a parallel processor.
Bandyopadhyay, Anirban; Miki, Kazushi
2007-06-01
In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.
Propositional Logics of Dependence
Yang, F.; Väänänen, J.
2016-01-01
In this paper, we study logics of dependence on the propositional level. We prove that several interesting propositional logics of dependence, including propositional dependence logic, propositional intuitionistic dependence logic as well as propositional inquisitive logic, are expressively complete
DEFF Research Database (Denmark)
Braüner, Torben
2011-01-01
Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....
Nanowire NMOS Logic Inverter Characterization.
Hashim, Yasir
2016-06-01
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.
Introduction to logic circuits & logic design with verilog
LaMeres, Brock J
2017-01-01
This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on ...
Introduction to logic circuits & logic design with VHDL
LaMeres, Brock J
2017-01-01
This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion...
Graphical approach for multiple values logic minimization
Awwal, Abdul Ahad S.; Iftekharuddin, Khan M.
1999-03-01
Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.
Bizer, David S; DeMarzo, Peter M
1992-01-01
The authors study environments in which agents may borrow sequentially from more than one leader. Although debt is prioritized, additional lending imposes an externality on prior debt because, with moral hazard, the probability of repayment of prior loans decreases. Equilibrium interest rates are higher than they would be if borrowers could commit to borrow from at most one bank. Even though the loan terms are less favorable than they would be under commitment, the indebtedness of borrowers i...
Chaplin, J C; Russell, N A; Krasnogor, N
2012-07-01
In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.
Smets, P
1995-01-01
We start by describing the nature of imperfect data, and giving an overview of the various models that have been proposed. Fuzzy sets theory is shown to be an extension of classical set theory, and as such has a proeminent role or modelling imperfect data. The mathematic of fuzzy sets theory is detailled, in particular the role of the triangular norms. The use of fuzzy sets theory in fuzzy logic and possibility theory,the nature of the generalized modus ponens and of the implication operator for approximate reasoning are analysed. The use of fuzzy logic is detailled for application oriented towards process control and database problems.
DEFF Research Database (Denmark)
Reynolds, John C.
2002-01-01
In joint work with Peter O'Hearn and others, based on early ideas of Burstall, we have developed an extension of Hoare logic that permits reasoning about low-level imperative programs that use shared mutable data structure. The simple imperative programming language is extended with commands (not...... with the inductive definition of predicates on abstract data structures, this extension permits the concise and flexible description of structures with controlled sharing. In this paper, we will survey the current development of this program logic, including extensions that permit unrestricted address arithmetic...
Classical Logic and Quantum Logic with Multiple and Common Lattice Models
Directory of Open Access Journals (Sweden)
Mladen Pavičić
2016-01-01
Full Text Available We consider a proper propositional quantum logic and show that it has multiple disjoint lattice models, only one of which is an orthomodular lattice (algebra underlying Hilbert (quantum space. We give an equivalent proof for the classical logic which turns out to have disjoint distributive and nondistributive ortholattices. In particular, we prove that both classical logic and quantum logic are sound and complete with respect to each of these lattices. We also show that there is one common nonorthomodular lattice that is a model of both quantum and classical logic. In technical terms, that enables us to run the same classical logic on both a digital (standard, two-subset, 0-1-bit computer and a nondigital (say, a six-subset computer (with appropriate chips and circuits. With quantum logic, the same six-element common lattice can serve us as a benchmark for an efficient evaluation of equations of bigger lattice models or theorems of the logic.
HDL to verification logic translator
Gambles, J. W.; Windley, P. J.
1992-01-01
The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.
CMOS digital integrated circuits a first course
Hawkins, Charles; Zarkesh-Ha, Payman
2016-01-01
This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.
Reconfigurable Optical Directed-Logic Circuits
2015-11-20
before etching and 1.03 nm rms after etching , which is much less than the optical wavelength 488 nm. Fig. 6. (a) SEM image of an AlN grating...implemented a wet chemical etch to produce an adiabatic taper that has been shown to efficiently couple into waveguides [16]. Tapered optical fibre tips were...fabricated by etching the tip in 48% aqueous hydrofluoric acid (HF) with an organic protective layer of 1-bromodecane. Prior to etching , the fiber
Circuit Simulation of All-Spin Logic
Alawein, Meshal
2016-01-01
. In this thesis, we propose an improved stochastic magnetization dynamics/time-dependent spin transport model based on a finite-difference scheme of both the temporal and spatial derivatives to capture the key features of ASL. The approach yields new finite
DEFF Research Database (Denmark)
Carbone, Marco; Montesi, Fabrizio; Schürmann, Carsten
2014-01-01
In Choreographic Programming, a distributed system is programmed by giving a choreography, a global description of its interactions, instead of separately specifying the behaviour of each of its processes. Process implementations in terms of a distributed language can then be automatically...... projected from a choreography. We present Linear Compositional Choreographies (LCC), a proof theory for reasoning about programs that modularly combine choreographies with processes. Using LCC, we logically reconstruct a semantics and a projection procedure for programs. For the first time, we also obtain...... a procedure for extracting choreographies from process terms....
Superconducting flux flow digital circuits
International Nuclear Information System (INIS)
Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.
1993-01-01
The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic
Small circuits for cryptography.
Energy Technology Data Exchange (ETDEWEB)
Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik
2005-10-01
This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.
Electronic circuits fundamentals & applications
Tooley, Mike
2015-01-01
Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The
Wave Pipelining Using Self Reset Logic
Directory of Open Access Journals (Sweden)
Miguel E. Litvin
2008-01-01
Full Text Available This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations. To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID. These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT. These properties simplify the implementation of wave pipelined circuits. General timing analysis is provided and compared with previous implementations. Results of circuit implementation are presented together with conclusions and future work.
International Nuclear Information System (INIS)
Mittelstaedt, P.
1979-01-01
The subspaces of Hilbert space constitute an orthocomplemented quasimodular lattice Lsub(q) for which neither a two-valued function nor generalized truth function exist. A generalisation of the dialogic method can be used as an interpretation of a lattice Lsub(qi), which may be considered as the intuitionistic part of Lsub(q). Some obvious modifications of the dialogic method are introduced which come from the possible incommensurability of propositions about quantum mechanical systems. With the aid of this generalized dialogic method a propositional calculus Qsub(eff) is derived which is similar to the calculus of effective (intuitionistic) logic, but contains a few restrictions which are based on the incommensurability of quantum mechanical propositions. It can be shown within the framework of the calculus Qsub(eff) that the value-definiteness of the elementary propositions which are proved by quantum mechanical propositions is inherited by all finite compund propositions. In this way one arrives at the calculus Q of full quantum logic which incorporates the principle of excluded middle for all propositions and which is a model for the lattice Lsub(q). (Auth.)
Bochvar-McCarthy logic and process algebra
Bergstra, J.A.; Ponse, A.
1998-01-01
We propose a combination of Bochvar's strict three-valued logic, McCarthy's sequential three-valued logic, and process algebra via the conditional guard construct. This combination entails the introduction of a new constant meaningless in process algebra. We present an operational semantics
Realistic Realizations Of Threshold Circuits
Razavi, Hassan M.
1987-08-01
Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings
DEFF Research Database (Denmark)
Modal logic is a subject with ancient roots in the western logical tradition. Up until the last few generations, it was pursued mainly as a branch of philosophy. But in recent years, the subject has taken new directions with connections to topics in computer science and mathematics. This volume...... is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...... epistemic logic, and the logic of evidence....
Modeling and simulation of single-event effect in CMOS circuit
International Nuclear Information System (INIS)
Yue Suge; Zhang Xiaolin; Zhao Yuanfu; Liu Lin; Wang Hanning
2015-01-01
This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed. (review)
Paraconsistent Computational Logic
DEFF Research Database (Denmark)
Jensen, Andreas Schmidt; Villadsen, Jørgen
2012-01-01
In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study....
Microelectromechanical reprogrammable logic device
Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.
2016-01-01
on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance
Doberkat, Ernst-Erich
2009-01-01
Combining coalgebraic reasoning, stochastic systems and logic, this volume presents the principles of coalgebraic logic from a categorical perspective. Modal logics are also discussed, including probabilistic interpretations and an analysis of Kripke models.
Logical operations realized on the Ising chain of N qubits
International Nuclear Information System (INIS)
Asano, Masanari; Tateda, Norihiro; Ishii, Chikara
2004-01-01
Multiqubit logical gates are proposed as implementations of logical operations on N qubits realized physically by the local manipulation of qubits before and after the one-time evolution of an Ising chain. This construction avoids complicated tuning of the interactions between qubits. The general rules of the action of multiqubit logical gates are derived by decomposing the process into the product of two-qubit logical operations. The formalism is demonstrated by the construction of a special type of multiqubit logical gate that is simulated by a quantum circuit composed of controlled-NOT gates
Low swing differential logic for mixed signal applications
International Nuclear Information System (INIS)
Fischer, P.; Kraft, E.
2004-01-01
Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power
Proceedings of the sixteenth international symposium on multiple-valued logic
International Nuclear Information System (INIS)
Anon.
1986-01-01
This book presents the papers given at a conference on the mathematical logic behind artificial intelligence and expert systems. Topics considered at the conference included logic programming, probability, memory processing, electro-optical effects, fuzzy logic, set theory, a fuzzy expert system based on relations, sequential machines, computerized simulation, and algorithms
Classical logic and logicism in human thought
Elqayam, Shira
2012-01-01
This chapter explores the role of classical logic as a theory of human reasoning. I distinguish between classical logic as a normative, computational and algorithmic system, and review its role is theories of human reasoning since the 1960s. The thesis I defend is that psychological theories have been moving further and further away from classical logic on all three levels. I examine some prominent example of logicist theories, which incorporate logic in their psychological account, includin...
Logic programming extensions of Horn clause logic
Directory of Open Access Journals (Sweden)
Ron Sigal
1988-11-01
Full Text Available Logic programming is now firmly established as an alternative programming paradigm, distinct and arguably superior to the still dominant imperative style of, for instance, the Algol family of languages. The concept of a logic programming language is not precisely defined, but it is generally understood to be characterized buy: a declarative nature; foundation in some well understood logical system, e.g., first order logic.
Adiabatic logic future trend and system level perspective
Teichmann, Philip
2012-01-01
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the p...
Junction and circuit fabrication
International Nuclear Information System (INIS)
Jackel, L.D.
1980-01-01
Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)
Cooper, James A.
1986-01-01
A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and failsafe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
Three-valued logics in modal logic
Kooi, Barteld; Tamminga, Allard
2013-01-01
Every truth-functional three-valued propositional logic can be conservatively translated into the modal logic S5. We prove this claim constructively in two steps. First, we define a Translation Manual that converts any propositional formula of any three-valued logic into a modal formula. Second, we
Energy Technology Data Exchange (ETDEWEB)
Celestino M, E.
2016-07-01
The Instituto Nacional de Investigaciones Nucleares (ININ) in Mexico has a nuclear reactor type TRIGA Mark III, which was put into operation in 1968. The reactor is used for staff training, radioisotope production, and for research projects of different areas. Over time and due to advances constantly has the electronics industry, maintenance of electronic systems is complicated because basically sometimes components that are no longer manufactured or no longer exist in the market, making it necessary to create projects required modernization. This is the case of the TRIGA reactor of ININ, so the Department of Automation and Instrumentation ININ is undertaking a new project to update the reactor control console. Systems that make up a nuclear reactor protection system (Ps) is relevant, since it is responsible for generating the necessary steps to shut down the reactor to an event of uncertainty which could affect the operators or the installation own actions. As part of the renovation project, this study design is presented to update the Logic of Action (La) of the Ps, whose final design must meet the requirements or specifications set by users and or regulations applicable to nuclear research reactors. One of the requirements established for the proposed new design La, is that it must be implemented with components and devices manufactured with latest technologies, and readily available on the market. The design which is operating currently uses TTL logic whose components are no longer available in the market, so for the new design you decide to use programmable circuits, and specifically, the CPLDs called (by the acronym Complex Programmable Logic Device). These CPLDs are electronic devices that solve complex logic equations and meeting the requirements of functionality and modernity for the new design of the La. In this work the criteria used for the selection of the CPLDs considering the availability and ease of software and hardware to use, and the design and
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
Energy Technology Data Exchange (ETDEWEB)
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)
2013-12-21
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
International Nuclear Information System (INIS)
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.
2013-01-01
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices
Toward spin-based Magneto Logic Gate in Graphene
Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland
Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.
A reconfigurable NAND/NOR genetic logic gate.
Goñi-Moreno, Angel; Amos, Martyn
2012-09-18
Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.
The application of computer logic design in the trigger system
International Nuclear Information System (INIS)
Zhao Dixin; Ding Huiliang; Gu Jianhui
1996-01-01
The programmable logic devices PLD and FPGA, which are developing steadily recently, can be configured by user. Designers define the logic functions of the circuit and revise these functions when necessary. The application of these devices in the trigger system and development system is introduced
A novel integrated circuit for semiconductor radiation detectors with sparse readout
International Nuclear Information System (INIS)
Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu
2008-01-01
A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)
Smart molecules at work--mimicking advanced logic operations.
Andréasson, Joakim; Pischel, Uwe
2010-01-01
Molecular logic is an interdisciplinary research field, which has captured worldwide interest. This tutorial review gives a brief introduction into molecular logic and Boolean algebra. This serves as the basis for a discussion of the state-of-the-art and future challenges in the field. Representative examples from the most recent literature including adders/subtractors, multiplexers/demultiplexers, encoders/decoders, and sequential logic devices (keypad locks) are highlighted. Other horizons, such as the utility of molecular logic in bio-related applications, are discussed as well.
Unbalanced Neuronal Circuits in Addiction
Volkow, Nora D.; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D.
2013-01-01
Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation, , to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it.
Heunen, Chris
2008-01-01
We consider categorical logic on the category of Hilbert spaces. More generally, in fact, any pre-Hilbert category suffices. We characterise closed subobjects, and prove that they form orthomodular lattices. This shows that quantum logic is just an incarnation of categorical logic, enabling us to establish an existential quantifier for quantum logic, and conclude that there cannot be a universal quantifier.
Circuit arrangement of an electronic component for the design of fail-safe protective circuits
International Nuclear Information System (INIS)
Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.
1974-01-01
The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de
Fast logic modules with programmed functions
International Nuclear Information System (INIS)
Zinov, V.G.; Selikov, A.V.
1987-01-01
Modern nuclear-physical experiment procedure requires automated control and adjustment of event selection and recording systems. Nanosecond programmed-control units realizing optional set of combinational logic functions are described. Programmed permanent storage device is the basis of one unit, and on-line storage device, preliminary provided with truth tables, is in the basis of the other units. The resolution time is 40 ns. By means of auxiliary unit the programmed logic devices with sequent storage elements (digital timer and pulse generator; multiple-phase generator; sequential digital controller) are realized. The units are performed in CAMAC standard, the modules size being 1M
Metamathematics of fuzzy logic
Hájek, Petr
1998-01-01
This book presents a systematic treatment of deductive aspects and structures of fuzzy logic understood as many valued logic sui generis. Some important systems of real-valued propositional and predicate calculus are defined and investigated. The aim is to show that fuzzy logic as a logic of imprecise (vague) propositions does have well-developed formal foundations and that most things usually named `fuzzy inference' can be naturally understood as logical deduction.
Berg Johansen, Christina; Bock Waldorff, Susanne
2015-01-01
This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guided by institutional logics, as well as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to...
Logic design of Josephson network. II
International Nuclear Information System (INIS)
Nakajima, K.; Onodera, Y.
1978-01-01
By numerical calculations of the differential-difference sine-Gordon equation, we have discussed the discrete Josephson-junction transmission lines which are constructed of a series of small-area Josephson junctions connected by superconducting strips. It is shown that the discrete Josephson lines containing D lines, N lines, T turning points, and S turning points are elementarily characterized by the discreteness parameter (2πLI/sub c//Phi 0 )/sup 1/2/. On the discrete Josephson logic circuits there exists a region of forbidden propagation in the (2πLI/sub c//Phi 0 )/sup 1/2/-γ (bias-current parameter) plane for single flux quanta. A single flux quantum can be stuffed in a small area of the discrete Josephson logic circuits. The discrete circuits can be conveniently and easily linked to each other, in a practical fabrication of a Josephson network
Logic delays of 5-μm resistor coupled Josephson logic
International Nuclear Information System (INIS)
Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.
1982-01-01
Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented
Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states
Energy Technology Data Exchange (ETDEWEB)
Kish, Laszlo B. [Texas A and M University, Department of Electrical and Computer Engineering, College Station, TX 77843-3128 (United States)], E-mail: laszlo.kish@ece.tamu.edu
2009-03-02
A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.
Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states
International Nuclear Information System (INIS)
Kish, Laszlo B.
2009-01-01
A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart
Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states
Kish, Laszlo B.
2009-03-01
A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case ( N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.
Simultaneous G-Quadruplex DNA Logic.
Bader, Antoine; Cockroft, Scott L
2018-04-03
A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.
Optical reversible programmable Boolean logic unit.
Chattopadhyay, Tanay
2012-07-20
Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.
New data structures and algorithms for logic synthesis and verification
Amaru, Luca Gaetano
2017-01-01
This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines. · Provides a comprehensive, theoretical study on majority and biconditional logic for logic synthesis; · Updates the current scenario in synthesis and verification – especially in light of emerging technologies; · Demonstrates applications to CMOS technology and emerging technologies.
The design of charge measurement circuit of MWPC
International Nuclear Information System (INIS)
Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu
2010-01-01
It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)
Connections among quantum logics
International Nuclear Information System (INIS)
Lock, P.F.; Hardegree, G.M.
1985-01-01
In this paper, a theory of quantum logics is proposed which is general enough to enable us to reexamine a previous work on quantum logics in the context of this theory. It is then easy to assess the differences between the different systems studied. The quantum logical systems which are incorporated are divided into two groups which we call ''quantum propositional logics'' and ''quantum event logics''. The work of Kochen and Specker (partial Boolean algebras) is included and so is that of Greechie and Gudder (orthomodular partially ordered sets), Domotar (quantum mechanical systems), and Foulis and Randall (operational logics) in quantum propositional logics; and Abbott (semi-Boolean algebras) and Foulis and Randall (manuals) in quantum event logics, In this part of the paper, an axiom system for quantum propositional logics is developed and the above structures in the context of this system examined. (author)
Divide and control: split design of multi-input DNA logic gates.
Gerasimova, Yulia V; Kolpashchikov, Dmitry M
2015-01-18
Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.
DEFF Research Database (Denmark)
Schürmann, Carsten; Sarnat, Jeffrey
2008-01-01
Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics......, such as Twelf, and yet they are often straightforward in proof assistants with stronger meta-logics. In this paper, we propose structural logical relations as a technique for conducting these proofs in systems with limited meta-logical strength by explicitly representing and reasoning about an auxiliary logic...
DEFF Research Database (Denmark)
Berg Johansen, Christina; Waldorff, Susanne Boch
This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...
Indeterministic Temporal Logic
Directory of Open Access Journals (Sweden)
Trzęsicki Kazimierz
2015-09-01
Full Text Available The questions od determinism, causality, and freedom have been the main philosophical problems debated since the beginning of temporal logic. The issue of the logical value of sentences about the future was stated by Aristotle in the famous tomorrow sea-battle passage. The question has inspired Łukasiewicz’s idea of many-valued logics and was a motive of A. N. Prior’s considerations about the logic of tenses. In the scheme of temporal logic there are different solutions to the problem. In the paper we consider indeterministic temporal logic based on the idea of temporal worlds and the relation of accessibility between them.
Electronics circuits and systems
Bishop, Owen
2007-01-01
The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set
Electronics circuits and systems
Bishop, Owen
2011-01-01
The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea
Heuristic Synthesis of Reversible Logic – A Comparative Study
Directory of Open Access Journals (Sweden)
Chua Shin Cheng
2014-01-01
Full Text Available Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based. All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.
Quantum Logic as a Dynamic Logic
Baltag, A.; Smets, S.
We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear “no”.
Quantum logic as a dynamic logic
Baltag, Alexandru; Smets, Sonja
We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear "no".
Transforming equality logic to propositional logic
Zantema, H.; Groote, J.F.
2003-01-01
Abstract We investigate and compare various ways of transforming equality formulas to propositional formulas, in order to be able to solve satisfiability in equality logic by means of satisfiability in propositional logic. We propose equality substitution as a new approach combining desirable
Designing Novel Quaternary Quantum Reversible Subtractor Circuits
Haghparast, Majid; Monfared, Asma Taheri
2018-01-01
Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.
Bolc, Leonard
1992-01-01
Many-valued logics were developed as an attempt to handle philosophical doubts about the "law of excluded middle" in classical logic. The first many-valued formal systems were developed by J. Lukasiewicz in Poland and E.Post in the U.S.A. in the 1920s, and since then the field has expanded dramatically as the applicability of the systems to other philosophical and semantic problems was recognized. Intuitionisticlogic, for example, arose from deep problems in the foundations of mathematics. Fuzzy logics, approximation logics, and probability logics all address questions that classical logic alone cannot answer. All these interpretations of many-valued calculi motivate specific formal systems thatallow detailed mathematical treatment. In this volume, the authors are concerned with finite-valued logics, and especially with three-valued logical calculi. Matrix constructions, axiomatizations of propositional and predicate calculi, syntax, semantic structures, and methodology are discussed. Separate chapters deal w...
Directory of Open Access Journals (Sweden)
P N Johnson-Laird
2010-10-01
Full Text Available An old view in logic going back to Aristotle is that an inference is valid in virtue of its logical form. Many psychologists have adopted the same point of view about human reasoning: the first step is to recover the logical form of an inference, and the second step is to apply rules of inference that match these forms in order to prove that the conclusion follows from the premises. The present paper argues against this idea. The logical form of an inference transcends the grammatical forms of the sentences used to express it, because logical form also depends on context. Context is not readily expressed in additional premises. And the recovery of logical form leads ineluctably to the need for infinitely many axioms to capture the logical properties of relations. An alternative theory is that reasoning depends on mental models, and this theory obviates the need to recover logical form.
Newton-Smith, WH
2003-01-01
A complete introduction to logic for first-year university students with no background in logic, philosophy or mathematics. In easily understood steps it shows the mechanics of the formal analysis of arguments.
High-speed dynamic domino circuit implemented with gaas mesfets
Yang, Long (Inventor); Long, Stephen I. (Inventor)
1990-01-01
A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.
Universal programmable logic gate and routing method
Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)
2009-01-01
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Connections among quantum logics
International Nuclear Information System (INIS)
Lock, P.F.; Hardegree, G.M.
1985-01-01
This paper gives a brief introduction to the major areas of work in quantum event logics: manuals (Foulis and Randall) and semi-Boolean algebras (Abbott). The two theories are compared, and the connection between quantum event logics and quantum propositional logics is made explicit. In addition, the work on manuals provides us with many examples of results stated in Part I. (author)
Manca, V.; Salibra, A.; Scollo, Giuseppe
1990-01-01
Equational type logic is an extension of (conditional) equational logic, that enables one to deal in a single, unified framework with diverse phenomena such as partiality, type polymorphism and dependent types. In this logic, terms may denote types as well as elements, and atomic formulae are either
DEFF Research Database (Denmark)
Xue, Bingtian; Larsen, Kim Guldstrand; Mardare, Radu Iulian
2015-01-01
We introduce Concurrent Weighted Logic (CWL), a multimodal logic for concurrent labeled weighted transition systems (LWSs). The synchronization of LWSs is described using dedicated functions that, in various concurrency paradigms, allow us to encode the compositionality of LWSs. To reflect these......-completeness results for this logic. To complete these proofs we involve advanced topological techniques from Model Theory....
Bergstra, J.A.
2011-01-01
Four options for assigning a meaning to Islamic Logic are surveyed including a new proposal for an option named "Real Islamic Logic" (RIL). That approach to Islamic Logic should serve modern Islamic objectives in a way comparable to the functionality of Islamic Finance. The prospective role of RIL
DEFF Research Database (Denmark)
Christiansen, Henning; Dahl, Veronica
2009-01-01
By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting....... We formalize these ideas, and exemplify them both within and outside first-order logic, and for both fixed and dynamic knowledge bases. Within the latter variety, we consider the usual left-to-right derivations that are traditional in logic grammars, but also -- in a significant departure from...
DEFF Research Database (Denmark)
Bentzen, Martin Mose
2014-01-01
A new deontic logic, Action Type Deontic Logic, is presented. To motivate this logic, a number of benchmark cases are shown, representing inferences a deontic logic should validate. Some of the benchmark cases are singled out for further comments and some formal approaches to deontic reasoning...... are evaluated with respect to the benchmark cases. After that follows an informal introduction to the ideas behind the formal semantics, focussing on the distinction between action types and action tokens. Then the syntax and semantics of Action Type Deontic Logic is presented and it is shown to meet...
Czech Academy of Sciences Publication Activity Database
Horčík, Rostislav; Cintula, Petr
2004-01-01
Roč. 43, - (2004), s. 477-503 ISSN 1432-0665 R&D Projects: GA AV ČR IAA1030004; GA ČR GA201/02/1540 Grant - others:GA CTU(CZ) project 0208613; net CEEPUS(SK) SK-042 Institutional research plan: CEZ:AV0Z1030915 Keywords : fuzzy logic * many-valued logic * Lukasiewicz logic * Lpi logic * Takeuti-Titani logic * MV-algebras * product MV-algebras Subject RIV: BA - General Mathematics Impact factor: 0.295, year: 2004
Resonance circuits for adiabatic circuits
Directory of Open Access Journals (Sweden)
C. Schlachta
2003-01-01
Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.
Logic verification system for power plant sequence diagrams
International Nuclear Information System (INIS)
Fukuda, Mitsuko; Yamada, Naoyuki; Teshima, Toshiaki; Kan, Ken-ichi; Utsunomiya, Mitsugu.
1994-01-01
A logic verification system for sequence diagrams of power plants has been developed. The system's main function is to verify correctness of the logic realized by sequence diagrams for power plant control systems. The verification is based on a symbolic comparison of the logic of the sequence diagrams with the logic of the corresponding IBDs (interlock Block Diagrams) in combination with reference to design knowledge. The developed system points out the sub-circuit which is responsible for any existing mismatches between the IBD logic and the logic realized by the sequence diagrams. Applications to the verification of actual sequence diagrams of power plants confirmed that the developed system is practical and effective. (author)
Logic in the curricula of Computer Science
Directory of Open Access Journals (Sweden)
Margareth Quindeless
2014-12-01
Full Text Available The aim of the programs in Computer Science is to educate and train students to understand the problems and build systems that solve them. This process involves applying a special reasoning to model interactions, capabilities, and limitations of the components involved. A good curriculum must involve the use of tools to assist in these tasks, and one that could be considered as a fundamental is the logic, because with it students develop the necessary reasoning. Besides, software developers analyze the behavior of the program during the designed, the depuration, and testing; hardware designers perform minimization and equivalence verification of circuits; designers of operating systems validate routing protocols, programing, and synchronization; and formal logic underlying all these activities. Therefore, a strong background in applied logic would help students to develop or potentiate their ability to reason about complex systems. Unfortunately, few curricula formed and properly trained in logic. Most includes only one or two courses of Discrete Mathematics, which in a few weeks covered truth tables and the propositional calculus, and nothing more. This is not enough, and higher level courses in which they are applied and many other logical concepts are needed. In addition, students will not see the importance of logic in their careers and need to modify the curriculum committees or adapt the curriculum to reverse this situation.
Instantons in Self-Organizing Logic Gates
Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano
2018-03-01
Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.
DEFF Research Database (Denmark)
Blackburn, Patrick Rowan; Huertas, Antonia; Manzano, Maria
2014-01-01
Leon Henkin was not a modal logician, but there is a branch of modal logic that has been deeply influenced by his work. That branch is hybrid logic, a family of logics that extend orthodox modal logic with special proposition symbols (called nominals) that name worlds. This paper explains why...... Henkin’s techniques are so important in hybrid logic. We do so by proving a completeness result for a hybrid type theory called HTT, probably the strongest hybrid logic that has yet been explored. Our completeness result builds on earlier work with a system called BHTT, or basic hybrid type theory...... is due to the first-order perspective, which lies at the heart of Henin’s best known work and hybrid logic....
Directory of Open Access Journals (Sweden)
Newton C. A. da Costa
2002-12-01
Full Text Available In view of the present state of development of non classical logic, especially of paraconsistent logic, a new stand regarding the relations between logic and ontology is defended In a parody of a dictum of Quine, my stand May be summarized as follows. To be is to be the value of a variable a specific language with a given underlying logic Yet my stand differs from Quine’s, because, among other reasons, I accept some first order heterodox logics as genuine alternatives to classical logic I also discuss some questions of non classical logic to substantiate my argument, and suggest that may position complements and extends some ideas advanced by L Apostel.
Institutional Logics in Action
DEFF Research Database (Denmark)
Lounsbury, Michael; Boxenbaum, Eva
2013-01-01
This double volume presents state-of-the-art research and thinking on the dynamics of actors and institutional logics. In the introduction, we briefly sketch the roots and branches of institutional logics scholarship before turning to the new buds of research on the topic of how actors engage...... institutional logics in the course of their organizational practice. We introduce an exciting line of new works on the meta-theoretical foundations of logics, institutional logic processes, and institutional complexity and organizational responses. Collectively, the papers in this volume advance the very...... prolific stream of research on institutional logics by deepening our insight into the active use of institutional logics in organizational action and interaction, including the institutional effects of such (inter)actions....
A Relational Account of Call-by-Value Sequentiality
DEFF Research Database (Denmark)
Riecke, Jon Gary; Sandholm, Anders Bo
2002-01-01
We construct a model for FPC, a purely functional, sequential, call-by-value language. The model is built from partial continuous functions, in the style of Plotkin, further constrained to be uniform with respect to a class of logical relations. We prove that the model is fully abstract....
Electronic circuit encyclopedia 2
International Nuclear Information System (INIS)
Park, Sun Ho
1992-10-01
This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.
Electronic circuit encyclopedia 2
Energy Technology Data Exchange (ETDEWEB)
Park, Sun Ho
1992-10-15
This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.
Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices
Directory of Open Access Journals (Sweden)
Tautvydas Brukštus
2016-06-01
Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.
Microcontroller based Integrated Circuit Tester
Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi
2015-01-01
The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...
Plastic Logic quits e-reader market
Perks, Simon
2012-07-01
A UK firm spun out from the University of Cambridge that sought to be a world leader in flexible organic electronic circuits and displays has pulled out of the competitive e-reader market as it struggles to find a commercial outlet for its technology. Plastic Logic announced in May that it is to close its development facility in Mountain View, California, with the loss of around 40 jobs.
"Glitch Logic" and Applications to Computing and Information Security
Stoica, Adrian; Katkoori, Srinivas
2009-01-01
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
Unbalanced neuronal circuits in addiction.
Volkow, Nora D; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D
2013-08-01
Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it. Published by Elsevier Ltd.
Reliability concerns with logical constants in Xilinx FPGA designs
Energy Technology Data Exchange (ETDEWEB)
Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX
2009-01-01
In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.
Dalen, Dirk
1983-01-01
A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...
Directory of Open Access Journals (Sweden)
Schang Fabien
2017-03-01
Full Text Available An analogy is made between two rather different domains, namely: logic, and football (or soccer. Starting from a comparative table between the two activities, an alternative explanation of logic is given in terms of players, ball, goal, and the like. Our main thesis is that, just as the task of logic is preserving truth from premises to the conclusion, footballers strive to keep the ball as far as possible until the opposite goal. Assuming this analogy may help think about logic in the same way as in dialogical logic, but it should also present truth-values in an alternative sense of speech-acts occurring in a dialogue. The relativity of truth-values is focused by this way, thereby leading to an additional way of logical pluralism.
International Nuclear Information System (INIS)
Wall, M.J.W.
1992-01-01
The notion of open-quotes probabilityclose quotes is generalized to that of open-quotes likelihood,close quotes and a natural logical structure is shown to exist for any physical theory which predicts likelihoods. Two physically based axioms are given for this logical structure to form an orthomodular poset, with an order-determining set of states. The results strengthen the basis of the quantum logic approach to axiomatic quantum theory. 25 refs
Logical database design principles
Garmany, John; Clark, Terry
2005-01-01
INTRODUCTION TO LOGICAL DATABASE DESIGNUnderstanding a Database Database Architectures Relational Databases Creating the Database System Development Life Cycle (SDLC)Systems Planning: Assessment and Feasibility System Analysis: RequirementsSystem Analysis: Requirements Checklist Models Tracking and Schedules Design Modeling Functional Decomposition DiagramData Flow Diagrams Data Dictionary Logical Structures and Decision Trees System Design: LogicalSYSTEM DESIGN AND IMPLEMENTATION The ER ApproachEntities and Entity Types Attribute Domains AttributesSet-Valued AttributesWeak Entities Constraint
Czech Academy of Sciences Publication Activity Database
Peliš, Michal
2017-01-01
Roč. 26, č. 3 (2017), s. 357-381 ISSN 1425-3305 R&D Projects: GA ČR(CZ) GC16-07954J Institutional support: RVO:67985955 Keywords : epistemic logic * erotetic implication * erotetic logic * logic of questions Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology http://apcz.umk.pl/czasopisma/index.php/LLP/article/view/LLP.2017.007
Pereyra, Nicolas A.
2018-06-01
This book gives a rigorous yet 'physics-focused' introduction to mathematical logic that is geared towards natural science majors. We present the science major with a robust introduction to logic, focusing on the specific knowledge and skills that will unavoidably be needed in calculus topics and natural science topics in general (rather than taking a philosophical-math-fundamental oriented approach that is commonly found in mathematical logic textbooks).
Crossley, J N; Brickhill, CJ; Stillwell, JC
2010-01-01
Although mathematical logic can be a formidably abstruse topic, even for mathematicians, this concise book presents the subject in a lively and approachable fashion. It deals with the very important ideas in modern mathematical logic without the detailed mathematical work required of those with a professional interest in logic.The book begins with a historical survey of the development of mathematical logic from two parallel streams: formal deduction, which originated with Aristotle, Euclid, and others; and mathematical analysis, which dates back to Archimedes in the same era. The streams beg
DEFF Research Database (Denmark)
Blackburn, Patrick Rowan; Jørgensen, Klaus Frovin
2012-01-01
In this paper we explore the logic of now, yesterday, today and tomorrow by combining the semantic approach to indexicality pioneered by Hans Kamp [9] and refined by David Kaplan [10] with hybrid tense logic. We first introduce a special now nominal (our @now corresponds to Kamp’s original now...... operator N) and prove completeness results for both logical and contextual validity. We then add propositional constants to handle yesterday, today and tomorrow; our system correctly treats sentences like “Niels will die yesterday” as contextually unsatisfiable. Building on our completeness results for now......, we prove completeness for the richer language, again for both logical and contextual validity....
DEFF Research Database (Denmark)
Lopez, Hugo Andres; Carbone, Marco; Hildebrandt, Thomas
2010-01-01
We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for speciﬁcation and veriﬁcation of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL...... ), a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service speciﬁcations. Finally, we show that, despite GL is undecidable, there is a signiﬁcant decidable fragment which we provide with a sound and complete proof...
International Nuclear Information System (INIS)
Andronov, A.A.; Kurin, V.V.; Levichev, M.Yu.; Ryndyk, D.A.; Vostokov, V.I.
1993-01-01
In recent years there has been much interest in superconductor logical devices. Our paper is devoted to the analysis of some new possibilities in this field. The main problems here are: minimization of time of logical operations and reducing of device scale. Josephson systems are quite appropriate for this purpose because of small size, short characteristic time and also small energy losses. Two different types of Josephson logic have been investigated during last years. The first type is based on hysteretic V-A characteristic of a single Josephson junction. Superconducting and resistive (with nonzero voltage) states are considered as logical zero and logical unit. The second one - rapid single flux quantum logic, has been developed recently and is based on SQUID-like bistability. Different logical states are the states with different number of magnetic flux quanta inside closed superconducting contour. Information is represented by voltage pulses with fixed ''area'' (∫ V(t)/dt). This pulses are generated when logical state of SQUID-like elementary cell changes. The fundamental role of magnetic flux quantization in this type of logic leads to the necessity of large enough self-inductance of superconductor contour and thus to limitations on minimal device dimensions. (orig.)
Directory of Open Access Journals (Sweden)
Marco Carbone
2011-10-01
Full Text Available We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL, a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof system for checking validity of formulae.
Introduction to mathematical logic
Mendelson, Elliott
2015-01-01
The new edition of this classic textbook, Introduction to Mathematical Logic, Sixth Edition explores the principal topics of mathematical logic. It covers propositional logic, first-order logic, first-order number theory, axiomatic set theory, and the theory of computability. The text also discusses the major results of Gödel, Church, Kleene, Rosser, and Turing.The sixth edition incorporates recent work on Gödel's second incompleteness theorem as well as restoring an appendix on consistency proofs for first-order arithmetic. This appendix last appeared in the first edition. It is offered in th
Design of reconfigurable logic controllers
Bukowiec, Arkadiusz; Doligalski, Michał; Tkacz, Jacek
2016-01-01
This book presents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the recon...
Integrated-Circuit Controller For Brushless dc Motor
Le, Dong Tuan
1994-01-01
Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.
Understanding Social Media Logic
Directory of Open Access Journals (Sweden)
José van Dijck
2013-08-01
Full Text Available Over the past decade, social media platforms have penetrated deeply into the mechanics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpinning its dynamics. This logic will be considered in light of what has been identified as mass media logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmability, popularity, connectivity, and datafication—and argue that these principles become increasingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance existing mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relatively simple to identify, but it is much harder to map the complex connections between platforms that distribute this logic: users that employ them, technologies that
Wiring of electronic evaluation circuits
International Nuclear Information System (INIS)
Bauer, R.; Svoboda, Z.
1977-01-01
The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)
Radiation damage to integrated injection logic cells
International Nuclear Information System (INIS)
Pease, R.L.; Galloway, K.F.; Stehlin, R.A.
1975-01-01
The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (l 2 L) cell and an l 2 L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED
Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao
2011-01-01
Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...
Weakly Intuitionistic Quantum Logic
Hermens, Ronnie
2013-01-01
In this article von Neumann's proposal that in quantum mechanics projections can be seen as propositions is followed. However, the quantum logic derived by Birkhoff and von Neumann is rejected due to the failure of the law of distributivity. The options for constructing a distributive logic while
Kuusisto, Antti
2013-01-01
In recent years, research into the mathematical foundations of modal logic has become increasingly popular. One of the main reasons for this is the fact that modal logic seems to adapt well to the requirements of a wide range of different fields of application. This paper is a summary of some of the author’s contributions to the understanding of modal definability theory.
Cirstea, C.; Kurz, A.; Pattinson, D.; Schröder, L.; Venema, Y.
2011-01-01
Applications of modal logics are abundant in computer science, and a large number of structurally different modal logics have been successfully employed in a diverse spectrum of application contexts. Coalgebraic semantics, on the other hand, provides a uniform and encompassing view on the large
CSIR Research Space (South Africa)
Klarman, S
2013-05-01
Full Text Available We introduce Description Logics of Context (DLCs) - an extension of Description Logics (DLs) for context-based reasoning. Our approach descends from J. McCarthy's tradition of treating contexts as formal objects over which one can quantify...
Criteria for logical formalization
Czech Academy of Sciences Publication Activity Database
Peregrin, Jaroslav; Svoboda, Vladimír
2013-01-01
Roč. 190, č. 14 (2013), s. 2897-2924 ISSN 0039-7857 R&D Projects: GA ČR(CZ) GAP401/10/1279 Institutional support: RVO:67985955 Keywords : logic * logical form * formalization * reflective equilibrium Subject RIV: AA - Philosophy ; Religion Impact factor: 0.637, year: 2013
NEVEN, Frank
2002-01-01
We survey some recent developments in the broad area of automata and logic which are motivated by the advent of XML. In particular, we consider unranked tree automata, tree-walking automata, and automata over infinite alphabets. We focus on their connection with logic and on questions imposed by XML.
Directory of Open Access Journals (Sweden)
Evandro Agazzi
2011-06-01
Full Text Available Humans have used arguments for defending or refuting statements long before the creation of logic as a specialized discipline. This can be interpreted as the fact that an intuitive notion of "logical consequence" or a psychic disposition to articulate reasoning according to this pattern is present in common sense, and logic simply aims at describing and codifying the features of this spontaneous capacity of human reason. It is well known, however, that several arguments easily accepted by common sense are actually "logical fallacies", and this indicates that logic is not just a descriptive, but also a prescriptive or normative enterprise, in which the notion of logical consequence is defined in a precise way and then certain rules are established in order to maintain the discourse in keeping with this notion. Yet in the justification of the correctness and adequacy of these rules commonsense reasoning must necessarily be used, and in such a way its foundational role is recognized. Moreover, it remains also true that several branches and forms of logic have been elaborated precisely in order to reflect the structural features of correct argument used in different fields of human reasoning and yet insufficiently mirrored by the most familiar logical formalisms.
A. Ponse (Alban); M.B. van der Zwaag
2002-01-01
textabstractWe distinguish two interpretations for the truth value `undefined' in Kleene's three-valued logic. Combining these two interpretations leads to a four-valued propositional logic that characterizes two particular ingredients of process algebra: ``choice' and ``inaction'. We study two
Uckelman, S.L.
2009-01-01
The origins of treating agency as a modal concept go back at least to the 11th century when Anselm, Archbishop of Canterbury, provided a modal explication of the Latin facere ‘to do’, which can be formalized within the context of modern modal logic and neighborhood semantics. The agentive logic
Temporalized Epistemic Default Logic
van der Hoek, W.; Meyer, J.J.; Treur, J.; Gabbay, D.
2001-01-01
The nonmonotonic logic Epistemic Default Logic (EDL) [Meyer and van der Hoek, 1993] is based on the metaphore of a meta-level architecture. It has already been established [Meyer and van der Hoek, 1993] how upward reflection can be formalized by a nonmonotonic entailment based on epistemic states,
Lopez, Antonio M., Jr.
1989-01-01
Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)
Microelectromechanical reprogrammable logic device
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-01-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295
Heterogeneous logics of competition
DEFF Research Database (Denmark)
Mossin, Christiane
2015-01-01
of competition are only realized as particular forms of social organization by virtue of interplaying with other kinds of logics, like legal logics. (2) Competition logics enjoy a peculiar status in-between constructedness and givenness; although competition depends on laws and mechanisms of socialization, we...... still experience competition as an expression of spontaneous human activities. On the basis of these perspectives, a study of fundamental rights of EU law, springing from the principle of ‘free movement of people’, is conducted. The first part of the empirical analysis seeks to detect the presence...... of a presumed logic of competition within EU law, whereas the second part focuses on particular legal logics. In this respect, the so-called ‘real link criterion’ (determining the access to transnational social rights for certain groups of unemployed people) is given special attention. What is particularly...
Microelectromechanical reprogrammable logic device
Hafiz, Md Abdullah Al
2016-03-29
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.
Sequential charged particle reaction
International Nuclear Information System (INIS)
Hori, Jun-ichi; Ochiai, Kentaro; Sato, Satoshi; Yamauchi, Michinori; Nishitani, Takeo
2004-01-01
The effective cross sections for producing the sequential reaction products in F82H, pure vanadium and LiF with respect to the 14.9-MeV neutron were obtained and compared with the estimation ones. Since the sequential reactions depend on the secondary charged particles behavior, the effective cross sections are corresponding to the target nuclei and the material composition. The effective cross sections were also estimated by using the EAF-libraries and compared with the experimental ones. There were large discrepancies between estimated and experimental values. Additionally, we showed the contribution of the sequential reaction on the induced activity and dose rate in the boundary region with water. From the present study, it has been clarified that the sequential reactions are of great importance to evaluate the dose rates around the surface of cooling pipe and the activated corrosion products. (author)
Optimized 4-bit Quantum Reversible Arithmetic Logic Unit
Ayyoub, Slimani; Achour, Benslama
2017-08-01
Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.
Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar
2012-12-26
The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.
Complex cellular logic computation using ribocomputing devices.
Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng
2017-08-03
Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.
Modeling a verification test system for mixed-signal circuits
San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.
In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block
Monolithic microwave integrated circuit with integral array antenna
International Nuclear Information System (INIS)
Stockton, R.J.; Munson, R.E.
1984-01-01
A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence
DEFF Research Database (Denmark)
2010-01-01
A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...
Nelson, Jane B.
1998-01-01
Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)
International Nuclear Information System (INIS)
Mittelstaedt, P.
1983-01-01
on the basis of the well-known quantum logic and quantum probability a formal language of relativistic quantum physics is developed. This language incorporates quantum logical as well as relativistic restrictions. It is shown that relativity imposes serious restrictions on the validity regions of propositions in space-time. By an additional postulate this relativistic quantum logic can be made consistent. The results of this paper are derived exclusively within the formal quantum language; they are, however, in accordance with well-known facts of relativistic quantum physics in Hilbert space. (author)
International Nuclear Information System (INIS)
Finkelstein, D.
1987-01-01
The von Neumann quantum logic lacks two basic symmetries of classical logic, that between sets and classes, and that between lower and higher order predicates. Similarly, the structural parallel between the set algebra and linear algebra of Grassmann and Peano was left incomplete by them in two respects. In this work a linear algebra is constructed that completes this correspondence and is interpreted as a new quantum logic that restores these invariances, and as a quantum set theory. It applies to experiments with coherent quantum phase relations between the quantum and the apparatus. The quantum set theory is applied to model a Lorentz-invariant quantum time-space complex
Logical inference and evaluation
International Nuclear Information System (INIS)
Perey, F.G.
1981-01-01
Most methodologies of evaluation currently used are based upon the theory of statistical inference. It is generally perceived that this theory is not capable of dealing satisfactorily with what are called systematic errors. Theories of logical inference should be capable of treating all of the information available, including that not involving frequency data. A theory of logical inference is presented as an extension of deductive logic via the concept of plausibility and the application of group theory. Some conclusions, based upon the application of this theory to evaluation of data, are also given
DEFF Research Database (Denmark)
Filipiuk, Piotr; Nielson, Flemming; Nielson, Hanne Riis
2012-01-01
We present a logic for the specification of static analysis problems that goes beyond the logics traditionally used. Its most prominent feature is the direct support for both inductive computations of behaviors as well as co-inductive specifications of properties. Two main theoretical contributions...... are a Moore Family result and a parametrized worst case time complexity result. We show that the logic and the associated solver can be used for rapid prototyping of analyses and illustrate a wide variety of applications within Static Analysis, Constraint Satisfaction Problems and Model Checking. In all cases...
International Nuclear Information System (INIS)
Bialkowski, J.; Moszynski, M.; Zagorski, A.
1981-01-01
The logic diagram principle of operation and some details of the design of the multiplicity logic unit are presented. This unit was specially designed to fulfil the requirements of a multidetector arrangement for gamma-ray multiplicity measurements. The unit is equipped with 16 inputs controlled by a common coincidence gate. It delivers a linear output pulse with the height proportional to the multiplicity of coincidences and logic pulses corresponding to 0, 1, ... up to >= 5-fold coincidences. These last outputs are used to steer the routing unit working with the multichannel analyser. (orig.)
Synchronization circuit for shaping electron beam picosecond pulses
International Nuclear Information System (INIS)
Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.
1985-01-01
A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes
Single-flux-quantum circuit technology for superconducting radiation detectors
International Nuclear Information System (INIS)
Fujimaki, Akira; Onogi, Masashi; Matsumoto, Tomohiro; Tanaka, Masamitsu; Sekiya, Akito; Hayakawa, Hisao; Yorozu, Shinichi; Terai, Hirotaka; Yoshikawa, Nobuyuki
2003-01-01
We discuss the application of the single-flux-quantum (SFQ) logic circuits to multi superconducting radiation detectors system. The SFQ-based analog-to-digital converters (ADCs) have the advantage in current sensitivity, which can reach less than 10 nA in a well-tuned ADC. We have also developed the design technology of the SFQ circuits. We demonstrate high-speed operation of large-scale integrated circuits such as a 2x2 cross/bar switch, arithmetic logic unit, indicating that our present SFQ technology is applicable to the multi radiation detectors system. (author)
Learning sequential control in a Neural Blackboard Architecture for in situ concept reasoning
van der Velde, Frank; van der Velde, Frank; Besold, Tarek R.; Lamb, Luis; Serafini, Luciano; Tabor, Whitney
2016-01-01
Simulations are presented and discussed of learning sequential control in a Neural Blackboard Architecture (NBA) for in situ concept-based reasoning. Sequential control is learned in a reservoir network, consisting of columns with neural circuits. This allows the reservoir to control the dynamics of
DMILL circuits. The hardened electronics decuples its performances
International Nuclear Information System (INIS)
Anon.
1998-01-01
Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)
Fisher, Michael; Gabbay, Dov; Gough, Graham
2000-01-01
Time is a fascinating subject that has captured mankind's imagination from ancient times to the present. It has been, and continues to be studied across a wide range of disciplines, from the natural sciences to philosophy and logic. More than two decades ago, Pnueli in a seminal work showed the value of temporal logic in the specification and verification of computer programs. Today, a strong, vibrant international research community exists in the broad community of computer science and AI. This volume presents a number of articles from leading researchers containing state-of-the-art results in such areas as pure temporal/modal logic, specification and verification, temporal databases, temporal aspects in AI, tense and aspect in natural language, and temporal theorem proving. Earlier versions of some of the articles were given at the most recent International Conference on Temporal Logic, University of Manchester, UK. Readership: Any student of the area - postgraduate, postdoctoral or even research professor ...
DEFF Research Database (Denmark)
Hendricks, Vincent Fella; Gierasimczuk, Nina; de Jong, Dick
2014-01-01
Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study of inform......Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study...... of information processing, but likewise helped bring logic and learning in close proximity. This proximity relation is examined with respect to learning and belief revision, updating and efficiency, and with respect to how learnability fits in the greater scheme of dynamic epistemic logic and scientific method....
Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture
Perkowski, M.A.; Foote, D.; Chen, Qihong; Al-Rabadi, A.; Jozwiak, L.
2002-01-01
For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design
A Web-Based Visualization and Animation Platform for Digital Logic Design
Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.
2015-01-01
This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…
Fail-safe logic elements for use with reactor safety systems
International Nuclear Information System (INIS)
Bobis, J.P.; McDowell, W.P.
1976-01-01
A complete fail-safe trip circuit is described which utilizes fail-safe logic elements. The logic elements used are analog multipliers and active bandpass filter networks. These elements perform Boolean operations on a set of AC signals from the output of a reactor safety-channel trip comparator
A single nano cantilever as a reprogrammable universal logic gate
Chappanda, K. N.
2017-02-24
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.
A single nano cantilever as a reprogrammable universal logic gate
International Nuclear Information System (INIS)
Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J
2017-01-01
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)
Characterization of quantum logics
International Nuclear Information System (INIS)
Lahti, P.J.
1980-01-01
The quantum logic approach to axiomatic quantum mechanics is used to analyze the conceptual foundations of the traditional quantum theory. The universal quantum of action h>0 is incorporated into the theory by introducing the uncertainty principle, the complementarity principle, and the superposition principle into the framework. A characterization of those quantum logics (L,S) which may provide quantum descriptions is then given. (author)
DEFF Research Database (Denmark)
Nilsson, Jørgen Fischer
1999-01-01
Conceptual spaces have been proposed as topological or geometric means for establishing conceptual structures and models. This paper, after briey reviewing conceptual spaces, focusses on the relationship between conceptual spaces and logical concept languages with operations for combining concepts...... to form concepts. Speci cally is introduced an algebraic concept logic, for which conceptual spaces are installed as semantic domain as replacement for, or enrichment of, the traditional....
Extending Value Logic Thinking to Value Logic Portfolios
DEFF Research Database (Denmark)
Andersen, Poul Houman; Ritter, Thomas
2014-01-01
Based on value creation logic theory (Stabell & Fjeldstad, 1998), this paper suggests an extension of the original Stabell & Fjeldstad model by an additional fourth value logic, the value system logic. Furthermore, instead of only allowing one dominant value creation logic for a given firm...... or transaction, an understanding of firms and transactions as a portfolio of value logics (i.e. an interconnected coexistence of different value creation logics) is proposed. These additions to the original value creation logic theory imply interesting avenues for both, strategic decision making in firms...
Towards a Formal Occurrence Logic based on Predicate Logic
DEFF Research Database (Denmark)
Badie, Farshad; Götzsche, Hans
2015-01-01
In this discussion we will concentrate on the main characteristics of an alternative kind of logic invented by Hans Götzsche: Occurrence Logic, which is not based on truth functionality. Our approach is based on temporal logic developed and elaborated by A. N. Prior. We will focus on characterising...... argumentation based on formal Occurrence Logic concerning events and occurrences, and illustrate the relations between Predicate Logic and Occurrence Logic. The relationships (and dependencies) is conducive to an approach that can analyse the occurrences of ”logical statements based on different logical...... principles” in different moments. We will also conclude that the elaborated Götzsche’s Occurrence Logic could be able to direct us to a truth-functional independent computer-based logic for analysing argumentation based on events and occurrences....
Sequential stochastic optimization
Cairoli, Renzo
1996-01-01
Sequential Stochastic Optimization provides mathematicians and applied researchers with a well-developed framework in which stochastic optimization problems can be formulated and solved. Offering much material that is either new or has never before appeared in book form, it lucidly presents a unified theory of optimal stopping and optimal sequential control of stochastic processes. This book has been carefully organized so that little prior knowledge of the subject is assumed; its only prerequisites are a standard graduate course in probability theory and some familiarity with discrete-paramet
Ghosh, Amal K.; Bhattacharya, Animesh; Raul, Moumita; Basuray, Amitabha
2012-07-01
Arithmetic logic unit (ALU) is the most important unit in any computing system. Optical computing is becoming popular day-by-day because of its ultrahigh processing speed and huge data handling capability. Obviously for the fast processing we need the optical TALU compatible with the multivalued logic. In this regard we are communicating the trinary arithmetic and logic unit (TALU) in modified trinary number (MTN) system, which is suitable for the optical computation and other applications in multivalued logic system. Here the savart plate and spatial light modulator (SLM) based optoelectronic circuits have been used to exploit the optical tree architecture (OTA) in optical interconnection network.
Modern logic and quantum mechanics
International Nuclear Information System (INIS)
Garden, R.W.
1984-01-01
The book applies the methods of modern logic and probabilities to ''interpreting'' quantum mechanics. The subject is described and discussed under the chapter headings: classical and quantum mechanics, modern logic, the propositional logic of mechanics, states and measurement in mechanics, the traditional analysis of probabilities, the probabilities of mechanics and the model logic of predictions. (U.K.)
Semantic theory for logic programming
Energy Technology Data Exchange (ETDEWEB)
Brown, F M
1981-01-01
The author axiomatizes a number of meta theoretic concepts which have been used in logic programming, including: meaning, logical truth, nonentailment, assertion and erasure, thus showing that these concepts are logical in nature and need not be defined as they have previously been defined in terms of the operations of any particular interpreter for logic programs. 10 references.
Relational Parametricity and Separation Logic
DEFF Research Database (Denmark)
Birkedal, Lars; Yang, Hongseok
2008-01-01
Separation logic is a recent extension of Hoare logic for reasoning about programs with references to shared mutable data structures. In this paper, we provide a new interpretation of the logic for a programming language with higher types. Our interpretation is based on Reynolds's relational...... parametricity, and it provides a formal connection between separation logic and data abstraction. Udgivelsesdato: 2008...
Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits
Directory of Open Access Journals (Sweden)
Michael S. Hsiao
2002-01-01
Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.
Self-clocked sequential circuits: - a design example | Aghdasi ...
African Journals Online (AJOL)
This paper uses a design methodology for the State variable toggling through data driven clocks to implement a Direct Memory Access Controller (DMAC) as a design example. The design is simulated on software and also implemented using discrete hardware components. The methodology can be extended to parallel ...
Sequential memory: Binding dynamics
Afraimovich, Valentin; Gong, Xue; Rabinovich, Mikhail
2015-10-01
Temporal order memories are critical for everyday animal and human functioning. Experiments and our own experience show that the binding or association of various features of an event together and the maintaining of multimodality events in sequential order are the key components of any sequential memories—episodic, semantic, working, etc. We study a robustness of binding sequential dynamics based on our previously introduced model in the form of generalized Lotka-Volterra equations. In the phase space of the model, there exists a multi-dimensional binding heteroclinic network consisting of saddle equilibrium points and heteroclinic trajectories joining them. We prove here the robustness of the binding sequential dynamics, i.e., the feasibility phenomenon for coupled heteroclinic networks: for each collection of successive heteroclinic trajectories inside the unified networks, there is an open set of initial points such that the trajectory going through each of them follows the prescribed collection staying in a small neighborhood of it. We show also that the symbolic complexity function of the system restricted to this neighborhood is a polynomial of degree L - 1, where L is the number of modalities.
Sequential Dependencies in Driving
Doshi, Anup; Tran, Cuong; Wilder, Matthew H.; Mozer, Michael C.; Trivedi, Mohan M.
2012-01-01
The effect of recent experience on current behavior has been studied extensively in simple laboratory tasks. We explore the nature of sequential effects in the more naturalistic setting of automobile driving. Driving is a safety-critical task in which delayed response times may have severe consequences. Using a realistic driving simulator, we find…
Mining compressing sequential problems
Hoang, T.L.; Mörchen, F.; Fradkin, D.; Calders, T.G.K.
2012-01-01
Compression based pattern mining has been successfully applied to many data mining tasks. We propose an approach based on the minimum description length principle to extract sequential patterns that compress a database of sequences well. We show that mining compressing patterns is NP-Hard and
Non-logic devices in logic processes
Ma, Yanjun
2017-01-01
This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes. Readers will benefit from the author’s extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.
Multi-valued LSI/VLSI logic design
Santrakul, K.
A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.
Electron commutator on integrated circuits
International Nuclear Information System (INIS)
Demidenko, V.V.
1975-01-01
The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru
Molecular logic gates: the past, present and future.
Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U
2018-04-03
The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.
Areces, Carlos; Hoffmann, Guillaume; Denis, Alexandre
We present a modal language that includes explicit operators to count the number of elements that a model might include in the extension of a formula, and we discuss how this logic has been previously investigated under different guises. We show that the language is related to graded modalities and to hybrid logics. We illustrate a possible application of the language to the treatment of plural objects and queries in natural language. We investigate the expressive power of this logic via bisimulations, discuss the complexity of its satisfiability problem, define a new reasoning task that retrieves the cardinality bound of the extension of a given input formula, and provide an algorithm to solve it.
Diagnosable structured logic array
Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)
2009-01-01
A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.
Carlsson, Christer; Fullér, Robert
2004-01-01
Fuzzy Logic in Management demonstrates that difficult problems and changes in the management environment can be more easily handled by bringing fuzzy logic into the practice of management. This explicit theme is developed through the book as follows: Chapter 1, "Management and Intelligent Support Technologies", is a short survey of management leadership and what can be gained from support technologies. Chapter 2, "Fuzzy Sets and Fuzzy Logic", provides a short introduction to fuzzy sets, fuzzy relations, the extension principle, fuzzy implications and linguistic variables. Chapter 3, "Group Decision Support Systems", deals with group decision making, and discusses methods for supporting the consensus reaching processes. Chapter 4, "Fuzzy Real Options for Strategic Planning", summarizes research where the fuzzy real options theory was implemented as a series of models. These models were thoroughly tested on a number of real life investments, and validated in 2001. Chapter 5, "Soft Computing Methods for Reducing...
DEFF Research Database (Denmark)
Mardare, Radu Iulian; Cardelli, Luca; Larsen, Kim Guldstrand
2012-01-01
Continuous Markovian Logic (CML) is a multimodal logic that expresses quantitative and qualitative properties of continuous-time labelled Markov processes with arbitrary (analytic) state-spaces, henceforth called continuous Markov processes (CMPs). The modalities of CML evaluate the rates...... of the exponentially distributed random variables that characterize the duration of the labeled transitions of a CMP. In this paper we present weak and strong complete axiomatizations for CML and prove a series of metaproperties, including the finite model property and the construction of canonical models. CML...... characterizes stochastic bisimilarity and it supports the definition of a quantified extension of the satisfiability relation that measures the "compatibility" between a model and a property. In this context, the metaproperties allows us to prove two robustness theorems for the logic stating that one can...
Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao
2017-04-25
Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.
Stoll, Robert R
1979-01-01
Set Theory and Logic is the result of a course of lectures for advanced undergraduates, developed at Oberlin College for the purpose of introducing students to the conceptual foundations of mathematics. Mathematics, specifically the real number system, is approached as a unity whose operations can be logically ordered through axioms. One of the most complex and essential of modern mathematical innovations, the theory of sets (crucial to quantum mechanics and other sciences), is introduced in a most careful concept manner, aiming for the maximum in clarity and stimulation for further study in
Introduction to mathematical logic
Mendelson, Elliott
2009-01-01
The Propositional CalculusPropositional Connectives. Truth TablesTautologies Adequate Sets of Connectives An Axiom System for the Propositional Calculus Independence. Many-Valued LogicsOther AxiomatizationsFirst-Order Logic and Model TheoryQuantifiersFirst-Order Languages and Their Interpretations. Satisfiability and Truth. ModelsFirst-Order TheoriesProperties of First-Order Theories Additional Metatheorems and Derived Rules Rule C Completeness Theorems First-Order Theories with EqualityDefinitions of New Function Letters and Individual Constants Prenex Normal Forms Isomorphism of Interpretati
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2011-01-01
We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML....... To guard against modelling artefacts we provide an alternative way of characterizing the policy combining algorithms and we formally prove the equivalence of these approaches. This allows us to pinpoint the shortcoming of previous approaches to formalization based either on Belnap logic or on D -algebra....
Evens, Aden
2015-01-01
Building a foundational understanding of the digital, Logic of the Digital reveals a unique digital ontology. Beginning from formal and technical characteristics, especially the binary code at the core of all digital technologies, Aden Evens traces the pathways along which the digital domain of abstract logic encounters the material, human world. How does a code using only 0s and 1s give rise to the vast range of applications and information that constitutes a great and growing portion of our world? Evens' analysis shows how any encounter between the actual and the digital must cross an ontolo
Short- circuit tests of circuit breakers
Chorovský, P.
2015-01-01
This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.
Indian Academy of Sciences (India)
andoh
Mechanism by which a nonlinear system embedded in a noisy environment ... we are increasingly encountering fundamental noise characteristics that cannot be .... Circuit is simple, robust, and capable of operating in very high frequency ...
Automatic design of digital synthetic gene circuits.
Directory of Open Access Journals (Sweden)
Mario A Marchisio
2011-02-01
Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.
Forced Sequence Sequential Decoding
DEFF Research Database (Denmark)
Jensen, Ole Riis
In this thesis we describe a new concatenated decoding scheme based on iterations between an inner sequentially decoded convolutional code of rate R=1/4 and memory M=23, and block interleaved outer Reed-Solomon codes with non-uniform profile. With this scheme decoding with good performance...... is possible as low as Eb/No=0.6 dB, which is about 1.7 dB below the signal-to-noise ratio that marks the cut-off rate for the convolutional code. This is possible since the iteration process provides the sequential decoders with side information that allows a smaller average load and minimizes the probability...... of computational overflow. Analytical results for the probability that the first Reed-Solomon word is decoded after C computations are presented. This is supported by simulation results that are also extended to other parameters....
Sequential Power-Dependence Theory
Buskens, Vincent; Rijt, Arnout van de
2008-01-01
Existing methods for predicting resource divisions in laboratory exchange networks do not take into account the sequential nature of the experimental setting. We extend network exchange theory by considering sequential exchange. We prove that Sequential Power-Dependence Theory—unlike
Modelling sequentially scored item responses
Akkermans, W.
2000-01-01
The sequential model can be used to describe the variable resulting from a sequential scoring process. In this paper two more item response models are investigated with respect to their suitability for sequential scoring: the partial credit model and the graded response model. The investigation is
Quantum logics with existence property
International Nuclear Information System (INIS)
Schindler, C.
1991-01-01
A quantum logic (σ-orthocomplete orthomodular poset L with a convex, unital, and separating set Δ of states) is said to have the existence property if the expectation functionals on lin(Δ) associated with the bounded observables of L form a vector space. Classical quantum logics as well as the Hilbert space logics of traditional quantum mechanics have this property. The author shows that, if a quantum logic satisfies certain conditions in addition to having property E, then the number of its blocks (maximal classical subsystems) must either be one (classical logics) or uncountable (as in Hilbert space logics)
GOAL Agents Instantiate Intention Logic
Hindriks, Koen; van der Hoek, Wiebe
2008-01-01
It is commonly believed there is a big gap between agent logics and computational agent frameworks. In this paper, we show that this gap is not as big as believed by showing that GOAL agents instantiate Intention Logic of Cohen and Levesque. That is, we show that GOAL agent programs can be formally related to Intention Logic.We do so by proving that the GOAL Verification Logic can be embedded into Intention Logic. It follows that (a fragment of) Intention Logic can be used t...
Querying Natural Logic Knowledge Bases
DEFF Research Database (Denmark)
Andreasen, Troels; Bulskov, Henrik; Jensen, Per Anker
2017-01-01
This paper describes the principles of a system applying natural logic as a knowledge base language. Natural logics are regimented fragments of natural language employing high level inference rules. We advocate the use of natural logic for knowledge bases dealing with querying of classes...... in ontologies and class-relationships such as are common in life-science descriptions. The paper adopts a version of natural logic with recursive restrictive clauses such as relative clauses and adnominal prepositional phrases. It includes passive as well as active voice sentences. We outline a prototype...... for partial translation of natural language into natural logic, featuring further querying and conceptual path finding in natural logic knowledge bases....
Forced Sequence Sequential Decoding
DEFF Research Database (Denmark)
Jensen, Ole Riis; Paaske, Erik
1998-01-01
We describe a new concatenated decoding scheme based on iterations between an inner sequentially decoded convolutional code of rate R=1/4 and memory M=23, and block interleaved outer Reed-Solomon (RS) codes with nonuniform profile. With this scheme decoding with good performance is possible as low...... as Eb/N0=0.6 dB, which is about 1.25 dB below the signal-to-noise ratio (SNR) that marks the cutoff rate for the full system. Accounting for about 0.45 dB due to the outer codes, sequential decoding takes place at about 1.7 dB below the SNR cutoff rate for the convolutional code. This is possible since...... the iteration process provides the sequential decoders with side information that allows a smaller average load and minimizes the probability of computational overflow. Analytical results for the probability that the first RS word is decoded after C computations are presented. These results are supported...
Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic
Ayala, Christopher Lawrence
Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using
Some relationships between logic programming and multiple-valued logic
International Nuclear Information System (INIS)
Rine, D.C.
1986-01-01
There have been suggestions in the artificial intelligence literature that investigations into relationships between logic programming and multiple-valued logic may be helpful. This paper presents some of these relationships through equivalent algebraic evaluations
Delay Insensitive Ternary CMOS Logic for Secure Hardware
Directory of Open Access Journals (Sweden)
Ravi S. P. Nair
2015-09-01
Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.
Guzman, R
2000-03-01
Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2014-01-01
We study the international standard XACML 3.0 for describing security access control policies in a compositional way. Our main contributions are (i) to derive a logic that precisely captures the intentions of the standard, (ii) to formally define a semantics for the XACML 3.0 component evaluation...
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2011-01-01
We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML...
Klev, Ansten Morch
2014-01-01
The notions of category and type are here studied through the lens of logical syntax: Aristotle's as well as Kant's categories through the traditional form of proposition `S is P', and modern doctrines of type through the Fregean form of proposition `F(a)', function applied to argument. Topics
Structures for Epistemic Logic
Bezhanishvili, N.; Hoek, W. van der
2013-01-01
Epistemic modal logic in a narrow sense studies and formalises reasoning about knowledge. In a wider sense, it gives a formal account of the informational attitude that agents may have, and covers notions like knowledge, belief, uncertainty, and hence incomplete or partial information. As is so
DEFF Research Database (Denmark)
Øhrstrøm, Peter
2009-01-01
's notion of branching time is analysed. It is argued that Prior can be criticized for identifying 'plain future'. Finally, Prior's four grades of tense-logical involvement are introduced and discussed. It is argued that the third grade is the most attractive form a philosophical point of view....
Expressivist Perspective on Logicality
Czech Academy of Sciences Publication Activity Database
Arazim, Pavel
2017-01-01
Roč. 11, č. 4 (2017), s. 409-419 ISSN 1661-8297 R&D Projects: GA ČR(CZ) GA17-15645S Institutional support: RVO:67985955 Keywords : logical constant * expressivism * topic-neutrality * proof- theory * conservativity Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology
DEFF Research Database (Denmark)
Jensen, Jonas Buhrkal; Birkedal, Lars
2012-01-01
, separation means physical separation. In this paper, we introduce \\emph{fictional separation logic}, which includes more general forms of fictional separating conjunctions P * Q, where "*" does not require physical separation, but may also be used in situations where the memory resources described by P and Q...
Czech Academy of Sciences Publication Activity Database
Klev, Ansten
2017-01-01
Roč. 25, č. 3 (2017), s. 341-368 ISSN 0031-8019 Institutional support: RVO:67985955 Keywords : Philosophy of mathematics * logicism * Richard Dedekind Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology Impact factor: 0.419, year: 2016
DEFF Research Database (Denmark)
Klose, Karl; Ostermann, Klaus
2010-01-01
In logic metaprogramming, programs are not stored as plain textfiles but rather derived from a deductive database. While the benefits of this approach for metaprogramming are obvious, its incompatibility with separate checking limits its applicability to large-scale projects. We analyze the probl...
LOGICAL SEMANTICS OF MODULARIZATION
DELAVALETTE, GRR
1992-01-01
An algebra of theories, signatures, renamings and the operations import and export is investigated. A normal form theorem for terms of this algebra is proved. Another algebraic approach and the relation with a fragment of second order logic are also considered.
Duration Calculus: Logical Foundations
DEFF Research Database (Denmark)
Hansen, Michael Reichhardt; Chaochen, Zhou
1997-01-01
The Duration Calculus (abbreviated DC) represents a logical approach to formal design of real-time systems, where real numbers are used to model time and Boolean valued functions over time are used to model states and events of real-time systems. Since it introduction, DC has been applied to many...
Logicism, intuitionism, and formalism
Symons, John
2008-01-01
Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.
Foundations of mathematical logic
Curry, Haskell B
2010-01-01
Written by a pioneer of mathematical logic, this comprehensive graduate-level text explores the constructive theory of first-order predicate calculus. It covers formal methods, including algorithms and epitheory, and offers a brief treatment of Markov's approach to algorithms, explains elementary facts about lattices and similar algebraic systems, and more. 1963 edition.
Czech Academy of Sciences Publication Activity Database
Svoboda, Vladimír; Peregrin, Jaroslav
2016-01-01
Roč. 30, č. 3 (2016), s. 263-287 ISSN 0920-427X R&D Projects: GA ČR(CZ) GA13-21076S Institutional support: RVO:67985955 Keywords : argumentation * logical form * incorrect argument * correct arguments Subject RIV: AA - Philosophy ; Religion Impact factor: 0.689, year: 2016
Parametric Linear Dynamic Logic
Directory of Open Access Journals (Sweden)
Peter Faymonville
2014-08-01
Full Text Available We introduce Parametric Linear Dynamic Logic (PLDL, which extends Linear Dynamic Logic (LDL by temporal operators equipped with parameters that bound their scope. LDL was proposed as an extension of Linear Temporal Logic (LTL that is able to express all ω-regular specifications while still maintaining many of LTL's desirable properties like an intuitive syntax and a translation into non-deterministic Büchi automata of exponential size. But LDL lacks capabilities to express timing constraints. By adding parameterized operators to LDL, we obtain a logic that is able to express all ω-regular properties and that subsumes parameterized extensions of LTL like Parametric LTL and PROMPT-LTL. Our main technical contribution is a translation of PLDL formulas into non-deterministic Büchi word automata of exponential size via alternating automata. This yields a PSPACE model checking algorithm and a realizability algorithm with doubly-exponential running time. Furthermore, we give tight upper and lower bounds on optimal parameter values for both problems. These results show that PLDL model checking and realizability are not harder than LTL model checking and realizability.
Temporal logic motion planning
CSIR Research Space (South Africa)
Seotsanyana, M
2010-01-01
Full Text Available In this paper, a critical review on temporal logic motion planning is presented. The review paper aims to address the following problems: (a) In a realistic situation, the motion planning problem is carried out in real-time, in a dynamic, uncertain...
Logic Programming for Linguistics
DEFF Research Database (Denmark)
Christiansen, Henning
2010-01-01
This article gives a short introduction on how to get started with logic pro- gramming in Prolog that does not require any previous programming expe- rience. The presentation is aimed at students of linguistics, but it does not go deeper into linguistics than any student who has some ideas of what...
Czech Academy of Sciences Publication Activity Database
Peregrin, Jaroslav
2010-01-01
Roč. 4, č. 2 (2010), s. 207-223 ISSN 1661-8297 R&D Projects: GA ČR(CZ) GAP401/10/1279 Institutional research plan: CEZ:AV0Z9009908 Keywords : logic * natural selection * modus potens * inferentialism Subject RIV: AA - Philosophy ; Religion
Quantum probabilistic logic programming
Balu, Radhakrishnan
2015-05-01
We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.
Temporalizing Epistemic Default Logic
van der Hoek, Wiebe; Meyer, John Jules; Treur, Jan
1998-01-01
We present an epistemic default logic, based on the metaphore of a meta-level architecture. Upward reflection is formalized by a nonmonotonic entailment relation, based on the objective facts that are either known or unknown at the object level. Then, the meta (monotonic) reasoning process generates
Logic Programming with Requests
De Schreye, Danny; Etalle, Sandro; van Raamsdonk, Femke
1999-01-01
We propose an extension of logic programming where the user can specify, together with the initial query, the information he is interested in by means of a request. This allows one to extract a result from an incomplete computation, such as the prefix of an infinite derivation. The classical
Logical Characterisation of Ontology Construction using Fuzzy Description Logics
DEFF Research Database (Denmark)
Badie, Farshad; Götzsche, Hans
had the extension of ontologies with Fuzzy Logic capabilities which plan to make proper backgrounds for ontology driven reasoning and argumentation on vague and imprecise domains. This presentation conceptualises learning from fuzzy classes using the Inductive Logic Programming framework. Then......, employs Description Logics in characterising and analysing fuzzy statements. And finally, provides a conceptual framework describing fuzzy concept learning in ontologies using the Inductive Logic Programming....
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations
Directory of Open Access Journals (Sweden)
Ausif Mahmood
1996-01-01
a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.
Automatic ranging circuit for a digital panel meter
International Nuclear Information System (INIS)
Mueller, T.R.; Ross, H.H.
1976-01-01
This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to ensure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit. The system was designed for readout of a fluorescence analyzer for uranium analysis
Greek, Indian and Arabic logic
Gabbay, Dov M
2004-01-01
Greek, Indian and Arabic Logic marks the initial appearance of the multi-volume Handbook of the History of Logic. Additional volumes will be published when ready, rather than in strict chronological order. Soon to appear are The Rise of Modern Logic: From Leibniz to Frege. Also in preparation are Logic From Russell to Gödel, Logic and the Modalities in the Twentieth Century, and The Many-Valued and Non-Monotonic Turn in Logic. Further volumes will follow, including Mediaeval and Renaissance Logic and Logic: A History of its Central. In designing the Handbook of the History of Logic, the Editors have taken the view that the history of logic holds more than an antiquarian interest, and that a knowledge of logic's rich and sophisticated development is, in various respects, relevant to the research programmes of the present day. Ancient logic is no exception. The present volume attests to the distant origins of some of modern logic's most important features, such as can be found in the claim by the authors of t...
Stochastic p -Bits for Invertible Logic
Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo
2017-07-01
Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small
Commutation circuit for an HVDC circuit breaker
Premerlani, William J.
1981-01-01
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.
Test generation for digital circuits using parallel processing
Hartmann, Carlos R.; Ali, Akhtar-Uz-Zaman M.
1990-12-01
The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic
Directory of Open Access Journals (Sweden)
Shipra Upadhyay
2013-01-01
Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.
Quantum Logic and Quantum Reconstruction
Stairs, Allen
2015-01-01
Quantum logic understood as a reconstruction program had real successes and genuine limitations. This paper offers a synopsis of both and suggests a way of seeing quantum logic in a larger, still thriving context.
DEFF Research Database (Denmark)
Braüner, Torben
2011-01-01
Hybrid logic is an extension of modal logic which allows us to refer explicitly to points of the model in the syntax of formulas. It is easy to justify interest in hybrid logic on applied grounds, with the usefulness of the additional expressive power. For example, when reasoning about time one...... often wants to build up a series of assertions about what happens at a particular instant, and standard modal formalisms do not allow this. What is less obvious is that the route hybrid logic takes to overcome this problem often actually improves the behaviour of the underlying modal formalism....... For example, it becomes far simpler to formulate proof-systems for hybrid logic, and completeness results can be proved of a generality that is simply not available in modal logic. That is, hybridization is a systematic way of remedying a number of known deficiencies of modal logic. First-order hybrid logic...
Logical analysis of biological systems
DEFF Research Database (Denmark)
Mardare, Radu Iulian
2005-01-01
R. Mardare, Logical analysis of biological systems. Fundamenta Informaticae, N 64:271-285, 2005.......R. Mardare, Logical analysis of biological systems. Fundamenta Informaticae, N 64:271-285, 2005....
Probabilistic logics and probabilistic networks
Haenni, Rolf; Wheeler, Gregory; Williamson, Jon; Andrews, Jill
2014-01-01
Probabilistic Logic and Probabilistic Networks presents a groundbreaking framework within which various approaches to probabilistic logic naturally fit. Additionally, the text shows how to develop computationally feasible methods to mesh with this framework.
Wansing, Heinrich; Willkommen, Caroline; Recent Trends in Philosophical Logic
2014-01-01
This volume presents recent advances in philosophical logic with chapters focusing on non-classical logics, including paraconsistent logics, substructural logics, modal logics of agency and other modal logics. The authors cover themes such as the knowability paradox, tableaux and sequent calculi, natural deduction, definite descriptions, identity, truth, dialetheism, and possible worlds semantics. The developments presented here focus on challenging problems in the specification of fundamental philosophical notions, as well as presenting new techniques and tools, thereby contributing to the development of the field. Each chapter contains a bibliography, to assist the reader in making connections in the specific areas covered. Thus this work provides both a starting point for further investigations into philosophical logic and an update on advances, techniques and applications in a dynamic field. The chapters originate from papers presented during the Trends in Logic XI conference at the Ruhr University ...
Preferential reasoning for modal logics
CSIR Research Space (South Africa)
Britz, K
2011-11-01
Full Text Available Modal logic is the foundation for a versatile and well-established class of knowledge representation formalisms in artificial intelligence. Enriching modal logics with non-monotonic reasoning capabilities such as preferential reasoning as developed...
From Logical to Distributional Models
Directory of Open Access Journals (Sweden)
Anne Preller
2014-12-01
Full Text Available The paper relates two variants of semantic models for natural language, logical functional models and compositional distributional vector space models, by transferring the logic and reasoning from the logical to the distributional models. The geometrical operations of quantum logic are reformulated as algebraic operations on vectors. A map from functional models to vector space models makes it possible to compare the meaning of sentences word by word.
Design and verification of distributed logic controllers with application of Petri nets
Energy Technology Data Exchange (ETDEWEB)
Wiśniewski, Remigiusz; Grobelna, Iwona; Grobelny, Michał; Wiśniewska, Monika [University of Zielona Góra, Licealna 9, 65-417 Zielona Góra (Poland)
2015-12-31
The paper deals with the designing and verification of distributed logic controllers. The control system is initially modelled with Petri nets and formally verified against structural and behavioral properties with the application of the temporal logic and model checking technique. After that it is decomposed into separate sequential automata that are working concurrently. Each of them is re-verified and if the validation is successful, the system can be finally implemented.
Modal Logics for Cryptographic Processes
DEFF Research Database (Denmark)
Frendrup, U.; Huttel, Hans; Jensen, N. J.
2002-01-01
We present three modal logics for the spi-calculus and show that they capture strong versions of the environment sensitive bisimulation introduced by Boreale et al. Our logics differ from conventional modal logics for process calculi in that they allow us to describe the knowledge of an attacker ...
Combining Paraconsistent Logic with Argumentation
Grooters, Diana; Prakken, Hendrik
2014-01-01
One tradition in the logical study of argumentation is to allow for arguments that combine strict and defeasible inference rules, and to derive the strict inference rules from a logic at least as strong as classical logic. An unsolved problem in this tradition is how the trivialising effect of the
Lectures on Logic and Computation
DEFF Research Database (Denmark)
The European Summer School in Logic, Language and Information (ESSLLI) is organized every year by the Association for Logic, Language and Information (FoLLI) in different sites around Europe. The main focus of ESSLLI is on the interface between linguistics, logic and computation. ESSLLI offers fo...
DEFF Research Database (Denmark)
Engberg, Uffe Henrik; Winskel, Glynn
This article shows how individual Petri nets form models of Girard's intuitionistic linear logic. It explores questions of expressiveness and completeness of linear logic with respect to this interpretation. An aim is to use Petri nets to give an understanding of linear logic and give some apprai...
Strong Completeness for Markovian Logics
DEFF Research Database (Denmark)
Kozen, Dexter; Mardare, Radu Iulian; Panangaden, Prakash
2013-01-01
In this paper we present Hilbert-style axiomatizations for three logics for reasoning about continuous-space Markov processes (MPs): (i) a logic for MPs defined for probability distributions on measurable state spaces, (ii) a logic for MPs defined for sub-probability distributions and (iii) a log...
International Nuclear Information System (INIS)
Prunier, J.
1977-01-01
The first generations of circuits intended to equip the multiwire proportional chambers provided the user with logical type indications (absence or presence of a signal at a given place). This logical indication was soon associated with a semi-analog data (presence or absence of a signal above an analog threshold, i.e. the discrimination function) as with FILAS, RBA and RBB circuits. The evolution continued with the appearance of analog data capture (time, amplitude, charge) and the corresponding circuits: IFT circuits, analog-to-digital converters [fr
International Nuclear Information System (INIS)
Yoshida, Toshihiro
1981-01-01
Probabilities of meson production in the sequential decay of Reggeons, which are formed from the projectile and the target in the hadron-hadron to Reggeon-Reggeon processes, are investigated. It is assumed that pair creation of heavy quarks and simultaneous creation of two antiquark-quark pairs are negligible. The leading-order terms with respect to ratio of creation probabilities of anti s s to anti u u (anti d d) are calculated. The production cross sections in the target fragmentation region are given in terms of probabilities in the initial decay of the Reggeons and an effect of manyparticle production. (author)
Analog circuit design designing dynamic circuit response
Feucht, Dennis
2010-01-01
This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.
Compact representations for the design of quantum logic
Niemann, Philipp
2017-01-01
This book discusses modern approaches and challenges of computer-aided design (CAD) of quantum circuits with a view to providing compact representations of quantum functionality. Focusing on the issue of quantum functionality, it presents Quantum Multiple-Valued Decision Diagrams (QMDDs – a means of compactly and efficiently representing and manipulating quantum logic. For future quantum computers, going well beyond the size of present-day prototypes, the manual design of quantum circuits that realize a given (quantum) functionality on these devices is no longer an option. In order to keep up with the technological advances, methods need to be provided which, similar to the design and synthesis of conventional circuits, automatically generate a circuit description of the desired functionality. To this end, an efficient representation of the desired quantum functionality is of the essence. While straightforward representations are restricted due to their (exponentially) large matrix descriptions and other de...
International Nuclear Information System (INIS)
Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.
1984-01-01
A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)
A programming language for composable DNA circuits.
Phillips, Andrew; Cardelli, Luca
2009-08-06
Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.
Micro-circuits for high energy physics
International Nuclear Information System (INIS)
Kunz, P.F.
1978-01-01
Microprogramming is an inherently elegant method for implementing many digital systems. It is a mixture of hardware and software techniques with the logic subsystems controlled by 'instructions' stored in a memory. In the past, designing microprogrammed systems was difficult, tedious, and expensive because the available components were capable of only limited number of functions. Today, however, large blocks of microprogrammed systems have been incorporated into a single integrated circuit, thus microprogramming has become a simple, practical method. (Auth.)
DEFF Research Database (Denmark)
Friche, Nanna; Normann Andersen, Vibeke
unintended consequences. Theoretically, we draw on different management and governance theories, e.g. performance management. Empirically, the study is based on surveys to teachers and students at all Danish vocational colleges and interviews with school leaders, teachers and students at six colleges (cases...... and well-being of students enrolled in the VETs must be strengthened. We focus on target 1, 2 and 4. The reform is being implemented in a field of VET that can be characterized by four logics of governance. Firstly, a governance logic characterized by institutional independence of vocational colleges......For the last fifteen years completion rates in Danish vocational education and training (VET) has stayed on a rather low level. In 2014, only half of the students enrolled in a vocational program on upper secondary level, graduated from the program (Flarup et al 2016). In Denmark, like in other...
Modern Logical Frameworks Design
DEFF Research Database (Denmark)
Murawska, Agata Anna
2017-01-01
lack support for reasoning about, or programming with, the mechanised systems. Our main motivation is to eventually make it possible to model and reason about complex concurrent systems and protocols. No matter the application, be it the development of a logic for multiparty session types...... or a cryptographic protocol used in a voting system, we need the ability to model and reason about both the building blocks of these systems and the intricate connections between them. To this end, this dissertation is an investigation into LF-based formalisms that might help address the aforementioned issues. We...... design and provide the meta-theory of two new frameworks, HyLF and Lincx. The former aims to extend the expressiveness of LF to include proof irrelevance and some user-defined behaviours, using ideas from hybrid logics. The latter is a showcase for an easier to implement framework, while also allowing...
Competing Logics and Healthcare
Saks, Mike
2018-01-01
This paper offers a short commentary on the editorial by Mannion and Exworthy. The paper highlights the positive insights offered by their analysis into the tensions between the competing institutional logics of standardization and customization in healthcare, in part manifested in the conflict between managers and professionals, and endorses the plea of the authors for further research in this field. However, the editorial is criticized for its lack of a strong societal reference point, the comparative absence of focus on hybridization, and its failure to highlight structural factors impinging on the opposing logics in a broader neo-institutional framework. With reference to the Procrustean metaphor, it is argued that greater stress should be placed on the healthcare user in future health policy. Finally, the case of complementary and alternative medicine is set out which – while not explicitly mentioned in the editorial – most effectively concretizes the tensions at the heart of this analysis of healthcare. PMID:29626406
Conventions and Institutional Logics
DEFF Research Database (Denmark)
Westenholz, Ann
Two theoretical approaches – Conventions and Institutional Logics – are brought together and the similarities and differences between the two are explored. It is not the intention to combine the approaches, but I would like to open both ‘boxes’ and make them available to each other with the purpose...... of creating a space for dialog. Both approaches were developed in the mid-1980s as a reaction to rational-choice economic theory and collectivistic sociological theory. These two theories were oversimplifying social life as being founded either in actor-micro level analyses or in structure-macro level...... analyses. The theoretical quest of both Conventions and Institutional Logics has been to understand the increasing indeterminacy, uncertainty and ambiguity in people’s lives where a sense of reality, of value, of moral, of feelings is not fixed. Both approaches have created new theoretical insights...
Directory of Open Access Journals (Sweden)
Douglas Walton
2015-12-01
Full Text Available This paper presents a formalization of informal logic using the Carneades Argumentation System (CAS, a formal, computational model of argument that consists of a formal model of argument graphs and audiences. Conflicts between pro and con arguments are resolved using proof standards, such as preponderance of the evidence. CAS also formalizes argumentation schemes. Schemes can be used to check whether a given argument instantiates the types of argument deemed normatively appropriate for the type of dialogue.
Probabilistic Logical Characterization
DEFF Research Database (Denmark)
Hermanns, Holger; Parma, Augusto; Segala, Roberto
2011-01-01
Probabilistic automata exhibit both probabilistic and non-deterministic choice. They are therefore a powerful semantic foundation for modeling concurrent systems with random phenomena arising in many applications ranging from artificial intelligence, security, systems biology to performance...... modeling. Several variations of bisimulation and simulation relations have proved to be useful as means to abstract and compare different automata. This paper develops a taxonomy of logical characterizations of these relations on image-finite and image-infinite probabilistic automata....
Bisimulations, games, and logic
DEFF Research Database (Denmark)
Nielsen, Mogens; Clausen, Christian
1994-01-01
In a recent paper by Joyal, Nielsen, and Winskel, bisimulation is defined in an abstract and uniform way across a wide range of different models for concurrency. In this paper, following a recent trend in theoretical computer science, we characterize their abstract definition game-theoretically a......-theoretically and logically in a non-interleaving model. Our characterizations appear as surprisingly simple extensions of corresponding characterizations of interleaving bisimulation....
Stereotypical Reasoning: Logical Properties
Lehmann, Daniel
2002-01-01
Stereotypical reasoning assumes that the situation at hand is one of a kind and that it enjoys the properties generally associated with that kind of situation. It is one of the most basic forms of nonmonotonic reasoning. A formal model for stereotypical reasoning is proposed and the logical properties of this form of reasoning are studied. Stereotypical reasoning is shown to be cumulative under weak assumptions.
1981-01-01
Rapport, Groupe Intelligence Pasero, R., Artificielle , Universite d’Aix-Marseille, Roussel, P. Luminy, France, 1973. [Kowalski 1974] Kowalski, R. A...THIS PAGZ(Whan Doee Es tMord) Item 20 (Cont’d) ------ work in the area of artificial intelligence and those used in general program development into a...logic programming with LISP for implementing intelligent data base query systems. Continued developments will allow for enhancements to be made to the
Magnetoresistive logic and biochip
International Nuclear Information System (INIS)
Brueckl, Hubert; Brzeska, Monika; Brinkmann, Dirk; Schotter, J.Joerg; Reiss, Guenter; Schepper, Willi; Kamp, P.-B.; Becker, Anke
2004-01-01
While some magnetoresistive devices based on giant magnetoresistance or spin-dependent tunneling are already commercialized, a new branch of development is evolving towards magnetoresistive logic with magnetic tunnel junctions. Furthermore, the new magnetoelectronic effects show promising properties in magnetoresistive biochips, which are capable of detecting even single molecules (e.g. DNA) by functionalized magnetic markers. The unclear limits of this approach are discussed with two model systems
Optimally Fortifying Logic Reliability through Criticality Ranking
Directory of Open Access Journals (Sweden)
Yu Bai
2015-02-01
Full Text Available With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI and hot carrier injection (HCI. This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the VDD values of some LUTs based on their modular criticality values. Although the idea of scaling VDD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the VDD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table, which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT’s reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.
POLYP: an automatic device for drawing sequential samples of gas
Energy Technology Data Exchange (ETDEWEB)
Gaglione, P; Koechler, C; Stanchi, L
1974-12-01
Polyp is an automatic device consisting of electronic equipment which drives sequentially 8 small pumps for drawing samples of gas. The electronic circuit is driven by a quartz oscillator and allows for the preselection of a waiting time in such a manner that a set of similar instruments placed in suitable position in the open country will start simultaneously. At the same time the first pump of each instrument will inflate a plastic bag for a preset time. The other seven pumps will inflate sequentially the other bags. The instrument is powered by rechargeable batteries and realized with C-MUS integrated circuits for a nearly negligible consumption. As it is foreseen for field operation it is waterproof.
POLYP: an automatic device for drawing sequential samples of gas
International Nuclear Information System (INIS)
Gaglione, P.; Koechler, C.; Stanchi, L.
1974-12-01
POLYP is an automatic device consisting of an electronic equipment which drives sequentially 8 small pumps for drawing samples of gas. The electronic circuit is driven by a quartz oscillator and allows for the preselection of a waiting time in such a manner that a set of similar instruments placed in suitable position in the open country will start simultaneously. At the same time the first pump of each instrument will inflate a plastic bag for a preset time. Thereafter the other seven pumps will inflate sequentially the other bag. The instrument is powered by rechargeable batteries and realized with C-MOS integrated circuits for a nearly negligible consumption. As it is foreseen for field operation it is waterproof
Synthetic Aperture Sequential Beamforming
DEFF Research Database (Denmark)
Kortbek, Jacob; Jensen, Jørgen Arendt; Gammelmark, Kim Løkke
2008-01-01
A synthetic aperture focusing (SAF) technique denoted Synthetic Aperture Sequential Beamforming (SASB) suitable for 2D and 3D imaging is presented. The technique differ from prior art of SAF in the sense that SAF is performed on pre-beamformed data contrary to channel data. The objective is to im......A synthetic aperture focusing (SAF) technique denoted Synthetic Aperture Sequential Beamforming (SASB) suitable for 2D and 3D imaging is presented. The technique differ from prior art of SAF in the sense that SAF is performed on pre-beamformed data contrary to channel data. The objective...... is to improve and obtain a more range independent lateral resolution compared to conventional dynamic receive focusing (DRF) without compromising frame rate. SASB is a two-stage procedure using two separate beamformers. First a set of Bmode image lines using a single focal point in both transmit and receive...... is stored. The second stage applies the focused image lines from the first stage as input data. The SASB method has been investigated using simulations in Field II and by off-line processing of data acquired with a commercial scanner. The performance of SASB with a static image object is compared with DRF...
A Paraconsistent Higher Order Logic
DEFF Research Database (Denmark)
Villadsen, Jørgen
2004-01-01
of paraconsistent logics in knowledge-based systems, logical semantics of natural language, etc. Higher order logics have the advantages of being expressive and with several automated theorem provers available. Also the type system can be helpful. We present a concise description of a paraconsistent higher order...... of the logic is examined by a case study in the domain of medicine. Thus we try to build a bridge between the HOL and MVL communities. A sequent calculus is proposed based on recent work by Muskens. Many non-classical logics are, at the propositional level, funny toys which work quite good, but when one wants...