WorldWideScience

Sample records for semiconductor cmos technology

  1. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  2. JPL CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  3. Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

    Science.gov (United States)

    Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

    2018-03-01

    This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

  4. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  5. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  6. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa; Hussain, Aftab M.; Hanna, Amir

    2016-01-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today

  7. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  8. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  9. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Science.gov (United States)

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  10. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  11. Radiation-hardened bulk CMOS technology

    International Nuclear Information System (INIS)

    Dawes, W.R. Jr.; Habing, D.H.

    1979-01-01

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  12. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  13. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  14. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  15. A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

    Science.gov (United States)

    2014-01-01

    ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

  16. Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

    Science.gov (United States)

    Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

    2013-05-06

    In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

  17. High-temperature complementary metal oxide semiconductors (CMOS)

    International Nuclear Information System (INIS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  18. Semiconductor technology program. Progress briefs

    Science.gov (United States)

    Bullis, W. M.

    1980-01-01

    Measurement technology for semiconductor materials, process control, and devices is reviewed. Activities include: optical linewidth and thermal resistance measurements; device modeling; dopant density profiles; resonance ionization spectroscopy; and deep level measurements. Standardized oxide charge terminology is also described.

  19. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    Science.gov (United States)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  20. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  1. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  2. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  3. Scaled CMOS Technology Reliability Users Guide

    Science.gov (United States)

    White, Mark

    2010-01-01

    The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is

  4. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  5. Introduction to semiconductor manufacturing technology

    CERN Document Server

    2012-01-01

    IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

  6. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  7. Device Innovation and Material Challenges at the Limits of CMOS Technology

    Science.gov (United States)

    Solomon, P. M.

    2000-08-01

    Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

  8. Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

    International Nuclear Information System (INIS)

    Tsukamoto, Katsuhiro; Kuroi, Takashi; Kawasaki, Yoji

    2011-01-01

    Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology's application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion-related technologies for emerging industries will also be presented.

  9. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  10. Dry etching technology for semiconductors

    CERN Document Server

    Nojiri, Kazuo

    2015-01-01

    This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

  11. Fundamentals of semiconductor processing technology

    CERN Document Server

    El-Kareh, Badih

    1995-01-01

    The drive toward new semiconductor technologies is intricately related to market demands for cheaper, smaller, faster, and more reliable circuits with lower power consumption. The development of new processing tools and technologies is aimed at optimizing one or more of these requirements. This goal can, however, only be achieved by a concerted effort between scientists, engineers, technicians, and operators in research, development, and manufac­ turing. It is therefore important that experts in specific disciplines, such as device and circuit design, understand the principle, capabil­ ities, and limitations of tools and processing technologies. It is also important that those working on specific unit processes, such as lithography or hot processes, be familiar with other unit processes used to manufacture the product. Several excellent books have been published on the subject of process technologies. These texts, however, cover subjects in too much detail, or do not cover topics important to modem tech­ n...

  12. Application of CMOS Technology to Silicon Photomultiplier Sensors

    Science.gov (United States)

    D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

    2017-01-01

    We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

  13. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  14. Integrated imaging sensor systems with CMOS active pixel sensor technology

    Science.gov (United States)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  15. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  16. AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    N. B. ROMLI

    2015-03-01

    Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

  17. Future challenges in single event effects for advanced CMOS technologies

    International Nuclear Information System (INIS)

    Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

    2010-01-01

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  18. Pixel front-end development in 65 nm CMOS technology

    International Nuclear Information System (INIS)

    Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

  19. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  20. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications

    KAUST Repository

    Hussain, Aftab M.

    2015-11-26

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today\\'s digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  2. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  3. Semiconductor

    International Nuclear Information System (INIS)

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  4. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  5. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  6. PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    T. Tharaneeswaran

    2012-06-01

    Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

  7. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  8. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  9. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  10. Radiation effects in semiconductors

    CERN Document Server

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  11. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    Science.gov (United States)

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  12. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  13. Suitability of integrated protection diodes from diverse semiconductor technologies

    NARCIS (Netherlands)

    van Wanum, Maurice; Lebouille, Tom; Visser, Guido; van Vliet, Frank Edward

    2009-01-01

    Abstract In this article diodes from three different semiconductor technologies are compared based on their suitability to protect a receiver. The semiconductor materials involved are silicon, gallium arsenide and gallium nitride. The diodes in the diverse semiconductor technologies themselves are

  14. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    National Research Council Canada - National Science Library

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  15. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  16. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  17. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  18. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  19. Fabrication of a Micromachined Capacitive Switch Using the CMOS-MEMS Technology

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Lin

    2015-11-01

    Full Text Available The study investigates the design and fabrication of a micromachined radio frequency (RF capacitive switch using the complementary metal oxide semiconductor-microelectromechanical system (CMOS-MEMS technology. The structure of the micromachined switch is composed of a membrane, eight springs, four inductors, and coplanar waveguide (CPW lines. In order to reduce the actuation voltage of the switch, the springs are designed as low stiffness. The finite element method (FEM software CoventorWare is used to simulate the actuation voltage and displacement of the switch. The micromachined switch needs a post-CMOS process to release the springs and membrane. A wet etching is employed to etch the sacrificial silicon dioxide layer, and to release the membrane and springs of the switch. Experiments show that the pull-in voltage of the switch is 12 V. The switch has an insertion loss of 0.8 dB at 36 GHz and an isolation of 19 dB at 36 GHz.

  20. Thermodynamic concepts in semiconductor quantum dot technology

    International Nuclear Information System (INIS)

    Shchukin, V.

    2001-01-01

    Major trends of the modern civilization are related to the changing of the industrial society into an information and knowledge-based society. This transformation is to a large extent based on the modern information and communication technology. The nobel prize-2000 in physics is a remarkable recognition of an extremely high significance of this kind of technology. The nobel prize has been awarded with one half jointly to Zhores I. Alferov and Herbert Kroemer for developing semiconductor heterostructures used in high-speed- and opto-electronics and one half to Jack St. Clair Kilby for this part in the invention of the integrated circuit. The development of the semiconductor heterostructures technology requires a profound understanding of the basic growth mechanisms involved in any technological process, including any type of epitaxy, either the liquid phase epitaxy (LPE), or the metalorganic vapor phase epitaxy (MOVPE), or the molecular beam epitaxy (MBE). Starting from this pioneering works on semiconductor heterostructures till present time, Professor Zh. Alferov has always paid much attention to complex and comprehensive study of the subject. This covers the growth - as well as the post-growth technology including the theoretical modeling of the technology, the characterization of the heterostructures, and the device design. Such complex approach has master mined the scientific and technological success of Abraham loffe Institute in the area of semiconductor heterostructures, and later, nano structures. (Orig../A.B.)

  1. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  2. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  3. Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, M.

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

  4. Radiation Tolerant Design with 0.18-micron CMOS Technology

    CERN Document Server

    Chen, Li; Durdle , Nelson G.

    This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and afte...

  5. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, Mohamed N.; Alshareef, Husam N.

    2015-01-01

    , which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin

  6. Merits of CMOS/SIMOX technology for low-voltage SRAM macros

    CERN Document Server

    Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

    1999-01-01

    A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

  7. A refractory metal gate approach for micronic CMOS technology

    International Nuclear Information System (INIS)

    Lubowiecki, V.; Ledys, J.L.; Plossu, C.; Balland, B.

    1987-01-01

    In the future, devices scaling down, integration density and performance improvements are going to bring a number of conventional circuit design and process techniques to their fundamental limits. To avoid any severe limitations in MOS ULSI (Ultra Large Scale Integration) technologies, interconnection materials and schemes are required to emerge, in order to face the Megabits memory field. Among those, the gate approach will obviously take a keyrole, when the operating speed of ULSI chips will reach the practical upper limits imposed by parasitic resistances and capacitances which stem from the circuit interconnect wiring. Even if fairly suitable for MOS process, doped polycrystalline silicon is being gradually replaced by refractory metal silicide or polycide structures, which match better with low resistivity requirements. However, as we approach the submicronic IC's, higher conductivity materials will be paid more and more attention. Recently, works have been devoted and published on refractory metal gate technologies. Molybdenum or tungsten, deposited either by CVD or PVD methods, are currently reported even if some drawbacks in their process integration still remain. This paper is willing to present such an approach based on tungsten (more reliable than Molybdenum deposited by LPCVD (giving more conductive and more stable films than PVD). Deposition process will be first described. Then CMOS process flow will allow us to focus on specific refractory metal gate issues. Finally, electrical and physical properties will be assessed, which will demonstrate the feasibility of such a technology as well as the compatibility of the tungsten with most of the usual techniques

  8. Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors

    International Nuclear Information System (INIS)

    Manfredi, P.F.; Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.

    2003-01-01

    During the past 15 years, the CMOS technologies have provided the most widely followed approach to signal processing with microstrip detectors. In more recent times, CMOS front-end systems have been developed to acquire and process signals from pixel detectors. During the past few years, the favor toward CMOS processes in their applications in the broad area of detector signal processing has been enhanced by the technological advancement known as device scaling and by two aspects connected to it. One is the shrinking in channel length L into the deep submicron region. The second one is the related reduction in the gate-oxide thickness t ox to a few nm. The reduction in t ox has, as a consequence of primary importance, a decreased 1/f-noise contribution to the equivalent noise charge (ENC). The thinner gate-oxide and the shrinking in gate length, in some regions of operations, concur to increase the transconductance of the device, which results in a smaller ENC contribution from channel thermal noise. The goal of the present paper is to address the question of whether or not the most advanced CMOS processes may meet the requirements set by high resolution, high dynamic range applications like the energy-dispersive photon analysis with solid-state detectors of comparatively large capacitance

  9. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    Science.gov (United States)

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

  10. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    International Nuclear Information System (INIS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

    2016-01-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  11. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  12. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  13. Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs

    International Nuclear Information System (INIS)

    Abare, W.E.; Huffman, D.D.; Moffett, G.E.

    1982-01-01

    This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented

  14. Long term ionization response of several BiCMOS VLSIC technologies

    International Nuclear Information System (INIS)

    Pease, R.L.; Combs, W.; Clark, S.

    1992-01-01

    BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

  15. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    International Nuclear Information System (INIS)

    Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

    2006-01-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

  16. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  17. Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

    OpenAIRE

    Pillonnet , Gaël; Jeanniot , Nicolas

    2016-01-01

    International audience; Integrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares th...

  18. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

  19. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  20. Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

    International Nuclear Information System (INIS)

    Jiang Yuxi; Li Jiao; Ran Feng; Cao Jialin; Yang Dianxiong

    2009-01-01

    Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented. (semiconductor devices)

  1. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

  2. Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

    Indian Academy of Sciences (India)

    Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR ... The semiconductor roadmap following Moore's law is responsible for ..... The financial support from University Grants Commi- ssion (UGC), New ...

  3. Total dose hardness of a commercial SiGe BiCMOS technology

    International Nuclear Information System (INIS)

    Van Vonno, N.; Lucas, R.; Thornberry, D.

    1999-01-01

    Over the past decade SiGe HBT technology has progress from the laboratory to actual commercial applications. When integrated into a BiMOS process, this technology has applications in low-cost space systems. In this paper, we report results of total dose testing of a SiGe/CMOS process accessible through a commercial foundry. (authors)

  4. Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

  5. Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

    International Nuclear Information System (INIS)

    Zhang, L.; Wang, M.; Fu, M.; Zhang, Y.; Yan, W.

    2017-01-01

    The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm 2 .

  6. Scaling limits and reliability of SOI CMOS technology

    International Nuclear Information System (INIS)

    Ioannou, D E

    2005-01-01

    As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

  7. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  8. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  9. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  10. Review of the Semiconductor Industry and Technology Roadmap.

    Science.gov (United States)

    Kumar, Sameer; Krenner, Nicole

    2002-01-01

    Points out that the semiconductor industry is extremely competitive and requires ongoing technological advances to improve performance while reducing costs to remain competitive and how essential it is to gain an understanding of important facets of the industry. Provides an overview of the initial and current semiconductor technology roadmap that…

  11. Review of wide band-gap semiconductors technology

    Directory of Open Access Journals (Sweden)

    Jin Haiwei

    2016-01-01

    Full Text Available Silicon carbide (SiC and gallium nitride (GaN are typical representative of the wide band-gap semiconductor material, which is also known as third-generation semiconductor materials. Compared with the conventional semiconductor silicon (Si or gallium arsenide (GaAs, wide band-gap semiconductor has the wide band gap, high saturated drift velocity, high critical breakdown field and other advantages; it is a highly desirable semiconductor material applied under the case of high-power, high-temperature, high-frequency, anti-radiation environment. These advantages of wide band-gap devices make them a hot spot of semiconductor technology research in various countries. This article describes the research agenda of United States and European in this area, focusing on the recent developments of the wide band-gap technology in the US and Europe, summed up the facing challenge of the wide band-gap technology.

  12. Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    2003-01-01

    The influence of different geometries (layouts) and structures of high-speed photodiodes in fully standard 0.18 μm CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. Three photodiode structures are studied: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. The

  13. Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

    NARCIS (Netherlands)

    Agarwal, V.; Dutta, S; Annema, AJ; Hueting, RJE; Steeneken, P.G.; Nauta, B

    2017-01-01

    This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant

  14. Broadband sub-THz spectroscopy modules integrated in 65-nm CMOS technology

    NARCIS (Netherlands)

    Matters-Kammerer, M.K.; van Goor, D.; Tripodi, L.

    2017-01-01

    The design and characterization of a broadband 20-480 GHz continuously tuneable on-chip spectrometer based on non-linear transmission lines in 65-nm CMOS technology is presented. The design procedure of the sampler that detects the ultra-broadband signal from the transmitter in time and frequency

  15. 1/f Noise Characterization in CMOS Transistors in 0.13μm Technology

    DEFF Research Database (Denmark)

    Citakovic, J.; Stenberg, L J; Andreani, Pietro

    2006-01-01

    Low-frequency noise has been studied on a set of n- and p-channel CMOS transistors fabricated in a 0.13μm technology. Noise measurements have been performed on transistors with different gate lengths operating under wide bias conditions, ranging from weak to strong inversion. Noise origin has been...

  16. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    Science.gov (United States)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  17. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS: A high performance 90 nm CMOS SAR ADC with hybrid architecture

    Science.gov (United States)

    Xingyuan, Tong; Jianming, Chen; Zhangming, Zhu; Yintang, Yang

    2010-01-01

    A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 × 214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

  19. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  20. Characterization and radiation studies of diode test structures in LFoundry CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    In order to prepare for the High Luminosity upgrade of the LHC, all subdetector systems of the ATLAS experiment will be upgraded. In preparation for this process, different possibilities for new radiation-hard and cost-efficient silicon sensor technologies to be used as part of hybrid pixel detectors in the ATLAS inner tracker are being investigated. One promising way to optimize the cost-efficiency of silicon-based pixel detectors is to use commercially available CMOS technologies such as the 150 nm process by LFoundry. In this talk, several CMOS pixel test structures, such as simple diodes and small pixel arrays, that were manufactured in this technology are characterized regarding general performance and radiation hardness and compared to each other as well as to the current ATLAS pixel detector.

  1. Semiconductor terahertz technology devices and systems at room temperature operation

    CERN Document Server

    Carpintero, G; Hartnagel, H; Preu, S; Raisanen, A

    2015-01-01

    Key advances in Semiconductor Terahertz (THz) Technology now promises important new applications enabling scientists and engineers to overcome the challenges of accessing the so-called "terahertz gap".  This pioneering reference explains the fundamental methods and surveys innovative techniques in the generation, detection and processing of THz waves with solid-state devices, as well as illustrating their potential applications in security and telecommunications, among other fields. With contributions from leading experts, Semiconductor Terahertz Technology: Devices and Systems at Room Tempe

  2. Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

    International Nuclear Information System (INIS)

    Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

    2009-01-01

    This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

  3. Nano-electromechanical switch-CMOS hybrid technology and its applications.

    Science.gov (United States)

    Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

    2011-01-01

    Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

  4. High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

    Science.gov (United States)

    Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

    2012-05-07

    This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

  5. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    Science.gov (United States)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  6. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  8. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  9. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  10. Blasting detonators incorporating semiconductor bridge technology

    Energy Technology Data Exchange (ETDEWEB)

    Bickes, R.W. Jr.

    1994-05-01

    The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

  11. SEU testing of a novel hardened register implemented using standard CMOS technology

    International Nuclear Information System (INIS)

    Monnier, T.; Roche, F.M.; Cosculluela, J.; Velazco, R.

    1999-01-01

    A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron nonradiation hardened CMOS technology. This paper presents the results of heavy ions tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact to die real estate, write time, or power consumption

  12. OMNI: An optoelectronic multichannel network interface based on hybrid CMOS-SEED technology

    Science.gov (United States)

    Pinkston, Timothy M.

    1996-11-01

    This paper presents a hybrid CMOS-SEED multiprocessor network interface smart pixel design that implements a reservation-based channel control protocol for collisionless concurrent access to multiple optical interprocessor communication channels. An asynchronous optical token is used as the arbitration mechanism for reservation control instead of slotted access. This work demonstrates that complex network protocol functions can be implemented using optoelectronic smart pixel technology.

  13. Critical parameters affecting the design of high frequency transmission lines in standard CMOS technology

    KAUST Repository

    Al Attar, Talal

    2017-05-13

    Different structures of transmission lines were designed and fabricated in standard CMOS technology to estimate some critical parameters including the RMS value of the surface roughness and the loss tangent. The input impedances for frequencies up to 50 GHz were modeled and compared with measurements. The results demonstrated a strong correlation between the used model with the proposed coefficients and the measured results, attesting the robustness of the model and the reliability of the incorporated coefficients values.

  14. Critical parameters affecting the design of high frequency transmission lines in standard CMOS technology

    KAUST Repository

    Al Attar, Talal; Alshehri, Abdullah; Almansouri, Abdullah Saud Mohammed; Al-Turki, Abdullah Turki

    2017-01-01

    Different structures of transmission lines were designed and fabricated in standard CMOS technology to estimate some critical parameters including the RMS value of the surface roughness and the loss tangent. The input impedances for frequencies up to 50 GHz were modeled and compared with measurements. The results demonstrated a strong correlation between the used model with the proposed coefficients and the measured results, attesting the robustness of the model and the reliability of the incorporated coefficients values.

  15. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Directory of Open Access Journals (Sweden)

    Preethi Padmanabhan

    2018-02-01

    Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  16. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Science.gov (United States)

    Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

    2018-01-01

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

  17. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

    Science.gov (United States)

    Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

    2018-02-03

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  18. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  19. Semiconductor laser technology for remote sensing experiments

    Science.gov (United States)

    Katz, Joseph

    1988-01-01

    Semiconductor injection lasers are required for implementing virtually all spaceborne remote sensing systems. Their main advantages are high reliability and efficiency, and their main roles are envisioned in pumping and injection locking of solid state lasers. In some shorter range applications they may even be utilized directly as the sources.

  20. A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

    Science.gov (United States)

    Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

    2017-04-01

    The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

  1. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  2. A millimeter wave linear superposition oscillator in 0.18 μm CMOS technology

    International Nuclear Information System (INIS)

    Yan Dong; Mao Luhong; Su Qiujie; Xie Sheng; Zhang Shilin

    2014-01-01

    This paper presents a millimeter wave (mm-wave) oscillator that generates signal at 36.56 GHz. The mm-wave oscillator is realized in a UMC 0.18 μm CMOS process. The linear superposition (LS) technique breaks through the limit of cut-off frequency (f T ), and realizes a much higher oscillation than f T . Measurement results show that the LS oscillator produces a calibrated −37.17 dBm output power when biased at 1.8 V; the output power of fundamental signal is −10.85 dBm after calibration. The measured phase noise at 1 MHz frequency offset is −112.54 dBc/Hz at the frequency of 9.14 GHz. This circuit can be properly applied to mm-wave communication systems with advantages of low cost and high integration density. (semiconductor integrated circuits)

  3. Radiation effects in technologies of semiconductor materials and devises

    International Nuclear Information System (INIS)

    Korshunov, F.P.; Bogatyrev, Yu.V.; Lastovskij, S.B.; Marchenko, I.G.; Zhdanovich, N.E.

    2003-01-01

    In the paper were considered the physical basics and practical results of using of penetrating radiations in technologies of nuclear transmutation of semiconductor materials (Si, GaAs) as well as in production of semiconductor devices including high-power silicon diodes, thyristors and transistors. It is shown the high efficiency of radiation technology for increasing of electronic device speed, exclusion of technological operations such as gold or platinum diffusions, increase of quality, decrease of prime cost and increase of good-to-bad device ratio yield

  4. Analysis of Different Topologies of Inverter in 0.18μm CMOS Technology and its Comparision

    OpenAIRE

    Ashish Panchal; Rajkumar Gehlot; Nidhi Maheshwari; Prafful Dubey

    2011-01-01

    In this paper we study inverter topologies under various criteria and caracteristics using Cadence tool.This paper includes analysis of inveter topologies utilized in VLSI that includes CMOS, Pseudo NMOS and Dynamic families. The characteristics include DC transfer characteristics, current Vs voltage characteristics,area and delay. The inverter topologies has been designed in 0.18μm CMOS technology with 1.8V supply voltage. SPECTRA RF simulator is used for circuit simulation. This paper also ...

  5. Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies.

    Science.gov (United States)

    Horie, Yu; Han, Seunghoon; Lee, Jeong-Yub; Kim, Jaekwan; Kim, Yongsung; Arbabi, Amir; Shin, Changgyun; Shi, Lilong; Arbabi, Ehsan; Kamali, Seyedeh Mahsa; Lee, Hong-Seok; Hwang, Sungwoo; Faraon, Andrei

    2017-05-10

    We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated CMOS image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO 2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 60-80%, and have an almost insensitive response over a ± 20° angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

  6. Superconducting Technology Assessment

    National Research Council Canada - National Science Library

    2005-01-01

    This Superconducting Technology Assessment (STA) has been conducted by the National Security Agency to address the fundamental question of a potential replacement for silicon complementary metal oxide semiconductor (CMOS...

  7. Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

    Science.gov (United States)

    Vishnoi, U.; Noll, T. G.

    2012-09-01

    The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit

  8. Semiconductor technology for reducing emissions and increasing efficiency

    Energy Technology Data Exchange (ETDEWEB)

    Duffin, B.; Frank, R. [Motorola Semiconductor Products Sector, Phoenix, AZ (United States)

    1997-12-31

    The cooperation and support of all industries are required to significantly impact a worldwide reduction in gaseous emissions that may contribute to climate change. Each industry also is striving to more efficiently utilize the resources that it consumes since this is both conservation for good citizenship and an intelligent approach to business. The semiconductor industry is also extremely concerned with these issues. However, semiconductor manufacturer`s products provide solutions for reduced emissions and increased efficiency in their industry, other industries and areas that can realize significant improvements through control technology. This paper will focus on semiconductor technologies of digital control, power switching and sensing to improve efficiency and reduce emissions in automotive, industrial, and office/home applications. 10 refs., 13 figs.

  9. Single-Photon Avalanche Diodes (SPAD) in CMOS 0.35 µm technology

    Energy Technology Data Exchange (ETDEWEB)

    Pellion, D.; Jradi, K.; Brochard, N. [Le2i – CNRS/Univ. de Bourgogne, Dijon (France); Prêle, D. [APC – CNRS/Univ. Paris Diderot, Paris (France); Ginhac, D. [Le2i – CNRS/Univ. de Bourgogne, Dijon (France)

    2015-07-01

    Some decades ago single photon detection used to be the terrain of photomultiplier tube (PMT), thanks to its characteristics of sensitivity and speed. However, PMT has several disadvantages such as low quantum efficiency, overall dimensions, and cost, making them unsuitable for compact design of integrated systems. So, the past decade has seen a dramatic increase in interest in new integrated single-photon detectors called Single-Photon Avalanche Diodes (SPAD) or Geiger-mode APD. SPAD are working in avalanche mode above the breakdown level. When an incident photon is captured, a very fast avalanche is triggered, generating an easily detectable current pulse. This paper discusses SPAD detectors fabricated in a standard CMOS technology featuring both single-photon sensitivity, and excellent timing resolution, while guaranteeing a high integration. In this work, we investigate the design of SPAD detectors using the AMS 0.35 µm CMOS Opto technology. Indeed, such standard CMOS technology allows producing large surface (few mm{sup 2}) of single photon sensitive detectors. Moreover, SPAD in CMOS technologies could be associated to electronic readout such as active quenching, digital to analog converter, memories and any specific processing required to build efficient calorimeters (Silicon PhotoMultiplier – SiPM) or high resolution imagers (SPAD imager). The present work investigates SPAD geometry. MOS transistor has been used instead of resistor to adjust the quenching resistance and find optimum value. From this first set of results, a detailed study of the dark count rate (DCR) has been conducted. Our results show a dark count rate increase with the size of the photodiodes and the temperature (at T=22.5 °C, the DCR of a 10 µm-photodiode is 2020 count s{sup −1} while it is 270 count s{sup −1} at T=−40 °C for a overvoltage of 800 mV). A small pixel size is desirable, because the DCR per unit area decreases with the pixel size. We also found that the adjustment

  10. A 1.8 GHz Voltage-Controlled Oscillator using CMOS Technology

    Science.gov (United States)

    Maisurah, M. H. Siti; Emran, F. Nazif; Norman Fadhil, Idham M.; Rahim, A. I. Abdul; Razman, Y. Mohamed

    2011-05-01

    A Voltage-Controlled Oscillator (VCO) for 1.8 GHz application has been designed using a combination of both 0.13 μm and 0.35 μm CMOS technology. The VCO has a large tuning range, which is from 1.39 GHz to 1.91 GHz, using a control voltage from 0 to 3V. The VCO exhibits a low phase-noise at 1.8 GHz which is around -119.8dBc/Hz at a frequency offset of 1 MHz.

  11. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    CERN Document Server

    Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

    2015-01-01

    front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

  12. A novel compact model for on-chip stacked transformers in RF-CMOS technology

    Science.gov (United States)

    Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

    2013-08-01

    A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

  13. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    NARCIS (Netherlands)

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche

  14. Development of Pixel Front-End Electronics using Advanced Deep Submicron CMOS Technologies

    CERN Document Server

    Havránek, Miroslav; Dingfelder, Jochen

    The content of this thesis is oriented on the R&D; of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore’s laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key pa...

  15. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; hide

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  16. Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

    Science.gov (United States)

    Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

    2008-09-01

    In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

  17. Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

    2017-08-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

  18. Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

    CERN Document Server

    Gonella, L; Silvestri, M; Gerardin, S; Pantano, D; Re, V; Manghisoni, M; Ratti, L; Ranieri, A

    2007-01-01

    The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of th...

  19. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology

    International Nuclear Information System (INIS)

    Poludniowski, G; Esposito, M; Evans, P M; Allinson, N M; Anaxagoras, T; Green, S; Parker, D J; Price, T; Manolopoulos, S; Nieto-Camero, J

    2014-01-01

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed. (paper)

  20. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology.

    Science.gov (United States)

    Poludniowski, G; Allinson, N M; Anaxagoras, T; Esposito, M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Price, T; Evans, P M

    2014-06-07

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed.

  1. Applying Physics: Opportunities in Semiconductor Technology Companies

    Science.gov (United States)

    Redinbo, Greg

    2011-03-01

    While many physicists practice in university settings, physics skills can also be applied outside the traditional academic track. ~Identifying these opportunities requires a clear understanding of how your physics training can be used in an industrial setting, understanding what challenges technology companies face, and identifying how your problem solving skills can be broadly applied in technology companies. ~In this talk I will highlight the common features of such companies, discuss what specific skills are useful for an industrial physicist, and explain roles (possibly unfamiliar) that may be available to you.

  2. Incorporating DSA in multipatterning semiconductor manufacturing technologies

    Science.gov (United States)

    Badr, Yasmine; Torres, J. A.; Ma, Yuansheng; Mitra, Joydeep; Gupta, Puneet

    2015-03-01

    Multi-patterning (MP) is the process of record for many sub-10nm process technologies. The drive to higher densities has required the use of double and triple patterning for several layers; but this increases the cost of the new processes especially for low volume products in which the mask set is a large percentage of the total cost. For that reason there has been a strong incentive to develop technologies like Directed Self Assembly (DSA), EUV or E-beam direct write to reduce the total number of masks needed in a new technology node. Because of the nature of the technology, DSA cylinder graphoepitaxy only allows single-size holes in a single patterning approach. However, by integrating DSA and MP into a hybrid DSA-MP process, it is possible to come up with decomposition approaches that increase the design flexibility, allowing different size holes or bar structures by independently changing the process for every patterning step. A simple approach to integrate multi-patterning with DSA is to perform DSA grouping and MP decomposition in sequence whether it is: grouping-then-decomposition or decomposition-then-grouping; and each of the two sequences has its pros and cons. However, this paper describes why these intuitive approaches do not produce results of acceptable quality from the point of view of design compliance and we highlight the need for custom DSA-aware MP algorithms.

  3. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  4. Strain distribution analysis in Si/SiGe line structures for CMOS technology using Raman spectroscopy

    International Nuclear Information System (INIS)

    Hecker, M; Roelke, M; Hermann, P; Zschech, E; Vartanian, V

    2010-01-01

    Strained silicon underneath the field-effect transistor gate increases significantly the charge carrier mobility and thus improves the performance of leading-edge Complementary Metal Oxide Semiconductor (CMOS) devices. For better understanding of the structure-strain relationship on the nanoscale and for optimization of device structures, the measurement of the local strain state has become essential. Raman spectroscopy is used in the present investigation to analyze the strain distribution in and close to silicon/embedded silicon-germanium (SiGe) line structures in conjunction with strain modeling applying finite element analysis. Both experimental results and modeling indicate the impact of geometry on the stress state. An increase of compressive stress within the Si lines is obtained for increasing SiGe line widths and decreasing Si line widths. The stress state within the Si lines is shown to be a mixed one deviating from a pure uniaxial state. Underneath the SiGe cavities, the presence of a tensile stress was observed. To investigate a procedure to scale down the spatial resolution of the Raman measurements, tip-enhanced Raman scattering experiments have been performed on free-standing SiGe lines with 100nm line width and line distance. The results show superior resolution and strain information not attainable in conventional Raman scans.

  5. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  6. Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

    Science.gov (United States)

    Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

    2008-08-01

    The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

  7. A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2001-01-01

    An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 1...

  8. A large dynamic range radiation tolerant analog memory in a quarter micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2000-01-01

    A 8*128 cell analog memory prototype has been designed in a commercial 0.25 jam CMOS process. The aim of this work was to investigate the possibility of designing large dynamic range mixed- mode switched capacitor circuits for High-Energy Physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant left bracket 1 right bracket . The memory cells employ gate-oxide capacitors for storage, allowing for a very high density. A voltage write - voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (V//D//D = 2.5 V), with a linearity of at least 7.5 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is plus or minus 0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after lOMrd (...

  9. A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong, E-mail: yujinshan@yeah.net [National Laboratory of Analog IC' s, Chongqing 400060 (China)

    2011-01-15

    A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. (semiconductor integrated circuits)

  10. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  11. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  12. New technology for the control of narrow-gap semiconductors

    International Nuclear Information System (INIS)

    Antoniou, I.; Bozhevolnov, V.; Melnikov, Yu.; Yafyasov, A.

    2003-01-01

    We present the results of the year work in the frame of the EU ESPRIT Project 28890 NTCONGS 'New technology for the control of narrow-gap semiconductors'. This work has involved both theoretical and experimental study, as well as the development of new specific equipment, towards the creation of a new generation of nanoelectronic devices able to operate at 77 K and even at room temperature

  13. Semiconductor radiation detectors technology and applications

    CERN Document Server

    2018-01-01

    The aim of this book is to educate the reader on radiation detectors, from sensor to read-out electronics to application. Relatively new detector materials, such as CdZTe and Cr compensated GaAs, are introduced, along with emerging applications of radiation detectors. This X-ray technology has practical applications in medical, industrial, and security applications. It identifies materials based on their molecular composition, not densities as the traditional transmission equipment does. With chapters written by an international selection of authors from both academia and industry, the book covers a wide range of topics on radiation detectors, which will satisfy the needs of both beginners and experts in the field.

  14. A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology

    OpenAIRE

    Seki, Ikuo; Nakashi, Kenichi; Ushida, Mitsuhiko; Taniguchi, Kenji

    1996-01-01

    This paper describes a CMOS 1st-order delay-line DPLL in l.2μm technology for clock regeneration. We have employed a parallel-architecture PC (Phase Comparator) to improve the speed and a DCO (Digitally Controlled Oscillator) without timing hazard. And we have also laid it out in 1.2μm CMOS, and simulated its performance by SPICE as well as logic simulation. Results show that the DPLL operates up to 60MHz, and that lock-in ranges are +5/-5% for regular" 10" input and +5/-5% for 2^13-1 PRBS (P...

  15. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    International Nuclear Information System (INIS)

    Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

  16. 60 GHz 5-bit digital controlled phase shifter in a digital 40 nm CMOS technology without ultra-thick metals

    NARCIS (Netherlands)

    Gao, H.; Ying, K.; Matters-Kammerer, M.K.; Harpe, P.; Wang, B.; Liu, B.; Serdijn, W.A.; Baltus, P.G.M.

    2016-01-01

    A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to

  17. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    International Nuclear Information System (INIS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-01-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10 14 cm −2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation

  18. Thermal Management of Power Semiconductor Packages - Matching Cooling Technologies with Packaging Technologies (Presentation)

    Energy Technology Data Exchange (ETDEWEB)

    Bennion, K.; Moreno, G.

    2010-04-27

    Heat removal for power semiconductor devices is critical for robust operation. Because there are different packaging options, different thermal management technologies, and a range of applications, there is a need for a methodology to match cooling technologies and package configurations to target applications. To meet this need, a methodology was developed to compare the sensitivity of cooling technologies on the overall package thermal performance over a range of power semiconductor packaging configurations. The results provide insight into the trade-offs associated with cooling technologies and package configurations. The approach provides a method for comparing new developments in power semiconductor packages and identifying potential thermal control technologies for the package. The results can help users select the appropriate combination of packaging configuration and cooling technology for the desired application.

  19. Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology

    CERN Document Server

    Firlej, M; Idzik, M; Moron, J; Swientek, K

    2014-01-01

    The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz–3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz–1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6mW was measured at 1 GHz for a division factor equal to 10.

  20. Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology

    International Nuclear Information System (INIS)

    Firlej, M; Fiutowski, T; Idzik, M; Moroń, J; Świentek, K

    2014-01-01

    The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz–3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz–1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10

  1. RAPS: an innovative active pixel for particle detection integrated in CMOS technology

    International Nuclear Information System (INIS)

    Passeri, Daniele; Placidi, Pisana; Verducci, Leonardo; Ciampolini, Paolo; Matrella, Guido; Marras, Alessandro; Bilei, G.M.

    2004-01-01

    In this paper we discuss some design, implementation and test issues, with respect to the development of the RAPS01 chip in the framework of the Radiation Active Pixel Sensors (RAPS) INFN project. The project aimed at verifying feasibility of smart, high-resolution pixel arrays with a fully standard, submicron CMOS technology for particle detection purposes. Layout optimization of the pixel, including sensitive element and local read and amplification circuits has been carried out. Different basic pixel schemes and read-out options have been proposed and devised. Chip fabrication has been completed and test phase is now under way: to this purpose a suitable test environment has been devised and test strategies have been planned

  2. Dual Comb Unit High-g Accelerometer Based on CMOS-MEMS Technology

    Directory of Open Access Journals (Sweden)

    Mehrdad Mottaghi

    2009-04-01

    Full Text Available In this paper a capacitive based high-g accelerometer with superior level of sensitivity is presented. It takes advantage of dual comb unit configuration and surface micromachining fabrication process. All aspects of mechanical design such as sensor structure, modal analysis, energy dissipations, dynamic response and stresses in moving structure as well as anchors are described. Electrical circuit based on CMOS technology and its output signal is presented. Fabrication process and packaging are also discussed. The proposed sensor can endure impact loads up to 120,000 g (g = 9.81 m.s-2 and achieves 16.75 µV.g-1 sensitivity with 5 V bridge excitation voltage. Main resonant frequency of structure is found to be 42.4 kHz. Intended applications of suggested sensor include military and aerospace industries as well as field of impact engineering.

  3. Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

    Science.gov (United States)

    Muhamad, M.; Soin, N.; Ramiah, H.

    2018-03-01

    This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

  4. Radiation tolerance study of a commercial 65 nm CMOS technology for high energy physics applications

    Energy Technology Data Exchange (ETDEWEB)

    Ding, Lili, E-mail: lili03.ding@gmail.com [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); State Key Laboratory of Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, Xi' an (China); Gerardin, Simone [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Bagatin, Marta [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); Bisello, Dario [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Mattiazzo, Serena [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); Paccagnella, Alessandro [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy)

    2016-09-21

    This paper reports the radiation tolerance study of a commercial 65 nm technology, which is a strong candidate for the Large Hadron Collider applications. After exposure to 3 MeV protons till 1 Grad dose, the 65 nm CMOS transistors, especially the pMOSFETs, showed severe long-term degradation mainly in the saturation drain currents. There were some differences between the degradation levels in the nMOSFETs and the pMOSFETs, which were likely attributed to the positive charges trapped in the gate spacers. After exposure to heavy ions till multiple strikes, the pMOSFETs did not show any sudden loss of drain currents, the degradations in the characteristics were negligible.

  5. A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel.

    Science.gov (United States)

    Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien

    2017-12-05

    A submicron pixel's light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e - /s at 60 °C, an ultra-low read noise of 0.90 e - ·rms, a high full well capacity (FWC) of 4100 e - , and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.

  6. Rare resource supply crisis and solution technology for semiconductor manufacturing

    Science.gov (United States)

    Fukuda, Hitomi; Hu, Sophia; Yoo, Youngsun; Takahisa, Kenji; Enami, Tatsuo

    2016-03-01

    There are growing concerns over future environmental impact and earth resource shortage throughout the world and in many industries. Our semiconductor industry is not excluded. "Green" has become an important topic as production volume become larger and more powerful. Especially, the rare gases are widely used in semiconductor manufacturing because of its inertness and extreme chemical stability. One major component of an Excimer laser system is Neon. It is used as a buffer gas for Argon (Ar) and Krypton (Kr) gases used in deep ultraviolet (DUV) lithography laser systems. Since Neon gas accounting for more than 96% of the laser gas mixture, a fairly large amount of neon gas is consumed to run these DUV lasers. However, due to country's instability both in politics and economics in Ukraine, the main producer of neon gas today, supply reduction has become an issue and is causing increasing concern. This concern is not only based on price increases, but has escalated to the point of supply shortages in 2015. This poses a critical situation for the semiconductor industry, which represents the leading consumer of neon gas in the world. Helium is another noble gas used for Excimer laser operation. It is used as a purge gas for optical component modules to prevent from being damaged by active gases and impurities. Helium has been used in various industries, including for medical equipment, linear motor cars, and semiconductors, and is indispensable for modern life. But consumption of helium in manufacturing has been increased dramatically, and its unstable supply and price rise has been a serious issue today. In this article, recent global supply issue of rare resources, especially Neon gas and Helium gas, and its solution technology to support semiconductor industry will be discussed.

  7. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1984-01-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

  8. Absorbed dose by a CMOS in radiotherapy

    International Nuclear Information System (INIS)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  9. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  10. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, Mohamed N.; Wang, Q. X.; Alshareef, Husam N.

    2014-01-01

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling

  11. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    Havranek, Miroslav

    2014-09-01

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  12. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Havranek, Miroslav

    2014-09-15

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  13. CMOS/SOS processing

    Science.gov (United States)

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  14. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1983-09-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

  15. The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

    Science.gov (United States)

    Tsujimura, Manabu

    2016-06-01

    For the last 60 years, the development of cutting-edge semiconductor devices has strongly emphasized scaling; the effort to scale down current CMOS devices may well achieve the target of 5 nm nodes by 2020. Planarization by chemical mechanical polishing (CMP), is one technology essential for supporting scaling. This paper summarizes the history of CMP transitions in the planarization process as well as the changing degree of planarity required, and, finally, introduces innovative technologies to meet the requirements. The use of CMP was triggered by the replacement of local oxidation of silicon (LOCOS) as the element isolation technology by shallow trench isolation (STI) in the 1980s. Then, CMP’s use expanded to improving embedability of aluminum wiring, tungsten (W) contacts, Cu wiring, and, more recently, to its adoption in high-k metal gate (HKMG) and FinFET (FF) processes. Initially, the required degree of planarity was 50 nm, but now 0 nm is required. Further, zero defects on a post-CMP wafer is now the goal, and it is possible that zero psi CMP loading pressure will be required going forward. Soon, it seems, everything will have to be “zero” and perfect. Although the process is also chemical in nature, the CMP process is actually mechanical with a load added using slurry particles several tens of nm in diameter. Zero load in the loading process, zero nm planarity with no trace of processing, and zero residual foreign material, including the very slurry particles used in the process, are all required. This article will provide an overview of how to achieve these new requirements and what technologies should be employed.

  16. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

    2017-01-01

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

  17. Characterization of pixel sensor designed in 180 nm SOI CMOS technology

    Science.gov (United States)

    Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

    2018-01-01

    A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

  18. A 900 MHz RF energy harvesting system in 40 nm CMOS technology with efficiency peaking at 47% and higher than 30% over a 22dB wide input power range

    NARCIS (Netherlands)

    Wang, J.; Jiang, Y.; Dijkhuis, J.; Dolmans, G.; Gao, H.; Baltus, P.G.M.

    2017-01-01

    A 900 MHz RF energy harvesting system is proposed for a far-field wireless power transfer application. The topology of a single-stage CMOS rectifier loaded with an integrated boost DC-DC converter is implemented in a 40 nm CMOS technology. The co-design of a cross-coupled CMOS rectifier and an

  19. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    Directory of Open Access Journals (Sweden)

    Abdulaziz Alhoshany

    2017-08-01

    Full Text Available This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  20. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection.

    Science.gov (United States)

    Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N

    2017-08-23

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  1. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    KAUST Repository

    Alhoshany, Abdulaziz

    2017-08-23

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  2. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    KAUST Repository

    Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N.

    2017-01-01

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  3. Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

    International Nuclear Information System (INIS)

    Manazza, A.; Gaioni, L.; Re, V.

    2011-01-01

    This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end.

  4. First tests of CHERWELL, a Monolithic Active Pixel Sensor: A CMOS Image Sensor (CIS) using 180 nm technology

    Energy Technology Data Exchange (ETDEWEB)

    Mylroie-Smith, James, E-mail: j.mylroie-smith@qmul.ac.uk [Queen Mary, University of London (United Kingdom); Kolya, Scott; Velthuis, Jaap [University of Bristol (United Kingdom); Bevan, Adrian; Inguglia, Gianluca [Queen Mary, University of London (United Kingdom); Headspith, Jon; Lazarus, Ian; Lemon, Roy [Daresbury Laboratory, STFC (United Kingdom); Crooks, Jamie; Turchetta, Renato; Wilson, Fergus [Rutherford Appleton Laboratory, STFC (United Kingdom)

    2013-12-11

    The Cherwell is a 4T CMOS sensor in 180 nm technology developed for the detection of charged particles. Here, the different test structures on the sensor will be described and first results from tests on the reference pixel variant are shown. The sensors were shown to have a noise of 12 e{sup −} and a signal to noise up to 150 in {sup 55}Fe.

  5. Surface passivation technology for III-V semiconductor nanoelectronics

    International Nuclear Information System (INIS)

    Hasegawa, Hideki; Akazawa, Masamichi

    2008-01-01

    The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors' group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy (MBE)-grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented

  6. The challenge of sCMOS image sensor technology to EMCCD

    Science.gov (United States)

    Chang, Weijing; Dai, Fang; Na, Qiyue

    2018-02-01

    In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

  7. CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

    Science.gov (United States)

    Fossum, Eric R.

    1996-01-01

    The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

  8. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Drago Strle

    2015-07-01

    Full Text Available This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC. The DSP is currently implemented on FPGA.

  9. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    Science.gov (United States)

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-07-22

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

  10. 10-bit segmented current steering DAC in 90nm CMOS technology

    International Nuclear Information System (INIS)

    Bringas, R Jr; Dy, F; Gerasta, O J

    2015-01-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm 2 .The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources. (paper)

  11. A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

    International Nuclear Information System (INIS)

    Mei Niansong; Sun Yu; Lu Bo; Pan Yaohua; Huang Yumei; Hong Zhiliang

    2011-01-01

    This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL). An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL. We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch. The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply. The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and -118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset, respectively; and the reference frequency spur is below -77 dBc. The chip size is 0.32 mm 2 and the power consumption is 30.6 mW. (semiconductor integrated circuits)

  12. CMOS Cell Sensors for Point-of-Care Diagnostics

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  13. Characterization of semiconductor and frontier materials by nuclear microprobe technology

    International Nuclear Information System (INIS)

    Zhu Jieqing; Li Xiaolin; Yang Changyi; Lu Rongrong; Wang Jiqing; Guo Panlin

    2002-01-01

    The nuclear microprobe technology is used to characterize the properties of semiconductor and other frontier materials at the stages of their synthesis, modification, integration and application. On the basis of the beam current being used, the analytical nuclear microprobe techniques being used in this project can be divided into two categories: high beam current (PIXE, RBS, PEB) or low beam current (IBIC, STIM) techniques. The material properties measured are the thickness and composition of a composite surface on a SiC ceramic, the sputtering-induced surface segregation and depth profile change in a Ag-Cu binary alloy, the irradiation effects on the CCE of CVD diamond, the CCE profile at a polycrystalline CVD diamond film and a GaAs diode at different voltage biases and finally, the characterization of individual sample on an integrated material chip. (author)

  14. An 80x80 microbolometer type thermal imaging sensor using the LWIR-band CMOS infrared (CIR) technology

    Science.gov (United States)

    Tankut, Firat; Cologlu, Mustafa H.; Askar, Hidir; Ozturk, Hande; Dumanli, Hilal K.; Oruc, Feyza; Tilkioglu, Bilge; Ugur, Beril; Akar, Orhan Sevket; Tepegoz, Murat; Akin, Tayfun

    2017-02-01

    This paper introduces an 80x80 microbolometer array with a 35 μm pixel pitch operating in the 8-12 μm wavelength range, where the detector is fabricated with the LWIR-band CMOS infrared technology, shortly named as CIR, which is a novel microbolometer implementation technique developed to reduce the detector cost in order to enable the use of microbolometer type sensors in high volume markets, such as the consumer market and IoT. Unlike the widely used conventional surface micromachined microbolometer approaches, MikroSens' CIR detector technology does not require the use of special high TCR materials like VOx or a-Si, instead, it allows to implement microbolometers with standard CMOS layers, where the suspended bulk micromachined structure is obtained by only few consecutive selective MEMS etching steps while protecting the wirebond pads with a simple lithograpy step. This approach not only reduces the fabrication cost but also increases the production yield. In addition, needing simple subtractive post-CMOS fabrication steps allows the CIR technology to be carried out in any CMOS and MEMS foundry in a truly fabless fashion, where industrially mature and Au-free wafer level vacuum packaging technologies can also be carried out, leading to cost advantage, simplicity, scalability, and flexibility. The CIR approach is used to implement an 80x80 FPA with 35 μm pixel pitch, namely MS0835A, using a 0.18 μm CMOS process. The fabricated sensor is measured to provide NETD (Noise Equivalent Temperature Difference) value of 163 mK at 17 fps (frames per second) and 71 mK at 4 fps with F/1.0 optics in a dewar environment. The measurement results of the wafer level vacuum packaged sensors with one side AR coating shows an NETD values of 112 mK at 4 fps with F/1.1 optics, i.e., demonstrates a good performance for high volume low-cost applications like advanced presence detection and human counting applications. The CIR approach of MikroSens is scalable and can be used to

  15. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  16. Characterization of ultrathin insulators in CMOS technology: Wearout and failure mechanisms due to processing and operation

    Science.gov (United States)

    Okandan, Murat

    In the CMOS technology the gate dielectric is the most critical layer, as its condition directly dictates the ultimate performance of the devices. In this thesis, the wear-out and failure mechanisms in ultra-thin (around 50A and lower) oxides are investigated. A new degradation phenomenon, quasi-breakdown (or soft-breakdown), and the annealing and stressing behavior of devices after quasi-breakdown are considered in detail. Devices that are in quasi-breakdown continue to operate as switches, but the gate leakage current is two orders of magnitude higher than the leakage in healthy devices and the stressing/annealing behavior of the devices are completely altered. This phenomenon is of utmost interest, since the reduction in SiO2 dielectric thickness has reached its physical limits, and the quasi-breakdown behavior is seen to dominate as a failure mode in this regime. The quasi-breakdown condition can be brought on by stresses during operation or processing. To further study this evolution through stresses and anneals, cyclic current-voltage (I-V) measurement has been further developed and utilized in this thesis. Cyclic IV is a simple and fast, two terminal measurement technique that looks at the transient current flowing in an MOS system during voltage sweeps from accumulation to inversion and back. During these sweeps, carrier trapping/detrapping, generation and recombination are observed. An experimental setup using a fast electrometer and analog to digital conversion (A/D) card and the software for control of the setup and data analysis were also developed to gain further insight into the detailed physics involved. Overall, the crucial aspects of wear-out and quasi-breakdown of ultrathin dielectrics, along with the methods for analyzing this evolution are presented in this thesis.

  17. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  18. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  19. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Science.gov (United States)

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  20. 1-bit sub threshold full adders in 65nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Tuan Vu, Cao

    In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results...

  1. A 100 MHz synchronized OEIC photoreceiver in n-well, CMOS technology

    DEFF Research Database (Denmark)

    Kamel, Ayadi; Danielsen, Per Lander

    1998-01-01

    We analyze and demonstrate a synchronized CMOS photoreceiver for the conversion of optical inputs of pulse-light to electronic digital signals. Small-signal and photonic analysis of the proposed circuit are detailed. The photoreceiver was operated at 100 MHz with only 13.3 fJ/pulse of 830-nm inpu...

  2. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  3. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

    International Nuclear Information System (INIS)

    Li Chen; Liao Huailin; Huang Ru; Wang Yangyuan

    2008-01-01

    In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

  4. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  5. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  6. Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

    International Nuclear Information System (INIS)

    Anelli, Giovanni Maria

    2000-01-01

    The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

  7. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    CERN Document Server

    Miucci, A; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; Rosa, A.La; Muenstermann, D.; George, M.; Grosse-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J.C.; Liu, J; Barbero, M.; Rozanov, A

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. 1Corresponding author. c CERN 2014, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/9/05/C050642014 JINST 9 C05064 A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation a...

  8. Experimental demonstration of CMOS-compatible long-range dielectric-loaded surface plasmon-polariton waveguides (LR-DLSPPWs)

    DEFF Research Database (Denmark)

    Zektzer, Roy; Desiatov, Boris; Mazurski, Noa

    2015-01-01

    We demonstrate the design, fabrication and experimental characterization of long-range dielectric-loaded surface plasmon-polariton waveguides (LR-DLSPPWs) that are compatible with complementary metal-oxide semiconductor (CMOS) technology. The demonstrated waveguides feature good mode confinement...

  9. Advanced excimer laser technologies enable green semiconductor manufacturing

    Science.gov (United States)

    Fukuda, Hitomi; Yoo, Youngsun; Minegishi, Yuji; Hisanaga, Naoto; Enami, Tatsuo

    2014-03-01

    "Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental "green cost" of laser operations in high-volume manufacturing environment (HVM) - primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton's Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry's transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

  10. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Havranek, Miroslav [University of Bonn, Bonn (Germany); Institute of Physics of the Academy of Sciences, Prague (Czech Republic)

    2015-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges coming from the higher hit rate will have to be solved by designing faster and more complex circuits, while at the same time keeping in mind very high radiation hardness requirements. Therefore matching the specification set by the high luminosity upgrade requires a large R and D effort. Our group is participating in such a joint development * namely the RD53 collaboration * which goal is to design a new pixel chip using an advanced 65 nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology will be shown together with a comparison with older technologies (130 nm, 250 nm). Most of the talk is allocated to presenting some of the circuits designed by our group, along with their performance measurement results.

  11. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  12. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    International Nuclear Information System (INIS)

    Barnaby, Hugh J.; Mclain, Michael; Esqueda, Ivan Sanchez

    2007-01-01

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits

  13. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric,I et al.

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  14. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  15. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    Directory of Open Access Journals (Sweden)

    A. Schmitz

    2005-01-01

    Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  16. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  17. Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

    Science.gov (United States)

    Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

    2018-01-01

    We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

  18. Semiconductor Manufacturing equipment introduction

    International Nuclear Information System (INIS)

    Im, Jong Sun

    2001-02-01

    This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

  19. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  20. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

    CERN Document Server

    Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

    2000-01-01

    A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

  1. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  2. Technological and organizational diversity and technical advance in the early history of the American semiconductor industry

    Science.gov (United States)

    Cohen, W.; Holbrook, D.; Klepper, S.

    1994-06-01

    This study examines the early years of the semiconductor industry and focuses on the roles played by different size firms in technologically innovative processes. A large and diverse pool of firms participated in the growth of the industry. Three related technological areas were chosen for in-depth analysis: integrated circuits, materials technology, and device packaging. Large business producing vacuum tubes dominated the early production of semiconductor devices. As the market for new devices grew during the 1950's, new firms were founded and existing firms from other industries, e.g. aircraft builders and instrument makers, began to pursue semiconductor electronics. Small firms began to cater to the emerging industry by supplying materials and equipment. These firms contributed to the development of certain aspects of one thousand firms that were playing some part in the semiconductor industry.

  3. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Science.gov (United States)

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  4. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  5. System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

    Science.gov (United States)

    Lee, Sung Pil

    2015-10-01

    Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

  6. Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

    Science.gov (United States)

    Biyikli, Necmi; Haider, Ali

    2017-09-01

    In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

  7. Neutron absorbed dose in a pacemaker CMOS

    International Nuclear Information System (INIS)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  8. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  9. An investigation into the use of CMOS active pixel technology in image-guided radiotherapy

    International Nuclear Information System (INIS)

    Osmond, J P F; Holland, A D; Harris, E J; Ott, R J; Evans, P M; Clark, A T

    2008-01-01

    The increased intelligence, read-out speed, radiation hardness and potential large size of CMOS active pixel sensors (APS) gives them a potential advantage over systems currently used for verification of complex treatments such as IMRT and the tracking of moving tumours. The aim of this work is to investigate the feasibility of using an APS-based system to image the megavoltage treatment beam produced by a linear accelerator (Linac), and to demonstrate the logic which may ultimately be incorporated into future sensor and FPGA design to evaluate treatment and track motion. A CMOS APS was developed by the MI 3 consortium and incorporated into a megavoltage imaging system using the standard lens and mirror configuration employed in camera-based EPIDs. The ability to resolve anatomical structure was evaluated using an Alderson RANDO head phantom, resolution evaluated using a quality control (QC3) phantom and contrast using an in-house developed phantom. A complex intensity-modulated radiotherapy (IMRT) treatment was imaged and two algorithms were used to determine the field-area and delivered dose, and the position of multi-leaf collimator (MLC) leaves off-line. Results were compared with prediction from the prescription and found to agree within a single image frame time for dose delivery and 0.02-0.03 cm for the position of collimator leaves. Such a system therefore shows potential as the basis for an on-line verification system capable of treatment verification and monitoring patient motion

  10. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  11. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  12. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    Science.gov (United States)

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Obermann, Theresa

    2017-06-15

    The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n{sup +}-implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e{sup -} to 3000 e{sup -} while the noise is 30 e{sup -} due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10{sup 14} neutrons/cm{sup 2} the performance suffers from the radiation damage leading to a signal of 1000 e{sup -} and a higher noise of 60 e{sup -} due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10{sup 14} particles/cm{sup 2}. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10{sup 14} particles/cm{sup 2}). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC

  14. Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

    International Nuclear Information System (INIS)

    Obermann, Theresa

    2017-06-01

    The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n + -implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e - to 3000 e - while the noise is 30 e - due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10 14 neutrons/cm 2 the performance suffers from the radiation damage leading to a signal of 1000 e - and a higher noise of 60 e - due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10 14 particles/cm 2 . Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10 14 particles/cm 2 ). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget

  15. Radiation processing of polymers and semiconductors at the Institute of Nuclear Chemistry and Technology

    International Nuclear Information System (INIS)

    Zimek, Z.; Przybytniak, G.; Kaluska, I.

    2006-01-01

    R(and)D studies in the field of radiation technology in Poland are mostly concentrated at the Institute of Nuclear Chemistry and Technology (INCT). The results of the INCT works on polymer and semiconductor modification have been implemented in various branches of national economy, particularly in industry and medicine. Radiation technology for polymer modification was implemented in the middle of the 1970-ties. Among others, the processes of irradiation and heat shrinkable products expansion have been developed. The transfer of this technology to Polish industry was performed in the middle of the 1980-ties. The present study aims at the formulation of new PE composites better suited to new generation of heat shrinkable products, for example, a new generation of hot-melt adhesives has been developed to meet specific requirements of customers. Modified polypropylene was used for the production of medical devices sterilized by radiation, especially disposable syringes, to overcome the low radiation resistance of the basic material. Modified polypropylene (PP-M) has been formulated at the INCT to provide material suitable for medical application and radiation sterilization process. Modification of semiconductor devices by EB was applied on an industrial scale since 1978 when the INCT and the LAMINA semiconductor factory successfully adopted that technology to improve specific semiconductor devices. This activity is continued on commercial basis where the INCT facilities served to contract irradiation of certain semiconductor devices according to the manufacturing program of the Polish factory and customers from abroad. (author)

  16. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  17. Integrated Cu-based TM-pass polarizer using CMOS technology platform

    KAUST Repository

    Ng, Tien Khee

    2010-01-01

    A transverse-magnetic-pass (TM-pass) copper (Cu) polarizer is proposed and analyzed using the previously published two-dimensional Method-of-Lines beam-propagation model. The proposed polarizer exhibits a simulated high-pass filter characteristics, with TM0 and TE0 mode transmissivity of >70% and <5%, respectively, in the wavelength regime of 1.2-1.6 μm. The polarization extinction ratio (PER) given by 10 log10 (PTM0)/(PTE0) is +11.5 dB across the high-pass wavelength regime. To the best of the authors\\' knowledge, we report here the smallest footprint CMOS-platform compatible TM-polarizer.

  18. CCST [Center for Compound Semiconductor Technology] research briefs

    International Nuclear Information System (INIS)

    Zipperian, T.E.; Voelker, E.R.

    1989-12-01

    This paper discusses the following topics: theoretical predictions of valence and conduction band offsets in III-V semiconductors; reflectance modulation of a semiconductor superlattice optical mirror; magnetoquantum oscillations of the phonon-drag thermoelectric power in quantum wells; correlation between photoluminescence line shape and device performance of p-channel strained-layer materials; control of threading dislocations in heteroepitaxial structures; improved growth of CdTe on GaAs by patterning; role of structure threading dislocations in relaxation of highly strained single-quantum-well structures; InAlAs growth optimization using reflection mass spectrometry; nonvolatile charge storage in III-V heterostructures; optically triggered thyristor switches; InAsSb strained-layer superlattice infrared detectors with high detectivities; resonant periodic gain surface-emitting semiconductor lasers; performance advantages of strained-quantum-well lasers in AlGaAs/InGaAs; optical integrated circuit for phased-array radar antenna control; and deposition and novel device fabrication from Tl 2 Ca 2 Ba 2 Cu 3 O y thin films

  19. Life-cycle assessment of semiconductors

    CERN Document Server

    Boyd, Sarah B

    2012-01-01

    Life-Cycle Assessment of Semiconductors presents the first and thus far only available transparent and complete life cycle assessment of semiconductor devices. A lack of reliable semiconductor LCA data has been a major challenge to evaluation of the potential environmental benefits of information technologies (IT). The analysis and results presented in this book will allow a higher degree of confidence and certainty in decisions concerning the use of IT in efforts to reduce climate change and other environmental effects. Coverage includes but is not limited to semiconductor manufacturing trends by product type and geography, unique coverage of life-cycle assessment, with a focus on uncertainty and sensitivity analysis of energy and global warming missions for CMOS logic devices, life cycle assessment of flash memory and life cycle assessment of DRAM. The information and conclusions discussed here will be highly relevant and useful to individuals and institutions. The book also: Provides a detailed, complete a...

  20. Radiation immune RAM semiconductor technology for the 80's. [Random Access Memory

    Science.gov (United States)

    Hanna, W. A.; Panagos, P.

    1983-01-01

    This paper presents current and short term future characteristics of RAM semiconductor technologies which were obtained by literature survey and discussions with cognizant Government and industry personnel. In particular, total ionizing dose tolerance and high energy particle susceptibility of the technologies are addressed. Technologies judged compatible with spacecraft applications are ranked to determine the best current and future technology for fast access (less than 60 ns), radiation tolerant RAM.

  1. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  2. FEOL technology trend

    International Nuclear Information System (INIS)

    Taur, Y.; Ning, T.H.

    1998-01-01

    Trends in front-end-of-line technology are discussed. At the chip level, many of the important parameters are published in the National Technology Roadmap for Semiconductors in 1994. At the device and circuit level, both bipolar and CMOS are scalable. However, the large standby power of bipolar circuits severely limits the integration level of bipolar chips. The inherently low standby power of CMOS, on the contrary, allows the integration level of CMOS circuits to continue increasing with scaling. In reality, both the electric field and power density of CMOS devices have been gradually rising over the generations owing to non-scaling effects of thermal voltage and silicon bandgap. As power supply voltage reaches 1.5V and below, circuit performance can only be gained at the expense of higher active or standby power of the chip. Implications of device scaling on contact and silicide technology are addressed. Trends of local and global interconnect scaling are discussed. (orig.)

  3. New era of silicon technologies due to radical reaction based semiconductor manufacturing

    International Nuclear Information System (INIS)

    Ohmi, Tadahiro; Hirayama, Masaki; Teramoto, Akinobu

    2006-01-01

    Current semiconductor technology, the so-called the molecule reaction based semiconductor manufacturing, now faces a very severe standstill due to the drastic increase of gate leakage currents and drain leakage currents. Radical reaction based semiconductor manufacturing has been developed to completely overcome the current standstill by introducing microwave excited high density plasma with very low electron temperatures and without accompanying charge-up damage. The introduction of radical reaction based semiconductor manufacturing has made it possible to fabricate LSI devices on any crystal orientation Si substrate surface as well as (100) Si substrate surfaces, and to eliminate a very severe limitation to the antenna ratio in the circuit layout patterns, which is strictly limited to less than 100-200 in order to obtain a relatively high production yield. (topical review)

  4. Micromachined high-performance RF passives in CMOS substrate

    International Nuclear Information System (INIS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  5. CMOS SPAD-based image sensor for single photon counting and time of flight imaging

    OpenAIRE

    Dutton, Neale Arthur William

    2016-01-01

    The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications....

  6. Semiconductor technology in protein kinase research and drug discovery: sensing a revolution.

    Science.gov (United States)

    Bhalla, Nikhil; Di Lorenzo, Mirella; Estrela, Pedro; Pula, Giordano

    2017-02-01

    Since the discovery of protein kinase activity in 1954, close to 600 kinases have been discovered that have crucial roles in cell physiology. In several pathological conditions, aberrant protein kinase activity leads to abnormal cell and tissue physiology. Therefore, protein kinase inhibitors are investigated as potential treatments for several diseases, including dementia, diabetes, cancer and autoimmune and cardiovascular disease. Modern semiconductor technology has recently been applied to accelerate the discovery of novel protein kinase inhibitors that could become the standard-of-care drugs of tomorrow. Here, we describe current techniques and novel applications of semiconductor technologies in protein kinase inhibitor drug discovery. Copyright © 2016 Elsevier Ltd. All rights reserved.

  7. Semiconductor measurement technology: reliability technology for cardiac pacemakers 2: a workshop report, 1976

    International Nuclear Information System (INIS)

    Schafft, H.A.

    1977-01-01

    Summaries are presented of 12 invited talks on the following topics: the procurement and assurance of high reliability electronic parts, leak rate and moisture measurements, pacemaker batteries, and pacemaker leads. The workshop, second in a series, was held in response to strong interest expressed by the pacemaker community to address technical questions relevant to the enhancement and assurance of cardiac pacemaker reliability. Discussed at the workshop were a process validation wafer concept for assuring process uniformity in device chips; screen tests for assuring reliable electronic parts; reliability prediction; reliability comparison of semiconductor technologies; mechanisms of short-circuiting dendritic growths; details of helium and radioisotope leak test methods; a study to correlate package leak rates, as measured with test gasses, and actual moisture infusion; battery life prediction; microcalorimetric measurements to nondestructively evaluate batteries for pacemakers; and an engineer's and a physician's view of the present status of pacemaker leads. References are included with most of the reports

  8. Ohmic metallization technology for wide band-gap semiconductors

    International Nuclear Information System (INIS)

    Iliadis, A.A.; Vispute, R.D.; Venkatesan, T.; Jones, K.A.

    2002-01-01

    Ohmic contact metallizations on p-type 6H-SiC and n-type ZnO using a novel approach of focused ion beam (FIB) surface-modification and direct-write metal deposition will be reviewed, and the properties of such focused ion beam assisted non-annealed contacts will be reported. The process uses a Ga focused ion beam to modify the surface of the semiconductor with different doses, and then introduces an organometallic compound in the Ga ion beam, to effect the direct-write deposition of a metal on the modified surface. Contact resistance measurements by the transmission line method produced values in the low 10 -4 Ω cm 2 range for surface-modified and direct-write Pt and W non-annealed contacts, and mid 10 -5 Ω cm 2 range for surface-modified and pulse laser deposited TiN contacts. An optimum Ga surface-modification dosage window is determined, within which the current transport mechanism of these contacts was found to proceed mainly by tunneling through the metal-modified-semiconductor interface layer

  9. Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology

    CERN Document Server

    Kuczynska, Marika; Bugiel, Szymon; Firlej, Miroslaw; Fiutowski, Tomasz; Idzik, Marek; Michelis, Stefano; Moron, Jakub; Przyborowski, Dominik; Swientek, Krzysztof

    2015-01-01

    A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, w...

  10. Deep n-well MAPS in a 130 nm CMOS technology: Beam test results

    International Nuclear Information System (INIS)

    Neri, N.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell'Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M.A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Paoloni, E.; Piendibene, M.

    2010-01-01

    We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13μm process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50x50μm 2 pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14μm. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.

  11. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  12. A low-power integrated humidity CMOS sensor by printing-on-chip technology.

    Science.gov (United States)

    Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

    2014-05-23

    A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  13. Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    J. Sturm

    2014-04-01

    Full Text Available The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends.

  14. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    Venuto, D. de; Corsi, F.; Ohletz, M.J.

    1999-01-01

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  15. Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

    International Nuclear Information System (INIS)

    Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

    2011-01-01

    This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

  16. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Science.gov (United States)

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  17. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Directory of Open Access Journals (Sweden)

    Sukanta Roy

    Full Text Available Micro-electro mechanical system (MEMS based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM. A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  18. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  19. Flicker noise comparison of direct conversion mixers using Schottky and HBT dioderings in SiGe:C BiCMOS technology

    DEFF Research Database (Denmark)

    Michaelsen, Rasmus Schandorph; Johansen, Tom Keinicke; Tamborg, Kjeld

    2015-01-01

    In this paper, we present flicker noise measurements of two X-band direct conversion mixers implemented in a SiGe:C BiCMOS technology. Both mixers use a ring structure with either Schottky diodes or diode-connected HBTs for double balanced operation. The mixers are packaged in a metal casing on a...... circuit demonstrates a 1/f noise corner frequency around 10 kHz....

  20. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Directory of Open Access Journals (Sweden)

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  1. Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

    CERN Document Server

    Kluit, R; Gromov, V

    2007-01-01

    The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

  2. SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

    Energy Technology Data Exchange (ETDEWEB)

    MCBRAYER,JOHN D.

    2000-12-01

    This report summarizes the results of work conducted by the Semiconductor Manufacturing Technologies Program at Sandia National Laboratories (Sandia) during 1999. This work was performed by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaF{sub 2}); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program.

  3. InP-DHBT-on-BiCMOS technology with fT/fmax of 400/350 GHz for heterogeneous integrated millimeter-wave sources

    DEFF Research Database (Denmark)

    Kraemer, Tomas; Ostermay, Ina; Jensen, Thomas

    2013-01-01

    -100 GHz. The 0.8 × 5 μm2 InP DHBTs show fT/fmax of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in Bi......This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with

  4. 32 x 16 CMOS smart pixel array for optical interconnects

    Science.gov (United States)

    Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

    2000-05-01

    Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

  5. Investigation of Toshiba 130nm CMOS process as a possible candidate for active silicon sensors in HEP and X-ray experiments

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yunan; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruhe Institute of Technology, Karlsruhe (Germany)

    2015-07-01

    Following the advances of commercial semiconductor manufacturing technologies there has recently been an increased interest within experimental physics community in applying CMOS manufacturing processes to developing active silicon sensors. Possibility of applying high voltage bias combined with high resistivity substrate allows for better depletion of sensor and therefore quicker and more efficient charge collection. One of processes that accommodates those features is Toshiba 130 nm CMOS technology (CMOS3E). Within our group a test chip was designed to examine the suitability of this technology for physics experiment (both for HEP and X-ray imaging). Design consisted of 4 pixel matrices with total of 12 different pixel flavors allowing for evaluation of various pixel geometries and architectures in terms of depletion depth, noise performance, charge collection efficiency, etc. During this talk initial outcome of this evaluation is presented, starting with brief introduction to technology itself, followed by results of TCAD simulations, description of final design and first measurements results.

  6. Proceedings of defect engineering in semiconductor growth, processing and device technology

    International Nuclear Information System (INIS)

    Ashok, S.; Chevallier, J.; Sumino, K.; Weber, E.

    1992-01-01

    This volume results from a symposium that was part of the 1992 Spring Meeting of the Materials Research Society, held in San Francisco from April 26 to May 1, 1992. The symposium, entitled Defect Engineering in Semiconductor Growth, Processing and Device Technology, was the first of its kind at MRS and brought together academic and industrial researchers with varying perspectives on defects in semiconductors. Its aim was to go beyond defect control, and focus instead on deliberate and controlled introduction and manipulation of defects in order to engineer some desired properties in semiconductor materials and devices. While the concept of defect engineering has at least a vague perception in techniques such as impurity/defect gettering and the use of the EL2 level in GaAs, more extensive as well as subtle uses of defects are emerging to augment the field. This symposium was intended principally to encourage creative new applications of defects in all aspects of semiconductor technology. The organization of this proceedings volume closely follows the topics around which the sessions were built. The papers on grown-in defects in bulk crystals deal with overviews of intrinsic and impurity-related defects, their influence on electrical, optical and mechanical properties, as well as the use of impurities to arrest certain types of defects during growth and defects to control growth. The issues addressed by the papers on defects in thin films include impurity and stoichiometry control, defects created by plasmas and the use of electron/ion irradiation for doping control

  7. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  8. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  9. Monolithic pixel detectors in a 0.13μm CMOS technology with sensor level continuous time charge amplification and shaping

    International Nuclear Information System (INIS)

    Ratti, L.; Manghisoni, M.; Re, V.; Speziali, V.; Traversi, G.; Bettarini, S.; Calderini, G.; Cenci, R.; Giorgi, M.; Forti, F.; Morsani, F.; Rizzo, G.

    2006-01-01

    This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13μm CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach

  10. [Application of next-generation semiconductor sequencing technologies in genetic diagnosis of inherited cardiomyopathies].

    Science.gov (United States)

    Zhao, Yue; Zhang, Hong; Xia, Xue-shan

    2015-07-01

    Inherited cardiomyopathy is the most common hereditary cardiac disease. It also causes a significant proportion of sudden cardiac deaths in young adults and athletes. So far, approximately one hundred genes have been reported to be involved in cardiomyopathies through different mechanisms. Therefore, the identification of the genetic basis and disease mechanisms of cardiomyopathies are important for establishing a clinical diagnosis and genetic testing. Next-generation semiconductor sequencing (NGSS) technology platform is a high-throughput sequencer capable of analyzing clinically derived genomes with high productivity, sensitivity and specificity. It was launched in 2010 by Life Technologies of USA, and it is based on a high density semiconductor chip, which was covered with tens of thousands of wells. NGSS has been successfully used in candidate gene mutation screening to identify hereditary disease. In this review, we summarize these genetic variations, challenge and application of NGSS in inherited cardiomyopathy, and its value in disease diagnosis, prevention and treatment.

  11. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  12. The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

    International Nuclear Information System (INIS)

    Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

    2006-01-01

    This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

  13. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  14. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Science.gov (United States)

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  15. Contribution to the study of the latch-up phenomenon in CMOS technologies

    International Nuclear Information System (INIS)

    Leroux, Charles

    1988-01-01

    The latch-up phenomenon is due to the presence of a parasite PNPN structure between a circuit supply and the ground. This structure may pass from its usual high impedance state to a low impedance state (few Ohms). The author reports the development of a test methodology able to identify this phenomenon. An analytic model has been developed which takes several issues into account: the three-dimensional aspect of resistances of this structure, the strong injection and its consequences. A new element is introduced which allows the phenomenon retention. This model without adjustment parameter gives good results with respect to experiment. A strategy of optimisation of these technologies with respect to the latch-up effect has also been defined. It leads to the production of a batch for which structures with a low insulation distance between sources of transistors of opposite type (four microns) display a hold voltage greater than the supply voltage (five volts) [fr

  16. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  17. Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

    Science.gov (United States)

    Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

    2018-04-01

    The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

  18. Technological parameter and experimental set-up influences on latch-up triggering level in bulk CMOS device

    International Nuclear Information System (INIS)

    Dubuc, J.P.; Azais, B.; Murcia, M. de

    1994-01-01

    This paper deals with experimental and simulation results on latch-up triggered by an electrical or X-rays pulse in CMOS/bulk devices. Test condition influences as well as the great importance of process parameters on latch-up immunity are emphasized. (author). 10 refs., 19 figs., 1 tab

  19. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Science.gov (United States)

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  20. Design of millimeter-wave MEMS-based reconfigurable front-end circuits using the standard CMOS technology

    International Nuclear Information System (INIS)

    Chang, Chia-Chan; Hsieh, Sheng-Chi; Chen, Chien-Hsun; Huang, Chin-Yen; Yao, Chun-Han; Lin, Chun-Chi

    2011-01-01

    This paper describes the designs of three reconfigurable CMOS-MEMS front-end components for V-/W-band applications. The suspended MEMS structure is released through post-CMOS micromachining. To achieve circuit reconfigurability, dual-state and multi-state fishbone-beam-drive actuators are proposed herein. The reconfigurable bandstop is fabricated in a 0.35 µm CMOS process with the chip size of 0.765 × 0.98 mm 2 , showing that the stop-band frequency can be switched from 60 to 50 GHz with 40 V actuation voltage. The measured isolation is better than 38 dB at 60 GHz and 34 dB at 50 GHz, respectively. The bandpass filter-integrated single-pole single-throw switch, using the 0.18 µm CMOS process, demonstrates that insertion loss and return loss are better than 6.2 and 15 dB from 88 to 100 GHz in the on-state, and isolation is better than 21 dB in the off-state with an actuation voltage of 51 V. The chip size is 0.7 × 1.04 mm 2 . The third component is a reconfigurable slot antenna fabricated in a 0.18 µm CMOS process with the chip size of 1.2 × 1.2 mm 2 . By utilizing the multi-state actuators, the frequencies of this antenna can be switched to 43, 47, 50.5, 54, 57.5 GHz with return loss better than 20 dB. Those circuits demonstrate good RF performance and are relatively compact by employing several size miniaturizing techniques, thereby enabling a great potential for the future single-chip transceiver.

  1. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    Science.gov (United States)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  2. Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

    Science.gov (United States)

    Hong, Augustin Jinwoo

    Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

  3. Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

    Science.gov (United States)

    Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

    2018-04-01

    We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

  4. Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

    2017-07-15

    A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  5. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  6. An integrated CMOS high data rate transceiver for video applications

    International Nuclear Information System (INIS)

    Liang Yaping; Sun Lingling; Che Dazhi; Liang Cheng

    2012-01-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at −3 dBm output power. (semiconductor integrated circuits)

  7. Nano/CMOS architectures using a field-programmable nanowire interconnect

    International Nuclear Information System (INIS)

    Snider, Gregory S; Williams, R Stanley

    2007-01-01

    A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

  8. An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

    Science.gov (United States)

    Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

    2012-12-17

    An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

  9. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  10. CMOS image sensor-based immunodetection by refractive-index change.

    Science.gov (United States)

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

  11. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  12. A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

    International Nuclear Information System (INIS)

    Zhang Mingke; Hu Qingsheng

    2013-01-01

    This paper presents a 0.18 μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm 2 . (semiconductor integrated circuits)

  13. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

    International Nuclear Information System (INIS)

    Lei Qianqian; Lin Min; Shi Yin

    2013-01-01

    A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from −65 to −8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics. (semiconductor integrated circuits)

  14. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  15. A Multipurpose CMOS Platform for Nanosensing.

    Science.gov (United States)

    Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

    2016-11-30

    This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  16. Status and progress in ion implantation technology for semiconductor device manufacturing

    International Nuclear Information System (INIS)

    Takahashi, Noriyuki

    1998-01-01

    Rapid growth in implant applications in the fabrication of semiconductors has encouraged a dramatic increase in the range of energies, beam currents and ion species used. The challenges of a wider energy range, higher beam currents, continued reduction in contamination, improved angle integrity and larger substrates have motivated the development of many innovations. Advanced processes in submicron device production uses up to twenty implantation steps. Thus the outstanding growth of this industry has led to the evolution of a thriving business of hundreds of implantation equipment systems each year with very specific requirements. The present paper reviews the principal process requirements which resulted in the evolution of the equipment technology, and describes the recent trends in the ion implanter technology all three principal categories: high current, medium current and high energy. (author)

  17. Large area SiC coating technology of RBSC for semiconductor processing component

    Energy Technology Data Exchange (ETDEWEB)

    Park, Ji Yeon; Kim, Weon Ju

    2001-06-01

    As the semiconductor process is developed for the larger area wafer and the larger-scale integration, the processing fixtures are required to have excellent mechanical and high temperature properties. This highlights the importance of silicon carbide-based materials as a substitute for quartz-based susceptors. In this study, SiC coating technology on reaction sintered (RS) SiC with thickness variation of +/- 10% within a diameter of 8 inch by low pressure chemical vapor deposition has been developed for making a plate type SiC fixture such as heater, baffle, etc., with a diameter of 12 inch. Additionally, a state of art on fabrication technology and products of the current commercial SiC fixtures has been described.

  18. Large area SiC coating technology of RBSC for semiconductor processing component

    International Nuclear Information System (INIS)

    Park, Ji Yeon; Kim, Weon Ju

    2001-06-01

    As the semiconductor process is developed for the larger area wafer and the larger-scale integration, the processing fixtures are required to have excellent mechanical and high temperature properties. This highlights the importance of silicon carbide-based materials as a substitute for quartz-based susceptors. In this study, SiC coating technology on reaction sintered (RS) SiC with thickness variation of +/- 10% within a diameter of 8 inch by low pressure chemical vapor deposition has been developed for making a plate type SiC fixture such as heater, baffle, etc., with a diameter of 12 inch. Additionally, a state of art on fabrication technology and products of the current commercial SiC fixtures has been described

  19. New semiconductor laser technology for gas sensing applications in the 1650nm range

    Science.gov (United States)

    Morrison, Gordon B.; Sherman, Jes; Estrella, Steven; Moreira, Renan L.; Leisher, Paul O.; Mashanovitch, Milan L.; Stephen, Mark; Numata, Kenji; Wu, Stewart; Riris, Haris

    2017-08-01

    Atmospheric methane (CH4) is the second most important anthropogenic greenhouse gas with approximately 25 times the radiative forcing of carbon dioxide (CO2) per molecule. CH4 also contributes to pollution in the lower atmosphere through chemical reactions leading to ozone production. Recent developments of LIDAR measurement technology for CH4 have been previously reported by Goddard Space Flight Center (GSFC). In this paper, we report on a novel, high-performance tunable semiconductor laser technology developed by Freedom Photonics for the 1650nm wavelength range operation, and for LIDAR detection of CH4. Devices described are monolithic, with simple control, and compatible with low-cost fabrication techniques. We present 3 different types of tunable lasers implemented for this application.

  20. A monolithic active pixel sensor for particle detection in 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Velthuis, J.J.; Allport, P.P.; Casse, G.; Evans, A.; Turchetta, R.; Villani, G.

    2006-01-01

    We are developing CMOS monolithic active pixel sensors (MAPS) for High Energy Physics applications. We have successfully produced 3 test structures. They feature several different pixel types including: standard 3MOS, 4MOS allowing Correlated Double Sampling (CDS), charge amplifier pixels and a flexible APS (FAPS). The FAPS has a 10 deep pipeline on each pixel. This is specifically designed with the beam structure of the TESLA proposal for the Linear Collider in mind. Results of a laser test on our first device and source test results on two more recent test structures will be presented

  1. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  2. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  3. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  4. Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

    Science.gov (United States)

    Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

    2015-05-01

    In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

  5. A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Anelli, Giovanni; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2 ) without any degradation in the performance

  6. A high-speed low-noise transimpedance amplifier in a 0.25 {mu}m CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Anelli, Giovanni E-mail: giovanni.anelli@cern.ch; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-10-11

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k{omega}, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO{sub 2}) without any degradation in the performance.

  7. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

    2009-12-15

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  8. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    International Nuclear Information System (INIS)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

    2009-01-01

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  9. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  10. 2nd International Conference on Ion Implantation in Semiconductors, Physics and Technology, Fundamental and Applied Aspects

    CERN Document Server

    Graul, Jürgen

    1971-01-01

    In recent years great progress has been made in the field of ion implantation, particularly with respect to applications in semiconductors. It would be impos­ sible not to note the growing interest in this field, both by research groups and those directly concerned with production of devices. Furthermore, as several papers have pointed out, ion implantation and its associated technologies promise exciting advances in the development of new kinds of devices and provide power­ ful new tools for materials investigations. It was, therefore, appropriate to arrange the II. International Conference on Ion Implantation in Semiconductors within the rather short time of one year since the first conference was held in 1970 in Thousand Oaks, California. Although ori­ ginally planned on a small scale with a very limited number of participants, more than two hundred scientists from 15 countries participated in the Conference which was held May 24 - 28, 1971 at the Congress Center in Garmisch-Partenkirchen. This volume c...

  11. A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

    International Nuclear Information System (INIS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2015-01-01

    The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block—VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz–3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz)

  12. A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

    Science.gov (United States)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2015-12-01

    The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block—VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz-3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz).

  13. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  14. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

    Energy Technology Data Exchange (ETDEWEB)

    Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

    2010-12-15

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  15. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 μm CMOS technology for the integrated camera of the Cherenkov Telescope Array

    International Nuclear Information System (INIS)

    Gascon, D; Sanuy, A; Ribo, M; Delagnes, E; Glicenstein, J-F; Sieiro, X; Feinstein, F; Vorobiov, S; Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P

    2010-01-01

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35μm CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  16. Readout electronics for low dark count pixel detectors based on Geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

    International Nuclear Information System (INIS)

    Vilella, E.; Arbat, A.; Comerma, A.; Trenado, J.; Alonso, O.; Gascon, D.; Vila, A.; Garrido, L.; Dieguez, A.

    2011-01-01

    High sensitivity and excellent timing accuracy of the Geiger mode avalanche photodiodes make them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase in the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 μm and a high integration 0.13 μm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

  17. Total dose effects on the shallow-trench isolation leakage current characteristics in a 0.35microm SiGe BiCMOS technology

    International Nuclear Information System (INIS)

    Niu, G.; Mathew, S.J.; Banerjee, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Subbanna, S.

    1999-01-01

    The effects of gamma irradiation on the Shallow-Trench Isolation (STI) leakage currents in a SiGe BiCMOS technology are investigated for the first time, and shown to be strongly dependent on the irradiation gate bias and operating substrate bias. A positive irradiation gate bias significantly enhances the STI leakage, suggesting a strong field assisted nature of the charge buildup process in the STI. Numerical simulations also suggest the existence of fixed positive charges deep in the bulk along the STI/Si interface. A negative substrate bias, however, effectively suppresses the STI leakage, and can be used to eliminate the leakage produced by the charges deep in the bulk under irradiation

  18. Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology.

    Science.gov (United States)

    Sekine, Hiroshi; Kobayashi, Masahiro; Onuki, Yusuke; Kawabata, Kazunari; Tsuboi, Toshiki; Matsuno, Yasushi; Takahashi, Hidekazu; Inoue, Shunsuke; Ichikawa, Takeshi

    2017-12-09

    CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e - temporal noise and 16,200 e - full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e - /lx·s and -89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure.

  19. A K-Band Low-Power Phase Shifter Based on Injection Locked Oscillator in 0.13 μm CMOS Technology

    Science.gov (United States)

    Qiu, Qi-Lin; Yu, Xiao-Peng; Sui, Wen-Quan

    2017-11-01

    In this paper, the design challenges of the injection-locked oscillator (ILO)-based phase shifter are reviewed and analyzed. The key design considerations such as the operating frequency, locking range, and linearity of the phase shifters are analysed in detail. It is possible to optimize the phase shifter in certain parameters such as ultra-low power while meeting the requirements of a certain system. As a design example, a K-band phase shifter is implemented using a commercial 0.13 μm CMOS technology, where a conventional LC tank based topology is implemented but optimised with a good balance among power consumption, working range, sensitivity, and silicon area, etc. Measurement results show that the proposed phase shift is able to work at 22-23.4 GHz with a range of 180∘ while consuming 3.14 mW from a 1.2 V supply voltage.

  20. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    Directory of Open Access Journals (Sweden)

    Liping Wei

    2014-09-01

    Full Text Available Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

  1. A Novel Semiconductor CIGS Photovoltaic Material and Thin-Film ED Technology

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    In order to achieve low-cost high-efficiency thin-film solar cells, a novel Semiconductor Photovoltaic (PV) active material CuIn1-xGaxSe2 (CIGS) and thin-film Electro-Deposition (ED) technology is explored. Firstly,the PV materials and technologies is investigated, then the detailed experimental processes of CIGS/Mo/glass structure by using the novel ED technology and the results are reported. These results shows that high quality CIGS polycrystalline thin-films can be obtained by the ED method, in which the polycrystalline CIGS is definitely identified by the (112), (204, 220) characteristic peaks of the tetragonal structure, the continuous CIGS thin-film layers with particle average size of about 2μm of length and around 1.6μm of thickness. The thickness and solargrade quality of CIGS thin-films can be produced with good repeatability. Discussion and analysis on the ED technique, CIGS energy band and sodium (Na) impurity properties, were also performed. The alloy CIGS exhibits not only increasing band-gap with increasing x, but also a change in material properties that is relevant to the device operation. The beneficial impurity Na originating from the low-cost soda-lime glass substrate becomes one prerequisite for high quality CIGS films. These novel material and technology are very useful for low-cost high-efficiency thin-film solar cells and other devices.

  2. Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project

    Science.gov (United States)

    Ellinger, Frank; Mikolajick, Thomas; Fettweis, Gerhard; Hentschel, Dieter; Kolodinski, Sabine; Warnecke, Helmut; Reppe, Thomas; Tzschoppe, Christoph; Dohl, Jan; Carta, Corrado; Fritsche, David; Tretter, Gregor; Wiatr, Maciej; Detlef Kronholz, Stefan; Mikalo, Ricardo Pablo; Heinrich, Harald; Paulo, Robert; Wolf, Robert; Hübner, Johannes; Waltsgott, Johannes; Meißner, Klaus; Richter, Robert; Michler, Oliver; Bausinger, Markus; Mehlich, Heiko; Hahmann, Martin; Möller, Henning; Wiemer, Maik; Holland, Hans-Jürgen; Gärtner, Roberto; Schubert, Stefan; Richter, Alexander; Strobel, Axel; Fehske, Albrecht; Cech, Sebastian; Aßmann, Uwe; Pawlak, Andreas; Schröter, Michael; Finger, Wolfgang; Schumann, Stefan; Höppner, Sebastian; Walter, Dennis; Eisenreich, Holger; Schüffny, René

    2013-07-01

    An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at cars Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

  3. The CMOS Integration of a Power Inverter

    OpenAIRE

    Mannarino, Eric Francis

    2016-01-01

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this proce...

  4. Aging sensor for CMOS memory cells

    OpenAIRE

    Santos, Hugo Fernandes da Silva

    2016-01-01

    Dissertação de Mestrado, Engenharia e Tecnologia, Instituto Superior de Engenharia, Universidade do Algarve, 2016 As memórias Complementary Metal Oxide Semiconductor (CMOS) ocupam uma percentagem de área significativa nos circuitos integrados e, com o desenvolvimento de tecnologias de fabrico a uma escala cada vez mais reduzida, surgem problemas de performance e de fiabilidade. Efeitos como o BTI (Bias Thermal Instability), TDDB (Time Dependent Dielectric Breakdown), HCI (Hot Carrier Injec...

  5. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  6. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  7. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    . The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

  8. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  9. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    Science.gov (United States)

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  10. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  11. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  12. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Directory of Open Access Journals (Sweden)

    Cheng-Chun Wu

    2016-10-01

    Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  13. Linear analysis of signal and noise characteristics of a nonlinear CMOS active-pixel detector for mammography

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Seungman [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Kim, Ho Kyung, E-mail: hokyung@pusan.ac.kr [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Center for Advanced Medical Engineering Research, Pusan National University, Busan 46241 (Korea, Republic of); Han, Jong Chul; Kam, Soohwa [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Youn, Hanbean [Department of Radiation Oncology, Pusan National University Yangsan Hospital, Yangsan, Gyeongsangnam-do 50612 (Korea, Republic of); Cunningham, Ian A. [Robarts Research Institute, Western University, London, Ontario N6A 5C1 (Canada)

    2017-03-01

    The imaging properties of a complementary metal-oxide-semiconductor (CMOS) active-pixel photodiode array coupled to a thin gadolinium-based granular phosphor screen with a fiber-optic faceplate are investigated. It is shown that this system has a nonlinear response at low detector exposure levels (<10 mR), resulting in an over-estimation of the detective quantum efficiency (DQE) by a factor of two in some cases. Errors in performance metrics on this scale make it difficult to compare new technologies with established systems and predict performance benchmarks that can be achieved in practice and help understand performance bottlenecks. It is shown the CMOS response is described by a power-law model that can be used to linearize image data. Linearization removed an unexpected dependence of the DQE on detector exposure level. - Highlights: • A nonlinear response of a CMOS detector at low exposure levels can overestimate DQE. • A power-law form can model the response of a CMOS detector at low exposure levels, and can be used to linearize image data. • Performance evaluation of nonlinear imaging systems must incorporate adequate linearizations.

  14. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Directory of Open Access Journals (Sweden)

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  15. Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

    Science.gov (United States)

    Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

    2012-06-01

    Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

  16. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    International Nuclear Information System (INIS)

    Yang Weidong; Pu Jie; Zhang Ruitao; Chen Chao; Zang Jiandong; Li Tiehu; Luo Pu

    2015-01-01

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB and INL less than ±4.3 LSB after the chip is calibrated. (paper)

  17. Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, N.D., E-mail: Duy.Nguyen@imec.b [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Rosseel, E. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Takeuchi, S. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Department of Physics and Astronomy, KU Leuven, B-3001 Leuven (Belgium); Everaert, J.-L. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Yang, L. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Department of Chemistry and INPAC Institute, KU Leuven, B-3001 Leuven (Belgium); Goossens, J.; Moussa, A.; Clarysse, T.; Richard, O.; Bender, H. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Zaima, S. [Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Nagoya, 464-8603 (Japan); Sakai, A. [Department of System Innovation, Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka, Osaka 560-8531 (Japan); Loo, R. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Lin, J.C. [TSMC, R and D, 8, Li-Hsin 6th Rd., Hsinchu Science-Based Park, Hsinchu, Taiwan (China); TSMC assignee at IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Vandervorst, W. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Instituut voor Kern- en Stralingsfysika - IKS, KU Leuven, B-3001 Leuven (Belgium); Caymax, M. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium)

    2010-01-01

    We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 {sup o}C, we measured an active dopant concentration of about 2.1 x 10{sup 20} cm{sup -} {sup 3} and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1-4 x 10{sup 13} cm{sup -} {sup 2}) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

  18. Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

    International Nuclear Information System (INIS)

    Nguyen, N.D.; Rosseel, E.; Takeuchi, S.; Everaert, J.-L.; Yang, L.; Goossens, J.; Moussa, A.; Clarysse, T.; Richard, O.; Bender, H.; Zaima, S.; Sakai, A.; Loo, R.; Lin, J.C.; Vandervorst, W.; Caymax, M.

    2010-01-01

    We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 o C, we measured an active dopant concentration of about 2.1 x 10 20 cm - 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1-4 x 10 13 cm - 2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

  19. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  20. CMOS image sensors: State-of-the-art

    Science.gov (United States)

    Theuwissen, Albert J. P.

    2008-09-01

    This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

  1. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  2. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  3. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...

  4. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  5. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  6. Toward CMOS image sensor based glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2012-09-07

    Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

  7. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.

    2016-05-18

    We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

  8. A High-Dynamic-Range Optical Remote Sensing Imaging Method for Digital TDI CMOS

    Directory of Open Access Journals (Sweden)

    Taiji Lan

    2017-10-01

    Full Text Available The digital time delay integration (digital TDI technology of the complementary metal-oxide-semiconductor (CMOS image sensor has been widely adopted and developed in the optical remote sensing field. However, the details of targets that have low illumination or low contrast in scenarios of high contrast are often drowned out because of the superposition of multi-stage images in digital domain multiplies the read noise and the dark noise, thus limiting the imaging dynamic range. Through an in-depth analysis of the information transfer model of digital TDI, this paper attempts to explore effective ways to overcome this issue. Based on the evaluation and analysis of multi-stage images, the entropy-maximized adaptive histogram equalization (EMAHE algorithm is proposed to improve the ability of images to express the details of dark or low-contrast targets. Furthermore, in this paper, an image fusion method is utilized based on gradient pyramid decomposition and entropy weighting of different TDI stage images, which can improve the detection ability of the digital TDI CMOS for complex scenes with high contrast, and obtain images that are suitable for recognition by the human eye. The experimental results show that the proposed methods can effectively improve the high-dynamic-range imaging (HDRI capability of the digital TDI CMOS. The obtained images have greater entropy and average gradients.

  9. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  10. Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor.

    Science.gov (United States)

    Zin, Hafiz M; Harris, Emma J; Osmond, John P F; Allinson, Nigel M; Evans, Philip M

    2013-05-21

    This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s(-1) with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

  11. SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2009-12-01

    Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

  12. Simulation and Performance Test Technology Development for Semiconductor Radiation Detection Instrument Fabrication

    International Nuclear Information System (INIS)

    Kim, Jong Kyung; Lee, W. G.; Kim, S. Y.; Shin, C. H.; Kim, K. O.; Park, J. M.; Jang, D. Y.; Kang, J. S.

    2010-06-01

    - Analysis on the Absorbed Dose and Electron Generation by Using MCNPX Code - Analysis on the Change of Measured Energy Spectrum As a Function of Bias Voltage Applied in Semiconductor Detector - Comparison of Monte Carlo Simulation Considering the Charge Collection Efficiency and Experimental Result - Development of Semiconductor Sensor Design Code Based on the Graphic User Interface - Analysis on Depth Profile of Ion-implanted Semiconductor Wafer Surface and Naturally Generated SiO2 Insulation Layer Using Auger Electron Spectroscopy - Measurement of AFM Images and Roughness to Abalyze Surface of Semiconductor Wafer with respect to Annealing and Cleaning Process - Measurement of Physical Properties for Semiconductor Detector Surface after CZT Passivation Process - Evaluation of Crystal Structure and Specific Resistance of CZT - Measurement/Analysis on Band Structure of CZT Crystal - Evaluation of Neutron Convertor Layer with respect to Change in Temperature - Measurement/Evaluation of physical characteristics for lattice parameter, specific resistance, and band structure of CZT crystal - Measurement/Evaluation of lattice transition of SiC semiconductor detector after radiation irradiation - Measurement/Evaluation of performance of semiconductor detector with respect to exposure in high temperature environment

  13. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    International Nuclear Information System (INIS)

    Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

    2016-01-01

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  14. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Carniti, P., E-mail: paolo.carniti@mib.infn.it [INFN, Sezione di Milano Bicocca, I-20126 Milano (Italy); Dipartimento di Fisica, Università di Milano Bicocca, I-20126 Milano (Italy); Cassina, L.; Gotti, C.; Maino, M.; Pessina, G. [INFN, Sezione di Milano Bicocca, I-20126 Milano (Italy); Dipartimento di Fisica, Università di Milano Bicocca, I-20126 Milano (Italy)

    2016-07-11

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  15. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    Science.gov (United States)

    Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

    2016-07-01

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  16. Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

    Science.gov (United States)

    Gagnard, Xavier; Bonnaud, Olivier

    2000-08-01

    We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

  17. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  18. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  19. Electrical properties of radio-frequency sputtered HfO{sub 2} thin films for advanced CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Sarkar, Pranab Kumar; Roy, Asim, E-mail: 28.asim@gmail.com [Department of Physics, National Institute of Technology Silchar, Silchar-788010, Assam, India Phone: +91-3842-224879 (India)

    2015-08-28

    The Hafnium oxide (HfO{sub 2}) high-k thin films have been deposited by radio frequency (rf) sputtering technique on p-type Si (100) substrate. The thickness, composition and phases of films in relation to annealing temperatures have been investigated by using cross sectional FE-SEM (Field Emission Scanning Electron Microscope) and grazing incidence x-ray diffraction (GI-XRD), respectively. GI-XRD analysis revealed that at annealing temperatures of 350°C, films phases change to crystalline from amorphous. The capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the annealed HfO{sub 2} film have been studied employing Al/HfO{sub 2}/p-Si metal–oxide–semiconductor (MOS) structures. The electrical properties such as dielectric constant, interface trap density and leakage current density have been also extracted from C-V and I-V Measurements. The value of dielectric constant, interface trap density and leakage current density of annealed HfO{sub 2} film is obtained as 23,7.57×1011eV{sup −1} cm{sup −2} and 2.7×10{sup −5} Acm{sup −2}, respectively. In this work we also reported the influence of post deposition annealing onto the trapping properties of hafnium oxide and optimized conditions under which no charge trapping is observed into the dielectric stack.

  20. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

    International Nuclear Information System (INIS)

    Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

  1. Simulations of depleted CMOS sensors for high-radiation environments

    CERN Document Server

    Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

    2017-01-01

    After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

  2. Optoelectronic device physics and technology of nitride semiconductors from the UV to the terahertz

    Science.gov (United States)

    Moustakas, Theodore D.; Paiella, Roberto

    2017-10-01

    This paper reviews the device physics and technology of optoelectronic devices based on semiconductors of the GaN family, operating in the spectral regions from deep UV to Terahertz. Such devices include LEDs, lasers, detectors, electroabsorption modulators and devices based on intersubband transitions in AlGaN quantum wells (QWs). After a brief history of the development of the field, we describe how the unique crystal structure, chemical bonding, and resulting spontaneous and piezoelectric polarizations in heterostructures affect the design, fabrication and performance of devices based on these materials. The heteroepitaxial growth and the formation and role of extended defects are addressed. The role of the chemical bonding in the formation of metallic contacts to this class of materials is also addressed. A detailed discussion is then presented on potential origins of the high performance of blue LEDs and poorer performance of green LEDs (green gap), as well as of the efficiency reduction of both blue and green LEDs at high injection current (efficiency droop). The relatively poor performance of deep-UV LEDs based on AlGaN alloys and methods to address the materials issues responsible are similarly addressed. Other devices whose state-of-the-art performance and materials-related issues are reviewed include violet-blue lasers, ‘visible blind’ and ‘solar blind’ detectors based on photoconductive and photovoltaic designs, and electroabsorption modulators based on bulk GaN or GaN/AlGaN QWs. Finally, we describe the basic physics of intersubband transitions in AlGaN QWs, and their applications to near-infrared and terahertz devices.

  3. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  4. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  5. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  6. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  7. Density functional theory and beyond-opportunities for quantum methods in materials modeling semiconductor technology

    International Nuclear Information System (INIS)

    Shankar, Sadasivan; Simka, Harsono; Haverty, Michael

    2008-01-01

    In the semiconductor industry, the use of new materials has been increasing with the advent of nanotechnology. As critical dimensions decrease, and the number of materials increases, the interactions between heterogeneous materials themselves and processing increase in complexity. Traditionally, applications of ab initio techniques are confined to electronic structure and band gap calculations of bulk materials, which are then used in coarse-grained models such as mesoscopic and continuum models. Density functional theory is the most widely used ab initio technique that was successfully extended to several applications. This paper illustrates applications of density functional theory to semiconductor processes and proposes further opportunities for use of such techniques in process development

  8. CMOS switched current phase-locked loop

    NARCIS (Netherlands)

    Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

    1997-01-01

    The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

  9. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  10. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  11. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  12. Registration of Large Motion Blurred CMOS Images

    Science.gov (United States)

    2017-08-28

    raju@ee.iitm.ac.in - Institution : Indian Institute of Technology (IIT) Madras, India - Mailing Address : Room ESB 307c, Dept. of Electrical ...AFRL-AFOSR-JP-TR-2017-0066 Registration of Large Motion Blurred CMOS Images Ambasamudram Rajagopalan INDIAN INSTITUTE OF TECHNOLOGY MADRAS Final...NUMBER 5f.  WORK UNIT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) INDIAN INSTITUTE OF TECHNOLOGY MADRAS SARDAR PATEL ROAD Chennai, 600036

  13. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  14. A 65 nm CMOS high efficiency 50 GHz VCO with regard to the coupling effect of inductors

    International Nuclear Information System (INIS)

    Ye Yu; Tian Tong

    2013-01-01

    A 50 GHz cross-coupled voltage controlled oscillator (VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor (CMOS) technology is reported. A pair of inductors has been fabricated, measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO's LC tank. By optimizing the tank voltage swing and the buffer's operation region, the VCO achieves a maximum efficiency of 11.4% by generating an average output power of 2.5 dBm while only consuming 19.7 mW (including buffers). The VCO exhibits a phase noise of −87 dBc/Hz at 1 MHz offset, leading to a figure of merit (FoM) of −167.5 dB/Hz and a tuning range of 3.8% (from 48.98 to 50.88 GHz). (semiconductor integrated circuits)

  15. The Semiconductor Industry and Emerging Technologies: A Study Using a Modified Delphi Method

    Science.gov (United States)

    Jordan, Edgar A.

    2010-01-01

    The purpose of this qualitative descriptive study was to determine what leaders in the semiconductor industry thought the future of computing would look like and what emerging materials showed the most promise to overcome the current theoretical limit of 10 nanometers for silicon dioxide. The researcher used a modified Delphi technique in two…

  16. Advanced microlens and color filter process technology for the high-efficiency CMOS and CCD image sensors

    Science.gov (United States)

    Fan, Yang-Tung; Peng, Chiou-Shian; Chu, Cheng-Yu

    2000-12-01

    New markets are emerging for digital electronic image device, especially in visual communications, PC camera, mobile/cell phone, security system, toys, vehicle image system and computer peripherals for document capture. To enable one-chip image system that image sensor is with a full digital interface, can make image capture devices in our daily lives. Adding a color filter to such image sensor in a pattern of mosaics pixel or wide stripes can make image more real and colorful. We can say 'color filter makes the life more colorful color filter is? Color filter means can filter image light source except the color with specific wavelength and transmittance that is same as color filter itself. Color filter process is coating and patterning green, red and blue (or cyan, magenta and yellow) mosaic resists onto matched pixel in image sensing array pixels. According to the signal caught from each pixel, we can figure out the environment image picture. Widely use of digital electronic camera and multimedia applications today makes the feature of color filter becoming bright. Although it has challenge but it is very worthy to develop the process of color filter. We provide the best service on shorter cycle time, excellent color quality, high and stable yield. The key issues of advanced color process have to be solved and implemented are planarization and micro-lens technology. Lost of key points of color filter process technology have to consider will also be described in this paper.

  17. Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments

    Energy Technology Data Exchange (ETDEWEB)

    Hoff, James R. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Deptuch, G. W. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Wu, Guoying [Southern Methodist Univ., Dallas, TX (United States); Gui, Ping [Southern Methodist Univ., Dallas, TX (United States)

    2015-06-04

    The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.

  18. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Science.gov (United States)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  19. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  20. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  1. An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

    Directory of Open Access Journals (Sweden)

    Mayukh Bhattacharyya

    2018-05-01

    Full Text Available Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

  2. An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications.

    Science.gov (United States)

    Bhattacharyya, Mayukh; Gruenwald, Waldemar; Jansen, Dirk; Reindl, Leonhard; Aghassi-Hagmann, Jasmin

    2018-05-07

    Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

  3. Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

    Science.gov (United States)

    Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

    2018-05-01

    Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

  4. DISEÑO DE UN AMPLIFICADOR RIEL A RIEL CON TECNOLOGÍA CMOS 0,18 µm DESENHO DE UM AMPLIFICADOR DO TRILHO-A-TRILHO COM TECNOLOGIA CMOS 0,18 µm DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    Diego F. Hernández

    2012-06-01

    Full Text Available En este artículo se realiza el análisis, diseño y simulación de un amplificador rail to rail R-R (riel a riel a la entrada y a la salida utilizando una fuente sencilla de 3,3 V. La tecnología usada fue CMOS TSMC de 0,18 µm, de bajo costo relativo para uso académico. El proceso de implementación se hizo con herramientas industrial Synopsys. En el artículo se detalla la etapa de entrada R-R complementaria, se describen el circuito sumador y la etapa de salida R-R clase AB. Finalmente, se muestran el layout definitivo y los resultados de la evaluación del diseño.Em este artigo realiza-se a análise, desenho e simulação de um amplificador rail to rail R-R (trilho a trilho à entrada e à saída utilizando uma fonte singela de 3,3 V. A tecnologia usada foi CMOS TSMC de 0,18 µm, de relativo baixo custo para uso acadêmico. O processo de implementação realizou-se com ferramentas industrial Synopsys. No artigo detalha-se a etapa de entrada R-R complementar, descreve-se o circuito somador e a etapa de saída R-R classe AB. Finalmente, mostra-se o layout definitivo e os resultados da avaliação do desenho.This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18µm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.

  5. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Science.gov (United States)

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  6. Solar energy harvesting by magnetic-semiconductor nanoheterostructure in water treatment technology.

    Science.gov (United States)

    Mahmoodi, Vahid; Bastami, Tahereh Rohani; Ahmadpour, Ali

    2018-03-01

    Photocatalytic degradation of toxic organic pollutants in the wastewater using dispersed semiconductor nanophotocatalysts has a number of advantages such as high activity, cost effectiveness, and utilization of free solar energy. However, it is difficult to recover and recycle nanophotocatalysts since the fine dispersed nanoparticles are easily suspended in waters. Furthermore, a large amount of photocatalysts will lead to color contamination. Thus, it is necessary to prepare photocatalysts with easy separation for the reusable application. To take advantage of high photocatalysis activity and reusability, magnetic photocatalysts with separation function were utilized. In this review, the photocatalytic principle, structure, and application of the magnetic-semiconductor nanoheterostructure photocatalysts under solar light are evaluated. Graphical abstract ᅟ.

  7. Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

    Science.gov (United States)

    Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

    2017-10-02

    Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

  8. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    International Nuclear Information System (INIS)

    Hu Rongbin; Wang Yuxin; Lu Wu

    2014-01-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  9. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    OpenAIRE

    Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

    2011-01-01

    Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

  10. UV lithography-based protein patterning on silicon: Towards the integration of bioactive surfaces and CMOS electronics

    Energy Technology Data Exchange (ETDEWEB)

    Lenci, S., E-mail: silvia.lenci@iet.unipi.it [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Tedeschi, L. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy); Pieri, F. [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Domenici, C. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy)

    2011-08-01

    A simple and fast methodology for protein patterning on silicon substrates is presented, providing an insight into possible issues related to the interaction between biological and microelectronic technologies. The method makes use of standard photoresist lithography and is oriented towards the implementation of biosensors containing Complementary Metal-Oxide-Semiconductor (CMOS) conditioning circuitry. Silicon surfaces with photoresist patterns were prepared and hydroxylated by means of resist- and CMOS backend-compatible solutions. Subsequent aminosilane deposition and resist lift-off in organic solvents resulted into well-controlled amino-terminated geometries. The discussion is focused on resist- and CMOS-compatibility problems related to the used chemicals. Some samples underwent gold nanoparticle (Au NP) labeling and Scanning Electron Microscopy (SEM) observation, in order to investigate the quality of the silane layer. Antibodies were immobilized on other samples, which were subsequently exposed to a fluorescently labeled antigen. Fluorescence microscopy observation showed that this method provides spatially selective immobilization of protein layers onto APTES-patterned silicon samples, while preserving protein reactivity inside the desired areas and low non-specific adsorption elsewhere. Strong covalent biomolecule binding was achieved, giving stable protein layers, which allows stringent binding conditions and a good binding specificity, really useful for biosensing.

  11. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  12. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    Energy Technology Data Exchange (ETDEWEB)

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  13. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  14. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  15. Optimization of ultra-low-power CMOS transistors

    International Nuclear Information System (INIS)

    Stockinger, M.

    2000-01-01

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  16. Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    Science.gov (United States)

    Zhao, C; Vassiljev, N; Konstantinidis, A C; Speller, R D; Kanicki, J

    2017-03-07

    High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm -1 ) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

  17. Report on surveys in fiscal 2000 on the workshop on semiconductor technology for 21st century; 2000 nendo 21 seiki wo hiraku handotai gijutsu workshop chosa hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-08-01

    A workshop was held in order to realize the high-level information society, and bring about the common recognition on the assignments in the directionality to go in the next five years and on the problems to be worked on with emphasis in semiconductor technologies to form the foundation thereof, standing on the viewpoint of about ten years ahead. The matters discussed in the major semiconductor technology field included promotion of development of functions and technologies sought in the next generation system LSI, CAD system technologies, assurance of design engineers, development of new devices corresponding to electric power saving requirement, promotion of high integration elementary technologies, innovation in memory elementary technologies and structuring of new devices, new materials and processes for SoC, establishment of the membrane technology to insulate low-k layers, necessity of coordination from the basics to the applied fields, development of lithography and measuring technologies of sub-100 nm, and post photo-lithography technologies, promotion of micro measurement and macro measurement technologies, requirements in high-profit type semiconductor production technologies, and structuring of production factories with high QTAT and flexibility. (NEDO)

  18. CMOS serial link for fully duplexed data communication

    Science.gov (United States)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  19. Compact Submillimeter-Wave Receivers Made with Semiconductor Nano-Fabrication Technologies

    Science.gov (United States)

    Jung, C.; Thomas, B.; Lee, C.; Peralta, A.; Chattopadhyay, G.; Gill, J.; Cooper, K.; Mehdi, I.

    2011-01-01

    Advanced semiconductor nanofabrication techniques are utilized to design, fabricate and demonstrate a super-compact, low-mass (<10 grams) submillimeter-wave heterodyne front-end. RF elements such as waveguides and channels are fabricated in a silicon wafer substrate using deep-reactive ion etching (DRIE). Etched patterns with sidewalls angles controlled with 1 deg precision are reported, while maintaining a surface roughness of better than 20 nm rms for the etched structures. This approach is being developed to build compact 2-D imaging arrays in the THz frequency range.

  20. Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

    Science.gov (United States)

    Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

    2015-01-01

    In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes.

  1. A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

    International Nuclear Information System (INIS)

    Zhang Jihong; Bai Xuefei; Huang Lu

    2013-01-01

    A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm 2 . (semiconductor integrated circuits)

  2. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    International Nuclear Information System (INIS)

    He Wenwei; Meng Qiao; Zhang Yi; Tang Kai

    2014-01-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm 2 with the pad. It consumes 210 mW from a 1.2 V single supply. (semiconductor integrated circuits)

  3. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  4. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  5. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  6. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  7. Semiconductor Physical Electronics

    CERN Document Server

    Li, Sheng

    2006-01-01

    Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

  8. Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

    Science.gov (United States)

    Tu, Hongen

    This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

  9. An integrated semiconductor device enabling non-optical genome sequencing.

    Science.gov (United States)

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  10. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

    CSIR Research Space (South Africa)

    Reddy, Reeshen

    2015-04-01

    Full Text Available the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion...

  11. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    International Nuclear Information System (INIS)

    Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

    2015-01-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

  12. Silicon CMOS architecture for a spin-based quantum computer.

    Science.gov (United States)

    Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

    2017-12-15

    Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

  13. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  14. Transition strategies for managing technological discontinuities: lessons from the history of the semiconductor industry

    NARCIS (Netherlands)

    Stoelhorst, J.W.

    2002-01-01

    This paper explores the nature of competition under conditions of technological change and asks how firms can manage technological discontinuities. By drawing on the literatures on strategic management and technology dynamics, it is proposed that firms should change the nature of their strategy as a

  15. CMOS SPDT switch for WLAN applications

    International Nuclear Information System (INIS)

    Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

    2015-01-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

  16. Cmos spdt switch for wlan applications

    Science.gov (United States)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  17. Assessment of Anisotropic Semiconductor Nanorod and Nanoplatelet Heterostructures with Polarized Emission for Liquid Crystal Display Technology.

    Science.gov (United States)

    Cunningham, Patrick D; Souza, João B; Fedin, Igor; She, Chunxing; Lee, Byeongdu; Talapin, Dmitri V

    2016-06-28

    Semiconductor nanorods can emit linear-polarized light at efficiencies over 80%. Polarization of light in these systems, confirmed through single-rod spectroscopy, can be explained on the basis of the anisotropy of the transition dipole moment and dielectric confinement effects. Here we report emission polarization in macroscopic semiconductor-polymer composite films containing CdSe/CdS nanorods and colloidal CdSe nanoplatelets. Anisotropic nanocrystals dispersed in polymer films of poly butyl-co-isobutyl methacrylate (PBiBMA) can be stretched mechanically in order to obtain unidirectionally aligned arrays. A high degree of alignment, corresponding to an orientation factor of 0.87, was achieved and large areas demonstrated polarized emission, with the contrast ratio I∥/I⊥ = 5.6, making these films viable candidates for use in liquid crystal display (LCD) devices. To some surprise, we observed significant optical anisotropy and emission polarization for 2D CdSe nanoplatelets with the electronic structure of quantum wells. The aligned nanorod arrays serve as optical funnels, absorbing unpolarized light and re-emitting light from deep-green to red with quantum efficiencies over 90% and high degree of linear polarization. Our results conclusively demonstrate the benefits of anisotropic nanostructures for LCD backlighting. The polymer films with aligned CdSe/CdS dot-in-rod and rod-in-rod nanostructures show more than 2-fold enhancement of brightness compared to the emitter layers with randomly oriented nanostructures. This effect can be explained as the combination of linearly polarized luminescence and directional emission from individual nanostructures.

  18. Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

    KAUST Repository

    Hussain, Aftab M.; Singh, Nirpendra; Fahad, Hossain M.; Rader, Kelly; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2014-01-01

    We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well

  19. A low-power CMOS smart temperature sensor for RFID application

    International Nuclear Information System (INIS)

    Xie Liangbo; Liu Jiaxin; Wang Yao; Wen Guangjun

    2014-01-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is −0.69/+0.85 °C after one-point calibration over a temperature range of −40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm 2 , and it is suitable for RFID application. (semiconductor integrated circuits)

  20. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Energy Technology Data Exchange (ETDEWEB)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua, E-mail: gaoleisheng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-08-15

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 {mu}m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 {mu}m{sup 2}. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  1. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    International Nuclear Information System (INIS)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua

    2010-01-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 μm 2 . Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  2. A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

    Science.gov (United States)

    Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

    2018-03-01

    A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

  3. Metal semiconductor contacts and devices

    CERN Document Server

    Cohen, Simon S; Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 13: Metal-Semiconductor Contacts and Devices presents the physics, technology, and applications of metal-semiconductor barriers in digital integrated circuits. The emphasis is placed on the interplay among the theory, processing, and characterization techniques in the development of practical metal-semiconductor contacts and devices.This volume contains chapters that are devoted to the discussion of the physics of metal-semiconductor interfaces and its basic phenomena; fabrication procedures; and interface characterization techniques, particularl

  4. Self-calibrated humidity sensor in CMOS without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  5. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  6. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  7. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    International Nuclear Information System (INIS)

    Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

  8. Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

    Science.gov (United States)

    2015-12-24

    manufacturing today (namely, the 14nm FinFET silicon CMOS technology). The JPEG algorithm is selected as a motivational example since it is widely...TIFF images of a U.S. Air Force F-16 aircraft provided by the University of Southern California Signal and Image Processing Institute (SIPI) image...silicon CMOS technology currently in high volume manufac- turing today (the 14 nm FinFET silicon CMOS technology). The main contribution of this

  9. Analysis of technology and development plan on Lithography process of display industry and semiconductor

    International Nuclear Information System (INIS)

    2005-02-01

    This reports the seminar on Lithography in 2005, which includes these contents; Introduction of Lithography, equipment in NNFC, Exposure technology with fabrication, basic and application optics, RET and Lens aberrations, Alignment and Overlay and Metrology, Resist process with prime, mechanism, issues, resist technology and track system, Mask and OPC such as mask, fabrication, mask technology, proximity effect and OPC, Next generation, Lithography with NGL, Immersion and imprint. In the last, there are questions and answers.

  10. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    Science.gov (United States)

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  11. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  12. Based on Weibull Information Fusion Analysis Semiconductors Quality the Key Technology of Manufacturing Execution Systems Reliability

    Science.gov (United States)

    Huang, Zhi-Hui; Tang, Ying-Chun; Dai, Kai

    2016-05-01

    Semiconductor materials and Product qualified rate are directly related to the manufacturing costs and survival of the enterprise. Application a dynamic reliability growth analysis method studies manufacturing execution system reliability growth to improve product quality. Refer to classical Duane model assumptions and tracking growth forecasts the TGP programming model, through the failure data, established the Weibull distribution model. Combining with the median rank of average rank method, through linear regression and least squares estimation method, match respectively weibull information fusion reliability growth curve. This assumption model overcome Duane model a weakness which is MTBF point estimation accuracy is not high, through the analysis of the failure data show that the method is an instance of the test and evaluation modeling process are basically identical. Median rank in the statistics is used to determine the method of random variable distribution function, which is a good way to solve the problem of complex systems such as the limited sample size. Therefore this method has great engineering application value.

  13. The CMOS integration of a power inverter

    Science.gov (United States)

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  14. Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

    Science.gov (United States)

    Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

    2018-03-01

    Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

  15. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    International Nuclear Information System (INIS)

    Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

    2011-01-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

  16. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  17. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  18. High efficiency grating couplers based on shared process with CMOS MOSFETs

    International Nuclear Information System (INIS)

    Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  19. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  20. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Science.gov (United States)

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  1. CMOS/SOS RAM transient radiation upset and ''inversion'' effect investigation

    International Nuclear Information System (INIS)

    Nikiforov, A.Y.; Poljakov, I.V.

    1996-01-01

    The Complementary Metal-Oxide-Semiconductor/Silicon-on-Sapphire Random Access Memory (CMOS/SOS RAM) transient upset and inversion effect were investigated with pulsed laser, pulsed voltage generator and low-intensity light simulators. It was found that the inversion of information occurs due to memory cell photocurrents simultaneously with the power supply voltage drop transfer to memory cells outputs

  2. CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

    Science.gov (United States)

    Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

    1996-01-01

    Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

  3. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

  4. Technology life cycle and specialization patterns of latecomer countries: The case of the semiconductor industry

    NARCIS (Netherlands)

    Triulzi, G.

    2014-01-01

    Catching-up, leapfrogging and falling behind in terms of output and productivity in high-tech industries crucially depends on firms' ability to keep pace with technological change. In fast changing industries today's specialization does not guarantee tomorrow's success as changes in the

  5. Design rules for RCA self-aligned silicon-gate CMOS/SOS process

    Science.gov (United States)

    1977-01-01

    The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

  6. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

    2016-01-01

    . The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

  7. Performance of capacitively coupled active pixel sensors in 180 nm HV-CMOS technology after irradiation to HL-LHC fluences

    International Nuclear Information System (INIS)

    Feigl, S

    2014-01-01

    In this ATLAS upgrade R and D project, we explore the concept of using a deep-submicron HV-CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the basic design of the HV2FEI4 test ASIC, results after irradiation with X-rays to 862 Mrad and neutrons up to 10 16 (1 MeV n eq )/cm 2 will be presented. Finally, a brief outlook on further development plans is given

  8. Semiconductor physics

    CERN Document Server

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  9. Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

    International Nuclear Information System (INIS)

    Mishra, Vijay; Kataria, S.K.

    2005-01-01

    A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

  10. Defects in semiconductors

    International Nuclear Information System (INIS)

    Pimentel, C.A.F.

    1983-01-01

    Some problems openned in the study of defects in semiconductors are presented. In particular, a review is made of the more important problems in Si monocrystals of basic and technological interest: microdefects and the presence of oxigen and carbon. The techniques usually utilized in the semiconductor material characterization are emphatized according its potentialities. Some applications of x-ray techniques in the epitaxial shell characterization in heterostructures, importants in electronic optics, are shown. The increase in the efficiency of these defect analysis methods in semiconductor materials with the use of synchrotron x-ray sources is shown. (L.C.) [pt

  11. Physics of semiconductor lasers

    CERN Document Server

    Mroziewicz, B; Nakwaski, W

    2013-01-01

    Written for readers who have some background in solid state physics but do not necessarily possess any knowledge of semiconductor lasers, this book provides a comprehensive and concise account of fundamental semiconductor laser physics, technology and properties. The principles of operation of these lasers are therefore discussed in detail with the interrelations between their design and optical, electrical and thermal properties. The relative merits of a large number of laser structures and their parameters are described to acquaint the reader with the various aspects of the semiconductor l

  12. Semiconductors bonds and bands

    CERN Document Server

    Ferry, David K

    2013-01-01

    As we settle into this second decade of the twenty-first century, it is evident that the advances in micro-electronics have truly revolutionized our day-to-day lifestyle. The technology is built upon semiconductors, materials in which the band gap has been engineered for special values suitable to the particular application. This book, written specifically for a one semester course for graduate students, provides a thorough understanding of the key solid state physics of semiconductors. It describes how quantum mechanics gives semiconductors unique properties that enabled the micro-electronics revolution, and sustain the ever-growing importance of this revolution.

  13. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  14. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  15. Large Format CMOS-based Detectors for Diffraction Studies

    Science.gov (United States)

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  16. Large Format CMOS-based Detectors for Diffraction Studies

    International Nuclear Information System (INIS)

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  17. Fiscal 1998 research achievement report. Development of key technology for high-efficiency semiconductor manufacturing process; 1998 nendo kokoritsu handotai seizo process kiban gijutsu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-05-01

    In the development of large-aperture/high-density plasma technology, research and development was carried out for balanced electron drift plasma technologies for uniform control of plasma density and the like, such as an excited plasma source and plasma drift to enable wide-range plasma generation in a chamber. In the development of high-efficiency exposure technology, studies were made for stable generation and control of short wavelength excimer laser and for higher-speed large-aperture mask writing by use of an electron beam. In the development of higher-speed processing and energy-efficient technologies, research and development was conducted involving probe card technology for increasing the speed of semiconductor inspection, software-aided virtual tester technology, local energy-efficient cleaning technology in wafer processing and transportation, sheet-type flexible manufacturing system, and the like. (NEDO)

  18. Designing defect-based qubit candidates in wide-gap binary semiconductors for solid-state quantum technologies

    Science.gov (United States)

    Seo, Hosung; Ma, He; Govoni, Marco; Galli, Giulia

    2017-12-01

    The development of novel quantum bits is key to extending the scope of solid-state quantum-information science and technology. Using first-principles calculations, we propose that large metal ion-vacancy pairs are promising qubit candidates in two binary crystals: 4 H -SiC and w -AlN. In particular, we found that the formation of neutral Hf- and Zr-vacancy pairs is energetically favorable in both solids; these defects have spin-triplet ground states, with electronic structures similar to those of the diamond nitrogen-vacancy center and the SiC divacancy. Interestingly, they exhibit different spin-strain coupling characteristics, and the nature of heavy metal ions may allow for easy defect implantation in desired lattice locations and ensure stability against defect diffusion. To support future experimental identification of the proposed defects, we report predictions of their optical zero-phonon line, zero-field splitting, and hyperfine parameters. The defect design concept identified here may be generalized to other binary semiconductors to facilitate the exploration of new solid-state qubits.

  19. Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

    Science.gov (United States)

    Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

    2017-08-01

    The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Market survey of semiconductors

    International Nuclear Information System (INIS)

    Mackintosh, I.M.; Diegel, D.; Brown, A.; Brinker, C.S. den

    1977-06-01

    Examination of technology and product trends over the range of current and future products in integrated circuits and optoelectronic displays. Analysis and forecast of major economic influences that affect the production costs of integrated circuits and optoelectronic displays. Forecast of the applications and markets for integrated circuits up to 1985 in West Europe, the USA and Japan. Historic development of the semiconductor industry and the prevailing tendencies - factors which influence success in the semiconductor industry. (orig.) [de

  1. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  2. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  3. The FinFET Breakthrough and Networks of Innovation in the Semiconductor Industry, 1980-2005: Applying Digital Tools to the History of Technology.

    Science.gov (United States)

    O'Reagan, Douglas; Fleming, Lee

    2018-01-01

    The "FinFET" design for transistors, developed at the University of California, Berkeley, in the 1990s, represented a major leap forward in the semiconductor industry. Understanding its origins and importance requires deep knowledge of local factors, such as the relationships among the lab's principal investigators, students, staff, and the institution. It also requires understanding this lab within the broader network of relationships that comprise the semiconductor industry-a much more difficult task using traditional historical methods, due to the paucity of sources on industrial research. This article is simultaneously 1) a history of an impactful technology and its social context, 2) an experiment in using data tools and visualizations as a complement to archival and oral history sources, to clarify and explore these "big picture" dimensions, and 3) an introduction to specific data visualization tools that we hope will be useful to historians of technology more generally.

  4. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    International Nuclear Information System (INIS)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao

    2010-01-01

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm 2 . System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  5. A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

    International Nuclear Information System (INIS)

    Bai Na; Lü Baitao

    2012-01-01

    A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency. (semiconductor integrated circuits)

  6. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao, E-mail: tanxi@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-12-15

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 {mu}m CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm{sup 2}. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  7. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing

    2011-01-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm 2 area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  8. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 {mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing, E-mail: wubin@ime.ac.cn [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2011-05-15

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 {mu}m 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm{sup 2} area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  9. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  10. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  11. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization.

    Science.gov (United States)

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C; Patel, Tushita

    2015-11-01

    Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50-300 e-) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). In this study, imaging performance of a large area (29×23 cm2) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165-400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. The LFW mode shows better DQE at low air kerma (Ka<10 μGy) and should be used for DBT. At current DBT applications, air kerma (Ka∼10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165-400 μm in size can be resolved using a MGD range of 0.3-1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for

  12. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    International Nuclear Information System (INIS)

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C.; Patel, Tushita

    2015-01-01

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e − ) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm 2 ) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K a < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K a ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 m

  13. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    Energy Technology Data Exchange (ETDEWEB)

    Zhao, Chumin; Kanicki, Jerzy, E-mail: kanicki@eecs.umich.edu [Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109 (United States); Konstantinidis, Anastasios C. [Department of Medical Physics and Biomedical Engineering, University College London, London WC1E 6BT, United Kingdom and Diagnostic Radiology and Radiation Protection, Christie Medical Physics and Engineering, The Christie NHS Foundation Trust, Manchester M20 4BX (United Kingdom); Patel, Tushita [Department of Physics, University of Virginia, Charlottesville, Virginia 22908 (United States)

    2015-11-15

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

  14. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    International Nuclear Information System (INIS)

    Kim, Y; Pham, C; Chang, J P

    2015-01-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  15. CMOS current controlled fully balanced current conveyor

    International Nuclear Information System (INIS)

    Wang Chunhua; Zhang Qiujing; Liu Haiguang

    2009-01-01

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology; with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  16. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  17. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    Directory of Open Access Journals (Sweden)

    Paul C. McIntyre

    2012-07-01

    Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS 8.64-11.62 GHz CMOS VCO and divider in a zero-IF 802.11a/b/g WLAN and Bluetooth application

    Science.gov (United States)

    Yu, Sun; Niansong, Mei; Bo, Lu; Yumei, Huang; Zhiliang, Hong

    2010-10-01

    A fully integrated VCO and divider implemented in SMIC 0.13-μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.11a WLAN in 5.8 GHz band or for 802.11b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of—113 dBc @ 1 MHz offset from the carrier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range (FOMT) of the VCO is -192.6 dBc/Hz.

  19. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  20. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  1. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  2. CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

    Directory of Open Access Journals (Sweden)

    Ekavut Kritchanchai

    2015-08-01

    Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

  3. Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

    Directory of Open Access Journals (Sweden)

    Farès TOUNSI

    2009-09-01

    Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

  4. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  5. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  6. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2014-05-01

    Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  7. A CMOS humidity sensor for passive RFID sensing applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  8. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  9. Future semiconductor material requirements and innovations as projected in the ITRS 2005 roadmap

    International Nuclear Information System (INIS)

    Arden, Wolfgang

    2006-01-01

    The international technology roadmap for semiconductors (ITRS) is a joint global effort of the semiconductor industry, the manufacturing equipment and material industry and the research community and consortia to define the future requirements and development of the semiconductor technology for the next 15 years. The ITRS started in 1992 as a US-national roadmap and became an international effort in 1998 with all major five industrial global regions (US, Japan, Taiwan, Korea and Europe) participating in its definition. The outlook in semiconductor manufacturing expects the continuous application of silicon technology for the next 15 years where complementary metal oxide semiconductor (CMOS) based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decade. The major section of the ITRS contains technical information about frontend processing and interconnects, device structures and memory concepts, lithography and metrology as well as factory integration and environmental issues. This paper will review the material requirements and the expected material innovations for the industry as outlined in the ITRS Version 2005. Materials to be discussed are, for example, high permittivity gate dielectrics, insulating layers with low dielectric constants for interconnects, and capacitor dielectrics for dynamic memories. In addition, the paper will address, for example, new transistor gate materials, new solutions for interconnect systems beyond copper as well as new starting materials for wafer sizes beyond 300 mm. This publication was presented as an invited paper in the Symposium V of the 2006 spring meeting of the European Materials Research Society (E-MRS) in Nice, May 29th

  10. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    CERN Document Server

    Benoit, M.

    2016-07-21

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  11. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  12. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  13. Technology modules from micro- and nano-electronics for the life sciences.

    Science.gov (United States)

    Birkholz, M; Mai, A; Wenger, C; Meliani, C; Scholz, R

    2016-05-01

    The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website. © 2015 Wiley Periodicals, Inc.

  14. CMOL/CMOS hardware architectures and performance/price for Bayesian memory - The building block of intelligent systems

    Science.gov (United States)

    Zaveri, Mazad Shaheriar

    The semiconductor/computer industry has been following Moore's law for several decades and has reaped the benefits in speed and density of the resultant scaling. Transistor density has reached almost one billion per chip, and transistor delays are in picoseconds. However, scaling has slowed down, and the semiconductor industry is now facing several challenges. Hybrid CMOS/nano technologies, such as CMOL, are considered as an interim solution to some of the challenges. Another potential architectural solution includes specialized architectures for applications/models in the intelligent computing domain, one aspect of which includes abstract computational models inspired from the neuro/cognitive sciences. Consequently in this dissertation, we focus on the hardware implementations of Bayesian Memory (BM), which is a (Bayesian) Biologically Inspired Computational Model (BICM). This model is a simplified version of George and Hawkins' model of the visual cortex, which includes an inference framework based on Judea Pearl's belief propagation. We then present a "hardware design space exploration" methodology for implementing and analyzing the (digital and mixed-signal) hardware for the BM. This particular methodology involves: analyzing the computational/operational cost and the related micro-architecture, exploring candidate hardware components, proposing various custom hardware architectures using both traditional CMOS and hybrid nanotechnology - CMOL, and investigating the baseline performance/price of these architectures. The results suggest that CMOL is a promising candidate for implementing a BM. Such implementations can utilize the very high density storage/computation benefits of these new nano-scale technologies much more efficiently; for example, the throughput per 858 mm2 (TPM) obtained for CMOL based architectures is 32 to 40 times better than the TPM for a CMOS based multiprocessor/multi-FPGA system, and almost 2000 times better than the TPM for a PC

  15. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    Science.gov (United States)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  16. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  17. Real-time two-dimensional imaging of potassium ion distribution using an ion semiconductor sensor with charged coupled device technology.

    Science.gov (United States)

    Hattori, Toshiaki; Masaki, Yoshitomo; Atsumi, Kazuya; Kato, Ryo; Sawada, Kazuaki

    2010-01-01

    Two-dimensional real-time observation of potassium ion distributions was achieved using an ion imaging device based on charge-coupled device (CCD) and metal-oxide semiconductor technologies, and an ion selective membrane. The CCD potassium ion image sensor was equipped with an array of 32 × 32 pixels (1024 pixels). It could record five frames per second with an area of 4.16 × 4.16 mm(2). Potassium ion images were produced instantly. The leaching of potassium ion from a 3.3 M KCl Ag/AgCl reference electrode was dynamically monitored in aqueous solution. The potassium ion selective membrane on the semiconductor consisted of plasticized poly(vinyl chloride) (PVC) with bis(benzo-15-crown-5). The addition of a polyhedral oligomeric silsesquioxane to the plasticized PVC membrane greatly improved adhesion of the membrane onto Si(3)N(4) of the semiconductor surface, and the potential response was stabilized. The potential response was linear from 10(-2) to 10(-5) M logarithmic concentration of potassium ion. The selectivity coefficients were K(K(+),Li(+))(pot) = 10(-2.85), K(K(+),Na(+))(pot) = 10(-2.30), K(K(+),Rb(+))(pot) =10(-1.16), and K(K(+),Cs(+))(pot) = 10(-2.05).

  18. Semiconductor spintronics

    CERN Document Server

    Xia, Jianbai; Chang, Kai

    2012-01-01

    Semiconductor Spintronics, as an emerging research discipline and an important advanced field in physics, has developed quickly and obtained fruitful results in recent decades. This volume is the first monograph summarizing the physical foundation and the experimental results obtained in this field. With the culmination of the authors' extensive working experiences, this book presents the developing history of semiconductor spintronics, its basic concepts and theories, experimental results, and the prospected future development. This unique book intends to provide a systematic and modern foundation for semiconductor spintronics aimed at researchers, professors, post-doctorates, and graduate students, and to help them master the overall knowledge of spintronics.

  19. Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

    Science.gov (United States)

    Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

    2015-10-01

    In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

  20. Automation and Integration in Semiconductor Manufacturing

    OpenAIRE

    Liao, Da-Yin

    2010-01-01

    Semiconductor automation originates from the prevention and avoidance of frauds in daily fab operations. As semiconductor technology and business continuously advance and grow, manufacturing systems must aggressively evolve to meet the changing technical and business requirements in this industry. Semiconductor manufacturing has been suffering pains from islands of automation. The problems associated with these systems are limited