WorldWideScience

Sample records for semiconductor chip interconnects

  1. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  2. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  3. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  4. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  5. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    Science.gov (United States)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

  6. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  7. Chip-Level Electromigration Reliability for Cu Interconnects

    International Nuclear Information System (INIS)

    Gall, M.; Oh, C.; Grinshpon, A.; Zolotov, V.; Panda, R.; Demircan, E.; Mueller, J.; Justison, P.; Ramakrishna, K.; Thrasher, S.; Hernandez, R.; Herrick, M.; Fox, R.; Boeck, B.; Kawasaki, H.; Haznedar, H.; Ku, P.

    2004-01-01

    Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The traditional method of verifying EM reliability only through current density limit checks is proving to be inadequate in general, or quite expensive at the best. A Statistical EM Budgeting (SEB) methodology has been proposed to assess more realistic chip-level EM reliability from the complex statistical distribution of currents in a chip. To be valuable, this approach requires accurate estimation of currents for all interconnect segments in a chip. However, no efficient technique to manage the complexity of such a task for very large chip designs is known. We present an efficient method to estimate currents exhaustively for all interconnects in a chip. The proposed method uses pre-characterization of cells and macros, and steps to identify and filter out symmetrically bi-directional interconnects. We illustrate the strength of the proposed approach using a high-performance microprocessor design for embedded applications as a case study

  8. Global On-Chip Differential Interconnects with Optimally-Placed Twists

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2005-01-01

    Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects

  9. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  10. Si micro photonics for optical interconnection

    International Nuclear Information System (INIS)

    Wada, K.; Ahn, D.H.; Lim, D.R.; Michel, J.; Kimerling, L.C.

    2006-01-01

    This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated

  11. Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

    Science.gov (United States)

    Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

    2008-02-01

    We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

  12. One-step fabrication of microfluidic chips with in-plane, adhesive-free interconnections

    International Nuclear Information System (INIS)

    Sabourin, D; Dufva, M; Jensen, T; Kutter, J; Snakenborg, D

    2010-01-01

    A simple method for creating interconnections to a common microfluidic device material, poly(methyl methacrylate) (PMMA), is presented. A press-fit interconnection is created between oversized, deformable tubing and complementary, undersized semi-circular ports fabricated into PMMA bonding surfaces by direct micromilling. Upon UV-assisted bonding the tubing is trapped in the ports of the PMMA chip and forms an integrated, in-plane and adhesive-free interconnection. The interconnections support the average pressure of 6.1 bar and can be made with small dead volumes. A comparison is made to a similar interconnection approach which uses tubing to act as a gasket between a needle and port on the microfluidic chip. (technical note)

  13. Simple and reusable fibre-to-chip interconnect with adjustable coupling eficiency

    NARCIS (Netherlands)

    Heideman, Rene; Lambeck, Paul; Parriaux, Olivier M.; Kley, Ernst-Bernhard

    1997-01-01

    A simple, efficient and reusable fiber-to-chip interconnect is presented. The interconnect is based on a V-groove (wet- chemically etched) in silicon, combined with a loose-mode Si3N4-channel waveguide. The loose-mode waveguide is adiabatically tapered to the integrated optical (sensor) circuitry.

  14. Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

    Science.gov (United States)

    King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

    1998-04-01

    We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

  15. Nano/CMOS architectures using a field-programmable nanowire interconnect

    International Nuclear Information System (INIS)

    Snider, Gregory S; Williams, R Stanley

    2007-01-01

    A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

  16. All-polymer organic semiconductor laser chips: Parallel fabrication and encapsulation

    DEFF Research Database (Denmark)

    Vannahme, Christoph; Klinkhammer, Sönke; Christiansen, Mads Brøkner

    2010-01-01

    Organic semiconductor lasers are of particular interest as tunable visible laser light sources. For bringing those to market encapsulation is needed to ensure practicable lifetimes. Additionally, fabrication technologies suitable for mass production must be used. We introduce all-polymer chips...... comprising encapsulated distributed feedback organic semiconductor lasers. Several chips are fabricated in parallel by thermal nanoimprint of the feedback grating on 4? wafer scale out of poly(methyl methacrylate) (PMMA) and cyclic olefin copolymer (COC). The lasers consisting of the organic semiconductor...... tris(8- hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2- methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM) are hermetically sealed by thermally bonding a polymer lid. The organic thin film is placed in a basin within the substrate and is not in direct contact to the lid...

  17. 32 x 16 CMOS smart pixel array for optical interconnects

    Science.gov (United States)

    Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

    2000-05-01

    Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

  18. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  19. 76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

    Science.gov (United States)

    2011-12-21

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With... importation, and the sale within the United States after importation of certain semiconductor chips with DRAM.... 7,906,809 (``the `809 patent''). The complaint further alleges that an industry in the United States...

  20. Analysis of the trade-offs between conventional and superconducting interconnections

    International Nuclear Information System (INIS)

    Frye, R.

    1989-01-01

    Superconductivity can now be achieved at temperatures compatible with semiconductor device operation. This raises the interesting possibility of using the new, high-temperature superconducting ceramics for interconnections in electronic systems. This paper examines some of the consequences of a resistance-free interconnection medium. A problem with conventional conductors in electronic systems is that the resistance of wires increases quadratically as the wire dimensions are scaled down. Below some minimum cross-sectional area, determined by the metal resistivity and wire length, the resistance in these lines begins to severely limit their bandwidth. Superconductors, on the other hand, are not constrained by the same scaling rules. They provide a high bandwidth interconnection at all sizes and lengths. The limitations for superconductors are set by their critical current densities. If line dimensions become too small, a superconductor will no longer support an adequate flow of current. An analysis is presented examining the performance trade-offs for conventional and superconducting interconnections in applications ranging from printed wiring boards to chips. For most semiconductor device-based applications, the potential gains in wiring density offered by superconductors are probably more important than the bandwidth improvements. An important result of the analysis is that it determines the values of critical current density above which superconductors outperform conventional wires in systems of various physical sizes. This identifies particular interconnection technologies for which high-temperature superconductors show the most promise

  1. Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

    CERN Document Server

    Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

    2014-01-01

    In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

  2. Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

    International Nuclear Information System (INIS)

    Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

    2015-01-01

    Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

  3. A 3Gb/s/ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects

    NARCIS (Netherlands)

    Schinkel, Daniel; Mensink, E.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2006-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the

  4. Interconnection blocks: a method for providing reusable, rapid, multiple, aligned and planar microfluidic interconnections

    DEFF Research Database (Denmark)

    Sabourin, David; Snakenborg, Detlef; Dufva, Hans Martin

    2009-01-01

    In this paper a method is presented for creating 'interconnection blocks' that are re-usable and provide multiple, aligned and planar microfluidic interconnections. Interconnection blocks made from polydimethylsiloxane allow rapid testing of microfluidic chips and unobstructed microfluidic observ...

  5. High-resolution X-ray imaging - a powerful nondestructive technique for applications in semiconductor industry

    International Nuclear Information System (INIS)

    Zschech, Ehrenfried; Yun, Wenbing; Schneider, Gerd

    2008-01-01

    The availability of high-brilliance X-ray sources, high-precision X-ray focusing optics and very efficient CCD area detectors has contributed essentially to the development of transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) with sub-50 nm resolution. Particularly, the fabrication of high aspect ratio Fresnel zone plates with zone widths approaching 15 nm has contributed to the enormous improvement in spatial resolution during the previous years. Currently, Fresnel zone plates give the ability to reach spatial resolutions of 15 to 20 nm in the soft and of about 30 to 50 nm in the hard X-ray energy range. X-ray microscopes with rotating anode X-ray sources that can be installed in an analytical lab next to a semiconductor fab have been developed recently. These unique TXM/XCT systems provide an important new capability of nondestructive 3D imaging of internal circuit structures without destructive sample preparation such as cross sectioning. These lab systems can be used for failure localization in micro- and nanoelectronic structures and devices, e.g., to visualize voids and residuals in on-chip metal interconnects without physical modification of the chip. Synchrotron radiation experiments have been used to study new processes and materials that have to be introduced into the semiconductor industry. The potential of TXM using synchrotron radiation in the soft X-ray energy range is shown for the nondestructive in situ imaging of void evolution in embedded on-chip copper interconnect structures during electromigration and for the imaging of different types of insulating thin films between the on-chip interconnects (spectromicroscopy). (orig.)

  6. Structural characteristics of carbon nanofibers for on-chip interconnect applications

    International Nuclear Information System (INIS)

    Ominami, Yusuke; Ngo, Quoc; Austin, Alexander J.; Yoong, Hans; Yang, Cary Y.; Cassell, Alan M.; Cruden, Brett A.; Li Jun; Meyyappan, M.

    2005-01-01

    In this letter, we compare the structures of plasma-enhanced chemical vapor deposition of Ni-catalyzed and Pd-catalyzed carbon nanofibers (CNFs) synthesized for on-chip interconnect applications with scanning transmission electron microscopy (STEM). The Ni-catalyzed CNF has a conventional fiberlike structure and many graphitic layers that are almost parallel to the substrate at the CNF base. In contrast, the Pd-catalyzed CNF has a multiwall nanotubelike structure on the sidewall spanning the entire CNF. The microstructure observed in the Pd-catalyzed fibers at the CNF-metal interface has the potential to lower contact resistance significantly, as our electrical measurements using current-sensing atomic force microscopy indicate. A structural model is presented based on STEM image analysis

  7. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  8. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  9. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Science.gov (United States)

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  10. Interconnection blocks: a method for providing reusable, rapid, multiple, aligned and planar microfluidic interconnections

    International Nuclear Information System (INIS)

    Sabourin, D; Snakenborg, D; Dufva, M

    2009-01-01

    In this paper a method is presented for creating 'interconnection blocks' that are re-usable and provide multiple, aligned and planar microfluidic interconnections. Interconnection blocks made from polydimethylsiloxane allow rapid testing of microfluidic chips and unobstructed microfluidic observation. The interconnection block method is scalable, flexible and supports high interconnection density. The average pressure limit of the interconnection block was near 5.5 bar and all individual results were well above the 2 bar threshold considered applicable to most microfluidic applications

  11. A one-semester course in modeling of VSLI interconnections

    CERN Document Server

    Goel, Ashok

    2015-01-01

    Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

  12. Impact of Isothermal Aging and Testing Temperature on Large Flip-Chip BGA Interconnect Mechanical Shock Performance

    Science.gov (United States)

    Lee, Tae-Kyu; Chen, Zhiqiang; Guirguis, Cherif; Akinade, Kola

    2017-10-01

    The stability of solder interconnects in a mechanical shock environment is crucial for large body size flip-chip ball grid array (FCBGA) electronic packages. Additionally, the junction temperature increases with higher electric power condition, which brings the component into an elevated temperature environment, thus introducing another consideration factor for mechanical stability of interconnection joints. Since most of the shock performance data available were produced at room temperature, the effect of elevated temperature is of interest to ensure the reliability of the device in a mechanical shock environment. To achieve a stable␣interconnect in a dynamic shock environment, the interconnections must tolerate mechanical strain, which is induced by the shock wave input and reaches the particular component interconnect joint. In this study, large body size (52.5 × 52.5 mm2) FCBGA components assembled on 2.4-mm-thick boards were tested with various isothermal pre-conditions and testing conditions. With a heating element embedded in the test board, a test temperature range from room temperature to 100°C was established. The effects of elevated temperature on mechanical shock performance were investigated. Failure and degradation mechanisms are identified and discussed based on the microstructure evolution and grain structure transformations.

  13. Lab-on-a-chip for label free biological semiconductor analysis of Staphylococcal Enterotoxin B

    NARCIS (Netherlands)

    Yang, Minghui; Sun, Steven; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

    2010-01-01

    We describe a new lab-on-a-chip (LOC) which utilizes a biological semiconductor (BSC) transducer for label free analysis of Staphylococcal Enterotoxin B (SEB) (or other biological interactions) directly and electronically. BSCs are new transducers based on electrical percolation through a

  14. Integrated Optical Interconnect Architectures for Embedded Systems

    CERN Document Server

    Nicolescu, Gabriela

    2013-01-01

    This book provides a broad overview of current research in optical interconnect technologies and architectures. Introductory chapters on high-performance computing and the associated issues in conventional interconnect architectures, and on the fundamental building blocks for integrated optical interconnect, provide the foundations for the bulk of the book which brings together leading experts in the field of optical interconnect architectures for data communication. Particular emphasis is given to the ways in which the photonic components are assembled into architectures to address the needs of data-intensive on-chip communication, and to the performance evaluation of such architectures for specific applications.   Provides state-of-the-art research on the use of optical interconnects in Embedded Systems; Begins with coverage of the basics for high-performance computing and optical interconnect; Includes a variety of on-chip optical communication topologies; Features coverage of system integration and opti...

  15. Electro-optic techniques for VLSI interconnect

    Science.gov (United States)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  16. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  17. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Hutcheson, L.D.

    1988-01-01

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  18. Carbon nanotubes for interconnects process, design and applications

    CERN Document Server

    Dijon, Jean; Maffucci, Antonio

    2017-01-01

    This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits. Provides a single-source reference on carbon nanotubes for interconnect applications; Includes c...

  19. Low power interconnect design

    CERN Document Server

    Saini, Sandeep

    2015-01-01

    This book provides practical solutions for delay and power reduction for on-chip interconnects and buses.  It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.  Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.   ·         Provides practical solutions for delay and power reduction for on-chip interconnects and buses; ·         Focuses on Deep Sub micron technology devices and interconnects; ·         Offers in depth analysis of delay, including details regarding crosstalk and parasitics;  ·         Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for del...

  20. Optical interconnection networks for high-performance computing systems

    International Nuclear Information System (INIS)

    Biberman, Aleksandr; Bergman, Keren

    2012-01-01

    Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. (review article)

  1. FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

    International Nuclear Information System (INIS)

    Sharma, Devendra Kumar; Kaushik, Brajesh Kumar; Sharma, R. K.

    2014-01-01

    The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line and coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method. (semiconductor integrated circuits)

  2. Area array interconnection handbook

    CERN Document Server

    Totta, Paul A

    2012-01-01

    Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later famil...

  3. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  4. Ultrahigh-speed hybrid laser for silicon photonic integrated chips

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

    2013-01-01

    Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

  5. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

    CERN Multimedia

    Saba, A

    2006-01-01

    2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

  6. Architecture for on-die interconnect

    Science.gov (United States)

    Khare, Surhud; More, Ankit; Somasekhar, Dinesh; Dunning, David S.

    2016-03-15

    In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

  7. An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

    International Nuclear Information System (INIS)

    Zhu Zhang-Ming; Hao Bao-Tian; En Yun-Fei; Yang Yin-Tang; Li Yue-Jin

    2011-01-01

    On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses. (interdisciplinary physics and related areas of science and technology)

  8. Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

    Science.gov (United States)

    Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

    2011-04-25

    Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

  9. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  10. Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects

    Science.gov (United States)

    Peter, Geoffrey John M.

    With the ever-increasing chip complexity, interconnects have to be designed to meet the new challenges. Advances in optical lithography have made chip feature sizes available today at 70 nm dimensions. With advances in Extreme Ultraviolet Lithography, X-ray Lithography, and Ion Projection Lithography it is expected that the line width will further decrease to 20 nm or less. With the decrease in feature size, the number of active devices on the chip increases. With higher levels of circuit integration, the challenge is to dissipate the increased heat flux from the chip surface area. Thermal management considerations include coefficient of thermal expansion (CTE) matching to prevent failure between the chip and the board. This in turn calls for improved system performance and reliability of the electronic structural systems. Experience has shown that in most electronic systems, failures are mostly due to CTE mismatch between the chip, board, and the solder joint (solder interconnect). The resulting high thermal-structural stress and strain due to CTE mismatch produces cracks in the solder joints with eventual failure of the electronic component. In order to reduce the thermal stress between the chip, board, and the solder joint, this dissertation examines the effect of inserting wire bundle (wire interconnect) between the chip and the board. The flexibility of the wires or fibers would reduce the stress at the rigid joints. Numerical simulations of two, and three-dimensional models of the solder and wire interconnects are examined. The numerical simulation is linear in nature and is based on linear isotropic material properties. The effect of different wire material properties is examined. The effect of varying the wire diameter is studied by changing the wire diameter. A major cause of electronic equipment failure is due to fatigue failure caused by thermal cycling, and vibrations. A two-dimensional modal and harmonic analysis was simulated for the wire interconnect

  11. Green interconnecting materials for semiconductor industry

    NARCIS (Netherlands)

    Matin, M.A.; Vellinga, W.P.; Geers, M.G.D.; Sawada, K.; Ishida, M.

    2009-01-01

    Interconnecting materials experience a complex thermo-mechanical load in applications. This may lead to the formation of macroscopic cracks resulting from induced stresses of the differences in thermal expansion coefficients on a sample scale (since different materials are involved) and on a grain

  12. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  13. Circuit and interconnect design for high bit-rate applications

    NARCIS (Netherlands)

    Veenstra, H.

    2006-01-01

    This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

  14. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  15. Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

    Science.gov (United States)

    Seiler, David G.

    1997-10-01

    A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

  16. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Directory of Open Access Journals (Sweden)

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  17. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  18. Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

    Science.gov (United States)

    Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

    2015-11-01

    Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

  19. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Science.gov (United States)

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

  20. Optical interconnection for a polymeric PLC device using simple positional alignment.

    Science.gov (United States)

    Ryu, Jin Hwa; Kim, Po Jin; Cho, Cheon Soo; Lee, El-Hang; Kim, Chang-Seok; Jeong, Myung Yung

    2011-04-25

    This study proposes a simple cost-effective method of optical interconnection between a planar lightwave circuit (PLC) device chip and an optical fiber. It was conducted to minimize and overcome the coupling loss caused by lateral offset which is due to the process tolerance and the dimensional limitation existing between PLC device chips and fiber array blocks with groove structures. A PLC device chip and a fiber array block were simultaneously fabricated in a series of polymer replication processes using the original master. The dimensions (i.e., width and thickness) of the under-clad of the PLC device chip were identical to those of the fiber array block. The PLC device chip and optical fiber were aligned by simple positional control for the vertical direction of the PLC device chip under a particular condition. The insertion loss of the proposed 1 x 2 multimode optical splitter device interconnection was 4.0 dB at 850 nm and the coupling loss was below 0.1 dB compared with single-fiber based active alignment.

  1. Hot Chips and Hot Interconnects for High End Computing Systems

    Science.gov (United States)

    Saini, Subhash

    2005-01-01

    I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

  2. Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

    NARCIS (Netherlands)

    Van den Berg, A.; Ren, P.; Marinissen, E.J.; Gaydadjiev, G.; Goossens, K.

    2010-01-01

    Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or

  3. Bandwidth analysis of functional interconnects used as test access mechanism

    NARCIS (Netherlands)

    Berg, van den Ardy; Ren, P.; Marinissen, Erik Jan; Gaydadjiev, G.N.; Goossens, K.G.W.

    2010-01-01

    Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or

  4. A low-cost, manufacturable method for fabricating capillary and optical fiber interconnects for microfluidic devices.

    Science.gov (United States)

    Hartmann, Daniel M; Nevill, J Tanner; Pettigrew, Kenneth I; Votaw, Gregory; Kung, Pang-Jen; Crenshaw, Hugh C

    2008-04-01

    Microfluidic chips require connections to larger macroscopic components, such as light sources, light detectors, and reagent reservoirs. In this article, we present novel methods for integrating capillaries, optical fibers, and wires with the channels of microfluidic chips. The method consists of forming planar interconnect channels in microfluidic chips and inserting capillaries, optical fibers, or wires into these channels. UV light is manually directed onto the ends of the interconnects using a microscope. UV-curable glue is then allowed to wick to the end of the capillaries, fibers, or wires, where it is cured to form rigid, liquid-tight connections. In a variant of this technique, used with light-guiding capillaries and optical fibers, the UV light is directed into the capillaries or fibers, and the UV-glue is cured by the cone of light emerging from the end of each capillary or fiber. This technique is fully self-aligned, greatly improves both the quality and the manufacturability of the interconnects, and has the potential to enable the fabrication of interconnects in a fully automated fashion. Using these methods, including a semi-automated implementation of the second technique, over 10,000 interconnects have been formed in almost 2000 microfluidic chips made of a variety of rigid materials. The resulting interconnects withstand pressures up to at least 800psi, have unswept volumes estimated to be less than 10 femtoliters, and have dead volumes defined only by the length of the capillary.

  5. Low energy routing platforms for optical interconnects using active plasmonics integrated with Silicon Photonics

    DEFF Research Database (Denmark)

    Vyrsokinos, K.; Papaioannou, S.; Kalavrouziotis, D.

    2013-01-01

    technologies to cope with the massive amount of data moving across all hierarchical communication levels, namely rack-to-rack, backplane, chip-to-chip and even on-chip interconnections. Plasmonics comes indeed as a disruptive technology that enables seamless interoperability between light beams and electronic...

  6. High-density hybrid interconnect methodologies

    International Nuclear Information System (INIS)

    John, J.; Zimmermann, L.; Moor, P.De; Hoof, C.Van

    2003-01-01

    Full text: The presentation gives an overview of the state-of-the-art of hybrid integration and in particular the IMEC technological approaches that will be able to address future hybrid detector needs. The dense hybrid flip-chip integration of an array of detectors and its dedicated readout electronics can be achieved with a variety of solderbump techniques such as pure Indium or Indium alloys, Ph-In, Ni/PbSn, but also conducting polymers... Particularly for cooled applications or ultra-high density applications, Indium solderbump technology (electroplated or evaporated) is the method of choice. The state-of-the-art of solderbump technologies that are to a high degree independent of the underlying detector material will be presented and examples of interconnect densities between 5x1E4cm-2 and 1x1E6 cm-2 will be demonstrated. For several classes of detectors, flip-chip integration is not allowed since the detectors have to be illuminated from the top. This applies to image sensors for EUV applications such as GaN/AlGaN based detectors and to MEMS-based sensors. In such cases, the only viable interconnection method has to be through the (thinned) detector wafer followed by a solderbump-based integration. The approaches for dense and ultra-dense through-the-wafer interconnect 'vias' will be presented and wafer thinning approaches will be shown

  7. Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

    Science.gov (United States)

    Savich, Gregory R.

    2004-01-01

    The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the

  8. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  9. Production and characterization of SLID interconnected n-in-p pixel modules with 75 micron thin silicon sensors

    CERN Document Server

    Andricek, L; Macchiolo, A; Moser, H.G; Nisius, R; Richter, R.H; Terzo, S; Weigell, P

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. T...

  10. Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

    CERN Document Server

    Andricek, L; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tunability, charge collection, cluster sizes and hit efficiencies. Targeting at ...

  11. Computer simulation of electromigration in microelectronics interconnect

    OpenAIRE

    Zhu, Xiaoxin

    2014-01-01

    Electromigration (EM) is a phenomenon that occurs in metal conductor carrying high density electric current. EM causes voids and hillocks that may lead to open or short circuits in electronic devices. Avoiding these failures therefore is a major challenge in semiconductor device and packaging design and manufacturing, and it will become an even greater challenge for the semiconductor assembly and packaging industry as electronics components and interconnects get smaller and smaller. According...

  12. Adaptive Code Division Multiple Access Protocol for Wireless Network-on-Chip Architectures

    Science.gov (United States)

    Vijayakumaran, Vineeth

    Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol

  13. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Science.gov (United States)

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  14. Micro-patterning of self-supporting layers with conducting polymer wires for 3D-chip interconnection applications

    International Nuclear Information System (INIS)

    Ackermann, J.; Videlot, C.; Nguyen, T.N.; Wang, L.; Sarro, P.M.; Crawley, D.; Nikolic, K.; Forshaw, M.

    2003-01-01

    Highly conducting polymers have attracted much interest because of their potential applications in sensors and electronic devices. By the use of templates like porous membranes during polymerization conducting molecular wires can be formed with highly anisotropic properties which can be used as interconnecting layers in a three-dimensional (3D)-chip stacking. We focussed on two electrochemical polymerization (ECP) techniques to produce molecular wires based on polypyrrole (PPy) embedded in isolating porous polycarbonate membranes as self-supporting layers. The growth of the polymer through the membrane pores was investigated in order to achieve a good conductivity through the pores, but with a small cross-talk between them. A new polymerization technique based on a structured cathode has been developed in order to control the polymerization locally. By that technique micro-patterned membranes with separated conducting polymer wires could be produced

  15. Electroless Ni-B plating on SiO2 with 3-aminopropyl-triethoxysilane as a barrier layer against Cu diffusion for through-Si via interconnections in a 3-dimensional multi-chip package

    International Nuclear Information System (INIS)

    Ikeda, Akihiro; Sakamoto, Atsushi; Hattori, Reiji; Kuroki, Yukinori

    2009-01-01

    Electroless Ni-B was plated on SiO 2 as a barrier layer against Cu diffusion for through-Si via (TSV) interconnections in a 3-dimensional multi-chip package. The electroless Ni-B was deposited on the entire area of the SiO 2 side wall of a deep via with vapor phase pre-deposition of 3-aminopropyl-triethoxysilane on the SiO 2 . The carrier lifetimes in the Si substrates plated with Ni-B/Cu did not decrease with an increase in annealing temperature up to 400 deg. C . The absence of degradation of carrier lifetimes indicates that Cu atoms did not diffuse into the Si through the Ni-B. The advantages of electroless Ni-B (good conformal deposition and forming an effective diffusion barrier against Cu) make it useful as a barrier layer for TSV interconnections in a 3-dimensional multi-chip package

  16. A novel conductive-polymer-based integration process for high-performance flip-chip packages

    Science.gov (United States)

    Lohokare, Saurabh

    Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

  17. Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

    Science.gov (United States)

    Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

    2016-05-01

    The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS

  18. Impact of Bundle Structure on Performance of on-Chip CNT Interconnects

    International Nuclear Information System (INIS)

    Kuruvilla, N.; Raina, J.P

    2014-01-01

    CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.

  19. Effects of advanced process approaches on electromigration degradation of Cu on-chip interconnects

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, M.A.

    2007-07-12

    This thesis provides a methodology for the investigation of electromigration (EM) in Cu-based interconnects. An experimental framework based on in-situ scanning electron microscopy (SEM) investigations was developed for that purpose. It is capable to visualize the EM-induced void formation and evolution in multi-level test structures in real time. Different types of interconnects were investigated. Furthermore, stressed and unstressed samples were studied applying advanced physical analysis techniques in order to obtain additional information about the microstructure of the interconnects as well as interfaces and grain boundaries. These data were correlated to the observed degradation phenomena. Correlations of the experimental results to recently established theoretical models were highlighted. Three types of Cu-based interconnects were studied. Pure Cu interconnects were compared to Al-alloyed (CuAl) and CoWP-coated interconnects. The latter two represent potential approaches that address EM-related reliability concerns. It was found that in such interconnects the dominant diffusion path is no longer the Cu/capping layer interface for interconnects as in pure Cu interconnects. Instead, void nucleation occurs at the bottom Cu/barrier interface with significant effects from grain boundaries. Moreover, the in-situ investigations revealed that the initial void nucleation does not occur at the cathode end of the lines but several micrometers away from it. The mean times-to-failure of CuAl and CoWP-coated interconnects were increased by at least one order of magnitude compared to Cu interconnects. The improvements were attributed to the presence of foreign metal atoms at the Cu/capping layer interface. Post-mortem EBSD investigations were used to reveal the microstructure of the tested samples. The data were correlated to the in-situ observations. (orig.)

  20. Packaging and interconnection for superconductive circuitry

    International Nuclear Information System (INIS)

    Anacker, W.

    1976-01-01

    A three dimensional microelectronic module packaged for reduced signal propagation delay times including a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon is described. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits

  1. 2D and 3D interconnect fabrication by picosecond Laser Induced Forward Transfer

    NARCIS (Netherlands)

    Oosterhuis, G.; Huis in 't veld, A.J.; Chall, P.

    2011-01-01

    Interconnects are an important cost driver in advanced 3D chip packaging. This holds for Through Silicon Vias (TSV) for chip stacking, but also for other integrated Si-technology. Especially in applications with a low number (<100 mm-2) of relatively large (10-2- um diameter), high aspect ratio

  2. Fixed Orientation Interconnection Problems: Theory, Algorithms and Applications

    DEFF Research Database (Denmark)

    Zachariasen, Martin

    Interconnection problems have natural applications in the design of integrated circuits (or chips). A modern chip consists of billions of transistors that are connected by metal wires on the surface of the chip. These metal wires are routed on a (fairly small) number of layers in such a way...... that electrically independent nets do not intersect each other. Traditional manufacturing technology limits the orientations of the wires to be either horizontal or vertical — and is known as Manhattan architecture. Over the last decade there has been a growing interest in general architectures, where more than two...... a significant step forward, both concerning theory and algorithms, for the fixed orientation Steiner tree problem. In addition, the work maintains a close link to applications and generalizations motivated by chip design....

  3. Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

    Science.gov (United States)

    Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

    2018-08-01

    In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

  4. Adapting Memory Hierarchies for Emerging Datacenter Interconnects

    Institute of Scientific and Technical Information of China (English)

    江涛; 董建波; 侯锐; 柴琳; 张立新; 孙凝晖; 田斌

    2015-01-01

    Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects—particularly as they affect remote memory access—and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms: a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes;and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and limitations.

  5. Testing of modern semiconductor memory structures

    NARCIS (Netherlands)

    Gaydadjiev, G.N.

    2007-01-01

    In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

  6. α-particle shielding of semiconductor device

    International Nuclear Information System (INIS)

    McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

    1981-01-01

    Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

  7. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  8. Production and characterisation of SLID interconnected n-in-p pixel modules with 75 μm thin silicon sensors

    Energy Technology Data Exchange (ETDEWEB)

    Andricek, L. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Beimforde, M.; Macchiolo, A.; Moser, H.-G. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Nisius, R., E-mail: Richard.Nisius@mpp.mpg.de [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Richter, R.H. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Terzo, S.; Weigell, P. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany)

    2014-09-11

    The performance of pixel modules built from 75 μm thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 μm thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of 10{sup 16}n{sub eq}/cm{sup 2}.

  9. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    (clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic......Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

  10. One-step fabrication of microfluidic chips with in-plane, adhesive-free interconnections

    DEFF Research Database (Denmark)

    Sabourin, David; Dufva, Martin; Jensen, Thomas Glasdam

    2010-01-01

    A simple method for creating interconnections to a common microfluidic device material, poly(methyl methacrylate) (PMMA), is presented. A press-fit interconnection is created between oversized, deformable tubing and complementary, undersized semi-circular ports fabricated into PMMA bonding surfac...

  11. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...

  12. Tuning and synthesis of semiconductor nanostructures by mechanical compression

    Energy Technology Data Exchange (ETDEWEB)

    Fan, Hongyou; Li, Binsong

    2015-11-17

    A mechanical compression method can be used to tune semiconductor nanoparticle lattice structure and synthesize new semiconductor nanostructures including nanorods, nanowires, nanosheets, and other three-dimensional interconnected structures. II-VI or IV-VI compound semiconductor nanoparticle assemblies can be used as starting materials, including CdSe, CdTe, ZnSe, ZnS, PbSe, and PbS.

  13. Standard semiconductor packaging for high-reliability low-cost MEMS applications

    Science.gov (United States)

    Harney, Kieran P.

    2005-01-01

    Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

  14. Optimization of high frequency flip-chip interconnects for digital superconducting circuits

    International Nuclear Information System (INIS)

    Rafique, M R; Engseth, H; Kidiyarova-Shevchenko, A

    2006-01-01

    This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than -20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s -1 speedand can operate above 100 Gbit s -1 speed. Wide bandwidth transmission requires the realization of an advanced flip-chip process with a small dimension of the MCM contact (less than 30 μm diameter of the contact pad) and small height of the flip-chip contact bumps of the order of 2 μm. Current processes with about 7 μm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s -1 ; however, the maximum speed of operation is 61 Gbit s -1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link

  15. AN ACCURATE MODELING OF DELAY AND SLEW METRICS FOR ON-CHIP VLSI RC INTERCONNECTS FOR RAMP INPUTS USING BURR’S DISTRIBUTION FUNCTION

    Directory of Open Access Journals (Sweden)

    Rajib Kar

    2010-09-01

    Full Text Available This work presents an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS circuits foe ramp input. Our metric assumption is based on the Burr’s Distribution function. The Burr’s distribution is used to characterize the normalized homogeneous portion of the step response. We used the PERI (Probability distribution function Extension for Ramp Inputs technique that extends delay metrics and slew metric for step inputs to the more general and realistic non-step inputs. The accuracy of our models is justified with the results compared with that of SPICE simulations.

  16. Design and Training of Limited-Interconnect Architectures

    Science.gov (United States)

    1991-07-16

    and signal processing. Neuromorphic (brain like) models, allow an alternative for achieving real-time operation tor such tasks, while having a...compact and robust architecture. Neuromorphic models consist of interconnections of simple computational nodes. In this approach, each node computes a...operational performance. I1. Research Objectives The research objectives were: 1. Development of on- chip local training rules specifically designed for

  17. Where the chips fall: environmental health in the semiconductor industry.

    Science.gov (United States)

    Chepesiuk, R

    1999-09-01

    Three recent lawsuits are focusing public attention on the environmental and occupational health effects of the world's largest and fastest growing manufacturing sector-the $150 billion semiconductor industry. The suits allege that exposure to toxic chemicals in semiconductor manufacturing plants led to adverse health effects such as miscarriage and cancer among workers. To manufacture computer components, the semiconductor industry uses large amounts of hazardous chemicals including hydrochloric acid, toxic metals and gases, and volatile solvents. Little is known about the long-term health consequences of exposure to chemicals by semiconductor workers. According to industry critics, the semiconductor industry also adversely impacts the environment, causing groundwater and air pollution and generating toxic waste as a by-product of the semiconductor manufacturing process. In contrast, the U.S. Bureau of Statistics shows the semiconductor industry as having a worker illness rate of about one-third of the average of all manufacturers, and advocates defend the industry, pointing to recent research collaborations and product replacement as proof that semiconductor manufacturers adequately protect both their employees and the environment.

  18. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    Science.gov (United States)

    Rogers, John A; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

    2014-05-20

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  19. Influence of interconnection on the long-term reliability of UV LED packages

    Science.gov (United States)

    Nieland, S.; Mitrenga, D.; Karolewski, D.; Brodersen, O.; Ortlepp, T.

    2017-02-01

    High power LEDs have conquered the mass market in recent years. Besides the main development focus to achieve higher productivity in the field of visible semiconductor LED processing, the wavelength range is further enhanced by active research and development in the direction of UVA / UVB / UVC. UVB and UVC LEDs are new and promising due to their numerous advantages. UV LEDs emit in a near range of one single emission peak with a width (FWHM) below 15 nm compared to conventional mercury discharge lamps and xenon sources, which show broad spectrums with many emission peaks over a wide range of wavelengths. Furthermore, the UV LED size is in the range of a few hundred microns and offers a high potential of significant system miniaturization. Of course, LED efficiency, lifetime and output power have to be increased [1]. Lifetime limiting issues of UVB/UVC-LED are the very high thermal stress in the chip resulting from the higher forward voltages (6-10 V @ 350 mA), the lower external quantum efficiency, below 10 % (most of the power disappears as heat), and the thermal resistance Rth of conventional LED packages being not able to dissipate these large amounts of heat for spreading. Beside the circuit boards and submounts which should have maximum thermal conductivity, the dimension of contacts as well as the interconnection of UV LED to the submount/package determinates the resolvable amount of heat [2]. In the paper different innovative interconnection techniques for UVC-LED systems will be discussed focused on the optimization of thermal conductivity in consideration of the assembly costs. Results on thermal simulation for the optimal contact dimensions and interconnections will be given. In addition, these theoretical results will be compared with results on electrical characterization as well as IR investigations on real UV LED packages in order to give recommendations for optimal UV LED assembly.

  20. Optoelectronic integrated circuits utilising vertical-cavity surface-emitting semiconductor lasers

    International Nuclear Information System (INIS)

    Zakharov, S D; Fyodorov, V B; Tsvetkov, V V

    1999-01-01

    Optoelectronic integrated circuits with additional optical inputs/outputs, in which vertical-cavity surface-emitting (VCSE) lasers perform the data transfer functions, are considered. The mutual relationship and the 'affinity' between optical means for data transfer and processing, on the one hand, and the traditional electronic component base, on the other, are demonstrated in the case of implementation of three-dimensional interconnects with a high transmission capacity. Attention is drawn to the problems encountered when semiconductor injection lasers are used in communication lines. It is shown what role can be played by VCSE lasers in solving these problems. A detailed analysis is made of the topics relating to possible structural and technological solutions in the fabrication of single lasers and of their arrays, and also of the problems hindering integrating of lasers into emitter arrays. Considerable attention is given to integrated circuits with optoelectronic smart pixels. Various technological methods for vertical integration of GaAs VCSE lasers with the silicon substrate of a microcircuit (chip) are discussed. (review)

  1. 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

    Directory of Open Access Journals (Sweden)

    Lee Mike Myung-Ok

    2006-01-01

    Full Text Available This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch through an indium bump interconnection array (IBIA. The configurable array processor (CAP is an array of heterogeneous processing elements (PEs, while the intelligent configurable switch (ICS comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

  2. An RLC interconnect analyzable crosstalk model considering self-heating effect

    International Nuclear Information System (INIS)

    Zhu Zhang-Ming; Liu Shu-Bin

    2012-01-01

    According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance—inductance—capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal—oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits. (interdisciplinary physics and related areas of science and technology)

  3. Metal-semiconductor interface in extreme temperature conditions

    International Nuclear Information System (INIS)

    Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

    2008-01-01

    We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

  4. Modular cryogenic interconnects for multi-qubit devices

    Energy Technology Data Exchange (ETDEWEB)

    Colless, J. I.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, The University of Sydney, Sydney, NSW 2006 (Australia)

    2014-11-15

    We have developed a modular interconnect platform for the control and readout of multiple solid-state qubits at cryogenic temperatures. The setup provides 74 filtered dc-bias connections, 32 control and readout connections with −3 dB frequency above 5 GHz, and 4 microwave feed lines that allow low loss (less than 3 dB) transmission 10 GHz. The incorporation of a radio-frequency interposer enables the platform to be separated into two printed circuit boards, decoupling the simple board that is bonded to the qubit chip from the multilayer board that incorporates expensive connectors and components. This modular approach lifts the burden of duplicating complex interconnect circuits for every prototype device. We report the performance of this platform at milli-Kelvin temperatures, including signal transmission and crosstalk measurements.

  5. Introduction to semiconductor manufacturing technology

    CERN Document Server

    2012-01-01

    IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

  6. X-ray imaging with photon counting hybrid semiconductor pixel detectors

    CERN Document Server

    Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

    1999-01-01

    Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

  7. An integrated semiconductor device enabling non-optical genome sequencing.

    Science.gov (United States)

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  8. Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

    Directory of Open Access Journals (Sweden)

    Salman Shafqat

    2017-09-01

    Full Text Available The exciting field of stretchable electronics (SE promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS-type process recipes using bulk integrated circuit (IC microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic stretch beyond 3000%, with <0.3% resistance change, and >10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.

  9. Room temperature cryogenic test interface

    International Nuclear Information System (INIS)

    Faris, S. M.; Davidson, A.; Moskowitz, P. A.; Sai-Halasz, G. A.

    1985-01-01

    This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station, with the cryogenic chip attached, extends into the liquid helium reservoir. The second chip station is in the room temperature environment required for semiconductor operation. Proper semiconductor operating temperature is achieved by a heater wire and control thermocouple in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus

  10. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  11. Solid-Phase Immunoassay of Polystyrene-Encapsulated Semiconductor Coreshells for Cardiac Marker Detection

    Directory of Open Access Journals (Sweden)

    Sanghee Kim

    2012-01-01

    Full Text Available A solid-phase immunoassay of polystyrene-encapsulated semiconductor nanoparticles was demonstrated for cardiac troponin I (cTnI detection. CdSe/ZnS coreshells were encapsulated with a carboxyl-functionalized polystyrene nanoparticle to capture the target antibody through a covalent bonding and to eliminate the photoblinking and toxicity of semiconductor luminescent immunosensor. The polystyrene-encapsulated CdSe/ZnS fluorophores on surface-modified glass chip identified cTnI antigens at the level of ~ng/mL. It was an initial demonstration of diagnostic chip for monitoring a cardiovascular disease.

  12. On-chip mode division multiplexing technologies

    DEFF Research Database (Denmark)

    Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

    2016-01-01

    Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... photonic integrated circuit mode (de) multiplexer for few-mode fibers (FMFs)....

  13. Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

    Science.gov (United States)

    Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

    2012-06-01

    The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

  14. SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

    Energy Technology Data Exchange (ETDEWEB)

    MCBRAYER,JOHN D.

    2000-12-01

    This report summarizes the results of work conducted by the Semiconductor Manufacturing Technologies Program at Sandia National Laboratories (Sandia) during 1999. This work was performed by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaF{sub 2}); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program.

  15. Incorporation of in-plane interconnects to reflow bonding for electrical functionality

    International Nuclear Information System (INIS)

    Moğulkoç, B; Jansen, H V; Ter Brake, H J M; Elwenspoek, M C

    2011-01-01

    Incorporation of in-plane electrical interconnects to reflow bonding is studied to provide electrical functionality to lab-on-a-chip or microfluidic devices. Reflow bonding is the packaging technology, in which glass tubes are joined to silicon substrates at elevated temperatures. The tubes are used to interface the silicon-based fluidic devices and are directly compatible with standard Swagelok® connectors. After the bonding, the electrically conductive lines will allow probing into the volume confined by the tube, where the fluidic device operates. Therefore methods for fabricating electrical interconnects that survive the bonding procedure at elevated temperature and do not alter the properties of the bond interface are investigated

  16. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

  17. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  18. Organic semiconductors in sensor applications

    CERN Document Server

    Malliaras, George; Owens, Róisín

    2008-01-01

    Organic semiconductors offer unique characteristics such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing, and facile integration with chemical and biological functionalities. These characteristics have prompted the application of organic semiconductors and their devices in physical, chemical, and biological sensors. This book covers this rapidly emerging field by discussing both optical and electrical sensor concepts. Novel transducers based on organic light-emitting diodes and organic thin-film transistors, as well as systems-on-a-chip architectures are presented. Functionalization techniques to enhance specificity are outlined, and models for the sensor response are described.

  19. Semiconductor laser joint study program with Rome Laboratory

    Science.gov (United States)

    Schaff, William J.; Okeefe, Sean S.; Eastman, Lester F.

    1994-09-01

    A program to jointly study vertical-cavity surface emitting lasers (VCSEL) for high speed vertical optical interconnects (VOI) has been conducted under an ES&E between Rome Laboratory and Cornell University. Lasers were designed, grown, and fabricated at Cornell University. A VCSEL measurement laboratory has been designed, built, and utilized at Rome Laboratory. High quality VCSEL material was grown and characterized by fabricating conventional lateral cavity lasers that emitted at the design wavelength of 1.04 microns. The VCSEL's emit at 1.06 microns. Threshold currents of 16 mA at 4.8 volts were obtained for 30 microns diameter devices. Output powers of 5 mW were measured. This is 500 times higher power than from the light emitting diodes employed previously for vertical optical interconnects. A new form of compositional grading using a cosinusoidal function has been developed and is very successful for reducing diode series resistance for high speed interconnection applications. A flip-chip diamond package compatible with high speed operation of 16 VCSEL elements has been designed and characterized. A flip-chip device binding effort at Rome Laboratory was also designed and initiated. This report presents details of the one-year effort, including process recipes and results.

  20. Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

    Science.gov (United States)

    Michaelides, Stylianos

    Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

  1. 11.72 sq cm SiC Wafer-scale Interconnected 64 kA PiN Diode

    Science.gov (United States)

    2012-01-30

    drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA2 -s. Preliminary development of high voltage interconnection...scale diode action (surge current integral), a key reliability parameter, exceeded 1.7 MA2 -s. Figure 6: The wafer-scale interconnected diode...scale diode was 382 J and the calculated action exceeded 1.7 MA2 -sec. High voltage operation of PiN diodes, thyristors, and other semiconductor

  2. Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅10 15 $n_{eq}$ /cm 2

    CERN Document Server

    Weigell, P; Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H

    2011-01-01

    A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to 2⋅10 15 \\,\

  3. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

    Science.gov (United States)

    Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

    2018-04-01

    Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

  4. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    KAUST Repository

    Sevilla, Galo T.

    2016-02-29

    Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  5. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  6. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  7. Field testing for cosmic ray soft errors in semiconductor memories

    International Nuclear Information System (INIS)

    O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

    1996-01-01

    This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

  8. Digitally tunable dual wavelength emission from semiconductor ring lasers with filtered optical feedback

    International Nuclear Information System (INIS)

    Khoder, Mulham; Verschaffelt, Guy; Nguimdo, Romain Modeste; Danckaert, Jan; Leijtens, Xaveer; Bolk, Jeroen

    2013-01-01

    We report on a novel integrated approach to obtain dual wavelength emission from a semiconductor laser based on on-chip filtered optical feedback. Using this approach, we show experiments and numerical simulations of dual wavelength emission of a semiconductor ring laser. The filtered optical feedback is realized on-chip by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifiers are placed in the feedback loop in order to control the feedback strength of each wavelength channel independently. By tuning the current injected into each of the amplifiers, we can effectively cancel the gain difference between the wavelength channels due to fabrication and material dichroism, thus resulting in stable dual wavelength emission. We also explore the accuracy needed in the operational parameters to maintain this dual wavelength emission. (letter)

  9. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  10. Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2$\\cdot 10^{15}$\\,n$_{\\mathrm{eq}}$/cm$^2$

    CERN Document Server

    INSPIRE-00237859; Beimforde, M.; Macchiolo, A.; Moser, H.G.; Nisius, R.; Richter, R.H.

    2011-01-01

    A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to $2\\cdot10^{15}$\\,\

  11. Origin of high photoconductive gain in fully transparent heterojunction nanocrystalline oxide image sensors and interconnects.

    Science.gov (United States)

    Jeon, Sanghun; Song, Ihun; Lee, Sungsik; Ryu, Byungki; Ahn, Seung-Eon; Lee, Eunha; Kim, Young; Nathan, Arokia; Robertson, John; Chung, U-In

    2014-11-05

    A technique for invisible image capture using a photosensor array based on transparent conducting oxide semiconductor thin-film transistors and transparent interconnection technologies is presented. A transparent conducting layer is employed for the sensor electrodes as well as interconnection in the array, providing about 80% transmittance at visible-light wavelengths. The phototransistor is a Hf-In-Zn-O/In-Zn-O heterostructure yielding a high quantum-efficiency in the visible range. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-07-30

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  13. Near-chip compliant layer for reducing perimeter stress during assembly process

    Energy Technology Data Exchange (ETDEWEB)

    Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

    2018-03-20

    A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

  14. Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

    OpenAIRE

    Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.

    2001-01-01

    The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interco...

  15. Two-dimensional optoelectronic interconnect-processor and its operational bit error rate

    Science.gov (United States)

    Liu, J. Jiang; Gollsneider, Brian; Chang, Wayne H.; Carhart, Gary W.; Vorontsov, Mikhail A.; Simonis, George J.; Shoop, Barry L.

    2004-10-01

    Two-dimensional (2-D) multi-channel 8x8 optical interconnect and processor system were designed and developed using complementary metal-oxide-semiconductor (CMOS) driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the photodetector (PD) arrays with corresponding wavelengths. We performed operation and bit-error-rate (BER) analysis on this free-space integrated 8x8 VCSEL optical interconnects driven by silicon-on-sapphire (SOS) circuits. Pseudo-random bit stream (PRBS) data sequence was used in operation of the interconnects. Eye diagrams were measured from individual channels and analyzed using a digital oscilloscope at data rates from 155 Mb/s to 1.5 Gb/s. Using a statistical model of Gaussian distribution for the random noise in the transmission, we developed a method to compute the BER instantaneously with the digital eye-diagrams. Direct measurements on this interconnects were also taken on a standard BER tester for verification. We found that the results of two methods were in the same order and within 50% accuracy. The integrated interconnects were investigated in an optoelectronic processing architecture of digital halftoning image processor. Error diffusion networks implemented by the inherently parallel nature of photonics promise to provide high quality digital halftoned images.

  16. Analysis and simulation of semiconductor devices

    CERN Document Server

    Selberherr, Siegfried

    1984-01-01

    The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

  17. Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

    Science.gov (United States)

    Wu, Yuan-Yun

    In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a

  18. On-chip spin-controlled orbital angular momentum directional coupling

    Science.gov (United States)

    Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

    2018-01-01

    Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

  19. Future semiconductor material requirements and innovations as projected in the ITRS 2005 roadmap

    International Nuclear Information System (INIS)

    Arden, Wolfgang

    2006-01-01

    The international technology roadmap for semiconductors (ITRS) is a joint global effort of the semiconductor industry, the manufacturing equipment and material industry and the research community and consortia to define the future requirements and development of the semiconductor technology for the next 15 years. The ITRS started in 1992 as a US-national roadmap and became an international effort in 1998 with all major five industrial global regions (US, Japan, Taiwan, Korea and Europe) participating in its definition. The outlook in semiconductor manufacturing expects the continuous application of silicon technology for the next 15 years where complementary metal oxide semiconductor (CMOS) based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decade. The major section of the ITRS contains technical information about frontend processing and interconnects, device structures and memory concepts, lithography and metrology as well as factory integration and environmental issues. This paper will review the material requirements and the expected material innovations for the industry as outlined in the ITRS Version 2005. Materials to be discussed are, for example, high permittivity gate dielectrics, insulating layers with low dielectric constants for interconnects, and capacitor dielectrics for dynamic memories. In addition, the paper will address, for example, new transistor gate materials, new solutions for interconnect systems beyond copper as well as new starting materials for wafer sizes beyond 300 mm. This publication was presented as an invited paper in the Symposium V of the 2006 spring meeting of the European Materials Research Society (E-MRS) in Nice, May 29th

  20. Fabrication method to create high-aspect ratio pillars for photonic coupling of board level interconnects

    Science.gov (United States)

    Debaes, C.; Van Erps, J.; Karppinen, M.; Hiltunen, J.; Suyal, H.; Last, A.; Lee, M. G.; Karioja, P.; Taghizadeh, M.; Mohr, J.; Thienpont, H.; Glebov, A. L.

    2008-04-01

    An important challenge that remains to date in board level optical interconnects is the coupling between the optical waveguides on printed wiring boards and the packaged optoelectronics chips, which are preferably surface mountable on the boards. One possible solution is the use of Ball Grid Array (BGA) packages. This approach offers a reliable attachment despite the large CTE mismatch between the organic FR4 board and the semiconductor materials. Collimation via micro-lenses is here typically deployed to couple the light vertically from the waveguide substrate to the optoelectronics while allowing for a small misalignment between board and package. In this work, we explore the fabrication issues of an alternative approach in which the vertical photonic connection between board and package is governed by a micro-optical pillar which is attached both to the board substrate and to the optoelectronic chips. Such an approach allows for high density connections and small, high-speed detector footprints while maintaining an acceptable tolerance between board and package. The pillar should exhibit some flexibility and thus a high-aspect ratio is preferred. This work presents and compares different fabrication methods and applies different materials for such high-aspect ratio pillars. The different fabrication methods are: photolithography, direct laser writing and deep proton writing. The selection of optical materials that was investigated is: SU8, Ormocers, PU and a multifunctional acrylate polymer. The resulting optical pillars have diameters ranging from 20um up to 80um, with total heights ranging between 30um and 100um (symbol for micron). The aspect-ratio of the fabricated structures ranges from 1.5 to 5.

  1. Thermoelectric Coolers with Sintered Silver Interconnects

    Science.gov (United States)

    Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2014-06-01

    The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

  2. Estimate the thermomechanical fatigue life of two flip chip packages

    International Nuclear Information System (INIS)

    Pash, R.A.; Ullah, H.S.; Khan, M.Z.

    2005-01-01

    The continuing demand towards high density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology, ball grid array (BOA) and chip scale package (CSP). In such structures the most widely used flip chip interconnects are solder joints. The reliability of flip chip structures largely depends on the reliability of solder joints. In this work solder joint fatigue life prediction for two chip scale packages is carried out. Elasto-plastic deformation behavior of the solder was simulated using ANSYS. Two dimensional plain strain finite element models were developed for each package to numerically compute the stress and total strain of the solder joints under temperature cycling. These stress and strain values are then used to predict the solder joint lifetime through modified Coffin Manson equation. The effect of solder joint's distance from edge of silicon die on life of the package is explored. The solder joint fatigue response is modeled for a typical temperature cycling of -60 to 140 degree C. (author)

  3. Microelectronics used for Semiconductor Imaging Detectors

    CERN Document Server

    Heijne, Erik H M

    2010-01-01

    Semiconductor crystal technology, microelectronics developments and nuclear particle detection have been in a relation of symbiosis, all the way from the beginning. The increase of complexity in electronics chips can now be applied to obtain much more information on the incident nuclear radiation. Some basic technologies are described, in order to acquire insight in possibilities and limitations for the most recent detectors.

  4. Dry etching technology for semiconductors

    CERN Document Server

    Nojiri, Kazuo

    2015-01-01

    This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

  5. Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

    Science.gov (United States)

    Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

    2007-04-01

    In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

  6. Compound semiconductor optical waveguide switch

    Science.gov (United States)

    Spahn, Olga B.; Sullivan, Charles T.; Garcia, Ernest J.

    2003-06-10

    An optical waveguide switch is disclosed which is formed from III-V compound semiconductors and which has a moveable optical waveguide with a cantilevered portion that can be bent laterally by an integral electrostatic actuator to route an optical signal (i.e. light) between the moveable optical waveguide and one of a plurality of fixed optical waveguides. A plurality of optical waveguide switches can be formed on a common substrate and interconnected to form an optical switching network.

  7. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  8. 75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

    Science.gov (United States)

    2010-03-02

    ... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

  9. SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

    Science.gov (United States)

    Fresh, D. L.; Adolphsen, J. W.

    1974-01-01

    A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

  10. Key techniques for space-based solar pumped semiconductor lasers

    Science.gov (United States)

    He, Yang; Xiong, Sheng-jun; Liu, Xiao-long; Han, Wei-hua

    2014-12-01

    In space, the absence of atmospheric turbulence, absorption, dispersion and aerosol factors on laser transmission. Therefore, space-based laser has important values in satellite communication, satellite attitude controlling, space debris clearing, and long distance energy transmission, etc. On the other hand, solar energy is a kind of clean and renewable resources, the average intensity of solar irradiation on the earth is 1353W/m2, and it is even higher in space. Therefore, the space-based solar pumped lasers has attracted much research in recent years, most research focuses on solar pumped solid state lasers and solar pumped fiber lasers. The two lasing principle is based on stimulated emission of the rare earth ions such as Nd, Yb, Cr. The rare earth ions absorb light only in narrow bands. This leads to inefficient absorption of the broad-band solar spectrum, and increases the system heating load, which make the system solar to laser power conversion efficiency very low. As a solar pumped semiconductor lasers could absorb all photons with energy greater than the bandgap. Thus, solar pumped semiconductor lasers could have considerably higher efficiencies than other solar pumped lasers. Besides, solar pumped semiconductor lasers has smaller volume chip, simpler structure and better heat dissipation, it can be mounted on a small satellite platform, can compose satellite array, which can greatly improve the output power of the system, and have flexible character. This paper summarizes the research progress of space-based solar pumped semiconductor lasers, analyses of the key technologies based on several application areas, including the processing of semiconductor chip, the design of small and efficient solar condenser, and the cooling system of lasers, etc. We conclude that the solar pumped vertical cavity surface-emitting semiconductor lasers will have a wide application prospects in the space.

  11. Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2010-01-01

    Abstract—This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair

  12. Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

    Science.gov (United States)

    Pleros, Nikos; Maniotis, Pavlos; Alexoudi, Theonitsa; Fitsios, Dimitris; Vagionas, Christos; Papaioannou, Sotiris; Vyrsokinos, K.; Kanellos, George T.

    2014-03-01

    The processor-memory performance gap, commonly referred to as "Memory Wall" problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

  13. Advanced organics for electronic substrates and packages

    CERN Document Server

    Fletcher, Andrew E

    1992-01-01

    Advanced Organics for Electronic Substrates and Packages provides information on packaging, which is one of the most technologically intensive activities in the electronics industry. The electronics packaging community has realized that while semiconductor devices continue to be improved upon for performance, cost, and reliability, it is the interconnection or packaging of these devices that will limit the performance of the systems. Technology must develop packaging for transistor chips, with high levels of performance and integration providing cooling, power, and interconnection, and yet pre

  14. Photonics-on-a-chip: recent advances in integrated waveguides as enabling detection elements for real-world, lab-on-a-chip biosensing applications.

    Science.gov (United States)

    Washburn, Adam L; Bailey, Ryan C

    2011-01-21

    By leveraging advances in semiconductor microfabrication technologies, chip-integrated optical biosensors are poised to make an impact as scalable and multiplexable bioanalytical measurement tools for lab-on-a-chip applications. In particular, waveguide-based optical sensing technology appears to be exceptionally amenable to chip integration and miniaturization, and, as a result, the recent literature is replete with examples of chip-integrated waveguide sensing platforms developed to address a wide range of contemporary analytical challenges. As an overview of the most recent advances within this dynamic field, this review highlights work from the last 2-3 years in the areas of grating-coupled, interferometric, photonic crystal, and microresonator waveguide sensors. With a focus towards device integration, particular emphasis is placed on demonstrations of biosensing using these technologies within microfluidically controlled environments. In addition, examples of multiplexed detection and sensing within complex matrices--important features for real-world applicability--are given special attention.

  15. Semiconductor detectors with proximity signal readout

    International Nuclear Information System (INIS)

    Asztalos, Stephen J.

    2012-01-01

    Semiconductor-based radiation detectors are routinely used for the detection, imaging, and spectroscopy of x-rays, gamma rays, and charged particles for applications in the areas of nuclear and medical physics, astrophysics, environmental remediation, nuclear nonproliferation, and homeland security. Detectors used for imaging and particle tracking are more complex in that they typically must also measure the location of the radiation interaction in addition to the deposited energy. In such detectors, the position measurement is often achieved by dividing or segmenting the electrodes into many strips or pixels and then reading out the signals from all of the electrode segments. Fine electrode segmentation is problematic for many of the standard semiconductor detector technologies. Clearly there is a need for a semiconductor-based radiation detector technology that can achieve fine position resolution while maintaining the excellent energy resolution intrinsic to semiconductor detectors, can be fabricated through simple processes, does not require complex electrical interconnections to the detector, and can reduce the number of required channels of readout electronics. Proximity electrode signal readout (PESR), in which the electrodes are not in physical contact with the detector surface, satisfies this need

  16. Laser isotope purification of lead for use in semiconductor chip interconnects

    International Nuclear Information System (INIS)

    Scheibner, K.; Haynam, C.; Worden, E.; Esser, B.

    1996-01-01

    Lead, used throughout the electronics industries, typically contains small amounts of radioactive 210 Pb (a daughter product of the planets ubiquitous 238 U) whose 210 Po daughter emits an α-particle that is known to cause soft errors in electronic circuits. The 210 Pb is not separable by chemical means. This paper describes the generic Atomic Vapor Laser Isotope Separation (AVLIS) process developed at the Lawrence Livermore National Laboratory (LLNL) over the last 20 years, with particular emphasis on recent efforts to develop the process physics and component technologies required to remove the offending 210 Pb using lasers. We have constructed a developmental facility that includes a process laser development area and a test bed for the vaporizer and ion and product collectors. We will be testing much of the equipment and demonstrating pilot scale AVLIS on a surrogate material later this year. Detection of the very low alpha emission even from commercially available low-alpha lead is challenging. LLNL's detection capabilities will be described. The goal of the development of lead purification technology is to demonstrate the capability in FY97, and to deploy a production machine capable of up to several MT/y of isotopically purified material, possible beginning in FY98

  17. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  18. Chip-integrated optical power limiter based on an all-passive micro-ring resonator

    Science.gov (United States)

    Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

    2014-10-01

    Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

  19. Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects.

    Science.gov (United States)

    Gooth, Johannes; Borg, Mattias; Schmid, Heinz; Schaller, Vanessa; Wirths, Stephan; Moselund, Kirsten; Luisier, Mathieu; Karg, Siegfried; Riel, Heike

    2017-04-12

    Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.

  20. Nanoantenna couplers for metal-insulator-metal waveguide interconnects

    Science.gov (United States)

    Onbasli, M. Cengiz; Okyay, Ali K.

    2010-08-01

    State-of-the-art copper interconnects suffer from increasing spatial power dissipation due to chip downscaling and RC delays reducing operation bandwidth. Wide bandwidth, minimized Ohmic loss, deep sub-wavelength confinement and high integration density are key features that make metal-insulator-metal waveguides (MIM) utilizing plasmonic modes attractive for applications in on-chip optical signal processing. Size-mismatch between two fundamental components (micron-size fibers and a few hundred nanometers wide waveguides) demands compact coupling methods for implementation of large scale on-chip optoelectronic device integration. Existing solutions use waveguide tapering, which requires more than 4λ-long taper distances. We demonstrate that nanoantennas can be integrated with MIM for enhancing coupling into MIM plasmonic modes. Two-dimensional finite-difference time domain simulations of antennawaveguide structures for TE and TM incident plane waves ranging from λ = 1300 to 1600 nm were done. The same MIM (100-nm-wide Ag/100-nm-wide SiO2/100-nm-wide Ag) was used for each case, while antenna dimensions were systematically varied. For nanoantennas disconnected from the MIM; field is strongly confined inside MIM-antenna gap region due to Fabry-Perot resonances. Major fraction of incident energy was not transferred into plasmonic modes. When the nanoantennas are connected to the MIM, stronger coupling is observed and E-field intensity at outer end of core is enhanced more than 70 times.

  1. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  2. A study on the optical parts for a semiconductor laser module

    Energy Technology Data Exchange (ETDEWEB)

    Oh, Jun-Girl; Lee, Dong-Kil; Kim, Yang-Gyu; Lee, Kwang-Hoon; Park, Young-Sik [Korea Photonics Technology Institute, Gwangju (Korea, Republic of); Jang, Kwang-Ho [Hanvit Optoline, Gwangju (Korea, Republic of); Kang, Seung-Goo [COSET, Gwangju (Korea, Republic of)

    2014-11-15

    A semiconductor laser module consists of a LD (laser diode) chip that generates a laser beam, two cylindrical lenses to collimate the laser beam, a high-reflection mirror to produce a large output by collecting the laser beam, a collimator lens to guide the laser beam to an optical fiber and a protection filter to block reflected laser light that might damage the LD chip. The cylindrical lenses used in a semiconductor laser module are defined as FACs (fast axis collimators) and SACs (slow axis collimators) and are attached to the system module to control the shape of the laser beam. The FAC lens and the SAC lens are made of a glass material to protect the lenses from thermal deformation. In addition, they have aspheric shapes to improve optical performances. This paper presents a mold core grinding process for an asymmetrical aspheric lens and a GMP (glass molding press), what can be used to make aspheric cylindrical lenses for use as FACs or SACs, and a protection filter made by using IAD (ion-beam-assisted deposition). Finally, we developed the aspheric cylindrical lenses and the protection filter for a 10-W semiconductor laser module.

  3. Optically coupled semiconductor device

    Energy Technology Data Exchange (ETDEWEB)

    Kumagaya, Naoki

    1988-11-18

    This invention concerns an optically coupled semiconductor device using the light as input signal and a MOS transistor for the output side in order to control on-off of the output side by the input signal which is insulated from the output. Concerning this sort of element, when a MOS transistor and a load resistance are planned to be accumulated on the same chip, a resistor and control of impurity concentration of the channel, etc. become necessary despite that the only formation of a simple P-N junction is enough, for a solar cell, hence cost reduction thereof cannot be done. In order to remove this defect, this invention offers an optically coupled semiconductor device featuring that two solar cells are connected in reverse parallel between the gate sources of the output MOS transistors and an operational light emitting element is individually set facing a respective solar cell. 4 figs.

  4. An efficient network for interconnecting remote monitoring instruments and computers

    International Nuclear Information System (INIS)

    Halbig, J.K.; Gainer, K.E.; Klosterbuer, S.F.

    1994-01-01

    Remote monitoring instrumentation must be connected with computers and other instruments. The cost and intrusiveness of installing cables in new and existing plants presents problems for the facility and the International Atomic Energy Agency (IAEA). The authors have tested a network that could accomplish this interconnection using mass-produced commercial components developed for use in industrial applications. Unlike components in the hardware of most networks, the components--manufactured and distributed in North America, Europe, and Asia--lend themselves to small and low-powered applications. The heart of the network is a chip with three microprocessors and proprietary network software contained in Read Only Memory. In addition to all nonuser levels of protocol, the software also contains message authentication capabilities. This chip can be interfaced to a variety of transmission media, for example, RS-485 lines, fiber topic cables, rf waves, and standard ac power lines. The use of power lines as the transmission medium in a facility could significantly reduce cabling costs

  5. A CMOS analog front-end chip for amperometric electrochemical sensors

    International Nuclear Information System (INIS)

    Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

    2015-01-01

    This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

  6. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  7. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  8. An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures

    Directory of Open Access Journals (Sweden)

    Maurizio Palesi

    2015-03-01

    Full Text Available Modern systems-on-chip (SoCs today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.

  9. Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

    CERN Document Server

    Macchiolo, A; Beimforde, M; Moser, H G; Nisius, R; Richter, R H

    2009-01-01

    We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.

  10. Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

    Science.gov (United States)

    Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

    2004-07-01

    A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

  11. Direct Liquid Evaporation Chemical Vapor Deposition(DLE-CVD) of Nickel, Manganese and Copper-Based Thin Films for Interconnects in Three-Dimensional Microelectronic Systems

    OpenAIRE

    Li, Kecheng

    2016-01-01

    Electrical interconnects are an intrinsic part of any electronic system. These interconnects have to perform reliably under a wide range of environmental conditions and survive stresses induced from thermal, mechanical, corrosive and electrical factors. Semiconductor technology is predominantly planar in nature, posing a severe limitation to the degree of device integrations into systems such as micro-processors or memories. 3D transistor FinFET (Fin type Field Effect Transistors) has been us...

  12. Integration of microelectronic chips in microfluidic systems on printed circuit board

    International Nuclear Information System (INIS)

    Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

    2012-01-01

    A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

  13. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  14. Gigabit chips: A case history of a transfer of federal technology

    Energy Technology Data Exchange (ETDEWEB)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs. (JDH)

  15. Gigabit chips: A case history of a transfer of federal technology

    International Nuclear Information System (INIS)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs

  16. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  17. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    OpenAIRE

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

  18. Novel electrochemical approach to study corrosion mechanism of Al-Au wire-bond pad interconnections

    DEFF Research Database (Denmark)

    Elisseeva, O. V.; Bruhn, A.; Cerezo, J.

    2013-01-01

    A gold-aluminium material combination is typically employed as an interconnection for microelectronic devices. One of the reliability risks of such devices is that of corrosion of aluminium bond pads resulting from the galvanic coupling between an aluminium bond pad and a gold wire. The research...... presented in this manuscript focuses on studying bond pad corrosion by selecting an appropriate model system and a dedicated set of electrochemical and analytical experimental tools. Taking into account the complex three-dimensional structure and the small dimensions of Au-Al interconnections (around 50......-100 μm), a dedicated and novel experimental approach was developed. Au-Al covered silicon chips were developed under clean room conditions. Three-dimensional electrodes were mimicked as flat, two-dimensional bond pad model systems, allowing the use of microelectrochemical local probe techniques. Thin...

  19. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  20. Development of a Ni-based superalloy with cellular structure and interconnected micro porosity

    International Nuclear Information System (INIS)

    Bernabe, A.; Lopez, E.; Gil-Sevillano, J.

    1998-01-01

    A cellular metallic material with interconnected porosity of controlled size of an order of 10 μm has been developed by electrochemical dissolution of tungsten grains in a W-Ni-Fe heavy alloy. The nickel superalloy with sponge structure and high surface/volume ratio can also be processed recycling chips from heavy metal machining (Patent number p9700191, 1997). Applications for the new materials could be found as support for catalysts, high temperature filters for corrosive fluids, burners, etc. (Author) 10 refs

  1. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  2. Optical trapping with Bessel beams generated from semiconductor lasers

    International Nuclear Information System (INIS)

    Sokolovskii, G S; Dudelev, V V; Losev, S N; Soboleva, K K; Deryagin, A G; Kuchinskii, V I; Sibbett, W; Rafailov, E U

    2014-01-01

    In this paper, we study generation of Bessel beams from semiconductor lasers with high beam propagation parameter M 2 and their utilization for optical trapping and manipulation of microscopic particles including living cells. The demonstrated optical tweezing with diodegenerated Bessel beams paves the way to replace their vibronic-generated counterparts for a range of applications towards novel lab-on-a-chip configurations

  3. Superconducting detectors for semiconductor quantum photonics

    International Nuclear Information System (INIS)

    Reithmaier, Guenther M.

    2015-01-01

    In this thesis we present the first successful on-chip detection of quantum light, thereby demonstrating the monolithic integration of superconducting single photon detectors with individually addressable semiconductor quantum dots in a prototypical quantum photonic circuit. Therefore, we optimized both the deposition of high quality superconducting NbN thin films on GaAs substrates and the fabrication of superconducting detectors and successfully integrated these novel devices with GaAs/AlGaAs ridge waveguides loaded with self-assembled InGaAs quantum dots.

  4. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  5. High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

    Science.gov (United States)

    Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

    2011-03-01

    The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

  6. Laser Soldering and Thermal Cycling Tests of Monolithic Silicon Pixel Chips

    CERN Document Server

    Strand, Frode Sneve

    2015-01-01

    An ALPIDE-1 monolithic silicon pixel sensor prototype has been laser soldered to a flex printed circuit using a novel interconnection technique using lasers. This technique is to be optimised to ensure stable, good quality connections between the sensor chips and the FPCs. To test the long-term stability of the connections, as well as study the effects on hit thresholds and noise in the sensor, it was thermally cycled in a climate chamber 1200 times. The soldered connections showed good qualities like even melting and good adhesion on pad/flex surfaces, and the chip remained in working condition for 1080 cycles. After this, a few connections failed, having cracks in the soldering tin, rendering the chip unusable. Threshold and noise characteristics seemed stable, except for the noise levels of sector 2 in the chip, for 1000 cycles in a temperature interval of "10^{\\circ}" and "50^{\\circ}" C. Still, further testing with wider temperature ranges and more cycles is needed to test the limitations of the chi...

  7. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-05-05

    ... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

  8. Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

    International Nuclear Information System (INIS)

    Chen Haijin; Lu Shengli; Shi Longxing

    2009-01-01

    A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

  9. An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, A.; Goossens, Kees

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  10. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, M.A.; Goossens, K.G.W.

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  11. Cancer and reproductive risks in the semiconductor industry.

    Science.gov (United States)

    LaDou, Joseph; Bailar, John C

    2007-01-01

    Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

  12. Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

    Science.gov (United States)

    Stinner, F. Scott

    As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

  13. Ceramic thermal wind sensor based on advanced direct chip attaching package

    International Nuclear Information System (INIS)

    Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

    2014-01-01

    An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

  14. Electron scattering at interfaces in nano-scale vertical interconnects: A combined experimental and ab initio study

    Science.gov (United States)

    Lanzillo, Nicholas A.; Restrepo, Oscar D.; Bhosale, Prasad S.; Cruz-Silva, Eduardo; Yang, Chih-Chao; Youp Kim, Byoung; Spooner, Terry; Standaert, Theodorus; Child, Craig; Bonilla, Griselda; Murali, Kota V. R. M.

    2018-04-01

    We present a combined theoretical and experimental study on the electron transport characteristics across several representative interface structures found in back-end-of-line interconnect stacks for advanced semiconductor manufacturing: Cu/Ta(N)/Co/Cu and Cu/Ta(N)/Ru/Cu. In particular, we evaluate the impact of replacing a thin TaN barrier with Ta while considering both Co and Ru as wetting layers. Both theory and experiment indicate a pronounced reduction in vertical resistance when replacing TaN with Ta, regardless of whether a Co or Ru wetting layer is used. This indicates that a significant portion of the total vertical resistance is determined by electron scattering at the Cu/Ta(N) interface. The electronic structure of these nano-sized interconnects is analyzed in terms of the atom-resolved projected density of states and k-resolved transmission spectra at the Fermi level. This work further develops a fundamental understanding of electron transport and material characteristics in nano-sized interconnects.

  15. Semiconductor Ion Implanters

    International Nuclear Information System (INIS)

    MacKinnon, Barry A.; Ruffell, John P.

    2011-01-01

    In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion! Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intel product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.

  16. Interconnection Guidelines

    Science.gov (United States)

    The Interconnection Guidelines provide general guidance on the steps involved with connecting biogas recovery systems to the utility electrical power grid. Interconnection best practices including time and cost estimates are discussed.

  17. Blasting detonators incorporating semiconductor bridge technology

    Energy Technology Data Exchange (ETDEWEB)

    Bickes, R.W. Jr.

    1994-05-01

    The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

  18. Sensor development at the semiconductor laboratory of the Max-Planck-Society

    Science.gov (United States)

    Bähr, A.; Lechner, P.; Ninkovic, J.

    2017-12-01

    For more than twenty years the semiconductor laboratory of the Max-Planck Society (MPG-HLL) is developing high-performing, specialised, scientific silicon sensors including the integration of amplifying electronics on the sensor chip. This paper summarises the actual status of these devices like pnCCDs and DePFET Active Pixel Sensors and their applications.

  19. Transurban interconnectivities

    DEFF Research Database (Denmark)

    Jørgensen, Claus Møller

    2012-01-01

    This essay discusses the interpretation of the revolutionary situations of 1848 in light of recent debates on interconnectivity in history. The concept of transurban interconnectivities is proposed as the most precise concept to capture the nature of interconnectivity in 1848. It is argued....... It is argued that circulating political communication accounts for similarities with respect to political agenda, organisational form and political repertoire evident in urban settings across Europe. This argument is supported by a series of examples of local organisation and local appropriations of liberalism...

  20. Optimization of Reliability and Power Consumption in Systems on a Chip

    OpenAIRE

    Simunic, Tajana; Mihic, Kresimir; De Micheli, Giovanni

    2005-01-01

    Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature, have made reliability assessment a much more significant issue in design. Although reliability of devices and interconnect has been broadly studied, here we characterize reliability at the system level. Thus we consider component-based System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and...

  1. Electronics Industry Study Report: Semiconductors and Defense Electronics

    Science.gov (United States)

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  2. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  3. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  4. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

  5. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  6. Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

    Science.gov (United States)

    Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

    2018-02-01

    The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

  7. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    NARCIS (Netherlands)

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be

  8. Optical interconnects

    CERN Document Server

    Chen, Ray T

    2006-01-01

    This book describes fully embedded board level optical interconnect in detail including the fabrication of the thin-film VCSEL array, its characterization, thermal management, the fabrication of optical interconnection layer, and the integration of devices on a flexible waveguide film. All the optical components are buried within electrical PCB layers in a fully embedded board level optical interconnect. Therefore, we can save foot prints on the top real estate of the PCB and relieve packaging difficulty reduced by separating fabrication processes. To realize fully embedded board level optical

  9. Thermo-mechanical properties and integrity of metallic interconnects in microelectronics

    Science.gov (United States)

    Ege, Efe Sinan

    In this dissertation, combined numerical (Finite Element Method) and experimental efforts were undertaken to study thermo-mechanical behavior in microelectronic devices. Interconnects, including chip-level metallization and package-level solder joints, are used to join many of the circuit parts in modern equipment. The dissertation is structured into six independent studies after the introductory chapter. The first two studies focus on thermo-mechanical fatigue of solder joints. Thermo-mechanical fatigue, in the form of damage along a microstructurally coarsened region in tin-lead solder, is analyzed along with the effects of intermetallic morphology. Also, lap-shear testing is modeled to characterize the joint and to investigate the validity of experimental data from different solder and substrate geometries. In the third study, the effects of pre-machined holes on strain localization and overall ductility in bulk eutectic tin-lead alloy is examined. Finite element analyses, taking into account the viscoplastic response, were carried out to provide a mechanistic rationale to corroborate the experimental findings. The fourth study concerns chip-level copper interconnects. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without the thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. This study is followed by a chapter on atomistics of interface-mediated plasticity in thin metallic films. The objective is to gain fundamental insight into the underlying mechanisms affecting the mechanical response of nanoscale thin films. The final study investigates the effect of microstructural heterogeneity on indentation response, for the purpose of raising awareness of the uncertainties involved in applying indentation techniques in probing mechanical properties of miniaturized devices.

  10. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    Energy Technology Data Exchange (ETDEWEB)

    Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

    2005-02-11

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

  11. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    International Nuclear Information System (INIS)

    Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

    2005-01-01

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

  12. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P, E-mail: Michael.Beimforde@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805, Muenchen (Germany)

    2010-12-15

    The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 {mu}m and 150 {mu}m has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10{sup 16}n{sub eq}cm{sup -2} have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

  13. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    International Nuclear Information System (INIS)

    Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P

    2010-01-01

    The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10 16 n eq cm -2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

  14. Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

    Directory of Open Access Journals (Sweden)

    Cheng Chuantong

    2017-07-01

    Full Text Available Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

  15. Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

    Science.gov (United States)

    Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

    2017-07-01

    Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

  16. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  17. Results on 3D interconnection from AIDA WP3

    Energy Technology Data Exchange (ETDEWEB)

    Moser, Hans-Günther, E-mail: hgm@hll.mpg.de

    2016-09-21

    From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

  18. Photovoltaic sub-cell interconnects

    Energy Technology Data Exchange (ETDEWEB)

    van Hest, Marinus Franciscus Antonius Maria; Swinger Platt, Heather Anne

    2017-05-09

    Photovoltaic sub-cell interconnect systems and methods are provided. In one embodiment, a photovoltaic device comprises a thin film stack of layers deposited upon a substrate, wherein the thin film stack layers are subdivided into a plurality of sub-cells interconnected in series by a plurality of electrical interconnection structures; and wherein the plurality of electrical interconnection structures each comprise no more than two scribes that penetrate into the thin film stack layers.

  19. A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

    Science.gov (United States)

    Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

    2017-12-01

    One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  20. A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

    Science.gov (United States)

    Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

    2017-12-01

    One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  1. Hybridization of active and passive elements for planar photonic components and interconnects

    Science.gov (United States)

    Pearson, M.; Bidnyk, S.; Balakrishnan, A.

    2007-02-01

    The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

  2. Interconnection blocks with minimal dead volumes permitting planar interconnection to thin microfluidic devices

    DEFF Research Database (Denmark)

    Sabourin, David; Snakenborg, Detlef; Dufva, Martin

    2010-01-01

    We have previously described 'Interconnection Blocks' which are re-usable, non-integrated PDMS blocks which allowing multiple, aligned and planar microfluidic interconnections. Here, we describe Interconnection Block versions with zero dead volumes that allow fluidic interfacing to flat or thin s...

  3. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2011-03-17

    ... existence of a domestic industry. The Commission's notice of investigation named several respondents...; Freescale Semiconductor Malaysia Sdn. Bhd. of Malaysia; Freescale Semiconductor Pte. Ltd. of Singapore; Mouser Electronics, Inc. of Mansfield, Texas; and Motorola Inc. of Schaumburg, Illinois. On August 16...

  4. An AES chip with DPA resistance using hardware-based random order execution

    International Nuclear Information System (INIS)

    Yu Bo; Li Xiangyu; Chen Cong; Sun Yihe; Wu Liji; Zhang Xiangmin

    2012-01-01

    This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm 2 . A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance. (semiconductor integrated circuits)

  5. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    International Nuclear Information System (INIS)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

  6. Resistance transition assisted geometry enhanced magnetoresistance in semiconductors

    International Nuclear Information System (INIS)

    Luo, Zhaochu; Zhang, Xiaozhong

    2015-01-01

    Magnetoresistance (MR) reported in some non-magnetic semiconductors (particularly silicon) has triggered considerable interest owing to the large magnitude of the effect. Here, we showed that MR in lightly doped n-Si can be significantly enhanced by introducing two diodes and proper design of the carrier path [Wan, Nature 477, 304 (2011)]. We designed a geometrical enhanced magnetoresistance (GEMR) device whose room-temperature MR ratio reaching 30% at 0.065 T and 20 000% at 1.2 T, respectively, approaching the performance of commercial MR devices. The mechanism of this GEMR is: the diodes help to define a high resistive state (HRS) and a low resistive state (LRS) in device by their openness and closeness, respectively. The ratio of apparent resistance between HRS and LRS is determined by geometry of silicon wafer and electrodes. Magnetic field could induce a transition from LRS to HRS by reshaping potential and current distribution among silicon wafer, resulting in a giant enhancement of intrinsic MR. We expect that this GEMR could be also realized in other semiconductors. The combination of high sensitivity to low magnetic fields and large high-field response should make this device concept attractive to the magnetic field sensing industry. Moreover, because this MR device is based on a conventional silicon/semiconductor platform, it should be possible to integrate this MR device with existing silicon/semiconductor devices and so aid the development of silicon/semiconductor-based magnetoelectronics. Also combining MR devices and semiconducting devices in a single Si/semiconductor chip may lead to some novel devices with hybrid function, such as electric-magnetic-photonic properties. Our work demonstrates that the charge property of semiconductor can be used in the magnetic sensing industry, where the spin properties of magnetic materials play a role traditionally

  7. Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

    Energy Technology Data Exchange (ETDEWEB)

    Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-12-01

    Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

  8. Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

    Science.gov (United States)

    Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

    2015-01-12

    Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

  9. Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

    Science.gov (United States)

    Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

    2016-01-21

    Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

  10. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    International Nuclear Information System (INIS)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua

    2010-01-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 μm 2 . Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  11. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  12. Bacteria inside semiconductors as potential sensor elements: biochip progress.

    Science.gov (United States)

    Sah, Vasu R; Baier, Robert E

    2014-06-24

    It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

  13. Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

    Science.gov (United States)

    Decrossas, Emmanuel; Glover, Michael D.; Porter, Kaoru; Cannon, Tom; Mantooth, H. Alan; Hamilton, M. C.

    2013-01-01

    Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

  14. Interconnection policy: a theoretical survey

    Directory of Open Access Journals (Sweden)

    César Mattos

    2003-01-01

    Full Text Available This article surveys the theoretical foundations of interconnection policy. The requirement of an interconnection policy should not be taken for granted in all circumstances, even considering the issue of network externalities. On the other hand, when it is required, an encompassing interconnection policy is usually justified. We provide an overview of the theory on interconnection pricing that results in several different prescriptions depending on which problem the regulator aims to address. We also present a survey on the literature on two-way interconnection.

  15. Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

    Science.gov (United States)

    Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

    2017-10-01

    In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

  16. Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

    Science.gov (United States)

    Wysocki, Gerard (Inventor); Tittel, Frank K. (Inventor); Curl, Robert F. (Inventor)

    2010-01-01

    A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

  17. Dynamic spin polarization by orientation-dependent separation in a ferromagnet-semiconductor hybrid

    Science.gov (United States)

    Korenev, V. L.; Akimov, I. A.; Zaitsev, S. V.; Sapega, V. F.; Langer, L.; Yakovlev, D. R.; Danilov, Yu. A.; Bayer, M.

    2012-07-01

    Integration of magnetism into semiconductor electronics would facilitate an all-in-one-chip computer. Ferromagnet/bulk semiconductor hybrids have been, so far, mainly considered as key devices to read out the ferromagnetism by means of spin injection. Here we demonstrate that a Mn-based ferromagnetic layer acts as an orientation-dependent separator for carrier spins confined in a semiconductor quantum well that is set apart from the ferromagnet by a barrier only a few nanometers thick. By this spin-separation effect, a non-equilibrium electron-spin polarization is accumulated in the quantum well due to spin-dependent electron transfer to the ferromagnet. The significant advance of this hybrid design is that the excellent optical properties of the quantum well are maintained. This opens up the possibility of optical readout of the ferromagnet's magnetization and control of the non-equilibrium spin polarization in non-magnetic quantum wells.

  18. On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

    Science.gov (United States)

    Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

    2017-08-30

    Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

  19. K-band single-chip electron spin resonance detector.

    Science.gov (United States)

    Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

    2012-04-01

    We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

  20. Purcell effect in an organic-inorganic halide perovskite semiconductor microcavity system

    International Nuclear Information System (INIS)

    Wang, Jun; Wang, Yafeng; Hu, Tao; Wu, Lin; Shen, Xuechu; Chen, Zhanghai; Cao, Runan; Xu, Fei; Da, Peimei; Zheng, Gengfeng; Lu, Jian

    2016-01-01

    Organic-inorganic halide perovskite semiconductors with the attractive physics properties, including strong photoluminescence (PL), huge oscillator strengths, and low nonradiative recombination losses, are ideal candidates for studying the light-matter interaction in nanostructures. Here, we demonstrate the coupling of the exciton state and the cavity mode in the lead halide perovskite microcavity system at room temperature. The Purcell effect in the coupling system is clearly observed by using angle-resolved photoluminescence spectra. Kinetic analysis based on time-resolved PL reveals that the spontaneous emission rate of the halide perovskite semiconductor is significantly enhanced at resonance of the exciton energy and the cavity mode. Our results provide the way for developing electrically driven organic polariton lasers, optical devices, and on-chip coherent quantum light sources

  1. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Energy Technology Data Exchange (ETDEWEB)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua, E-mail: gaoleisheng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-08-15

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 {mu}m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 {mu}m{sup 2}. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  2. Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

    Science.gov (United States)

    Biyikli, Necmi; Haider, Ali

    2017-09-01

    In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

  3. Semiconductor Laser Diode Pumps for Inertial Fusion Energy Lasers

    International Nuclear Information System (INIS)

    Deri, R.J.

    2011-01-01

    Solid-state lasers have been demonstrated as attractive drivers for inertial confinement fusion on the National Ignition Facility (NIF) at Lawrence Livermore National Laboratory (LLNL) and at the Omega Facility at the Laboratory for Laser Energetics (LLE) in Rochester, NY. For power plant applications, these lasers must be pumped by semiconductor diode lasers to achieve the required laser system efficiency, repetition rate, and lifetime. Inertial fusion energy (IFE) power plants will require approximately 40-to-80 GW of peak pump power, and must operate efficiently and with high system availability for decades. These considerations lead to requirements on the efficiency, price, and production capacity of the semiconductor pump sources. This document provides a brief summary of these requirements, and how they can be met by a natural evolution of the current semiconductor laser industry. The detailed technical requirements described in this document flow down from a laser ampl9ifier design described elsewhere. In brief, laser amplifiers comprising multiple Nd:glass gain slabs are face-pumped by two planar diode arrays, each delivering 30 to 40 MW of peak power at 872 nm during a ∼ 200 (micro)s quasi-CW (QCW) pulse with a repetition rate in the range of 10 to 20 Hz. The baseline design of the diode array employs a 2D mosaic of submodules to facilitate manufacturing. As a baseline, they envision that each submodule is an array of vertically stacked, 1 cm wide, edge-emitting diode bars, an industry standard form factor. These stacks are mounted on a common backplane providing cooling and current drive. Stacks are conductively cooled to the backplane, to minimize both diode package cost and the number of fluid interconnects for improved reliability. While the baseline assessment in this document is based on edge-emitting devices, the amplifier design does not preclude future use of surface emitting diodes, which may offer appreciable future cost reductions and

  4. Interconnected networks

    CERN Document Server

    2016-01-01

    This volume provides an introduction to and overview of the emerging field of interconnected networks which include multi layer or multiplex networks, as well as networks of networks. Such networks present structural and dynamical features quite different from those observed in isolated networks. The presence of links between different networks or layers of a network typically alters the way such interconnected networks behave – understanding the role of interconnecting links is therefore a crucial step towards a more accurate description of real-world systems. While examples of such dissimilar properties are becoming more abundant – for example regarding diffusion, robustness and competition – the root of such differences remains to be elucidated. Each chapter in this topical collection is self-contained and can be read on its own, thus making it also suitable as reference for experienced researchers wishing to focus on a particular topic.

  5. A Monolithic Interconnected module with a tunnel Junction for Enhanced Electrical and Optical Performance

    Energy Technology Data Exchange (ETDEWEB)

    Murray, Christopher Sean; Wilt, David Morgan

    1999-06-30

    An improved thermophotovoltaic (TPV) n/p/n device is provided. Monolithic Interconnected Modules (MIMs), semiconductor devices converting infrared radiation to electricity, have been developed with improved electrical and optical performance. The structure is an n-type emitter on a p-type base with an n-type lateral conduction layer. The incorporation of a tunnel junction and the reduction in the amount of p-type material used results in negligible parasitic absorption, decreased series resistance, increased voltage and increased active area. The novel use of a tunnel junction results in the potential for a TPV device with efficiency greater than 24%.

  6. Interconnection of Distributed Energy Resources

    Energy Technology Data Exchange (ETDEWEB)

    Reiter, Emerson [National Renewable Energy Lab. (NREL), Golden, CO (United States)

    2017-04-19

    This is a presentation on interconnection of distributed energy resources, including the relationships between different aspects of interconnection, best practices and lessons learned from different areas of the U.S., and an update on technical advances and standards for interconnection.

  7. Channel-Selectable Optical Link Based on a Silicon Microring for on-Chip Interconnection

    International Nuclear Information System (INIS)

    Qiu Chen; Hu Ting; Wang Wan-Jun; Yu Ping; Jiang Xiao-Qing; Yang Jian-Yi

    2012-01-01

    A channel-selectable optical link based on a silicon microring resonator is proposed and demonstrated. This optical link consists of the wavelength-tunable microring modulators and the filters, defined on a silicon-on-insulator (SOI) platform. With a p—i—n junction embedded in the microring modulator, light at the resonant wavelength of the ring resonator is modulated. The 2 nd -order microring add-drop filter routes the modulated light. The channel selectivity is demonstrated by heating the microrings. With a thermal tuning efficiency of 5.9 mW/nm, the filter drop port response was successfully tuned with 0.8 nm channel spacing. We also show that modulation can be achieved in these channels. This device aims to offer flexibility and increase the bandwidth usage efficiency in optical interconnection

  8. A microprocessor based on a two-dimensional semiconductor

    Science.gov (United States)

    Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

    2017-04-01

    The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

  9. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  10. Opportunities and challenges in the wider adoption of liver and interconnected microphysiological systems.

    Science.gov (United States)

    Hughes, David J; Kostrzewski, Tomasz; Sceats, Emma L

    2017-10-01

    Liver disease represents a growing global health burden. The development of in vitro liver models which allow the study of disease and the prediction of metabolism and drug-induced liver injury in humans remains a challenge. The maintenance of functional primary hepatocytes cultures, the parenchymal cell of the liver, has historically been difficult with dedifferentiation and the consequent loss of hepatic function limiting utility. The desire for longer term functional liver cultures sparked the development of numerous systems, including collagen sandwiches, spheroids, micropatterned co-cultures and liver microphysiological systems. This review will focus on liver microphysiological systems, often referred to as liver-on-a-chip, and broaden to include platforms with interconnected microphysiological systems or multi-organ-chips. The interconnection of microphysiological systems presents the opportunity to explore system level effects, investigate organ cross talk, and address questions which were previously the preserve of animal experimentation. As a field, microphysiological systems have reached a level of maturity suitable for commercialization and consequent evaluation by a wider community of users, in academia and the pharmaceutical industry. Here scientific, operational, and organizational considerations relevant to the wider adoption of microphysiological systems will be discussed. Applications in which microphysiological systems might offer unique scientific insights or enable studies currently feasible only with animal models are described, and challenges which might be addressed to enable wider adoption of the technologies are highlighted. A path forward which envisions the development of microphysiological systems in partnerships between academia, vendors and industry, is proposed. Impact statement Microphysiological systems are in vitro models of human tissues and organs. These systems have advanced rapidly in recent years and are now being

  11. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  12. Benefits of transmission interconnections

    International Nuclear Information System (INIS)

    Lyons, D.

    2006-01-01

    The benefits of new power transmission interconnections from Alberta were discussed with reference to the challenges and measures needed to move forward. Alberta's electricity system has had a long period of sustained growth in generation and demand and this trend is expected to continue. However, no new interconnections have been built since 1985 because the transmission network has not expanded in consequence with the growth in demand. As such, Alberta remains weakly interconnected with the rest of the western region. The benefits of stronger transmission interconnections include improved reliability, long-term generation capability, hydrothermal synergies, a more competitive market, system efficiencies and fuel diversity. It was noted that the more difficult challenges are not technical. Rather, the difficult challenges lie in finding an appropriate business model that recognizes different market structures. It was emphasized that additional interconnections are worthwhile and will require significant collaboration among market participants and governments. It was concluded that interties enable resource optimization between systems and their benefits far exceed their costs. tabs., figs

  13. Fluidic interconnections for microfluidic systems: A new integrated fluidic interconnection allowing plug 'n' play functionality

    DEFF Research Database (Denmark)

    Perozziello, Gerardo; Bundgaard, Frederik; Geschke, Oliver

    2008-01-01

    A crucial challenge in packaging of microsystems is microfluidic interconnections. These have to seal the ports of the system, and have to provide the appropriate interface to other devices or the external environment. Integrated fluidic interconnections appear to be a good solution for interconn...... external metal ferrules and the system. Theoretical calculations are made to dimension and model the integrated fluidic interconnection. Leakage tests are performed on the interconnections, in order to experimentally confirm the model, and detect its limits....

  14. In-memory interconnect protocol configuration registers

    Energy Technology Data Exchange (ETDEWEB)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  15. In-memory interconnect protocol configuration registers

    Science.gov (United States)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  16. Review on the dynamics of semiconductor nanowire lasers

    Science.gov (United States)

    Röder, Robert; Ronning, Carsten

    2018-03-01

    Semiconductor optoelectronic devices have contributed tremendously to the technological progress in the past 50-60 years. Today, they also play a key role in nanophotonics stimulated by the inherent limitations of electronic integrated circuits and the growing demand for faster communications on chip. In particular, the field of ‘nanowire photonics’ has emerged including the search for coherent light sources with a nano-scaled footprint. The past decade has been dedicated to find suitable semiconductor nanowire (NW) materials for such nanolasers. Nowadays, such NW lasers consistently work at room temperature covering a huge spectral range from the ultraviolet down to the mid-infrared depending on the band gap of the NW material. Furthermore, first approaches towards the modification and optimization of such NW laser devices have been demonstrated. The underlying dynamics of the electronic and photonic NW systems have also been studied very recently, as they need to be understood in order to push the technological relevance of nano-scaled coherent light sources. Therefore, this review will first present novel measurement approaches in order to study the ultrafast temporal and optical mode dynamics of individual NW laser devices. Furthermore, these fundamental new insights are reviewed and deeply discussed towards the efficient control and adjustment of the dynamics in semiconductor NW lasers.

  17. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  18. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  19. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Science.gov (United States)

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  20. Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Oh Young; Jung, Hoon Sun; Lee, Jung Hoon; Choa, Sung-Hoon [Seoul Nat’l Univ. of Science and Technology, Seoul (Korea, Republic of)

    2017-06-15

    In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

  1. Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

    Science.gov (United States)

    Yang, Lei; Gong, Jie; Ume, I. Charles

    2014-02-01

    In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be

  2. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  3. Semiconductor

    International Nuclear Information System (INIS)

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  4. Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3

    International Nuclear Information System (INIS)

    Loecker, M.

    2007-04-01

    Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 μm 2 pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e - ). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed

  5. Development of semiconductor electronics

    International Nuclear Information System (INIS)

    Bardeen, John.

    1977-01-01

    In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

  6. TSOM method for semiconductor metrology

    Science.gov (United States)

    Attota, Ravikiran; Dixson, Ronald G.; Kramar, John A.; Potzick, James E.; Vladár, András E.; Bunday, Benjamin; Novak, Erik; Rudack, Andrew

    2011-03-01

    Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes. Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis, inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with potentially significant savings and yield improvements in manufacturing.

  7. High-performance, scalable optical network-on-chip architectures

    Science.gov (United States)

    Tan, Xianfang

    The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of

  8. Four-port mode-selective silicon optical router for on-chip optical interconnect.

    Science.gov (United States)

    Jia, Hao; Zhou, Ting; Fu, Xin; Ding, Jianfeng; Zhang, Lei; Yang, Lin

    2018-04-16

    We propose and demonstrate a four-port mode-selective optical router on a silicon-on-insulator platform. The passive routing property ensures that the router consumes no power to establish the optical links. For each port, input signals with different modes are selectively routed to the target ports through the pre-designed architecture. In general, the device intrinsically supports broadcasting of multiplexed signals from one port to the other three ports through mode division multiplexing. In some applications, the input signal from one port would only be sent to another port as in reconfigurable optical routers. The prototype is constructed by mode multiplexers/de-multiplexers and single-mode interconnect waveguides between them. The insertion losses for all optical links are lower than 8.0 dB, and the largest optical crosstalk values are lower than -18.7 dB and -22.0 dB for the broadcasting and port-to-port routing modes, respectively, at the wavelength range of 1525-1565 nm. In order to verify the routing functionality, a 40-Gbps bidirectional data transmission experiment is performed. The device offers a promising building block for passive routing by utilizing the dimension of the modes.

  9. Policy issues in interconnecting networks

    Science.gov (United States)

    Leiner, Barry M.

    1989-01-01

    To support the activities of the Federal Research Coordinating Committee (FRICC) in creating an interconnected set of networks to serve the research community, two workshops were held to address the technical support of policy issues that arise when interconnecting such networks. The workshops addressed the required and feasible technologies and architectures that could be used to satisfy the desired policies for interconnection. The results of the workshop are documented.

  10. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    OpenAIRE

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. P...

  11. Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

    Directory of Open Access Journals (Sweden)

    Vasu R. Sah

    2014-06-01

    Full Text Available It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities’ features at the time of first production of these potential biochips.

  12. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  13. Optically pumped semiconductor lasers for atomic and molecular physics

    Science.gov (United States)

    Burd, S.; Leibfried, D.; Wilson, A. C.; Wineland, D. J.

    2015-03-01

    Experiments in atomic, molecular and optical (AMO) physics rely on lasers at many different wavelengths and with varying requirements on spectral linewidth, power and intensity stability. Optically pumped semiconductor lasers (OPSLs), when combined with nonlinear frequency conversion, can potentially replace many of the laser systems currently in use. We are developing a source for laser cooling and spectroscopy of Mg+ ions at 280 nm, based on a frequency quadrupled OPSL with the gain chip fabricated at the ORC at Tampere Univ. of Technology, Finland. This OPSL system could serve as a prototype for many other sources used in atomic and molecular physics.

  14. 18 CFR 292.306 - Interconnection costs.

    Science.gov (United States)

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any electric...

  15. Opening of K+ channels by capacitive stimulation from silicon chip

    Science.gov (United States)

    Ulbrich, M. H.; Fromherz, P.

    2005-10-01

    The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

  16. Decentralised output feedback control of Markovian jump interconnected systems with unknown interconnections

    Science.gov (United States)

    Li, Li-Wei; Yang, Guang-Hong

    2017-07-01

    The problem of decentralised output feedback control is addressed for Markovian jump interconnected systems with unknown interconnections and general transition rates (TRs) allowed to be unknown or known with uncertainties. A class of decentralised dynamic output feedback controllers are constructed, and a cyclic-small-gain condition is exploited to dispose the unknown interconnections so that the resultant closed-loop system is stochastically stable and satisfies an H∞ performance. With slack matrices to cope with the nonlinearities incurred by unknown and uncertain TRs in control synthesis, a novel controller design condition is developed in linear matrix inequality formalism. Compared with the existing works, the proposed approach leads to less conservatism. Finally, two examples are used to illustrate the effectiveness of the new results.

  17. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    International Nuclear Information System (INIS)

    Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

    1993-01-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

  18. Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

    Science.gov (United States)

    Chang, Yin-Jung

    With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the

  19. Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC)

    International Nuclear Information System (INIS)

    Celik, Cihangir; Unlue, Kenan; Narayanan, Vijaykrishnan; Irwin, Mary J.

    2011-01-01

    Soft errors are transient errors caused due to excess charge carriers induced primarily by external radiations in the semiconductor devices. Soft error phenomena could be used to detect thermal neutrons with a neutron monitoring/detection system by enhancing soft error occurrences in the memory devices. This way, one can convert all semiconductor memory devices into neutron detection systems. Such a device is being developed at The Pennsylvania State University and named Neutron Intercepting Silicon Chip (NISC). The NISC is envisioning a miniature, power efficient, and active/passive operation neutron sensor/detector system. NISC aims to achieve this goal by introducing 10 B-enriched Borophosphosilicate Glass (BPSG) insulation layers in the semiconductor memories. In order to model and analyze the NISC, an analysis tool using Geant4 as the transport and tracking engine is developed for the simulation of the charged particle interactions in the semiconductor memory model, named NISC Soft Error Analysis Tool (NISCSAT). A simple model with 10 B-enriched layer on top of the lumped silicon region is developed in order to represent the semiconductor memory node. Soft error probability calculations were performed via the NISCSAT with both single node and array configurations to investigate device scaling by using different node dimensions in the model. Mono-energetic, mono-directional thermal and fast neutrons are used as the neutron sources. Soft error contribution due to the BPSG layer is also investigated with different 10 B contents and the results are presented in this paper.

  20. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  1. Fuel cell system with interconnect

    Science.gov (United States)

    Goettler, Richard; Liu, Zhien

    2017-12-12

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  2. Deposition and characterisation of copper for high density interconnects

    International Nuclear Information System (INIS)

    McCusker, N.

    1999-09-01

    Copper has been deposited by sputtering and investigated for application as high density interconnects, with a view to maximising its performance and reliability. A sputter deposition process using gettering has been developed, which produces consistently pure, low resistivity films. A relationship between film thickness and resistivity has been explained by studying the grain growth process in copper films using atomic force microscopy. The Maydas-Shatzkes model has been used to separate the contributions of grain boundary and surface scattering to thin film resistivity, in copper and gold. Stress and texture in copper film have been studied. Annealing has been used to promote grain growth and texture development. Electromigration has been studied in copper and aluminium interconnects using a multi-line accelerated test set-up. A difference in failure distributions and void morphologies has been explained by an entirely different damage mechanism. The importance of surface/interface migration in electromigration damage of copper lines has been established and explained using a grain boundary-grooving model. A tantalum overlayer was found to extend the lifetime of copper lines. A composite sputtering target has been used to deposit copper/zirconium alloy films. The composition of the alloys was studied by Rutherford backscattering, Auger and secondary neutral mass spectrometry. The alloy films had an improved electromigration lifetime. A surface controlled mechanism is proposed to explain the advantage. A metal oxide semiconductor (MOS) capacitor technique is used to investigate barrier reliability. Tungsten is shown to be an effective diffusion barrier for copper, up to 700 deg. C. (author)

  3. A CMOS G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor network application

    Energy Technology Data Exchange (ETDEWEB)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing, E-mail: zhiqunli@seu.edu.cn [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2011-05-15

    A G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 {mu}m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  4. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    DEFF Research Database (Denmark)

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... and display ultrasensitive mass detection in air. A mass sensitivity of 4 ag/Hz has been determined in air by placing a single glycerine drop, having a measured weight of 57 fg, at the apex of a cantilever and subsequently measuring a frequency shift of 14.8 kHz. CMOS integration enables electrostatic...

  5. Method and apparatus for positioning a beam of charged particles

    International Nuclear Information System (INIS)

    Michail, M.S.; Woodard, O.C.; Yourke, H.S.

    1975-01-01

    A beam of charged particles is stepped from one predetermined position to another to form a desired pattern on a semiconductor wafer. There is a dynamic correction for the deviation of the actual position of the beam from its predetermined position, so that the beam is applied to the deviated position rather than the predetermined position. Through the location of four registration marks, the writing field is precisely defined. Writing fields may be interconnected by the sharing of registration marks, enabling the construction of chips which are larger than a single writing field. (auth)

  6. Universal Interconnection Technology Workshop Proceedings

    Energy Technology Data Exchange (ETDEWEB)

    Sheaffer, P.; Lemar, P.; Honton, E. J.; Kime, E.; Friedman, N. R.; Kroposki, B.; Galdo, J.

    2002-10-01

    The Universal Interconnection Technology (UIT) Workshop - sponsored by the U.S. Department of Energy, Distributed Energy and Electric Reliability (DEER) Program, and Distribution and Interconnection R&D - was held July 25-26, 2002, in Chicago, Ill., to: (1) Examine the need for a modular universal interconnection technology; (2) Identify UIT functional and technical requirements; (3) Assess the feasibility of and potential roadblocks to UIT; (4) Create an action plan for UIT development. These proceedings begin with an overview of the workshop. The body of the proceedings provides a series of industry representative-prepared papers on UIT functions and features, present interconnection technology, approaches to modularization and expandability, and technical issues in UIT development as well as detailed summaries of group discussions. Presentations, a list of participants, a copy of the agenda, and contact information are provided in the appendices of this document.

  7. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  8. Silicon based cryogenic platform for the integration of qubit and classical control chips

    Science.gov (United States)

    Leonhardt, T.; Hollmann, A.; Jirovec, D.; Neumann, R.; Klemt, B.; Kindel, S.; Kucharski, M.; Fischer, G.; Bougeard, D.; Bluhm, H.; Schreiber, L. R.

    Electrostatically confined electron-spin-qubits proved viable for quantum information processing. Yet their up-scaling not only demands improvement of physical qubits, but also the development and cryogenic integration of classical control hardware. Therefore, we created a platform to integrate quantum chips and classical electronics. These multilayer interposer chips incorporate passive circuit elements, high bandwidth coplanar wave guides and interconnects for electron spin resonant qubit control as well as low impedance DC microstrips reducing EM-crosstalk from AC to DC lines. We used the interposer for measurements of a Si/SiGe quantum dot at 30 mK. We also characterized a commercial voltage controlled oszillator (VCO) based on hetero-bipolar transistors. Tunable about 30 GHz it is ideal for electron spin resonant qubit control. Cooled from 300 to 4 K it exhibits a slightly increased output power and frequency, while the phase noise level is constant. The device remains functional up to magnetic fields of 6 T.

  9. Robust design and thermal fatigue life prediction of anisotropic conductive film flip chip package

    International Nuclear Information System (INIS)

    Nam, Hyun Wook

    2004-01-01

    The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF(Anisotropic Conductive Film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue life of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear bi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design Of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2 nd DOE was conducted to obtain RSM equation for the choose 3 design parameter. The coefficient of determination (R 2 ) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for Feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430μm, and 78μm, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter

  10. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  11. Epidemics spreading in interconnected complex networks

    International Nuclear Information System (INIS)

    Wang, Y.; Xiao, G.

    2012-01-01

    We study epidemic spreading in two interconnected complex networks. It is found that in our model the epidemic threshold of the interconnected network is always lower than that in any of the two component networks. Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. Theoretical analysis and simulation results show that, generally speaking, the epidemic size is not significantly affected by the inter-network correlation. In interdependent networks which can be viewed as a special case of interconnected networks, however, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant. -- Highlights: ► We study epidemic spreading in two interconnected complex networks. ► The epidemic threshold is lower than that in any of the two networks. And Interconnection correlation has impacts on threshold and average outbreak size. ► Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. ► We demonstrated and proved that Interconnection correlation does not affect epidemic size significantly. ► In interdependent networks, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant.

  12. Epidemics spreading in interconnected complex networks

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Y. [School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (Singapore); Institute of High Performance Computing, Agency for Science, Technology and Research (A-STAR), Singapore 138632 (Singapore); Xiao, G., E-mail: egxxiao@ntu.edu.sg [School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (Singapore)

    2012-09-03

    We study epidemic spreading in two interconnected complex networks. It is found that in our model the epidemic threshold of the interconnected network is always lower than that in any of the two component networks. Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. Theoretical analysis and simulation results show that, generally speaking, the epidemic size is not significantly affected by the inter-network correlation. In interdependent networks which can be viewed as a special case of interconnected networks, however, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant. -- Highlights: ► We study epidemic spreading in two interconnected complex networks. ► The epidemic threshold is lower than that in any of the two networks. And Interconnection correlation has impacts on threshold and average outbreak size. ► Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. ► We demonstrated and proved that Interconnection correlation does not affect epidemic size significantly. ► In interdependent networks, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant.

  13. Semiconductor devices for entangled photon pair generation: a review

    Science.gov (United States)

    Orieux, Adeline; Versteegh, Marijn A. M.; Jöns, Klaus D.; Ducci, Sara

    2017-07-01

    Entanglement is one of the most fascinating properties of quantum mechanical systems; when two particles are entangled the measurement of the properties of one of the two allows the properties of the other to be instantaneously known, whatever the distance separating them. In parallel with fundamental research on the foundations of quantum mechanics performed on complex experimental set-ups, we assist today with bourgeoning of quantum information technologies bound to exploit entanglement for a large variety of applications such as secure communications, metrology and computation. Among the different physical systems under investigation, those involving photonic components are likely to play a central role and in this context semiconductor materials exhibit a huge potential in terms of integration of several quantum components in miniature chips. In this article we review the recent progress in the development of semiconductor devices emitting entangled photons. We will present the physical processes allowing the generation of entanglement and the tools to characterize it; we will give an overview of major recent results of the last few years and highlight perspectives for future developments.

  14. Semiconductor micro cavities: half light, half matter

    International Nuclear Information System (INIS)

    Baumberg, Jeremy J.

    2003-01-01

    World, Jeremy J Baumberg of the University of Southampton, UK, explains how semiconductor micro cavities could one day even be used as a new type of ultra-efficient light emitter for optoelectronic interconnects or quantum processors. (U.K.)

  15. Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

    International Nuclear Information System (INIS)

    Mishra, Vijay; Kataria, S.K.

    2005-01-01

    A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

  16. An analog VLSI chip emulating polarization vision of Octopus retina.

    Science.gov (United States)

    Momeni, Massoud; Titus, Albert H

    2006-01-01

    Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

  17. Comprehensive evaluation of global energy interconnection development index

    Science.gov (United States)

    Liu, Lin; Zhang, Yi

    2018-04-01

    Under the background of building global energy interconnection and realizing green and low-carbon development, this article constructed the global energy interconnection development index system which based on the current situation of global energy interconnection development. Through using the entropy method for the weight analysis of global energy interconnection development index, and then using gray correlation method to analyze the selected countries, this article got the global energy interconnection development index ranking and level classification.

  18. Evaluation of hybrid polymers for high-precision manufacturing of 3D optical interconnects by two-photon absorption lithography

    Science.gov (United States)

    Schleunitz, A.; Klein, J. J.; Krupp, A.; Stender, B.; Houbertz, R.; Gruetzner, G.

    2017-02-01

    The fabrication of optical interconnects has been widely investigated for the generation of optical circuit boards. Twophoton absorption (TPA) lithography (or high-precision 3D printing) as an innovative production method for direct manufacture of individual 3D photonic structures gains more and more attention when optical polymers are employed. In this regard, we have evaluated novel ORMOCER-based hybrid polymers tailored for the manufacture of optical waveguides by means of high-precision 3D printing. In order to facilitate future industrial implementation, the processability was evaluated and the optical performance of embedded waveguides was assessed. The results illustrate that hybrid polymers are not only viable consumables for industrial manufacture of polymeric micro-optics using generic processes such as UV molding. They also are potential candidates to fabricate optical waveguide systems down to the chip level where TPA-based emerging manufacturing techniques are engaged. Hence, it is shown that hybrid polymers continue to meet the increasing expectations of dynamically growing markets of micro-optics and optical interconnects due to the flexibility of the employed polymer material concept.

  19. Introduction to Open Core Protocol Fastpath to System-on-Chip Design

    CERN Document Server

    Schwaderer, W David

    2012-01-01

    This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

  20. Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

    Science.gov (United States)

    Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

    1997-01-01

    The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

  1. Interconnect fatigue design for terrestrial photovoltaic modules

    Science.gov (United States)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1982-03-01

    The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field.

  2. Organs-on-a-chip: Current applications and consideration points for in vitro ADME-Tox studies.

    Science.gov (United States)

    Ishida, Seiichi

    2018-02-01

    Assay systems using in vitro cultured cells are increasingly applied for evaluation of the efficacy, safety, and toxicity of drug candidates. In vitro cell-based assays have two main applications in the drug discovery process: searching for a compound that is effective against the target disease (seed investigation) and confirmation of safety during use of the identified compounds (safety assessment). Currently available in vitro cell-based assays have been designed to evaluate the efficacy and toxicity in single organs, but the in vivo pharmacokinetics and pharmacodynamics of the administered drug candidates have not been considered. Thus, an evaluation system that interconnects cell culture units, one of which has appropriate drug metabolism activities and the other assesses the efficacy and toxicity of compounds, is needed. Accordingly, the in vitro ADME-Tox culture system known as organs-on-a-chip has been proposed. In this review, after introducing the organs-on-a-chip system, the evaluation of enterohepatic circulation and the gut-liver axis relationship will be presented as an example of the application of the organs-on-a-chip system for ADME studies based on inter-organ network. Additionally, the functions required for the organs-on-a-chip system and the necessity of standardization of cells mounted on the chip system will be discussed. Copyright © 2018 The Japanese Society for the Study of Xenobiotics. Published by Elsevier Ltd. All rights reserved.

  3. Fitting tissue chips and microphysiological systems into the grand scheme of medicine, biology, pharmacology, and toxicology.

    Science.gov (United States)

    Watson, David E; Hunziker, Rosemarie; Wikswo, John P

    2017-10-01

    Microphysiological systems (MPS), which include engineered organoids (EOs), single organ/tissue chips (TCs), and multiple organs interconnected to create miniature in vitro models of human physiological systems, are rapidly becoming effective tools for drug development and the mechanistic understanding of tissue physiology and pathophysiology. The second MPS thematic issue of Experimental Biology and Medicine comprises 15 articles by scientists and engineers from the National Institutes of Health, the IQ Consortium, the Food and Drug Administration, and Environmental Protection Agency, an MPS company, and academia. Topics include the progress, challenges, and future of organs-on-chips, dissemination of TCs into Pharma, children's health protection, liver zonation, liver chips and their coupling to interconnected systems, gastrointestinal MPS, maturation of immature cardiomyocytes in a heart-on-a-chip, coculture of multiple cell types in a human skin construct, use of synthetic hydrogels to create EOs that form neural tissue models, the blood-brain barrier-on-a-chip, MPS models of coupled female reproductive organs, coupling MPS devices to create a body-on-a-chip, and the use of a microformulator to recapitulate endocrine circadian rhythms. While MPS hardware has been relatively stable since the last MPS thematic issue, there have been significant advances in cell sourcing, with increased reliance on human-induced pluripotent stem cells, and in characterization of the genetic and functional cell state in MPS bioreactors. There is growing appreciation of the need to minimize perfusate-to-cell-volume ratios and respect physiological scaling of coupled TCs. Questions asked by drug developers are followed by an analysis of the potential value, costs, and needs of Pharma. Of highest value and lowest switching costs may be the development of MPS disease models to aid in the discovery of disease mechanisms; novel compounds including probes, leads, and clinical candidates

  4. Recent Development of SOFC Metallic Interconnect

    Energy Technology Data Exchange (ETDEWEB)

    Wu JW, Liu XB

    2010-04-01

    Interest in solid oxide fuel cells (SOFC) stems from their higher e±ciencies and lower levels of emitted pollu- tants, compared to traditional power production methods. Interconnects are a critical part in SOFC stacks, which connect cells in series electrically, and also separate air or oxygen at the cathode side from fuel at the anode side. Therefore, the requirements of interconnects are the most demanding, i:e:, to maintain high elec- trical conductivity, good stability in both reducing and oxidizing atmospheres, and close coe±cient of thermal expansion (CTE) match and good compatibility with other SOFC ceramic components. The paper reviewed the interconnect materials, and coatings for metallic interconnect materials.

  5. Misalignment corrections in optical interconnects

    Science.gov (United States)

    Song, Deqiang

    Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or

  6. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  7. Development and operation of interconnections in a restructuring context

    International Nuclear Information System (INIS)

    2003-01-01

    In many countries the electrical network is not fully interconnected and the best technical solution to achieve interconnection has to be found. At the same time the electricity industry is being restructured and interconnecting independent energy markets presents technical challenges. It is therefore timely to consider interconnection development and operation options: examine the benefits of interconnecting electrical networks and the development strategies, review the interconnection design options and the technologies available, identify the operational issues, the security problems of large interconnected systems, the protection issues, consider the impact of the restructuring of the electrical supply industry, assess the political, environmental and social implications of interconnections. reorganized in slovenia from 5-7 april 2004. (author)

  8. FEOL technology trend

    International Nuclear Information System (INIS)

    Taur, Y.; Ning, T.H.

    1998-01-01

    Trends in front-end-of-line technology are discussed. At the chip level, many of the important parameters are published in the National Technology Roadmap for Semiconductors in 1994. At the device and circuit level, both bipolar and CMOS are scalable. However, the large standby power of bipolar circuits severely limits the integration level of bipolar chips. The inherently low standby power of CMOS, on the contrary, allows the integration level of CMOS circuits to continue increasing with scaling. In reality, both the electric field and power density of CMOS devices have been gradually rising over the generations owing to non-scaling effects of thermal voltage and silicon bandgap. As power supply voltage reaches 1.5V and below, circuit performance can only be gained at the expense of higher active or standby power of the chip. Implications of device scaling on contact and silicide technology are addressed. Trends of local and global interconnect scaling are discussed. (orig.)

  9. How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

    International Nuclear Information System (INIS)

    Pfeiffer, K.F.G.

    2003-01-01

    Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

  10. Reconfigurable Optical Interconnections Via Dynamic Computer-Generated Holograms

    Science.gov (United States)

    Liu, Hua-Kuang (Inventor); Zhou, Shao-Min (Inventor)

    1996-01-01

    A system is presented for optically providing one-to-many irregular interconnections, and strength-adjustable many-to-many irregular interconnections which may be provided with strengths (weights) w(sub ij) using multiple laser beams which address multiple holograms and means for combining the beams modified by the holograms to form multiple interconnections, such as a cross-bar switching network. The optical means for interconnection is based on entering a series of complex computer-generated holograms on an electrically addressed spatial light modulator for real-time reconfigurations, thus providing flexibility for interconnection networks for large-scale practical use. By employing multiple sources and holograms, the number of interconnection patterns achieved is increased greatly.

  11. Microtexture of Strain in electroplated copper interconnects

    International Nuclear Information System (INIS)

    Spolenak, R.; Barr, D.L.; Gross, M.E.; Evans-Lutterodt, K.; Brown, W.L.; Tamura, N.; MacDowell, A.A.; Celestre, R.S.; Padmore, H.A.; Valek, B.C.; Bravman, J.C.; Flinn, P.; Marieb, T.; Keller, R.R.; Batterman, B.W.; Patel, J.R.

    2001-01-01

    The microstructure of narrow metal conductors in the electrical interconnections on IC chips has often been identified as of major importance in the reliability of these devices. The stresses and stress gradients that develop in the conductors as a result of thermal expansion differences in the materials and of electromigration at high current densities are believed to be strongly dependent on the details of the grain structure. The present work discusses new techniques based on microbeam x-ray diffraction (MBXRD) that have enabled measurement not only of the microstructure of totally encapsulated conductors but also of the local stresses in them on a micron and submicron scale. White x-rays from the Advanced Light Source were focused to a micron spot size by Kirkpatrick-Baez mirrors. The sample was stepped under the micro-beam and Laue images obtained at each sample location using a CCD area detector. Microstructure and local strain were deduced from these images. Cu lines with widths ranging from 0.8 mm to 5 mm and thickness of 1 mm were investigated. Comparisons are made between the capabilities of MBXRD and the well established techniques of broad beam XRD, electron back scatter diffraction (EBSD) and focused ion beam imagining (FIB)

  12. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  13. Holistic design in high-speed optical interconnects

    Science.gov (United States)

    Saeedi, Saman

    Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

  14. Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

    Science.gov (United States)

    Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

    2018-03-01

    In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

  15. Yarr: A PCIe based readout system for semiconductor tracking systems

    Energy Technology Data Exchange (ETDEWEB)

    Heim, Timon [Bergische Universitaet Wuppertal, Wuppertal (Germany); CERN, Geneva (Switzerland); Maettig, Peter [Bergische Universitaet Wuppertal, Wuppertal (Germany); Pernegger, Heinz [CERN, Geneva (Switzerland)

    2015-07-01

    The Yarr readout system is a novel DAQ concept, using an FPGA board connected via PCIe to a computer, to read out semiconductor tracking systems. The system uses the FPGA as a reconfigurable IO interface which, in conjunction with the very high speed of the PCIe bus, enables a focus of processing the data stream coming from the pixel detector in software. Modern computer system could potentially make the need of custom signal processing hardware in readout systems obsolete and the Yarr readout system showcases this for FE-I4 chips, which are state-of-the-art readout chips used in the ATLAS Pixel Insertable B-Layer and developed for tracking in high multiplicity environments. The underlying concept of the Yarr readout system tries to move intelligence from hardware into the software without the loss of performance, which is made possible by modern multi-core processors. The FPGA board firmware acts like a buffer and does no further processing of the data stream, enabling rapid integration of new hardware due to minimal firmware minimisation.

  16. 47 CFR 90.477 - Interconnected systems.

    Science.gov (United States)

    2010-10-01

    ... part and medical emergency systems in the 450-470 MHz band, interconnection will be permitted only... operating on frequencies in the bands below 800 MHz are not subject to the interconnection provisions of...

  17. Total Ionizing Dose Testing of the ABC130 ASIC for the ATLAS Phase-II Semiconductor Tracker Upgrade

    CERN Document Server

    Morningstar, Alan

    2015-01-01

    The Large Hadron Collider's (LHC) current inner detector was not built to withstand the radiation damage from the 3000 $\\text{fb}^{-1}$ of integrated luminosity that is planned for the high luminosity LHC (HL-LHC). Therefore, the ATLAS inner detector (ID) must be completely upgraded. As a part of this upgrade, the semiconductor tracker (SCT) and transition radiation tracker (TRT) will be replaced with new silicon microstrip sensors {[}1{]}. These silicon strips will be read out by the ABC130 chip and thus the ABC130 must be able to withstand an expected 30 Mrad of radiation over 10 years. The ABC130 chip was irradiated with 70 Mrad of x-ray radiation over the course of 2 days and the results are discussed in this report.

  18. Interconnecting heterogeneous database management systems

    Science.gov (United States)

    Gligor, V. D.; Luckenbaugh, G. L.

    1984-01-01

    It is pointed out that there is still a great need for the development of improved communication between remote, heterogeneous database management systems (DBMS). Problems regarding the effective communication between distributed DBMSs are primarily related to significant differences between local data managers, local data models and representations, and local transaction managers. A system of interconnected DBMSs which exhibit such differences is called a network of distributed, heterogeneous DBMSs. In order to achieve effective interconnection of remote, heterogeneous DBMSs, the users must have uniform, integrated access to the different DBMs. The present investigation is mainly concerned with an analysis of the existing approaches to interconnecting heterogeneous DBMSs, taking into account four experimental DBMS projects.

  19. Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

    Science.gov (United States)

    Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

    2014-09-01

    The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

  20. Semiconductor apparatus and method of fabrication for a semiconductor apparatus

    NARCIS (Netherlands)

    2010-01-01

    The invention relates to a semiconductor apparatus (1) and a method of fabrication for a semiconductor apparatus (1), wherein the semiconductor apparatus (1) comprises a semiconductor layer (2) and a passivation layer (3), arranged on a surface of the semiconductor layer (2), for passivating the

  1. Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

    Directory of Open Access Journals (Sweden)

    Mitsumasa Koyanagi

    2011-02-01

    Full Text Available New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D and hetero integration of complementary metal-oxide semiconductors (CMOS and microelectromechanical systems (MEMS. By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

  2. Ultra-High Capacity Silicon Photonic Interconnects through Spatial Multiplexing

    Science.gov (United States)

    Chen, Christine P.

    The market for higher data rate communication is driving the semiconductor industry to develop new techniques of writing at smaller scales, while continuing to scale bandwidth at low power consumption. Silicon photonic (SiPh) devices offer a potential solution to the electronic interconnect bandwidth bottleneck. SiPh leverages the technology commensurate of decades of fabrication development with the unique functionality of next-generation optical interconnects. Finer fabrication techniques have allowed for manufacturing physical characteristics of waveguide structures that can support multiple modes in a single waveguide. By refining modal characteristics in photonic waveguide structures, through mode multiplexing with the asymmetric y-junction and microring resonator, higher aggregate data bandwidth is demonstrated via various combinations of spatial multiplexing, broadening applications supported by the integrated platform. The main contributions of this dissertation are summarized as follows. Experimental demonstrations of new forms of spatial multiplexing combined together exhibit feasibility of data transmission through mode-division multiplexing (MDM), mode-division and wavelength-division multiplexing (MDM-WDM), and mode-division and polarization-division multiplexing (MDM-PDM) through a C-band, Si photonic platform. Error-free operation through mode multiplexers and demultiplexers show how data can be viably scaled on multiple modes and with existing spatial domains simultaneously. Furthermore, we explore expanding device channel support from two to three arms. Finding that a slight mismatch in the third arm can increase crosstalk contributions considerably, especially when increasing data rate, we explore a methodical way to design the asymmetric y-junction device by considering its angles and multiplexer/demultiplexer arm width. By taking into consideration device fabrication variations, we turn towards optimizing device performance post

  3. Manufacturing of planar ceramic interconnects

    Energy Technology Data Exchange (ETDEWEB)

    Armstrong, B.L.; Coffey, G.W.; Meinhardt, K.D.; Armstrong, T.R. [Pacific Northwest National Lab., Richland, WA (United States)

    1996-12-31

    The fabrication of ceramic interconnects for solid oxide fuel cells (SOFC) and separator plates for electrochemical separation devices has been a perennial challenge facing developers. Electrochemical vapor deposition (EVD), plasma spraying, pressing, tape casting and tape calendering are processes that are typically utilized to fabricate separator plates or interconnects for the various SOFC designs and electrochemical separation devices. For sake of brevity and the selection of a planar fuel cell or gas separation device design, pressing will be the only fabrication technique discussed here. This paper reports on the effect of the characteristics of two doped lanthanum manganite powders used in the initial studies as a planar porous separator for a fuel cell cathode and as a dense interconnect for an oxygen generator.

  4. Operation of the ATLAS Semiconductor Tracker: commissioning and performance results with cosmic ray data

    OpenAIRE

    González-Sevilla, S

    2009-01-01

    The Semiconductor Tracker (SCT) is one of the three sub-systems of the ATLAS internal tracker. Its complete installation and sign-off took about 18 months and was finished at the beginning of 2008. Since then, the SCT has been run successfully taking data in combined mode with the other ATLAS sub-systems. The major problems related with cooling failures and the mortality of off-detector opto-chips have been solved. As in summer 2009, more than 99% of the main detector components are fully wor...

  5. Optimal interconnection and renewable targets for north-west Europe

    International Nuclear Information System (INIS)

    Lynch, Muireann Á.; Tol, Richard S.J.; O'Malley, Mark J.

    2012-01-01

    We present a mixed-integer, linear programming model for determining optimal interconnection for a given level of renewable generation using a cost minimisation approach. Optimal interconnection and capacity investment decisions are determined under various targets for renewable penetration. The model is applied to a test system for eight regions in Northern Europe. It is found that considerations on the supply side dominate demand side considerations when determining optimal interconnection investment: interconnection is found to decrease generation capacity investment and total costs only when there is a target for renewable generation. Higher wind integration costs see a concentration of wind in high-wind regions with interconnection to other regions. - Highlights: ► We use mixed-integer linear programming to determine optimal interconnection locations for given renewable targets. ► The model is applied to a test system for eight regions in Northern Europe. ► Interconnection reduces costs only when there is a renewable target. ► Wind integration costs affect the interconnection portfolio.

  6. Research on SOI-based micro-resonator devices

    Science.gov (United States)

    Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

    2010-10-01

    SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

  7. Advanced processing of CdTe pixel radiation detectors

    Science.gov (United States)

    Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

    2017-12-01

    We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

  8. The road to miniaturization

    International Nuclear Information System (INIS)

    Iwai, Hiroshi; Hei Wong

    2006-01-01

    Silicon microelectronics has revolutionized the way we live, but how long can the relentless down sizing of devices continue? Hei Wong and Hiroshi Iwai describe the challenges facing the semiconductor industry today. For the last four decades the miniaturization of the microchip has been the driving force behind developments in all kinds of technology, from home entertainment to space exploration. At the heart of this revolution lies the metal-oxide-semiconductor (MOS) transistor, which has evolved in two ways. First, it has become smaller, with the latest devices measuring a thousandth of their original size. Second, the number of transistors that can be interconnected on a single chip has risen from a few tens to hundreds of millions. The density of microchips has followed an exponential trend that was famously identified by Gordon Moore of Intel in 1965. Moore predicted that the number of components that could be crammed into an integrated circuit would double every two years for the foreseeable future. In fact, he slightly underestimated the trend, because the average number has actually doubled every 18 months. The question keeping chip manufacturers awake in 2005 is how long this exponential growth can continue. (U.K.)

  9. The Interconnections of the LHC Cryomagnets

    CERN Document Server

    Jacquemod, A; Skoczen, Blazej; Tock, J P

    2001-01-01

    The main components of the LHC, the next world-class facility in high-energy physics, are the twin-aperture high-field superconducting cryomagnets to be installed in the existing 26.7-km long tunnel. After installation and alignment, the cryomagnets have to be interconnected. The interconnections must ensure the continuity of several functions: vacuum enclosures, beam pipe image currents (RF contacts), cryogenic circuits, electrical power supply, and thermal insulation. In the machine, about 1700 interconnections between cryomagnets are necessary. The interconnections constitute a unique system that is nearly entirely assembled in the tunnel. For each of them, various operations must be done: TIG welding of cryogenic channels (~ 50 000 welds), induction soldering of main superconducting cables (~ 10 000 joints), ultrasonic welding of auxiliary superconducting cables (~ 20 000 welds), mechanical assembly of various elements, and installation of the multi-layer insulation (~ 200 000 m2). Defective junctions cou...

  10. Epidemics in interconnected small-world networks.

    Science.gov (United States)

    Liu, Meng; Li, Daqing; Qin, Pengju; Liu, Chaoran; Wang, Huijuan; Wang, Feilong

    2015-01-01

    Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks has rarely been considered. Here, we study the susceptible-infected-susceptible (SIS) model of epidemic spreading in a system comprising two interconnected small-world networks. We find that the epidemic threshold in such networks decreases when the rewiring probability of the component small-world networks increases. When the infection rate is low, the rewiring probability affects the global steady-state infection density, whereas when the infection rate is high, the infection density is insensitive to the rewiring probability. Moreover, epidemics in interconnected small-world networks are found to spread at different velocities that depend on the rewiring probability.

  11. Epidemics in interconnected small-world networks.

    Directory of Open Access Journals (Sweden)

    Meng Liu

    Full Text Available Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks has rarely been considered. Here, we study the susceptible-infected-susceptible (SIS model of epidemic spreading in a system comprising two interconnected small-world networks. We find that the epidemic threshold in such networks decreases when the rewiring probability of the component small-world networks increases. When the infection rate is low, the rewiring probability affects the global steady-state infection density, whereas when the infection rate is high, the infection density is insensitive to the rewiring probability. Moreover, epidemics in interconnected small-world networks are found to spread at different velocities that depend on the rewiring probability.

  12. Solar-cell interconnect design for terrestrial photovoltaic modules

    Science.gov (United States)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1984-01-01

    Useful solar cell interconnect reliability design and life prediction algorithms are presented, together with experimental data indicating that the classical strain cycle (fatigue) curve for the interconnect material does not account for the statistical scatter that is required in reliability predictions. This shortcoming is presently addressed by fitting a functional form to experimental cumulative interconnect failure rate data, which thereby yields statistical fatigue curves enabling not only the prediction of cumulative interconnect failures during the design life of an array field, but also the quantitative interpretation of data from accelerated thermal cycling tests. Optimal interconnect cost reliability design algorithms are also derived which may allow the minimization of energy cost over the design life of the array field.

  13. A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

    International Nuclear Information System (INIS)

    Tang, Jiajie; Sun, Xiaowei; Luo, Le

    2011-01-01

    A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

  14. Self-Rerouting and Curative Interconnect Technology (SERCUIT)

    Science.gov (United States)

    2017-12-01

    SPECIAL REPORT RDMR-CS-17-01 SELF-REROUTING AND CURATIVE INTERCONNECT TECHNOLOGY (SERCUIT) Shiv Joshi Concepts to Systems, Inc...Final 4. TITLE AND SUBTITLE Self-Rerouting and Curative Interconnect Technology (SERCUIT) 5. FUNDING NUMBERS 6. AUTHOR(S) Shiv Joshi...concepts2systems.com (p) 434-207-5189 x (f) Click to view full size Title Contract Number SELF-REROUTING AND CURATIVE INTERCONNECT TECHNOLOGY (SERCUIT) W911W6-17-C-0029

  15. Network interconnections: an architectural reference model

    NARCIS (Netherlands)

    Butscher, B.; Lenzini, L.; Morling, R.; Vissers, C.A.; Popescu-Zeletin, R.; van Sinderen, Marten J.; Heger, D.; Krueger, G.; Spaniol, O.; Zorn, W.

    1985-01-01

    One of the major problems in understanding the different approaches in interconnecting networks of different technologies is the lack of reference to a general model. The paper develops the rationales for a reference model of network interconnection and focuses on the architectural implications for

  16. Semiconductor Manufacturing equipment introduction

    International Nuclear Information System (INIS)

    Im, Jong Sun

    2001-02-01

    This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

  17. Epidemics in interconnected small-world networks

    NARCIS (Netherlands)

    Liu, M.; Li, D.; Qin, P.; Liu, C.; Wang, H.; Wang, F.

    2015-01-01

    Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks

  18. [Application of next-generation semiconductor sequencing technologies in genetic diagnosis of inherited cardiomyopathies].

    Science.gov (United States)

    Zhao, Yue; Zhang, Hong; Xia, Xue-shan

    2015-07-01

    Inherited cardiomyopathy is the most common hereditary cardiac disease. It also causes a significant proportion of sudden cardiac deaths in young adults and athletes. So far, approximately one hundred genes have been reported to be involved in cardiomyopathies through different mechanisms. Therefore, the identification of the genetic basis and disease mechanisms of cardiomyopathies are important for establishing a clinical diagnosis and genetic testing. Next-generation semiconductor sequencing (NGSS) technology platform is a high-throughput sequencer capable of analyzing clinically derived genomes with high productivity, sensitivity and specificity. It was launched in 2010 by Life Technologies of USA, and it is based on a high density semiconductor chip, which was covered with tens of thousands of wells. NGSS has been successfully used in candidate gene mutation screening to identify hereditary disease. In this review, we summarize these genetic variations, challenge and application of NGSS in inherited cardiomyopathy, and its value in disease diagnosis, prevention and treatment.

  19. Interconnect rise time in superconducting integrating circuits

    International Nuclear Information System (INIS)

    Preis, D.; Shlager, K.

    1988-01-01

    The influence of resistive losses on the voltage rise time of an integrated-circuit interconnection is reported. A distribution-circuit model is used to present the interconnect. Numerous parametric curves are presented based on numerical evaluation of the exact analytical expression for the model's transient response. For the superconducting case in which the series resistance of the interconnect approaches zero, the step-response rise time is longer but signal strength increases significantly

  20. 76 FR 39870 - PJM Interconnection, LLC; PJM Power Providers Group v. PJM Interconnection, LLC; Notice of Date...

    Science.gov (United States)

    2011-07-07

    .... EL11-20-001] PJM Interconnection, LLC; PJM Power Providers Group v. PJM Interconnection, LLC; Notice of... Sell Offers for Planned Generation Capacity Resources submitted into PJM's Reliability Pricing Model... presents an opportunity to exercise buyer market power; (2) whether the Fixed Resource Requirement (FRR...

  1. Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

    KAUST Repository

    Johansson, Johan R.

    2012-03-12

    We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

  2. Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

    KAUST Repository

    Johansson, Johan R.; Bosaeus, Niklas; Kann, Nina; Å kerman, Bjö rn; Nordé n, Bengt; Khalid, Waqas

    2012-01-01

    We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

  3. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  4. The synchrotron light source as a tool for microtechnology

    CERN Document Server

    Harvey, E C

    2002-01-01

    We are all familiar with lathes and milling machines for shaping parts in machine shops and factories. But what if the parts we need to make are significantly smaller than a millimetre, and featuring details even smaller? Semiconductor chip manufacturers have faced these problems and have learnt to use new ways to make devices. No longer are transistors made one at a time, but rather are 'printed' millions at a time, together with their interconnection wiring in a process called photolithography. Light from an excimer laser is directed through masks that incorporate the patterns required and photoexposes surfaces positioned behind the masks. This form of photolithography is today a standard process in semiconductor FAB plants and has several critical advantages in terms of cost, reproducibility, reliability and its ability to scale towards ever smaller and more complex systems

  5. Optical Interconnects for Future Data Center Networks

    CERN Document Server

    Bergman, Keren; Tomkos, Ioannis

    2013-01-01

    Optical Interconnects for Future Data Center Networks covers optical networks and how they can provide high bandwidth, energy efficient interconnects with increased communication bandwidth. This volume, with contributions from leading researchers in the field, presents an integrated view of the expected future requirements of data centers and serves as a reference for some of the most advanced and promising solutions proposed by researchers from leading universities, research labs, and companies. The work also includes several novel architectures, each demonstrating different technologies such as optical circuits, optical switching, MIMO optical OFDM, and others. Additionally, Optical Interconnects for Future Data Center Networks provides invaluable insights into the benefits and advantages of optical interconnects and how they can be a promising alternative for future data center networks.

  6. On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

    International Nuclear Information System (INIS)

    Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

    2010-01-01

    We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

  7. Review of Interconnection Practices and Costs in the Western States

    Energy Technology Data Exchange (ETDEWEB)

    Bird, Lori A [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Flores-Espino, Francisco [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Volpi, Christina M [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ardani, Kristen B [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Manning, David [Western Interstate Energy Board (WIEB); McAllister, Richard [Western Interstate Energy Board (WIEB)

    2018-04-27

    The objective of this report is to evaluate the nature of barriers to interconnecting distributed PV, assess costs of interconnection, and compare interconnection practices across various states in the Western Interconnection. The report addresses practices for interconnecting both residential and commercial-scale PV systems to the distribution system. This study is part of a larger, joint project between the Western Interstate Energy Board (WIEB) and the National Renewable Energy Laboratory (NREL), funded by the U.S. Department of Energy, to examine barriers to distributed PV in the 11 states wholly within the Western Interconnection.

  8. Toward designing semiconductor-semiconductor heterojunctions for photocatalytic applications

    Science.gov (United States)

    Zhang, Liping; Jaroniec, Mietek

    2018-02-01

    Semiconductor photocatalysts show a great potential for environmental and energy-related applications, however one of the major disadvantages is their relatively low photocatalytic performance due to the recombination of electron-hole pairs. Therefore, intensive research is being conducted toward design of heterojunctions, which have been shown to be effective for improving the charge-transfer properties and efficiency of photocatalysts. According to the type of band alignment and direction of internal electric field, heterojunctions are categorized into five different types, each of which is associated with its own charge transfer characteristics. Since the design of heterojunctions requires the knowledge of band edge positions of component semiconductors, the commonly used techniques for the assessment of band edge positions are reviewed. Among them the electronegativity-based calculation method is applied for a large number of popular visible-light-active semiconductors, including some widely investigated bismuth-containing semiconductors. On basis of the calculated band edge positions and the type of component semiconductors reported, heterojunctions composed of the selected bismuth-containing semiconductors are proposed. Finally, the most popular synthetic techniques for the fabrication of heterojunctions are briefly discussed.

  9. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  10. Identifying influential spreaders in interconnected networks

    International Nuclear Information System (INIS)

    Zhao, Dawei; Li, Lixiang; Huo, Yujia; Yang, Yixian; Li, Shudong

    2014-01-01

    Identifying the most influential spreaders in spreading dynamics is of the utmost importance for various purposes for understanding or controlling these processes. The existing relevant works are limited to a single network. Most real networks are actually not isolated, but typically coupled and affected by others. The properties of epidemic spreading have recently been found to have some significant differences in interconnected networks from those in a single network. In this paper, we focus on identifying the influential spreaders in interconnected networks. We find that the well-known k-shell index loses effectiveness; some insignificant spreaders in a single network become the influential spreaders in the whole interconnected networks while some influential spreaders become no longer important. The simulation results show that the spreading capabilities of the nodes not only depend on their influence for the network topology, but also are dramatically influenced by the spreading rate. Based on this perception, a novel index is proposed for measuring the influential spreaders in interconnected networks. We then support the efficiency of this index with numerical simulations. (paper)

  11. Regulatory Issues Surrounding Merchant Interconnection

    International Nuclear Information System (INIS)

    Kuijlaars, Kees-Jan; Zwart, Gijsbert

    2003-11-01

    We discussed various issues concerning the regulatory perspective on private investment in interconnectors. One might claim that leaving investment in transmission infrastructure to competing market parties is more efficient than relying on regulated investment only (especially in the case of long (DC) lines connecting previously unconnected parts of the grids, so that externalities from e.g. loop flows do not play a significant role). We considered that some aspects of interconnection might reduce these market benefits. In particular, the large fixed costs of interconnection construction may lead to significant under investment (due to both first mover monopoly power and the fact that part of generation cost efficiencies realised by interconnection are not captured by the investor itself, and remain external to the investment decision). Second, merchant ownership restricts future opportunities for adaptation of regulation, as would be required e.g. for introduction of potentially more sophisticated methods of congestion management or market splitting. Some of the disadvantages of merchant investment may be mitigated however by a suitable regulatory framework, and we discussed some views in this direction. The issues we discussed are not intended to give a complete framework, and detailed regulation will certainly involve many more specific requirements. Areas we did not touch upon include e.g. the treatment of deep connection costs, rules for operation and maintenance of the line, and impact on availability of capacity on other interconnections

  12. Regulatory Issues Surrounding Merchant Interconnection

    Energy Technology Data Exchange (ETDEWEB)

    Kuijlaars, Kees-Jan; Zwart, Gijsbert [Office for Energy Regulation (DTe), The Hague (Netherlands)

    2003-11-01

    We discussed various issues concerning the regulatory perspective on private investment in interconnectors. One might claim that leaving investment in transmission infrastructure to competing market parties is more efficient than relying on regulated investment only (especially in the case of long (DC) lines connecting previously unconnected parts of the grids, so that externalities from e.g. loop flows do not play a significant role). We considered that some aspects of interconnection might reduce these market benefits. In particular, the large fixed costs of interconnection construction may lead to significant under investment (due to both first mover monopoly power and the fact that part of generation cost efficiencies realised by interconnection are not captured by the investor itself, and remain external to the investment decision). Second, merchant ownership restricts future opportunities for adaptation of regulation, as would be required e.g. for introduction of potentially more sophisticated methods of congestion management or market splitting. Some of the disadvantages of merchant investment may be mitigated however by a suitable regulatory framework, and we discussed some views in this direction. The issues we discussed are not intended to give a complete framework, and detailed regulation will certainly involve many more specific requirements. Areas we did not touch upon include e.g. the treatment of deep connection costs, rules for operation and maintenance of the line, and impact on availability of capacity on other interconnections.

  13. Atomic layer deposited TiO2 for implantable brain-chip interfacing devices

    International Nuclear Information System (INIS)

    Cianci, E.; Lattanzio, S.; Seguini, G.; Vassanelli, S.; Fanciulli, M.

    2012-01-01

    In this paper we investigated atomic layer deposition (ALD) TiO 2 thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 °C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al 2 O 3 buffer layer between TiO 2 and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

  14. Free-Space Optical Interconnect Employing VCSEL Diodes

    Science.gov (United States)

    Simons, Rainee N.; Savich, Gregory R.; Torres, Heidi

    2009-01-01

    Sensor signal processing is widely used on aircraft and spacecraft. The scheme employs multiple input/output nodes for data acquisition and CPU (central processing unit) nodes for data processing. To connect 110 nodes and CPU nodes, scalable interconnections such as backplanes are desired because the number of nodes depends on requirements of each mission. An optical backplane consisting of vertical-cavity surface-emitting lasers (VCSELs), VCSEL drivers, photodetectors, and transimpedance amplifiers is the preferred approach since it can handle several hundred megabits per second data throughput.The next generation of satellite-borne systems will require transceivers and processors that can handle several Gb/s of data. Optical interconnects have been praised for both their speed and functionality with hopes that light can relieve the electrical bottleneck predicted for the near future. Optoelectronic interconnects provide a factor of ten improvement over electrical interconnects.

  15. Brookhaven segment interconnect

    International Nuclear Information System (INIS)

    Morse, W.M.; Benenson, G.; Leipuner, L.B.

    1983-01-01

    We have performed a high energy physics experiment using a multisegment Brookhaven FASTBUS system. The system was composed of three crate segments and two cable segments. We discuss the segment interconnect module which permits communication between the various segments

  16. Optical backplane interconnect switch for data processors and computers

    Science.gov (United States)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  17. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  18. 76 FR 45248 - PJM Interconnection, L.L.C., PJM Power Providers Group v. PJM Interconnection, L.L.C...

    Science.gov (United States)

    2011-07-28

    ...-002; Docket No. EL11-20-001] PJM Interconnection, L.L.C., PJM Power Providers Group v. PJM Interconnection, L.L.C.; Supplemental Notice of Staff Technical Conference On June 13, 2011, the Commission issued... Resources Services, Inc., Maryland Public Service Commission, Monitoring Analytics, L.L.C., National Rural...

  19. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  20. Integrated microelectronic capacitive readout subsystem for lab-on-a-chip applications

    International Nuclear Information System (INIS)

    Spathis, Christos; Georgakopoulou, Konstantina; Petrellis, Nikos; Efstathiou, Konstantinos; Birbas, Alexios

    2014-01-01

    A mixed-signal capacitive biosensor readout system is presented with its main readout functionality embedded in an integrated circuit, compatible with complementary metal oxide semiconductor-type biosensors. The system modularity allows its usage as a consumable since it eventually leads to a system-on-chip where sensor and readout circuitry are hosted on the same die. In this work, a constant current source is used for measuring the input capacitance. Compared to most capacitive biosensor readout circuits, this method offers the convenience of adjusting both the range and the resolution, depending on the requirements dictated by the application. The chip consumes less than 5 mW of power and the die area is 0.06 mm 2 . It shows a broad input capacitance range (capable of measuring bio-capacitances from 6 pF to 9.8 nF), configurable resolution (down to 1 fF), robustness to various biological experiments and good linearity. The integrated nature of the readout system is proven to be sufficient both for one-time in situ (consumable-type) bio-measurements and its incorporation into a point-of-care system. (paper)

  1. Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

    Science.gov (United States)

    Pechal, M.; Besse, J.-C.; Mondal, M.; Oppliger, M.; Gasparinetti, S.; Wallraff, A.

    2016-08-01

    A switch capable of routing microwave signals at cryogenic temperatures is a desirable component for state-of-the-art experiments in many fields of applied physics, including but not limited to quantum-information processing, communication, and basic research in engineered quantum systems. Conventional mechanical switches provide low insertion loss but disturb operation of dilution cryostats and the associated experiments by heat dissipation. Switches based on semiconductors or microelectromechanical systems have a lower thermal budget but are not readily integrated with current superconducting circuits. Here we design and test an on-chip switch built by combining tunable transmission-line resonators with microwave beam splitters. The device is superconducting and as such dissipates a negligible amount of heat. It is compatible with current superconducting circuit fabrication techniques, operates with a bandwidth exceeding 100 MHz, is capable of handling photon fluxes on the order of 1 05 μ s-1 , equivalent to powers exceeding -90 dBm , and can be switched within approximately 6-8 ns. We successfully demonstrate operation of the device in the quantum regime by integrating it on a chip with a single-photon source and using it to route nonclassical itinerant microwave fields at the single-photon level.

  2. Design of an Elliptic Curve Cryptography processor for RFID tag chips.

    Science.gov (United States)

    Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

    2014-09-26

    Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

  3. SSC [Superconducting Super Collider] magnet mechanical interconnections

    International Nuclear Information System (INIS)

    Bossert, R.C.; Niemann, R.C.; Carson, J.A.; Ramstein, W.L.; Reynolds, M.P.; Engler, N.H.

    1989-03-01

    Installation of superconducting accelerator dipole and quadrupole magnets and spool pieces in the SSC tunnel requires the interconnection of the cryostats. The connections are both of an electrical and mechanical nature. The details of the mechanical connections are presented. The connections include piping, thermal shields and insulation. There are seven piping systems to be connected. These systems must carry cryogenic fluids at various pressures or maintain vacuum and must be consistently leak tight. The interconnection region must be able to expand and contract as magnets change in length while cooling and warming. The heat leak characteristics of the interconnection region must be comparable to that of the body of the magnet. Rapid assembly and disassembly is required. The magnet cryostat development program is discussed. Results of quality control testing are reported. Results of making full scale interconnections under magnet test situations are reviewed. 11 figs., 4 tabs

  4. Semiconductor physics

    CERN Document Server

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  5. Fusion-bonded fluidic interconnects

    International Nuclear Information System (INIS)

    Fazal, I; Elwenspoek, M C

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are discussed in terms of the homogeneity and strength of fusion bond. High pressure testing shows that the bond strength is large enough for most applications of fluidic interconnects. The bond strength for 525 µm thick silicon, with glass tubes having an outer diameter of 6 mm and with a wall thickness of 2 mm, is more than 60 bars after annealing at a temperature of 800 °C

  6. Phase space dynamics and control of the quantum particles associated to hypergraph states

    Directory of Open Access Journals (Sweden)

    Berec Vesna

    2015-01-01

    Full Text Available As today’s nanotechnology focus becomes primarily oriented toward production and manipulation of materials at the subatomic level, allowing the performance and complexity of interconnects where the device density accepts more than hundreds devices on a single chip, the manipulation of semiconductor nanostructures at the subatomic level sets its prime tasks on preserving and adequate transmission of information encoded in specified (quantum states. The presented study employs the quantum communication protocol based on the hypergraph network model where the numerical solutions of equations of motion of quantum particles are associated to vertices (assembled with device chip, which follow specific controllable paths in the phase space. We address these findings towards ultimate quest for prediction and selective control of quantum particle trajectories. In addition, presented protocols could represent valuable tool for reducing background noise and uncertainty in low-dimensional and operationally meaningful, scalable complex systems.

  7. Colligation, Or the Logical Inference of Interconnection

    DEFF Research Database (Denmark)

    Falster, Peter

    1998-01-01

    laws or assumptions. Yet interconnection as an abstract concept seems to be without scientific underpinning in pure logic. Adopting a historical viewpoint, our aim is to show that the reasoning of interconnection may be identified with a neglected kind of logical inference, called "colligation...

  8. Colligation or, The Logical Inference of Interconnection

    DEFF Research Database (Denmark)

    Franksen, Ole Immanuel; Falster, Peter

    2000-01-01

    laws or assumptions. Yet interconnection as an abstract concept seems to be without scientific underpinning in oure logic. Adopting a historical viewpoint, our aim is to show that the reasoning of interconnection may be identified with a neglected kind of logical inference, called "colligation...

  9. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  10. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  11. STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

    Directory of Open Access Journals (Sweden)

    Ireneusz Zagórski

    2016-12-01

    Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

  12. Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

    International Nuclear Information System (INIS)

    Gozzo, F.; Cossy-Favre, A.; Padmore, H.

    1997-01-01

    Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by the Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here

  13. Chip-To-Chip Optical Interconnection Using MEMS Mirrors

    Science.gov (United States)

    2009-03-26

    power generated through a resistor is a function of this common current but different resistances, different amounts of heat are generated in the two...Chiu, “Modeling and control of piezo - electric cantilever beam micro mirror and micro laser arrays to reduce image band- ing in electrophotographic

  14. Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

    Science.gov (United States)

    Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

    2018-03-01

    The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

  15. Measurement stand for diagnosis of semiconductor detectors based on IBM PC/XT computer (4-way spectrometric analysis of pulses)

    International Nuclear Information System (INIS)

    Gruszecki, M.

    1990-01-01

    The technical assumptions and partial realization of our technological stand for quality inspection of semiconductor detectors for ionizing radiation manufactured in the INP in Cracow are described. To increase the efficiency of the measurements simultaneous checking of 4 semiconductor chips or finished products is suggested. In order to justify this measurement technique a review of possible variants of the measurement apparatus is presented for the systems consisting of home made units. Comparative parameters for the component modules and for complete measuring systems are given. The construction and operation of data acquisition system based on IBM PC/XT are described. The system ensures simultaneous registration of pulses obtained from 4 detectors with maximal rate of up to 500 x 10 3 pulses/s. 42 refs., 6 figs., 3 tabs. (author)

  16. Rapid, all dry microfabrication of three-dimensional Co3O4/Pt nanonetworks for high-performance microsupercapacitors.

    Science.gov (United States)

    Ma, Xinyu; Feng, Shuxuan; He, Liang; Yan, Mengyu; Tian, Xiaocong; Li, Yanxi; Tang, Chunjuan; Hong, Xufeng; Mai, Liqiang

    2017-08-17

    On-chip electrochemical energy storage devices have attracted growing attention due to the decreasing size of electronic devices. Various approaches have been applied for constructing the microsupercapacitors. However, the microfabrication of high-performance microsupercapacitors by conventional and fully compatible semiconductor microfabrication technologies is still a critical challenge. Herein, unique three-dimensional (3D) Co 3 O 4 nanonetwork microelectrodes formed by the interconnection of Co 3 O 4 nanosheets are constructed by controllable physical vapor deposition combined with rapid thermal annealing. This construction process is an all dry and rapid (≤5 minutes) procedure. Afterward, by sputtering highly electrically conductive Pt nanoparticles on the microelectrodes, the 3D Co 3 O 4 /Pt nanonetworks based microsupercapacitor is fabricated, showing a high volume capacitance (35.7 F cm -3 ) at a scan rate of 20 mV s -1 due to the unique interconnected structures, high electrical conductivity and high surface area of the microelectrodes. This microfabrication process is also used to construct high-performance flexible microsupercapacitors, and it can be applied in the construction of wearable devices. The proposed strategy is completely compatible with the current semiconductor microfabrication and shows great potential in the applications of the large-scale integration of micro/nano and wearable devices.

  17. Development of thin pixel sensors and a novel interconnection technology for the SLHC

    International Nuclear Information System (INIS)

    Macchiolo, A.; Andricek, L.; Beimforde, M.; Dubbert, J.; Ghodbane, N.; Kortner, O.; Kroha, H.; Moser, H.G.; Nisius, R.; Richter, R.H.

    2008-01-01

    We present an R and D activity aiming to develop a new detector concept in the framework of the ATLAS pixel detector upgrade in view of the Super-LHC. The new devices combine 75-150 μm thick pixels sensors with a vertical integration technology. A new production of thin pixel sensors on n- and p-type material is under way at the MPI Semiconductor Laboratory. These devices will be connected to the ATLAS read-out electronics with the new Solid-Liquid InterDiffusion technique as an alternative to the bump-bonding process. We also plan for the signals to be extracted from the back of the electronics wafer through Inter-Chip-Vias. The compatibility of the Solid-Liquid InterDiffusion process with the silicon sensor functionality has already been demonstrated by measurements on two wafers hosting diodes with an active thickness of 50 μm

  18. Bio-patch design and implementation based on a low-power system-on-chip and paper-based inkjet printing technology.

    Science.gov (United States)

    Yang, Geng; Xie, Li; Mantysalo, Matti; Chen, Jian; Tenhunen, Hannu; Zheng, L R

    2012-11-01

    This paper presents the prototype implementation of a Bio-Patch using fully integrated low-power System-on-Chip (SoC) sensor and paper-based inkjet printing technology. The SoC sensor is featured with programmable gain and bandwidth to accommodate a variety of bio-signals. It is fabricated in a 0.18-ìm standard CMOS technology, with a total power consumption of 20 ìW from a 1.2 V supply. Both the electrodes and interconnections are implemented by printing conductive nano-particle inks on a flexible photo paper substrate using inkjet printing technology. A Bio-Patch prototype is developed by integrating the SoC sensor, a soft battery, printed electrodes and interconnections on a photo paper substrate. The Bio-Patch can work alone or operate along with other patches to establish a wired network for synchronous multiple-channel bio-signals recording. The measurement results show that electrocardiogram and electromyogram are successfully measured in in-vivo tests using the implemented Bio-Patch prototype.

  19. Laser printing of 3D metallic interconnects

    Science.gov (United States)

    Beniam, Iyoel; Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Raymond C. Y.; Piqué, Alberto

    2016-04-01

    The use of laser-induced forward transfer (LIFT) techniques for the printing of functional materials has been demonstrated for numerous applications. The printing gives rise to patterns, which can be used to fabricate planar interconnects. More recently, various groups have demonstrated electrical interconnects from laser-printed 3D structures. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or of pastes containing dispersed metallic particles. However, the generated 3D structures do not posses the same metallic conductivity as a bulk metal interconnect of the same cross-section and length as those formed by wire bonding or tab welding. An alternative is to laser transfer entire 3D structures using a technique known as lase-and-place. Lase-and-place is a LIFT process whereby whole components and parts can be transferred from a donor substrate onto a desired location with one single laser pulse. This paper will describe the use of LIFT to laser print freestanding, solid metal foils or beams precisely over the contact pads of discrete devices to interconnect them into fully functional circuits. Furthermore, this paper will also show how the same laser can be used to bend or fold the bulk metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief for the circuits under flexing or during motion from thermal mismatch. These interconnect "ridges" can span wide gaps (on the order of a millimeter) and accommodate height differences of tens of microns between adjacent devices. Examples of these laser printed 3D metallic bridges and their role in the development of next generation electronics by additive manufacturing will be presented.

  20. High temperature corrosion of metallic interconnects in solid oxide fuel cells

    International Nuclear Information System (INIS)

    Bastidas, D. M.

    2006-01-01

    Research and development has made it possible to use metallic interconnects in solid oxide fuel cells (SOFC) instead of ceramic materials. The use of metallic interconnects was formerly hindered by the high operating temperature, which made the interconnect degrade too much and too fast to be an efficient alternative. When the operating temperature was lowered, the use of metallic interconnects proved to be favourable since they are easier and cheaper to produce than ceramic interconnects. However, metallic interconnects continue to be degraded despite the lowered temperature, and their corrosion products contribute to electrical degradation in the fuel cell. coatings of nickel, chromium, aluminium, zinc, manganese, yttrium or lanthanum between the interconnect and the electrodes reduce this degradation during operation. (Author) 66 refs

  1. Atomic layer deposited TiO{sub 2} for implantable brain-chip interfacing devices

    Energy Technology Data Exchange (ETDEWEB)

    Cianci, E., E-mail: elena.cianci@mdm.imm.cnr.it [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (MB) (Italy); Lattanzio, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Dipartimento di Ingegneria dell' Informazione, Universita di Padova, 35131 Padova (Italy); Seguini, G. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Vassanelli, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Fanciulli, M. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano-Bicocca, 20126 Milano (Italy)

    2012-05-01

    In this paper we investigated atomic layer deposition (ALD) TiO{sub 2} thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 Degree-Sign C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al{sub 2}O{sub 3} buffer layer between TiO{sub 2} and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

  2. A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication.

    Directory of Open Access Journals (Sweden)

    Usman Ali Gulzari

    Full Text Available A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor's and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.

  3. Driving Interconnected Networks to Supercriticality

    Directory of Open Access Journals (Sweden)

    Filippo Radicchi

    2014-04-01

    Full Text Available Networks in the real world do not exist as isolated entities, but they are often part of more complicated structures composed of many interconnected network layers. Recent studies have shown that such mutual dependence makes real networked systems potentially exposed to atypical structural and dynamical behaviors, and thus there is an urgent necessity to better understand the mechanisms at the basis of these anomalies. Previous research has mainly focused on the emergence of atypical properties in relation to the moments of the intra- and interlayer degree distributions. In this paper, we show that an additional ingredient plays a fundamental role for the possible scenario that an interconnected network can face: the correlation between intra- and interlayer degrees. For sufficiently high amounts of correlation, an interconnected network can be tuned, by varying the moments of the intra- and interlayer degree distributions, in distinct topological and dynamical regimes. When instead the correlation between intra- and interlayer degrees is lower than a critical value, the system enters in a supercritical regime where dynamical and topological phases are no longer distinguishable.

  4. Financial viability of the Sonora-Baja California interconnection line

    International Nuclear Information System (INIS)

    Alonso, G.; Ortega, G.

    2017-09-01

    In the Development Program of the National Electricity Sector 2015-2029, an electric interconnection line between Sonora and Baja California (Mexico) is proposed, this study analyzes the financial viability of this interconnection line based on the maximum hourly and seasonal energy demand between both regions and proposes alternatives for the supply of electric power that supports the economic convenience of this interconnection line. The results show that additional capacity is required in Sonora to cover the maximum demands of both regions since in the current condition of the National Electric System the interconnection line is not justified. (Author)

  5. Laser printed interconnects for flexible electronics

    Science.gov (United States)

    Pique, Alberto; Beniam, Iyoel; Mathews, Scott; Charipar, Nicholas

    Laser-induced forward transfer (LIFT) can be used to generate microscale 3D structures for interconnect applications non-lithographically. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or dispersed metallic nanoparticles. However, the resulting 3D structures do not achieve the bulk conductivity of metal interconnects of the same cross-section and length as those formed by wire bonding or tab welding. It is possible, however, to laser transfer entire structures using a LIFT technique known as lase-and-place. Lase-and-place allows whole components and parts to be transferred from a donor substrate onto a desired location with one single laser pulse. This talk will present the use of LIFT to laser print freestanding solid metal interconnects to connect individual devices into functional circuits. Furthermore, the same laser can bend or fold the thin metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief due to flexing or thermal mismatch. Examples of these laser printed 3D metallic bridges and their role in the development of next generation flexible electronics by additive manufacturing will be presented. This work was funded by the Office of Naval Research (ONR) through the Naval Research Laboratory Basic Research Program.

  6. The Electrical Characteristics of The N-Organic Semiconductor/P-Inorganic Semiconductor Diode

    International Nuclear Information System (INIS)

    Aydin, M. E.

    2008-01-01

    n-organic semiconductor (PEDOT) / p-inorganic semiconductor Si diode was formed by deep coating method. The method has been achieved by coating n-inorganic semiconductor PEDOT on top of p-inorganic semiconductor. The n-organic semiconductor PEDOT/ p-inorganic semiconductor diode demonstrated rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The barrier height , ideality factor values were obtained as of 0.88 eV and 1.95 respectively. The diode showed non-ideal I-V behavior with an ideality factor greater than unity that could be ascribed to the interfacial layer

  7. Carbon nanotube and graphene nanoribbon interconnects

    CERN Document Server

    Das, Debaprasad

    2014-01-01

    "The book, Caron Nanotube and Graphene Nanoribbon Interconnects, authored by Drs. Debapraad Das and Hafizur Rahaman serves as a good source of material on CNT and GNR interconnects for readers who wish to get into this area and also for practicing engineers who would like to be updated in advances of this field."-Prof. Ashok Srivastava, Louisiana State University, Baton Rouge, USA"Mathematical analysis included in each and every chapter is the main strength of the materials. ... The book is very precise and useful for those who are working in this area. ... highly focused, very compact, and easy to apply. ... This book depicts a detailed analysis and modelling of carbon nanotube and graphene nanoribbon interconnects. The book also covers the electrical circuit modelling of carbon nanotubes and graphene nanoribbons."-Prof. Chandan Kumar Sarkar, Jadavpur University, Kolkata, India.

  8. Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    Science.gov (United States)

    Hashida, Takushi; Nagata, Makoto

    Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

  9. Economic and environmental benefits of interconnected systems. The Spanish example

    International Nuclear Information System (INIS)

    Chicharro, A.S.; Dios Alija, R. de

    1996-01-01

    The interconnected systems provide large technical and economic benefits which, evaluated and contrasted with the associated network investment cost, usually produce important net savings. There are continental electrical systems formed by many interconnected subsystems. The optimal size of an interconnection should be defined within an economic background. It is necessary to take into account the global environmental effects. The approach and results of studies carried out by Red Electrica is presented, in order to analyse both economic and environmental benefits resulting from an increase in the present Spanish interconnection capacities. From both economic and environmental points of view, the development of the interconnected systems is highly positive. (author)

  10. Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

    Science.gov (United States)

    Ashenafi, Emeshaw

    Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

  11. Cellular structures with interconnected microchannels

    Science.gov (United States)

    Shaefer, Robert Shahram; Ghoniem, Nasr M.; Williams, Brian

    2018-01-30

    A method for fabricating a cellular tritium breeder component includes obtaining a reticulated carbon foam skeleton comprising a network of interconnected ligaments. The foam skeleton is then melt-infiltrated with a tritium breeder material, for example, lithium zirconate or lithium titanate. The foam skeleton is then removed to define a cellular breeder component having a network of interconnected tritium purge channels. In an embodiment the ligaments of the foam skeleton are enlarged by adding carbon using chemical vapor infiltration (CVI) prior to melt-infiltration. In an embodiment the foam skeleton is coated with a refractory material, for example, tungsten, prior to melt infiltration.

  12. Interconnectivity: Benefits and Challenges

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2010-09-15

    Access to affordable and reliable electricity supplies is a basic prerequisite for economic and social development, prosperity, health, education and all other aspects of modern society. Electricity can be generated both near and far from the consumption areas as transmission lines, grid interconnections and distribution systems can transport it to the final consumer. In the vast majority of countries, the electricity sector used to be owned and run by the state. The wave of privatisation and market introduction in a number of countries and regions which started in the late 1980's has in many cases involved unbundling of generation from transmission and distribution (T and D). This has nearly everywhere exposed transmission bottlenecks limiting the development of well-functioning markets. Transmission on average accounts for about 10-15% of total final kWh cost paid by the end-user but it is becoming a key issue for effective operation of liberalised markets and for their further development. An integrated and adequate transmission infrastructure is of utmost importance for ensuring the delivery of the most competitively priced electricity, including externalities, to customers, both near and far from the power generating facilities. In this report, the role of interconnectivity in the development of energy systems is examined with the associated socio-economic, environmental, financial and regulatory aspects that must be taken into account for successful interconnection projects.

  13. Semiconductor Physical Electronics

    CERN Document Server

    Li, Sheng

    2006-01-01

    Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

  14. Performance of thin pixel sensors irradiated up to a fluence of 1016neqcm-2 and development of a new interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    Macchiolo, A.; Andricek, L.; Beimforde, M.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Weigell, P.

    2011-01-01

    A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R and D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and 150μm has been produced using a thinning technique developed at the Max-Planck-Institut Halbleiterlabor (HLL). Charge Collection Efficiency measurements have been performed, yielding a higher CCE than expected from the present radiation damage models. The interconnection of thin n-in-p pixels to the FE-I3 ATLAS electronics is under way, exploiting the Solid Liquid Interdiffusion (SLID) technique developed by the Fraunhofer Institut EMFT. In addition, preliminary studies aimed at Inter-Chip-Vias (ICV) etching into the FE-I3 electronics are reported. ICVs will be used to route the signals vertically through the read-out chip, to newly created pads on the backside. This should serve as a proof of principle for future four-side tileable pixel assemblies, avoiding the cantilever presently needed in the chip for the wire bonding.

  15. Cross-border versus cross-sector interconnectivity in renewable energy systems

    International Nuclear Information System (INIS)

    Thellufsen, Jakob Zinck; Lund, Henrik

    2017-01-01

    In the transition to renewable energy systems, fluctuating renewable energy, such as wind and solar power, plays a large and important role. This creates a challenge in terms of meeting demands, as the energy production fluctuates based on weather patterns. To utilise high amounts of fluctuating renewable energy, the energy system has to be more flexible in terms of decoupling demand and production. This paper investigates two potential ways to increase flexibility. The first is the interconnection between energy systems, for instance between two countries, labelled as cross-border interconnection, and the second is cross-sector interconnection, i.e., the integration between different parts of an energy system, for instance heat and electricity. This paper seeks to compare the types of interconnectivity and discuss to which extent they are mutually beneficial. To do this, the study investigates two energy systems that represent Northern and Southern Europe. Both systems go through three developmental steps that increase the cross-sector interconnectivity. At each developmental step an increasing level of transmission capacities is examined to identify the benefits of cross-border interconnectivity. The results show that while both measures increase the system utilisation of renewable energy and the system efficiency, the cross-sector interconnection gives the best system performance. To analyse the possible interaction between cross-sector and cross-border interconnectivity, two main aspects have to be clarified. The first part defines the approach and the second is the construction of the two archetypes. - Highlights: • A method to investigate system integration and system interconnection is suggested. • The implementation is investigated across a Northern and Southern energy system. • The study identifies benefits of system integration and system interconnection. • The performance of the energy system benefits most from system integration.

  16. Fuel cell electrode interconnect contact material encapsulation and method

    Science.gov (United States)

    Derose, Anthony J.; Haltiner, Jr., Karl J.; Gudyka, Russell A.; Bonadies, Joseph V.; Silvis, Thomas W.

    2016-05-31

    A fuel cell stack includes a plurality of fuel cell cassettes each including a fuel cell with an anode and a cathode. Each fuel cell cassette also includes an electrode interconnect adjacent to the anode or the cathode for providing electrical communication between an adjacent fuel cell cassette and the anode or the cathode. The interconnect includes a plurality of electrode interconnect protrusions defining a flow passage along the anode or the cathode for communicating oxidant or fuel to the anode or the cathode. An electrically conductive material is disposed between at least one of the electrode interconnect protrusions and the anode or the cathode in order to provide a stable electrical contact between the electrode interconnect and the anode or cathode. An encapsulating arrangement segregates the electrically conductive material from the flow passage thereby, preventing volatilization of the electrically conductive material in use of the fuel cell stack.

  17. Fundamentals of semiconductor devices

    CERN Document Server

    Lindmayer, Joseph

    1965-01-01

    Semiconductor properties ; semiconductor junctions or diodes ; transistor fundamentals ; inhomogeneous impurity distributions, drift or graded-base transistors ; high-frequency properties of transistors ; band structure of semiconductors ; high current densities and mechanisms of carrier transport ; transistor transient response and recombination processes ; surfaces, field-effect transistors, and composite junctions ; additional semiconductor characteristics ; additional semiconductor devices and microcircuits ; more metal, insulator, and semiconductor combinations for devices ; four-pole parameters and configuration rotation ; four-poles of combined networks and devices ; equivalent circuits ; the error function and its properties ; Fermi-Dirac statistics ; useful physical constants.

  18. Electrode and interconnect for miniature fuel cells using direct methanol feed

    Science.gov (United States)

    Narayanan, Sekharipuram R. (Inventor); Valdez, Thomas I. (Inventor); Clara, Filiberto (Inventor)

    2004-01-01

    An improved system for interconnects in a fuel cell. In one embodiment, the membranes are located in parallel with one another, and current flow between them is facilitated by interconnects. In another embodiment, all of the current flow is through the interconnects which are located on the membranes. The interconnects are located between two electrodes.

  19. Miniature interferometer for refractive index measurement in microfluidic chip

    Science.gov (United States)

    Chen, Minghui; Geiser, Martial; Truffer, Frederic; Song, Chengli

    2012-12-01

    The design and development of the miniaturized interferometer for measurement of the refractive index or concentration of sub-microliter volume aqueous solution in microfludic chip is presented. It is manifested by a successful measurement of the refractive index of sugar-water solution, by utilizing a laser diode for light source and the small robust instrumentation for practical implementation. Theoretically, the measurement principle and the feasibility of the system are analyzed. Experimental device is constructed with a diode laser, lens, two optical plate and a complementary metal oxide semiconductor (CMOS). Through measuring the positional changes of the interference fringes, the refractive index change are retrieved. A refractive index change of 10-4 is inferred from the measured image data. The entire system is approximately the size of half and a deck of cards and can operate on battery power for long time.

  20. Current Solutions: Recent Experience in Interconnecting Distributed Energy Resources

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, M.

    2003-09-01

    This report catalogues selected real-world technical experiences of utilities and customers that have interconnected distributed energy assets with the electric grid. This study was initiated to assess the actual technical practices for interconnecting distributed generation and had a particular focus on the technical issues covered under the Institute of Electrical and Electronics Engineers (IEEE) 1547(TM) Standard for Interconnecting Distributed Resources With Electric Power Systems.

  1. Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects

    International Nuclear Information System (INIS)

    Majumder, M.K.; Pandya, N.D.; Kaushik, B.K.; Manhas, S.K.

    2013-01-01

    Carbon nanotube (CN T) can be considered as an emerging interconnect material in current nano scale regime. They are more promising than other interconnect materials such as Al or Cu because of their robustness to electromigration. This research paper aims to address the crosstalk-related issues (signal integrity) in interconnect lines. Different analytical models of single- (SWCNT), double- (DWCNT), and multiwalled CNTs (MWCNT) are studied to analyze the crosstalk delay at global interconnect lengths. A capacitively coupled three-line bus architecture employing CMOS driver is used for accurate estimation of crosstalk delay. Each line in bus architecture is represented with the equivalent RLC models of single and bundled SWCNT, DWCNT, and MWCNT interconnects. Crosstalk delay is observed at middle line (victim) when it switches in opposite direction with respect to the other two lines (aggressors). Using the data predicted by ITRS 2012, a comparative analysis on the basis of crosstalk delay is performed for bundled SWCNT/DWCNT and single MWCNT interconnects. It is observed that the overall crosstalk delay is improved by 40.92% and 21.37% for single MWCNT in comparison to bundled SWCNT and bundled DWCNT interconnects, respectively.

  2. The effect of long-distance interconnection on wind power variability

    International Nuclear Information System (INIS)

    Fertig, Emily; Apt, Jay; Jaramillo, Paulina; Katzenstein, Warren

    2012-01-01

    We use time- and frequency-domain techniques to quantify the extent to which long-distance interconnection of wind plants in the United States would reduce the variability of wind power output. Previous work has shown that interconnection of just a few wind plants across moderate distances could greatly reduce the ratio of fast- to slow-ramping generators in the balancing portfolio. We find that interconnection of aggregate regional wind plants would not reduce this ratio further but would reduce variability at all frequencies examined. Further, interconnection of just a few wind plants reduces the average hourly change in power output, but interconnection across regions provides little further reduction. Interconnection also reduces the magnitude of low-probability step changes and doubles firm power output (capacity available at least 92% of the time) compared with a single region. First-order analysis indicates that balancing wind and providing firm power with local natural gas turbines would be more cost-effective than with transmission interconnection. For net load, increased wind capacity would require more balancing resources but in the same proportions by frequency as currently, justifying the practice of treating wind as negative load. (letter)

  3. SU-8 cantilever chip interconnection

    DEFF Research Database (Denmark)

    Johansson, Alicia Charlotte; Janting, Jakob; Schultz, Peter

    2006-01-01

    The polymer SU-8 is becoming widely used for all kinds of micromechanical and microfluidic devices, not only as a photoresist but also as the constitutional material of the devices. Many of these polymeric devices need to include a microfluidic system as well as electrical connection from the ele...

  4. Chip compacting press; Jido kirikuzu asshukuki

    Energy Technology Data Exchange (ETDEWEB)

    Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

    1998-08-15

    The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

  5. A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2018-01-01

    Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

  6. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  7. Compound Semiconductor Radiation Detector

    International Nuclear Information System (INIS)

    Kim, Y. K.; Park, S. H.; Lee, W. G.; Ha, J. H.

    2005-01-01

    In 1945, Van Heerden measured α, β and γ radiations with the cooled AgCl crystal. It was the first radiation measurement using the compound semiconductor detector. Since then the compound semiconductor has been extensively studied as radiation detector. Generally the radiation detector can be divided into the gas detector, the scintillator and the semiconductor detector. The semiconductor detector has good points comparing to other radiation detectors. Since the density of the semiconductor detector is higher than that of the gas detector, the semiconductor detector can be made with the compact size to measure the high energy radiation. In the scintillator, the radiation is measured with the two-step process. That is, the radiation is converted into the photons, which are changed into electrons by a photo-detector, inside the scintillator. However in the semiconductor radiation detector, the radiation is measured only with the one-step process. The electron-hole pairs are generated from the radiation interaction inside the semiconductor detector, and these electrons and charged ions are directly collected to get the signal. The energy resolution of the semiconductor detector is generally better than that of the scintillator. At present, the commonly used semiconductors as the radiation detector are Si and Ge. However, these semiconductor detectors have weak points. That is, one needs thick material to measure the high energy radiation because of the relatively low atomic number of the composite material. In Ge case, the dark current of the detector is large at room temperature because of the small band-gap energy. Recently the compound semiconductor detectors have been extensively studied to overcome these problems. In this paper, we will briefly summarize the recent research topics about the compound semiconductor detector. We will introduce the research activities of our group, too

  8. Solid spectroscopy: semiconductors

    International Nuclear Information System (INIS)

    Silva, C.E.T.G. da

    1983-01-01

    Photoemission as technique of study of the semiconductor electronic structure is shortly discussed. Homogeneous and heterogeneous semiconductors, where volume and surface electronic structure, core levels and O and H chemisorption in GaAs, Schottky barrier are treated, respectively. Amorphous semiconductors are also discussed. (L.C.) [pt

  9. Cost based interconnection charges as a way to induce competition

    DEFF Research Database (Denmark)

    Falch, Morten

    The objective of this paper is to analyse the relationship between regulation of interconnection charges and the level of competition. One of the most important issues in the debate on interconnect regulation has been use of forward looking costs for setting of interconnection charges. This debat...... has been ongoing within the EU as well as in US. This paper discusses the European experiences and in particular the Danish experiences with use of cost based interconnection charges, and their impact on competition in the telecom market....

  10. Cross-border versus cross-sector interconnectivity in renewable energy systems

    DEFF Research Database (Denmark)

    Thellufsen, Jakob Zinck; Lund, Henrik

    2017-01-01

    renewable energy, the energy system has to be more flexible in terms of decoupling demand and production. This paper investigates two potential ways to increase flexibility. The first is the interconnection between energy systems, for instance between two countries, labelled as cross-border interconnection...... systems that represent Northern and Southern Europe. Both systems go through three developmental steps that increase the cross-sector interconnectivity. At each developmental step an increasing level of transmission capacities is examined to identify the benefits of cross-border interconnectivity...

  11. Digital optical interconnects for photonic computing

    Science.gov (United States)

    Guilfoyle, Peter S.; Stone, Richard V.; Zeise, Frederick F.

    1994-05-01

    A 32-bit digital optical computer (DOC II) has been implemented in hardware utilizing 8,192 free-space optical interconnects. The architecture exploits parallel interconnect technology by implementing microcode at the primitive level. A burst mode of 0.8192 X 1012 binary operations per sec has been reliably demonstrated. The prototype has been successful in demonstrating general purpose computation. In addition to emulating the RISC instruction set within the UNIX operating environment, relational database text search operations have been implemented on DOC II.

  12. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

    NARCIS (Netherlands)

    2008-01-01

    The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) which is provided with at least one semiconductor element, wherein on the surface of the semiconductor body (1) a mesa- shaped semiconductor region (2) is formed, a masking layer (3) is

  13. Analysis of interconnecting energy systems over a synchronized life cycle

    International Nuclear Information System (INIS)

    Nian, Victor

    2016-01-01

    Highlights: • A methodology is developed for evaluating a life cycle of interconnected systems. • A new concept of partial temporal boundary is introduced via quantitative formulation. • The interconnecting systems are synchronized through the partial temporal boundary. • A case study on the life cycle of the coal–uranium system is developed. - Abstract: Life cycle analysis (LCA) using the process chain analysis (PCA) approach has been widely applied to energy systems. When applied to an individual energy system, such as coal or nuclear electricity generation, an LCA–PCA methodology can yield relatively accurate results with its detailed process representation based on engineering data. However, there are fundamental issues when applying conventional LCA–PCA methodology to a more complex life cycle, namely, a synchronized life cycle of interconnected energy systems. A synchronized life cycle of interconnected energy systems is established through direct interconnections among the processes of different energy systems, and all interconnecting systems are bounded within the same timeframe. Under such a life cycle formation, there are some major complications when applying conventional LCA–PCA methodology to evaluate the interconnecting energy systems. Essentially, the conventional system and boundary formulations developed for a life cycle of individual energy system cannot be directly applied to a life cycle of interconnected energy systems. To address these inherent issues, a new LCA–PCA methodology is presented in this paper, in which a new concept of partial temporal boundary is introduced to synchronize the interconnecting energy systems. The importance and advantages of these new developments are demonstrated through a case study on the life cycle of the coal–uranium system.

  14. Multilevel Dual Damascene copper interconnections

    Science.gov (United States)

    Lakshminarayanan, S.

    Copper has been acknowledged as the interconnect material for future generations of ICs to overcome the bottlenecks on speed and reliability present with the current Al based wiring. A new set of challenges brought to the forefront when copper replaces aluminum, have to be met and resolved to make it a viable option. Unit step processes related to copper technology have been under development for the last few years. In this work, the application of copper as the interconnect material in multilevel structures with SiO2 as the interlevel dielectric has been explored, with emphasis on integration issues and complete process realization. Interconnect definition was achieved by the Dual Damascene approach using chemical mechanical polishing of oxide and copper. The choice of materials used as adhesion promoter/diffusion barrier included Ti, Ta and CVD TiN. Two different polish chemistries (NH4OH or HNO3 based) were used to form the interconnects. The diffusion barrier was removed during polishing (in the case of TiN) or by a post CMP etch (as with Ti or Ta). Copper surface passivation was performed using boron implantation and PECVD nitride encapsulation. The interlevel dielectric way composed of a multilayer stack of PECVD SiO2 and SixNy. A baseline process sequence which ensured the mechanical and thermal compatibility of the different unit steps was first created. A comprehensive test vehicle was designed and test structures were fabricated using the process flow developed. Suitable modifications were subsequently introduced in the sequence as and when processing problems were encountered. Electrical characterization was performed on the fabricated devices, interconnects, contacts and vias. The structures were subjected to thermal stressing to assess their stability and performance. The measurement of interconnect sheet resistances revealed lower copper loss due to dishing on samples polished using HNO3 based slurry. Interconnect resistances remained stable upto 400o

  15. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  16. Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3; Charakterisierung von bildgebenden Pixeldetektoren aus Si und CdTe ausgelesen mit dem zaehlenden Roentgenchip MPEC 2.3

    Energy Technology Data Exchange (ETDEWEB)

    Loecker, M.

    2007-04-15

    Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 {mu}m{sup 2} pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e{sup -}). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed.

  17. Distributed Energy Resources Interconnection Systems: Technology Review and Research Needs

    Energy Technology Data Exchange (ETDEWEB)

    Friedman, N. R.

    2002-09-01

    Interconnecting distributed energy resources (DER) to the electric utility grid (or Area Electric Power System, Area EPS) involves system engineering, safety, and reliability considerations. This report documents US DOE Distribution and Interconnection R&D (formerly Distributed Power Program) activities, furthering the development and safe and reliable integration of DER interconnected with our nation's electric power systems. The key to that is system integration and technology development of the interconnection devices that perform the functions necessary to maintain the safety, power quality, and reliability of the EPS when DER are connected to it.

  18. Interconnecting with VIPs

    Science.gov (United States)

    Collins, Robert

    2013-01-01

    Interconnectedness changes lives. It can even save lives. Recently the author got to witness and be part of something in his role as a teacher of primary science that has changed lives: it may even have saved lives. It involved primary science teaching--and the climate. Robert Collins describes how it is all interconnected. The "Toilet…

  19. High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-05-01

    This final report is a compilation of final reports from each of the groups participating in the program. The main three groups involved in this effort are the Thomas J. Watson Research Center of IBM Corporation in Yorktown Heights, New York, Assembly Process Design of IBM Corporation in Endicott, New York, and SMT Laboratory of Universal Instruments Corporation in Binghamton, New York. The group at the research center focused on the conductive adhesive materials development and characterization. The group in process development focused on processing of the Polymer-Metal-Solvent Paste (PMSP) to form conductive adhesive bumps, formation of the Polymer-Metal Composite (PMC) on semiconductor devices and study of the bonding process to circuitized organic carriers, and the long term durability and reliability of joints formed using the process. The group at Universal Instruments focused on development of an equipment set and bonding parameters for the equipment to produce bond assembly tooling. Reports of each of these individual groups are presented here reviewing their technical efforts and achievements.

  20. Contacts to semiconductors

    International Nuclear Information System (INIS)

    Tove, P.A.

    1975-08-01

    Contacts to semiconductors play an important role in most semiconductor devices. These devices range from microelectronics to power components, from high-sensitivity light or radiation detectors to light-emitting of microwave-generating components. Silicon is the dominating material but compound semiconductors are increasing in importance. The following survey is an attempt to classify contact properties and the physical mechanisms involved, as well as fabrication methods and methods of investigation. The main interest is in metal-semiconductor type contacts where a few basic concepts are dealt with in some detail. (Auth.)

  1. On-chip micro-power: three-dimensional structures for micro-batteries and micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Wang, Chunlei

    2010-04-01

    With the miniaturization of portable electronic devices, there is a demand for micro-power source which can be integrated on the semiconductor chips. Various micro-batteries have been developed in recent years to generate or store the energy that is needed by microsystems. Micro-supercapacitors are also developed recently to couple with microbatteries and energy harvesting microsystems and provide the peak power. Increasing the capacity per footprint area of micro-batteries and micro-supercapacitors is a great challenge. One promising route is the manufacturing of three dimensional (3D) structures for these micro-devices. In this paper, the recent advances in fabrication of 3D structure for micro-batteries and micro-supercapacitors are briefly reviewed.

  2. 14 CFR 29.957 - Flow between interconnected tanks.

    Science.gov (United States)

    2010-01-01

    ... AIRCRAFT AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY ROTORCRAFT Powerplant Fuel System § 29.957 Flow between interconnected tanks. (a) Where tank outlets are interconnected and allow fuel to flow between them due to gravity or flight accelerations, it must be impossible for fuel to flow between tanks in...

  3. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  4. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  5. Semiconductor spintronics

    International Nuclear Information System (INIS)

    Fabian, J.; Abiague, A.M.; Ertler, Ch.; Stano, P.; Zutic, I.

    2007-01-01

    Spintronics refers commonly to phenomena in which the spin of electrons in a solid state environment plays the determining role. In a more narrow sense spintronics is an emerging research field of electronics: spintronics devices are based on a spin control of electronics, or on an electrical and optical control of spin of magnetism. While metal spintronics has already found its niche in the computer industry - giant magnetoresistance systems are used as hard disk read heads - semiconductor spintronics is vet demonstrate its full potential. This review presents selected themes of semiconductor spintronics, introducing important concepts in spin transport, spin transport, spin injection. Silsbee-Johnson spin-charge coupling, and spin-dependent tunneling, as well as spin relaxation and spin dynamics. The most fundamental spin-dependent interaction in nonmagnetic semiconductors is spin-orbit coupling. Depending on the crystal symmetries of the material, as well as on the structural properties of semiconductor based heterostructures, the spin-orbit coupling takes on different functional forms, giving a nice playground of effective spin-orbit Hamiltonians. The effective Hamiltonians for the most relevant classes of materials and heterostructures are derived here from realistic electronic band structure descriptions. Most semiconductor device systems are still theoretical concepts, waiting for experimental demonstrations. A review of selected proposed, and a few demonstrated devices is presented, with detailed description of two important classes: magnetic resonant tunnel structures and bipolar magnetic diodes and transistors. In view of the importance of ferromagnetic semiconductor material, a brief discussion of diluted magnetic semiconductors is included. In most cases the presentation is of tutorial style, introducing the essential theoretical formalism at an accessible level, with case-study-like illustrations of actual experimental results, as well as with brief

  6. Method of manufacturing a semiconductor sensor device and semiconductor sensor device

    NARCIS (Netherlands)

    2009-01-01

    The invention relates to a method of manufacturing a semiconductor sensor device (10) for sensing a substance comprising a plurality of mutually parallel mesa-shaped semiconductor regions (1) which are formed on a surface of a semiconductor body (11) and which are connected at a first end to a first

  7. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  8. Monolithic integration of microfluidic channels and semiconductor lasers

    Science.gov (United States)

    Cran-McGreehin, Simon J.; Dholakia, Kishan; Krauss, Thomas F.

    2006-08-01

    We present a fabrication method for the monolithic integration of microfluidic channels into semiconductor laser material. Lasers are designed to couple directly into the microfluidic channel, allowing submerged particles pass through the output beams of the lasers. The interaction between particles in the channel and the lasers, operated in either forward or reverse bias, allows for particle detection, and the optical forces can be used to trap and move particles. Both interrogation and manipulation are made more amenable for lab-on-a-chip applications through monolithic integration. The devices are very small, they require no external optical components, have perfect intrinsic alignment, and can be created with virtually any planar configuration of lasers in order to perform a variety of tasks. Their operation requires no optical expertise and only low electrical power, thus making them suitable for computer interfacing and automation. Insulating the pn junctions from the fluid is the key challenge, which is overcome by using photo-definable SU8-2000 polymer.

  9. Next generation space interconnect research and development in space communications

    Science.gov (United States)

    Collier, Charles Patrick

    2017-11-01

    Interconnect or "bus" is one of the critical technologies in design of spacecraft avionics systems that dictates its architecture and complexity. MIL-STD-1553B has long been used as the avionics backbone technology. As avionics systems become more and more capable and complex, however, limitations of MIL-STD-1553B such as insufficient 1 Mbps bandwidth and separability have forced current avionics architects and designers to use combination of different interconnect technologies in order to meet various requirements: CompactPCI is used for backplane interconnect; LVDS or RS422 is used for low and high-speed direct point-to-point interconnect; and some proprietary interconnect standards are designed for custom interfaces. This results in a very complicated system that consumes significant spacecraft mass and power and requires extensive resources in design, integration and testing of spacecraft systems.

  10. Semiconductor laser shearing interferometer

    International Nuclear Information System (INIS)

    Ming Hai; Li Ming; Chen Nong; Xie Jiaping

    1988-03-01

    The application of semiconductor laser on grating shearing interferometry is studied experimentally in the present paper. The method measuring the coherence of semiconductor laser beam by ion etching double frequency grating is proposed. The experimental result of lens aberration with semiconductor laser shearing interferometer is given. Talbot shearing interferometry of semiconductor laser is also described. (author). 2 refs, 9 figs

  11. Effects of PCB Pad Metal Finishes on the Cu-Pillar/Sn-Ag Micro Bump Joint Reliability of Chip-on-Board (COB) Assembly

    Science.gov (United States)

    Kim, Youngsoon; Lee, Seyong; Shin, Ji-won; Paik, Kyung-Wook

    2016-06-01

    While solder bumps have been used as the bump structure to form the interconnection during the last few decades, the continuing scaling down of devices has led to a change in the bump structure to Cu-pillar/Sn-Ag micro-bumps. Cu-pillar/Sn-Ag micro-bump interconnections differ from conventional solder bump interconnections in terms of their assembly processing and reliability. A thermo-compression bonding method with pre-applied b-stage non-conductive films has been adopted to form solder joints between Cu pillar/Sn-Ag micro bumps and printed circuit board vehicles, using various pad metal finishes. As a result, various interfacial inter-metallic compounds (IMCs) reactions and stress concentrations occur at the Cu pillar/Sn-Ag micro bumps joints. Therefore, it is necessary to investigate the influence of pad metal finishes on the structural reliability of fine pitch Cu pillar/Sn-Ag micro bumps flip chip packaging. In this study, four different pad surface finishes (Thin Ni ENEPIG, OSP, ENEPIG, ENIG) were evaluated in terms of their interconnection reliability by thermal cycle (T/C) test up to 2000 cycles at temperatures ranging from -55°C to 125°C and high-temperature storage test up to 1000 h at 150°C. The contact resistances of the Cu pillar/Sn-Ag micro bump showed significant differences after the T/C reliability test in the following order: thin Ni ENEPIG > OSP > ENEPIG where the thin Ni ENEPIG pad metal finish provided the best Cu pillar/Sn-Ag micro bump interconnection in terms of bump joint reliability. Various IMCs formed between the bump joint areas can account for the main failure mechanism.

  12. The Enhanced Segment Interconnect for FASTBUS data communications

    International Nuclear Information System (INIS)

    Machen, D.R.; Downing, R.W.; Kirsten, F.A.; Nelson, R.O.

    1987-01-01

    The Enhanced Segment Interconnect concept (ESI) for improved FASTBUS data communications is a development supported by the U.S. Department of Energy under the Small Business Innovation Research (SBIR) program. The ESI will contain both the Segment Interconnect (SI) Tyhpe S-1 and an optional buffered interconnect for store-and-forward data communications; fiber-optic-coupled serial ports will provide optional data paths. The ESI can be applied in large FASTBUS-implemented physics experiments whose data-set or data-transmission distance requirements dictate alternate approaches to data communications. This paper describes the functions of the ESI and the status of its development, now 25% complete

  13. National Offshore Wind Energy Grid Interconnection Study Executive Summary

    Energy Technology Data Exchange (ETDEWEB)

    Daniel, John P. [ABB, Inc., Cary, NC (United States); Liu, Shu [ABB, Inc., Cary, NC (United States); Ibanez, Eduardo [National Renewable Energy Lab. (NREL), Golden, CO (United States); Pennock, Ken [AWS Truepower, Albany, NY (United States); Reed, Gregory [Univ. of Pittsburgh, PA (United States); Hanes, Spencer [Duke Energy, Charlotte, NC (United States)

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States.

  14. National Offshore Wind Energy Grid Interconnection Study Full Report

    Energy Technology Data Exchange (ETDEWEB)

    Daniel, John P. [ABB, Inc., Cary, NC (United States); Liu, Shu [ABB, Inc., Cary, NC (United States); Ibanez, Eduardo [National Renewable Energy Lab. (NREL), Golden, CO (United States); Pennock, Ken [AWS Truepower, Albany, NY (United States); Reed, Gregory [Univ. of Pittsburgh, PA (United States); Hanes, Spencer [Duke Energy, Charlotte, NC (United States)

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States.

  15. The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

    Science.gov (United States)

    Choi, Edward

    Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the

  16. Cost-effective parallel optical interconnection module based on fully passive-alignment process

    Science.gov (United States)

    Son, Dong Hoon; Heo, Young Soon; Park, Hyoung-Jun; Kang, Hyun Seo; Kim, Sung Chang

    2017-11-01

    In optical interconnection technology, high-speed and large data transitions with low error rate and cost reduction are key issues for the upcoming 8K media era. The researchers present notable types of optical manufacturing structures of a four-channel parallel optical module by fully passive alignment, which are able to reduce manufacturing time and cost. Each of the components, such as vertical-cavity surface laser/positive-intrinsic negative-photodiode array, microlens array, fiber array, and receiver (RX)/transmitter (TX) integrated circuit, is integrated successfully using flip-chip bonding, die bonding, and passive alignment with a microscope. Clear eye diagrams are obtained by 25.78-Gb/s (for TX) and 25.7-Gb/s (for RX) nonreturn-to-zero signals of pseudorandom binary sequence with a pattern length of 231 to 1. The measured responsivity and minimum sensitivity of the RX are about 0.5 A/W and ≤-6.5 dBm at a bit error rate (BER) of 10-12, respectively. The optical power margin at a BER of 10-12 is 7.5 dB, and cross talk by the adjacent channel is ≤1 dB.

  17. "Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

    Directory of Open Access Journals (Sweden)

    Krohn Knut

    2008-08-01

    Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

  18. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    International Nuclear Information System (INIS)

    Ma Haifeng; Zhou Feng

    2010-01-01

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 x 320 μm 2 , which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  19. Electro-mechanical control of an on-chip optical beam splitter containing an embedded quantum emitter.

    Science.gov (United States)

    Bishop, Z K; Foster, A P; Royall, B; Bentham, C; Clarke, E; Skolnick, M S; Wilson, L R

    2018-05-01

    We demonstrate electro-mechanical control of an on-chip GaAs optical beam splitter containing a quantum dot single-photon source. The beam splitter consists of two nanobeam waveguides, which form a directional coupler (DC). The splitting ratio of the DC is controlled by varying the out-of-plane separation of the two waveguides using electromechanical actuation. We reversibly tune the beam splitter between an initial state, with emission into both output arms, and a final state with photons emitted into a single output arm. The device represents a compact and scalable tuning approach for use in III-V semiconductor integrated quantum optical circuits.

  20. Electro-mechanical control of an on-chip optical beam splitter containing an embedded quantum emitter

    Science.gov (United States)

    Bishop, Z. K.; Foster, A. P.; Royall, B.; Bentham, C.; Clarke, E.; Skolnick, M. S.; Wilson, L. R.

    2018-05-01

    We demonstrate electro-mechanical control of an on-chip GaAs optical beam splitter containing a quantum dot single-photon source. The beam splitter consists of two nanobeam waveguides, which form a directional coupler (DC). The splitting ratio of the DC is controlled by varying the out-of-plane separation of the two waveguides using electro-mechanical actuation. We reversibly tune the beam splitter between an initial state, with emission into both output arms, and a final state with photons emitted into a single output arm. The device represents a compact and scalable tuning approach for use in III-V semiconductor integrated quantum optical circuits.

  1. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  2. Characterization of semiconductor and frontier materials by nuclear microprobe technology

    International Nuclear Information System (INIS)

    Zhu Jieqing; Li Xiaolin; Yang Changyi; Lu Rongrong; Wang Jiqing; Guo Panlin

    2002-01-01

    The nuclear microprobe technology is used to characterize the properties of semiconductor and other frontier materials at the stages of their synthesis, modification, integration and application. On the basis of the beam current being used, the analytical nuclear microprobe techniques being used in this project can be divided into two categories: high beam current (PIXE, RBS, PEB) or low beam current (IBIC, STIM) techniques. The material properties measured are the thickness and composition of a composite surface on a SiC ceramic, the sputtering-induced surface segregation and depth profile change in a Ag-Cu binary alloy, the irradiation effects on the CCE of CVD diamond, the CCE profile at a polycrystalline CVD diamond film and a GaAs diode at different voltage biases and finally, the characterization of individual sample on an integrated material chip. (author)

  3. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  4. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  5. Area and Power Modeling for Networks-on-Chip with Layout Awareness

    Directory of Open Access Journals (Sweden)

    Paolo Meloni

    2007-01-01

    Full Text Available Networks-on-Chip (NoCs are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.

  6. Encapsulation of Fluidic Tubing and Microelectrodes in Microfluidic Devices: Integrating Off-Chip Process and Coupling Conventional Capillary Electrophoresis with Electrochemical Detection.

    Science.gov (United States)

    Becirovic, Vedada; Doonan, Steven R; Martin, R Scott

    2013-08-21

    In this paper, an approach to fabricate epoxy or polystyrene microdevices with encapsulated tubing and electrodes is described. Key features of this approach include a fixed alignment between the fluidic tubing and electrodes, the ability to polish the device when desired, and the low dead volume nature of the fluidic interconnects. It is shown that a variety of tubing can be encapsulated with this approach, including fused silica capillary, polyetheretherketone (PEEK), and perfluoroalkoxy (PFA), with the resulting tubing/microchip interface not leading to significant band broadening or plug dilution. The applicability of the devices with embedded tubing is demonstrated by integrating several off-chip analytical methods to the microchip. This includes droplet transfer, droplet desegmentation, and microchip-based flow injection analysis. Off-chip generated droplets can be transferred to the microchip with minimal coalescence, while flow injection studies showed improved peak shape and sensitivity when compared to the use of fluidic interconnects with an appreciable dead volume. Importantly, it is shown that this low dead volume approach can be extended to also enable the integration of conventional capillary electrophoresis (CE) with electrochemical detection. This is accomplished by embedding fused silica capillary along with palladium (for grounding the electrophoresis voltage) and platinum (for detection) electrodes. With this approach, up to 128,000 theoretical plates for dopamine was possible. In all cases, the tubing and electrodes are housed in a rigid base; this results in extremely robust devices that will be of interest to researchers wanting to develop microchips for use by non-experts.

  7. Crossing the Resolution Limit in Near-Infrared Imaging of Silicon Chips: Targeting 10-nm Node Technology

    Directory of Open Access Journals (Sweden)

    Krishna Agarwal

    2015-05-01

    Full Text Available The best reported resolution in optical failure analysis of silicon chips is 120-nm half pitch demonstrated by Semicaps Private Limited, whereas the current and future industry requirement for 10-nm node technology is 100-nm half pitch. We show the first experimental evidence for resolution of features with 100-nm half pitch buried in silicon (λ/10.6, thus fulfilling the industry requirement. These results are obtained using near-infrared reflection-mode imaging using a solid immersion lens. The key novel feature of our approach is the choice of an appropriately sized collection pinhole. Although it is usually understood that, in general, resolution is improved by using the smallest pinhole consistent with an adequate signal level, it is found that in practice for silicon chips there is an optimum pinhole size, determined by the generation of induced currents in the sample. In failure analysis of silicon chips, nondestructive imaging is important to avoid disturbing the functionality of integrated circuits. High-resolution imaging techniques like SEM or TEM require the transistors to be exposed destructively. Optical microscopy techniques may be used, but silicon is opaque in the visible spectrum, mandating the use of near-infrared light and thus poor resolution in conventional optical microscopy. We expect our result to change the way semiconductor failure analysis is performed.

  8. Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

    Science.gov (United States)

    Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

    2006-01-01

    We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

  9. Optics vs copper: from the perspective of "Thunderbolt" interconnect technology

    Science.gov (United States)

    Cheng, Hengju; Krause, Christine; Ko, Jamyuen; Gao, Miaobin; Liu, Guobin; Wu, Huichin; Qi, Mike; Lam, Chun-Chit

    2013-02-01

    Interconnect technology has been progressed at a very fast pace for the past decade. The signaling rates have steadily increased from 100:Mb/s to 25Gb/s. In every generation of interconnect technology evolution, optics always seems to take over at first, however, at the end, the cost advantage of copper wins over. Because of this, optical interconnects are limited to longer distance links where the attenuation in copper cable is too large for the integrated circuits to compensate. Optical interconnect has long been viewed as the premier solution in compared with copper interconnect. With the release of Thunderbolt technology, we are entering a new era in consumer electronics that runs at 10Gb/s line rate (20Gb/s throughput per connector interface). Thunderbolt interconnect technology includes both active copper cables and active optical cables as the transmission media which have very different physical characteristics. In order for optics to succeed in consumer electronics, several technology hurdles need to be cleared. For example, the optical cable needs to handle the consumer abuses such as pinch and bend. Also, the optical engine used in the active optical cable needs to be physically very small so that we don't change the looks and feels of the cable/connector. Most importantly, the cost of optics needs to come down significantly to effectively compete with the copper solution. Two interconnect technologies are compared and discussed on the relative cost, power consumption, form factor, density, and future scalability.

  10. Fusion-bonded fluidic interconnects

    NARCIS (Netherlands)

    Fazal, I.; Elwenspoek, Michael Curt

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are

  11. Chip-by-chip configurable interconnection using digital printing techniques

    International Nuclear Information System (INIS)

    Mashayekhi, Mohammad; Carrabina, Jordi; Winchester, Lee; Laurila, Mika-Matti; Mäntysalo, Matti; Ogier, Simon; Terés, Lluís

    2017-01-01

    Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. (paper)

  12. All-zigzag graphene nanoribbons for planar interconnect application

    Science.gov (United States)

    Chen, Po-An; Chiang, Meng-Hsueh; Hsu, Wei-Chou

    2017-07-01

    A feasible "lightning-shaped" zigzag graphene nanoribbon (ZGNR) structure for planar interconnects is proposed. Based on the density functional theory and non-equilibrium Green's function, the electron transport properties are evaluated. The lightning-shaped structure increases significantly the conductance of the graphene interconnect with an odd number of zigzag chains. This proposed technique can effectively utilize the linear I-V characteristic of asymmetric ZGNRs for interconnect application. Variability study accounting for width/length variation and the edge effect is also included. The transmission spectra, transmission eigenstates, and transmission pathways are analyzed to gain the physical insights. This lightning-shaped ZGNR enables all 2D material-based devices and circuits on flexible and transparent substrates.

  13. Monolithic Inorganic ZnO/GaN Semiconductors Heterojunction White Light-Emitting Diodes.

    Science.gov (United States)

    Jeong, Seonghoon; Oh, Seung Kyu; Ryou, Jae-Hyun; Ahn, Kwang-Soon; Song, Keun Man; Kim, Hyunsoo

    2018-01-31

    Monolithic light-emitting diodes (LEDs) that can generate white color at the one-chip level without the wavelength conversion through packaged phosphors or chip integration for photon recycling are of particular importance to produce compact, cost-competitive, and smart lighting sources. In this study, monolithic white LEDs were developed based on ZnO/GaN semiconductor heterojunctions. The electroluminescence (EL) wavelength of the ZnO/GaN heterojunction could be tuned by a post-thermal annealing process, causing the generation of an interfacial Ga 2 O 3 layer. Ultraviolet, violet-bluish, and greenish-yellow broad bands were observed from n-ZnO/p-GaN without an interfacial layer, whereas a strong greenish-yellow band emission was the only one observed from that with an interfacial layer. By controlled integration of ZnO/GaN heterojunctions with different postannealing conditions, monolithic white LED was demonstrated with color coordinates in the range (0.3534, 0.3710)-(0.4197, 0.4080) and color temperatures of 4778-3349 K in the Commission Internationale de l'Eclairage 1931 chromaticity diagram. Furthermore, the monolithic white LED produced approximately 2.1 times higher optical output power than a conventional ZnO/GaN heterojunction due to the carrier confinement effect at the Ga 2 O 3 /n-ZnO interface.

  14. Photo-response of a P3HT:PCBM blend in metal-insulator-semiconductor capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Devynck, M.; Rostirolla, B.; Watson, C. P.; Taylor, D. M., E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom)

    2014-11-03

    Metal-insulator-semiconductor capacitors are investigated, in which the insulator is cross-linked polyvinylphenol and the active layer a blend of poly(3-hexylthiophene), P3HT, and the electron acceptor [6,6]-phenyl-C{sub 61}-butyric acid methyl ester (PCBM). Admittance spectra and capacitance-voltage measurements obtained in the dark both display similar behaviour to those previously observed in P3HT-only devices. However, the photo-capacitance response is significantly enhanced in the P3HT:PCBM case, where exciton dissociation leads to electron transfer into the PCBM component. The results are consistent with a network of PCBM aggregates that is continuous through the film but with no lateral interconnection between the aggregates at or near the blend/insulator interface.

  15. Optical interconnect for large-scale systems

    Science.gov (United States)

    Dress, William

    2013-02-01

    This paper presents a switchless, optical interconnect module that serves as a node in a network of identical distribution modules for large-scale systems. Thousands to millions of hosts or endpoints may be interconnected by a network of such modules, avoiding the need for multi-level switches. Several common network topologies are reviewed and their scaling properties assessed. The concept of message-flow routing is discussed in conjunction with the unique properties enabled by the optical distribution module where it is shown how top-down software control (global routing tables, spanning-tree algorithms) may be avoided.

  16. The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

    Science.gov (United States)

    Nikolova, Silviya; Stearns, Sally

    2014-03-03

    Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

  17. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  18. Développement d'architectures HW/SW tolérantes aux fautes et auto-calibrantes pour les technologies Intégrées 3D

    OpenAIRE

    Pasca , Vladimir

    2013-01-01

    3D technology promises energy-efficient heterogeneous integrated systems, which may open the way to thousands cores chips. Silicon dies containing processing elements are stacked and connected by vertical wires called Through-Silicon-Vias. In 3D chips, interconnecting an increasing number of processing elements requires a scalable high-performance interconnect solution: the 3D Network-on-Chip. Despite the advantages of 3D integration, testing, reliability and yield remain the major challenges...

  19. Microeconomics of process control in semiconductor manufacturing

    Science.gov (United States)

    Monahan, Kevin M.

    2003-06-01

    Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

  20. Electronic properties of semiconductor heterostructures

    International Nuclear Information System (INIS)

    Einevoll, G.T.

    1991-02-01

    Ten papers on the electronic properties of semiconductors and semiconductor heterostructures constitute the backbone of this thesis. Four papers address the form and validity of the single-band effective mass approximation for semiconductor heterostructures. In four other papers properties of acceptor states in bulk semiconductors and semiconductor heterostructures are studied using the novel effective bond-orbital model. The last two papers deal with localized excitions. 122 refs

  1. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  2. Organic semiconductor crystals.

    Science.gov (United States)

    Wang, Chengliang; Dong, Huanli; Jiang, Lang; Hu, Wenping

    2018-01-22

    Organic semiconductors have attracted a lot of attention since the discovery of highly doped conductive polymers, due to the potential application in field-effect transistors (OFETs), light-emitting diodes (OLEDs) and photovoltaic cells (OPVs). Single crystals of organic semiconductors are particularly intriguing because they are free of grain boundaries and have long-range periodic order as well as minimal traps and defects. Hence, organic semiconductor crystals provide a powerful tool for revealing the intrinsic properties, examining the structure-property relationships, demonstrating the important factors for high performance devices and uncovering fundamental physics in organic semiconductors. This review provides a comprehensive overview of the molecular packing, morphology and charge transport features of organic semiconductor crystals, the control of crystallization for achieving high quality crystals and the device physics in the three main applications. We hope that this comprehensive summary can give a clear picture of the state-of-art status and guide future work in this area.

  3. Opto-Electronic and Interconnects Hierarchical Design Automation System (OE-IDEAS)

    National Research Council Canada - National Science Library

    Turowski, M

    2004-01-01

    As microelectronics technology continues to advance, the associated electrical interconnection technology is not likely to keep pace, due to many parasitic effects appearing in metallic interconnections...

  4. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  5. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  6. Compact semiconductor lasers

    CERN Document Server

    Yu, Siyuan; Lourtioz, Jean-Michel

    2014-01-01

    This book brings together in a single volume a unique contribution by the top experts around the world in the field of compact semiconductor lasers to provide a comprehensive description and analysis of the current status as well as future directions in the field of micro- and nano-scale semiconductor lasers. It is organized according to the various forms of micro- or nano-laser cavity configurations with each chapter discussing key technical issues, including semiconductor carrier recombination processes and optical gain dynamics, photonic confinement behavior and output coupling mechanisms, carrier transport considerations relevant to the injection process, and emission mode control. Required reading for those working in and researching the area of semiconductors lasers and micro-electronics.

  7. A model-based prognostic approach to predict interconnect failure using impedance analysis

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Dae Il; Yoon, Jeong Ah [Dept. of System Design and Control Engineering. Ulsan National Institute of Science and Technology, Ulsan (Korea, Republic of)

    2016-10-15

    The reliability of electronic assemblies is largely affected by the health of interconnects, such as solder joints, which provide mechanical, electrical and thermal connections between circuit components. During field lifecycle conditions, interconnects are often subjected to a DC open circuit, one of the most common interconnect failure modes, due to cracking. An interconnect damaged by cracking is sometimes extremely hard to detect when it is a part of a daisy-chain structure, neighboring with other healthy interconnects that have not yet cracked. This cracked interconnect may seem to provide a good electrical contact due to the compressive load applied by the neighboring healthy interconnects, but it can cause the occasional loss of electrical continuity under operational and environmental loading conditions in field applications. Thus, cracked interconnects can lead to the intermittent failure of electronic assemblies and eventually to permanent failure of the product or the system. This paper introduces a model-based prognostic approach to quantitatively detect and predict interconnect failure using impedance analysis and particle filtering. Impedance analysis was previously reported as a sensitive means of detecting incipient changes at the surface of interconnects, such as cracking, based on the continuous monitoring of RF impedance. To predict the time to failure, particle filtering was used as a prognostic approach using the Paris model to address the fatigue crack growth. To validate this approach, mechanical fatigue tests were conducted with continuous monitoring of RF impedance while degrading the solder joints under test due to fatigue cracking. The test results showed the RF impedance consistently increased as the solder joints were degraded due to the growth of cracks, and particle filtering predicted the time to failure of the interconnects similarly to their actual timesto- failure based on the early sensitivity of RF impedance.

  8. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  9. Experiment list: SRX122465 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

  10. Fermi level dependent native defect formation: Consequences for metal-semiconductor and semiconductor-semiconductor interfaces

    International Nuclear Information System (INIS)

    Walukiewicz, W.

    1988-02-01

    The amphoteric native defect model of the Schottky barrier formation is used to analyze the Fermi level pinning at metal/semiconductor interfaces for submonolayer metal coverages. It is assumed that the energy required for defect generation is released in the process of surface back-relaxation. Model calculations for metal/GaAs interfaces show a weak dependence of the Fermi level pinning on the thickness of metal deposited at room temperature. This weak dependence indicates a strong dependence of the defect formation energy on the Fermi level, a unique feature of amphoteric native defects. This result is in very good agreement with experimental data. It is shown that a very distinct asymmetry in the Fermi level pinning on p- and n-type GaAs observed at liquid nitrogen temperatures can be understood in terms of much different recombination rates for amphoteric native defects in those two types of materials. Also, it is demonstrated that the Fermi level stabilization energy, a central concept of the amphoteric defect system, plays a fundamental role in other phenomena in semiconductors such as semiconductor/semiconductor heterointerface intermixing and saturation of free carrier concentration. 33 refs., 6 figs

  11. Semiconductor spintronics

    CERN Document Server

    Xia, Jianbai; Chang, Kai

    2012-01-01

    Semiconductor Spintronics, as an emerging research discipline and an important advanced field in physics, has developed quickly and obtained fruitful results in recent decades. This volume is the first monograph summarizing the physical foundation and the experimental results obtained in this field. With the culmination of the authors' extensive working experiences, this book presents the developing history of semiconductor spintronics, its basic concepts and theories, experimental results, and the prospected future development. This unique book intends to provide a systematic and modern foundation for semiconductor spintronics aimed at researchers, professors, post-doctorates, and graduate students, and to help them master the overall knowledge of spintronics.

  12. Experiment list: SRX122555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip anti...body catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-7

  13. Method of doping a semiconductor

    International Nuclear Information System (INIS)

    Yang, C.Y.; Rapp, R.A.

    1983-01-01

    A method is disclosed for doping semiconductor material. An interface is established between a solid electrolyte and a semiconductor to be doped. The electrolyte is chosen to be an ionic conductor of the selected impurity and the semiconductor material and electrolyte are jointly chosen so that any compound formed from the impurity and the semiconductor will have a free energy no lower than the electrolyte. A potential is then established across the interface so as to allow the impurity ions to diffuse into the semiconductor. In one embodiment the semiconductor and electrolyte may be heated so as to increase the diffusion coefficient

  14. Stability Analysis of Interconnected Fuzzy Systems Using the Fuzzy Lyapunov Method

    Directory of Open Access Journals (Sweden)

    Ken Yeh

    2010-01-01

    Full Text Available The fuzzy Lyapunov method is investigated for use with a class of interconnected fuzzy systems. The interconnected fuzzy systems consist of J interconnected fuzzy subsystems, and the stability analysis is based on Lyapunov functions. Based on traditional Lyapunov stability theory, we further propose a fuzzy Lyapunov method for the stability analysis of interconnected fuzzy systems. The fuzzy Lyapunov function is defined in fuzzy blending quadratic Lyapunov functions. Some stability conditions are derived through the use of fuzzy Lyapunov functions to ensure that the interconnected fuzzy systems are asymptotically stable. Common solutions can be obtained by solving a set of linear matrix inequalities (LMIs that are numerically feasible. Finally, simulations are performed in order to verify the effectiveness of the proposed stability conditions in this paper.

  15. 75 FR 40815 - PJM Interconnection, L.L.C.; Notice of Filing

    Science.gov (United States)

    2010-07-14

    ... Interconnection, L.L.C.; Notice of Filing July 7, 2010. Take notice that on July 1, 2010, PJM Interconnection, L.L.C. (PJM) filed revised sheets to Schedule 1 of the Amended and Restated Operating Agreement of PJM Interconnection, L.L.C. (Operating Agreement) and the parallel provisions of Attachment K--Appendix of the PJM...

  16. 75 FR 22773 - PJM Interconnection, L.L.C.; Notice of Filing

    Science.gov (United States)

    2010-04-30

    ... Interconnection, L.L.C.; Notice of Filing April 23, 2010. Take notice that on April 22, 2010, PJM Interconnection, L.L.C. (PJM) filed revised tariff sheets to its Schedule 1 of the Amended and Restated Operating... (Commission) March 23, 2010 Order on Compliance Filing, PJM Interconnection, L.L.C., 130 FERC ] 61,230 (2010...

  17. 77 FR 34378 - PJM Interconnection, L.L.C.; Notice of Complaint

    Science.gov (United States)

    2012-06-11

    ... Interconnection, L.L.C.; Notice of Complaint Take notice that on June 1, 2012, pursuant to section 206 of the Federal Power Act (FPA), 16 U.S.C. 824(e), PJM Interconnection, L.L.C. (PJM) filed proposed revisions to the Amended and Restated Operating Agreement of PJM Interconnection L.L.C. (Operating Agreement) to...

  18. Novel room temperature ferromagnetic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Gupta, Amita [KTH Royal Inst. of Technology, Stockholm (Sweden)

    2004-06-01

    Today's information world, bits of data are processed by semiconductor chips, and stored in the magnetic disk drives. But tomorrow's information technology may see magnetism (spin) and semiconductivity (charge) combined in one 'spintronic' device that exploits both charge and 'spin' to carry data (the best of two worlds). Spintronic devices such as spin valve transistors, spin light emitting diodes, non-volatile memory, logic devices, optical isolators and ultra-fast optical switches are some of the areas of interest for introducing the ferromagnetic properties at room temperature in a semiconductor to make it multifunctional. The potential advantages of such spintronic devices will be higher speed, greater efficiency, and better stability at a reduced power consumption. This Thesis contains two main topics: In-depth understanding of magnetism in Mn doped ZnO, and our search and identification of at least six new above room temperature ferromagnetic semiconductors. Both complex doped ZnO based new materials, as well as a number of nonoxides like phosphides, and sulfides suitably doped with Mn or Cu are shown to give rise to ferromagnetism above room temperature. Some of the highlights of this work are discovery of room temperature ferromagnetism in: (1) ZnO:Mn (paper in Nature Materials, Oct issue, 2003); (2) ZnO doped with Cu (containing no magnetic elements in it); (3) GaP doped with Cu (again containing no magnetic elements in it); (4) Enhancement of Magnetization by Cu co-doping in ZnO:Mn; (5) CdS doped with Mn, and a few others not reported in this thesis. We discuss in detail the first observation of ferromagnetism above room temperature in the form of powder, bulk pellets, in 2-3 mu-m thick transparent pulsed laser deposited films of the Mn (<4 at. percent) doped ZnO. High-resolution transmission electron microscopy (HRTEM) and electron energy loss spectroscopy (EELS) spectra recorded from 2 to 200nm areas showed homogeneous

  19. LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

    International Nuclear Information System (INIS)

    Heijne, E.H.M.; Antinori, F.; Barberis, D.

    1996-01-01

    The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

  20. Welfare and competition effects of electricity interconnection between Ireland and Great Britain

    International Nuclear Information System (INIS)

    Malaguzzi Valeri, Laura

    2009-01-01

    This study analyzes the effects of additional interconnection on welfare and competition in the Irish electricity market. I simulate the wholesale electricity markets of the island of Ireland and Great Britain for 2005. I find that in order for the two markets to be integrated in 2005, additional interconnection would have to be large. The amount of interconnection decreases for high costs of carbon, since this causes the markets to become more similar. This suggests that in the absence of strategic behavior of firms, most of the gains from trade derive not from differences in size between countries, but from technology differences and are strongly influenced by fuel and carbon costs. Social welfare increases with interconnection, although at a decreasing rate. As the amount of interconnection increases, there are also positive effects on competition in Ireland, the less competitive of the two markets. Finally, it is unlikely that private investors will pay for the optimal amount of interconnection since their returns are significantly smaller than the total social benefit of interconnection. (author)

  1. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-15

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

  2. Supply systems of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-01

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

  3. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

    2009-07-01

    The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

  4. On-demand semiconductor single-photon source with near-unity indistinguishability.

    Science.gov (United States)

    He, Yu-Ming; He, Yu; Wei, Yu-Jia; Wu, Dian; Atatüre, Mete; Schneider, Christian; Höfling, Sven; Kamp, Martin; Lu, Chao-Yang; Pan, Jian-Wei

    2013-03-01

    Single-photon sources based on semiconductor quantum dots offer distinct advantages for quantum information, including a scalable solid-state platform, ultrabrightness and interconnectivity with matter qubits. A key prerequisite for their use in optical quantum computing and solid-state networks is a high level of efficiency and indistinguishability. Pulsed resonance fluorescence has been anticipated as the optimum condition for the deterministic generation of high-quality photons with vanishing effects of dephasing. Here, we generate pulsed single photons on demand from a single, microcavity-embedded quantum dot under s-shell excitation with 3 ps laser pulses. The π pulse-excited resonance-fluorescence photons have less than 0.3% background contribution and a vanishing two-photon emission probability. Non-postselective Hong-Ou-Mandel interference between two successively emitted photons is observed with a visibility of 0.97(2), comparable to trapped atoms and ions. Two single photons are further used to implement a high-fidelity quantum controlled-NOT gate.

  5. Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

    Directory of Open Access Journals (Sweden)

    Huei Chaeng Chin

    2014-01-01

    Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

  6. Interconnection network architectures based on integrated orbital angular momentum emitters

    Science.gov (United States)

    Scaffardi, Mirco; Zhang, Ning; Malik, Muhammad Nouman; Lazzeri, Emma; Klitis, Charalambos; Lavery, Martin; Sorel, Marc; Bogoni, Antonella

    2018-02-01

    Novel architectures for two-layer interconnection networks based on concentric OAM emitters are presented. A scalability analysis is done in terms of devices characteristics, power budget and optical signal to noise ratio by exploiting experimentally measured parameters. The analysis shows that by exploiting optical amplifications, the proposed interconnection networks can support a number of ports higher than 100. The OAM crosstalk induced-penalty, evaluated through an experimental characterization, do not significantly affect the interconnection network performance.

  7. High-Temperature, Wirebondless, Ultracompact Wide Bandgap Power Semiconductor Modules

    Science.gov (United States)

    Elmes, John

    2015-01-01

    Silicon carbide (SiC) and other wide bandgap semiconductors offer great promise of high power rating, high operating temperature, simple thermal management, and ultrahigh power density for both space and commercial power electronic systems. However, this great potential is seriously limited by the lack of reliable high-temperature device packaging technology. This Phase II project developed an ultracompact hybrid power module packaging technology based on the use of double lead frames and direct lead frame-to-chip transient liquid phase (TLP) bonding that allows device operation up to 450 degC. The new power module will have a very small form factor with 3-5X reduction in size and weight from the prior art, and it will be capable of operating from 450 degC to -125 degC. This technology will have a profound impact on power electronics and energy conversion technologies and help to conserve energy and the environment as well as reduce the nation's dependence on fossil fuels.

  8. 76 FR 16405 - Notice of Attendance at PJM INterconnection, L.L.C., Meetings

    Science.gov (United States)

    2011-03-23

    ... INterconnection, L.L.C., Meetings The Federal Energy Regulatory Commission (Commission) hereby gives notice that members of the Commission and Commission staff may attend upcoming PJM Interconnection, L.L.C., (PJM...: Docket No. EL05-121, PJM Interconnection, L.L.C. Docket No. ER06-456, PJM Interconnection, L.L.C. Docket...

  9. Time Domain Analysis of Graphene Nanoribbon Interconnects Based on Transmission Line ‎Model

    Directory of Open Access Journals (Sweden)

    S. Haji Nasiri

    2012-03-01

    Full Text Available Time domain analysis of multilayer graphene nanoribbon (MLGNR interconnects, based on ‎transmission line modeling (TLM using a six-order linear parametric expression, has been ‎presented for the first time. We have studied the effects of interconnect geometry along with ‎its contact resistance on its step response and Nyquist stability. It is shown that by increasing ‎interconnects dimensions their propagation delays are increased and accordingly the system ‎becomes relatively more stable. In addition, we have compared time responses and Nyquist ‎stabilities of MLGNR and SWCNT bundle interconnects, with the same external dimensions. ‎The results show that under the same conditions, the propagation delays for MLGNR ‎interconnects are smaller than those of SWCNT bundle interconnects are. Hence, SWCNT ‎bundle interconnects are relatively more stable than their MLGNR rivals.‎

  10. Assessment of on-farm anaerobic digester grid interconnections

    International Nuclear Information System (INIS)

    Ruhnke, W.

    2006-01-01

    While several anaerobic digestion (AD) pilot plants have recently been built in Canada, early reports suggest that interconnection barriers are delaying their widescale implementation. This paper examined grid interconnection experiences from the perspectives of farmers, local distributing companies (LDCs) and other stakeholders. The aim of the paper was to identify challenges to the implementation of AD systems. Case studies included an Ontario Dairy Herd AD system generating 50 kW; a Saskatchewan hog farm AD system generating 120 kW and an Alberta outdoor beef feedlot AD system generating 1000 kW. Two survey forms were created for project operators, and LDCs. The following 3 category barriers were identified: (1) technical concerns over islanding conditions, power quality requirements, power flow studies and other engineering analyses; (2) business practices barriers such as a lack of response after initial utility contact; and (3) regulatory barriers including the unavailability of fair buy-back rates, the lack of net metering programs, restrictive net metering programs, and pricing issues. It was suggested that collaborative efforts among all stakeholders are needed to resolve barriers quickly. Recommendations included the adoption of uniform technical standards for connecting generators to the grid, as well as adopting standard commercial practices for any required LDC interconnection review. It was also suggested that standard business terms for interconnection agreements should be established. Regulatory principles should be compatible with distributed power choices in regulated and unregulated markets. It was concluded that resolving interconnection barriers is a critical step towards realizing market opportunities available for AD technologies. refs., tabs., figs

  11. Fully Printed Flexible Single-Chip RFID Tag with Light Detection Capabilities

    Directory of Open Access Journals (Sweden)

    Aniello Falco

    2017-03-01

    Full Text Available A printed passive radiofrequency identification (RFID tag in the ultra-high frequency band for light and temperature monitoring is presented. The whole tag has been manufactured by printing techniques on a flexible substrate. Antenna and interconnects are realized with silver nanoparticles via inkjet printing. A sprayed photodetector performs the light monitoring, whereas temperature measurement comes from an in-built sensor in the silicon RFID chip. One of the advantages of this system is the digital read-out and transmission of the sensors information on the RFID tag that ensures reliability. Furthermore, the use of printing techniques allows large-scale manufacturing and the direct fabrication of the tag on the desired surface. This work proves for the first time the feasibility of the embedment of large-scale organic photodetectors onto inkjet printed RFID tags. Here, we solve the problem of integration of different manufacturing techniques to develop an optimal final sensor system.

  12. Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

    DEFF Research Database (Denmark)

    Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly

    2016-01-01

    -pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz...... was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA(1/2), which is superior among microcavity lasers. This shows a high potential for a very high speed at low......For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have...

  13. Single chip camera active pixel sensor

    Science.gov (United States)

    Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

    2003-01-01

    A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

  14. Electromagnetism and interconnections

    CERN Document Server

    Charruau, S

    2009-01-01

    This book covers the theoretical problems of modeling electrical behavior of the interconnections encountered in everyday electronic products. The coverage shows the theoretical tools of waveform prediction at work in the design of a complex and high-speed digital electronic system. Scientists, research engineers, and postgraduate students interested in electromagnetism, microwave theory, electrical engineering, or the development of simulation tools software for high speed electronic system design automation will find this book an illuminating resource.

  15. Interface analysis of embedded chip resistor device package and its effect on drop shock reliability.

    Science.gov (United States)

    Park, Se-Hoon; Kim, Sun Kyoung; Kim, Young-Ho

    2012-04-01

    In this study, the drop reliability of an embedded passive package is investigated under JESD22-B111 condition. Chip resistors were buried in a PCB board, and it was electrically interconnected by electroless and electrolytic copper plating on a tin pad of a chip resistor without intermetallic phase. However tin, nickel, and copper formed a complex intermetallic phase, such as (Cu, Ni)6Sn5, (Cu, Ni)3Sn, and (Ni, Cu)3Sn2, at the via interface and via wall after reflow and aging. Since the amount of the tin layer was small compared with the solder joint, excessive intermetallic layer growth was not observed during thermal aging. Drop failures are always initiated at the IMC interface, and as aging time increases Cu-Sn-Ni IMC phases are transformed continuously due to Cu diffusion. We studied the intermetallic formation of the Cu via interface and simulated the stress distribution of drop shock by using material properties and board structure of embedded passive boards. The drop simulation was conducted according to the JEDEC standard. It was revealed that the crack starting point related to failure fracture changed due to intermetallic phase transformation along the via interface, and the position where failure occurs experimentally agrees well with our simulation results.

  16. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  17. An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

    Science.gov (United States)

    Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

    2001-11-01

    The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

  18. Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2012-01-01

    Full Text Available Two multiprocessor system-on-chip (MPSoC architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

  19. Electronic interconnects and devices with topological surface states and methods for fabricating same

    Science.gov (United States)

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2016-05-03

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  20. Electronic interconnects and devices with topological surface states and methods for fabricating same

    Energy Technology Data Exchange (ETDEWEB)

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2017-04-04

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.