WorldWideScience

Sample records for semiconductor chip interconnects

  1. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  2. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  3. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  4. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  5. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  6. Green interconnecting materials for semiconductor industry

    NARCIS (Netherlands)

    Matin, M.A.; Vellinga, W.P.; Geers, M.G.D.; Sawada, K.; Ishida, M.

    2009-01-01

    Interconnecting materials experience a complex thermo-mechanical load in applications. This may lead to the formation of macroscopic cracks resulting from induced stresses of the differences in thermal expansion coefficients on a sample scale (since different materials are involved) and on a grain

  7. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    Science.gov (United States)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

  8. Chip-Level Electromigration Reliability for Cu Interconnects

    International Nuclear Information System (INIS)

    Gall, M.; Oh, C.; Grinshpon, A.; Zolotov, V.; Panda, R.; Demircan, E.; Mueller, J.; Justison, P.; Ramakrishna, K.; Thrasher, S.; Hernandez, R.; Herrick, M.; Fox, R.; Boeck, B.; Kawasaki, H.; Haznedar, H.; Ku, P.

    2004-01-01

    Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The traditional method of verifying EM reliability only through current density limit checks is proving to be inadequate in general, or quite expensive at the best. A Statistical EM Budgeting (SEB) methodology has been proposed to assess more realistic chip-level EM reliability from the complex statistical distribution of currents in a chip. To be valuable, this approach requires accurate estimation of currents for all interconnect segments in a chip. However, no efficient technique to manage the complexity of such a task for very large chip designs is known. We present an efficient method to estimate currents exhaustively for all interconnects in a chip. The proposed method uses pre-characterization of cells and macros, and steps to identify and filter out symmetrically bi-directional interconnects. We illustrate the strength of the proposed approach using a high-performance microprocessor design for embedded applications as a case study

  9. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  10. Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

    Science.gov (United States)

    Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

    2008-02-01

    We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

  11. Global On-Chip Differential Interconnects with Optimally-Placed Twists

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2005-01-01

    Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects

  12. Hot Chips and Hot Interconnects for High End Computing Systems

    Science.gov (United States)

    Saini, Subhash

    2005-01-01

    I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

  13. Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

    Science.gov (United States)

    King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

    1998-04-01

    We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

  14. Simple and reusable fibre-to-chip interconnect with adjustable coupling eficiency

    NARCIS (Netherlands)

    Heideman, Rene; Lambeck, Paul; Parriaux, Olivier M.; Kley, Ernst-Bernhard

    1997-01-01

    A simple, efficient and reusable fiber-to-chip interconnect is presented. The interconnect is based on a V-groove (wet- chemically etched) in silicon, combined with a loose-mode Si3N4-channel waveguide. The loose-mode waveguide is adiabatically tapered to the integrated optical (sensor) circuitry.

  15. One-step fabrication of microfluidic chips with in-plane, adhesive-free interconnections

    International Nuclear Information System (INIS)

    Sabourin, D; Dufva, M; Jensen, T; Kutter, J; Snakenborg, D

    2010-01-01

    A simple method for creating interconnections to a common microfluidic device material, poly(methyl methacrylate) (PMMA), is presented. A press-fit interconnection is created between oversized, deformable tubing and complementary, undersized semi-circular ports fabricated into PMMA bonding surfaces by direct micromilling. Upon UV-assisted bonding the tubing is trapped in the ports of the PMMA chip and forms an integrated, in-plane and adhesive-free interconnection. The interconnections support the average pressure of 6.1 bar and can be made with small dead volumes. A comparison is made to a similar interconnection approach which uses tubing to act as a gasket between a needle and port on the microfluidic chip. (technical note)

  16. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  17. 76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

    Science.gov (United States)

    2011-12-21

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With... importation, and the sale within the United States after importation of certain semiconductor chips with DRAM.... 7,906,809 (``the `809 patent''). The complaint further alleges that an industry in the United States...

  18. Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

    CERN Document Server

    Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

    2014-01-01

    In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

  19. Structural characteristics of carbon nanofibers for on-chip interconnect applications

    International Nuclear Information System (INIS)

    Ominami, Yusuke; Ngo, Quoc; Austin, Alexander J.; Yoong, Hans; Yang, Cary Y.; Cassell, Alan M.; Cruden, Brett A.; Li Jun; Meyyappan, M.

    2005-01-01

    In this letter, we compare the structures of plasma-enhanced chemical vapor deposition of Ni-catalyzed and Pd-catalyzed carbon nanofibers (CNFs) synthesized for on-chip interconnect applications with scanning transmission electron microscopy (STEM). The Ni-catalyzed CNF has a conventional fiberlike structure and many graphitic layers that are almost parallel to the substrate at the CNF base. In contrast, the Pd-catalyzed CNF has a multiwall nanotubelike structure on the sidewall spanning the entire CNF. The microstructure observed in the Pd-catalyzed fibers at the CNF-metal interface has the potential to lower contact resistance significantly, as our electrical measurements using current-sensing atomic force microscopy indicate. A structural model is presented based on STEM image analysis

  20. Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

    Science.gov (United States)

    Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

    2015-11-01

    Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

  1. A 3Gb/s/ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects

    NARCIS (Netherlands)

    Schinkel, Daniel; Mensink, E.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2006-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the

  2. Where the chips fall: environmental health in the semiconductor industry.

    Science.gov (United States)

    Chepesiuk, R

    1999-09-01

    Three recent lawsuits are focusing public attention on the environmental and occupational health effects of the world's largest and fastest growing manufacturing sector-the $150 billion semiconductor industry. The suits allege that exposure to toxic chemicals in semiconductor manufacturing plants led to adverse health effects such as miscarriage and cancer among workers. To manufacture computer components, the semiconductor industry uses large amounts of hazardous chemicals including hydrochloric acid, toxic metals and gases, and volatile solvents. Little is known about the long-term health consequences of exposure to chemicals by semiconductor workers. According to industry critics, the semiconductor industry also adversely impacts the environment, causing groundwater and air pollution and generating toxic waste as a by-product of the semiconductor manufacturing process. In contrast, the U.S. Bureau of Statistics shows the semiconductor industry as having a worker illness rate of about one-third of the average of all manufacturers, and advocates defend the industry, pointing to recent research collaborations and product replacement as proof that semiconductor manufacturers adequately protect both their employees and the environment.

  3. Lab-on-a-chip for label free biological semiconductor analysis of Staphylococcal Enterotoxin B

    NARCIS (Netherlands)

    Yang, Minghui; Sun, Steven; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

    2010-01-01

    We describe a new lab-on-a-chip (LOC) which utilizes a biological semiconductor (BSC) transducer for label free analysis of Staphylococcal Enterotoxin B (SEB) (or other biological interactions) directly and electronically. BSCs are new transducers based on electrical percolation through a

  4. All-polymer organic semiconductor laser chips: Parallel fabrication and encapsulation

    DEFF Research Database (Denmark)

    Vannahme, Christoph; Klinkhammer, Sönke; Christiansen, Mads Brøkner

    2010-01-01

    Organic semiconductor lasers are of particular interest as tunable visible laser light sources. For bringing those to market encapsulation is needed to ensure practicable lifetimes. Additionally, fabrication technologies suitable for mass production must be used. We introduce all-polymer chips...... comprising encapsulated distributed feedback organic semiconductor lasers. Several chips are fabricated in parallel by thermal nanoimprint of the feedback grating on 4? wafer scale out of poly(methyl methacrylate) (PMMA) and cyclic olefin copolymer (COC). The lasers consisting of the organic semiconductor...... tris(8- hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2- methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM) are hermetically sealed by thermally bonding a polymer lid. The organic thin film is placed in a basin within the substrate and is not in direct contact to the lid...

  5. Impact of Isothermal Aging and Testing Temperature on Large Flip-Chip BGA Interconnect Mechanical Shock Performance

    Science.gov (United States)

    Lee, Tae-Kyu; Chen, Zhiqiang; Guirguis, Cherif; Akinade, Kola

    2017-10-01

    The stability of solder interconnects in a mechanical shock environment is crucial for large body size flip-chip ball grid array (FCBGA) electronic packages. Additionally, the junction temperature increases with higher electric power condition, which brings the component into an elevated temperature environment, thus introducing another consideration factor for mechanical stability of interconnection joints. Since most of the shock performance data available were produced at room temperature, the effect of elevated temperature is of interest to ensure the reliability of the device in a mechanical shock environment. To achieve a stable␣interconnect in a dynamic shock environment, the interconnections must tolerate mechanical strain, which is induced by the shock wave input and reaches the particular component interconnect joint. In this study, large body size (52.5 × 52.5 mm2) FCBGA components assembled on 2.4-mm-thick boards were tested with various isothermal pre-conditions and testing conditions. With a heating element embedded in the test board, a test temperature range from room temperature to 100°C was established. The effects of elevated temperature on mechanical shock performance were investigated. Failure and degradation mechanisms are identified and discussed based on the microstructure evolution and grain structure transformations.

  6. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

  7. Effects of advanced process approaches on electromigration degradation of Cu on-chip interconnects

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, M.A.

    2007-07-12

    This thesis provides a methodology for the investigation of electromigration (EM) in Cu-based interconnects. An experimental framework based on in-situ scanning electron microscopy (SEM) investigations was developed for that purpose. It is capable to visualize the EM-induced void formation and evolution in multi-level test structures in real time. Different types of interconnects were investigated. Furthermore, stressed and unstressed samples were studied applying advanced physical analysis techniques in order to obtain additional information about the microstructure of the interconnects as well as interfaces and grain boundaries. These data were correlated to the observed degradation phenomena. Correlations of the experimental results to recently established theoretical models were highlighted. Three types of Cu-based interconnects were studied. Pure Cu interconnects were compared to Al-alloyed (CuAl) and CoWP-coated interconnects. The latter two represent potential approaches that address EM-related reliability concerns. It was found that in such interconnects the dominant diffusion path is no longer the Cu/capping layer interface for interconnects as in pure Cu interconnects. Instead, void nucleation occurs at the bottom Cu/barrier interface with significant effects from grain boundaries. Moreover, the in-situ investigations revealed that the initial void nucleation does not occur at the cathode end of the lines but several micrometers away from it. The mean times-to-failure of CuAl and CoWP-coated interconnects were increased by at least one order of magnitude compared to Cu interconnects. The improvements were attributed to the presence of foreign metal atoms at the Cu/capping layer interface. Post-mortem EBSD investigations were used to reveal the microstructure of the tested samples. The data were correlated to the in-situ observations. (orig.)

  8. One-step fabrication of microfluidic chips with in-plane, adhesive-free interconnections

    DEFF Research Database (Denmark)

    Sabourin, David; Dufva, Martin; Jensen, Thomas Glasdam

    2010-01-01

    A simple method for creating interconnections to a common microfluidic device material, poly(methyl methacrylate) (PMMA), is presented. A press-fit interconnection is created between oversized, deformable tubing and complementary, undersized semi-circular ports fabricated into PMMA bonding surfac...

  9. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    Science.gov (United States)

    Rogers, John A; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

    2014-05-20

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  10. Impact of Bundle Structure on Performance of on-Chip CNT Interconnects

    International Nuclear Information System (INIS)

    Kuruvilla, N.; Raina, J.P

    2014-01-01

    CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.

  11. Optimization of high frequency flip-chip interconnects for digital superconducting circuits

    International Nuclear Information System (INIS)

    Rafique, M R; Engseth, H; Kidiyarova-Shevchenko, A

    2006-01-01

    This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than -20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s -1 speedand can operate above 100 Gbit s -1 speed. Wide bandwidth transmission requires the realization of an advanced flip-chip process with a small dimension of the MCM contact (less than 30 μm diameter of the contact pad) and small height of the flip-chip contact bumps of the order of 2 μm. Current processes with about 7 μm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s -1 ; however, the maximum speed of operation is 61 Gbit s -1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link

  12. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

    CERN Multimedia

    Saba, A

    2006-01-01

    2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

  13. Si micro photonics for optical interconnection

    International Nuclear Information System (INIS)

    Wada, K.; Ahn, D.H.; Lim, D.R.; Michel, J.; Kimerling, L.C.

    2006-01-01

    This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated

  14. Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2010-01-01

    Abstract—This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair

  15. An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, A.; Goossens, Kees

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  16. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, M.A.; Goossens, K.G.W.

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  17. Micro-patterning of self-supporting layers with conducting polymer wires for 3D-chip interconnection applications

    International Nuclear Information System (INIS)

    Ackermann, J.; Videlot, C.; Nguyen, T.N.; Wang, L.; Sarro, P.M.; Crawley, D.; Nikolic, K.; Forshaw, M.

    2003-01-01

    Highly conducting polymers have attracted much interest because of their potential applications in sensors and electronic devices. By the use of templates like porous membranes during polymerization conducting molecular wires can be formed with highly anisotropic properties which can be used as interconnecting layers in a three-dimensional (3D)-chip stacking. We focussed on two electrochemical polymerization (ECP) techniques to produce molecular wires based on polypyrrole (PPy) embedded in isolating porous polycarbonate membranes as self-supporting layers. The growth of the polymer through the membrane pores was investigated in order to achieve a good conductivity through the pores, but with a small cross-talk between them. A new polymerization technique based on a structured cathode has been developed in order to control the polymerization locally. By that technique micro-patterned membranes with separated conducting polymer wires could be produced

  18. Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

    Science.gov (United States)

    Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

    2011-04-25

    Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

  19. Laser isotope purification of lead for use in semiconductor chip interconnects

    International Nuclear Information System (INIS)

    Scheibner, K.; Haynam, C.; Worden, E.; Esser, B.

    1996-01-01

    Lead, used throughout the electronics industries, typically contains small amounts of radioactive 210 Pb (a daughter product of the planets ubiquitous 238 U) whose 210 Po daughter emits an α-particle that is known to cause soft errors in electronic circuits. The 210 Pb is not separable by chemical means. This paper describes the generic Atomic Vapor Laser Isotope Separation (AVLIS) process developed at the Lawrence Livermore National Laboratory (LLNL) over the last 20 years, with particular emphasis on recent efforts to develop the process physics and component technologies required to remove the offending 210 Pb using lasers. We have constructed a developmental facility that includes a process laser development area and a test bed for the vaporizer and ion and product collectors. We will be testing much of the equipment and demonstrating pilot scale AVLIS on a surrogate material later this year. Detection of the very low alpha emission even from commercially available low-alpha lead is challenging. LLNL's detection capabilities will be described. The goal of the development of lead purification technology is to demonstrate the capability in FY97, and to deploy a production machine capable of up to several MT/y of isotopically purified material, possible beginning in FY98

  20. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  1. Channel-Selectable Optical Link Based on a Silicon Microring for on-Chip Interconnection

    International Nuclear Information System (INIS)

    Qiu Chen; Hu Ting; Wang Wan-Jun; Yu Ping; Jiang Xiao-Qing; Yang Jian-Yi

    2012-01-01

    A channel-selectable optical link based on a silicon microring resonator is proposed and demonstrated. This optical link consists of the wavelength-tunable microring modulators and the filters, defined on a silicon-on-insulator (SOI) platform. With a p—i—n junction embedded in the microring modulator, light at the resonant wavelength of the ring resonator is modulated. The 2 nd -order microring add-drop filter routes the modulated light. The channel selectivity is demonstrated by heating the microrings. With a thermal tuning efficiency of 5.9 mW/nm, the filter drop port response was successfully tuned with 0.8 nm channel spacing. We also show that modulation can be achieved in these channels. This device aims to offer flexibility and increase the bandwidth usage efficiency in optical interconnection

  2. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  3. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Directory of Open Access Journals (Sweden)

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  4. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  5. Four-port mode-selective silicon optical router for on-chip optical interconnect.

    Science.gov (United States)

    Jia, Hao; Zhou, Ting; Fu, Xin; Ding, Jianfeng; Zhang, Lei; Yang, Lin

    2018-04-16

    We propose and demonstrate a four-port mode-selective optical router on a silicon-on-insulator platform. The passive routing property ensures that the router consumes no power to establish the optical links. For each port, input signals with different modes are selectively routed to the target ports through the pre-designed architecture. In general, the device intrinsically supports broadcasting of multiplexed signals from one port to the other three ports through mode division multiplexing. In some applications, the input signal from one port would only be sent to another port as in reconfigurable optical routers. The prototype is constructed by mode multiplexers/de-multiplexers and single-mode interconnect waveguides between them. The insertion losses for all optical links are lower than 8.0 dB, and the largest optical crosstalk values are lower than -18.7 dB and -22.0 dB for the broadcasting and port-to-port routing modes, respectively, at the wavelength range of 1525-1565 nm. In order to verify the routing functionality, a 40-Gbps bidirectional data transmission experiment is performed. The device offers a promising building block for passive routing by utilizing the dimension of the modes.

  6. Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

    Science.gov (United States)

    Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

    2016-05-01

    The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS

  7. High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-05-01

    This final report is a compilation of final reports from each of the groups participating in the program. The main three groups involved in this effort are the Thomas J. Watson Research Center of IBM Corporation in Yorktown Heights, New York, Assembly Process Design of IBM Corporation in Endicott, New York, and SMT Laboratory of Universal Instruments Corporation in Binghamton, New York. The group at the research center focused on the conductive adhesive materials development and characterization. The group in process development focused on processing of the Polymer-Metal-Solvent Paste (PMSP) to form conductive adhesive bumps, formation of the Polymer-Metal Composite (PMC) on semiconductor devices and study of the bonding process to circuitized organic carriers, and the long term durability and reliability of joints formed using the process. The group at Universal Instruments focused on development of an equipment set and bonding parameters for the equipment to produce bond assembly tooling. Reports of each of these individual groups are presented here reviewing their technical efforts and achievements.

  8. Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

    Science.gov (United States)

    Wu, Yuan-Yun

    In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a

  9. Semiconductor

    International Nuclear Information System (INIS)

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  10. AN ACCURATE MODELING OF DELAY AND SLEW METRICS FOR ON-CHIP VLSI RC INTERCONNECTS FOR RAMP INPUTS USING BURR’S DISTRIBUTION FUNCTION

    Directory of Open Access Journals (Sweden)

    Rajib Kar

    2010-09-01

    Full Text Available This work presents an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS circuits foe ramp input. Our metric assumption is based on the Burr’s Distribution function. The Burr’s distribution is used to characterize the normalized homogeneous portion of the step response. We used the PERI (Probability distribution function Extension for Ramp Inputs technique that extends delay metrics and slew metric for step inputs to the more general and realistic non-step inputs. The accuracy of our models is justified with the results compared with that of SPICE simulations.

  11. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  12. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-05-05

    ... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

  13. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Science.gov (United States)

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

  14. Interconnection blocks: a method for providing reusable, rapid, multiple, aligned and planar microfluidic interconnections

    DEFF Research Database (Denmark)

    Sabourin, David; Snakenborg, Detlef; Dufva, Hans Martin

    2009-01-01

    In this paper a method is presented for creating 'interconnection blocks' that are re-usable and provide multiple, aligned and planar microfluidic interconnections. Interconnection blocks made from polydimethylsiloxane allow rapid testing of microfluidic chips and unobstructed microfluidic observ...

  15. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Science.gov (United States)

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  16. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2011-03-17

    ... existence of a domestic industry. The Commission's notice of investigation named several respondents...; Freescale Semiconductor Malaysia Sdn. Bhd. of Malaysia; Freescale Semiconductor Pte. Ltd. of Singapore; Mouser Electronics, Inc. of Mansfield, Texas; and Motorola Inc. of Schaumburg, Illinois. On August 16...

  17. 32 x 16 CMOS smart pixel array for optical interconnects

    Science.gov (United States)

    Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

    2000-05-01

    Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

  18. Area array interconnection handbook

    CERN Document Server

    Totta, Paul A

    2012-01-01

    Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later famil...

  19. Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

    International Nuclear Information System (INIS)

    Mishra, Vijay; Kataria, S.K.

    2005-01-01

    A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

  20. Electroless Ni-B plating on SiO2 with 3-aminopropyl-triethoxysilane as a barrier layer against Cu diffusion for through-Si via interconnections in a 3-dimensional multi-chip package

    International Nuclear Information System (INIS)

    Ikeda, Akihiro; Sakamoto, Atsushi; Hattori, Reiji; Kuroki, Yukinori

    2009-01-01

    Electroless Ni-B was plated on SiO 2 as a barrier layer against Cu diffusion for through-Si via (TSV) interconnections in a 3-dimensional multi-chip package. The electroless Ni-B was deposited on the entire area of the SiO 2 side wall of a deep via with vapor phase pre-deposition of 3-aminopropyl-triethoxysilane on the SiO 2 . The carrier lifetimes in the Si substrates plated with Ni-B/Cu did not decrease with an increase in annealing temperature up to 400 deg. C . The absence of degradation of carrier lifetimes indicates that Cu atoms did not diffuse into the Si through the Ni-B. The advantages of electroless Ni-B (good conformal deposition and forming an effective diffusion barrier against Cu) make it useful as a barrier layer for TSV interconnections in a 3-dimensional multi-chip package

  1. Interconnection blocks: a method for providing reusable, rapid, multiple, aligned and planar microfluidic interconnections

    International Nuclear Information System (INIS)

    Sabourin, D; Snakenborg, D; Dufva, M

    2009-01-01

    In this paper a method is presented for creating 'interconnection blocks' that are re-usable and provide multiple, aligned and planar microfluidic interconnections. Interconnection blocks made from polydimethylsiloxane allow rapid testing of microfluidic chips and unobstructed microfluidic observation. The interconnection block method is scalable, flexible and supports high interconnection density. The average pressure limit of the interconnection block was near 5.5 bar and all individual results were well above the 2 bar threshold considered applicable to most microfluidic applications

  2. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  3. SU-8 cantilever chip interconnection

    DEFF Research Database (Denmark)

    Johansson, Alicia Charlotte; Janting, Jakob; Schultz, Peter

    2006-01-01

    The polymer SU-8 is becoming widely used for all kinds of micromechanical and microfluidic devices, not only as a photoresist but also as the constitutional material of the devices. Many of these polymeric devices need to include a microfluidic system as well as electrical connection from the ele...

  4. Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

    Energy Technology Data Exchange (ETDEWEB)

    Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-12-01

    Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

  5. Interconnection Guidelines

    Science.gov (United States)

    The Interconnection Guidelines provide general guidance on the steps involved with connecting biogas recovery systems to the utility electrical power grid. Interconnection best practices including time and cost estimates are discussed.

  6. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Science.gov (United States)

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  7. Nano/CMOS architectures using a field-programmable nanowire interconnect

    International Nuclear Information System (INIS)

    Snider, Gregory S; Williams, R Stanley

    2007-01-01

    A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

  8. Low power interconnect design

    CERN Document Server

    Saini, Sandeep

    2015-01-01

    This book provides practical solutions for delay and power reduction for on-chip interconnects and buses.  It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.  Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.   ·         Provides practical solutions for delay and power reduction for on-chip interconnects and buses; ·         Focuses on Deep Sub micron technology devices and interconnects; ·         Offers in depth analysis of delay, including details regarding crosstalk and parasitics;  ·         Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for del...

  9. Analysis of the trade-offs between conventional and superconducting interconnections

    International Nuclear Information System (INIS)

    Frye, R.

    1989-01-01

    Superconductivity can now be achieved at temperatures compatible with semiconductor device operation. This raises the interesting possibility of using the new, high-temperature superconducting ceramics for interconnections in electronic systems. This paper examines some of the consequences of a resistance-free interconnection medium. A problem with conventional conductors in electronic systems is that the resistance of wires increases quadratically as the wire dimensions are scaled down. Below some minimum cross-sectional area, determined by the metal resistivity and wire length, the resistance in these lines begins to severely limit their bandwidth. Superconductors, on the other hand, are not constrained by the same scaling rules. They provide a high bandwidth interconnection at all sizes and lengths. The limitations for superconductors are set by their critical current densities. If line dimensions become too small, a superconductor will no longer support an adequate flow of current. An analysis is presented examining the performance trade-offs for conventional and superconducting interconnections in applications ranging from printed wiring boards to chips. For most semiconductor device-based applications, the potential gains in wiring density offered by superconductors are probably more important than the bandwidth improvements. An important result of the analysis is that it determines the values of critical current density above which superconductors outperform conventional wires in systems of various physical sizes. This identifies particular interconnection technologies for which high-temperature superconductors show the most promise

  10. Transurban interconnectivities

    DEFF Research Database (Denmark)

    Jørgensen, Claus Møller

    2012-01-01

    This essay discusses the interpretation of the revolutionary situations of 1848 in light of recent debates on interconnectivity in history. The concept of transurban interconnectivities is proposed as the most precise concept to capture the nature of interconnectivity in 1848. It is argued....... It is argued that circulating political communication accounts for similarities with respect to political agenda, organisational form and political repertoire evident in urban settings across Europe. This argument is supported by a series of examples of local organisation and local appropriations of liberalism...

  11. Optical interconnects

    CERN Document Server

    Chen, Ray T

    2006-01-01

    This book describes fully embedded board level optical interconnect in detail including the fabrication of the thin-film VCSEL array, its characterization, thermal management, the fabrication of optical interconnection layer, and the integration of devices on a flexible waveguide film. All the optical components are buried within electrical PCB layers in a fully embedded board level optical interconnect. Therefore, we can save foot prints on the top real estate of the PCB and relieve packaging difficulty reduced by separating fabrication processes. To realize fully embedded board level optical

  12. Integrated Optical Interconnect Architectures for Embedded Systems

    CERN Document Server

    Nicolescu, Gabriela

    2013-01-01

    This book provides a broad overview of current research in optical interconnect technologies and architectures. Introductory chapters on high-performance computing and the associated issues in conventional interconnect architectures, and on the fundamental building blocks for integrated optical interconnect, provide the foundations for the bulk of the book which brings together leading experts in the field of optical interconnect architectures for data communication. Particular emphasis is given to the ways in which the photonic components are assembled into architectures to address the needs of data-intensive on-chip communication, and to the performance evaluation of such architectures for specific applications.   Provides state-of-the-art research on the use of optical interconnects in Embedded Systems; Begins with coverage of the basics for high-performance computing and optical interconnect; Includes a variety of on-chip optical communication topologies; Features coverage of system integration and opti...

  13. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  14. Interconnected networks

    CERN Document Server

    2016-01-01

    This volume provides an introduction to and overview of the emerging field of interconnected networks which include multi layer or multiplex networks, as well as networks of networks. Such networks present structural and dynamical features quite different from those observed in isolated networks. The presence of links between different networks or layers of a network typically alters the way such interconnected networks behave – understanding the role of interconnecting links is therefore a crucial step towards a more accurate description of real-world systems. While examples of such dissimilar properties are becoming more abundant – for example regarding diffusion, robustness and competition – the root of such differences remains to be elucidated. Each chapter in this topical collection is self-contained and can be read on its own, thus making it also suitable as reference for experienced researchers wishing to focus on a particular topic.

  15. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  16. Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

    International Nuclear Information System (INIS)

    Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

    2015-01-01

    Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

  17. A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication.

    Directory of Open Access Journals (Sweden)

    Usman Ali Gulzari

    Full Text Available A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor's and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.

  18. LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

    International Nuclear Information System (INIS)

    Heijne, E.H.M.; Antinori, F.; Barberis, D.

    1996-01-01

    The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

  19. Carbon nanotubes for interconnects process, design and applications

    CERN Document Server

    Dijon, Jean; Maffucci, Antonio

    2017-01-01

    This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits. Provides a single-source reference on carbon nanotubes for interconnect applications; Includes c...

  20. A one-semester course in modeling of VSLI interconnections

    CERN Document Server

    Goel, Ashok

    2015-01-01

    Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

  1. Computer simulation of electromigration in microelectronics interconnect

    OpenAIRE

    Zhu, Xiaoxin

    2014-01-01

    Electromigration (EM) is a phenomenon that occurs in metal conductor carrying high density electric current. EM causes voids and hillocks that may lead to open or short circuits in electronic devices. Avoiding these failures therefore is a major challenge in semiconductor device and packaging design and manufacturing, and it will become an even greater challenge for the semiconductor assembly and packaging industry as electronics components and interconnects get smaller and smaller. According...

  2. Circuit and interconnect design for high bit-rate applications

    NARCIS (Netherlands)

    Veenstra, H.

    2006-01-01

    This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

  3. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...

  4. Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

    NARCIS (Netherlands)

    Van den Berg, A.; Ren, P.; Marinissen, E.J.; Gaydadjiev, G.; Goossens, K.

    2010-01-01

    Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or

  5. Bandwidth analysis of functional interconnects used as test access mechanism

    NARCIS (Netherlands)

    Berg, van den Ardy; Ren, P.; Marinissen, Erik Jan; Gaydadjiev, G.N.; Goossens, K.G.W.

    2010-01-01

    Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or

  6. FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

    International Nuclear Information System (INIS)

    Sharma, Devendra Kumar; Kaushik, Brajesh Kumar; Sharma, R. K.

    2014-01-01

    The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line and coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method. (semiconductor integrated circuits)

  7. High-resolution X-ray imaging - a powerful nondestructive technique for applications in semiconductor industry

    International Nuclear Information System (INIS)

    Zschech, Ehrenfried; Yun, Wenbing; Schneider, Gerd

    2008-01-01

    The availability of high-brilliance X-ray sources, high-precision X-ray focusing optics and very efficient CCD area detectors has contributed essentially to the development of transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) with sub-50 nm resolution. Particularly, the fabrication of high aspect ratio Fresnel zone plates with zone widths approaching 15 nm has contributed to the enormous improvement in spatial resolution during the previous years. Currently, Fresnel zone plates give the ability to reach spatial resolutions of 15 to 20 nm in the soft and of about 30 to 50 nm in the hard X-ray energy range. X-ray microscopes with rotating anode X-ray sources that can be installed in an analytical lab next to a semiconductor fab have been developed recently. These unique TXM/XCT systems provide an important new capability of nondestructive 3D imaging of internal circuit structures without destructive sample preparation such as cross sectioning. These lab systems can be used for failure localization in micro- and nanoelectronic structures and devices, e.g., to visualize voids and residuals in on-chip metal interconnects without physical modification of the chip. Synchrotron radiation experiments have been used to study new processes and materials that have to be introduced into the semiconductor industry. The potential of TXM using synchrotron radiation in the soft X-ray energy range is shown for the nondestructive in situ imaging of void evolution in embedded on-chip copper interconnect structures during electromigration and for the imaging of different types of insulating thin films between the on-chip interconnects (spectromicroscopy). (orig.)

  8. Chip-To-Chip Optical Interconnection Using MEMS Mirrors

    Science.gov (United States)

    2009-03-26

    power generated through a resistor is a function of this common current but different resistances, different amounts of heat are generated in the two...Chiu, “Modeling and control of piezo - electric cantilever beam micro mirror and micro laser arrays to reduce image band- ing in electrophotographic

  9. Chip-by-chip configurable interconnection using digital printing techniques

    International Nuclear Information System (INIS)

    Mashayekhi, Mohammad; Carrabina, Jordi; Winchester, Lee; Laurila, Mika-Matti; Mäntysalo, Matti; Ogier, Simon; Terés, Lluís

    2017-01-01

    Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. (paper)

  10. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  11. Electro-optic techniques for VLSI interconnect

    Science.gov (United States)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  12. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Hutcheson, L.D.

    1988-01-01

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  13. Low energy routing platforms for optical interconnects using active plasmonics integrated with Silicon Photonics

    DEFF Research Database (Denmark)

    Vyrsokinos, K.; Papaioannou, S.; Kalavrouziotis, D.

    2013-01-01

    technologies to cope with the massive amount of data moving across all hierarchical communication levels, namely rack-to-rack, backplane, chip-to-chip and even on-chip interconnections. Plasmonics comes indeed as a disruptive technology that enables seamless interoperability between light beams and electronic...

  14. Ultrahigh-speed hybrid laser for silicon photonic integrated chips

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

    2013-01-01

    Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

  15. Packaging and interconnection for superconductive circuitry

    International Nuclear Information System (INIS)

    Anacker, W.

    1976-01-01

    A three dimensional microelectronic module packaged for reduced signal propagation delay times including a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon is described. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits

  16. Architecture for on-die interconnect

    Science.gov (United States)

    Khare, Surhud; More, Ankit; Somasekhar, Dinesh; Dunning, David S.

    2016-03-15

    In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

  17. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  18. High-density hybrid interconnect methodologies

    International Nuclear Information System (INIS)

    John, J.; Zimmermann, L.; Moor, P.De; Hoof, C.Van

    2003-01-01

    Full text: The presentation gives an overview of the state-of-the-art of hybrid integration and in particular the IMEC technological approaches that will be able to address future hybrid detector needs. The dense hybrid flip-chip integration of an array of detectors and its dedicated readout electronics can be achieved with a variety of solderbump techniques such as pure Indium or Indium alloys, Ph-In, Ni/PbSn, but also conducting polymers... Particularly for cooled applications or ultra-high density applications, Indium solderbump technology (electroplated or evaporated) is the method of choice. The state-of-the-art of solderbump technologies that are to a high degree independent of the underlying detector material will be presented and examples of interconnect densities between 5x1E4cm-2 and 1x1E6 cm-2 will be demonstrated. For several classes of detectors, flip-chip integration is not allowed since the detectors have to be illuminated from the top. This applies to image sensors for EUV applications such as GaN/AlGaN based detectors and to MEMS-based sensors. In such cases, the only viable interconnection method has to be through the (thinned) detector wafer followed by a solderbump-based integration. The approaches for dense and ultra-dense through-the-wafer interconnect 'vias' will be presented and wafer thinning approaches will be shown

  19. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  20. An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

    International Nuclear Information System (INIS)

    Zhu Zhang-Ming; Hao Bao-Tian; En Yun-Fei; Yang Yin-Tang; Li Yue-Jin

    2011-01-01

    On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses. (interdisciplinary physics and related areas of science and technology)

  1. Brookhaven segment interconnect

    International Nuclear Information System (INIS)

    Morse, W.M.; Benenson, G.; Leipuner, L.B.

    1983-01-01

    We have performed a high energy physics experiment using a multisegment Brookhaven FASTBUS system. The system was composed of three crate segments and two cable segments. We discuss the segment interconnect module which permits communication between the various segments

  2. Optical interconnection networks for high-performance computing systems

    International Nuclear Information System (INIS)

    Biberman, Aleksandr; Bergman, Keren

    2012-01-01

    Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. (review article)

  3. Testing of modern semiconductor memory structures

    NARCIS (Netherlands)

    Gaydadjiev, G.N.

    2007-01-01

    In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

  4. Adapting Memory Hierarchies for Emerging Datacenter Interconnects

    Institute of Scientific and Technical Information of China (English)

    江涛; 董建波; 侯锐; 柴琳; 张立新; 孙凝晖; 田斌

    2015-01-01

    Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects—particularly as they affect remote memory access—and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms: a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes;and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and limitations.

  5. Influence of interconnection on the long-term reliability of UV LED packages

    Science.gov (United States)

    Nieland, S.; Mitrenga, D.; Karolewski, D.; Brodersen, O.; Ortlepp, T.

    2017-02-01

    High power LEDs have conquered the mass market in recent years. Besides the main development focus to achieve higher productivity in the field of visible semiconductor LED processing, the wavelength range is further enhanced by active research and development in the direction of UVA / UVB / UVC. UVB and UVC LEDs are new and promising due to their numerous advantages. UV LEDs emit in a near range of one single emission peak with a width (FWHM) below 15 nm compared to conventional mercury discharge lamps and xenon sources, which show broad spectrums with many emission peaks over a wide range of wavelengths. Furthermore, the UV LED size is in the range of a few hundred microns and offers a high potential of significant system miniaturization. Of course, LED efficiency, lifetime and output power have to be increased [1]. Lifetime limiting issues of UVB/UVC-LED are the very high thermal stress in the chip resulting from the higher forward voltages (6-10 V @ 350 mA), the lower external quantum efficiency, below 10 % (most of the power disappears as heat), and the thermal resistance Rth of conventional LED packages being not able to dissipate these large amounts of heat for spreading. Beside the circuit boards and submounts which should have maximum thermal conductivity, the dimension of contacts as well as the interconnection of UV LED to the submount/package determinates the resolvable amount of heat [2]. In the paper different innovative interconnection techniques for UVC-LED systems will be discussed focused on the optimization of thermal conductivity in consideration of the assembly costs. Results on thermal simulation for the optimal contact dimensions and interconnections will be given. In addition, these theoretical results will be compared with results on electrical characterization as well as IR investigations on real UV LED packages in order to give recommendations for optimal UV LED assembly.

  6. 2D and 3D interconnect fabrication by picosecond Laser Induced Forward Transfer

    NARCIS (Netherlands)

    Oosterhuis, G.; Huis in 't veld, A.J.; Chall, P.

    2011-01-01

    Interconnects are an important cost driver in advanced 3D chip packaging. This holds for Through Silicon Vias (TSV) for chip stacking, but also for other integrated Si-technology. Especially in applications with a low number (<100 mm-2) of relatively large (10-2- um diameter), high aspect ratio

  7. SEMICONDUCTOR INTEGRATED CIRCUITS: An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

    Science.gov (United States)

    Fangxiong, Chen; Min, Lin; Heping, Ma; Hailong, Jia; Yin, Shi; Forster, Dai

    2009-08-01

    An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (IIP3) is 16.621 dBm, with 50 Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system) and Bluetooth systems.

  8. Benefits of transmission interconnections

    International Nuclear Information System (INIS)

    Lyons, D.

    2006-01-01

    The benefits of new power transmission interconnections from Alberta were discussed with reference to the challenges and measures needed to move forward. Alberta's electricity system has had a long period of sustained growth in generation and demand and this trend is expected to continue. However, no new interconnections have been built since 1985 because the transmission network has not expanded in consequence with the growth in demand. As such, Alberta remains weakly interconnected with the rest of the western region. The benefits of stronger transmission interconnections include improved reliability, long-term generation capability, hydrothermal synergies, a more competitive market, system efficiencies and fuel diversity. It was noted that the more difficult challenges are not technical. Rather, the difficult challenges lie in finding an appropriate business model that recognizes different market structures. It was emphasized that additional interconnections are worthwhile and will require significant collaboration among market participants and governments. It was concluded that interties enable resource optimization between systems and their benefits far exceed their costs. tabs., figs

  9. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  10. Interconnecting with VIPs

    Science.gov (United States)

    Collins, Robert

    2013-01-01

    Interconnectedness changes lives. It can even save lives. Recently the author got to witness and be part of something in his role as a teacher of primary science that has changed lives: it may even have saved lives. It involved primary science teaching--and the climate. Robert Collins describes how it is all interconnected. The "Toilet…

  11. CAISSON: Interconnect Network Simulator

    Science.gov (United States)

    Springer, Paul L.

    2006-01-01

    Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.

  12. Fixed Orientation Interconnection Problems: Theory, Algorithms and Applications

    DEFF Research Database (Denmark)

    Zachariasen, Martin

    Interconnection problems have natural applications in the design of integrated circuits (or chips). A modern chip consists of billions of transistors that are connected by metal wires on the surface of the chip. These metal wires are routed on a (fairly small) number of layers in such a way...... that electrically independent nets do not intersect each other. Traditional manufacturing technology limits the orientations of the wires to be either horizontal or vertical — and is known as Manhattan architecture. Over the last decade there has been a growing interest in general architectures, where more than two...... a significant step forward, both concerning theory and algorithms, for the fixed orientation Steiner tree problem. In addition, the work maintains a close link to applications and generalizations motivated by chip design....

  13. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  14. Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

    Science.gov (United States)

    Savich, Gregory R.

    2004-01-01

    The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the

  15. An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates

    International Nuclear Information System (INIS)

    Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark; Vianco, Paul Thomas; Zender, Gary L.; Hlava, Paul Frank; Rejent, Jerome Andrew

    2008-01-01

    inconsistent proportions of metal and glassy phase particles present during the subsequent firing process. The consequences were subtle, intermittent changes to the thick film microstructure that gave rise to the reaction layer and, thus, the low pull strength phenomenon. A mitigation strategy would be the use of physical vapor deposition (PVD) techniques to create thin film bond pads; this is multi-chip module, deposited (MCM-D) technology

  16. An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

    Energy Technology Data Exchange (ETDEWEB)

    Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark; Vianco, Paul Thomas; Zender, Gary L.; Hlava, Paul Frank; Rejent, Jerome Andrew

    2008-09-01

    inconsistent proportions of metal and glassy phase particles present during the subsequent firing process. The consequences were subtle, intermittent changes to the thick film microstructure that gave rise to the reaction layer and, thus, the low pull strength phenomenon. A mitigation strategy would be the use of physical vapor deposition (PVD) techniques to create thin film bond pads; this is multi-chip module, deposited (MCM-D) technology.

  17. Semiconductor physics

    CERN Document Server

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  18. Photovoltaic sub-cell interconnects

    Energy Technology Data Exchange (ETDEWEB)

    van Hest, Marinus Franciscus Antonius Maria; Swinger Platt, Heather Anne

    2017-05-09

    Photovoltaic sub-cell interconnect systems and methods are provided. In one embodiment, a photovoltaic device comprises a thin film stack of layers deposited upon a substrate, wherein the thin film stack layers are subdivided into a plurality of sub-cells interconnected in series by a plurality of electrical interconnection structures; and wherein the plurality of electrical interconnection structures each comprise no more than two scribes that penetrate into the thin film stack layers.

  19. Electromagnetism and interconnections

    CERN Document Server

    Charruau, S

    2009-01-01

    This book covers the theoretical problems of modeling electrical behavior of the interconnections encountered in everyday electronic products. The coverage shows the theoretical tools of waveform prediction at work in the design of a complex and high-speed digital electronic system. Scientists, research engineers, and postgraduate students interested in electromagnetism, microwave theory, electrical engineering, or the development of simulation tools software for high speed electronic system design automation will find this book an illuminating resource.

  20. Interconnectivity: Benefits and Challenges

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2010-09-15

    Access to affordable and reliable electricity supplies is a basic prerequisite for economic and social development, prosperity, health, education and all other aspects of modern society. Electricity can be generated both near and far from the consumption areas as transmission lines, grid interconnections and distribution systems can transport it to the final consumer. In the vast majority of countries, the electricity sector used to be owned and run by the state. The wave of privatisation and market introduction in a number of countries and regions which started in the late 1980's has in many cases involved unbundling of generation from transmission and distribution (T and D). This has nearly everywhere exposed transmission bottlenecks limiting the development of well-functioning markets. Transmission on average accounts for about 10-15% of total final kWh cost paid by the end-user but it is becoming a key issue for effective operation of liberalised markets and for their further development. An integrated and adequate transmission infrastructure is of utmost importance for ensuring the delivery of the most competitively priced electricity, including externalities, to customers, both near and far from the power generating facilities. In this report, the role of interconnectivity in the development of energy systems is examined with the associated socio-economic, environmental, financial and regulatory aspects that must be taken into account for successful interconnection projects.

  1. Interconnection of Distributed Energy Resources

    Energy Technology Data Exchange (ETDEWEB)

    Reiter, Emerson [National Renewable Energy Lab. (NREL), Golden, CO (United States)

    2017-04-19

    This is a presentation on interconnection of distributed energy resources, including the relationships between different aspects of interconnection, best practices and lessons learned from different areas of the U.S., and an update on technical advances and standards for interconnection.

  2. Optically coupled semiconductor device

    Energy Technology Data Exchange (ETDEWEB)

    Kumagaya, Naoki

    1988-11-18

    This invention concerns an optically coupled semiconductor device using the light as input signal and a MOS transistor for the output side in order to control on-off of the output side by the input signal which is insulated from the output. Concerning this sort of element, when a MOS transistor and a load resistance are planned to be accumulated on the same chip, a resistor and control of impurity concentration of the channel, etc. become necessary despite that the only formation of a simple P-N junction is enough, for a solar cell, hence cost reduction thereof cannot be done. In order to remove this defect, this invention offers an optically coupled semiconductor device featuring that two solar cells are connected in reverse parallel between the gate sources of the output MOS transistors and an operational light emitting element is individually set facing a respective solar cell. 4 figs.

  3. A low-cost, manufacturable method for fabricating capillary and optical fiber interconnects for microfluidic devices.

    Science.gov (United States)

    Hartmann, Daniel M; Nevill, J Tanner; Pettigrew, Kenneth I; Votaw, Gregory; Kung, Pang-Jen; Crenshaw, Hugh C

    2008-04-01

    Microfluidic chips require connections to larger macroscopic components, such as light sources, light detectors, and reagent reservoirs. In this article, we present novel methods for integrating capillaries, optical fibers, and wires with the channels of microfluidic chips. The method consists of forming planar interconnect channels in microfluidic chips and inserting capillaries, optical fibers, or wires into these channels. UV light is manually directed onto the ends of the interconnects using a microscope. UV-curable glue is then allowed to wick to the end of the capillaries, fibers, or wires, where it is cured to form rigid, liquid-tight connections. In a variant of this technique, used with light-guiding capillaries and optical fibers, the UV light is directed into the capillaries or fibers, and the UV-glue is cured by the cone of light emerging from the end of each capillary or fiber. This technique is fully self-aligned, greatly improves both the quality and the manufacturability of the interconnects, and has the potential to enable the fabrication of interconnects in a fully automated fashion. Using these methods, including a semi-automated implementation of the second technique, over 10,000 interconnects have been formed in almost 2000 microfluidic chips made of a variety of rigid materials. The resulting interconnects withstand pressures up to at least 800psi, have unswept volumes estimated to be less than 10 femtoliters, and have dead volumes defined only by the length of the capillary.

  4. Interconnection policy: a theoretical survey

    Directory of Open Access Journals (Sweden)

    César Mattos

    2003-01-01

    Full Text Available This article surveys the theoretical foundations of interconnection policy. The requirement of an interconnection policy should not be taken for granted in all circumstances, even considering the issue of network externalities. On the other hand, when it is required, an encompassing interconnection policy is usually justified. We provide an overview of the theory on interconnection pricing that results in several different prescriptions depending on which problem the regulator aims to address. We also present a survey on the literature on two-way interconnection.

  5. Compound semiconductor optical waveguide switch

    Science.gov (United States)

    Spahn, Olga B.; Sullivan, Charles T.; Garcia, Ernest J.

    2003-06-10

    An optical waveguide switch is disclosed which is formed from III-V compound semiconductors and which has a moveable optical waveguide with a cantilevered portion that can be bent laterally by an integral electrostatic actuator to route an optical signal (i.e. light) between the moveable optical waveguide and one of a plurality of fixed optical waveguides. A plurality of optical waveguide switches can be formed on a common substrate and interconnected to form an optical switching network.

  6. Design and Training of Limited-Interconnect Architectures

    Science.gov (United States)

    1991-07-16

    and signal processing. Neuromorphic (brain like) models, allow an alternative for achieving real-time operation tor such tasks, while having a...compact and robust architecture. Neuromorphic models consist of interconnections of simple computational nodes. In this approach, each node computes a...operational performance. I1. Research Objectives The research objectives were: 1. Development of on- chip local training rules specifically designed for

  7. LHC beampipe interconnection

    CERN Document Server

    Particle beams circulate for around 10 hours in the Large Hadron Collider (LHC). During this time, the particles make four hundred million revolutions of the machine, travelling a distance equivalent to the diameter of the solar system. The beams must travel in a pipe which is emptied of air, to avoid collisions between the particles and air molecules (which are considerably bigger than protons). The beam pipes are pumped down to an air pressure similar to that on the surface of the moon. Much of the LHC runs at 1.9 degrees above absolute zero. When material is cooled, it contracts. The interconnections must absorb this contraction whilst maintaining electrical connectivity.

  8. Organic semiconductors in sensor applications

    CERN Document Server

    Malliaras, George; Owens, Róisín

    2008-01-01

    Organic semiconductors offer unique characteristics such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing, and facile integration with chemical and biological functionalities. These characteristics have prompted the application of organic semiconductors and their devices in physical, chemical, and biological sensors. This book covers this rapidly emerging field by discussing both optical and electrical sensor concepts. Novel transducers based on organic light-emitting diodes and organic thin-film transistors, as well as systems-on-a-chip architectures are presented. Functionalization techniques to enhance specificity are outlined, and models for the sensor response are described.

  9. Introduction to semiconductor manufacturing technology

    CERN Document Server

    2012-01-01

    IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

  10. On-chip mode division multiplexing technologies

    DEFF Research Database (Denmark)

    Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

    2016-01-01

    Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... photonic integrated circuit mode (de) multiplexer for few-mode fibers (FMFs)....

  11. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  12. Fabrication method to create high-aspect ratio pillars for photonic coupling of board level interconnects

    Science.gov (United States)

    Debaes, C.; Van Erps, J.; Karppinen, M.; Hiltunen, J.; Suyal, H.; Last, A.; Lee, M. G.; Karioja, P.; Taghizadeh, M.; Mohr, J.; Thienpont, H.; Glebov, A. L.

    2008-04-01

    An important challenge that remains to date in board level optical interconnects is the coupling between the optical waveguides on printed wiring boards and the packaged optoelectronics chips, which are preferably surface mountable on the boards. One possible solution is the use of Ball Grid Array (BGA) packages. This approach offers a reliable attachment despite the large CTE mismatch between the organic FR4 board and the semiconductor materials. Collimation via micro-lenses is here typically deployed to couple the light vertically from the waveguide substrate to the optoelectronics while allowing for a small misalignment between board and package. In this work, we explore the fabrication issues of an alternative approach in which the vertical photonic connection between board and package is governed by a micro-optical pillar which is attached both to the board substrate and to the optoelectronic chips. Such an approach allows for high density connections and small, high-speed detector footprints while maintaining an acceptable tolerance between board and package. The pillar should exhibit some flexibility and thus a high-aspect ratio is preferred. This work presents and compares different fabrication methods and applies different materials for such high-aspect ratio pillars. The different fabrication methods are: photolithography, direct laser writing and deep proton writing. The selection of optical materials that was investigated is: SU8, Ormocers, PU and a multifunctional acrylate polymer. The resulting optical pillars have diameters ranging from 20um up to 80um, with total heights ranging between 30um and 100um (symbol for micron). The aspect-ratio of the fabricated structures ranges from 1.5 to 5.

  13. α-particle shielding of semiconductor device

    International Nuclear Information System (INIS)

    McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

    1981-01-01

    Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

  14. Fuel cell system with interconnect

    Science.gov (United States)

    Goettler, Richard; Liu, Zhien

    2017-12-12

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  15. Policy issues in interconnecting networks

    Science.gov (United States)

    Leiner, Barry M.

    1989-01-01

    To support the activities of the Federal Research Coordinating Committee (FRICC) in creating an interconnected set of networks to serve the research community, two workshops were held to address the technical support of policy issues that arise when interconnecting such networks. The workshops addressed the required and feasible technologies and architectures that could be used to satisfy the desired policies for interconnection. The results of the workshop are documented.

  16. Tuning and synthesis of semiconductor nanostructures by mechanical compression

    Energy Technology Data Exchange (ETDEWEB)

    Fan, Hongyou; Li, Binsong

    2015-11-17

    A mechanical compression method can be used to tune semiconductor nanoparticle lattice structure and synthesize new semiconductor nanostructures including nanorods, nanowires, nanosheets, and other three-dimensional interconnected structures. II-VI or IV-VI compound semiconductor nanoparticle assemblies can be used as starting materials, including CdSe, CdTe, ZnSe, ZnS, PbSe, and PbS.

  17. Epidemics on interconnected networks

    Science.gov (United States)

    Dickison, Mark; Havlin, S.; Stanley, H. E.

    2012-06-01

    Populations are seldom completely isolated from their environment. Individuals in a particular geographic or social region may be considered a distinct network due to strong local ties but will also interact with individuals in other networks. We study the susceptible-infected-recovered process on interconnected network systems and find two distinct regimes. In strongly coupled network systems, epidemics occur simultaneously across the entire system at a critical infection strength βc, below which the disease does not spread. In contrast, in weakly coupled network systems, a mixed phase exists below βc of the coupled network system, where an epidemic occurs in one network but does not spread to the coupled network. We derive an expression for the network and disease parameters that allow this mixed phase and verify it numerically. Public health implications of communities comprising these two classes of network systems are also mentioned.

  18. Thermoelectric Coolers with Sintered Silver Interconnects

    Science.gov (United States)

    Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2014-06-01

    The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

  19. Production and characterization of SLID interconnected n-in-p pixel modules with 75 micron thin silicon sensors

    CERN Document Server

    Andricek, L; Macchiolo, A; Moser, H.G; Nisius, R; Richter, R.H; Terzo, S; Weigell, P

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. T...

  20. Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

    CERN Document Server

    Andricek, L; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tunability, charge collection, cluster sizes and hit efficiencies. Targeting at ...

  1. A test chip for automatic reliability measurements of interconnect vias

    NARCIS (Netherlands)

    Lippe, K.; Hasper, A.; Elfrink, G.W.; Niehof, J.; Kerkhoff, Hans G.

    1992-01-01

    A test circuit for electromigration reliability measurements was designed and tested. The device under test (DUT) is a via-hole chain. The test circuit permits simultaneous measurements of a number of DUTs, and a fatal error of one DUT does not influence the measurement results of the other DUTs.

  2. Semiconductor Ion Implanters

    International Nuclear Information System (INIS)

    MacKinnon, Barry A.; Ruffell, John P.

    2011-01-01

    In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion! Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intel product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.

  3. Interconnect mechanisms in microelectronic packaging

    Science.gov (United States)

    Roma, Maria Penafrancia C.

    alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

  4. Semiconductor Manufacturing equipment introduction

    International Nuclear Information System (INIS)

    Im, Jong Sun

    2001-02-01

    This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

  5. Semiconductor spintronics

    CERN Document Server

    Xia, Jianbai; Chang, Kai

    2012-01-01

    Semiconductor Spintronics, as an emerging research discipline and an important advanced field in physics, has developed quickly and obtained fruitful results in recent decades. This volume is the first monograph summarizing the physical foundation and the experimental results obtained in this field. With the culmination of the authors' extensive working experiences, this book presents the developing history of semiconductor spintronics, its basic concepts and theories, experimental results, and the prospected future development. This unique book intends to provide a systematic and modern foundation for semiconductor spintronics aimed at researchers, professors, post-doctorates, and graduate students, and to help them master the overall knowledge of spintronics.

  6. Location constrained resource interconnection

    International Nuclear Information System (INIS)

    Hawkins, D.

    2008-01-01

    This presentation discussed issues related to wind integration from the perspective of the California Independent System Operator (ISO). Issues related to transmission, reliability, and forecasting were reviewed. Renewable energy sources currently used by the ISO were listed, and details of a new transmission financing plan designed to address the location constraints of renewable energy sources and provide for new transmission infrastructure was presented. The financing mechanism will be financed by participating transmission owners through revenue requirements. New transmission interconnections will include network facilities and generator tie-lines. Tariff revisions have also been implemented to recover the costs of new facilities and generators. The new transmission project will permit wholesale transmission access to areas where there are significant energy resources that are not transportable. A rate impact cap of 15 per cent will be imposed on transmission owners to mitigate short-term costs to ratepayers. The presentation also outlined energy resource area designation plans, renewable energy forecasts, and new wind technologies. Ramping issues were also discussed. It was concluded that the ISO expects to ensure that 20 per cent of its energy will be derived from renewable energy sources. tabs., figs

  7. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

    Science.gov (United States)

    Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

    2018-04-01

    Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

  8. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  9. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  10. Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects

    Science.gov (United States)

    Peter, Geoffrey John M.

    With the ever-increasing chip complexity, interconnects have to be designed to meet the new challenges. Advances in optical lithography have made chip feature sizes available today at 70 nm dimensions. With advances in Extreme Ultraviolet Lithography, X-ray Lithography, and Ion Projection Lithography it is expected that the line width will further decrease to 20 nm or less. With the decrease in feature size, the number of active devices on the chip increases. With higher levels of circuit integration, the challenge is to dissipate the increased heat flux from the chip surface area. Thermal management considerations include coefficient of thermal expansion (CTE) matching to prevent failure between the chip and the board. This in turn calls for improved system performance and reliability of the electronic structural systems. Experience has shown that in most electronic systems, failures are mostly due to CTE mismatch between the chip, board, and the solder joint (solder interconnect). The resulting high thermal-structural stress and strain due to CTE mismatch produces cracks in the solder joints with eventual failure of the electronic component. In order to reduce the thermal stress between the chip, board, and the solder joint, this dissertation examines the effect of inserting wire bundle (wire interconnect) between the chip and the board. The flexibility of the wires or fibers would reduce the stress at the rigid joints. Numerical simulations of two, and three-dimensional models of the solder and wire interconnects are examined. The numerical simulation is linear in nature and is based on linear isotropic material properties. The effect of different wire material properties is examined. The effect of varying the wire diameter is studied by changing the wire diameter. A major cause of electronic equipment failure is due to fatigue failure caused by thermal cycling, and vibrations. A two-dimensional modal and harmonic analysis was simulated for the wire interconnect

  11. Microelectronics used for Semiconductor Imaging Detectors

    CERN Document Server

    Heijne, Erik H M

    2010-01-01

    Semiconductor crystal technology, microelectronics developments and nuclear particle detection have been in a relation of symbiosis, all the way from the beginning. The increase of complexity in electronics chips can now be applied to obtain much more information on the incident nuclear radiation. Some basic technologies are described, in order to acquire insight in possibilities and limitations for the most recent detectors.

  12. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  13. Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

    Science.gov (United States)

    Seiler, David G.

    1997-10-01

    A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

  14. Interconnecting heterogeneous database management systems

    Science.gov (United States)

    Gligor, V. D.; Luckenbaugh, G. L.

    1984-01-01

    It is pointed out that there is still a great need for the development of improved communication between remote, heterogeneous database management systems (DBMS). Problems regarding the effective communication between distributed DBMSs are primarily related to significant differences between local data managers, local data models and representations, and local transaction managers. A system of interconnected DBMSs which exhibit such differences is called a network of distributed, heterogeneous DBMSs. In order to achieve effective interconnection of remote, heterogeneous DBMSs, the users must have uniform, integrated access to the different DBMs. The present investigation is mainly concerned with an analysis of the existing approaches to interconnecting heterogeneous DBMSs, taking into account four experimental DBMS projects.

  15. Semiconductor spintronics

    International Nuclear Information System (INIS)

    Fabian, J.; Abiague, A.M.; Ertler, Ch.; Stano, P.; Zutic, I.

    2007-01-01

    Spintronics refers commonly to phenomena in which the spin of electrons in a solid state environment plays the determining role. In a more narrow sense spintronics is an emerging research field of electronics: spintronics devices are based on a spin control of electronics, or on an electrical and optical control of spin of magnetism. While metal spintronics has already found its niche in the computer industry - giant magnetoresistance systems are used as hard disk read heads - semiconductor spintronics is vet demonstrate its full potential. This review presents selected themes of semiconductor spintronics, introducing important concepts in spin transport, spin transport, spin injection. Silsbee-Johnson spin-charge coupling, and spin-dependent tunneling, as well as spin relaxation and spin dynamics. The most fundamental spin-dependent interaction in nonmagnetic semiconductors is spin-orbit coupling. Depending on the crystal symmetries of the material, as well as on the structural properties of semiconductor based heterostructures, the spin-orbit coupling takes on different functional forms, giving a nice playground of effective spin-orbit Hamiltonians. The effective Hamiltonians for the most relevant classes of materials and heterostructures are derived here from realistic electronic band structure descriptions. Most semiconductor device systems are still theoretical concepts, waiting for experimental demonstrations. A review of selected proposed, and a few demonstrated devices is presented, with detailed description of two important classes: magnetic resonant tunnel structures and bipolar magnetic diodes and transistors. In view of the importance of ferromagnetic semiconductor material, a brief discussion of diluted magnetic semiconductors is included. In most cases the presentation is of tutorial style, introducing the essential theoretical formalism at an accessible level, with case-study-like illustrations of actual experimental results, as well as with brief

  16. Universal Interconnection Technology Workshop Proceedings

    Energy Technology Data Exchange (ETDEWEB)

    Sheaffer, P.; Lemar, P.; Honton, E. J.; Kime, E.; Friedman, N. R.; Kroposki, B.; Galdo, J.

    2002-10-01

    The Universal Interconnection Technology (UIT) Workshop - sponsored by the U.S. Department of Energy, Distributed Energy and Electric Reliability (DEER) Program, and Distribution and Interconnection R&D - was held July 25-26, 2002, in Chicago, Ill., to: (1) Examine the need for a modular universal interconnection technology; (2) Identify UIT functional and technical requirements; (3) Assess the feasibility of and potential roadblocks to UIT; (4) Create an action plan for UIT development. These proceedings begin with an overview of the workshop. The body of the proceedings provides a series of industry representative-prepared papers on UIT functions and features, present interconnection technology, approaches to modularization and expandability, and technical issues in UIT development as well as detailed summaries of group discussions. Presentations, a list of participants, a copy of the agenda, and contact information are provided in the appendices of this document.

  17. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  18. Oxide semiconductors

    CERN Document Server

    Svensson, Bengt G; Jagadish, Chennupati

    2013-01-01

    Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scient

  19. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1962-01-01

    Semiconductor Statistics presents statistics aimed at complementing existing books on the relationships between carrier densities and transport effects. The book is divided into two parts. Part I provides introductory material on the electron theory of solids, and then discusses carrier statistics for semiconductors in thermal equilibrium. Of course a solid cannot be in true thermodynamic equilibrium if any electrical current is passed; but when currents are reasonably small the distribution function is but little perturbed, and the carrier distribution for such a """"quasi-equilibrium"""" co

  20. Field testing for cosmic ray soft errors in semiconductor memories

    International Nuclear Information System (INIS)

    O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

    1996-01-01

    This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

  1. Modular cryogenic interconnects for multi-qubit devices

    Energy Technology Data Exchange (ETDEWEB)

    Colless, J. I.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, The University of Sydney, Sydney, NSW 2006 (Australia)

    2014-11-15

    We have developed a modular interconnect platform for the control and readout of multiple solid-state qubits at cryogenic temperatures. The setup provides 74 filtered dc-bias connections, 32 control and readout connections with −3 dB frequency above 5 GHz, and 4 microwave feed lines that allow low loss (less than 3 dB) transmission 10 GHz. The incorporation of a radio-frequency interposer enables the platform to be separated into two printed circuit boards, decoupling the simple board that is bonded to the qubit chip from the multilayer board that incorporates expensive connectors and components. This modular approach lifts the burden of duplicating complex interconnect circuits for every prototype device. We report the performance of this platform at milli-Kelvin temperatures, including signal transmission and crosstalk measurements.

  2. Standard semiconductor packaging for high-reliability low-cost MEMS applications

    Science.gov (United States)

    Harney, Kieran P.

    2005-01-01

    Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

  3. Ultra-High Capacity Silicon Photonic Interconnects through Spatial Multiplexing

    Science.gov (United States)

    Chen, Christine P.

    The market for higher data rate communication is driving the semiconductor industry to develop new techniques of writing at smaller scales, while continuing to scale bandwidth at low power consumption. Silicon photonic (SiPh) devices offer a potential solution to the electronic interconnect bandwidth bottleneck. SiPh leverages the technology commensurate of decades of fabrication development with the unique functionality of next-generation optical interconnects. Finer fabrication techniques have allowed for manufacturing physical characteristics of waveguide structures that can support multiple modes in a single waveguide. By refining modal characteristics in photonic waveguide structures, through mode multiplexing with the asymmetric y-junction and microring resonator, higher aggregate data bandwidth is demonstrated via various combinations of spatial multiplexing, broadening applications supported by the integrated platform. The main contributions of this dissertation are summarized as follows. Experimental demonstrations of new forms of spatial multiplexing combined together exhibit feasibility of data transmission through mode-division multiplexing (MDM), mode-division and wavelength-division multiplexing (MDM-WDM), and mode-division and polarization-division multiplexing (MDM-PDM) through a C-band, Si photonic platform. Error-free operation through mode multiplexers and demultiplexers show how data can be viably scaled on multiple modes and with existing spatial domains simultaneously. Furthermore, we explore expanding device channel support from two to three arms. Finding that a slight mismatch in the third arm can increase crosstalk contributions considerably, especially when increasing data rate, we explore a methodical way to design the asymmetric y-junction device by considering its angles and multiplexer/demultiplexer arm width. By taking into consideration device fabrication variations, we turn towards optimizing device performance post

  4. Misalignment corrections in optical interconnects

    Science.gov (United States)

    Song, Deqiang

    Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or

  5. Semiconductor Detectors

    International Nuclear Information System (INIS)

    Cortina, E.

    2007-01-01

    Particle detectors based on semiconductor materials are among the few devices used for particle detection that are available to the public at large. In fact we are surrounded by them in our daily lives: they are used in photoelectric cells for opening doors, in digital photographic and video camera, and in bar code readers at supermarket cash registers. (Author)

  6. Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

    Directory of Open Access Journals (Sweden)

    Salman Shafqat

    2017-09-01

    Full Text Available The exciting field of stretchable electronics (SE promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS-type process recipes using bulk integrated circuit (IC microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic stretch beyond 3000%, with <0.3% resistance change, and >10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.

  7. Development of semiconductor electronics

    International Nuclear Information System (INIS)

    Bardeen, John.

    1977-01-01

    In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

  8. Manufacturing of planar ceramic interconnects

    Energy Technology Data Exchange (ETDEWEB)

    Armstrong, B.L.; Coffey, G.W.; Meinhardt, K.D.; Armstrong, T.R. [Pacific Northwest National Lab., Richland, WA (United States)

    1996-12-31

    The fabrication of ceramic interconnects for solid oxide fuel cells (SOFC) and separator plates for electrochemical separation devices has been a perennial challenge facing developers. Electrochemical vapor deposition (EVD), plasma spraying, pressing, tape casting and tape calendering are processes that are typically utilized to fabricate separator plates or interconnects for the various SOFC designs and electrochemical separation devices. For sake of brevity and the selection of a planar fuel cell or gas separation device design, pressing will be the only fabrication technique discussed here. This paper reports on the effect of the characteristics of two doped lanthanum manganite powders used in the initial studies as a planar porous separator for a fuel cell cathode and as a dense interconnect for an oxygen generator.

  9. Analysis and simulation of semiconductor devices

    CERN Document Server

    Selberherr, Siegfried

    1984-01-01

    The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

  10. Optical interconnection for a polymeric PLC device using simple positional alignment.

    Science.gov (United States)

    Ryu, Jin Hwa; Kim, Po Jin; Cho, Cheon Soo; Lee, El-Hang; Kim, Chang-Seok; Jeong, Myung Yung

    2011-04-25

    This study proposes a simple cost-effective method of optical interconnection between a planar lightwave circuit (PLC) device chip and an optical fiber. It was conducted to minimize and overcome the coupling loss caused by lateral offset which is due to the process tolerance and the dimensional limitation existing between PLC device chips and fiber array blocks with groove structures. A PLC device chip and a fiber array block were simultaneously fabricated in a series of polymer replication processes using the original master. The dimensions (i.e., width and thickness) of the under-clad of the PLC device chip were identical to those of the fiber array block. The PLC device chip and optical fiber were aligned by simple positional control for the vertical direction of the PLC device chip under a particular condition. The insertion loss of the proposed 1 x 2 multimode optical splitter device interconnection was 4.0 dB at 850 nm and the coupling loss was below 0.1 dB compared with single-fiber based active alignment.

  11. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  12. Cellular structures with interconnected microchannels

    Science.gov (United States)

    Shaefer, Robert Shahram; Ghoniem, Nasr M.; Williams, Brian

    2018-01-30

    A method for fabricating a cellular tritium breeder component includes obtaining a reticulated carbon foam skeleton comprising a network of interconnected ligaments. The foam skeleton is then melt-infiltrated with a tritium breeder material, for example, lithium zirconate or lithium titanate. The foam skeleton is then removed to define a cellular breeder component having a network of interconnected tritium purge channels. In an embodiment the ligaments of the foam skeleton are enlarged by adding carbon using chemical vapor infiltration (CVI) prior to melt-infiltration. In an embodiment the foam skeleton is coated with a refractory material, for example, tungsten, prior to melt infiltration.

  13. Microtexture of Strain in electroplated copper interconnects

    International Nuclear Information System (INIS)

    Spolenak, R.; Barr, D.L.; Gross, M.E.; Evans-Lutterodt, K.; Brown, W.L.; Tamura, N.; MacDowell, A.A.; Celestre, R.S.; Padmore, H.A.; Valek, B.C.; Bravman, J.C.; Flinn, P.; Marieb, T.; Keller, R.R.; Batterman, B.W.; Patel, J.R.

    2001-01-01

    The microstructure of narrow metal conductors in the electrical interconnections on IC chips has often been identified as of major importance in the reliability of these devices. The stresses and stress gradients that develop in the conductors as a result of thermal expansion differences in the materials and of electromigration at high current densities are believed to be strongly dependent on the details of the grain structure. The present work discusses new techniques based on microbeam x-ray diffraction (MBXRD) that have enabled measurement not only of the microstructure of totally encapsulated conductors but also of the local stresses in them on a micron and submicron scale. White x-rays from the Advanced Light Source were focused to a micron spot size by Kirkpatrick-Baez mirrors. The sample was stepped under the micro-beam and Laue images obtained at each sample location using a CCD area detector. Microstructure and local strain were deduced from these images. Cu lines with widths ranging from 0.8 mm to 5 mm and thickness of 1 mm were investigated. Comparisons are made between the capabilities of MBXRD and the well established techniques of broad beam XRD, electron back scatter diffraction (EBSD) and focused ion beam imagining (FIB)

  14. Semiconductor sensors

    International Nuclear Information System (INIS)

    Hartmann, Frank

    2011-01-01

    Semiconductor sensors have been around since the 1950s and today, every high energy physics experiment has one in its repertoire. In Lepton as well as Hadron colliders, silicon vertex and tracking detectors led to the most amazing physics and will continue doing so in the future. This contribution tries to depict the history of these devices exemplarily without being able to honor all important developments and installations. The current understanding of radiation damage mechanisms and recent R and D topics demonstrating the future challenges and possible technical solutions for the SLHC detectors are presented. Consequently semiconductor sensor candidates for an LHC upgrade and a future linear collider are also briefly introduced. The work presented here is a collage of the work of many individual silicon experts spread over several collaborations across the world.

  15. Semiconductor Optics

    CERN Document Server

    Klingshirn, Claus F

    2012-01-01

    This updated and enlarged new edition of Semiconductor Optics provides an introduction to and an overview of semiconductor optics from the IR through the visible to the UV, including linear and nonlinear optical properties, dynamics, magneto and electrooptics, high-excitation effects and laser processes, some applications, experimental techniques and group theory. The mathematics is kept as elementary as possible, sufficient for an intuitive understanding of the experimental results and techniques treated. The subjects covered extend from physics to materials science and optoelectronics. Significantly updated chapters add coverage of current topics such as electron hole plasma, Bose condensation of excitons and meta materials. Over 120 problems, chapter introductions and a detailed index make it the key textbook for graduate students in physics. The mathematics is kept as elementary as possible, sufficient for an intuitive understanding of the experimental results and techniques treated. The subjects covered ...

  16. High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-07-30

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  17. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  18. Semiconductor annealing

    International Nuclear Information System (INIS)

    Young, J.M.; Scovell, P.D.

    1982-01-01

    A process for annealing crystal damage in ion implanted semiconductor devices in which the device is rapidly heated to a temperature between 450 and 900 0 C and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device may be heated on a graphite element mounted between electrodes in an inert atmosphere in a chamber. (author)

  19. Fusion-bonded fluidic interconnects

    NARCIS (Netherlands)

    Fazal, I.; Elwenspoek, Michael Curt

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are

  20. Nanophotonic Devices for Optical Interconnect

    DEFF Research Database (Denmark)

    Van Thourhout, D.; Spuesens, T.; Selvaraja, S.K.

    2010-01-01

    We review recent progress in nanophotonic devices for compact optical interconnect networks. We focus on microdisk-laser-based transmitters and discuss improved design and advanced functionality including all-optical wavelength conversion and flip-flops. Next we discuss the fabrication uniformity...... of the passive routing circuits and their thermal tuning. Finally, we discuss the performance of a wavelength selective detector....

  1. Regulatory Issues Surrounding Merchant Interconnection

    International Nuclear Information System (INIS)

    Kuijlaars, Kees-Jan; Zwart, Gijsbert

    2003-11-01

    We discussed various issues concerning the regulatory perspective on private investment in interconnectors. One might claim that leaving investment in transmission infrastructure to competing market parties is more efficient than relying on regulated investment only (especially in the case of long (DC) lines connecting previously unconnected parts of the grids, so that externalities from e.g. loop flows do not play a significant role). We considered that some aspects of interconnection might reduce these market benefits. In particular, the large fixed costs of interconnection construction may lead to significant under investment (due to both first mover monopoly power and the fact that part of generation cost efficiencies realised by interconnection are not captured by the investor itself, and remain external to the investment decision). Second, merchant ownership restricts future opportunities for adaptation of regulation, as would be required e.g. for introduction of potentially more sophisticated methods of congestion management or market splitting. Some of the disadvantages of merchant investment may be mitigated however by a suitable regulatory framework, and we discussed some views in this direction. The issues we discussed are not intended to give a complete framework, and detailed regulation will certainly involve many more specific requirements. Areas we did not touch upon include e.g. the treatment of deep connection costs, rules for operation and maintenance of the line, and impact on availability of capacity on other interconnections

  2. Regulatory Issues Surrounding Merchant Interconnection

    Energy Technology Data Exchange (ETDEWEB)

    Kuijlaars, Kees-Jan; Zwart, Gijsbert [Office for Energy Regulation (DTe), The Hague (Netherlands)

    2003-11-01

    We discussed various issues concerning the regulatory perspective on private investment in interconnectors. One might claim that leaving investment in transmission infrastructure to competing market parties is more efficient than relying on regulated investment only (especially in the case of long (DC) lines connecting previously unconnected parts of the grids, so that externalities from e.g. loop flows do not play a significant role). We considered that some aspects of interconnection might reduce these market benefits. In particular, the large fixed costs of interconnection construction may lead to significant under investment (due to both first mover monopoly power and the fact that part of generation cost efficiencies realised by interconnection are not captured by the investor itself, and remain external to the investment decision). Second, merchant ownership restricts future opportunities for adaptation of regulation, as would be required e.g. for introduction of potentially more sophisticated methods of congestion management or market splitting. Some of the disadvantages of merchant investment may be mitigated however by a suitable regulatory framework, and we discussed some views in this direction. The issues we discussed are not intended to give a complete framework, and detailed regulation will certainly involve many more specific requirements. Areas we did not touch upon include e.g. the treatment of deep connection costs, rules for operation and maintenance of the line, and impact on availability of capacity on other interconnections.

  3. Local Network Wideband Interconnection Alternatives.

    Science.gov (United States)

    1984-01-01

    signal. 3.2.2 Limitations Although satellites offer the advantages of insensitivity to distance, point-to-multipoint communication capability and...Russell, the CATV franchisee for the town of Bedford, has not yit set rates for leasing channels on their network. If this network were interconnected

  4. An RLC interconnect analyzable crosstalk model considering self-heating effect

    International Nuclear Information System (INIS)

    Zhu Zhang-Ming; Liu Shu-Bin

    2012-01-01

    According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance—inductance—capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal—oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits. (interdisciplinary physics and related areas of science and technology)

  5. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  6. Semiconductor annealing

    International Nuclear Information System (INIS)

    Young, J.M.; Scovell, P.D.

    1981-01-01

    A process for annealing crystal damage in ion implanted semiconductor devices is described in which the device is rapidly heated to a temperature between 450 and 600 0 C and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device may be heated on a graphite element mounted between electrodes in an inert atmosphere in a chamber. The process may be enhanced by the application of optical radiation from a Xenon lamp. (author)

  7. Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

    Science.gov (United States)

    Michaelides, Stylianos

    Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

  8. Incorporation of in-plane interconnects to reflow bonding for electrical functionality

    International Nuclear Information System (INIS)

    Moğulkoç, B; Jansen, H V; Ter Brake, H J M; Elwenspoek, M C

    2011-01-01

    Incorporation of in-plane electrical interconnects to reflow bonding is studied to provide electrical functionality to lab-on-a-chip or microfluidic devices. Reflow bonding is the packaging technology, in which glass tubes are joined to silicon substrates at elevated temperatures. The tubes are used to interface the silicon-based fluidic devices and are directly compatible with standard Swagelok® connectors. After the bonding, the electrically conductive lines will allow probing into the volume confined by the tube, where the fluidic device operates. Therefore methods for fabricating electrical interconnects that survive the bonding procedure at elevated temperature and do not alter the properties of the bond interface are investigated

  9. Semiconductor Laser Diode Pumps for Inertial Fusion Energy Lasers

    International Nuclear Information System (INIS)

    Deri, R.J.

    2011-01-01

    Solid-state lasers have been demonstrated as attractive drivers for inertial confinement fusion on the National Ignition Facility (NIF) at Lawrence Livermore National Laboratory (LLNL) and at the Omega Facility at the Laboratory for Laser Energetics (LLE) in Rochester, NY. For power plant applications, these lasers must be pumped by semiconductor diode lasers to achieve the required laser system efficiency, repetition rate, and lifetime. Inertial fusion energy (IFE) power plants will require approximately 40-to-80 GW of peak pump power, and must operate efficiently and with high system availability for decades. These considerations lead to requirements on the efficiency, price, and production capacity of the semiconductor pump sources. This document provides a brief summary of these requirements, and how they can be met by a natural evolution of the current semiconductor laser industry. The detailed technical requirements described in this document flow down from a laser ampl9ifier design described elsewhere. In brief, laser amplifiers comprising multiple Nd:glass gain slabs are face-pumped by two planar diode arrays, each delivering 30 to 40 MW of peak power at 872 nm during a ∼ 200 (micro)s quasi-CW (QCW) pulse with a repetition rate in the range of 10 to 20 Hz. The baseline design of the diode array employs a 2D mosaic of submodules to facilitate manufacturing. As a baseline, they envision that each submodule is an array of vertically stacked, 1 cm wide, edge-emitting diode bars, an industry standard form factor. These stacks are mounted on a common backplane providing cooling and current drive. Stacks are conductively cooled to the backplane, to minimize both diode package cost and the number of fluid interconnects for improved reliability. While the baseline assessment in this document is based on edge-emitting devices, the amplifier design does not preclude future use of surface emitting diodes, which may offer appreciable future cost reductions and

  10. 47 CFR 90.477 - Interconnected systems.

    Science.gov (United States)

    2010-10-01

    ... part and medical emergency systems in the 450-470 MHz band, interconnection will be permitted only... operating on frequencies in the bands below 800 MHz are not subject to the interconnection provisions of...

  11. Magnetic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Bihler, Christoph

    2009-04-15

    In this thesis we investigated in detail the properties of Ga{sub 1-x}Mn{sub x}As, Ga{sub 1-x}Mn{sub x}P, and Ga{sub 1-x}Mn{sub x}N dilute magnetic semiconductor thin films with a focus on the magnetic anisotropy and the changes of their properties upon hydrogenation. We applied two complementary spectroscopic techniques to address the position of H in magnetic semiconductors: (i) Electron paramagnetic resonance, which provides direct information on the symmetry of the crystal field of the Mn{sup 2+} atoms and (ii) x-ray absorption fine structure analysis which allows to probe the local crystallographic neighborhood of the absorbing Mn atom via analysing the fine structure at the Mn K absorption edge. Finally, we discussed the obstacles that have to be overcome to achieve Curie temperatures above the current maximum in Ga{sub 1-x}Mn{sub x}As of 185 K. Here, we outlined in detail the generic problem of the formation of precipitates at the example of Ge:MN. (orig.)

  12. Fusion-bonded fluidic interconnects

    International Nuclear Information System (INIS)

    Fazal, I; Elwenspoek, M C

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are discussed in terms of the homogeneity and strength of fusion bond. High pressure testing shows that the bond strength is large enough for most applications of fluidic interconnects. The bond strength for 525 µm thick silicon, with glass tubes having an outer diameter of 6 mm and with a wall thickness of 2 mm, is more than 60 bars after annealing at a temperature of 800 °C

  13. System interconnection studies using WASP

    Energy Technology Data Exchange (ETDEWEB)

    Bayrak, Y [Turkish Electricity Generation and Transmission Corp., Ankara (Turkey)

    1997-09-01

    The aim of this paper is to describe the application of WASP as a modelling tool for determining the development of two electric systems with interconnections. A case study has been carried out to determine the possibilities of transfer of baseload energy between Turkey and a neighboring country. The objective of this case study is to determine the amount of energy that can be transferred, variations of Loss Probability (LOLP) and unserved energy, and the cost of additional generation with interconnection. The break-even cost will be determined to obtain the minimum charge rate at which TEAS (Turkish Electricity Generation-Transmission Corp.) needs to sell the energy in order to recover the costs. The minimum charge rate for both capacity and energy will be estimated without considering extra capacity additions, except for the ones needed by the Turkish system alone. (author). 2 figs, 3 tabs.

  14. Multilevel Dual Damascene copper interconnections

    Science.gov (United States)

    Lakshminarayanan, S.

    Copper has been acknowledged as the interconnect material for future generations of ICs to overcome the bottlenecks on speed and reliability present with the current Al based wiring. A new set of challenges brought to the forefront when copper replaces aluminum, have to be met and resolved to make it a viable option. Unit step processes related to copper technology have been under development for the last few years. In this work, the application of copper as the interconnect material in multilevel structures with SiO2 as the interlevel dielectric has been explored, with emphasis on integration issues and complete process realization. Interconnect definition was achieved by the Dual Damascene approach using chemical mechanical polishing of oxide and copper. The choice of materials used as adhesion promoter/diffusion barrier included Ti, Ta and CVD TiN. Two different polish chemistries (NH4OH or HNO3 based) were used to form the interconnects. The diffusion barrier was removed during polishing (in the case of TiN) or by a post CMP etch (as with Ti or Ta). Copper surface passivation was performed using boron implantation and PECVD nitride encapsulation. The interlevel dielectric way composed of a multilayer stack of PECVD SiO2 and SixNy. A baseline process sequence which ensured the mechanical and thermal compatibility of the different unit steps was first created. A comprehensive test vehicle was designed and test structures were fabricated using the process flow developed. Suitable modifications were subsequently introduced in the sequence as and when processing problems were encountered. Electrical characterization was performed on the fabricated devices, interconnects, contacts and vias. The structures were subjected to thermal stressing to assess their stability and performance. The measurement of interconnect sheet resistances revealed lower copper loss due to dishing on samples polished using HNO3 based slurry. Interconnect resistances remained stable upto 400o

  15. Nanoantenna couplers for metal-insulator-metal waveguide interconnects

    Science.gov (United States)

    Onbasli, M. Cengiz; Okyay, Ali K.

    2010-08-01

    State-of-the-art copper interconnects suffer from increasing spatial power dissipation due to chip downscaling and RC delays reducing operation bandwidth. Wide bandwidth, minimized Ohmic loss, deep sub-wavelength confinement and high integration density are key features that make metal-insulator-metal waveguides (MIM) utilizing plasmonic modes attractive for applications in on-chip optical signal processing. Size-mismatch between two fundamental components (micron-size fibers and a few hundred nanometers wide waveguides) demands compact coupling methods for implementation of large scale on-chip optoelectronic device integration. Existing solutions use waveguide tapering, which requires more than 4λ-long taper distances. We demonstrate that nanoantennas can be integrated with MIM for enhancing coupling into MIM plasmonic modes. Two-dimensional finite-difference time domain simulations of antennawaveguide structures for TE and TM incident plane waves ranging from λ = 1300 to 1600 nm were done. The same MIM (100-nm-wide Ag/100-nm-wide SiO2/100-nm-wide Ag) was used for each case, while antenna dimensions were systematically varied. For nanoantennas disconnected from the MIM; field is strongly confined inside MIM-antenna gap region due to Fabry-Perot resonances. Major fraction of incident energy was not transferred into plasmonic modes. When the nanoantennas are connected to the MIM, stronger coupling is observed and E-field intensity at outer end of core is enhanced more than 70 times.

  16. Driving Interconnected Networks to Supercriticality

    Directory of Open Access Journals (Sweden)

    Filippo Radicchi

    2014-04-01

    Full Text Available Networks in the real world do not exist as isolated entities, but they are often part of more complicated structures composed of many interconnected network layers. Recent studies have shown that such mutual dependence makes real networked systems potentially exposed to atypical structural and dynamical behaviors, and thus there is an urgent necessity to better understand the mechanisms at the basis of these anomalies. Previous research has mainly focused on the emergence of atypical properties in relation to the moments of the intra- and interlayer degree distributions. In this paper, we show that an additional ingredient plays a fundamental role for the possible scenario that an interconnected network can face: the correlation between intra- and interlayer degrees. For sufficiently high amounts of correlation, an interconnected network can be tuned, by varying the moments of the intra- and interlayer degree distributions, in distinct topological and dynamical regimes. When instead the correlation between intra- and interlayer degrees is lower than a critical value, the system enters in a supercritical regime where dynamical and topological phases are no longer distinguishable.

  17. 18 CFR 292.306 - Interconnection costs.

    Science.gov (United States)

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any electric...

  18. Semiconductor Laser Measurements Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Semiconductor Laser Measurements Laboratory is equipped to investigate and characterize the lasing properties of semiconductor diode lasers. Lasing features such...

  19. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  20. Origin of high photoconductive gain in fully transparent heterojunction nanocrystalline oxide image sensors and interconnects.

    Science.gov (United States)

    Jeon, Sanghun; Song, Ihun; Lee, Sungsik; Ryu, Byungki; Ahn, Seung-Eon; Lee, Eunha; Kim, Young; Nathan, Arokia; Robertson, John; Chung, U-In

    2014-11-05

    A technique for invisible image capture using a photosensor array based on transparent conducting oxide semiconductor thin-film transistors and transparent interconnection technologies is presented. A transparent conducting layer is employed for the sensor electrodes as well as interconnection in the array, providing about 80% transmittance at visible-light wavelengths. The phototransistor is a Hf-In-Zn-O/In-Zn-O heterostructure yielding a high quantum-efficiency in the visible range. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

    Science.gov (United States)

    Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

    2015-09-01

    This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

  2. Dry etching technology for semiconductors

    CERN Document Server

    Nojiri, Kazuo

    2015-01-01

    This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

  3. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  4. 75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

    Science.gov (United States)

    2010-03-02

    ... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

  5. In-memory interconnect protocol configuration registers

    Energy Technology Data Exchange (ETDEWEB)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  6. In-memory interconnect protocol configuration registers

    Science.gov (United States)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  7. Metal-semiconductor interface in extreme temperature conditions

    International Nuclear Information System (INIS)

    Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

    2008-01-01

    We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

  8. Semiconductor laser shearing interferometer

    International Nuclear Information System (INIS)

    Ming Hai; Li Ming; Chen Nong; Xie Jiaping

    1988-03-01

    The application of semiconductor laser on grating shearing interferometry is studied experimentally in the present paper. The method measuring the coherence of semiconductor laser beam by ion etching double frequency grating is proposed. The experimental result of lens aberration with semiconductor laser shearing interferometer is given. Talbot shearing interferometry of semiconductor laser is also described. (author). 2 refs, 9 figs

  9. Epidemic spreading on interconnected networks.

    Science.gov (United States)

    Saumell-Mendiola, Anna; Serrano, M Ángeles; Boguñá, Marián

    2012-08-01

    Many real networks are not isolated from each other but form networks of networks, often interrelated in nontrivial ways. Here, we analyze an epidemic spreading process taking place on top of two interconnected complex networks. We develop a heterogeneous mean-field approach that allows us to calculate the conditions for the emergence of an endemic state. Interestingly, a global endemic state may arise in the coupled system even though the epidemics is not able to propagate on each network separately and even when the number of coupling connections is small. Our analytic results are successfully confronted against large-scale numerical simulations.

  10. TSOM method for semiconductor metrology

    Science.gov (United States)

    Attota, Ravikiran; Dixson, Ronald G.; Kramar, John A.; Potzick, James E.; Vladár, András E.; Bunday, Benjamin; Novak, Erik; Rudack, Andrew

    2011-03-01

    Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes. Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis, inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with potentially significant savings and yield improvements in manufacturing.

  11. Optical trapping with Bessel beams generated from semiconductor lasers

    International Nuclear Information System (INIS)

    Sokolovskii, G S; Dudelev, V V; Losev, S N; Soboleva, K K; Deryagin, A G; Kuchinskii, V I; Sibbett, W; Rafailov, E U

    2014-01-01

    In this paper, we study generation of Bessel beams from semiconductor lasers with high beam propagation parameter M 2 and their utilization for optical trapping and manipulation of microscopic particles including living cells. The demonstrated optical tweezing with diodegenerated Bessel beams paves the way to replace their vibronic-generated counterparts for a range of applications towards novel lab-on-a-chip configurations

  12. Chip-integrated optical power limiter based on an all-passive micro-ring resonator

    Science.gov (United States)

    Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

    2014-10-01

    Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

  13. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    KAUST Repository

    Sevilla, Galo T.

    2016-02-29

    Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  14. Optoelectronic integrated circuits utilising vertical-cavity surface-emitting semiconductor lasers

    International Nuclear Information System (INIS)

    Zakharov, S D; Fyodorov, V B; Tsvetkov, V V

    1999-01-01

    Optoelectronic integrated circuits with additional optical inputs/outputs, in which vertical-cavity surface-emitting (VCSE) lasers perform the data transfer functions, are considered. The mutual relationship and the 'affinity' between optical means for data transfer and processing, on the one hand, and the traditional electronic component base, on the other, are demonstrated in the case of implementation of three-dimensional interconnects with a high transmission capacity. Attention is drawn to the problems encountered when semiconductor injection lasers are used in communication lines. It is shown what role can be played by VCSE lasers in solving these problems. A detailed analysis is made of the topics relating to possible structural and technological solutions in the fabrication of single lasers and of their arrays, and also of the problems hindering integrating of lasers into emitter arrays. Considerable attention is given to integrated circuits with optoelectronic smart pixels. Various technological methods for vertical integration of GaAs VCSE lasers with the silicon substrate of a microcircuit (chip) are discussed. (review)

  15. Interconnect fatigue design for terrestrial photovoltaic modules

    Science.gov (United States)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1982-03-01

    The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field.

  16. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  17. Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

    Science.gov (United States)

    Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

    2018-08-01

    In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

  18. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  19. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

  20. Semiconductor nanostructures

    Energy Technology Data Exchange (ETDEWEB)

    Marstein Erik Stensrud

    2003-07-01

    This thesis presents a study of two material systems containing semiconductor nanocrystals, namely porous silicon (PSi) films and germanium (Ge) nanocrystals embedded in silicon dioxide (SiO2) films. The PSi films were made by anodic etching of silicon (Si) substrates in an electrolyte containing hydrofluoric acid. The PSi films were doped with erbium (Er) using two different doping methods. electrochemical doping and doping by immersing the PSi films in a solution containing Er. The resulting Er concentration profiles were investigated using scanning electron microscopy (SEN1) combined with energy dispersive X-ray analysis (EDS). The main subject of the work on PSi presented in this thesis was investigating and comparing these two doping methods. Ge nanocrystals were made by implanting Ge ions into Si02 films that were subsequently annealed. However. nanocrystal formation occurred only for certain sets of processing parameters. The dependence of the microstructure of the Ge implanted Si02 films on the processing parameters were therefore investigated. A range of methods were employed for these investigations, including transmission electron microscopy (TEM) combined with EDS, X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). The observed structures, ranging from Ge nanocrystals to voids with diameters of several tens of nanometers and Ge rich Si02 films without any nanocrystals is described. A model explaining the void formation is also presented. For certain sets of processing parameters. An accumulation of Ge at the Si-Si02 interface was observed. The effect of this accumulation on the electrical properties of MOS structures made from Ge implanted SiO2 films was investigated using CV-measurements. (Author)

  1. Visualizing interconnections among climate risks

    Science.gov (United States)

    Tanaka, K.; Yokohata, T.; Nishina, K.; Takahashi, K.; Emori, S.; Kiguchi, M.; Iseri, Y.; Honda, Y.; Okada, M.; Masaki, Y.; Yamamoto, A.; Shigemitsu, M.; Yoshimori, M.; Sueyoshi, T.; Hanasaki, N.; Ito, A.; Sakurai, G.; Iizumi, T.; Nishimori, M.; Lim, W. H.; Miyazaki, C.; Kanae, S.; Oki, T.

    2015-12-01

    It is now widely recognized that climate change is affecting various sectors of the world. Climate change impact on one sector may spread out to other sectors including those seemingly remote, which we call "interconnections of climate risks". While a number of climate risks have been identified in the Intergovernmental Panel on Climate Change (IPCC) Fifth Assessment Report (AR5), there has been no attempt to explore their interconnections comprehensively. Here we present a first and most exhaustive visualization of climate risks drawn based on a systematic literature survey. Our risk network diagrams depict that changes in the climate system impact natural capitals (terrestrial water, crop, and agricultural land) as well as social infrastructures, influencing the socio-economic system and ultimately our access to food, water, and energy. Our findings suggest the importance of incorporating climate risk interconnections into impact and vulnerability assessments and call into question the widely used damage function approaches, which address a limited number of climate change impacts in isolation. Furthermore, the diagram is useful to educate decision makers, stakeholders, and general public about cascading risks that can be triggered by the climate change. Socio-economic activities today are becoming increasingly more inter-dependent because of the rapid technological progress, urbanization, and the globalization among others. Equally complex is the ecosystem that is susceptible to climate change, which comprises interwoven processes affecting one another. In the context of climate change, a number of climate risks have been identified and classified according to regions and sectors. These reports, however, did not fully address the inter-relations among risks because of the complexity inherent in this issue. Climate risks may ripple through sectors in the present inter-dependent world, posing a challenge ahead of us to maintain the resilience of the system. It is

  2. Interconnect rise time in superconducting integrating circuits

    International Nuclear Information System (INIS)

    Preis, D.; Shlager, K.

    1988-01-01

    The influence of resistive losses on the voltage rise time of an integrated-circuit interconnection is reported. A distribution-circuit model is used to present the interconnect. Numerous parametric curves are presented based on numerical evaluation of the exact analytical expression for the model's transient response. For the superconducting case in which the series resistance of the interconnect approaches zero, the step-response rise time is longer but signal strength increases significantly

  3. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  4. Fundamentals of semiconductor devices

    CERN Document Server

    Lindmayer, Joseph

    1965-01-01

    Semiconductor properties ; semiconductor junctions or diodes ; transistor fundamentals ; inhomogeneous impurity distributions, drift or graded-base transistors ; high-frequency properties of transistors ; band structure of semiconductors ; high current densities and mechanisms of carrier transport ; transistor transient response and recombination processes ; surfaces, field-effect transistors, and composite junctions ; additional semiconductor characteristics ; additional semiconductor devices and microcircuits ; more metal, insulator, and semiconductor combinations for devices ; four-pole parameters and configuration rotation ; four-poles of combined networks and devices ; equivalent circuits ; the error function and its properties ; Fermi-Dirac statistics ; useful physical constants.

  5. Results on 3D interconnection from AIDA WP3

    Energy Technology Data Exchange (ETDEWEB)

    Moser, Hans-Günther, E-mail: hgm@hll.mpg.de

    2016-09-21

    From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

  6. A novel conductive-polymer-based integration process for high-performance flip-chip packages

    Science.gov (United States)

    Lohokare, Saurabh

    Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

  7. Fluidic interconnections for microfluidic systems: A new integrated fluidic interconnection allowing plug 'n' play functionality

    DEFF Research Database (Denmark)

    Perozziello, Gerardo; Bundgaard, Frederik; Geschke, Oliver

    2008-01-01

    A crucial challenge in packaging of microsystems is microfluidic interconnections. These have to seal the ports of the system, and have to provide the appropriate interface to other devices or the external environment. Integrated fluidic interconnections appear to be a good solution for interconn...... external metal ferrules and the system. Theoretical calculations are made to dimension and model the integrated fluidic interconnection. Leakage tests are performed on the interconnections, in order to experimentally confirm the model, and detect its limits....

  8. An efficient network for interconnecting remote monitoring instruments and computers

    International Nuclear Information System (INIS)

    Halbig, J.K.; Gainer, K.E.; Klosterbuer, S.F.

    1994-01-01

    Remote monitoring instrumentation must be connected with computers and other instruments. The cost and intrusiveness of installing cables in new and existing plants presents problems for the facility and the International Atomic Energy Agency (IAEA). The authors have tested a network that could accomplish this interconnection using mass-produced commercial components developed for use in industrial applications. Unlike components in the hardware of most networks, the components--manufactured and distributed in North America, Europe, and Asia--lend themselves to small and low-powered applications. The heart of the network is a chip with three microprocessors and proprietary network software contained in Read Only Memory. In addition to all nonuser levels of protocol, the software also contains message authentication capabilities. This chip can be interfaced to a variety of transmission media, for example, RS-485 lines, fiber topic cables, rf waves, and standard ac power lines. The use of power lines as the transmission medium in a facility could significantly reduce cabling costs

  9. Production and characterisation of SLID interconnected n-in-p pixel modules with 75 μm thin silicon sensors

    Energy Technology Data Exchange (ETDEWEB)

    Andricek, L. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Beimforde, M.; Macchiolo, A.; Moser, H.-G. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Nisius, R., E-mail: Richard.Nisius@mpp.mpg.de [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Richter, R.H. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Terzo, S.; Weigell, P. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany)

    2014-09-11

    The performance of pixel modules built from 75 μm thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 μm thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of 10{sup 16}n{sub eq}/cm{sup 2}.

  10. Interconnection blocks with minimal dead volumes permitting planar interconnection to thin microfluidic devices

    DEFF Research Database (Denmark)

    Sabourin, David; Snakenborg, Detlef; Dufva, Martin

    2010-01-01

    We have previously described 'Interconnection Blocks' which are re-usable, non-integrated PDMS blocks which allowing multiple, aligned and planar microfluidic interconnections. Here, we describe Interconnection Block versions with zero dead volumes that allow fluidic interfacing to flat or thin s...

  11. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    (clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic......Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

  12. Network interconnections: an architectural reference model

    NARCIS (Netherlands)

    Butscher, B.; Lenzini, L.; Morling, R.; Vissers, C.A.; Popescu-Zeletin, R.; van Sinderen, Marten J.; Heger, D.; Krueger, G.; Spaniol, O.; Zorn, W.

    1985-01-01

    One of the major problems in understanding the different approaches in interconnecting networks of different technologies is the lack of reference to a general model. The paper develops the rationales for a reference model of network interconnection and focuses on the architectural implications for

  13. Epidemics in interconnected small-world networks

    NARCIS (Netherlands)

    Liu, M.; Li, D.; Qin, P.; Liu, C.; Wang, H.; Wang, F.

    2015-01-01

    Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks

  14. Colligation, Or the Logical Inference of Interconnection

    DEFF Research Database (Denmark)

    Falster, Peter

    1998-01-01

    laws or assumptions. Yet interconnection as an abstract concept seems to be without scientific underpinning in pure logic. Adopting a historical viewpoint, our aim is to show that the reasoning of interconnection may be identified with a neglected kind of logical inference, called "colligation...

  15. Colligation or, The Logical Inference of Interconnection

    DEFF Research Database (Denmark)

    Franksen, Ole Immanuel; Falster, Peter

    2000-01-01

    laws or assumptions. Yet interconnection as an abstract concept seems to be without scientific underpinning in oure logic. Adopting a historical viewpoint, our aim is to show that the reasoning of interconnection may be identified with a neglected kind of logical inference, called "colligation...

  16. Adaptive Code Division Multiple Access Protocol for Wireless Network-on-Chip Architectures

    Science.gov (United States)

    Vijayakumaran, Vineeth

    Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol

  17. Direct Liquid Evaporation Chemical Vapor Deposition(DLE-CVD) of Nickel, Manganese and Copper-Based Thin Films for Interconnects in Three-Dimensional Microelectronic Systems

    OpenAIRE

    Li, Kecheng

    2016-01-01

    Electrical interconnects are an intrinsic part of any electronic system. These interconnects have to perform reliably under a wide range of environmental conditions and survive stresses induced from thermal, mechanical, corrosive and electrical factors. Semiconductor technology is predominantly planar in nature, posing a severe limitation to the degree of device integrations into systems such as micro-processors or memories. 3D transistor FinFET (Fin type Field Effect Transistors) has been us...

  18. SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

    Science.gov (United States)

    Fresh, D. L.; Adolphsen, J. W.

    1974-01-01

    A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

  19. Solid spectroscopy: semiconductors

    International Nuclear Information System (INIS)

    Silva, C.E.T.G. da

    1983-01-01

    Photoemission as technique of study of the semiconductor electronic structure is shortly discussed. Homogeneous and heterogeneous semiconductors, where volume and surface electronic structure, core levels and O and H chemisorption in GaAs, Schottky barrier are treated, respectively. Amorphous semiconductors are also discussed. (L.C.) [pt

  20. Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

    OpenAIRE

    Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.

    2001-01-01

    The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interco...

  1. Two-dimensional optoelectronic interconnect-processor and its operational bit error rate

    Science.gov (United States)

    Liu, J. Jiang; Gollsneider, Brian; Chang, Wayne H.; Carhart, Gary W.; Vorontsov, Mikhail A.; Simonis, George J.; Shoop, Barry L.

    2004-10-01

    Two-dimensional (2-D) multi-channel 8x8 optical interconnect and processor system were designed and developed using complementary metal-oxide-semiconductor (CMOS) driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the photodetector (PD) arrays with corresponding wavelengths. We performed operation and bit-error-rate (BER) analysis on this free-space integrated 8x8 VCSEL optical interconnects driven by silicon-on-sapphire (SOS) circuits. Pseudo-random bit stream (PRBS) data sequence was used in operation of the interconnects. Eye diagrams were measured from individual channels and analyzed using a digital oscilloscope at data rates from 155 Mb/s to 1.5 Gb/s. Using a statistical model of Gaussian distribution for the random noise in the transmission, we developed a method to compute the BER instantaneously with the digital eye-diagrams. Direct measurements on this interconnects were also taken on a standard BER tester for verification. We found that the results of two methods were in the same order and within 50% accuracy. The integrated interconnects were investigated in an optoelectronic processing architecture of digital halftoning image processor. Error diffusion networks implemented by the inherently parallel nature of photonics promise to provide high quality digital halftoned images.

  2. Semiconductor detectors with proximity signal readout

    International Nuclear Information System (INIS)

    Asztalos, Stephen J.

    2012-01-01

    Semiconductor-based radiation detectors are routinely used for the detection, imaging, and spectroscopy of x-rays, gamma rays, and charged particles for applications in the areas of nuclear and medical physics, astrophysics, environmental remediation, nuclear nonproliferation, and homeland security. Detectors used for imaging and particle tracking are more complex in that they typically must also measure the location of the radiation interaction in addition to the deposited energy. In such detectors, the position measurement is often achieved by dividing or segmenting the electrodes into many strips or pixels and then reading out the signals from all of the electrode segments. Fine electrode segmentation is problematic for many of the standard semiconductor detector technologies. Clearly there is a need for a semiconductor-based radiation detector technology that can achieve fine position resolution while maintaining the excellent energy resolution intrinsic to semiconductor detectors, can be fabricated through simple processes, does not require complex electrical interconnections to the detector, and can reduce the number of required channels of readout electronics. Proximity electrode signal readout (PESR), in which the electrodes are not in physical contact with the detector surface, satisfies this need

  3. Superconducting detectors for semiconductor quantum photonics

    International Nuclear Information System (INIS)

    Reithmaier, Guenther M.

    2015-01-01

    In this thesis we present the first successful on-chip detection of quantum light, thereby demonstrating the monolithic integration of superconducting single photon detectors with individually addressable semiconductor quantum dots in a prototypical quantum photonic circuit. Therefore, we optimized both the deposition of high quality superconducting NbN thin films on GaAs substrates and the fabrication of superconducting detectors and successfully integrated these novel devices with GaAs/AlGaAs ridge waveguides loaded with self-assembled InGaAs quantum dots.

  4. Blasting detonators incorporating semiconductor bridge technology

    Energy Technology Data Exchange (ETDEWEB)

    Bickes, R.W. Jr.

    1994-05-01

    The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

  5. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  6. 11.72 sq cm SiC Wafer-scale Interconnected 64 kA PiN Diode

    Science.gov (United States)

    2012-01-30

    drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA2 -s. Preliminary development of high voltage interconnection...scale diode action (surge current integral), a key reliability parameter, exceeded 1.7 MA2 -s. Figure 6: The wafer-scale interconnected diode...scale diode was 382 J and the calculated action exceeded 1.7 MA2 -sec. High voltage operation of PiN diodes, thyristors, and other semiconductor

  7. Compound Semiconductor Radiation Detector

    International Nuclear Information System (INIS)

    Kim, Y. K.; Park, S. H.; Lee, W. G.; Ha, J. H.

    2005-01-01

    In 1945, Van Heerden measured α, β and γ radiations with the cooled AgCl crystal. It was the first radiation measurement using the compound semiconductor detector. Since then the compound semiconductor has been extensively studied as radiation detector. Generally the radiation detector can be divided into the gas detector, the scintillator and the semiconductor detector. The semiconductor detector has good points comparing to other radiation detectors. Since the density of the semiconductor detector is higher than that of the gas detector, the semiconductor detector can be made with the compact size to measure the high energy radiation. In the scintillator, the radiation is measured with the two-step process. That is, the radiation is converted into the photons, which are changed into electrons by a photo-detector, inside the scintillator. However in the semiconductor radiation detector, the radiation is measured only with the one-step process. The electron-hole pairs are generated from the radiation interaction inside the semiconductor detector, and these electrons and charged ions are directly collected to get the signal. The energy resolution of the semiconductor detector is generally better than that of the scintillator. At present, the commonly used semiconductors as the radiation detector are Si and Ge. However, these semiconductor detectors have weak points. That is, one needs thick material to measure the high energy radiation because of the relatively low atomic number of the composite material. In Ge case, the dark current of the detector is large at room temperature because of the small band-gap energy. Recently the compound semiconductor detectors have been extensively studied to overcome these problems. In this paper, we will briefly summarize the recent research topics about the compound semiconductor detector. We will introduce the research activities of our group, too

  8. SSC [Superconducting Super Collider] magnet mechanical interconnections

    International Nuclear Information System (INIS)

    Bossert, R.C.; Niemann, R.C.; Carson, J.A.; Ramstein, W.L.; Reynolds, M.P.; Engler, N.H.

    1989-03-01

    Installation of superconducting accelerator dipole and quadrupole magnets and spool pieces in the SSC tunnel requires the interconnection of the cryostats. The connections are both of an electrical and mechanical nature. The details of the mechanical connections are presented. The connections include piping, thermal shields and insulation. There are seven piping systems to be connected. These systems must carry cryogenic fluids at various pressures or maintain vacuum and must be consistently leak tight. The interconnection region must be able to expand and contract as magnets change in length while cooling and warming. The heat leak characteristics of the interconnection region must be comparable to that of the body of the magnet. Rapid assembly and disassembly is required. The magnet cryostat development program is discussed. Results of quality control testing are reported. Results of making full scale interconnections under magnet test situations are reviewed. 11 figs., 4 tabs

  9. Optical Interconnects for Future Data Center Networks

    CERN Document Server

    Bergman, Keren; Tomkos, Ioannis

    2013-01-01

    Optical Interconnects for Future Data Center Networks covers optical networks and how they can provide high bandwidth, energy efficient interconnects with increased communication bandwidth. This volume, with contributions from leading researchers in the field, presents an integrated view of the expected future requirements of data centers and serves as a reference for some of the most advanced and promising solutions proposed by researchers from leading universities, research labs, and companies. The work also includes several novel architectures, each demonstrating different technologies such as optical circuits, optical switching, MIMO optical OFDM, and others. Additionally, Optical Interconnects for Future Data Center Networks provides invaluable insights into the benefits and advantages of optical interconnects and how they can be a promising alternative for future data center networks.

  10. The Interconnections of the LHC Cryomagnets

    CERN Document Server

    Jacquemod, A; Skoczen, Blazej; Tock, J P

    2001-01-01

    The main components of the LHC, the next world-class facility in high-energy physics, are the twin-aperture high-field superconducting cryomagnets to be installed in the existing 26.7-km long tunnel. After installation and alignment, the cryomagnets have to be interconnected. The interconnections must ensure the continuity of several functions: vacuum enclosures, beam pipe image currents (RF contacts), cryogenic circuits, electrical power supply, and thermal insulation. In the machine, about 1700 interconnections between cryomagnets are necessary. The interconnections constitute a unique system that is nearly entirely assembled in the tunnel. For each of them, various operations must be done: TIG welding of cryogenic channels (~ 50 000 welds), induction soldering of main superconducting cables (~ 10 000 joints), ultrasonic welding of auxiliary superconducting cables (~ 20 000 welds), mechanical assembly of various elements, and installation of the multi-layer insulation (~ 200 000 m2). Defective junctions cou...

  11. Recent Development of SOFC Metallic Interconnect

    Energy Technology Data Exchange (ETDEWEB)

    Wu JW, Liu XB

    2010-04-01

    Interest in solid oxide fuel cells (SOFC) stems from their higher e±ciencies and lower levels of emitted pollu- tants, compared to traditional power production methods. Interconnects are a critical part in SOFC stacks, which connect cells in series electrically, and also separate air or oxygen at the cathode side from fuel at the anode side. Therefore, the requirements of interconnects are the most demanding, i:e:, to maintain high elec- trical conductivity, good stability in both reducing and oxidizing atmospheres, and close coe±cient of thermal expansion (CTE) match and good compatibility with other SOFC ceramic components. The paper reviewed the interconnect materials, and coatings for metallic interconnect materials.

  12. Epidemics in interconnected small-world networks.

    Science.gov (United States)

    Liu, Meng; Li, Daqing; Qin, Pengju; Liu, Chaoran; Wang, Huijuan; Wang, Feilong

    2015-01-01

    Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks has rarely been considered. Here, we study the susceptible-infected-susceptible (SIS) model of epidemic spreading in a system comprising two interconnected small-world networks. We find that the epidemic threshold in such networks decreases when the rewiring probability of the component small-world networks increases. When the infection rate is low, the rewiring probability affects the global steady-state infection density, whereas when the infection rate is high, the infection density is insensitive to the rewiring probability. Moreover, epidemics in interconnected small-world networks are found to spread at different velocities that depend on the rewiring probability.

  13. Epidemics in interconnected small-world networks.

    Directory of Open Access Journals (Sweden)

    Meng Liu

    Full Text Available Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks has rarely been considered. Here, we study the susceptible-infected-susceptible (SIS model of epidemic spreading in a system comprising two interconnected small-world networks. We find that the epidemic threshold in such networks decreases when the rewiring probability of the component small-world networks increases. When the infection rate is low, the rewiring probability affects the global steady-state infection density, whereas when the infection rate is high, the infection density is insensitive to the rewiring probability. Moreover, epidemics in interconnected small-world networks are found to spread at different velocities that depend on the rewiring probability.

  14. Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

    Science.gov (United States)

    Pleros, Nikos; Maniotis, Pavlos; Alexoudi, Theonitsa; Fitsios, Dimitris; Vagionas, Christos; Papaioannou, Sotiris; Vyrsokinos, K.; Kanellos, George T.

    2014-03-01

    The processor-memory performance gap, commonly referred to as "Memory Wall" problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

  15. Estimate the thermomechanical fatigue life of two flip chip packages

    International Nuclear Information System (INIS)

    Pash, R.A.; Ullah, H.S.; Khan, M.Z.

    2005-01-01

    The continuing demand towards high density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology, ball grid array (BOA) and chip scale package (CSP). In such structures the most widely used flip chip interconnects are solder joints. The reliability of flip chip structures largely depends on the reliability of solder joints. In this work solder joint fatigue life prediction for two chip scale packages is carried out. Elasto-plastic deformation behavior of the solder was simulated using ANSYS. Two dimensional plain strain finite element models were developed for each package to numerically compute the stress and total strain of the solder joints under temperature cycling. These stress and strain values are then used to predict the solder joint lifetime through modified Coffin Manson equation. The effect of solder joint's distance from edge of silicon die on life of the package is explored. The solder joint fatigue response is modeled for a typical temperature cycling of -60 to 140 degree C. (author)

  16. Semiconductor apparatus and method of fabrication for a semiconductor apparatus

    NARCIS (Netherlands)

    2010-01-01

    The invention relates to a semiconductor apparatus (1) and a method of fabrication for a semiconductor apparatus (1), wherein the semiconductor apparatus (1) comprises a semiconductor layer (2) and a passivation layer (3), arranged on a surface of the semiconductor layer (2), for passivating the

  17. Epidemics spreading in interconnected complex networks

    International Nuclear Information System (INIS)

    Wang, Y.; Xiao, G.

    2012-01-01

    We study epidemic spreading in two interconnected complex networks. It is found that in our model the epidemic threshold of the interconnected network is always lower than that in any of the two component networks. Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. Theoretical analysis and simulation results show that, generally speaking, the epidemic size is not significantly affected by the inter-network correlation. In interdependent networks which can be viewed as a special case of interconnected networks, however, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant. -- Highlights: ► We study epidemic spreading in two interconnected complex networks. ► The epidemic threshold is lower than that in any of the two networks. And Interconnection correlation has impacts on threshold and average outbreak size. ► Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. ► We demonstrated and proved that Interconnection correlation does not affect epidemic size significantly. ► In interdependent networks, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant.

  18. Epidemics spreading in interconnected complex networks

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Y. [School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (Singapore); Institute of High Performance Computing, Agency for Science, Technology and Research (A-STAR), Singapore 138632 (Singapore); Xiao, G., E-mail: egxxiao@ntu.edu.sg [School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (Singapore)

    2012-09-03

    We study epidemic spreading in two interconnected complex networks. It is found that in our model the epidemic threshold of the interconnected network is always lower than that in any of the two component networks. Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. Theoretical analysis and simulation results show that, generally speaking, the epidemic size is not significantly affected by the inter-network correlation. In interdependent networks which can be viewed as a special case of interconnected networks, however, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant. -- Highlights: ► We study epidemic spreading in two interconnected complex networks. ► The epidemic threshold is lower than that in any of the two networks. And Interconnection correlation has impacts on threshold and average outbreak size. ► Detailed theoretical analysis is proposed which allows quick and accurate calculations of epidemic threshold and average outbreak/epidemic size. ► We demonstrated and proved that Interconnection correlation does not affect epidemic size significantly. ► In interdependent networks, impacts of inter-network correlation on the epidemic threshold and outbreak size are more significant.

  19. Semiconductor Physical Electronics

    CERN Document Server

    Li, Sheng

    2006-01-01

    Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

  20. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  1. Novel electrochemical approach to study corrosion mechanism of Al-Au wire-bond pad interconnections

    DEFF Research Database (Denmark)

    Elisseeva, O. V.; Bruhn, A.; Cerezo, J.

    2013-01-01

    A gold-aluminium material combination is typically employed as an interconnection for microelectronic devices. One of the reliability risks of such devices is that of corrosion of aluminium bond pads resulting from the galvanic coupling between an aluminium bond pad and a gold wire. The research...... presented in this manuscript focuses on studying bond pad corrosion by selecting an appropriate model system and a dedicated set of electrochemical and analytical experimental tools. Taking into account the complex three-dimensional structure and the small dimensions of Au-Al interconnections (around 50......-100 μm), a dedicated and novel experimental approach was developed. Au-Al covered silicon chips were developed under clean room conditions. Three-dimensional electrodes were mimicked as flat, two-dimensional bond pad model systems, allowing the use of microelectrochemical local probe techniques. Thin...

  2. Contacts to semiconductors

    International Nuclear Information System (INIS)

    Tove, P.A.

    1975-08-01

    Contacts to semiconductors play an important role in most semiconductor devices. These devices range from microelectronics to power components, from high-sensitivity light or radiation detectors to light-emitting of microwave-generating components. Silicon is the dominating material but compound semiconductors are increasing in importance. The following survey is an attempt to classify contact properties and the physical mechanisms involved, as well as fabrication methods and methods of investigation. The main interest is in metal-semiconductor type contacts where a few basic concepts are dealt with in some detail. (Auth.)

  3. Semiconductor Electrical Measurements Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Semiconductor Electrical Measurements Laboratory is a research laboratory which complements the Optical Measurements Laboratory. The laboratory provides for Hall...

  4. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  5. Solid-Phase Immunoassay of Polystyrene-Encapsulated Semiconductor Coreshells for Cardiac Marker Detection

    Directory of Open Access Journals (Sweden)

    Sanghee Kim

    2012-01-01

    Full Text Available A solid-phase immunoassay of polystyrene-encapsulated semiconductor nanoparticles was demonstrated for cardiac troponin I (cTnI detection. CdSe/ZnS coreshells were encapsulated with a carboxyl-functionalized polystyrene nanoparticle to capture the target antibody through a covalent bonding and to eliminate the photoblinking and toxicity of semiconductor luminescent immunosensor. The polystyrene-encapsulated CdSe/ZnS fluorophores on surface-modified glass chip identified cTnI antigens at the level of ~ng/mL. It was an initial demonstration of diagnostic chip for monitoring a cardiovascular disease.

  6. Development of a Ni-based superalloy with cellular structure and interconnected micro porosity

    International Nuclear Information System (INIS)

    Bernabe, A.; Lopez, E.; Gil-Sevillano, J.

    1998-01-01

    A cellular metallic material with interconnected porosity of controlled size of an order of 10 μm has been developed by electrochemical dissolution of tungsten grains in a W-Ni-Fe heavy alloy. The nickel superalloy with sponge structure and high surface/volume ratio can also be processed recycling chips from heavy metal machining (Patent number p9700191, 1997). Applications for the new materials could be found as support for catalysts, high temperature filters for corrosive fluids, burners, etc. (Author) 10 refs

  7. Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

    Science.gov (United States)

    Decrossas, Emmanuel; Glover, Michael D.; Porter, Kaoru; Cannon, Tom; Mantooth, H. Alan; Hamilton, M. C.

    2013-01-01

    Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

  8. Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

    CERN Document Server

    Macchiolo, A; Beimforde, M; Moser, H G; Nisius, R; Richter, R H

    2009-01-01

    We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.

  9. Deposition and characterisation of copper for high density interconnects

    International Nuclear Information System (INIS)

    McCusker, N.

    1999-09-01

    Copper has been deposited by sputtering and investigated for application as high density interconnects, with a view to maximising its performance and reliability. A sputter deposition process using gettering has been developed, which produces consistently pure, low resistivity films. A relationship between film thickness and resistivity has been explained by studying the grain growth process in copper films using atomic force microscopy. The Maydas-Shatzkes model has been used to separate the contributions of grain boundary and surface scattering to thin film resistivity, in copper and gold. Stress and texture in copper film have been studied. Annealing has been used to promote grain growth and texture development. Electromigration has been studied in copper and aluminium interconnects using a multi-line accelerated test set-up. A difference in failure distributions and void morphologies has been explained by an entirely different damage mechanism. The importance of surface/interface migration in electromigration damage of copper lines has been established and explained using a grain boundary-grooving model. A tantalum overlayer was found to extend the lifetime of copper lines. A composite sputtering target has been used to deposit copper/zirconium alloy films. The composition of the alloys was studied by Rutherford backscattering, Auger and secondary neutral mass spectrometry. The alloy films had an improved electromigration lifetime. A surface controlled mechanism is proposed to explain the advantage. A metal oxide semiconductor (MOS) capacitor technique is used to investigate barrier reliability. Tungsten is shown to be an effective diffusion barrier for copper, up to 700 deg. C. (author)

  10. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  11. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  12. Electronics Industry Study Report: Semiconductors and Defense Electronics

    Science.gov (United States)

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  13. Semiconductors data handbook

    CERN Document Server

    Madelung, Otfried

    2004-01-01

    This volume Semiconductors: Data Handbook contains frequently used data from the corresponding larger Landolt-Börnstein handbooks in a low price book for the individual scientist working in the laboratory. The Handbook contain important information about a large number of semiconductors

  14. Semiconductor radiation detection systems

    CERN Document Server

    2010-01-01

    Covers research in semiconductor detector and integrated circuit design in the context of medical imaging using ionizing radiation. This book explores other applications of semiconductor radiation detection systems in security applications such as luggage scanning, dirty bomb detection and border control.

  15. Spin physics in semiconductors

    CERN Document Server

    Dyakonov, Mikhail I

    2008-01-01

    This book describes beautiful optical and transport phenomena related to the electron and nuclear spins in semiconductors with emphasis on a clear presentation of the physics involved. Recent results on quantum wells and quantum dots are reviewed. The book is intended for students and researchers in the fields of semiconductor physics and nanoelectronics.

  16. Compound Semiconductor Radiation Detectors

    CERN Document Server

    Owens, Alan

    2012-01-01

    Although elemental semiconductors such as silicon and germanium are standard for energy dispersive spectroscopy in the laboratory, their use for an increasing range of applications is becoming marginalized by their physical limitations, namely the need for ancillary cooling, their modest stopping powers, and radiation intolerance. Compound semiconductors, on the other hand, encompass such a wide range of physical and electronic properties that they have become viable competitors in a number of applications. Compound Semiconductor Radiation Detectors is a consolidated source of information on all aspects of the use of compound semiconductors for radiation detection and measurement. Serious Competitors to Germanium and Silicon Radiation Detectors Wide-gap compound semiconductors offer the ability to operate in a range of hostile thermal and radiation environments while still maintaining sub-keV spectral resolution at X-ray wavelengths. Narrow-gap materials offer the potential of exceeding the spectral resolutio...

  17. Terahertz semiconductor nonlinear optics

    DEFF Research Database (Denmark)

    Turchinovich, Dmitry; Hvam, Jørn Märcher; Hoffmann, Matthias

    2013-01-01

    In this proceedings we describe our recent results on semiconductor nonlinear optics, investigated using single-cycle THz pulses. We demonstrate the nonlinear absorption and self-phase modulation of strong-field THz pulses in doped semiconductors, using n-GaAs as a model system. The THz...... nonlinearity in doped semiconductors originates from the near-instantaneous heating of free electrons in the ponderomotive potential created by electric field of the THz pulse, leading to ultrafast increase of electron effective mass by intervalley scattering. Modification of effective mass in turn leads...... to a decrease of plasma frequency in semiconductor and produces a substantial modification of THz-range material dielectric function, described by the Drude model. As a result, the nonlinearity of both absorption coefficient and refractive index of the semiconductor is observed. In particular we demonstrate...

  18. Organic semiconductor crystals.

    Science.gov (United States)

    Wang, Chengliang; Dong, Huanli; Jiang, Lang; Hu, Wenping

    2018-01-22

    Organic semiconductors have attracted a lot of attention since the discovery of highly doped conductive polymers, due to the potential application in field-effect transistors (OFETs), light-emitting diodes (OLEDs) and photovoltaic cells (OPVs). Single crystals of organic semiconductors are particularly intriguing because they are free of grain boundaries and have long-range periodic order as well as minimal traps and defects. Hence, organic semiconductor crystals provide a powerful tool for revealing the intrinsic properties, examining the structure-property relationships, demonstrating the important factors for high performance devices and uncovering fundamental physics in organic semiconductors. This review provides a comprehensive overview of the molecular packing, morphology and charge transport features of organic semiconductor crystals, the control of crystallization for achieving high quality crystals and the device physics in the three main applications. We hope that this comprehensive summary can give a clear picture of the state-of-art status and guide future work in this area.

  19. Comprehensive evaluation of global energy interconnection development index

    Science.gov (United States)

    Liu, Lin; Zhang, Yi

    2018-04-01

    Under the background of building global energy interconnection and realizing green and low-carbon development, this article constructed the global energy interconnection development index system which based on the current situation of global energy interconnection development. Through using the entropy method for the weight analysis of global energy interconnection development index, and then using gray correlation method to analyze the selected countries, this article got the global energy interconnection development index ranking and level classification.

  20. An integrated semiconductor device enabling non-optical genome sequencing.

    Science.gov (United States)

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  1. Carbon nanotube and graphene nanoribbon interconnects

    CERN Document Server

    Das, Debaprasad

    2014-01-01

    "The book, Caron Nanotube and Graphene Nanoribbon Interconnects, authored by Drs. Debapraad Das and Hafizur Rahaman serves as a good source of material on CNT and GNR interconnects for readers who wish to get into this area and also for practicing engineers who would like to be updated in advances of this field."-Prof. Ashok Srivastava, Louisiana State University, Baton Rouge, USA"Mathematical analysis included in each and every chapter is the main strength of the materials. ... The book is very precise and useful for those who are working in this area. ... highly focused, very compact, and easy to apply. ... This book depicts a detailed analysis and modelling of carbon nanotube and graphene nanoribbon interconnects. The book also covers the electrical circuit modelling of carbon nanotubes and graphene nanoribbons."-Prof. Chandan Kumar Sarkar, Jadavpur University, Kolkata, India.

  2. A Monolithic Interconnected module with a tunnel Junction for Enhanced Electrical and Optical Performance

    Energy Technology Data Exchange (ETDEWEB)

    Murray, Christopher Sean; Wilt, David Morgan

    1999-06-30

    An improved thermophotovoltaic (TPV) n/p/n device is provided. Monolithic Interconnected Modules (MIMs), semiconductor devices converting infrared radiation to electricity, have been developed with improved electrical and optical performance. The structure is an n-type emitter on a p-type base with an n-type lateral conduction layer. The incorporation of a tunnel junction and the reduction in the amount of p-type material used results in negligible parasitic absorption, decreased series resistance, increased voltage and increased active area. The novel use of a tunnel junction results in the potential for a TPV device with efficiency greater than 24%.

  3. Laser printing of 3D metallic interconnects

    Science.gov (United States)

    Beniam, Iyoel; Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Raymond C. Y.; Piqué, Alberto

    2016-04-01

    The use of laser-induced forward transfer (LIFT) techniques for the printing of functional materials has been demonstrated for numerous applications. The printing gives rise to patterns, which can be used to fabricate planar interconnects. More recently, various groups have demonstrated electrical interconnects from laser-printed 3D structures. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or of pastes containing dispersed metallic particles. However, the generated 3D structures do not posses the same metallic conductivity as a bulk metal interconnect of the same cross-section and length as those formed by wire bonding or tab welding. An alternative is to laser transfer entire 3D structures using a technique known as lase-and-place. Lase-and-place is a LIFT process whereby whole components and parts can be transferred from a donor substrate onto a desired location with one single laser pulse. This paper will describe the use of LIFT to laser print freestanding, solid metal foils or beams precisely over the contact pads of discrete devices to interconnect them into fully functional circuits. Furthermore, this paper will also show how the same laser can be used to bend or fold the bulk metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief for the circuits under flexing or during motion from thermal mismatch. These interconnect "ridges" can span wide gaps (on the order of a millimeter) and accommodate height differences of tens of microns between adjacent devices. Examples of these laser printed 3D metallic bridges and their role in the development of next generation electronics by additive manufacturing will be presented.

  4. Optical interconnect for large-scale systems

    Science.gov (United States)

    Dress, William

    2013-02-01

    This paper presents a switchless, optical interconnect module that serves as a node in a network of identical distribution modules for large-scale systems. Thousands to millions of hosts or endpoints may be interconnected by a network of such modules, avoiding the need for multi-level switches. Several common network topologies are reviewed and their scaling properties assessed. The concept of message-flow routing is discussed in conjunction with the unique properties enabled by the optical distribution module where it is shown how top-down software control (global routing tables, spanning-tree algorithms) may be avoided.

  5. Regulate or deregulate. Influencing network interconnection charges

    Energy Technology Data Exchange (ETDEWEB)

    Van De Wielle, B.

    2003-06-01

    We study the choice between regulating interconnection charges or delegating their determination to the operators, both in a non-mature and a mature market. Three regulatory regimes are considered: full, cost-based and bill-and-keep. Delegation corresponds to bargaining about the interconnection charges using the regulatory schemes as disagreement outcomes. Applying regulation benefits the consumers. Under full regulation, access charges account for asymmetries and allow a unique Ramsey price. Delegation benefits the operators. In a mature market delegation robs the government of any market influence. In a non-mature market government preferences coincide with those of the largest operator and are disadvantageous for entry.

  6. Digital optical interconnects for photonic computing

    Science.gov (United States)

    Guilfoyle, Peter S.; Stone, Richard V.; Zeise, Frederick F.

    1994-05-01

    A 32-bit digital optical computer (DOC II) has been implemented in hardware utilizing 8,192 free-space optical interconnects. The architecture exploits parallel interconnect technology by implementing microcode at the primitive level. A burst mode of 0.8192 X 1012 binary operations per sec has been reliably demonstrated. The prototype has been successful in demonstrating general purpose computation. In addition to emulating the RISC instruction set within the UNIX operating environment, relational database text search operations have been implemented on DOC II.

  7. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  8. Novel room temperature ferromagnetic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Gupta, Amita [KTH Royal Inst. of Technology, Stockholm (Sweden)

    2004-06-01

    Today's information world, bits of data are processed by semiconductor chips, and stored in the magnetic disk drives. But tomorrow's information technology may see magnetism (spin) and semiconductivity (charge) combined in one 'spintronic' device that exploits both charge and 'spin' to carry data (the best of two worlds). Spintronic devices such as spin valve transistors, spin light emitting diodes, non-volatile memory, logic devices, optical isolators and ultra-fast optical switches are some of the areas of interest for introducing the ferromagnetic properties at room temperature in a semiconductor to make it multifunctional. The potential advantages of such spintronic devices will be higher speed, greater efficiency, and better stability at a reduced power consumption. This Thesis contains two main topics: In-depth understanding of magnetism in Mn doped ZnO, and our search and identification of at least six new above room temperature ferromagnetic semiconductors. Both complex doped ZnO based new materials, as well as a number of nonoxides like phosphides, and sulfides suitably doped with Mn or Cu are shown to give rise to ferromagnetism above room temperature. Some of the highlights of this work are discovery of room temperature ferromagnetism in: (1) ZnO:Mn (paper in Nature Materials, Oct issue, 2003); (2) ZnO doped with Cu (containing no magnetic elements in it); (3) GaP doped with Cu (again containing no magnetic elements in it); (4) Enhancement of Magnetization by Cu co-doping in ZnO:Mn; (5) CdS doped with Mn, and a few others not reported in this thesis. We discuss in detail the first observation of ferromagnetism above room temperature in the form of powder, bulk pellets, in 2-3 mu-m thick transparent pulsed laser deposited films of the Mn (<4 at. percent) doped ZnO. High-resolution transmission electron microscopy (HRTEM) and electron energy loss spectroscopy (EELS) spectra recorded from 2 to 200nm areas showed homogeneous

  9. 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

    Directory of Open Access Journals (Sweden)

    Lee Mike Myung-Ok

    2006-01-01

    Full Text Available This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch through an indium bump interconnection array (IBIA. The configurable array processor (CAP is an array of heterogeneous processing elements (PEs, while the intelligent configurable switch (ICS comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

  10. Cancer and reproductive risks in the semiconductor industry.

    Science.gov (United States)

    LaDou, Joseph; Bailar, John C

    2007-01-01

    Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

  11. Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

    Science.gov (United States)

    Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

    2012-06-01

    The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

  12. Defects in semiconductors

    International Nuclear Information System (INIS)

    Pimentel, C.A.F.

    1983-01-01

    Some problems openned in the study of defects in semiconductors are presented. In particular, a review is made of the more important problems in Si monocrystals of basic and technological interest: microdefects and the presence of oxigen and carbon. The techniques usually utilized in the semiconductor material characterization are emphatized according its potentialities. Some applications of x-ray techniques in the epitaxial shell characterization in heterostructures, importants in electronic optics, are shown. The increase in the efficiency of these defect analysis methods in semiconductor materials with the use of synchrotron x-ray sources is shown. (L.C.) [pt

  13. Introduction to Semiconductor Devices

    Science.gov (United States)

    Brennan, Kevin F.

    2005-03-01

    This volume offers a solid foundation for understanding the most important devices used in the hottest areas of electronic engineering today, from semiconductor fundamentals to state-of-the-art semiconductor devices in the telecommunications and computing industries. Kevin Brennan describes future approaches to computing hardware and RF power amplifiers, and explains how emerging trends and system demands of computing and telecommunications systems influence the choice, design and operation of semiconductor devices. In addition, he covers MODFETs and MOSFETs, short channel effects, and the challenges faced by continuing miniaturization. His book is both an excellent senior/graduate text and a valuable reference for practicing engineers and researchers.

  14. Spin physics in semiconductors

    CERN Document Server

    2017-01-01

    This book offers an extensive introduction to the extremely rich and intriguing field of spin-related phenomena in semiconductors. In this second edition, all chapters have been updated to include the latest experimental and theoretical research. Furthermore, it covers the entire field: bulk semiconductors, two-dimensional semiconductor structures, quantum dots, optical and electric effects, spin-related effects, electron-nuclei spin interactions, Spin Hall effect, spin torques, etc. Thanks to its self-contained style, the book is ideally suited for graduate students and researchers new to the field.

  15. Physics of semiconductor lasers

    CERN Document Server

    Mroziewicz, B; Nakwaski, W

    2013-01-01

    Written for readers who have some background in solid state physics but do not necessarily possess any knowledge of semiconductor lasers, this book provides a comprehensive and concise account of fundamental semiconductor laser physics, technology and properties. The principles of operation of these lasers are therefore discussed in detail with the interrelations between their design and optical, electrical and thermal properties. The relative merits of a large number of laser structures and their parameters are described to acquaint the reader with the various aspects of the semiconductor l

  16. Semiconductors bonds and bands

    CERN Document Server

    Ferry, David K

    2013-01-01

    As we settle into this second decade of the twenty-first century, it is evident that the advances in micro-electronics have truly revolutionized our day-to-day lifestyle. The technology is built upon semiconductors, materials in which the band gap has been engineered for special values suitable to the particular application. This book, written specifically for a one semester course for graduate students, provides a thorough understanding of the key solid state physics of semiconductors. It describes how quantum mechanics gives semiconductors unique properties that enabled the micro-electronics revolution, and sustain the ever-growing importance of this revolution.

  17. Defects in semiconductors

    CERN Document Server

    Romano, Lucia; Jagadish, Chennupati

    2015-01-01

    This volume, number 91 in the Semiconductor and Semimetals series, focuses on defects in semiconductors. Defects in semiconductors help to explain several phenomena, from diffusion to getter, and to draw theories on materials' behavior in response to electrical or mechanical fields. The volume includes chapters focusing specifically on electron and proton irradiation of silicon, point defects in zinc oxide and gallium nitride, ion implantation defects and shallow junctions in silicon and germanium, and much more. It will help support students and scientists in their experimental and theoret

  18. Semiconductor laser joint study program with Rome Laboratory

    Science.gov (United States)

    Schaff, William J.; Okeefe, Sean S.; Eastman, Lester F.

    1994-09-01

    A program to jointly study vertical-cavity surface emitting lasers (VCSEL) for high speed vertical optical interconnects (VOI) has been conducted under an ES&E between Rome Laboratory and Cornell University. Lasers were designed, grown, and fabricated at Cornell University. A VCSEL measurement laboratory has been designed, built, and utilized at Rome Laboratory. High quality VCSEL material was grown and characterized by fabricating conventional lateral cavity lasers that emitted at the design wavelength of 1.04 microns. The VCSEL's emit at 1.06 microns. Threshold currents of 16 mA at 4.8 volts were obtained for 30 microns diameter devices. Output powers of 5 mW were measured. This is 500 times higher power than from the light emitting diodes employed previously for vertical optical interconnects. A new form of compositional grading using a cosinusoidal function has been developed and is very successful for reducing diode series resistance for high speed interconnection applications. A flip-chip diamond package compatible with high speed operation of 16 VCSEL elements has been designed and characterized. A flip-chip device binding effort at Rome Laboratory was also designed and initiated. This report presents details of the one-year effort, including process recipes and results.

  19. Electric network interconnection of Mashreq Arab Countries

    International Nuclear Information System (INIS)

    El-Amin, I.M.; Al-Shehri, A.M.; Opoku, G.; Al-Baiyat, S.A.; Zedan, F.M.

    1994-01-01

    Power system interconnection is a well established practice for a variety of technical and economical reasons. Several interconnected networks exist worldwide for a number of factors. Some of these networks cross international boundaries. This presentation discusses the future developments of the power systems of Mashreq Arab Countries (MAC). MAC consists of Bahrain, Egypt, Iraq, Jordan, Kuwait, Lebanon, Oman, Qatar, Saudi Arabia, United Arab Emirates (UAE), and Yemen. Mac power systems are operated by government or semigovernment bodies. Many of these countries have national or regional electric grids but are generally isolated from each other. With the exception of Saudi Arabia power systems, which employ 60 Hz, all other MAC utilities use 50 Hz frequency. Each country is served by one utility, except Saudi Arabia, which is served by four major utilities and some smaller utilities serving remote towns and small load centers. The major utilities are the Saudi Consolidated electric Company in the Eastern Province (SCECO East), SCECO Center, SCECO West, and SCECO South. These are the ones considered in this study. The energy resources in MAC are varied. Countries such as Egypt, Iraq, and Syria have significant hydro resources.The gulf countries and Iraq have abundant fossil fuel, The variation in energy resources as well as the characteristics of the electric load make it essential to look into interconnections beyond the national boundaries. Most of the existing or planned interconnections involve few power systems. A study involving 12 countries and over 20 utilities with different characteristics represents a very large scale undertaking

  20. Health and the environment: Examining some interconnections

    International Nuclear Information System (INIS)

    Nair, G.; Castelino, J.; Parr, R.M.

    1994-01-01

    In various ways, the IAEA is working with national and international agencies to broaden scientific understanding of the interconnections between the environment and human health. Often nuclear and related technologies are applied in the search for answers to complex and puzzling questions. This article highlights some of that work, illustrating the dimensions of both the problems and the potential solutions

  1. Systems theory of interconnected port contact systems

    NARCIS (Netherlands)

    Eberard, D.; Maschke, B.M.; Schaft, A.J. van der

    2005-01-01

    Port-based network modeling of a large class of complex physical systems leads to dynamical systems known as port-Hamiltonian systems. The key ingredient of any port-Hamiltonian system is a power-conserving interconnection structure (mathematically formalized by the geometric notion of a Dirac

  2. Experimental demonstration of titanium nitride plasmonic interconnects

    DEFF Research Database (Denmark)

    Kinsey, N.; Ferrera, M.; Naik, G. V.

    2014-01-01

    An insulator-metal-insulator plasmonic interconnect using TiN, a CMOS-compatible material, is proposed and investigated experimentally at the telecommunication wavelength of 1.55 mu m. The TiN waveguide was shown to obtain propagation losses less than 0.8 dB/mm with a mode size of 9.8 mu m...

  3. Nominate an Organization | Distributed Generation Interconnection

    Science.gov (United States)

    Collaborative | NREL Nominate an Organization Nominate an Organization Do you know of an organization doing high-quality, innovative work on the interconnection of distributed generation? Want to practices by nominating an organization to be profiled in an online case study! Please include your

  4. Patterned electrodeposition of interconnects using microcontact printing

    NARCIS (Netherlands)

    Hovestad, A.; Rendering, H.; Maijenburg, A.W.

    2012-01-01

    Microcontact printing combined with electroless deposition is a potential low cost technique to make electrical interconnects for opto-electronic devices. Microcontact printed inhibitors locally prevent electroless deposition resulting in a pre-defined pattern of metal tracks. The inhibition of

  5. An architectural model for network interconnection

    NARCIS (Netherlands)

    van Sinderen, Marten J.; Vissers, C.A.; Kalin, T.

    1983-01-01

    This paper presents a technique of successive decomposition of a common users' activity to illustrate the problems of network interconnection. The criteria derived from this approach offer a structuring principle which is used to develop an architectural model that embeds heterogeneous subnetworks

  6. Identifying influential spreaders in interconnected networks

    International Nuclear Information System (INIS)

    Zhao, Dawei; Li, Lixiang; Huo, Yujia; Yang, Yixian; Li, Shudong

    2014-01-01

    Identifying the most influential spreaders in spreading dynamics is of the utmost importance for various purposes for understanding or controlling these processes. The existing relevant works are limited to a single network. Most real networks are actually not isolated, but typically coupled and affected by others. The properties of epidemic spreading have recently been found to have some significant differences in interconnected networks from those in a single network. In this paper, we focus on identifying the influential spreaders in interconnected networks. We find that the well-known k-shell index loses effectiveness; some insignificant spreaders in a single network become the influential spreaders in the whole interconnected networks while some influential spreaders become no longer important. The simulation results show that the spreading capabilities of the nodes not only depend on their influence for the network topology, but also are dramatically influenced by the spreading rate. Based on this perception, a novel index is proposed for measuring the influential spreaders in interconnected networks. We then support the efficiency of this index with numerical simulations. (paper)

  7. Laser printed interconnects for flexible electronics

    Science.gov (United States)

    Pique, Alberto; Beniam, Iyoel; Mathews, Scott; Charipar, Nicholas

    Laser-induced forward transfer (LIFT) can be used to generate microscale 3D structures for interconnect applications non-lithographically. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or dispersed metallic nanoparticles. However, the resulting 3D structures do not achieve the bulk conductivity of metal interconnects of the same cross-section and length as those formed by wire bonding or tab welding. It is possible, however, to laser transfer entire structures using a LIFT technique known as lase-and-place. Lase-and-place allows whole components and parts to be transferred from a donor substrate onto a desired location with one single laser pulse. This talk will present the use of LIFT to laser print freestanding solid metal interconnects to connect individual devices into functional circuits. Furthermore, the same laser can bend or fold the thin metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief due to flexing or thermal mismatch. Examples of these laser printed 3D metallic bridges and their role in the development of next generation flexible electronics by additive manufacturing will be presented. This work was funded by the Office of Naval Research (ONR) through the Naval Research Laboratory Basic Research Program.

  8. Key techniques for space-based solar pumped semiconductor lasers

    Science.gov (United States)

    He, Yang; Xiong, Sheng-jun; Liu, Xiao-long; Han, Wei-hua

    2014-12-01

    In space, the absence of atmospheric turbulence, absorption, dispersion and aerosol factors on laser transmission. Therefore, space-based laser has important values in satellite communication, satellite attitude controlling, space debris clearing, and long distance energy transmission, etc. On the other hand, solar energy is a kind of clean and renewable resources, the average intensity of solar irradiation on the earth is 1353W/m2, and it is even higher in space. Therefore, the space-based solar pumped lasers has attracted much research in recent years, most research focuses on solar pumped solid state lasers and solar pumped fiber lasers. The two lasing principle is based on stimulated emission of the rare earth ions such as Nd, Yb, Cr. The rare earth ions absorb light only in narrow bands. This leads to inefficient absorption of the broad-band solar spectrum, and increases the system heating load, which make the system solar to laser power conversion efficiency very low. As a solar pumped semiconductor lasers could absorb all photons with energy greater than the bandgap. Thus, solar pumped semiconductor lasers could have considerably higher efficiencies than other solar pumped lasers. Besides, solar pumped semiconductor lasers has smaller volume chip, simpler structure and better heat dissipation, it can be mounted on a small satellite platform, can compose satellite array, which can greatly improve the output power of the system, and have flexible character. This paper summarizes the research progress of space-based solar pumped semiconductor lasers, analyses of the key technologies based on several application areas, including the processing of semiconductor chip, the design of small and efficient solar condenser, and the cooling system of lasers, etc. We conclude that the solar pumped vertical cavity surface-emitting semiconductor lasers will have a wide application prospects in the space.

  9. Review of Interconnection Practices and Costs in the Western States

    Energy Technology Data Exchange (ETDEWEB)

    Bird, Lori A [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Flores-Espino, Francisco [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Volpi, Christina M [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ardani, Kristen B [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Manning, David [Western Interstate Energy Board (WIEB); McAllister, Richard [Western Interstate Energy Board (WIEB)

    2018-04-27

    The objective of this report is to evaluate the nature of barriers to interconnecting distributed PV, assess costs of interconnection, and compare interconnection practices across various states in the Western Interconnection. The report addresses practices for interconnecting both residential and commercial-scale PV systems to the distribution system. This study is part of a larger, joint project between the Western Interstate Energy Board (WIEB) and the National Renewable Energy Laboratory (NREL), funded by the U.S. Department of Energy, to examine barriers to distributed PV in the 11 states wholly within the Western Interconnection.

  10. Biggest semiconductor installed

    CERN Multimedia

    2008-01-01

    Scientists and technicians at the European Laboratory for Particle Physics, commonly known by its French acronym CERN (Centre Europen pour la Recherche Nuclaire), have completed the installation of the largest semiconductor silicon detector.

  11. Compact semiconductor lasers

    CERN Document Server

    Yu, Siyuan; Lourtioz, Jean-Michel

    2014-01-01

    This book brings together in a single volume a unique contribution by the top experts around the world in the field of compact semiconductor lasers to provide a comprehensive description and analysis of the current status as well as future directions in the field of micro- and nano-scale semiconductor lasers. It is organized according to the various forms of micro- or nano-laser cavity configurations with each chapter discussing key technical issues, including semiconductor carrier recombination processes and optical gain dynamics, photonic confinement behavior and output coupling mechanisms, carrier transport considerations relevant to the injection process, and emission mode control. Required reading for those working in and researching the area of semiconductors lasers and micro-electronics.

  12. Radiation effects in semiconductors

    CERN Document Server

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  13. Market survey of semiconductors

    International Nuclear Information System (INIS)

    Mackintosh, I.M.; Diegel, D.; Brown, A.; Brinker, C.S. den

    1977-06-01

    Examination of technology and product trends over the range of current and future products in integrated circuits and optoelectronic displays. Analysis and forecast of major economic influences that affect the production costs of integrated circuits and optoelectronic displays. Forecast of the applications and markets for integrated circuits up to 1985 in West Europe, the USA and Japan. Historic development of the semiconductor industry and the prevailing tendencies - factors which influence success in the semiconductor industry. (orig.) [de

  14. Electronic properties of semiconductor heterostructures

    International Nuclear Information System (INIS)

    Einevoll, G.T.

    1991-02-01

    Ten papers on the electronic properties of semiconductors and semiconductor heterostructures constitute the backbone of this thesis. Four papers address the form and validity of the single-band effective mass approximation for semiconductor heterostructures. In four other papers properties of acceptor states in bulk semiconductors and semiconductor heterostructures are studied using the novel effective bond-orbital model. The last two papers deal with localized excitions. 122 refs

  15. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  16. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    NARCIS (Netherlands)

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be

  17. Sensor development at the semiconductor laboratory of the Max-Planck-Society

    Science.gov (United States)

    Bähr, A.; Lechner, P.; Ninkovic, J.

    2017-12-01

    For more than twenty years the semiconductor laboratory of the Max-Planck Society (MPG-HLL) is developing high-performing, specialised, scientific silicon sensors including the integration of amplifying electronics on the sensor chip. This paper summarises the actual status of these devices like pnCCDs and DePFET Active Pixel Sensors and their applications.

  18. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  19. Photonics-on-a-chip: recent advances in integrated waveguides as enabling detection elements for real-world, lab-on-a-chip biosensing applications.

    Science.gov (United States)

    Washburn, Adam L; Bailey, Ryan C

    2011-01-21

    By leveraging advances in semiconductor microfabrication technologies, chip-integrated optical biosensors are poised to make an impact as scalable and multiplexable bioanalytical measurement tools for lab-on-a-chip applications. In particular, waveguide-based optical sensing technology appears to be exceptionally amenable to chip integration and miniaturization, and, as a result, the recent literature is replete with examples of chip-integrated waveguide sensing platforms developed to address a wide range of contemporary analytical challenges. As an overview of the most recent advances within this dynamic field, this review highlights work from the last 2-3 years in the areas of grating-coupled, interferometric, photonic crystal, and microresonator waveguide sensors. With a focus towards device integration, particular emphasis is placed on demonstrations of biosensing using these technologies within microfluidically controlled environments. In addition, examples of multiplexed detection and sensing within complex matrices--important features for real-world applicability--are given special attention.

  20. National Offshore Wind Energy Grid Interconnection Study Executive Summary

    Energy Technology Data Exchange (ETDEWEB)

    Daniel, John P. [ABB, Inc., Cary, NC (United States); Liu, Shu [ABB, Inc., Cary, NC (United States); Ibanez, Eduardo [National Renewable Energy Lab. (NREL), Golden, CO (United States); Pennock, Ken [AWS Truepower, Albany, NY (United States); Reed, Gregory [Univ. of Pittsburgh, PA (United States); Hanes, Spencer [Duke Energy, Charlotte, NC (United States)

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States.

  1. Development and operation of interconnections in a restructuring context

    International Nuclear Information System (INIS)

    2003-01-01

    In many countries the electrical network is not fully interconnected and the best technical solution to achieve interconnection has to be found. At the same time the electricity industry is being restructured and interconnecting independent energy markets presents technical challenges. It is therefore timely to consider interconnection development and operation options: examine the benefits of interconnecting electrical networks and the development strategies, review the interconnection design options and the technologies available, identify the operational issues, the security problems of large interconnected systems, the protection issues, consider the impact of the restructuring of the electrical supply industry, assess the political, environmental and social implications of interconnections. reorganized in slovenia from 5-7 april 2004. (author)

  2. National Offshore Wind Energy Grid Interconnection Study Full Report

    Energy Technology Data Exchange (ETDEWEB)

    Daniel, John P. [ABB, Inc., Cary, NC (United States); Liu, Shu [ABB, Inc., Cary, NC (United States); Ibanez, Eduardo [National Renewable Energy Lab. (NREL), Golden, CO (United States); Pennock, Ken [AWS Truepower, Albany, NY (United States); Reed, Gregory [Univ. of Pittsburgh, PA (United States); Hanes, Spencer [Duke Energy, Charlotte, NC (United States)

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States.

  3. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  4. Optimal selection of TLD chips

    International Nuclear Information System (INIS)

    Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

    1996-01-01

    Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

  5. ADJUSTABLE CHIP HOLDER

    DEFF Research Database (Denmark)

    2009-01-01

    An adjustable microchip holder for holding a microchip is provided having a plurality of displaceable interconnection pads for connecting the connection holes of a microchip with one or more external devices or equipment. The adjustable microchip holder can fit different sizes of microchips...

  6. X-ray imaging with photon counting hybrid semiconductor pixel detectors

    CERN Document Server

    Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

    1999-01-01

    Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

  7. Characterization of a Cobalt-Tungsten Interconnect

    DEFF Research Database (Denmark)

    Harthøj, Anders; Holt, Tobias; Caspersen, Michael

    2012-01-01

    is to act both as a diffusion barrier for chromium and provide better protection against high temperature oxidation than a pure cobalt coating. This work presents a characterization of a cobalt-tungsten alloy coating electrodeposited on the ferritic steel Crofer 22 H which subsequently was oxidized in air......A ferritic steel interconnect for a solid oxide fuel cell must be coated in order to prevent chromium evaporation from the steel substrate. The Technical University of Denmark and Topsoe Fuel Cell have developed an interconnect coating based on a cobalt-tungsten alloy. The purpose of the coating...... for 300 h at 800 °C. The coating was characterized with Glow Discharge Optical Spectroscopy (GDOES), Scanning Electron Microscopy (SEM) and X-Ray Diffraction (XRD). The oxidation properties were evaluated by measuring weight change of coated samples of Crofer 22 H and Crofer 22 APU as a function...

  8. Interconnection of bundled solid oxide fuel cells

    Science.gov (United States)

    Brown, Michael; Bessette, II, Norman F; Litka, Anthony F; Schmidt, Douglas S

    2014-01-14

    A system and method for electrically interconnecting a plurality of fuel cells to provide dense packing of the fuel cells. Each one of the plurality of fuel cells has a plurality of discrete electrical connection points along an outer surface. Electrical connections are made directly between the discrete electrical connection points of adjacent fuel cells so that the fuel cells can be packed more densely. Fuel cells have at least one outer electrode and at least one discrete interconnection to an inner electrode, wherein the outer electrode is one of a cathode and and anode and wherein the inner electrode is the other of the cathode and the anode. In tubular solid oxide fuel cells the discrete electrical connection points are spaced along the length of the fuel cell.

  9. Copper Nanowire Production for Interconnect Applications

    Science.gov (United States)

    Han, Jin-Woo (Inventor); Meyyappan, Meyya (Inventor)

    2014-01-01

    A method of fabricating metallic Cu nanowires with lengths up to about 25 micrometers and diameters in a range 20-100 nanometers, or greater if desired. Vertically oriented or laterally oriented copper oxide structures (CuO and/or Cu2O) are grown on a Cu substrate. The copper oxide structures are reduced with 99+ percent H or H2, and in this reduction process the lengths decrease (to no more than about 25 micrometers), the density of surviving nanostructures on a substrate decreases, and the diameters of the surviving nanostructures have a range, of about 20-100 nanometers. The resulting nanowires are substantially pure Cu and can be oriented laterally (for local or global interconnects) or can be oriented vertically (for standard vertical interconnects).

  10. Accurate Modeling Method for Cu Interconnect

    Science.gov (United States)

    Yamada, Kenta; Kitahara, Hiroshi; Asai, Yoshihiko; Sakamoto, Hideo; Okada, Norio; Yasuda, Makoto; Oda, Noriaki; Sakurai, Michio; Hiroi, Masayuki; Takewaki, Toshiyuki; Ohnishi, Sadayuki; Iguchi, Manabu; Minda, Hiroyasu; Suzuki, Mieko

    This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

  11. Development of Interconnect Technologies for Particle Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Tripathi, Mani [Univ. of California, Davis, CA (United States)

    2015-01-29

    This final report covers the three years of this grant, for the funding period 9/1/2010 - 8/31/2013. The project consisted of generic detector R&D work at UC Davis, with an emphasis on developing interconnect technologies for applications in HEP. Much of the work is done at our Facility for Interconnect Technologies (FIT) at UC Davis. FIT was established using ARRA funds, with further studies supported by this grant. Besides generic R&D work at UC Davis, FIT is engaged in providing bump bonding help to several DOE supported detector R&D efforts. Some of the developmental work was also supported by funding from other sources: continuing CMS project funds and the Linear Collider R&D funds. The latter program is now terminated. The three year program saw a good deal of progress on several fronts, which are reported here.

  12. Interconnection of psychology, color and design

    OpenAIRE

    Minchuk, A. M.; Kudryashova, Aleksandra Vladimirovna

    2016-01-01

    The paper presents the direct interconnection between color, design and psychology on the basis of theoretical and historical analysis. It describes the peculiarities of how peopleperceive color. In the paper some of the historical details concerning the way our ancestors used color are presented and the modern scientific discoveries in the field of psychology, which give the evidence of the great psychological, emotional and physical influence of color on a person are shown as well. The pape...

  13. Viewing Integrated-Circuit Interconnections By SEM

    Science.gov (United States)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  14. Hybridization of active and passive elements for planar photonic components and interconnects

    Science.gov (United States)

    Pearson, M.; Bidnyk, S.; Balakrishnan, A.

    2007-02-01

    The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

  15. Digitally tunable dual wavelength emission from semiconductor ring lasers with filtered optical feedback

    International Nuclear Information System (INIS)

    Khoder, Mulham; Verschaffelt, Guy; Nguimdo, Romain Modeste; Danckaert, Jan; Leijtens, Xaveer; Bolk, Jeroen

    2013-01-01

    We report on a novel integrated approach to obtain dual wavelength emission from a semiconductor laser based on on-chip filtered optical feedback. Using this approach, we show experiments and numerical simulations of dual wavelength emission of a semiconductor ring laser. The filtered optical feedback is realized on-chip by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifiers are placed in the feedback loop in order to control the feedback strength of each wavelength channel independently. By tuning the current injected into each of the amplifiers, we can effectively cancel the gain difference between the wavelength channels due to fabrication and material dichroism, thus resulting in stable dual wavelength emission. We also explore the accuracy needed in the operational parameters to maintain this dual wavelength emission. (letter)

  16. The first LHC sector is fully interconnected

    CERN Multimedia

    2006-01-01

    Sector 7-8 is the first sector of the LHC to become fully operational. All the magnets, cryogenic line, vacuum chambers and services are interconnected. The cool down of this sector can soon commence. LHC project leader Lyn Evans, the teams from CERN's AT/MCS, AT/VAC and AT/MEL groups, and the members of the IEG consortium celebrate the completion of the first LHC sector. The 10th of November was a red letter day for the LHC accelerator teams, marking the completion of the first sector of the machine. The magnets of sector 7-8, together with the cryogenic line, the vacuum chambers and the distribution feedboxes (DFBs) are now all completely interconnected. Sector 7-8 has thus been closed and is the first LHC sector to become operational. The interconnection work required several thousand electrical, cryogenic and insulating connections to be made on the 210 interfaces between the magnets in the arc, the 30 interfaces between the special magnets and the interfaces with the cryogenic line. 'This represent...

  17. Implementation of interconnect simulation tools in spice

    Science.gov (United States)

    Satsangi, H.; Schutt-Aine, J. E.

    1993-01-01

    Accurate computer simulation of high speed digital computer circuits and communication circuits requires a multimode approach to simulate both the devices and the interconnects between devices. Classical circuit analysis algorithms (lumped parameter) are needed for circuit devices and the network formed by the interconnected devices. The interconnects, however, have to be modeled as transmission lines which incorporate electromagnetic field analysis. An approach to writing a multimode simulator is to take an existing software package which performs either lumped parameter analysis or field analysis and add the missing type of analysis routines to the package. In this work a traditionally lumped parameter simulator, SPICE, is modified so that it will perform lossy transmission line analysis using a different model approach. Modifying SPICE3E2 or any other large software package is not a trivial task. An understanding of the programming conventions used, simulation software, and simulation algorithms is required. This thesis was written to clarify the procedure for installing a device into SPICE3E2. The installation of three devices is documented and the installations of the first two provide a foundation for installation of the lossy line which is the third device. The details of discussions are specific to SPICE, but the concepts will be helpful when performing installations into other circuit analysis packages.

  18. The variability of interconnected wind plants

    International Nuclear Information System (INIS)

    Katzenstein, Warren; Fertig, Emily; Apt, Jay

    2010-01-01

    We present the first frequency-dependent analyses of the geographic smoothing of wind power's variability, analyzing the interconnected measured output of 20 wind plants in Texas. Reductions in variability occur at frequencies corresponding to times shorter than ∼24 h and are quantified by measuring the departure from a Kolmogorov spectrum. At a frequency of 2.8x10 -4 Hz (corresponding to 1 h), an 87% reduction of the variability of a single wind plant is obtained by interconnecting 4 wind plants. Interconnecting the remaining 16 wind plants produces only an additional 8% reduction. We use step change analyses and correlation coefficients to compare our results with previous studies, finding that wind power ramps up faster than it ramps down for each of the step change intervals analyzed and that correlation between the power output of wind plants 200 km away is half that of co-located wind plants. To examine variability at very low frequencies, we estimate yearly wind energy production in the Great Plains region of the United States from automated wind observations at airports covering 36 years. The estimated wind power has significant inter-annual variability and the severity of wind drought years is estimated to be about half that observed nationally for hydroelectric power.

  19. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  20. Method of doping a semiconductor

    International Nuclear Information System (INIS)

    Yang, C.Y.; Rapp, R.A.

    1983-01-01

    A method is disclosed for doping semiconductor material. An interface is established between a solid electrolyte and a semiconductor to be doped. The electrolyte is chosen to be an ionic conductor of the selected impurity and the semiconductor material and electrolyte are jointly chosen so that any compound formed from the impurity and the semiconductor will have a free energy no lower than the electrolyte. A potential is then established across the interface so as to allow the impurity ions to diffuse into the semiconductor. In one embodiment the semiconductor and electrolyte may be heated so as to increase the diffusion coefficient

  1. Energetic diversification in the interconnected electric system

    International Nuclear Information System (INIS)

    Villanueva M, C.; Beltran M, H.; Serrano G, J.A.

    2007-01-01

    In the interconnected electric system of Mexico the demanded electricity in different timetable periods it is synthesized in the annual curve of load duration, which is characterized by three regions. The energy in every period is quantified according to the under curve areas in each region, which depend of the number of hours in that the power demand exceeds the minimum and the intermediate demands respectively that are certain percentages of the yearly maximum demand. In that context, the generating power stations are dispatched according to the marginal costs of the produced electricity and the electric power to be generated every year by each type of central it is located in some of the regions of the curve of load duration, as they are their marginal costs and their operation characteristic techniques. By strategic reasons it is desirable to diversify the primary energy sources that are used in the national interconnected system to generate the electricity that demand the millions of consumers that there are in Mexico. On one hand, when intensifying the use of renewable sources and of nucleo electric centrals its decrease the import volumes of natural gas, which has very volatile prices and it is a fuel when burning in the power stations produces hothouse gases that are emitted to the atmosphere. On the other hand, when diversifying the installed capacity of the different central types in the interconnected system, a better adaptation of the produced electricity volumes is achieved by each type to the timetable variation, daily, weekly and seasonal of the electric demand, as one manifests this in the curve of load duration. To exemplify a possible diversification plan of the installed capacity in the national interconnected system that includes nucleo electric centrals and those that use renewable energy, charts are presented that project of 2005 at 2015 the capacity, energy and ost of the electricity of different central types, located in each one of the

  2. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  3. Semiconductor micro cavities: half light, half matter

    International Nuclear Information System (INIS)

    Baumberg, Jeremy J.

    2003-01-01

    World, Jeremy J Baumberg of the University of Southampton, UK, explains how semiconductor micro cavities could one day even be used as a new type of ultra-efficient light emitter for optoelectronic interconnects or quantum processors. (U.K.)

  4. Fundamentals of semiconductor lasers

    CERN Document Server

    Numai, Takahiro

    2015-01-01

    This book explains physics under the operating principles of semiconductor lasers in detail based on the experience of the author, dealing with the first manufacturing of phase-shifted DFB-LDs and recent research on transverse modes.   The book also bridges a wide gap between journal papers and textbooks, requiring only an undergraduate-level knowledge of electromagnetism and quantum mechanics, and helps readers to understand journal papers where definitions of some technical terms vary, depending on the paper. Two definitions of the photon density in the rate equations and two definitions of the phase-shift in the phase-shifted DFB-LD are explained, and differences in the calculated results are indicated, depending on the definitions.    Readers can understand the physics of semiconductor lasers and analytical tools for Fabry-Perot LDs, DFB-LDs, and VCSELs and will be stimulated to develop semiconductor lasers themselves.

  5. Coherent dynamics in semiconductors

    DEFF Research Database (Denmark)

    Hvam, Jørn Märcher

    1998-01-01

    enhanced in quantum confined lower-dimensional systems, where exciton and biexciton effects dominate the spectra even at room temperature. The coherent dynamics of excitons are at modest densities well described by the optical Bloch equations and a number of the dynamical effects known from atomic......Ultrafast nonlinear optical spectroscopy is used to study the coherent dynamics of optically excited electron-hole pairs in semiconductors. Coulomb interaction implies that the optical inter-band transitions are dominated, at least at low temperatures, by excitonic effects. They are further...... and molecular systems are found and studied in the exciton-biexciton system of semiconductors. At densities where strong exciton interactions, or many-body effects, become dominant, the semiconductor Bloch equations present a more rigorous treatment of the phenomena Ultrafast degenerate four-wave mixing is used...

  6. Hydrogen in semiconductors II

    CERN Document Server

    Nickel, Norbert H; Weber, Eicke R; Nickel, Norbert H

    1999-01-01

    Since its inception in 1966, the series of numbered volumes known as Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. The "Willardson and Beer" Series, as it is widely known, has succeeded in publishing numerous landmark volumes and chapters. Not only did many of these volumes make an impact at the time of their publication, but they continue to be well-cited years after their original release. Recently, Professor Eicke R. Weber of the University of California at Berkeley joined as a co-editor of the series. Professor Weber, a well-known expert in the field of semiconductor materials, will further contribute to continuing the series' tradition of publishing timely, highly relevant, and long-impacting volumes. Some of the recent volumes, such as Hydrogen in Semiconductors, Imperfections in III/V Materials, Epitaxial Microstructures, High-Speed Heterostructure Devices, Oxygen in Silicon, and others promise that this tradition ...

  7. Photoelectronic properties of semiconductors

    CERN Document Server

    Bube, Richard H

    1992-01-01

    The interaction between light and electrons in semiconductors forms the basis for many interesting and practically significant properties. This book examines the fundamental physics underlying this rich complexity of photoelectronic properties of semiconductors, and will familiarise the reader with the relatively simple models that are useful in describing these fundamentals. The basic physics is also illustrated with typical recent examples of experimental data and observations. Following introductory material on the basic concepts, the book moves on to consider a wide range of phenomena, including photoconductivity, recombination effects, photoelectronic methods of defect analysis, photoeffects at grain boundaries, amorphous semiconductors, photovoltaic effects and photoeffects in quantum wells and superlattices. The author is Professor of Materials Science and Electrical Engineering at Stanford University, and has taught this material for many years. He is an experienced author, his earlier books having fo...

  8. Modeling, Simulation and Design of Plasmonic Interconnects for On-Chip Signal Processing

    Science.gov (United States)

    2011-02-14

    Transactions on Nanotechnology. (already available in IEEE Xplore , though the paper version has not been scheduled yet). 7. K. Song, and P. Mazumder, “One...in Nanoelectronics and Plasmonics,” Proceedings on IEEE Conference on Nanotechnology, Cincinnati, July 2006. 2. K. Song and P. Mazumder, “Surface...Plasmon Dynamics of a Metallic Nanoparticle,” Proceedings on IEEE Conference on Nanotechnology, Hong Kong, Aug. 2007. 3. K. Song and P. Mazumder

  9. Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

    Directory of Open Access Journals (Sweden)

    Maged Ghoneima

    2007-01-01

    The proposed multicycle bus scheme also leads to significant energy savings due to eliminating the power-hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a  65-nm process environment indicate that energy savings up to 20% are achievable for a 6-cycle 9 mm long 16-bit bus.

  10. Integrated reconfigurable microring based silicon WDM receiver for on-chip optical interconnect

    International Nuclear Information System (INIS)

    Shen, Ao; Yang, Long-Zhi; Dai, Ting-Ge; Hao, Yin-Lei; Jiang, Xiao-Qing; Yang, Jian-Yi; Qiu, Chen

    2015-01-01

    We demonstrate an integrated reconfigurable wavelength division multiplexing receiver on the silicon-on-insulator (SOI) platform. The receiver is composed of a 1 × 8 thermally tunable microring resonator filter and Ge–Si photodetectors. With low thermal tuning powers the channel allocation of the receiver can be reconfigured with high accuracy and flexibility. The thermal tuning efficiency is approximately 8 mW nm −1 . We show eight-channel configurations with channel spacing of 100 GHz and 50 GHz and a configuration in which all eight channels cover an entire free spectral range of the ring with uniform channel spacing of 1.2 nm. Each channel can receive high-quality signals with a data rate of up to 13.5 Gb s −1 ; thus an aggregate data rate higher than 100 Gb s −1 can be achieved. (paper)

  11. Economic and environmental benefits of interconnected systems. The Spanish example

    International Nuclear Information System (INIS)

    Chicharro, A.S.; Dios Alija, R. de

    1996-01-01

    The interconnected systems provide large technical and economic benefits which, evaluated and contrasted with the associated network investment cost, usually produce important net savings. There are continental electrical systems formed by many interconnected subsystems. The optimal size of an interconnection should be defined within an economic background. It is necessary to take into account the global environmental effects. The approach and results of studies carried out by Red Electrica is presented, in order to analyse both economic and environmental benefits resulting from an increase in the present Spanish interconnection capacities. From both economic and environmental points of view, the development of the interconnected systems is highly positive. (author)

  12. Resistance transition assisted geometry enhanced magnetoresistance in semiconductors

    International Nuclear Information System (INIS)

    Luo, Zhaochu; Zhang, Xiaozhong

    2015-01-01

    Magnetoresistance (MR) reported in some non-magnetic semiconductors (particularly silicon) has triggered considerable interest owing to the large magnitude of the effect. Here, we showed that MR in lightly doped n-Si can be significantly enhanced by introducing two diodes and proper design of the carrier path [Wan, Nature 477, 304 (2011)]. We designed a geometrical enhanced magnetoresistance (GEMR) device whose room-temperature MR ratio reaching 30% at 0.065 T and 20 000% at 1.2 T, respectively, approaching the performance of commercial MR devices. The mechanism of this GEMR is: the diodes help to define a high resistive state (HRS) and a low resistive state (LRS) in device by their openness and closeness, respectively. The ratio of apparent resistance between HRS and LRS is determined by geometry of silicon wafer and electrodes. Magnetic field could induce a transition from LRS to HRS by reshaping potential and current distribution among silicon wafer, resulting in a giant enhancement of intrinsic MR. We expect that this GEMR could be also realized in other semiconductors. The combination of high sensitivity to low magnetic fields and large high-field response should make this device concept attractive to the magnetic field sensing industry. Moreover, because this MR device is based on a conventional silicon/semiconductor platform, it should be possible to integrate this MR device with existing silicon/semiconductor devices and so aid the development of silicon/semiconductor-based magnetoelectronics. Also combining MR devices and semiconducting devices in a single Si/semiconductor chip may lead to some novel devices with hybrid function, such as electric-magnetic-photonic properties. Our work demonstrates that the charge property of semiconductor can be used in the magnetic sensing industry, where the spin properties of magnetic materials play a role traditionally

  13. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    Energy Technology Data Exchange (ETDEWEB)

    Rogers, John A.; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G.; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

    2016-04-26

    The present invention relates to novel diacylglycerol acyltransferase genes and proteins, and methods of their use. In particular, the invention describes genes encoding proteins having diacylglycerol acetyltransferase activity, specifically for transferring an acetyl group to a diacylglycerol substrate to form acetyl-Triacylglycerols (ac-TAGS), for example, a 3-acetyl-1,2-diacyl-sn-glycerol. The present invention encompasses both native and recombinant wild-type forms of the transferase, as well as mutants and variant forms. The present invention also relates to methods of using novel diacylglycerol acyltransferase genes and proteins, including their expression in transgenic organisms at commercially viable levels, for increasing production of 3-acetyl-1,2-diacyl-sn-glycerols in plant oils and altering the composition of oils produced by microorganisms, such as yeast, by increasing ac-TAG production. Additionally, oils produced by methods of the present inventions comprising genes and proteins are contemplated for use as biodiesel fuel, in polymer production and as naturally produced food oils with reduced calories.

  14. Advances in semiconductor lasers

    CERN Document Server

    Coleman, James J; Jagadish, Chennupati

    2012-01-01

    Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scien

  15. Superconductivity in doped semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Bustarret, E., E-mail: Etienne.bustarret@neel.cnrs.fr

    2015-07-15

    A historical survey of the main normal and superconducting state properties of several semiconductors doped into superconductivity is proposed. This class of materials includes selenides, tellurides, oxides and column-IV semiconductors. Most of the experimental data point to a weak coupling pairing mechanism, probably phonon-mediated in the case of diamond, but probably not in the case of strontium titanate, these being the most intensively studied materials over the last decade. Despite promising theoretical predictions based on a conventional mechanism, the occurrence of critical temperatures significantly higher than 10 K has not been yet verified. However, the class provides an enticing playground for testing theories and devices alike.

  16. Semiconductor opto-electronics

    CERN Document Server

    Moss, TS; Ellis, B

    1972-01-01

    Semiconductor Opto-Electronics focuses on opto-electronics, covering the basic physical phenomena and device behavior that arise from the interaction between electromagnetic radiation and electrons in a solid. The first nine chapters of this book are devoted to theoretical topics, discussing the interaction of electromagnetic waves with solids, dispersion theory and absorption processes, magneto-optical effects, and non-linear phenomena. Theories of photo-effects and photo-detectors are treated in detail, including the theories of radiation generation and the behavior of semiconductor lasers a

  17. Ternary chalcopyrite semiconductors

    CERN Document Server

    Shay, J L; Pamplin, B R

    2013-01-01

    Ternary Chalcopyrite Semiconductors: Growth, Electronic Properties, and Applications covers the developments of work in the I-III-VI2 and II-IV-V2 ternary chalcopyrite compounds. This book is composed of eight chapters that focus on the crystal growth, characterization, and applications of these compounds to optical communications systems. After briefly dealing with the status of ternary chalcopyrite compounds, this book goes on describing the crystal growth of II-IV-V2 and I-III-VI2 single crystals. Chapters 3 and 4 examine the energy band structure of these semiconductor compounds, illustrat

  18. Compound semiconductor device physics

    CERN Document Server

    Tiwari, Sandip

    2013-01-01

    This book provides one of the most rigorous treatments of compound semiconductor device physics yet published. A complete understanding of modern devices requires a working knowledge of low-dimensional physics, the use of statistical methods, and the use of one-, two-, and three-dimensional analytical and numerical analysis techniques. With its systematic and detailed**discussion of these topics, this book is ideal for both the researcher and the student. Although the emphasis of this text is on compound semiconductor devices, many of the principles discussed will also be useful to those inter

  19. Introductory semiconductor device physics

    CERN Document Server

    Parker, Greg

    2004-01-01

    ATOMS AND BONDINGThe Periodic TableIonic BondingCovalent BondingMetallic bondingvan der Waals BondingStart a DatabaseENERGY BANDS AND EFFECTIVE MASSSemiconductors, Insulators and MetalsSemiconductorsInsulatorsMetalsThe Concept of Effective MassCARRIER CONCENTRATIONS IN SEMICONDUCTORSDonors and AcceptorsFermi-LevelCarrier Concentration EquationsDonors and Acceptors Both PresentCONDUCTION IN SEMICONDUCTORSCarrier DriftCarrier MobilitySaturated Drift VelocityMobility Variation with TemperatureA Derivation of Ohm's LawDrift Current EquationsSemiconductor Band Diagrams with an Electric Field Presen

  20. Particles in Semiconductor Processing

    NARCIS (Netherlands)

    Knotter, D. Martin; Wali, F.; Kohli, Rajiv; Mittal, Kashmiri L.

    2010-01-01

    Advances in integrated circuits (ICs) have a high impact on society. These advances result in continuously increasing performance of home personal computers, higher density flash memory chips, faster wireless communication in combination with smaller antennas, and all kinds of combinations of the

  1. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  2. Decentralised output feedback control of Markovian jump interconnected systems with unknown interconnections

    Science.gov (United States)

    Li, Li-Wei; Yang, Guang-Hong

    2017-07-01

    The problem of decentralised output feedback control is addressed for Markovian jump interconnected systems with unknown interconnections and general transition rates (TRs) allowed to be unknown or known with uncertainties. A class of decentralised dynamic output feedback controllers are constructed, and a cyclic-small-gain condition is exploited to dispose the unknown interconnections so that the resultant closed-loop system is stochastically stable and satisfies an H∞ performance. With slack matrices to cope with the nonlinearities incurred by unknown and uncertain TRs in control synthesis, a novel controller design condition is developed in linear matrix inequality formalism. Compared with the existing works, the proposed approach leads to less conservatism. Finally, two examples are used to illustrate the effectiveness of the new results.

  3. Tunable radiation emitting semiconductor device

    NARCIS (Netherlands)

    2009-01-01

    A tunable radiation emitting semiconductor device includes at least one elongated structure at least partially fabricated from one or more semiconductor materials exhibiting a bandgap characteristic including one or more energy transitions whose energies correspond to photon energies of light

  4. Physical principles of semiconductor detectors

    International Nuclear Information System (INIS)

    Micek, S.L.

    1979-01-01

    The general properties of semiconductors with respect to the possibilities of their use as the ionization radiation detectors are discussed. Some chosen types of semiconductor junctions and their characteristics are briefly presented. There are also discussed the physical phenomena connected with the formation of barriers in various types of semiconductor counters. Finally, the basic properties of three main types of semiconductor detectors are given. (author)

  5. Metal semiconductor contacts and devices

    CERN Document Server

    Cohen, Simon S; Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 13: Metal-Semiconductor Contacts and Devices presents the physics, technology, and applications of metal-semiconductor barriers in digital integrated circuits. The emphasis is placed on the interplay among the theory, processing, and characterization techniques in the development of practical metal-semiconductor contacts and devices.This volume contains chapters that are devoted to the discussion of the physics of metal-semiconductor interfaces and its basic phenomena; fabrication procedures; and interface characterization techniques, particularl

  6. Handbook of luminescent semiconductor materials

    CERN Document Server

    Bergman, Leah

    2011-01-01

    Photoluminescence spectroscopy is an important approach for examining the optical interactions in semiconductors and optical devices with the goal of gaining insight into material properties. With contributions from researchers at the forefront of this field, Handbook of Luminescent Semiconductor Materials explores the use of this technique to study semiconductor materials in a variety of applications, including solid-state lighting, solar energy conversion, optical devices, and biological imaging. After introducing basic semiconductor theory and photoluminescence principles, the book focuses

  7. Holistic design in high-speed optical interconnects

    Science.gov (United States)

    Saeedi, Saman

    Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

  8. Depletion field focusing in semiconductors

    NARCIS (Netherlands)

    Prins, M.W.J.; Gelder, Van A.P.

    1996-01-01

    We calculate the three-dimensional depletion field profile in a semiconductor, for a planar semiconductor material with a spatially varying potential upon the surface, and for a tip-shaped semiconductor with a constant surface potential. The nonuniform electric field gives rise to focusing or

  9. Nonlinear Elasticity of Doped Semiconductors

    Science.gov (United States)

    2017-02-01

    AFRL-RY-WP-TR-2016-0206 NONLINEAR ELASTICITY OF DOPED SEMICONDUCTORS Mark Dykman and Kirill Moskovtsev Michigan State University...2016 4. TITLE AND SUBTITLE NONLINEAR ELASTICITY OF DOPED SEMICONDUCTORS 5a. CONTRACT NUMBER FA8650-16-1-7600 5b. GRANT NUMBER 5c. PROGRAM...vibration amplitude. 15. SUBJECT TERMS semiconductors , microresonators, microelectromechanical 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF

  10. Environmental Regulation Impacts on Eastern Interconnection Performance

    Energy Technology Data Exchange (ETDEWEB)

    Markham, Penn N [ORNL; Liu, Yilu [ORNL; Young II, Marcus Aaron [ORNL

    2013-07-01

    In the United States, recent environmental regulations will likely result in the removal of nearly 30 GW of oil and coal-fired generation from the power grid, mostly in the Eastern Interconnection (EI). The effects of this transition on voltage stability and transmission line flows have previously not been studied from a system-wide perspective. This report discusses the results of power flow studies designed to simulate the evolution of the EI over the next few years as traditional generation sources are replaced with environmentally friendlier ones such as natural gas and wind.

  11. Optical Interconnection Via Computer-Generated Holograms

    Science.gov (United States)

    Liu, Hua-Kuang; Zhou, Shaomin

    1995-01-01

    Method of free-space optical interconnection developed for data-processing applications like parallel optical computing, neural-network computing, and switching in optical communication networks. In method, multiple optical connections between multiple sources of light in one array and multiple photodetectors in another array made via computer-generated holograms in electrically addressed spatial light modulators (ESLMs). Offers potential advantages of massive parallelism, high space-bandwidth product, high time-bandwidth product, low power consumption, low cross talk, and low time skew. Also offers advantage of programmability with flexibility of reconfiguration, including variation of strengths of optical connections in real time.

  12. Interconnectivity and the Electronic Academic Library

    Directory of Open Access Journals (Sweden)

    Donald E. Riggs

    1988-03-01

    Full Text Available 無Due to the emphasis on the use of computing networks on campuses and to the very nature of more information being accessible to library users only via electronic means, we are witnessing a migration to electronic academic libraries. this new type of library is being required to have interconnections with the campus' other online information/data systems. Arizona State University libraries have been provided the opportunity to develop an electronic library that will be the focal point of a campus-wide information/data network.

  13. Semi-conductor rectifiers

    International Nuclear Information System (INIS)

    1981-01-01

    A method is described for treating a semiconductor rectifier, comprising: heating the rectifier to a temperature in the range of 100 0 C to 500 0 C, irradiating the rectifier while maintaining its temperature within the said range, and then annealing the rectifier at a temperature of between 280 0 C and 350 0 C for between two and ten hours. (author)

  14. Semiconductor detector physics

    International Nuclear Information System (INIS)

    Equer, B.

    1987-01-01

    Comprehension of semiconductor detectors follows comprehension of some elements of solid state physics. They are recalled here, limited to the necessary physical principles, that is to say the conductivity. P-n and MIS junctions are discussed in view of their use in detection. Material and structure (MOS, p-n, multilayer, ..) are also reviewed [fr

  15. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  16. Optimization of Reliability and Power Consumption in Systems on a Chip

    OpenAIRE

    Simunic, Tajana; Mihic, Kresimir; De Micheli, Giovanni

    2005-01-01

    Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature, have made reliability assessment a much more significant issue in design. Although reliability of devices and interconnect has been broadly studied, here we characterize reliability at the system level. Thus we consider component-based System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and...

  17. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  18. National Offshore Wind Energy Grid Interconnection Study

    Energy Technology Data Exchange (ETDEWEB)

    Daniel, John P. [ABB Inc; Liu, Shu [ABB Inc; Ibanez, Eduardo [National Renewable Energy Laboratory; Pennock, Ken [AWS Truepower; Reed, Greg [University of Pittsburgh; Hanes, Spencer [Duke Energy

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States. A total of 54GW of offshore wind was assumed to be the target for the analyses conducted. A variety of issues are considered including: the anticipated staging of offshore wind; the offshore wind resource availability; offshore wind energy power production profiles; offshore wind variability; present and potential technologies for collection and delivery of offshore wind energy to the onshore grid; potential impacts to existing utility systems most likely to receive large amounts of offshore wind; and regulatory influences on offshore wind development. The technologies considered the reliability of various high-voltage ac (HVAC) and high-voltage dc (HVDC) technology options and configurations. The utility system impacts of GW-scale integration of offshore wind are considered from an operational steady-state perspective and from a regional and national production cost perspective.

  19. Interconnected ponds operation for flood hazard distribution

    Science.gov (United States)

    Putra, S. S.; Ridwan, B. W.

    2016-05-01

    The climatic anomaly, which comes with extreme rainfall, will increase the flood hazard in an area within a short period of time. The river capacity in discharging the flood is not continuous along the river stretch and sensitive to the flood peak. This paper contains the alternatives on how to locate the flood retention pond that are physically feasible to reduce the flood peak. The flood ponds were designed based on flood curve number criteria (TR-55, USDA) with the aim of rapid flood peak capturing and gradual flood retuning back to the river. As a case study, the hydrologic condition of upper Ciliwung river basin with several presumed flood pond locations was conceptually designed. A fundamental tank model that reproducing the operation of interconnected ponds was elaborated to achieve the designed flood discharge that will flows to the downstream area. The flood hazard distribution status, as the model performance criteria, will be computed within Ciliwung river reach in Manggarai Sluice Gate spot. The predicted hazard reduction with the operation of the interconnected retention area result had been bench marked with the normal flow condition.

  20. Message Passing Framework for Globally Interconnected Clusters

    International Nuclear Information System (INIS)

    Hafeez, M; Riaz, N; Asghar, S; Malik, U A; Rehman, A

    2011-01-01

    In prevailing technology trends it is apparent that the network requirements and technologies will advance in future. Therefore the need of High Performance Computing (HPC) based implementation for interconnecting clusters is comprehensible for scalability of clusters. Grid computing provides global infrastructure of interconnecting clusters consisting of dispersed computing resources over Internet. On the other hand the leading model for HPC programming is Message Passing Interface (MPI). As compared to Grid computing, MPI is better suited for solving most of the complex computational problems. MPI itself is restricted to a single cluster. It does not support message passing over the internet to use the computing resources of different clusters in an optimal way. We propose a model that provides message passing capabilities between parallel applications over the internet. The proposed model is based on Architecture for Java Universal Message Passing (A-JUMP) framework and Enterprise Service Bus (ESB) named as High Performance Computing Bus. The HPC Bus is built using ActiveMQ. HPC Bus is responsible for communication and message passing in an asynchronous manner. Asynchronous mode of communication offers an assurance for message delivery as well as a fault tolerance mechanism for message passing. The idea presented in this paper effectively utilizes wide-area intercluster networks. It also provides scheduling, dynamic resource discovery and allocation, and sub-clustering of resources for different jobs. Performance analysis and comparison study of the proposed framework with P2P-MPI are also presented in this paper.

  1. Towards energy aware optical networks and interconnects

    Science.gov (United States)

    Glesk, Ivan; Osadola, Tolulope; Idris, Siti

    2013-10-01

    In a today's world, information technology has been identified as one of the major factors driving economic prosperity. Datacenters businesses have been growing significantly in the past few years. The equipments in these datacenters need to be efficiently connected to each other and also to the outside world in order to enable effective exchange of information. This is why there is need for highly scalable, energy savvy and reliable network connectivity infrastructure that is capable of accommodating the large volume of data being exchanged at any time within the datacenter network and the outside network in general. These devices that can ensure such effective connectivity currently require large amount of energy in order to meet up with these increasing demands. In this paper, an overview of works being done towards realizing energy aware optical networks and interconnects for datacenters is presented. Also an OCDMA approach is discussed as potential multiple access technique for future optical network interconnections. We also presented some challenges that might inhibit effective implementation of the OCDMA multiplexing scheme.

  2. Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

    Science.gov (United States)

    Yang, Lei; Gong, Jie; Ume, I. Charles

    2014-02-01

    In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be

  3. Amdahl 470 Chip Package

    CERN Multimedia

    1975-01-01

    In the late 70s the larger IBM computers were water cooled. Amdahl, an IBM competitor, invented an air cooling technology for it's computers. His company worked hard, developing a computer that was faster and less expensive than the IBM System/360 mainframe computer systems. This object contains an actual Amdahl series 470 computer logic chip with an air cooling device mounted on top. The package leads and cooling tower are gold-plated.

  4. Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

    Science.gov (United States)

    Wysocki, Gerard (Inventor); Tittel, Frank K. (Inventor); Curl, Robert F. (Inventor)

    2010-01-01

    A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

  5. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  6. Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

    Science.gov (United States)

    Biyikli, Necmi; Haider, Ali

    2017-09-01

    In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

  7. K-band single-chip electron spin resonance detector.

    Science.gov (United States)

    Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

    2012-04-01

    We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

  8. Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

    Science.gov (United States)

    Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

    2018-03-01

    In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

  9. Optically pumped semiconductor lasers for atomic and molecular physics

    Science.gov (United States)

    Burd, S.; Leibfried, D.; Wilson, A. C.; Wineland, D. J.

    2015-03-01

    Experiments in atomic, molecular and optical (AMO) physics rely on lasers at many different wavelengths and with varying requirements on spectral linewidth, power and intensity stability. Optically pumped semiconductor lasers (OPSLs), when combined with nonlinear frequency conversion, can potentially replace many of the laser systems currently in use. We are developing a source for laser cooling and spectroscopy of Mg+ ions at 280 nm, based on a frequency quadrupled OPSL with the gain chip fabricated at the ORC at Tampere Univ. of Technology, Finland. This OPSL system could serve as a prototype for many other sources used in atomic and molecular physics.

  10. Integration of microelectronic chips in microfluidic systems on printed circuit board

    International Nuclear Information System (INIS)

    Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

    2012-01-01

    A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

  11. Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

    Science.gov (United States)

    Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

    2017-10-01

    In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

  12. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  13. Reconfigurable Optical Interconnections Via Dynamic Computer-Generated Holograms

    Science.gov (United States)

    Liu, Hua-Kuang (Inventor); Zhou, Shao-Min (Inventor)

    1996-01-01

    A system is presented for optically providing one-to-many irregular interconnections, and strength-adjustable many-to-many irregular interconnections which may be provided with strengths (weights) w(sub ij) using multiple laser beams which address multiple holograms and means for combining the beams modified by the holograms to form multiple interconnections, such as a cross-bar switching network. The optical means for interconnection is based on entering a series of complex computer-generated holograms on an electrically addressed spatial light modulator for real-time reconfigurations, thus providing flexibility for interconnection networks for large-scale practical use. By employing multiple sources and holograms, the number of interconnection patterns achieved is increased greatly.

  14. High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

    Science.gov (United States)

    Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

    2011-03-01

    The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

  15. Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2$\\cdot 10^{15}$\\,n$_{\\mathrm{eq}}$/cm$^2$

    CERN Document Server

    INSPIRE-00237859; Beimforde, M.; Macchiolo, A.; Moser, H.G.; Nisius, R.; Richter, R.H.

    2011-01-01

    A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to $2\\cdot10^{15}$\\,\

  16. Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅10 15 $n_{eq}$ /cm 2

    CERN Document Server

    Weigell, P; Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H

    2011-01-01

    A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to 2⋅10 15 \\,\

  17. Compact Interconnection Networks Based on Quantum Dots

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

    2003-01-01

    Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

  18. Thermo-mechanical properties and integrity of metallic interconnects in microelectronics

    Science.gov (United States)

    Ege, Efe Sinan

    In this dissertation, combined numerical (Finite Element Method) and experimental efforts were undertaken to study thermo-mechanical behavior in microelectronic devices. Interconnects, including chip-level metallization and package-level solder joints, are used to join many of the circuit parts in modern equipment. The dissertation is structured into six independent studies after the introductory chapter. The first two studies focus on thermo-mechanical fatigue of solder joints. Thermo-mechanical fatigue, in the form of damage along a microstructurally coarsened region in tin-lead solder, is analyzed along with the effects of intermetallic morphology. Also, lap-shear testing is modeled to characterize the joint and to investigate the validity of experimental data from different solder and substrate geometries. In the third study, the effects of pre-machined holes on strain localization and overall ductility in bulk eutectic tin-lead alloy is examined. Finite element analyses, taking into account the viscoplastic response, were carried out to provide a mechanistic rationale to corroborate the experimental findings. The fourth study concerns chip-level copper interconnects. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without the thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. This study is followed by a chapter on atomistics of interface-mediated plasticity in thin metallic films. The objective is to gain fundamental insight into the underlying mechanisms affecting the mechanical response of nanoscale thin films. The final study investigates the effect of microstructural heterogeneity on indentation response, for the purpose of raising awareness of the uncertainties involved in applying indentation techniques in probing mechanical properties of miniaturized devices.

  19. Opportunities and challenges in the wider adoption of liver and interconnected microphysiological systems.

    Science.gov (United States)

    Hughes, David J; Kostrzewski, Tomasz; Sceats, Emma L

    2017-10-01

    Liver disease represents a growing global health burden. The development of in vitro liver models which allow the study of disease and the prediction of metabolism and drug-induced liver injury in humans remains a challenge. The maintenance of functional primary hepatocytes cultures, the parenchymal cell of the liver, has historically been difficult with dedifferentiation and the consequent loss of hepatic function limiting utility. The desire for longer term functional liver cultures sparked the development of numerous systems, including collagen sandwiches, spheroids, micropatterned co-cultures and liver microphysiological systems. This review will focus on liver microphysiological systems, often referred to as liver-on-a-chip, and broaden to include platforms with interconnected microphysiological systems or multi-organ-chips. The interconnection of microphysiological systems presents the opportunity to explore system level effects, investigate organ cross talk, and address questions which were previously the preserve of animal experimentation. As a field, microphysiological systems have reached a level of maturity suitable for commercialization and consequent evaluation by a wider community of users, in academia and the pharmaceutical industry. Here scientific, operational, and organizational considerations relevant to the wider adoption of microphysiological systems will be discussed. Applications in which microphysiological systems might offer unique scientific insights or enable studies currently feasible only with animal models are described, and challenges which might be addressed to enable wider adoption of the technologies are highlighted. A path forward which envisions the development of microphysiological systems in partnerships between academia, vendors and industry, is proposed. Impact statement Microphysiological systems are in vitro models of human tissues and organs. These systems have advanced rapidly in recent years and are now being

  20. Current Solutions: Recent Experience in Interconnecting Distributed Energy Resources

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, M.

    2003-09-01

    This report catalogues selected real-world technical experiences of utilities and customers that have interconnected distributed energy assets with the electric grid. This study was initiated to assess the actual technical practices for interconnecting distributed generation and had a particular focus on the technical issues covered under the Institute of Electrical and Electronics Engineers (IEEE) 1547(TM) Standard for Interconnecting Distributed Resources With Electric Power Systems.

  1. Interconnection network architectures based on integrated orbital angular momentum emitters

    Science.gov (United States)

    Scaffardi, Mirco; Zhang, Ning; Malik, Muhammad Nouman; Lazzeri, Emma; Klitis, Charalambos; Lavery, Martin; Sorel, Marc; Bogoni, Antonella

    2018-02-01

    Novel architectures for two-layer interconnection networks based on concentric OAM emitters are presented. A scalability analysis is done in terms of devices characteristics, power budget and optical signal to noise ratio by exploiting experimentally measured parameters. The analysis shows that by exploiting optical amplifications, the proposed interconnection networks can support a number of ports higher than 100. The OAM crosstalk induced-penalty, evaluated through an experimental characterization, do not significantly affect the interconnection network performance.

  2. Self-Rerouting and Curative Interconnect Technology (SERCUIT)

    Science.gov (United States)

    2017-12-01

    SPECIAL REPORT RDMR-CS-17-01 SELF-REROUTING AND CURATIVE INTERCONNECT TECHNOLOGY (SERCUIT) Shiv Joshi Concepts to Systems, Inc...Final 4. TITLE AND SUBTITLE Self-Rerouting and Curative Interconnect Technology (SERCUIT) 5. FUNDING NUMBERS 6. AUTHOR(S) Shiv Joshi...concepts2systems.com (p) 434-207-5189 x (f) Click to view full size Title Contract Number SELF-REROUTING AND CURATIVE INTERCONNECT TECHNOLOGY (SERCUIT) W911W6-17-C-0029

  3. Bacteria inside semiconductors as potential sensor elements: biochip progress.

    Science.gov (United States)

    Sah, Vasu R; Baier, Robert E

    2014-06-24

    It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

  4. Single frequency semiconductor lasers

    CERN Document Server

    Fang, Zujie; Chen, Gaoting; Qu, Ronghui

    2017-01-01

    This book systematically introduces the single frequency semiconductor laser, which is widely used in many vital advanced technologies, such as the laser cooling of atoms and atomic clock, high-precision measurements and spectroscopy, coherent optical communications, and advanced optical sensors. It presents both the fundamentals and characteristics of semiconductor lasers, including basic F-P structure and monolithic integrated structures; interprets laser noises and their measurements; and explains mechanisms and technologies relating to the main aspects of single frequency lasers, including external cavity lasers, frequency stabilization technologies, frequency sweeping, optical phase locked loops, and so on. It paints a clear, physical picture of related technologies and reviews new developments in the field as well. It will be a useful reference to graduate students, researchers, and engineers in the field.

  5. Basic semiconductor physics

    CERN Document Server

    Hamaguchi, Chihiro

    2017-01-01

    This book presents a detailed description of basic semiconductor physics. The text covers a wide range of important phenomena in semiconductors, from the simple to the advanced. Four different methods of energy band calculations in the full band region are explained: local empirical pseudopotential, non-local pseudopotential, KP perturbation and tight-binding methods. The effective mass approximation and electron motion in a periodic potential, Boltzmann transport equation and deformation potentials used for analysis of transport properties are discussed. Further, the book examines experiments and theoretical analyses of cyclotron resonance in detail. Optical and transport properties, magneto-transport, two-dimensional electron gas transport (HEMT and MOSFET) and quantum transport are reviewed, while optical transition, electron-phonon interaction and electron mobility are also addressed. Energy and electronic structure of a quantum dot (artificial atom) are explained with the help of Slater determinants. The...

  6. Semiconductor physics an introduction

    CERN Document Server

    Seeger, Karlheinz

    1999-01-01

    Semiconductor Physics - An Introduction - is suitable for the senior undergraduate or new graduate student majoring in electrical engineering or physics. It will also be useful to solid-state scientists and device engineers involved in semiconductor design and technology. The text provides a lucid account of charge transport, energy transport and optical processes, and a detailed description of many devices. It includes sections on superlattices and quantum well structures, the effects of deep-level impurities on transport, the quantum Hall effect and the calculation of the influence of a magnetic field on the carrier distribution function. This 6th edition has been revised and corrected, and new sections have been added to different chapters.

  7. Three dimensional strained semiconductors

    Science.gov (United States)

    Voss, Lars; Conway, Adam; Nikolic, Rebecca J.; Leao, Cedric Rocha; Shao, Qinghui

    2016-11-08

    In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

  8. Compound semiconductor device modelling

    CERN Document Server

    Miles, Robert

    1993-01-01

    Compound semiconductor devices form the foundation of solid-state microwave and optoelectronic technologies used in many modern communication systems. In common with their low frequency counterparts, these devices are often represented using equivalent circuit models, but it is often necessary to resort to physical models in order to gain insight into the detailed operation of compound semiconductor devices. Many of the earliest physical models were indeed developed to understand the 'unusual' phenomena which occur at high frequencies. Such was the case with the Gunn and IMPATI diodes, which led to an increased interest in using numerical simulation methods. Contemporary devices often have feature sizes so small that they no longer operate within the familiar traditional framework, and hot electron or even quantum­ mechanical models are required. The need for accurate and efficient models suitable for computer aided design has increased with the demand for a wider range of integrated devices for operation at...

  9. Doping of organic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Luessem, B.; Riede, M.; Leo, K. [Institut fuer Angewandte Photophysik, TU Dresden (Germany)

    2013-01-15

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  10. Images through semiconductors

    International Nuclear Information System (INIS)

    Anon.

    1986-01-01

    Improved image processing techniques are constantly being developed for television and for scanners using X-rays or other radiation for industrial or medical applications, etc. As Erik Heijne of CERN explains here, particle physics too has its own special requirements for image processing. The increasing use of semiconductor techniques for handling measurements down to the level of a few microns provides another example of the close interplay between scientific research and technological development. (orig.).

  11. Muonium states in semiconductors

    International Nuclear Information System (INIS)

    Patterson, B.D.

    1987-01-01

    There is a brief summary of what is known about the muonium states isotropic, anisotropic and diamagnetic in diamond and zincblende semiconductors. The report deals with muonium spectroscopy, including the formation probabilities, hyperfine parameters and electronic g-factors of the states. The dynamics of the states is treated including a discussion of the transition from isotropic Mu to anisotropic Mu in diamond, temperature-dependent linewidthes in silicon and germanium and effects of daping and radiation damage

  12. Nonradiative recombination in semiconductors

    CERN Document Server

    Abakumov, VN; Yassievich, IN

    1991-01-01

    In recent years, great progress has been made in the understandingof recombination processes controlling the number of excessfree carriers in semiconductors under nonequilibrium conditions. As a result, it is now possible to give a comprehensivetheoretical description of these processes. The authors haveselected a number of experimental results which elucidate theunderlying physical problems and enable a test of theoreticalmodels. The following topics are dealt with: phenomenological theory ofrecombination, theoretical models of shallow and deep localizedstates, cascade model of carrier captu

  13. Doping of organic semiconductors

    International Nuclear Information System (INIS)

    Luessem, B.; Riede, M.; Leo, K.

    2013-01-01

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  14. Isotopically controlled semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Haller, Eugene E.

    2006-06-19

    The following article is an edited transcript based on the Turnbull Lecture given by Eugene E. Haller at the 2005 Materials Research Society Fall Meeting in Boston on November 29, 2005. The David Turnbull Lectureship is awarded to recognize the career of a scientist who has made outstanding contributions to understanding materials phenomena and properties through research, writing, and lecturing, as exemplified by the life work of David Turnbull. Haller was named the 2005 David Turnbull Lecturer for his 'pioneering achievements and leadership in establishing the field of isotopically engineered semiconductors; for outstanding contributions to materials growth, doping and diffusion; and for excellence in lecturing, writing, and fostering international collaborations'. The scientific interest, increased availability, and technological promise of highly enriched isotopes have led to a sharp rise in the number of experimental and theoretical studies with isotopically controlled semiconductor crystals. This article reviews results obtained with isotopically controlled semiconductor bulk and thin-film heterostructures. Isotopic composition affects several properties such as phonon energies, band structure, and lattice constant in subtle, but, for their physical understanding, significant ways. Large isotope-related effects are observed for thermal conductivity in local vibrational modes of impurities and after neutron transmutation doping. Spectacularly sharp photoluminescence lines have been observed in ultrapure, isotopically enriched silicon crystals. Isotope multilayer structures are especially well suited for simultaneous self- and dopant-diffusion studies. The absence of any chemical, mechanical, or electrical driving forces makes possible the study of an ideal random-walk problem. Isotopically controlled semiconductors may find applications in quantum computing, nanoscience, and spintronics.

  15. Distributed Energy Resources Interconnection Systems: Technology Review and Research Needs

    Energy Technology Data Exchange (ETDEWEB)

    Friedman, N. R.

    2002-09-01

    Interconnecting distributed energy resources (DER) to the electric utility grid (or Area Electric Power System, Area EPS) involves system engineering, safety, and reliability considerations. This report documents US DOE Distribution and Interconnection R&D (formerly Distributed Power Program) activities, furthering the development and safe and reliable integration of DER interconnected with our nation's electric power systems. The key to that is system integration and technology development of the interconnection devices that perform the functions necessary to maintain the safety, power quality, and reliability of the EPS when DER are connected to it.

  16. Cost based interconnection charges as a way to induce competition

    DEFF Research Database (Denmark)

    Falch, Morten

    The objective of this paper is to analyse the relationship between regulation of interconnection charges and the level of competition. One of the most important issues in the debate on interconnect regulation has been use of forward looking costs for setting of interconnection charges. This debat...... has been ongoing within the EU as well as in US. This paper discusses the European experiences and in particular the Danish experiences with use of cost based interconnection charges, and their impact on competition in the telecom market....

  17. Financial viability of the Sonora-Baja California interconnection line

    International Nuclear Information System (INIS)

    Alonso, G.; Ortega, G.

    2017-09-01

    In the Development Program of the National Electricity Sector 2015-2029, an electric interconnection line between Sonora and Baja California (Mexico) is proposed, this study analyzes the financial viability of this interconnection line based on the maximum hourly and seasonal energy demand between both regions and proposes alternatives for the supply of electric power that supports the economic convenience of this interconnection line. The results show that additional capacity is required in Sonora to cover the maximum demands of both regions since in the current condition of the National Electric System the interconnection line is not justified. (Author)

  18. 78 FR 73239 - Small Generator Interconnection Agreements and Procedures

    Science.gov (United States)

    2013-12-05

    ... Electronics Engineers (IEEE) Standard 1547 for Interconnecting Distributed Resources with Electric Power... discriminatory manner.\\38\\ \\37\\ The Electricity Consumers Resource Council, American Chemistry Council, American...

  19. Survey of semiconductor physics

    CERN Document Server

    Böer, Karl W

    1992-01-01

    Any book that covers a large variety of subjects and is written by one author lacks by necessity the depth provided by an expert in his or her own field of specialization. This book is no exception. It has been written with the encouragement of my students and colleagues, who felt that an extensive card file I had accumulated over the years of teaching solid state and semiconductor physics would be helpful to more than just a few of us. This file, updated from time to time, contained lecture notes and other entries that were useful in my research and permitted me to give to my students a broader spectrum of information than is available in typical textbooks. When assembling this material into a book, I divided the top­ ics into material dealing with the homogeneous semiconductor, the subject of the previously published Volume 1, and the inhomoge­ neous semiconductor, the subject of this Volume 2. In order to keep the book to a manageable size, sections of tutorial character which can be used as text for a g...

  20. The Physics of Semiconductors

    Science.gov (United States)

    Brennan, Kevin F.

    1999-02-01

    Modern fabrication techniques have made it possible to produce semiconductor devices whose dimensions are so small that quantum mechanical effects dominate their behavior. This book describes the key elements of quantum mechanics, statistical mechanics, and solid-state physics that are necessary in understanding these modern semiconductor devices. The author begins with a review of elementary quantum mechanics, and then describes more advanced topics, such as multiple quantum wells. He then disusses equilibrium and nonequilibrium statistical mechanics. Following this introduction, he provides a thorough treatment of solid-state physics, covering electron motion in periodic potentials, electron-phonon interaction, and recombination processes. The final four chapters deal exclusively with real devices, such as semiconductor lasers, photodiodes, flat panel displays, and MOSFETs. The book contains many homework exercises and is suitable as a textbook for electrical engineering, materials science, or physics students taking courses in solid-state device physics. It will also be a valuable reference for practicing engineers in optoelectronics and related areas.

  1. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    OpenAIRE

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. P...

  2. Asynchronous decentralized method for interconnected electricity markets

    International Nuclear Information System (INIS)

    Huang, Anni; Joo, Sung-Kwan; Song, Kyung-Bin; Kim, Jin-Ho; Lee, Kisung

    2008-01-01

    This paper presents an asynchronous decentralized method to solve the optimization problem of interconnected electricity markets. The proposed method decomposes the optimization problem of combined electricity markets into individual optimization problems. The impact of neighboring markets' information is included in the objective function of the individual market optimization problem by the standard Lagrangian relaxation method. Most decentralized optimization methods use synchronous models of communication to exchange updated market information among markets during the iterative process. In this paper, however, the solutions of the individual optimization problems are coordinated through an asynchronous communication model until they converge to the global optimal solution of combined markets. Numerical examples are presented to demonstrate the advantages of the proposed asynchronous method over the existing synchronous methods. (author)

  3. Virtual interconnection platform initiative scoping study

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Yong [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Kou, Gefei [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Pan, Zuohong [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Liu, Yilu [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); King Jr., Thomas J. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2016-01-01

    Due to security and liability concerns, the research community has limited access to realistic large-scale power grid models to test and validate new operation and control methodologies. It is also difficult for industry to evaluate the relative value of competing new tools without a common platform for comparison. This report proposes to develop a large-scale virtual power grid model that retains basic features and represents future trends of major U.S. electric interconnections. This model will include realistic power flow and dynamics information as well as a relevant geospatial distribution of assets. This model will be made widely available to the research community for various power system stability and control studies and can be used as a common platform for comparing the efficacies of various new technologies.

  4. New transmission interconnection reduces consumer costs

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2008-09-15

    The Central American electric interconnection system (SIEPAC) project will involve the construction of a 1830 km 230 kV transmission system that will link Guatemala, El Salvador, Honduras, Costa Rica, Nicaragua, and Panama. The system is expected to alleviate the region's power shortages and reduce electricity costs for consumers. Costs for the SIEPAC project have been estimated at $370 million. The system will serve approximately 37 million customers, and will include 15 substations. The contract for building the electrical equipment has been awarded to Schweitzer Engineering Laboratories (SEL) who plan to manufacture components at a plant in Mexico. The equipment will include high speed line protection, automation, and control systems. Line current differential systems and satellite-synchronized clocks will also be used. The new transmission system is expected to be fully operational by 2009. 1 fig.

  5. SIDES - Segment Interconnect Diagnostic Expert System

    International Nuclear Information System (INIS)

    Booth, A.W.; Forster, R.; Gustafsson, L.; Ho, N.

    1989-01-01

    It is well known that the FASTBUS Segment Interconnect (SI) provides a communication path between two otherwise independent, asynchronous bus segments. The SI is probably the most important module in any FASTBUS data acquisition network since it's failure to function can cause whole segments of the network to be inaccessible and sometimes inoperable. This paper describes SIDES, an intelligent program designed to diagnose SI's both in situ as they operate in a data acquisition network, and in the laboratory in an acceptance/repair environment. The paper discusses important issues such as knowledge acquisition; extracting knowledge from human experts and other knowledge sources. SIDES can benefit high energy physics experiments, where SI problems can be diagnosed and solved more quickly. Equipment pool technicians can also benefit from SIDES, first by decreasing the number of SI's erroneously turned in for repair, and secondly as SIDES acts as an intelligent assistant to the technician in the diagnosis and repair process

  6. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  7. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    OpenAIRE

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

  8. Electric power grid interconnection in Northeast Asia

    International Nuclear Information System (INIS)

    Yun, Won-Cheol; Zhang, Zhong Xiang

    2006-01-01

    In spite of regional closeness, energy cooperation in Northeast Asia has remained unexplored. However, this situation appears to be changing. The government of South Korea seems to be very enthusiastic for power grid interconnection between the Russian Far East and South Korea to overcome difficulties in finding new sites for building power facilities to meet its need for increased electricity supplies. This paper analyzes the feasibility of this electric power grid interconnection route. The issues addressed include electricity market structures; the prospects for electric power industry restructuring in the Russian Federation and South Korea; the political issues related to North Korea; the challenges for the governments involved and the obstacles anticipated in moving this project forward; project financing and the roles and concerns from multilateral and regional banks; and institutional framework for energy cooperation. While there are many technical issues that need to be resolved, we think that the great challenge lies in the financing of this commercial project. Thus, the governments of the Russian Federation and South Korea involved in the project need to foster the development of their internal capital markets and to create confidence with international investors. To this end, on energy side, this involves defining a clear energy policy implemented by independent regulators, speeding up the already started but delayed reform process of restructuring electric power industry and markets, and establishing a fair and transparent dispute resolution mechanism in order to reduce non-commercial risks to a minimum. The paper argues that establishing a framework for energy cooperation in this region will contribute positively towards that end, although views differ regarding its specific form. Finally, given that North Korea has a crucial transit role to play and faces a very unstable political situation, it is concluded that moving the project forward needs to be

  9. Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

    Science.gov (United States)

    Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

    2004-07-01

    A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

  10. On-chip spin-controlled orbital angular momentum directional coupling

    Science.gov (United States)

    Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

    2018-01-01

    Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

  11. Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

    Science.gov (United States)

    Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

    2007-04-01

    In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

  12. Gigabit chips: A case history of a transfer of federal technology

    Energy Technology Data Exchange (ETDEWEB)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs. (JDH)

  13. Gigabit chips: A case history of a transfer of federal technology

    International Nuclear Information System (INIS)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs

  14. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  15. High-performance, scalable optical network-on-chip architectures

    Science.gov (United States)

    Tan, Xianfang

    The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of

  16. Future semiconductor material requirements and innovations as projected in the ITRS 2005 roadmap

    International Nuclear Information System (INIS)

    Arden, Wolfgang

    2006-01-01

    The international technology roadmap for semiconductors (ITRS) is a joint global effort of the semiconductor industry, the manufacturing equipment and material industry and the research community and consortia to define the future requirements and development of the semiconductor technology for the next 15 years. The ITRS started in 1992 as a US-national roadmap and became an international effort in 1998 with all major five industrial global regions (US, Japan, Taiwan, Korea and Europe) participating in its definition. The outlook in semiconductor manufacturing expects the continuous application of silicon technology for the next 15 years where complementary metal oxide semiconductor (CMOS) based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decade. The major section of the ITRS contains technical information about frontend processing and interconnects, device structures and memory concepts, lithography and metrology as well as factory integration and environmental issues. This paper will review the material requirements and the expected material innovations for the industry as outlined in the ITRS Version 2005. Materials to be discussed are, for example, high permittivity gate dielectrics, insulating layers with low dielectric constants for interconnects, and capacitor dielectrics for dynamic memories. In addition, the paper will address, for example, new transistor gate materials, new solutions for interconnect systems beyond copper as well as new starting materials for wafer sizes beyond 300 mm. This publication was presented as an invited paper in the Symposium V of the 2006 spring meeting of the European Materials Research Society (E-MRS) in Nice, May 29th

  17. Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects.

    Science.gov (United States)

    Gooth, Johannes; Borg, Mattias; Schmid, Heinz; Schaller, Vanessa; Wirths, Stephan; Moselund, Kirsten; Luisier, Mathieu; Karg, Siegfried; Riel, Heike

    2017-04-12

    Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.

  18. Electrodes for Semiconductor Gas Sensors

    Science.gov (United States)

    Lee, Sung Pil

    2017-01-01

    The electrodes of semiconductor gas sensors are important in characterizing sensors based on their sensitivity, selectivity, reversibility, response time, and long-term stability. The types and materials of electrodes used for semiconductor gas sensors are analyzed. In addition, the effect of interfacial zones and surface states of electrode–semiconductor interfaces on their characteristics is studied. This study describes that the gas interaction mechanism of the electrode–semiconductor interfaces should take into account the interfacial zone, surface states, image force, and tunneling effect. PMID:28346349

  19. Updating Small Generator Interconnection Procedures for New Market Conditions

    Energy Technology Data Exchange (ETDEWEB)

    Coddington, M.; Fox, K.; Stanfield, S.; Varnado, L.; Culley, T.; Sheehan, M.

    2012-12-01

    Federal and state regulators are faced with the challenge of keeping interconnection procedures updated against a backdrop of evolving technology, new codes and standards, and considerably transformed market conditions. This report is intended to educate policymakers and stakeholders on beneficial reforms that will keep interconnection processes efficient and cost-effective while maintaining a safe and reliable power system.

  20. Optimal interconnection and renewable targets for north-west Europe

    International Nuclear Information System (INIS)

    Lynch, Muireann Á.; Tol, Richard S.J.; O'Malley, Mark J.

    2012-01-01

    We present a mixed-integer, linear programming model for determining optimal interconnection for a given level of renewable generation using a cost minimisation approach. Optimal interconnection and capacity investment decisions are determined under various targets for renewable penetration. The model is applied to a test system for eight regions in Northern Europe. It is found that considerations on the supply side dominate demand side considerations when determining optimal interconnection investment: interconnection is found to decrease generation capacity investment and total costs only when there is a target for renewable generation. Higher wind integration costs see a concentration of wind in high-wind regions with interconnection to other regions. - Highlights: ► We use mixed-integer linear programming to determine optimal interconnection locations for given renewable targets. ► The model is applied to a test system for eight regions in Northern Europe. ► Interconnection reduces costs only when there is a renewable target. ► Wind integration costs affect the interconnection portfolio.

  1. 14 CFR 29.957 - Flow between interconnected tanks.

    Science.gov (United States)

    2010-01-01

    ... AIRCRAFT AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY ROTORCRAFT Powerplant Fuel System § 29.957 Flow between interconnected tanks. (a) Where tank outlets are interconnected and allow fuel to flow between them due to gravity or flight accelerations, it must be impossible for fuel to flow between tanks in...

  2. Robert Aymar seals the last interconnect in the LHC

    CERN Multimedia

    Maximilien Brice

    2007-01-01

    The LHC completes the circle. On 7 November, in a brief ceremony in the LHC tunnel, CERN Director General Robert Aymar (Photo 1) sealed the last interconnect between the main magnets of the Large Hadron Collider (LHC). Jean-Philippe Tock, leader of the Interconnections team, tightens the last bolt (Photos 4-8).

  3. Mapping of interconnection of climate risks

    Science.gov (United States)

    Yokohata, Tokuta; Tanaka, Katsumasa; Nishina, Kazuya; Takanashi, Kiyoshi; Emori, Seita; Kiguchi, Masashi; Iseri, Yoshihiko; Honda, Yasushi; Okada, Masashi; Masaki, Yoshimitsu; Yamamoto, Akitomo; Shigemitsu, Masahito; Yoshimori, Masakazu; Sueyoshi, Tetsuo; Iwase, Kenta; Hanasaki, Naota; Ito, Akihiko; Sakurai, Gen; Iizumi, Toshichika; Oki, Taikan

    2015-04-01

    Anthropogenic climate change possibly causes various impacts on human society and ecosystem. Here, we call possible damages or benefits caused by the future climate change as "climate risks". Many climate risks are closely interconnected with each other by direct cause-effect relationship. In this study, the major climate risks are comprehensively summarized based on the survey of studies in the literature using IPCC AR5 etc, and their cause-effect relationship are visualized by a "network diagram". This research is conducted by the collaboration between the experts of various fields, such as water, energy, agriculture, health, society, and eco-system under the project called ICA-RUS (Integrated Climate Assessment - Risks, Uncertainties and Society). First, the climate risks are classified into 9 categories (water, energy, food, health, disaster, industry, society, ecosystem, and tipping elements). Second, researchers of these fields in our project survey the research articles, and pick up items of climate risks, and possible cause-effect relationship between the risk items. A long list of the climate risks is summarized into ~130, and that of possible cause-effect relationship between the risk items is summarized into ~300, because the network diagram would be illegible if the number of the risk items and cause-effect relationship is too large. Here, we only consider the risks that could occur if climate mitigation policies are not conducted. Finally, the chain of climate risks is visualized by creating a "network diagram" based on a network graph theory (Fruchtman & Reingold algorithm). Through the analysis of network diagram, we find that climate risks at various sectors are closely related. For example, the decrease in the precipitation under the global climate change possibly causes the decrease in river runoff and the decrease in soil moisture, which causes the changes in crop production. The changes in crop production can have an impact on society by

  4. Fuel cell electrode interconnect contact material encapsulation and method

    Science.gov (United States)

    Derose, Anthony J.; Haltiner, Jr., Karl J.; Gudyka, Russell A.; Bonadies, Joseph V.; Silvis, Thomas W.

    2016-05-31

    A fuel cell stack includes a plurality of fuel cell cassettes each including a fuel cell with an anode and a cathode. Each fuel cell cassette also includes an electrode interconnect adjacent to the anode or the cathode for providing electrical communication between an adjacent fuel cell cassette and the anode or the cathode. The interconnect includes a plurality of electrode interconnect protrusions defining a flow passage along the anode or the cathode for communicating oxidant or fuel to the anode or the cathode. An electrically conductive material is disposed between at least one of the electrode interconnect protrusions and the anode or the cathode in order to provide a stable electrical contact between the electrode interconnect and the anode or cathode. An encapsulating arrangement segregates the electrically conductive material from the flow passage thereby, preventing volatilization of the electrically conductive material in use of the fuel cell stack.

  5. Next generation space interconnect research and development in space communications

    Science.gov (United States)

    Collier, Charles Patrick

    2017-11-01

    Interconnect or "bus" is one of the critical technologies in design of spacecraft avionics systems that dictates its architecture and complexity. MIL-STD-1553B has long been used as the avionics backbone technology. As avionics systems become more and more capable and complex, however, limitations of MIL-STD-1553B such as insufficient 1 Mbps bandwidth and separability have forced current avionics architects and designers to use combination of different interconnect technologies in order to meet various requirements: CompactPCI is used for backplane interconnect; LVDS or RS422 is used for low and high-speed direct point-to-point interconnect; and some proprietary interconnect standards are designed for custom interfaces. This results in a very complicated system that consumes significant spacecraft mass and power and requires extensive resources in design, integration and testing of spacecraft systems.

  6. Optical backplane interconnect switch for data processors and computers

    Science.gov (United States)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  7. Solar-cell interconnect design for terrestrial photovoltaic modules

    Science.gov (United States)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1984-01-01

    Useful solar cell interconnect reliability design and life prediction algorithms are presented, together with experimental data indicating that the classical strain cycle (fatigue) curve for the interconnect material does not account for the statistical scatter that is required in reliability predictions. This shortcoming is presently addressed by fitting a functional form to experimental cumulative interconnect failure rate data, which thereby yields statistical fatigue curves enabling not only the prediction of cumulative interconnect failures during the design life of an array field, but also the quantitative interpretation of data from accelerated thermal cycling tests. Optimal interconnect cost reliability design algorithms are also derived which may allow the minimization of energy cost over the design life of the array field.

  8. Near-chip compliant layer for reducing perimeter stress during assembly process

    Energy Technology Data Exchange (ETDEWEB)

    Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

    2018-03-20

    A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

  9. Layered semiconductor neutron detectors

    Science.gov (United States)

    Mao, Samuel S; Perry, Dale L

    2013-12-10

    Room temperature operating solid state hand held neutron detectors integrate one or more relatively thin layers of a high neutron interaction cross-section element or materials with semiconductor detectors. The high neutron interaction cross-section element (e.g., Gd, B or Li) or materials comprising at least one high neutron interaction cross-section element can be in the form of unstructured layers or micro- or nano-structured arrays. Such architecture provides high efficiency neutron detector devices by capturing substantially more carriers produced from high energy .alpha.-particles or .gamma.-photons generated by neutron interaction.

  10. Basic properties of semiconductors

    CERN Document Server

    Landsberg, PT

    2013-01-01

    Since Volume 1 was published in 1982, the centres of interest in the basic physics of semiconductors have shifted. Volume 1 was called Band Theory and Transport Properties in the first edition, but the subject has broadened to such an extent that Basic Properties is now a more suitable title. Seven chapters have been rewritten by the original authors. However, twelve chapters are essentially new, with the bulk of this work being devoted to important current topics which give this volume an almost encyclopaedic form. The first three chapters discuss various aspects of modern band theory and the

  11. Electrowetting on semiconductors

    Science.gov (United States)

    Palma, Cesar; Deegan, Robert

    2015-01-01

    Applying a voltage difference between a conductor and a sessile droplet sitting on a thin dielectric film separating it from the conductor will cause the drop to spread. When the conductor is a good metal, the change of the drop's contact angle due to the voltage is given by the Young-Lippmann (YL) equation. Here, we report experiments with lightly doped, single crystal silicon as the conductive electrode. We derive a modified YL equation that includes effects due to the semiconductor and contact line pinning. We show that light induces a non-reversible wetting transition, and that our model agrees well with our experimental results.

  12. Semiconductor ionizino. radiation detectors

    International Nuclear Information System (INIS)

    1982-01-01

    Spectrometric semiconductor detectors of ionizing radiation with the electron-hole junction, based on silicon and germanium are presented. The following parameters are given for the individual types of germanium detectors: energy range of detected radiation, energy resolution given as full width at half maximum (FWHM) and full width at one tenth of maximum (FWTM) for 57 Co and 60 Co, detection sensitivity, optimal voltage, and electric capacitance at optimal voltage. For silicon detectors the value of FWHM for 239 Pu is given, the sensitive area and the depth of the sensitive area. (E.S.)

  13. Band structure of semiconductors

    CERN Document Server

    Tsidilkovski, I M

    2013-01-01

    Band Structure of Semiconductors provides a review of the theoretical and experimental methods of investigating band structure and an analysis of the results of the developments in this field. The book presents the problems, methods, and applications in the study of band structure. Topics on the computational methods of band structure; band structures of important semiconducting materials; behavior of an electron in a perturbed periodic field; effective masses and g-factors for the most commonly encountered band structures; and the treatment of cyclotron resonance, Shubnikov-de Haas oscillatio

  14. Development of thin pixel sensors and a novel interconnection technology for the SLHC

    International Nuclear Information System (INIS)

    Macchiolo, A.; Andricek, L.; Beimforde, M.; Dubbert, J.; Ghodbane, N.; Kortner, O.; Kroha, H.; Moser, H.G.; Nisius, R.; Richter, R.H.

    2008-01-01

    We present an R and D activity aiming to develop a new detector concept in the framework of the ATLAS pixel detector upgrade in view of the Super-LHC. The new devices combine 75-150 μm thick pixels sensors with a vertical integration technology. A new production of thin pixel sensors on n- and p-type material is under way at the MPI Semiconductor Laboratory. These devices will be connected to the ATLAS read-out electronics with the new Solid-Liquid InterDiffusion technique as an alternative to the bump-bonding process. We also plan for the signals to be extracted from the back of the electronics wafer through Inter-Chip-Vias. The compatibility of the Solid-Liquid InterDiffusion process with the silicon sensor functionality has already been demonstrated by measurements on two wafers hosting diodes with an active thickness of 50 μm

  15. Robust design and thermal fatigue life prediction of anisotropic conductive film flip chip package

    International Nuclear Information System (INIS)

    Nam, Hyun Wook

    2004-01-01

    The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF(Anisotropic Conductive Film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue life of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear bi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design Of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2 nd DOE was conducted to obtain RSM equation for the choose 3 design parameter. The coefficient of determination (R 2 ) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for Feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430μm, and 78μm, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter

  16. 76 FR 45248 - PJM Interconnection, L.L.C., PJM Power Providers Group v. PJM Interconnection, L.L.C...

    Science.gov (United States)

    2011-07-28

    ...-002; Docket No. EL11-20-001] PJM Interconnection, L.L.C., PJM Power Providers Group v. PJM Interconnection, L.L.C.; Supplemental Notice of Staff Technical Conference On June 13, 2011, the Commission issued... Resources Services, Inc., Maryland Public Service Commission, Monitoring Analytics, L.L.C., National Rural...

  17. 76 FR 39870 - PJM Interconnection, LLC; PJM Power Providers Group v. PJM Interconnection, LLC; Notice of Date...

    Science.gov (United States)

    2011-07-07

    .... EL11-20-001] PJM Interconnection, LLC; PJM Power Providers Group v. PJM Interconnection, LLC; Notice of... Sell Offers for Planned Generation Capacity Resources submitted into PJM's Reliability Pricing Model... presents an opportunity to exercise buyer market power; (2) whether the Fixed Resource Requirement (FRR...

  18. Interconnection issues in Ontario : a status check

    International Nuclear Information System (INIS)

    Helbronner, V.

    2010-01-01

    This PowerPoint presentation discussed wind and renewable energy interconnection issues in Ontario. The province's Green Energy Act established a feed-in tariff (FIT) program and provided priority connection access to the electricity system for renewable energy generation facilities that meet regulatory requirements. As a result of the province's initiatives, Hydro One has identified 20 priority transmission expansion projects and is focusing on servicing renewable resource clusters. As of October 2010, the Ontario Power Authority (OPA) has received 1469 MW of FIT contracts executed for wind projects. A further 5953 MW of wind projects are awaiting approval. A Korean consortium is now planning to develop 2500 MW of renewable energy projects in the province. The OPA has also been asked to develop an updated transmission expansion plan. Transmission/distribution availability tests (TAT/DAT) have been established to determine if there is sufficient connection availability for FIT application projects. Economic connection tests (ECTs) are conducted to assess whether grid upgrade costs to enable additional FIT capacity are justifiable. When projects pass the ECT, grid upgrades needed for the connection included in grid expansion plans. Ontario's long term energy plan was also reviewed. tabs., figs.

  19. Thermal Runaways in LHC Interconnections: Experiments

    CERN Document Server

    Willering, G P; Bottura, L; Scheuerlein, C; Verweij, A P

    2011-01-01

    The incident in the LHC in September 2008 occurred in an interconnection between two magnets of the 13 kA dipole circuit. This event was traced to a defect in one of the soldered joints between two superconducting cables stabilized by a copper busbar. Further investigation revealed defective joints of other types. A combination of (1) a poor contact between the superconducting cable and the copper stabilizer and (2) an electrical discontinuity in the stabilizer at the level of the connection can lead to an unprotected quench of the busbar. Once the heating power in the unprotected superconducting cable exceeds the heat removal capacity a thermal run-away occurs, resulting in a fast melt-down of the non-stabilized cable. We have performed a thorough investigation of the conditions upon which a thermal run-away in the defect can occur. To this aim, we have prepared heavily instrumented samples with well-defined and controlled defects. In this paper we describe the experiment, and the analysis of the data, and w...

  20. Single filament semiconductor laser

    International Nuclear Information System (INIS)

    Botez, D.

    1980-01-01

    A semiconductor laser comprising: a body of semiconductor material including a substrate having a surface and a pair of spaced, substantially parallel dove-tailed shaped grooves in said surface, said body having a pair of end surfaces between which said grooves extend, said end surfaces being reflective to light with at least one of said end surfaces being partially transparent to light a first epitaxial layer over said surface of the substrate and the surfaces of the grooves, said first epitaxial layer having a flat surface portion over the portion of the substrate surface between the grooves, a thin second epitaxial layer over said first epitaxial layer, a third epitaxial layer over said second epitaxial layer, said first and third epitaxial layers being of opposite conductivity types and the second epitaxial layer being the active recombination region of the laser with the light being generated therein in the vicinity of the portion which is over the flat surface portion of the first epitaxial layer, and a pair of contacts on said body with one contact being over said third epitaxial body and the other being on said substrate

  1. Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

    Science.gov (United States)

    Stinner, F. Scott

    As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

  2. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  3. II-VI semiconductor compounds

    CERN Document Server

    1993-01-01

    For condensed matter physicists and electronic engineers, this volume deals with aspects of II-VI semiconductor compounds. Areas covered include devices and applications of II-VI compounds; Co-based II-IV semi-magnetic semiconductors; and electronic structure of strained II-VI superlattices.

  4. Electronic structure of semiconductor interfaces

    Energy Technology Data Exchange (ETDEWEB)

    Herman, F

    1983-02-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered.

  5. Quantum transport in semiconductor nanowires

    NARCIS (Netherlands)

    Van Dam, J.

    2006-01-01

    This thesis describes a series of experiments aimed at understanding the low-temperature electrical transport properties of semiconductor nanowires. The semiconductor nanowires (1-100 nm in diameter) are grown from nanoscale gold particles via a chemical process called vapor-liquid-solid (VLS)

  6. Semiconductor photocatalysis principles and applications

    CERN Document Server

    Kisch, Horst

    2014-01-01

    Focusing on the basic principles of semiconductor photocatalysis, this book also gives a brief introduction to photochemistry, photoelectrochemistry, and homogeneous photocatalysis. In addition, the author - one of the leading authorities in the field - presents important environmental and practical aspects. A valuable, one-stop source for all chemists, material scientists, and physicists working in this area, as well as novice researchers entering semiconductor photocatalysis.

  7. Progress in semiconductor drift detectors

    International Nuclear Information System (INIS)

    Rehak, P.; Walton, J.; Gatti, E.

    1985-01-01

    Progress in testing semiconductor drift detectors is reported. Generally better position and energy resolutions were obtained than resolutions published previously. The improvement is mostly due to new electronics better matched to different detectors. It is shown that semiconductor drift detectors are becoming versatile and reliable detectors for position and energy measurements

  8. Semiconductor materials and their properties

    NARCIS (Netherlands)

    Reinders, Angelina H.M.E.; Verlinden, Pierre; van Sark, Wilfried; Freundlich, Alexandre; Reinders, Angele; Verlinden, Pierre; van Sark, Wilfried; Freundlich, Alexandre

    2017-01-01

    Semiconductor materials are the basic materials which are used in photovoltaic (PV) devices. This chapter introduces solid-state physics and semiconductor properties that are relevant to photovoltaics without spending too much time on unnecessary information. Usually atoms in the group of

  9. Optical coherent control in semiconductors

    DEFF Research Database (Denmark)

    Østergaard, John Erland; Vadim, Lyssenko; Hvam, Jørn Märcher

    2001-01-01

    of quantum control including the recent applications to semiconductors and nanostructures. We study the influence of inhomogeneous broadening in semiconductors on CC results. Photoluminescence (PL) and the coherent emission in four-wave mixing (FWM) is recorded after resonant excitation with phase...

  10. Terahertz Nonlinear Optics in Semiconductors

    DEFF Research Database (Denmark)

    Turchinovich, Dmitry; Hvam, Jørn Märcher; Hoffmann, Matthias C.

    2013-01-01

    We demonstrate the nonlinear optical effects – selfphase modulation and saturable absorption of a single-cycle THz pulse in a semiconductor. Resulting from THz-induced modulation of Drude plasma, these nonlinear optical effects, in particular, lead to self-shortening and nonlinear spectral...... breathing of a single-cycle THz pulse in a semiconductor....

  11. Electronic structure of semiconductor interfaces

    International Nuclear Information System (INIS)

    Herman, F.

    1983-01-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered. (Author) [pt

  12. Single chip camera active pixel sensor

    Science.gov (United States)

    Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

    2003-01-01

    A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

  13. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  14. Organic semiconductors in a spin

    CERN Document Server

    Samuel, I

    2002-01-01

    A little palladium can go a long way in polymer-based light-emitting diodes. Inorganic semiconductors such as silicon and gallium arsenide are essential for countless applications in everyday life, ranging from PCs to CD players. However, while they offer unrivalled computational speed, inorganic semiconductors are also rigid and brittle, which means that they are less suited to applications such as displays and flexible electronics. A completely different class of materials - organic semiconductors - are being developed for these applications. Organic semiconductors have many attractive features: they are easy to make, they can emit visible light, and there is tremendous scope for tailoring their properties to specific applications by changing their chemical structure. Research groups and companies around the world have developed a wide range of organic-semiconductor devices, including transistors, light-emitting diodes (LEDs), solar cells and lasers. (U.K.)

  15. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  16. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, Michael

    2010-07-19

    edge demonstrate that the active sensor area fraction can be increased to fulfill the requirements for the detector upgrades. A subset of sensors, irradiated up to the fluence expected at the sLHC demonstrated that thin sensors show a higher charge collection efficiency than expected from current radiation damage models. First thin diodes equipped with the SLID metallization and first test structures that were connected with SLID indicate that this novel interconnection as part of the ICV-SLID technology could be a suitable replacement for the present bump-bonding technology. Finally, a new calibration algorithm for the ATLAS pixel readout chips is presented which is used to lower the discriminator threshold from 4000 electrons to 2000 electrons, to account for the reduction of the signal size due to radiation damage and the reduced sensor thickness. (orig.)

  17. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    Beimforde, Michael

    2010-01-01

    sensor area fraction can be increased to fulfill the requirements for the detector upgrades. A subset of sensors, irradiated up to the fluence expected at the sLHC demonstrated that thin sensors show a higher charge collection efficiency than expected from current radiation damage models. First thin diodes equipped with the SLID metallization and first test structures that were connected with SLID indicate that this novel interconnection as part of the ICV-SLID technology could be a suitable replacement for the present bump-bonding technology. Finally, a new calibration algorithm for the ATLAS pixel readout chips is presented which is used to lower the discriminator threshold from 4000 electrons to 2000 electrons, to account for the reduction of the signal size due to radiation damage and the reduced sensor thickness. (orig.)

  18. Optics vs copper: from the perspective of "Thunderbolt" interconnect technology

    Science.gov (United States)

    Cheng, Hengju; Krause, Christine; Ko, Jamyuen; Gao, Miaobin; Liu, Guobin; Wu, Huichin; Qi, Mike; Lam, Chun-Chit

    2013-02-01

    Interconnect technology has been progressed at a very fast pace for the past decade. The signaling rates have steadily increased from 100:Mb/s to 25Gb/s. In every generation of interconnect technology evolution, optics always seems to take over at first, however, at the end, the cost advantage of copper wins over. Because of this, optical interconnects are limited to longer distance links where the attenuation in copper cable is too large for the integrated circuits to compensate. Optical interconnect has long been viewed as the premier solution in compared with copper interconnect. With the release of Thunderbolt technology, we are entering a new era in consumer electronics that runs at 10Gb/s line rate (20Gb/s throughput per connector interface). Thunderbolt interconnect technology includes both active copper cables and active optical cables as the transmission media which have very different physical characteristics. In order for optics to succeed in consumer electronics, several technology hurdles need to be cleared. For example, the optical cable needs to handle the consumer abuses such as pinch and bend. Also, the optical engine used in the active optical cable needs to be physically very small so that we don't change the looks and feels of the cable/connector. Most importantly, the cost of optics needs to come down significantly to effectively compete with the copper solution. Two interconnect technologies are compared and discussed on the relative cost, power consumption, form factor, density, and future scalability.

  19. Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects

    International Nuclear Information System (INIS)

    Majumder, M.K.; Pandya, N.D.; Kaushik, B.K.; Manhas, S.K.

    2013-01-01

    Carbon nanotube (CN T) can be considered as an emerging interconnect material in current nano scale regime. They are more promising than other interconnect materials such as Al or Cu because of their robustness to electromigration. This research paper aims to address the crosstalk-related issues (signal integrity) in interconnect lines. Different analytical models of single- (SWCNT), double- (DWCNT), and multiwalled CNTs (MWCNT) are studied to analyze the crosstalk delay at global interconnect lengths. A capacitively coupled three-line bus architecture employing CMOS driver is used for accurate estimation of crosstalk delay. Each line in bus architecture is represented with the equivalent RLC models of single and bundled SWCNT, DWCNT, and MWCNT interconnects. Crosstalk delay is observed at middle line (victim) when it switches in opposite direction with respect to the other two lines (aggressors). Using the data predicted by ITRS 2012, a comparative analysis on the basis of crosstalk delay is performed for bundled SWCNT/DWCNT and single MWCNT interconnects. It is observed that the overall crosstalk delay is improved by 40.92% and 21.37% for single MWCNT in comparison to bundled SWCNT and bundled DWCNT interconnects, respectively.

  20. Analysis of interconnecting energy systems over a synchronized life cycle

    International Nuclear Information System (INIS)

    Nian, Victor

    2016-01-01

    Highlights: • A methodology is developed for evaluating a life cycle of interconnected systems. • A new concept of partial temporal boundary is introduced via quantitative formulation. • The interconnecting systems are synchronized through the partial temporal boundary. • A case study on the life cycle of the coal–uranium system is developed. - Abstract: Life cycle analysis (LCA) using the process chain analysis (PCA) approach has been widely applied to energy systems. When applied to an individual energy system, such as coal or nuclear electricity generation, an LCA–PCA methodology can yield relatively accurate results with its detailed process representation based on engineering data. However, there are fundamental issues when applying conventional LCA–PCA methodology to a more complex life cycle, namely, a synchronized life cycle of interconnected energy systems. A synchronized life cycle of interconnected energy systems is established through direct interconnections among the processes of different energy systems, and all interconnecting systems are bounded within the same timeframe. Under such a life cycle formation, there are some major complications when applying conventional LCA–PCA methodology to evaluate the interconnecting energy systems. Essentially, the conventional system and boundary formulations developed for a life cycle of individual energy system cannot be directly applied to a life cycle of interconnected energy systems. To address these inherent issues, a new LCA–PCA methodology is presented in this paper, in which a new concept of partial temporal boundary is introduced to synchronize the interconnecting energy systems. The importance and advantages of these new developments are demonstrated through a case study on the life cycle of the coal–uranium system.

  1. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    Energy Technology Data Exchange (ETDEWEB)

    Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

    2005-02-11

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

  2. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  3. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    International Nuclear Information System (INIS)

    Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

    2005-01-01

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

  4. Ceramic thermal wind sensor based on advanced direct chip attaching package

    International Nuclear Information System (INIS)

    Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

    2014-01-01

    An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

  5. Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

    Science.gov (United States)

    Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

    2016-01-21

    Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

  6. A CMOS analog front-end chip for amperometric electrochemical sensors

    International Nuclear Information System (INIS)

    Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

    2015-01-01

    This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

  7. Electron scattering at interfaces in nano-scale vertical interconnects: A combined experimental and ab initio study

    Science.gov (United States)

    Lanzillo, Nicholas A.; Restrepo, Oscar D.; Bhosale, Prasad S.; Cruz-Silva, Eduardo; Yang, Chih-Chao; Youp Kim, Byoung; Spooner, Terry; Standaert, Theodorus; Child, Craig; Bonilla, Griselda; Murali, Kota V. R. M.

    2018-04-01

    We present a combined theoretical and experimental study on the electron transport characteristics across several representative interface structures found in back-end-of-line interconnect stacks for advanced semiconductor manufacturing: Cu/Ta(N)/Co/Cu and Cu/Ta(N)/Ru/Cu. In particular, we evaluate the impact of replacing a thin TaN barrier with Ta while considering both Co and Ru as wetting layers. Both theory and experiment indicate a pronounced reduction in vertical resistance when replacing TaN with Ta, regardless of whether a Co or Ru wetting layer is used. This indicates that a significant portion of the total vertical resistance is determined by electron scattering at the Cu/Ta(N) interface. The electronic structure of these nano-sized interconnects is analyzed in terms of the atom-resolved projected density of states and k-resolved transmission spectra at the Fermi level. This work further develops a fundamental understanding of electron transport and material characteristics in nano-sized interconnects.

  8. Interacting Social Processes on Interconnected Networks.

    Directory of Open Access Journals (Sweden)

    Lucila G Alvarez-Zuzek

    Full Text Available We propose and study a model for the interplay between two different dynamical processes -one for opinion formation and the other for decision making- on two interconnected networks A and B. The opinion dynamics on network A corresponds to that of the M-model, where the state of each agent can take one of four possible values (S = -2,-1, 1, 2, describing its level of agreement on a given issue. The likelihood to become an extremist (S = ±2 or a moderate (S = ±1 is controlled by a reinforcement parameter r ≥ 0. The decision making dynamics on network B is akin to that of the Abrams-Strogatz model, where agents can be either in favor (S = +1 or against (S = -1 the issue. The probability that an agent changes its state is proportional to the fraction of neighbors that hold the opposite state raised to a power β. Starting from a polarized case scenario in which all agents of network A hold positive orientations while all agents of network B have a negative orientation, we explore the conditions under which one of the dynamics prevails over the other, imposing its initial orientation. We find that, for a given value of β, the two-network system reaches a consensus in the positive state (initial state of network A when the reinforcement overcomes a crossover value r*(β, while a negative consensus happens for r βc. We develop an analytical mean-field approach that gives an insight into these regimes and shows that both dynamics are equivalent along the crossover line (r*, β*.

  9. Genomic Predictability of Interconnected Biparental Maize Populations

    Science.gov (United States)

    Riedelsheimer, Christian; Endelman, Jeffrey B.; Stange, Michael; Sorrells, Mark E.; Jannink, Jean-Luc; Melchinger, Albrecht E.

    2013-01-01

    Intense structuring of plant breeding populations challenges the design of the training set (TS) in genomic selection (GS). An important open question is how the TS should be constructed from multiple related or unrelated small biparental families to predict progeny from individual crosses. Here, we used a set of five interconnected maize (Zea mays L.) populations of doubled-haploid (DH) lines derived from four parents to systematically investigate how the composition of the TS affects the prediction accuracy for lines from individual crosses. A total of 635 DH lines genotyped with 16,741 polymorphic SNPs were evaluated for five traits including Gibberella ear rot severity and three kernel yield component traits. The populations showed a genomic similarity pattern, which reflects the crossing scheme with a clear separation of full sibs, half sibs, and unrelated groups. Prediction accuracies within full-sib families of DH lines followed closely theoretical expectations, accounting for the influence of sample size and heritability of the trait. Prediction accuracies declined by 42% if full-sib DH lines were replaced by half-sib DH lines, but statistically significantly better results could be achieved if half-sib DH lines were available from both instead of only one parent of the validation population. Once both parents of the validation population were represented in the TS, including more crosses with a constant TS size did not increase accuracies. Unrelated crosses showing opposite linkage phases with the validation population resulted in negative or reduced prediction accuracies, if used alone or in combination with related families, respectively. We suggest identifying and excluding such crosses from the TS. Moreover, the observed variability among populations and traits suggests that these uncertainties must be taken into account in models optimizing the allocation of resources in GS. PMID:23535384

  10. Ion implantation for semiconductors

    International Nuclear Information System (INIS)

    Grey-Morgan, T.

    1995-01-01

    Full text: Over the past two decades, thousands of particle accelerators have been used to implant foreign atoms like boron, phosphorus and arsenic into silicon crystal wafers to produce special embedded layers for manufacturing semiconductor devices. Depending on the device required, the atomic species, the depth of implant and doping levels are the main parameters for the implantation process; the selection and parameter control is totally automated. The depth of the implant, usually less than 1 micron, is determined by the ion energy, which can be varied between 2 and 600 keV. The ion beam is extracted from a Freeman or Bernas type ion source and accelerated to 60 keV before mass analysis. For higher beam energies postacceleration is applied up to 200 keV and even higher energies can be achieved by mass selecting multiplycharged ions, but with a corresponding reduction in beam output. Depending on the device to be manufactured, doping levels can range from 10 10 to 10 15 atoms/cm 2 and are controlled by implanter beam currents in the range up to 30mA; continuous process monitoring ensures uniformity across the wafer of better than 1 % . As semiconductor devices get smaller, additional sophistication is required in the design of the implanter. The silicon wafers charge electrically during implantation and this charge must be dissipated continuously to reduce the electrical stress in the device and avoid destructive electrical breakdown. Electron flood guns produce low energy electrons (below 10 electronvolts) to neutralize positive charge buildup and implanter design must ensure minimum contamination by other isotopic species and ensure low internal sputter rates. The pace of technology in the semiconductor industry is such that implanters are being built now for 256 Megabit circuits but which are only likely to be widely available five years from now. Several specialist companies manufacture implanter systems, each costing around US$5 million, depending on the

  11. The Enhanced Segment Interconnect for FASTBUS data communications

    International Nuclear Information System (INIS)

    Machen, D.R.; Downing, R.W.; Kirsten, F.A.; Nelson, R.O.

    1987-01-01

    The Enhanced Segment Interconnect concept (ESI) for improved FASTBUS data communications is a development supported by the U.S. Department of Energy under the Small Business Innovation Research (SBIR) program. The ESI will contain both the Segment Interconnect (SI) Tyhpe S-1 and an optional buffered interconnect for store-and-forward data communications; fiber-optic-coupled serial ports will provide optional data paths. The ESI can be applied in large FASTBUS-implemented physics experiments whose data-set or data-transmission distance requirements dictate alternate approaches to data communications. This paper describes the functions of the ESI and the status of its development, now 25% complete

  12. Semiconductor radiation detector

    Science.gov (United States)

    Bell, Zane W.; Burger, Arnold

    2010-03-30

    A semiconductor detector for ionizing electromagnetic radiation, neutrons, and energetic charged particles. The detecting element is comprised of a compound having the composition I-III-VI.sub.2 or II-IV-V.sub.2 where the "I" component is from column 1A or 1B of the periodic table, the "II" component is from column 2B, the "III" component is from column 3A, the "IV" component is from column 4A, the "V" component is from column 5A, and the "VI" component is from column 6A. The detecting element detects ionizing radiation by generating a signal proportional to the energy deposited in the element, and detects neutrons by virtue of the ionizing radiation emitted by one or more of the constituent materials subsequent to capture. The detector may contain more than one neutron-sensitive component.

  13. Semiconductor testing method

    International Nuclear Information System (INIS)

    Brown, Stephen.

    1992-01-01

    In a method of avoiding use of nuclear radiation, eg gamma rays, X-rays, electron beams, for testing semiconductor components for resistance to hard radiation, which hard radiation causes data corruption in some memory devices and 'latch-up' in others, similar fault effects can be achieved using a xenon or other 'light' flash gun even though the penetration of light is significantly less than that of gamma rays. The method involves treating a device with gamma radiation, measuring a particular fault current at the onset of a fault event, repeating the test with light to confirm the occurrence of the fault event at the same measured fault current, and using the fault current value as a reference for future tests using light on similar devices. (author)

  14. Radial semiconductor drift chambers

    International Nuclear Information System (INIS)

    Rawlings, K.J.

    1987-01-01

    The conditions under which the energy resolution of a radial semiconductor drift chamber based detector system becomes dominated by the step noise from the detector dark current have been investigated. To minimise the drift chamber dark current attention should be paid to carrier generation at Si/SiO 2 interfaces. This consideration conflicts with the desire to reduce the signal risetime: a higher drift field for shorter signal pulses requires a larger area of SiO 2 . Calculations for the single shaping and pseudo Gaussian passive filters indicate that for the same degree of signal risetime sensitivity in a system dominated by the step noise from the detector dark current, the pseudo Gaussian filter gives only a 3% improvement in signal/noise and 12% improvement in rate capability compared with the single shaper performance. (orig.)

  15. Energy distribution in semiconductors

    International Nuclear Information System (INIS)

    Ance, C.

    1979-01-01

    For various semiconductors the dispersive energy Esub(d) defined in the Wemple-Didomenico model is connected with the covalent and ionic energies Esub(h) and C. A continuous curve of ionicity against the ratio of the two energies Esub(A) and Esub(B), connected to Esub(h) and C is reported. Afromowitz's model is applied to the ternary compounds Gasub(1-x)Alsub(x)Sb using optical decomposition. From these results the average energy gap Esub(g) is given by Esub(g) = D 0 M 0 sup((IB))/(epsilon 1 (0)-1) where M 0 sup((IB)) is the interband transition contribution to the optical moment M 0 . (author)

  16. Organic Semiconductor Photovoltaics

    Science.gov (United States)

    Sariciftci, Niyazi Serdar

    2005-03-01

    Recent developments on organic photovoltaic elements are reviewed. Semiconducting conjugated polymers and molecules as well as nanocrystalline inorganic semiconductors are used in composite thin films. The photophysics of such photoactive devices is based on the photoinduced charge transfer from donor type semiconducting molecules onto acceptor type molecules such as Buckminsterfullerene, C60 and/or nanoparticles. Similar to the first steps in natural photosynthesis, this photoinduced electron transfer leads to a number of potentially interesting applications which include sensitization of the photoconductivity and photovoltaic phenomena. Examples of photovoltaic architectures are discussed with their potential in terrestrial solar energy conversion. Several materials are introduced and discussed for their photovoltaic activities. Furthermore, nanomorphology has been investigated with AFM, SEM and TEM. The morphology/property relationship for a given photoactive system is found to be a major effect.

  17. Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

    Directory of Open Access Journals (Sweden)

    Vasu R. Sah

    2014-06-01

    Full Text Available It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities’ features at the time of first production of these potential biochips.

  18. Review on the dynamics of semiconductor nanowire lasers

    Science.gov (United States)

    Röder, Robert; Ronning, Carsten

    2018-03-01

    Semiconductor optoelectronic devices have contributed tremendously to the technological progress in the past 50-60 years. Today, they also play a key role in nanophotonics stimulated by the inherent limitations of electronic integrated circuits and the growing demand for faster communications on chip. In particular, the field of ‘nanowire photonics’ has emerged including the search for coherent light sources with a nano-scaled footprint. The past decade has been dedicated to find suitable semiconductor nanowire (NW) materials for such nanolasers. Nowadays, such NW lasers consistently work at room temperature covering a huge spectral range from the ultraviolet down to the mid-infrared depending on the band gap of the NW material. Furthermore, first approaches towards the modification and optimization of such NW laser devices have been demonstrated. The underlying dynamics of the electronic and photonic NW systems have also been studied very recently, as they need to be understood in order to push the technological relevance of nano-scaled coherent light sources. Therefore, this review will first present novel measurement approaches in order to study the ultrafast temporal and optical mode dynamics of individual NW laser devices. Furthermore, these fundamental new insights are reviewed and deeply discussed towards the efficient control and adjustment of the dynamics in semiconductor NW lasers.

  19. Microeconomics of process control in semiconductor manufacturing

    Science.gov (United States)

    Monahan, Kevin M.

    2003-06-01

    Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

  20. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2016-01-01

    On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range.......On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range....