WorldWideScience

Sample records for semiconductor chip designs

  1. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  2. All-polymer organic semiconductor laser chips: Parallel fabrication and encapsulation

    DEFF Research Database (Denmark)

    Vannahme, Christoph; Klinkhammer, Sönke; Christiansen, Mads Brøkner

    2010-01-01

    Organic semiconductor lasers are of particular interest as tunable visible laser light sources. For bringing those to market encapsulation is needed to ensure practicable lifetimes. Additionally, fabrication technologies suitable for mass production must be used. We introduce all-polymer chips...... comprising encapsulated distributed feedback organic semiconductor lasers. Several chips are fabricated in parallel by thermal nanoimprint of the feedback grating on 4? wafer scale out of poly(methyl methacrylate) (PMMA) and cyclic olefin copolymer (COC). The lasers consisting of the organic semiconductor...... tris(8- hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2- methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM) are hermetically sealed by thermally bonding a polymer lid. The organic thin film is placed in a basin within the substrate and is not in direct contact to the lid...

  3. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  4. 76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

    Science.gov (United States)

    2011-12-21

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With... importation, and the sale within the United States after importation of certain semiconductor chips with DRAM.... 7,906,809 (``the `809 patent''). The complaint further alleges that an industry in the United States...

  5. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  6. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  7. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Science.gov (United States)

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

  8. Introduction to Open Core Protocol Fastpath to System-on-Chip Design

    CERN Document Server

    Schwaderer, W David

    2012-01-01

    This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

  9. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Science.gov (United States)

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  10. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Directory of Open Access Journals (Sweden)

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  11. Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

    Science.gov (United States)

    Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

    2018-02-01

    The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

  12. Lab-on-a-chip for label free biological semiconductor analysis of Staphylococcal Enterotoxin B

    NARCIS (Netherlands)

    Yang, Minghui; Sun, Steven; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

    2010-01-01

    We describe a new lab-on-a-chip (LOC) which utilizes a biological semiconductor (BSC) transducer for label free analysis of Staphylococcal Enterotoxin B (SEB) (or other biological interactions) directly and electronically. BSCs are new transducers based on electrical percolation through a

  13. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  14. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  15. Toward designing semiconductor-semiconductor heterojunctions for photocatalytic applications

    Science.gov (United States)

    Zhang, Liping; Jaroniec, Mietek

    2018-02-01

    Semiconductor photocatalysts show a great potential for environmental and energy-related applications, however one of the major disadvantages is their relatively low photocatalytic performance due to the recombination of electron-hole pairs. Therefore, intensive research is being conducted toward design of heterojunctions, which have been shown to be effective for improving the charge-transfer properties and efficiency of photocatalysts. According to the type of band alignment and direction of internal electric field, heterojunctions are categorized into five different types, each of which is associated with its own charge transfer characteristics. Since the design of heterojunctions requires the knowledge of band edge positions of component semiconductors, the commonly used techniques for the assessment of band edge positions are reviewed. Among them the electronegativity-based calculation method is applied for a large number of popular visible-light-active semiconductors, including some widely investigated bismuth-containing semiconductors. On basis of the calculated band edge positions and the type of component semiconductors reported, heterojunctions composed of the selected bismuth-containing semiconductors are proposed. Finally, the most popular synthetic techniques for the fabrication of heterojunctions are briefly discussed.

  16. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  17. Introduction to semiconductor manufacturing technology

    CERN Document Server

    2012-01-01

    IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

  18. Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

    Science.gov (United States)

    Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

    2011-04-25

    Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

  19. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  20. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  1. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  2. Essential issues in SOC design designing complex systems-on-chip

    CERN Document Server

    Lin, Youn-long Steve

    2007-01-01

    Covers issues related to system-on-chip (SoC) design. This book covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.

  3. Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

    Science.gov (United States)

    Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

    2006-01-01

    We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

  4. Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

    Science.gov (United States)

    Seiler, David G.

    1997-10-01

    A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

  5. Design and Development of a Portable Metal Chip Baler using A System Design Approach

    Directory of Open Access Journals (Sweden)

    Hassan Mohd Fahrul

    2017-01-01

    Full Text Available A large amount of metal chips at workplace will result in untidy and unsafe condition thus measurements of safety are needed in some industries, where the metal chips will be collected and put into a container until the volume is sufficient to be recycled. Due to that reason, the metal chips require a lot of spaces for storage before going to recycle. In this study, a portable metal chip baler as a device for compacting those metal chips is presented based on a system approach of engineering design. Basically, the system design evolves through four phases of development that are started from conceptual design, preliminary system design, detail design and development to system test and evaluation. The portable metal chip baler uses current technology such as pneumatic cylinder to compress the metal chips so that the system capable to operate efficiently. The output from this system is the metal chips are compacted into a block shape and a working prototype was developed to prove the concept of the system. As a summary, the conceptual design of portable metal chip baler was proven and was presented using the philosophy of the systems design approach. This tool may assists workers especially in the Small-Medium Enterprise (SME manufacturing industries, school or universities’ workshops for managing metal chips easily and systematically.

  6. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  7. Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

    Science.gov (United States)

    Michaelides, Stylianos

    Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

  8. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  9. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  10. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    OpenAIRE

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

  11. Design of systems on a chip design and test

    CERN Document Server

    Reis, Ricardo; Jess, Jochen AG

    2007-01-01

    Addresses the design challenges associated with generations of the semiconductor technology. This book includes contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs.

  12. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  13. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Science.gov (United States)

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  14. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  15. A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

    Science.gov (United States)

    Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

    2012-01-01

    This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

  16. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  17. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    NARCIS (Netherlands)

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be

  18. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  19. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  20. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  1. Dry etching technology for semiconductors

    CERN Document Server

    Nojiri, Kazuo

    2015-01-01

    This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

  2. Circuit design techniques for non-crystalline semiconductors

    CERN Document Server

    Sambandan, Sanjiv

    2012-01-01

    Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

  3. Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

    International Nuclear Information System (INIS)

    Chen Haijin; Lu Shengli; Shi Longxing

    2009-01-01

    A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

  4. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  5. Testing of modern semiconductor memory structures

    NARCIS (Netherlands)

    Gaydadjiev, G.N.

    2007-01-01

    In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

  6. α-particle shielding of semiconductor device

    International Nuclear Information System (INIS)

    McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

    1981-01-01

    Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

  7. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  8. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  9. Design of an on-chip reflectance map

    NARCIS (Netherlands)

    Terwisscha van Scheltinga, Jeroen; Smit, Jaap; Bosma, Marco

    1995-01-01

    A reflectance map design is described which uses a minimal amount of memory for the table, in order to be applicable as an on-chip shader. The shader is designed for use with the volumetric super resolution hardware, which performs shading at supersampled locations. However, the design may be used

  10. SEU tolerant memory design for the ATLAS pixel readout chip

    International Nuclear Information System (INIS)

    Menouni, M; Barbero, M; Breugnon, P; Fougeron, D; Gensolen, F; Arutinov, D; Backhaus, M; Gonella, L; Hemperek, T; Karagounis, M; Beccherle, R; Darbo, G; Caminada, L; Dube, S; Fleury, J; Garcia-Sciveres, M; Gnani, D; Jensen, F; Gromov, V; Kluit, R

    2013-01-01

    The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

  11. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  12. Embedded memory design for multi-core and systems on chip

    CERN Document Server

    Mohammad, Baker

    2014-01-01

    This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit ...

  13. High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-07-30

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  14. Where the chips fall: environmental health in the semiconductor industry.

    Science.gov (United States)

    Chepesiuk, R

    1999-09-01

    Three recent lawsuits are focusing public attention on the environmental and occupational health effects of the world's largest and fastest growing manufacturing sector-the $150 billion semiconductor industry. The suits allege that exposure to toxic chemicals in semiconductor manufacturing plants led to adverse health effects such as miscarriage and cancer among workers. To manufacture computer components, the semiconductor industry uses large amounts of hazardous chemicals including hydrochloric acid, toxic metals and gases, and volatile solvents. Little is known about the long-term health consequences of exposure to chemicals by semiconductor workers. According to industry critics, the semiconductor industry also adversely impacts the environment, causing groundwater and air pollution and generating toxic waste as a by-product of the semiconductor manufacturing process. In contrast, the U.S. Bureau of Statistics shows the semiconductor industry as having a worker illness rate of about one-third of the average of all manufacturers, and advocates defend the industry, pointing to recent research collaborations and product replacement as proof that semiconductor manufacturers adequately protect both their employees and the environment.

  15. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  16. Key techniques for space-based solar pumped semiconductor lasers

    Science.gov (United States)

    He, Yang; Xiong, Sheng-jun; Liu, Xiao-long; Han, Wei-hua

    2014-12-01

    In space, the absence of atmospheric turbulence, absorption, dispersion and aerosol factors on laser transmission. Therefore, space-based laser has important values in satellite communication, satellite attitude controlling, space debris clearing, and long distance energy transmission, etc. On the other hand, solar energy is a kind of clean and renewable resources, the average intensity of solar irradiation on the earth is 1353W/m2, and it is even higher in space. Therefore, the space-based solar pumped lasers has attracted much research in recent years, most research focuses on solar pumped solid state lasers and solar pumped fiber lasers. The two lasing principle is based on stimulated emission of the rare earth ions such as Nd, Yb, Cr. The rare earth ions absorb light only in narrow bands. This leads to inefficient absorption of the broad-band solar spectrum, and increases the system heating load, which make the system solar to laser power conversion efficiency very low. As a solar pumped semiconductor lasers could absorb all photons with energy greater than the bandgap. Thus, solar pumped semiconductor lasers could have considerably higher efficiencies than other solar pumped lasers. Besides, solar pumped semiconductor lasers has smaller volume chip, simpler structure and better heat dissipation, it can be mounted on a small satellite platform, can compose satellite array, which can greatly improve the output power of the system, and have flexible character. This paper summarizes the research progress of space-based solar pumped semiconductor lasers, analyses of the key technologies based on several application areas, including the processing of semiconductor chip, the design of small and efficient solar condenser, and the cooling system of lasers, etc. We conclude that the solar pumped vertical cavity surface-emitting semiconductor lasers will have a wide application prospects in the space.

  17. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  18. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  19. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Directory of Open Access Journals (Sweden)

    Ho-Chiao Chuang

    2014-06-01

    Full Text Available This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments.

  20. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Science.gov (United States)

    Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

    2014-01-01

    This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

  1. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    Energy Technology Data Exchange (ETDEWEB)

    Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

    2005-02-11

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

  2. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    International Nuclear Information System (INIS)

    Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

    2005-01-01

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

  3. Design of an Enterobacteriaceae Pan-genome Microarray Chip

    DEFF Research Database (Denmark)

    Lukjancenko, Oksana; Ussery, David

    2010-01-01

    -density microarray chip has been designed, using 116 Enterobacteriaceae genome sequences, taking into account the enteric pan-genome. Probes for the microarray were checked in silico and performance of the chip, based on experimental strains from four different genera, demonstrate a relatively high ability...... to distinguish those strains on genus, species, and pathotype/serovar levels. Additionally, the microarray performed well when investigating which genes were found in a given strain of interest. The Enterobacteriaceae pan-genome microarray, based on 116 genomes, provides a valuable tool for determination...

  4. Metal-semiconductor interface in extreme temperature conditions

    International Nuclear Information System (INIS)

    Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

    2008-01-01

    We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

  5. An FPGA design flow for reconfigurable network-based multi-processor systems on chip

    NARCIS (Netherlands)

    Kumar, A.; Hansson, M.A; Huisken, J.; Corporaal, H.

    2007-01-01

    Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity

  6. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  7. Robust design and thermal fatigue life prediction of anisotropic conductive film flip chip package

    International Nuclear Information System (INIS)

    Nam, Hyun Wook

    2004-01-01

    The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF(Anisotropic Conductive Film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue life of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear bi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design Of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2 nd DOE was conducted to obtain RSM equation for the choose 3 design parameter. The coefficient of determination (R 2 ) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for Feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430μm, and 78μm, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter

  8. Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

    Energy Technology Data Exchange (ETDEWEB)

    Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-12-01

    Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

  9. X-ray imaging with photon counting hybrid semiconductor pixel detectors

    CERN Document Server

    Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

    1999-01-01

    Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

  10. An integrated semiconductor device enabling non-optical genome sequencing.

    Science.gov (United States)

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  11. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  12. Design of an Elliptic Curve Cryptography processor for RFID tag chips.

    Science.gov (United States)

    Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

    2014-09-26

    Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

  13. Resistance transition assisted geometry enhanced magnetoresistance in semiconductors

    International Nuclear Information System (INIS)

    Luo, Zhaochu; Zhang, Xiaozhong

    2015-01-01

    Magnetoresistance (MR) reported in some non-magnetic semiconductors (particularly silicon) has triggered considerable interest owing to the large magnitude of the effect. Here, we showed that MR in lightly doped n-Si can be significantly enhanced by introducing two diodes and proper design of the carrier path [Wan, Nature 477, 304 (2011)]. We designed a geometrical enhanced magnetoresistance (GEMR) device whose room-temperature MR ratio reaching 30% at 0.065 T and 20 000% at 1.2 T, respectively, approaching the performance of commercial MR devices. The mechanism of this GEMR is: the diodes help to define a high resistive state (HRS) and a low resistive state (LRS) in device by their openness and closeness, respectively. The ratio of apparent resistance between HRS and LRS is determined by geometry of silicon wafer and electrodes. Magnetic field could induce a transition from LRS to HRS by reshaping potential and current distribution among silicon wafer, resulting in a giant enhancement of intrinsic MR. We expect that this GEMR could be also realized in other semiconductors. The combination of high sensitivity to low magnetic fields and large high-field response should make this device concept attractive to the magnetic field sensing industry. Moreover, because this MR device is based on a conventional silicon/semiconductor platform, it should be possible to integrate this MR device with existing silicon/semiconductor devices and so aid the development of silicon/semiconductor-based magnetoelectronics. Also combining MR devices and semiconducting devices in a single Si/semiconductor chip may lead to some novel devices with hybrid function, such as electric-magnetic-photonic properties. Our work demonstrates that the charge property of semiconductor can be used in the magnetic sensing industry, where the spin properties of magnetic materials play a role traditionally

  14. K-band single-chip electron spin resonance detector.

    Science.gov (United States)

    Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

    2012-04-01

    We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

  15. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  16. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  17. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  18. Solid-Phase Immunoassay of Polystyrene-Encapsulated Semiconductor Coreshells for Cardiac Marker Detection

    Directory of Open Access Journals (Sweden)

    Sanghee Kim

    2012-01-01

    Full Text Available A solid-phase immunoassay of polystyrene-encapsulated semiconductor nanoparticles was demonstrated for cardiac troponin I (cTnI detection. CdSe/ZnS coreshells were encapsulated with a carboxyl-functionalized polystyrene nanoparticle to capture the target antibody through a covalent bonding and to eliminate the photoblinking and toxicity of semiconductor luminescent immunosensor. The polystyrene-encapsulated CdSe/ZnS fluorophores on surface-modified glass chip identified cTnI antigens at the level of ~ng/mL. It was an initial demonstration of diagnostic chip for monitoring a cardiovascular disease.

  19. Designing solution-processable air-stable liquid crystalline crosslinkable semiconductors

    DEFF Research Database (Denmark)

    McCulloch, I.; Bailey, C.; Genevicius, K.

    2006-01-01

    organic light emitting diode displays, low frequency radio frequency identification tag and other low performance electronics. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes...... the development of reactive mesogen semiconductors, which form large crosslinked LC domains on polymerization within mesophases. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed...

  20. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  1. SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

    Energy Technology Data Exchange (ETDEWEB)

    MCBRAYER,JOHN D.

    2000-12-01

    This report summarizes the results of work conducted by the Semiconductor Manufacturing Technologies Program at Sandia National Laboratories (Sandia) during 1999. This work was performed by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaF{sub 2}); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program.

  2. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  3. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

  4. Dynamic spin polarization by orientation-dependent separation in a ferromagnet-semiconductor hybrid

    Science.gov (United States)

    Korenev, V. L.; Akimov, I. A.; Zaitsev, S. V.; Sapega, V. F.; Langer, L.; Yakovlev, D. R.; Danilov, Yu. A.; Bayer, M.

    2012-07-01

    Integration of magnetism into semiconductor electronics would facilitate an all-in-one-chip computer. Ferromagnet/bulk semiconductor hybrids have been, so far, mainly considered as key devices to read out the ferromagnetism by means of spin injection. Here we demonstrate that a Mn-based ferromagnetic layer acts as an orientation-dependent separator for carrier spins confined in a semiconductor quantum well that is set apart from the ferromagnet by a barrier only a few nanometers thick. By this spin-separation effect, a non-equilibrium electron-spin polarization is accumulated in the quantum well due to spin-dependent electron transfer to the ferromagnet. The significant advance of this hybrid design is that the excellent optical properties of the quantum well are maintained. This opens up the possibility of optical readout of the ferromagnet's magnetization and control of the non-equilibrium spin polarization in non-magnetic quantum wells.

  5. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...... to the transaction-level model. The thesis, as a whole makes contributions by describing a design methodology for networked multiprocessor embedded systems at three layers of abstraction from system-level through transaction-level to the cycle accurate level as well as demonstrating it practically by implementing...

  6. Organic semiconductors in sensor applications

    CERN Document Server

    Malliaras, George; Owens, Róisín

    2008-01-01

    Organic semiconductors offer unique characteristics such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing, and facile integration with chemical and biological functionalities. These characteristics have prompted the application of organic semiconductors and their devices in physical, chemical, and biological sensors. This book covers this rapidly emerging field by discussing both optical and electrical sensor concepts. Novel transducers based on organic light-emitting diodes and organic thin-film transistors, as well as systems-on-a-chip architectures are presented. Functionalization techniques to enhance specificity are outlined, and models for the sensor response are described.

  7. Research on and design of key circuits in RFID tag chip for container management

    Directory of Open Access Journals (Sweden)

    Wang Wenjie

    2016-01-01

    Full Text Available This paper introduces the design of semi-passive RFID tag chip capable of monitoring container safety. A system framework complying with requirements by ISO/IEC 18000-6C is firstly presented, and then differences from the key units of common passive chip, such as switch-state monitoring circuit, power management unit and anti-shake design in baseband processor, are elaborated. The main function of such a chip is to record the container opening frequency during transportation. Finally, the realizations of each unit’s function are simulated.

  8. Thermal Design of Power Electronic Circuits

    CERN Document Server

    Künzi, R.

    2015-06-15

    The heart of every switched mode converter consists of several switching semiconductor elements. Due to their non-ideal behaviour there are ON state and switching losses heating up the silicon chip. That heat must effectively be transferred to the environment in order to prevent overheating or even destruction of the element. For a cost-effective design, the semiconductors should be operated close to their thermal limits. Unfortunately the chip temperature cannot be measured directly. Therefore a detailed understanding of how losses arise, including their quantitative estimation, is required. Furthermore, the heat paths to the environment must be understood in detail. This paper describes the main issues of loss generation and its transfer to the environment and how it can be estimated by the help of datasheets and/or experiments.

  9. A Designed Room Temperature Multilayered Magnetic Semiconductor

    Science.gov (United States)

    Bouma, Dinah Simone; Charilaou, Michalis; Bordel, Catherine; Duchin, Ryan; Barriga, Alexander; Farmer, Adam; Hellman, Frances; Materials Science Division, Lawrence Berkeley National Lab Team

    2015-03-01

    A room temperature magnetic semiconductor has been designed and fabricated by using an epitaxial antiferromagnet (NiO) grown in the (111) orientation, which gives surface uncompensated magnetism for an odd number of planes, layered with the lightly doped semiconductor Al-doped ZnO (AZO). Magnetization and Hall effect measurements of multilayers of NiO and AZO are presented for varying thickness of each. The magnetic properties vary as a function of the number of Ni planes in each NiO layer; an odd number of Ni planes yields on each NiO layer an uncompensated moment which is RKKY-coupled to the moments on adjacent NiO layers via the carriers in the AZO. This RKKY coupling oscillates with the AZO layer thickness, and it disappears entirely in samples where the AZO is replaced with undoped ZnO. The anomalous Hall effect data indicate that the carriers in the AZO are spin-polarized according to the direction of the applied field at both low temperature and room temperature. NiO/AZO multilayers are therefore a promising candidate for spintronic applications demanding a room-temperature semiconductor.

  10. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  11. Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

    Science.gov (United States)

    Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

    1997-01-01

    The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

  12. Design and Construction of an Atomic Clock on an Atom Chip

    International Nuclear Information System (INIS)

    Reinhard, Friedemann

    2009-01-01

    We describe the design and construction of an atomic clock on an atom chip, intended as a secondary standard, with a stability in the range of few 10 -13 at 1 s. This clock is based on a two-photon transition between the hyperfine states |F = 1; m F = -1> and |2; 1> of the electronic ground state of the 87 Rb atom. This transition is interrogated using a Ramsey scheme, operating on either a cloud of thermal atoms or a Bose-Einstein condensate. In contrast to atomic fountain clocks, this clock is magnetically trapped on an atom chip. We describe a theoretical model of the clock stability and the design and construction of a dedicated apparatus. It is able to control the magnetic field at the relative 10 -5 level and features a hybrid atom chip, containing DC conductors as well as a microwave transmission line for the clock interrogation. (author)

  13. Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

    Science.gov (United States)

    Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

    2014-09-01

    The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

  14. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  15. Bacteria inside semiconductors as potential sensor elements: biochip progress.

    Science.gov (United States)

    Sah, Vasu R; Baier, Robert E

    2014-06-24

    It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

  16. Field testing for cosmic ray soft errors in semiconductor memories

    International Nuclear Information System (INIS)

    O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

    1996-01-01

    This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

  17. Digitally tunable dual wavelength emission from semiconductor ring lasers with filtered optical feedback

    International Nuclear Information System (INIS)

    Khoder, Mulham; Verschaffelt, Guy; Nguimdo, Romain Modeste; Danckaert, Jan; Leijtens, Xaveer; Bolk, Jeroen

    2013-01-01

    We report on a novel integrated approach to obtain dual wavelength emission from a semiconductor laser based on on-chip filtered optical feedback. Using this approach, we show experiments and numerical simulations of dual wavelength emission of a semiconductor ring laser. The filtered optical feedback is realized on-chip by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifiers are placed in the feedback loop in order to control the feedback strength of each wavelength channel independently. By tuning the current injected into each of the amplifiers, we can effectively cancel the gain difference between the wavelength channels due to fabrication and material dichroism, thus resulting in stable dual wavelength emission. We also explore the accuracy needed in the operational parameters to maintain this dual wavelength emission. (letter)

  18. A microprocessor based on a two-dimensional semiconductor

    Science.gov (United States)

    Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

    2017-04-01

    The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

  19. Near-chip compliant layer for reducing perimeter stress during assembly process

    Energy Technology Data Exchange (ETDEWEB)

    Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

    2018-03-20

    A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

  20. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  1. Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

    Science.gov (United States)

    Ashenafi, Emeshaw

    Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

  2. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif; Arsalan, Muhammad; Roy, L; Salama, Khaled N.

    2012-01-01

    with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been

  3. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  4. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

  5. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  6. DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

    NARCIS (Netherlands)

    Stefanov, T.; Pimentel, A.; Nikolov, H.; Ha, S.; Teich, J.

    2017-01-01

    The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design

  7. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    DEFF Research Database (Denmark)

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... and display ultrasensitive mass detection in air. A mass sensitivity of 4 ag/Hz has been determined in air by placing a single glycerine drop, having a measured weight of 57 fg, at the apex of a cantilever and subsequently measuring a frequency shift of 14.8 kHz. CMOS integration enables electrostatic...

  8. Analysis and simulation of semiconductor devices

    CERN Document Server

    Selberherr, Siegfried

    1984-01-01

    The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

  9. Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

    Science.gov (United States)

    Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

    2017-10-01

    In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

  10. Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

    Science.gov (United States)

    Holmes, Anna M.; Monaco, Lisa; Barnes, Cindy; Spearing, Scott; Jenkins, Andy; Johnson, Todd; Mayer, Derek; Cole, Helen

    2003-01-01

    The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

  11. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  12. Driving the SID chip: Assembly language, composition, and sound design for the C64

    Directory of Open Access Journals (Sweden)

    James Newman

    2017-12-01

    Full Text Available The MOS6581, more commonly known as the Sound Interface Device, or SID chip, was the sonic heart of the Commodore 64 home computer. By considering the chip’s development, specification, uses and creative abuses by composers and programmers, alongside its continuing legacy, this paper argues that, more than any other device, the SID chip is responsible for shaping the sound of videogame music. Compared with the brutal atonality of chips such as Atari’s TIA, the SID chip offers a complex 3-channel synthesizer with dynamic waveform selection, per-channel ADSR envelopes, multi-mode filter, ring and cross modulation. However, while the specification is sophisticated, the exploitation of the vagaries and imperfections of the chip are just as significant to its sonic character. As such, the compositional, sound design and programming techniques developed by 1980s composer-coders like Rob Hubbard and Martin Galway are central in defining the distinctive sound of C64 gameplay. Exploring the affordances of the chip and the distinctive ways they were harnessed, the argument of this paper centers on the inexorable link between the technological and the musical. Crucially, composers like Hubbard et al. developed their own bespoke low-level drivers to interface with the SID chip to create pseudo-polyphony through rapid arpeggiation and channel sharing, drum synthesis through waveform manipulation, portamento, and even sample playback. This paper analyses the indivisibility of sound design, synthesis and composition in the birth of these musical forms and aesthetics, and assesses their impact on what would go on to be defined as chiptunes.

  13. Microelectronics used for Semiconductor Imaging Detectors

    CERN Document Server

    Heijne, Erik H M

    2010-01-01

    Semiconductor crystal technology, microelectronics developments and nuclear particle detection have been in a relation of symbiosis, all the way from the beginning. The increase of complexity in electronics chips can now be applied to obtain much more information on the incident nuclear radiation. Some basic technologies are described, in order to acquire insight in possibilities and limitations for the most recent detectors.

  14. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  15. Rational In Silico Design of an Organic Semiconductor with Improved Electron Mobility.

    Science.gov (United States)

    Friederich, Pascal; Gómez, Verónica; Sprau, Christian; Meded, Velimir; Strunk, Timo; Jenne, Michael; Magri, Andrea; Symalla, Franz; Colsmann, Alexander; Ruben, Mario; Wenzel, Wolfgang

    2017-11-01

    Organic semiconductors find a wide range of applications, such as in organic light emitting diodes, organic solar cells, and organic field effect transistors. One of their most striking disadvantages in comparison to crystalline inorganic semiconductors is their low charge-carrier mobility, which manifests itself in major device constraints such as limited photoactive layer thicknesses. Trial-and-error attempts to increase charge-carrier mobility are impeded by the complex interplay of the molecular and electronic structure of the material with its morphology. Here, the viability of a multiscale simulation approach to rationally design materials with improved electron mobility is demonstrated. Starting from one of the most widely used electron conducting materials (Alq 3 ), novel organic semiconductors with tailored electronic properties are designed for which an improvement of the electron mobility by three orders of magnitude is predicted and experimentally confirmed. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. A CMOS G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor network application

    Energy Technology Data Exchange (ETDEWEB)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing, E-mail: zhiqunli@seu.edu.cn [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2011-05-15

    A G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 {mu}m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  17. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  18. 75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

    Science.gov (United States)

    2010-03-02

    ... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

  19. Design and implementation of a hybrid circuit system for micro sensor signal processing

    International Nuclear Information System (INIS)

    Wang Zhuping; Chen Jing; Liu Ruqing

    2011-01-01

    This paper covers a micro sensor analog signal processing circuit system (MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board. The ultimate aim is to form a hybrid circuit used for mixed-signal processing, which can be applied to a micro sensor flow monitoring system. (semiconductor integrated circuits)

  20. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  1. Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

    Directory of Open Access Journals (Sweden)

    Vasu R. Sah

    2014-06-01

    Full Text Available It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities’ features at the time of first production of these potential biochips.

  2. Design of Water Temperature Control System Based on Single Chip Microcomputer

    Science.gov (United States)

    Tan, Hanhong; Yan, Qiyan

    2017-12-01

    In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

  3. Recent advances in design and fabrication of on-chip micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Wang, Chunlei

    2012-06-01

    Recent development in miniaturized electronic devices has increased the demand for power sources that are sufficiently compact and can potentially be integrated on a chip with other electronic components. Miniaturized electrochemical capacitors (EC) or micro-supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. Recently, we have developed several types of micro-supercapacitors with different structural designs and active materials. Carbon-Microelectromechanical Systems (C-MEMS) with three dimensional (3D) interdigital structures are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of pseudo-capacitive materials. More recently, we have also developed microsupercapacitor based on hybrid graphene and carbon nanotube interdigital structures. In this paper, the recent advances in design and fabrication of on-chip micro-supercapacitors are reviewed.

  4. Photonics-on-a-chip: recent advances in integrated waveguides as enabling detection elements for real-world, lab-on-a-chip biosensing applications.

    Science.gov (United States)

    Washburn, Adam L; Bailey, Ryan C

    2011-01-21

    By leveraging advances in semiconductor microfabrication technologies, chip-integrated optical biosensors are poised to make an impact as scalable and multiplexable bioanalytical measurement tools for lab-on-a-chip applications. In particular, waveguide-based optical sensing technology appears to be exceptionally amenable to chip integration and miniaturization, and, as a result, the recent literature is replete with examples of chip-integrated waveguide sensing platforms developed to address a wide range of contemporary analytical challenges. As an overview of the most recent advances within this dynamic field, this review highlights work from the last 2-3 years in the areas of grating-coupled, interferometric, photonic crystal, and microresonator waveguide sensors. With a focus towards device integration, particular emphasis is placed on demonstrations of biosensing using these technologies within microfluidically controlled environments. In addition, examples of multiplexed detection and sensing within complex matrices--important features for real-world applicability--are given special attention.

  5. Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

    CERN Document Server

    Liberali, Valentino; The ATLAS collaboration

    2016-01-01

    We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

  6. Programmable System-on-Chip (PSoC) Embedded Readout Designs for Liquid Helium Level Sensors.

    Science.gov (United States)

    Parasakthi, C; Gireesan, K; Usha Rani, R; Sheela, O K; Janawadkar, M P

    2014-08-01

    This article reports the development of programmable system-on-chip (PSoC)-based embedded readout designs for liquid helium level sensors using resistive liquid vapor discriminators. The system has been built for the measurement of liquid helium level in a concave-bottomed, helmet-shaped, fiber-reinforced plastic cryostat for magnetoencephalography. This design incorporates three carbon resistors as cost-effective sensors, which are mounted at desired heights inside the cryostat and were used to infer the liquid helium level by measuring their temperature-dependent resistance. Localized electrical heating of the carbon resistors was used to discriminate whether the resistor is immersed in liquid helium or its vapor by exploiting the difference in the heat transfer rates in the two environments. This report describes a single PSoC chip for the design and development of a constant current source to drive the three carbon resistors, a multiplexer to route the sensor outputs to the analog-to-digital converter (ADC), a buffer to avoid loading of the sensors, an ADC for digitizing the data, and a display using liquid crystal display cum light-emitting diode modules. The level sensor readout designed with a single PSoC chip enables cost-effective and reliable measurement system design. © 2014 Society for Laboratory Automation and Screening.

  7. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  8. Normalization and experimental design for ChIP-chip data

    Directory of Open Access Journals (Sweden)

    Alekseyenko Artyom A

    2007-06-01

    Full Text Available Abstract Background Chromatin immunoprecipitation on tiling arrays (ChIP-chip has been widely used to investigate the DNA binding sites for a variety of proteins on a genome-wide scale. However, several issues in the processing and analysis of ChIP-chip data have not been resolved fully, including the effect of background (mock control subtraction and normalization within and across arrays. Results The binding profiles of Drosophila male-specific lethal (MSL complex on a tiling array provide a unique opportunity for investigating these topics, as it is known to bind on the X chromosome but not on the autosomes. These large bound and control regions on the same array allow clear evaluation of analytical methods. We introduce a novel normalization scheme specifically designed for ChIP-chip data from dual-channel arrays and demonstrate that this step is critical for correcting systematic dye-bias that may exist in the data. Subtraction of the mock (non-specific antibody or no antibody control data is generally needed to eliminate the bias, but appropriate normalization obviates the need for mock experiments and increases the correlation among replicates. The idea underlying the normalization can be used subsequently to estimate the background noise level in each array for normalization across arrays. We demonstrate the effectiveness of the methods with the MSL complex binding data and other publicly available data. Conclusion Proper normalization is essential for ChIP-chip experiments. The proposed normalization technique can correct systematic errors and compensate for the lack of mock control data, thus reducing the experimental cost and producing more accurate results.

  9. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  10. A study on the optical parts for a semiconductor laser module

    Energy Technology Data Exchange (ETDEWEB)

    Oh, Jun-Girl; Lee, Dong-Kil; Kim, Yang-Gyu; Lee, Kwang-Hoon; Park, Young-Sik [Korea Photonics Technology Institute, Gwangju (Korea, Republic of); Jang, Kwang-Ho [Hanvit Optoline, Gwangju (Korea, Republic of); Kang, Seung-Goo [COSET, Gwangju (Korea, Republic of)

    2014-11-15

    A semiconductor laser module consists of a LD (laser diode) chip that generates a laser beam, two cylindrical lenses to collimate the laser beam, a high-reflection mirror to produce a large output by collecting the laser beam, a collimator lens to guide the laser beam to an optical fiber and a protection filter to block reflected laser light that might damage the LD chip. The cylindrical lenses used in a semiconductor laser module are defined as FACs (fast axis collimators) and SACs (slow axis collimators) and are attached to the system module to control the shape of the laser beam. The FAC lens and the SAC lens are made of a glass material to protect the lenses from thermal deformation. In addition, they have aspheric shapes to improve optical performances. This paper presents a mold core grinding process for an asymmetrical aspheric lens and a GMP (glass molding press), what can be used to make aspheric cylindrical lenses for use as FACs or SACs, and a protection filter made by using IAD (ion-beam-assisted deposition). Finally, we developed the aspheric cylindrical lenses and the protection filter for a 10-W semiconductor laser module.

  11. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  12. Optically coupled semiconductor device

    Energy Technology Data Exchange (ETDEWEB)

    Kumagaya, Naoki

    1988-11-18

    This invention concerns an optically coupled semiconductor device using the light as input signal and a MOS transistor for the output side in order to control on-off of the output side by the input signal which is insulated from the output. Concerning this sort of element, when a MOS transistor and a load resistance are planned to be accumulated on the same chip, a resistor and control of impurity concentration of the channel, etc. become necessary despite that the only formation of a simple P-N junction is enough, for a solar cell, hence cost reduction thereof cannot be done. In order to remove this defect, this invention offers an optically coupled semiconductor device featuring that two solar cells are connected in reverse parallel between the gate sources of the output MOS transistors and an operational light emitting element is individually set facing a respective solar cell. 4 figs.

  13. Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

    CERN Document Server

    Poikela, Tuomas; Paakkulainen, J

    2010-01-01

    The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

  14. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G.; Kosel, Jü rgen

    2016-01-01

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  15. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan

    2016-08-26

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  16. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Chinthaka P. Gooneratne

    2016-08-01

    Full Text Available The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA for the manipulation of superparamagnetic beads (SPBs, and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

  17. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  18. A new electrode design for ambipolar injection in organic semiconductors.

    Science.gov (United States)

    Kanagasekaran, Thangavel; Shimotani, Hidekazu; Shimizu, Ryota; Hitosugi, Taro; Tanigaki, Katsumi

    2017-10-17

    Organic semiconductors have attracted much attention for low-cost, flexible and human-friendly optoelectronics. However, achieving high electron-injection efficiency is difficult from air-stable electrodes and cannot be equivalent to that of holes. Here, we present a novel concept of electrode composed of a bilayer of tetratetracontane (TTC) and polycrystalline organic semiconductors (pc-OSC) covered by a metal layer. Field-effect transistors of single-crystal organic semiconductors with the new electrodes of M/pc-OSC/TTC (M: Ca or Au) show both highly efficient electron and hole injection. Contact resistance for electron injection from Au/pc-OSC/TTC and hole injection from Ca/pc-OSC/TTC are comparable to those for electron injection from Ca and hole injection from Au, respectively. Furthermore, the highest field-effect mobilities of holes (22 cm 2  V -1  s -1 ) and electrons (5.0 cm 2  V -1  s -1 ) are observed in rubrene among field-effect transistors with electrodes so far proposed by employing Ca/pc-OSC/TTC and Au/pc-OSC/TTC electrodes for electron and hole injection, respectively.One of technological challenges building organic electronics is efficient injection of electrons at metal-semiconductor interfaces compared to that of holes. The authors show an air-stable electrode design with induced gap states, which support Fermi level pinning and thus ambipolar carrier injection.

  19. Development of a chip-based ingroove microplasma source: Design, characterization, and diagnostics

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuemei; Meng, Fanying; Yuan, Xin; Yan, Yanyue; Zhao, Zhongjun; Duan, Yixiang, E-mail: yduan@scu.edu.cn [Research Center of Analytical Instrumentation, College of Chemistry and College of Life Science Sichuan University, Chengdu (China); Tang, Jie [State Key Laboratory of Transient Optics and Photonics, Xi' an Institute of Optics and Precision Mechanics of CAS, Xi' an (China)

    2014-03-10

    A chip-based ingroove microplasma source was designed for molecular emission spectrometry by using a space-confined direct current duct in air. The voltage-current characteristics of different size generators, emission spectroscopy of argon were discussed, respectively. It is found that the emission intensity of excited Ar and N{sub 2} approaches its maximum near the cathode, while OH and O peaks most likely appear close to the anode. The electron density, electronic excitation temperature, rotational temperature, and vibrational temperature of the argon plasma were also calculated. More importantly, the chip-based ingroove microplasma shows much better stability compared with its counterparts.

  20. A CMOS analog front-end chip for amperometric electrochemical sensors

    International Nuclear Information System (INIS)

    Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

    2015-01-01

    This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

  1. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Science.gov (United States)

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  2. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  3. Performance of Multithreaded Chip Multiprocessors And Implications for Operating System Design

    OpenAIRE

    Fedorova, Alexandra; Seltzer, Margo I.; Small, Christopher A.; Nussbaum, Daniel

    2005-01-01

    An operating system’s design is often influenced by the architecture of the target hardware. While uniprocessor and multiprocessor architectures are well understood, such is not the case for multithreaded chip multiprocessors (CMT) – a new generation of processors designed to improve performance of memory-intensive applications. The first systems equipped with CMT processors are just becoming available, so it is critical that we now understand how to obtain the best performance from such syst...

  4. Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

    Science.gov (United States)

    Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

    2004-07-01

    A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

  5. Integration of microelectronic chips in microfluidic systems on printed circuit board

    International Nuclear Information System (INIS)

    Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

    2012-01-01

    A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

  6. Design and construct of a tunable semiconductor laser

    Directory of Open Access Journals (Sweden)

    J. Sabbaghzadeh

    2000-06-01

    Full Text Available   In this paper we explain in detail the design of a semiconductor laser coupled with the reflected beams from a grating. Since the beams reflected are diffracted at different angles, only one component of them can be resonated in the cavity. This technique reduces the output frequency of the laser and increases its stability.   Since this system has various applications in the spectroscopy, gas concentrations, air pollution measurements, investigation of atomic and molecular structure, and so on, system is believed to be simple and accurate. This design is made for the first time in Iran and its reliability has been tested by the measurement of the rubidium atom, and the result is given.

  7. Design, realization and test of a rad-hard 2D-compressor and packing chip for high energy physics experiments

    International Nuclear Information System (INIS)

    Antinori, Samuele; Falchieri, Davide; Gabrielli, Alessandro; Gandolfi, Enzo

    2004-01-01

    CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 μm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN

  8. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  9. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    Energy Technology Data Exchange (ETDEWEB)

    Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  10. Design and FPGA-implementation of multilayer neural networks with on-chip learning

    International Nuclear Information System (INIS)

    Haggag, S.S.M.Y

    2008-01-01

    Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

  11. How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

    International Nuclear Information System (INIS)

    Pfeiffer, K.F.G.

    2003-01-01

    Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

  12. Gigabit chips: A case history of a transfer of federal technology

    Energy Technology Data Exchange (ETDEWEB)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs. (JDH)

  13. Gigabit chips: A case history of a transfer of federal technology

    International Nuclear Information System (INIS)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs

  14. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  15. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    Directory of Open Access Journals (Sweden)

    Xin Wang

    2007-01-01

    Full Text Available Two network-on-chip (NoC designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

  16. Chip-Oriented Fluorimeter Design and Detection System Development for DNA Quantification in Nano-Liter Volumes

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2009-12-01

    Full Text Available The chip-based polymerase chain reaction (PCR system has been developed in recent years to achieve DNA quantification. Using a microstructure and miniature chip, the volume consumption for a PCR can be reduced to a nano-liter. With high speed cycling and a low reaction volume, the time consumption of one PCR cycle performed on a chip can be reduced. However, most of the presented prototypes employ commercial fluorimeters which are not optimized for fluorescence detection of such a small quantity sample. This limits the performance of DNA quantification, especially low experiment reproducibility. This study discusses the concept of a chip-oriented fluorimeter design. Using the analytical model, the current study analyzes the sensitivity and dynamic range of the fluorimeter to fit the requirements for detecting fluorescence in nano-liter volumes. Through the optimized processes, a real-time PCR on a chip system with only one nano-liter volume test sample is as sensitive as the commercial real-time PCR machine using the sample with twenty micro-liter volumes. The signal to noise (S/N ratio of a chip system for DNA quantification with hepatitis B virus (HBV plasmid samples is 3 dB higher. DNA quantification by the miniature chip shows higher reproducibility compared to the commercial machine with respect to samples of initial concentrations from 103 to 105 copies per reaction.

  17. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  18. Semiconductor-inspired design principles for superconducting quantum computing.

    Science.gov (United States)

    Shim, Yun-Pil; Tahan, Charles

    2016-03-17

    Superconducting circuits offer tremendous design flexibility in the quantum regime culminating most recently in the demonstration of few qubit systems supposedly approaching the threshold for fault-tolerant quantum information processing. Competition in the solid-state comes from semiconductor qubits, where nature has bestowed some very useful properties which can be utilized for spin qubit-based quantum computing. Here we begin to explore how selective design principles deduced from spin-based systems could be used to advance superconducting qubit science. We take an initial step along this path proposing an encoded qubit approach realizable with state-of-the-art tunable Josephson junction qubits. Our results show that this design philosophy holds promise, enables microwave-free control, and offers a pathway to future qubit designs with new capabilities such as with higher fidelity or, perhaps, operation at higher temperature. The approach is also especially suited to qubits on the basis of variable super-semi junctions.

  19. Design and Characterisation of III-V Semiconductor Nanowire Lasers

    Science.gov (United States)

    Saxena, Dhruv

    The development of small, power-efficient lasers underpins many of the technologies that we utilise today. Semiconductor nanowires are promising for miniaturising lasers to even smaller dimensions. III-V semiconductors, such as Gallium Arsenide (GaAs) and Indium Phosphide (InP), are the most widely used materials for optoelectronic devices and so the development of nanowire lasers based on these materials is expected to have technologically significant outcomes. This PhD dissertation presents a comprehensive study of the design of III-V semiconductor nanowire lasers, with bulk and quantum confined active regions. Based on the design, various III-V semiconductor nanowire lasers are demonstrated, namely, GaAs nanowire lasers, GaAs/AlGaAs multi-quantum well (MQW) nanowire lasers and InP nanowire lasers. These nanowire lasers are shown to operate at room temperature, have low thresholds, and lase from different transverse modes. The structural and optoelectronic quality of nanowire lasers are characterised via electron microscopy and photoluminescence spectroscopic techniques. Lasing is characterised in all these devices by optical pumping. The lasing characteristics are analysed by rate equation modelling and the lasing mode(s) in these devices is characterised by threshold gain modelling, polarisation measurements and Fourier plane imaging. Firstly, GaAs nanowire lasers that operate at room temperature are demonstrated. This is achieved by determining the optimal nanowire diameter to reduce threshold gain and by passivating nanowires to improve their quantum efficiency (QE). High-quality surface passivated GaAs nanowires of suitable diameters are grown. The growth procedure is tailored to improve both QE and structural uniformity of nanowires. Room-temperature lasing is demonstrated from individual nanowires and lasing is characterised to be from TM01 mode by threshold gain modelling. To lower threshold even further, nanowire lasers with GaAs/AlGaAs coaxial multi

  20. Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link

    Science.gov (United States)

    Sangirov, Jamshid; Nguyen, Nga T. H.; Ngo, Trong-Hieu; Im, Dong-min; Ukaegbu, Augustine I.; Lee, Tae-Woo; Cho, Mu Hee; Park, Hyo-Hoon

    2010-02-01

    An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

  1. Optical trapping with Bessel beams generated from semiconductor lasers

    International Nuclear Information System (INIS)

    Sokolovskii, G S; Dudelev, V V; Losev, S N; Soboleva, K K; Deryagin, A G; Kuchinskii, V I; Sibbett, W; Rafailov, E U

    2014-01-01

    In this paper, we study generation of Bessel beams from semiconductor lasers with high beam propagation parameter M 2 and their utilization for optical trapping and manipulation of microscopic particles including living cells. The demonstrated optical tweezing with diodegenerated Bessel beams paves the way to replace their vibronic-generated counterparts for a range of applications towards novel lab-on-a-chip configurations

  2. Multimedia Terminal System-on-Chip Design and Simulation

    Directory of Open Access Journals (Sweden)

    Barbieri Ivano

    2005-01-01

    Full Text Available This paper proposes a design approach based on integrated architectural and system-on-chip (SoC simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW digital signal processors (DSPs, the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

  3. Superconducting detectors for semiconductor quantum photonics

    International Nuclear Information System (INIS)

    Reithmaier, Guenther M.

    2015-01-01

    In this thesis we present the first successful on-chip detection of quantum light, thereby demonstrating the monolithic integration of superconducting single photon detectors with individually addressable semiconductor quantum dots in a prototypical quantum photonic circuit. Therefore, we optimized both the deposition of high quality superconducting NbN thin films on GaAs substrates and the fabrication of superconducting detectors and successfully integrated these novel devices with GaAs/AlGaAs ridge waveguides loaded with self-assembled InGaAs quantum dots.

  4. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  5. Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

    Science.gov (United States)

    Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

    2011-01-01

    The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

  6. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-05-05

    ... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

  7. Cancer and reproductive risks in the semiconductor industry.

    Science.gov (United States)

    LaDou, Joseph; Bailar, John C

    2007-01-01

    Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

  8. Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

    Science.gov (United States)

    Celik, Cihangir

    -scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement

  9. Ceramic thermal wind sensor based on advanced direct chip attaching package

    International Nuclear Information System (INIS)

    Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

    2014-01-01

    An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

  10. Semiconductor Ion Implanters

    International Nuclear Information System (INIS)

    MacKinnon, Barry A.; Ruffell, John P.

    2011-01-01

    In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion! Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intel product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.

  11. Blasting detonators incorporating semiconductor bridge technology

    Energy Technology Data Exchange (ETDEWEB)

    Bickes, R.W. Jr.

    1994-05-01

    The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

  12. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  13. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  14. Sensor development at the semiconductor laboratory of the Max-Planck-Society

    Science.gov (United States)

    Bähr, A.; Lechner, P.; Ninkovic, J.

    2017-12-01

    For more than twenty years the semiconductor laboratory of the Max-Planck Society (MPG-HLL) is developing high-performing, specialised, scientific silicon sensors including the integration of amplifying electronics on the sensor chip. This paper summarises the actual status of these devices like pnCCDs and DePFET Active Pixel Sensors and their applications.

  15. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  16. Blood cleaner on-chip design for artificial human kidney manipulation

    Directory of Open Access Journals (Sweden)

    Suwanpayak N

    2011-05-01

    Full Text Available N Suwanpayak1, MA Jalil2, MS Aziz3, FD Ismail3, J Ali3, PP Yupapin11Nanoscale Science and Engineering Research Alliance (N'SERA, Advanced Research Center for Photonics, Faculty of Science, King Mongkut's Institute of Technology, Ladkrabang, Bangkok, Thailand; 2Ibnu Sina Institute of Fundamental Science Studies (IIS, 3Institute of Advanced Photonics Science, Nanotechnology Research Alliance, Universiti Teknologi Malaysia, Johor Bahru, MalaysiaAbstract: A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney, and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.Keywords: optical trapping, blood dialysis, blood cleaner, human kidney manipulation

  17. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  18. A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

    Science.gov (United States)

    Sheng, Duo; Hong, Min-Rong

    2016-10-14

    This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

  19. Electronics Industry Study Report: Semiconductors and Defense Electronics

    Science.gov (United States)

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  20. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  1. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  2. Possibilities for mixed mode chip manufacturing in EUROPRACTICE

    Science.gov (United States)

    Das, C.

    1997-02-01

    EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

  3. Miniature interferometer for refractive index measurement in microfluidic chip

    Science.gov (United States)

    Chen, Minghui; Geiser, Martial; Truffer, Frederic; Song, Chengli

    2012-12-01

    The design and development of the miniaturized interferometer for measurement of the refractive index or concentration of sub-microliter volume aqueous solution in microfludic chip is presented. It is manifested by a successful measurement of the refractive index of sugar-water solution, by utilizing a laser diode for light source and the small robust instrumentation for practical implementation. Theoretically, the measurement principle and the feasibility of the system are analyzed. Experimental device is constructed with a diode laser, lens, two optical plate and a complementary metal oxide semiconductor (CMOS). Through measuring the positional changes of the interference fringes, the refractive index change are retrieved. A refractive index change of 10-4 is inferred from the measured image data. The entire system is approximately the size of half and a deck of cards and can operate on battery power for long time.

  4. Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

    Science.gov (United States)

    Pechal, M.; Besse, J.-C.; Mondal, M.; Oppliger, M.; Gasparinetti, S.; Wallraff, A.

    2016-08-01

    A switch capable of routing microwave signals at cryogenic temperatures is a desirable component for state-of-the-art experiments in many fields of applied physics, including but not limited to quantum-information processing, communication, and basic research in engineered quantum systems. Conventional mechanical switches provide low insertion loss but disturb operation of dilution cryostats and the associated experiments by heat dissipation. Switches based on semiconductors or microelectromechanical systems have a lower thermal budget but are not readily integrated with current superconducting circuits. Here we design and test an on-chip switch built by combining tunable transmission-line resonators with microwave beam splitters. The device is superconducting and as such dissipates a negligible amount of heat. It is compatible with current superconducting circuit fabrication techniques, operates with a bandwidth exceeding 100 MHz, is capable of handling photon fluxes on the order of 1 05 μ s-1 , equivalent to powers exceeding -90 dBm , and can be switched within approximately 6-8 ns. We successfully demonstrate operation of the device in the quantum regime by integrating it on a chip with a single-photon source and using it to route nonclassical itinerant microwave fields at the single-photon level.

  5. Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

    2017-09-01

    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

  6. Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2010-01-01

    Full Text Available Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design.

  7. Origami chip-on-sensor design: progress and new developments

    International Nuclear Information System (INIS)

    Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

    2013-01-01

    The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

  8. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  9. Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

    Science.gov (United States)

    Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

    2008-02-01

    We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

  10. Device reliability challenges for modern semiconductor circuit design – a review

    Directory of Open Access Journals (Sweden)

    C. Schlünder

    2009-05-01

    Full Text Available Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1. Degradation mechanisms like Negative Bias Temperature Instability (NBTI or Hot Carrier Injection (HCI lead to parameter drifts during operation adding on top of the process variations.

    The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

    An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

  11. The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

    CERN Document Server

    Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

  12. Design of 20-44 GHz broadband doubler MMIC

    International Nuclear Information System (INIS)

    Li Qin; Wang Zhigong; Li Wei

    2010-01-01

    This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at V DD = 3.5 V, V SS = -3.5 V, I d = 200 mA and the chip size is 1.5 x 1.8 mm 2 . (semiconductor integrated circuits)

  13. Global Production Networks, Innovation, and Work: Why Chip and System Design in the IT Industry are Moving to Asia

    OpenAIRE

    Dieter Ernst; Boy Luethje

    2003-01-01

    This paper was prepared as an issue paper, to be discussed at the Planning Meeting of the SSRC on "Emerging Pathways to Innovation in Asia," September 12-13, 2003. The paper describes a research project that explores why chip design is moving to Asia, despite its high knowledge-intensity. Trade economists would search for an answer by looking at differences in the cost of employing a chip design engineer and comparative factor and resource endowments. However, an analysis of Asia's comparativ...

  14. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  15. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  16. Design of a one-chip board microcontrol unit for active vibration control of a naval ship mounting system

    International Nuclear Information System (INIS)

    Oh, Jong-Seok; Choi, Seung-Bok; Han, Young-Min; Nguyen, Vien-Quoc; Moon, Seok-Jun

    2012-01-01

    This work presents an experimental implementation of a user-tunable one-chip board microcontrol unit which is specifically designed for vibration control of the active mounting system for naval ships. The proposed mounting system consists of four active mounts supporting vibration-sensitive equipment. Each active mount constitutes a rubber element, an inertial mass and the piezostack actuator. It is designed for particular applications that require effective isolation performance against wide frequency ranges, such as naval ship equipment. After describing the configuration of the active mount, dynamic characteristics of the rubber element and the piezostack actuator are experimentally identified. Accordingly, the proposed mounting system is constructed and the governing equations of motion are formulated. In order to attenuate the unwanted vibrations transferred from the upper mass, a feedforward controller with fast Fourier algorithm is designed and experimentally realized using the one-chip microcontrol board which is specially made for this practical application. In order to evaluate the performance of the one-chip microcontrol unit, vibration control results of the proposed active mounting system are presented in the frequency domain. (technical note)

  17. Design and implementation of an ultra-low power passive UHF RFID tag

    International Nuclear Information System (INIS)

    Shen Jinpeng; Wang Xin'an; Liu Shan; Zong Hongqiang; Huang Jinfeng; Yang Xin; Feng Xiaoxing; Ge Binjie

    2012-01-01

    This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of −12 dBm. (semiconductor integrated circuits)

  18. Semiconductor radiation detection systems

    CERN Document Server

    2010-01-01

    Covers research in semiconductor detector and integrated circuit design in the context of medical imaging using ionizing radiation. This book explores other applications of semiconductor radiation detection systems in security applications such as luggage scanning, dirty bomb detection and border control.

  19. Design and evaluation of modelocked semiconductor lasers for low noise and high stability

    DEFF Research Database (Denmark)

    Yvind, Kresten; Larsson, David; Christiansen, Lotte Jin

    2005-01-01

    We present work on design of monolithic mode-locked semiconductor lasers with focus on the gain medium. The use of highly inverted quantum wells in a low-loss waveguide enables both low quantum noise, low-chirped pulses and a large stability region. Broadband noise measurements are performed...

  20. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  1. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    International Nuclear Information System (INIS)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm 2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is −10.7 dBm/−8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is −0.6 °C/0.5 °C (−1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (−30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode. (semiconductor integrated circuits)

  2. Monolithic integration of microfluidic channels and semiconductor lasers

    Science.gov (United States)

    Cran-McGreehin, Simon J.; Dholakia, Kishan; Krauss, Thomas F.

    2006-08-01

    We present a fabrication method for the monolithic integration of microfluidic channels into semiconductor laser material. Lasers are designed to couple directly into the microfluidic channel, allowing submerged particles pass through the output beams of the lasers. The interaction between particles in the channel and the lasers, operated in either forward or reverse bias, allows for particle detection, and the optical forces can be used to trap and move particles. Both interrogation and manipulation are made more amenable for lab-on-a-chip applications through monolithic integration. The devices are very small, they require no external optical components, have perfect intrinsic alignment, and can be created with virtually any planar configuration of lasers in order to perform a variety of tasks. Their operation requires no optical expertise and only low electrical power, thus making them suitable for computer interfacing and automation. Insulating the pn junctions from the fluid is the key challenge, which is overcome by using photo-definable SU8-2000 polymer.

  3. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...... routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower...

  4. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2011-03-17

    ... existence of a domestic industry. The Commission's notice of investigation named several respondents...; Freescale Semiconductor Malaysia Sdn. Bhd. of Malaysia; Freescale Semiconductor Pte. Ltd. of Singapore; Mouser Electronics, Inc. of Mansfield, Texas; and Motorola Inc. of Schaumburg, Illinois. On August 16...

  5. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  6. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    International Nuclear Information System (INIS)

    Ma Haifeng; Zhou Feng

    2010-01-01

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 x 320 μm 2 , which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  7. Design and analysis of spiral inductors

    CERN Document Server

    Haobijam, Genemala

    2013-01-01

    The book addresses the critical challenges faced by the ever-expanding wireless communication market and the increasing frequency of operation due to continuous innovation of high performance integrated passive devices. The challenges like low quality factor, design complexity, manufacturability, processing cost, etc., are studied with examples and specifics. Silicon on-chip inductor was first reported in 1990 by Nguyen and Meyer in a 0.8 µm silicon bipolar complementary metal oxide semiconductor technology (BiCMOS). Since then, there has been an enormous progress in the research on the perfo

  8. An AES chip with DPA resistance using hardware-based random order execution

    International Nuclear Information System (INIS)

    Yu Bo; Li Xiangyu; Chen Cong; Sun Yihe; Wu Liji; Zhang Xiangmin

    2012-01-01

    This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm 2 . A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance. (semiconductor integrated circuits)

  9. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    International Nuclear Information System (INIS)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

  10. Integrated materials design of organic semiconductors for field-effect transistors.

    Science.gov (United States)

    Mei, Jianguo; Diao, Ying; Appleton, Anthony L; Fang, Lei; Bao, Zhenan

    2013-05-08

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm(2)/(V s). In this perspective, we highlight some of the major milestones along the way to provide a historical view of OFET development, introduce the integrated molecular design concepts and process engineering approaches that lead to the current success, and identify the challenges ahead to make OFETs applicable in real applications.

  11. Molecular Electrical Doping of Organic Semiconductors: Fundamental Mechanisms and Emerging Dopant Design Rules.

    Science.gov (United States)

    Salzmann, Ingo; Heimel, Georg; Oehzelt, Martin; Winkler, Stefanie; Koch, Norbert

    2016-03-15

    -Dirac occupation of which ultimately determines the doping efficiency, thus emerges as key challenge. As a first step, the formation of charge transfer complexes is identified as being detrimental to the doping efficiency, which suggests sterically shielding the functional core of dopant molecules as an additional design rule to complement the requirement of low ionization energies or high electron affinities in efficient n-type or p-type dopants, respectively. In an extended outlook, we finally argue that, to fully meet this challenge, an improved understanding is required of just how the admixture of dopant molecules to organic semiconductors does affect the density of states: compared with their inorganic counterparts, traps for charge carriers are omnipresent in organic semiconductors due to structural and chemical imperfections, and Coulomb attraction between ionized dopants and free charge carriers is typically stronger in organic semiconductors owing to their lower dielectric constant. Nevertheless, encouraging progress is being made toward developing a unifying picture that captures the entire range of doping induced phenomena, from ion-pair to complex formation, in both conjugated polymers and molecules. Once completed, such a picture will provide viable guidelines for synthetic and supramolecular chemistry that will enable further technological advances in organic and hybrid organic/inorganic devices.

  12. Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

    Science.gov (United States)

    Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

    2015-01-12

    Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

  13. Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

    Science.gov (United States)

    Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

    2016-01-21

    Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

  14. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    International Nuclear Information System (INIS)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua

    2010-01-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 μm 2 . Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  15. Design and simulation of MEMS microvalves for silicon photonic biosensor chip

    Science.gov (United States)

    Amemiya, Yoshiteru; Nakashima, Yuuto; Maeda, Jun; Yokoyama, Shin

    2018-04-01

    For the early and easy diagnosis of diseases, we have proposed a silicon photonic biosensor chip with two kinds of MEMS microvalves for a multiple-item detection system. The driving voltage of the vertical type with the circular-plate capacitor structure and that of the lateral type with the comb-shaped electrode are investigated. From mechanical calculations, the driving voltage of the vertical type is estimated to be 30 V and that of the lateral type to be 15 V. The propagation loss at the intersecting waveguides of arrayed ring-resonator biosensors is also estimated. In the case of optimized intersecting waveguides, more than 67% transmittance of TE-mode light is simulated for the series connection of 20 intersecting waveguides. It is confirmed that it is possible to fabricate an 8 × 12 arrayed biosensor chip in an area of 1 × 1.5 mm2 taking the device size of the microvalves into consideration. We have, for the first time, designed a whole system, including sensors and a fluid channel with MEMS microvalves.

  16. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  17. Design and Performance of the CMS Pixel Detector Readout Chip

    CERN Document Server

    Kästli, H C; Erdmann, W; Hörmann, C; Horisberger, R P; Kotlinski, D; Meier, B; Hoermann, Ch.

    2006-01-01

    The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

  18. Structural Design Principle of Small-Molecule Organic Semiconductors for Metal-Free, Visible-Light-Promoted Photocatalysis.

    Science.gov (United States)

    Wang, Lei; Huang, Wei; Li, Run; Gehrig, Dominik; Blom, Paul W M; Landfester, Katharina; Zhang, Kai A I

    2016-08-08

    Herein, we report on the structural design principle of small-molecule organic semiconductors as metal-free, pure organic and visible light-active photocatalysts. Two series of electron-donor and acceptor-type organic semiconductor molecules were synthesized to meet crucial requirements, such as 1) absorption range in the visible region, 2) sufficient photoredox potential, and 3) long lifetime of photogenerated excitons. The photocatalytic activity was demonstrated in the intermolecular C-H functionalization of electron-rich heteroaromates with malonate derivatives. A mechanistic study of the light-induced electron transport between the organic photocatalyst, substrate, and the sacrificial agent are described. With their tunable absorption range and defined energy-band structure, the small-molecule organic semiconductors could offer a new class of metal-free and visible light-active photocatalysts for chemical reactions. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Integrated Materials Design of Organic Semiconductors for Field-Effect Transistors

    KAUST Repository

    Mei, Jianguo

    2013-05-08

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm2/(V s). In this perspective, we highlight some of the major milestones along the way to provide a historical view of OFET development, introduce the integrated molecular design concepts and process engineering approaches that lead to the current success, and identify the challenges ahead to make OFETs applicable in real applications. © 2013 American Chemical Society.

  20. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally...

  1. Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

    Science.gov (United States)

    Wysocki, Gerard (Inventor); Tittel, Frank K. (Inventor); Curl, Robert F. (Inventor)

    2010-01-01

    A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

  2. Microeconomics of process control in semiconductor manufacturing

    Science.gov (United States)

    Monahan, Kevin M.

    2003-06-01

    Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

  3. On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

    Science.gov (United States)

    Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

    2017-08-30

    Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

  4. A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2018-01-01

    Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

  5. Design of automatic curtain controlled by wireless based on single chip 51 microcomputer

    Science.gov (United States)

    Han, Dafeng; Chen, Xiaoning

    2017-08-01

    In order to realize the wireless control of the domestic intelligent curtains, a set of wireless intelligent curtain control system based on 51 single chip microcomputer have been designed in this paper. The intelligent curtain can work in the manual mode, automatic mode and sleep mode and can be carried out by the button and mobile phone APP mode loop switch. Through the photosensitive resistance module and human pyroelectric infrared sensor to collect the indoor light value and the data whether there is the person in the room, and then after single chip processing, the motor drive module is controlled to realize the positive inversion of the asynchronous motor, the intelligent opening and closing of the curtain have been realized. The operation of the motor can be stopped under the action of the switch and the curtain opening and closing and timing switch can be controlled through the keys and mobile phone APP. The optical fiber intensity, working mode, curtain state and system time are displayed by LCD1602. The system has a high reliability and security under practical testing and with the popularity and development of smart home, the design has broad market prospects.

  6. Epitaxy of semiconductor-superconductor nanowires

    DEFF Research Database (Denmark)

    Krogstrup, P.; Ziino, N.L.B.; Chang, W.

    2015-01-01

    Controlling the properties of semiconductor/metal interfaces is a powerful method for designing functionality and improving the performance of electrical devices. Recently semiconductor/superconductor hybrids have appeared as an important example where the atomic scale uniformity of the interface...

  7. Design and exploration of semiconductors from first principles: A review of recent advances

    Science.gov (United States)

    Oba, Fumiyasu; Kumagai, Yu

    2018-06-01

    Recent first-principles approaches to semiconductors are reviewed, with an emphasis on theoretical insight into emerging materials and in silico exploration of as-yet-unreported materials. As relevant theory and methodologies have developed, along with computer performance, it is now feasible to predict a variety of material properties ab initio at the practical level of accuracy required for detailed understanding and elaborate design of semiconductors; these material properties include (i) fundamental bulk properties such as band gaps, effective masses, dielectric constants, and optical absorption coefficients; (ii) the properties of point defects, including native defects, residual impurities, and dopants, such as donor, acceptor, and deep-trap levels, and formation energies, which determine the carrier type and density; and (iii) absolute and relative band positions, including ionization potentials and electron affinities at semiconductor surfaces, band offsets at heterointerfaces between dissimilar semiconductors, and Schottky barrier heights at metal–semiconductor interfaces, which are often discussed systematically using band alignment or lineup diagrams. These predictions from first principles have made it possible to elucidate the characteristics of semiconductors used in industry, including group III–V compounds such as GaN, GaP, and GaAs and their alloys with related Al and In compounds; amorphous oxides, represented by In–Ga–Zn–O transparent conductive oxides (TCOs), represented by In2O3, SnO2, and ZnO; and photovoltaic absorber and buffer layer materials such as CdTe and CdS among group II–VI compounds and chalcopyrite CuInSe2, CuGaSe2, and CuIn1‑ x Ga x Se2 (CIGS) alloys, in addition to the prototypical elemental semiconductors Si and Ge. Semiconductors attracting renewed or emerging interest have also been investigated, for instance, divalent tin compounds, including SnO and SnS; wurtzite-derived ternary compounds such as ZnSnN2 and Cu

  8. Metal-semiconductor, composite radiation detectors

    International Nuclear Information System (INIS)

    Orvis, W.J.; Yee, J.H.; Fuess, D.A.

    1991-12-01

    In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high- efficiency gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, we have modeled parts of the detector and have nearly completed a prototype device. 2 refs

  9. Purcell effect in an organic-inorganic halide perovskite semiconductor microcavity system

    International Nuclear Information System (INIS)

    Wang, Jun; Wang, Yafeng; Hu, Tao; Wu, Lin; Shen, Xuechu; Chen, Zhanghai; Cao, Runan; Xu, Fei; Da, Peimei; Zheng, Gengfeng; Lu, Jian

    2016-01-01

    Organic-inorganic halide perovskite semiconductors with the attractive physics properties, including strong photoluminescence (PL), huge oscillator strengths, and low nonradiative recombination losses, are ideal candidates for studying the light-matter interaction in nanostructures. Here, we demonstrate the coupling of the exciton state and the cavity mode in the lead halide perovskite microcavity system at room temperature. The Purcell effect in the coupling system is clearly observed by using angle-resolved photoluminescence spectra. Kinetic analysis based on time-resolved PL reveals that the spontaneous emission rate of the halide perovskite semiconductor is significantly enhanced at resonance of the exciton energy and the cavity mode. Our results provide the way for developing electrically driven organic polariton lasers, optical devices, and on-chip coherent quantum light sources

  10. High-resolution X-ray imaging - a powerful nondestructive technique for applications in semiconductor industry

    International Nuclear Information System (INIS)

    Zschech, Ehrenfried; Yun, Wenbing; Schneider, Gerd

    2008-01-01

    The availability of high-brilliance X-ray sources, high-precision X-ray focusing optics and very efficient CCD area detectors has contributed essentially to the development of transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) with sub-50 nm resolution. Particularly, the fabrication of high aspect ratio Fresnel zone plates with zone widths approaching 15 nm has contributed to the enormous improvement in spatial resolution during the previous years. Currently, Fresnel zone plates give the ability to reach spatial resolutions of 15 to 20 nm in the soft and of about 30 to 50 nm in the hard X-ray energy range. X-ray microscopes with rotating anode X-ray sources that can be installed in an analytical lab next to a semiconductor fab have been developed recently. These unique TXM/XCT systems provide an important new capability of nondestructive 3D imaging of internal circuit structures without destructive sample preparation such as cross sectioning. These lab systems can be used for failure localization in micro- and nanoelectronic structures and devices, e.g., to visualize voids and residuals in on-chip metal interconnects without physical modification of the chip. Synchrotron radiation experiments have been used to study new processes and materials that have to be introduced into the semiconductor industry. The potential of TXM using synchrotron radiation in the soft X-ray energy range is shown for the nondestructive in situ imaging of void evolution in embedded on-chip copper interconnect structures during electromigration and for the imaging of different types of insulating thin films between the on-chip interconnects (spectromicroscopy). (orig.)

  11. n-Channel semiconductor materials design for organic complementary circuits.

    Science.gov (United States)

    Usta, Hakan; Facchetti, Antonio; Marks, Tobin J

    2011-07-19

    Organic semiconductors have unique properties compared to traditional inorganic materials such as amorphous or crystalline silicon. Some important advantages include their adaptability to low-temperature processing on flexible substrates, low cost, amenability to high-speed fabrication, and tunable electronic properties. These features are essential for a variety of next-generation electronic products, including low-power flexible displays, inexpensive radio frequency identification (RFID) tags, and printable sensors, among many other applications. Accordingly, the preparation of new materials based on π-conjugated organic molecules or polymers has been a central scientific and technological research focus over the past decade. Currently, p-channel (hole-transporting) materials are the leading class of organic semiconductors. In contrast, high-performance n-channel (electron-transporting) semiconductors are relatively rare, but they are of great significance for the development of plastic electronic devices such as organic field-effect transistors (OFETs). In this Account, we highlight the advances our team has made toward realizing moderately and highly electron-deficient n-channel oligomers and polymers based on oligothiophene, arylenediimide, and (bis)indenofluorene skeletons. We have synthesized and characterized a "library" of structurally related semiconductors, and we have investigated detailed structure-property relationships through optical, electrochemical, thermal, microstructural (both single-crystal and thin-film), and electrical measurements. Our results reveal highly informative correlations between structural parameters at various length scales and charge transport properties. We first discuss oligothiophenes functionalized with perfluoroalkyl and perfluoroarene substituents, which represent the initial examples of high-performance n-channel semiconductors developed in this project. The OFET characteristics of these compounds are presented with an

  12. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Energy Technology Data Exchange (ETDEWEB)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua, E-mail: gaoleisheng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-08-15

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 {mu}m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 {mu}m{sup 2}. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  13. Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

    Science.gov (United States)

    Biyikli, Necmi; Haider, Ali

    2017-09-01

    In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

  14. High-performance green semiconductor devices: materials, designs, and fabrication

    Science.gov (United States)

    Jung, Yei Hwan; Zhang, Huilong; Gong, Shaoqin; Ma, Zhenqiang

    2017-06-01

    From large industrial computers to non-portable home appliances and finally to light-weight portable gadgets, the rapid evolution of electronics has facilitated our daily pursuits and increased our life comforts. However, these rapid advances have led to a significant decrease in the lifetime of consumer electronics. The serious environmental threat that comes from electronic waste not only involves materials like plastics and heavy metals, but also includes toxic materials like mercury, cadmium, arsenic, and lead, which can leak into the ground and contaminate the water we drink, the food we eat, and the animals that live around us. Furthermore, most electronics are comprised of non-renewable, non-biodegradable, and potentially toxic materials. Difficulties in recycling the increasing amount of electronic waste could eventually lead to permanent environmental pollution. As such, discarded electronics that can naturally degrade over time would reduce recycling challenges and minimize their threat to the environment. This review provides a snapshot of the current developments and challenges of green electronics at the semiconductor device level. It looks at the developments that have been made in an effort to help reduce the accumulation of electronic waste by utilizing unconventional, biodegradable materials as components. While many semiconductors are classified as non-biodegradable, a few biodegradable semiconducting materials exist and are used as electrical components. This review begins with a discussion of biodegradable materials for electronics, followed by designs and processes for the manufacturing of green electronics using different techniques and designs. In the later sections of the review, various examples of biodegradable electrical components, such as sensors, circuits, and batteries, that together can form a functional electronic device, are discussed and new applications using green electronics are reviewed.

  15. FISH & CHIPS: Four Electrode Conductivity / Salinity Sensor on a Silicon Multi-sensor chip for Fisheries Research

    DEFF Research Database (Denmark)

    Hyldgård, Anders; Olafsdottir, Iris; Olesen, M.

    2005-01-01

    The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given......The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given...

  16. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  17. Physics of semiconductor lasers

    CERN Document Server

    Mroziewicz, B; Nakwaski, W

    2013-01-01

    Written for readers who have some background in solid state physics but do not necessarily possess any knowledge of semiconductor lasers, this book provides a comprehensive and concise account of fundamental semiconductor laser physics, technology and properties. The principles of operation of these lasers are therefore discussed in detail with the interrelations between their design and optical, electrical and thermal properties. The relative merits of a large number of laser structures and their parameters are described to acquaint the reader with the various aspects of the semiconductor l

  18. The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

    International Nuclear Information System (INIS)

    Marconi, S; Christiansen, J; Conti, E; Placidi, P; Hemperek, T

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared

  19. Roadmap on semiconductor-cell biointerfaces

    Science.gov (United States)

    Tian, Bozhi; Xu, Shuai; Rogers, John A.; Cestellos-Blanco, Stefano; Yang, Peidong; Carvalho-de-Souza, João L.; Bezanilla, Francisco; Liu, Jia; Bao, Zhenan; Hjort, Martin; Cao, Yuhong; Melosh, Nicholas; Lanzani, Guglielmo; Benfenati, Fabio; Galli, Giulia; Gygi, Francois; Kautz, Rylan; Gorodetsky, Alon A.; Kim, Samuel S.; Lu, Timothy K.; Anikeeva, Polina; Cifra, Michal; Krivosudský, Ondrej; Havelka, Daniel; Jiang, Yuanwen

    2018-05-01

    This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world.

  20. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing

    2011-01-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm 2 area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  1. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 {mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing, E-mail: wubin@ime.ac.cn [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2011-05-15

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 {mu}m 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm{sup 2} area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  2. Design and characterization of a 52K SNP chip for goats.

    Directory of Open Access Journals (Sweden)

    Gwenola Tosser-Klopp

    Full Text Available The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50-60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed: Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes, sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years.

  3. Overcoming Limitations in Semiconductor Alloy Design

    Science.gov (United States)

    Christian, Theresa Marie

    Inorganic semiconductors provide an astonishingly versatile, robust, and efficient platform for optoelectronic energy conversion devices. However, conventional alloys and growth regimes face materials challenges that restrict the full potential of these devices. Novel alloy designs based on isoelectronic co-doping, metamorphic growth and controllable atomic ordering offer new pathways to practical and ultra-high-efficiency optoelectronic devices including solar cells and light-emitting diodes. Abnormal isoelectronic alloys of GaP1-xBix, GaP 1-x-yBixNy, and GaAs1-xBix with unprecedented bismuth incorporation fractions and crystalline quality are explored in this thesis research. Comparative studies of several GaP1-xBix and GaP1-x-yBixNy alloys demonstrate that the site-specific incorporation of bismuth during epitaxial growth is sensitive to growth temperature and has dramatic effects on carrier transfer processes in these alloys. Additionally, distinctive bismuth-related localized states are spectrally identified for the first time in samples of GaAs1-xBix grown by laser-assisted epitaxial growth. These results address fundamental questions about the nature of bismuth-bismuth inter-impurity interactions. Finally, a metamorphic growth strategy for a novel light-emitting diode (LED) design is also discussed. This work utilized direct-bandgap AlxIn1-xP active layers with atomic ordering-based electron confinement to improve emission in the yellow and green spectral regions, where incumbent technologies are least effective, and demonstrated the feasibility of non-lattice-matched LED active materials for visible light emission.

  4. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong

    2015-08-23

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  5. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong; Alouini, Mohamed-Slim

    2015-01-01

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  6. Review on the dynamics of semiconductor nanowire lasers

    Science.gov (United States)

    Röder, Robert; Ronning, Carsten

    2018-03-01

    Semiconductor optoelectronic devices have contributed tremendously to the technological progress in the past 50-60 years. Today, they also play a key role in nanophotonics stimulated by the inherent limitations of electronic integrated circuits and the growing demand for faster communications on chip. In particular, the field of ‘nanowire photonics’ has emerged including the search for coherent light sources with a nano-scaled footprint. The past decade has been dedicated to find suitable semiconductor nanowire (NW) materials for such nanolasers. Nowadays, such NW lasers consistently work at room temperature covering a huge spectral range from the ultraviolet down to the mid-infrared depending on the band gap of the NW material. Furthermore, first approaches towards the modification and optimization of such NW laser devices have been demonstrated. The underlying dynamics of the electronic and photonic NW systems have also been studied very recently, as they need to be understood in order to push the technological relevance of nano-scaled coherent light sources. Therefore, this review will first present novel measurement approaches in order to study the ultrafast temporal and optical mode dynamics of individual NW laser devices. Furthermore, these fundamental new insights are reviewed and deeply discussed towards the efficient control and adjustment of the dynamics in semiconductor NW lasers.

  7. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    Energy Technology Data Exchange (ETDEWEB)

    Ma Haifeng; Zhou Feng, E-mail: fengzhou@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-01-15

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 {mu}m CMOS technology and occupies an active area as small as 220 x 320 {mu}m{sup 2}, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 {mu}A quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  8. Semiconductor Laser Diode Pumps for Inertial Fusion Energy Lasers

    International Nuclear Information System (INIS)

    Deri, R.J.

    2011-01-01

    increased reliability. The high-level requirements on the semiconductor lasers involve reliability, price points on a price-per-Watt basis, and a set of technical requirements. The technical requirements for the amplifier design in reference 1 are discussed in detail and are summarized in Table 1. These values are still subject to changes as the overall laser system continues to be optimized. Since pump costs can be a significant fraction of the overall laser system cost, it is important to achieve sufficiently low price points for these components. At this time, the price target for tenth-of-akind IFE plant is $0.007/Watt for packaged devices. At this target level, the pumps account for approximately one third of the laser cost. The pump lasers should last for the life of the power plant, leading to a target component lifetime requirement of roughly 14 Ghosts, corresponding to a 30 year plant life and 15 Hz repetition rate. An attractive path forward involes pump operation at high output power levels, on a Watts-per-bar (Watts/chip) basis. This reduces the cost of pump power (price-per-Watt), since to first order the unit price does not increase with power/bar. The industry has seen a continual improvement in power output, with current 1 cm-wide bars emitting up to 500 W QCW (quasi-continuous wave). Increased power/bar also facilitates achieving high irradiance in the array plane. On the other hand, increased power implies greater heat loads and (possibly) higher current drive, which will require increased attention to thermal management and parasitic series resistance. Diode chips containing multiple p-n junctions and quantum wells (also called nanostack structures) may provide an additional approach to reduce the peak current.

  9. 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2014-04-01

    A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

  10. 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.; Arsalan, Muhammad; Cheema, Hammad; Salama, Khaled N.; Shamim, Atif

    2014-01-01

    A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

  11. Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

    Science.gov (United States)

    King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

    1998-04-01

    We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

  12. Electronic structure of semiconductor interfaces

    Energy Technology Data Exchange (ETDEWEB)

    Herman, F

    1983-02-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered.

  13. Electronic structure of semiconductor interfaces

    International Nuclear Information System (INIS)

    Herman, F.

    1983-01-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered. (Author) [pt

  14. A system-level multiprocessor system-on-chip modeling framework

    DEFF Research Database (Denmark)

    Virk, Kashif Munir; Madsen, Jan

    2004-01-01

    We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and...... SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework....

  15. Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

    2018-05-01

    Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

  16. Semiconductor laser diodes and the design of a D.C. powered laser diode drive unit

    OpenAIRE

    Cappuccio, Joseph C., Jr.

    1988-01-01

    Approved for public release; distribution is unlimited This thesis addresses the design, development and operational analysis of a D.C. powered semiconductor laser diode drive unit. A laser diode requires an extremely stable power supply since a picosecond spike of current or power supply switching transient could result in permanent damage. The design offers stability and various features for operational protection of the laser diode. The ability to intensity modulate (analog) and pulse m...

  17. Semiconductor

    International Nuclear Information System (INIS)

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  18. Introduction to Semiconductor Devices

    Science.gov (United States)

    Brennan, Kevin F.

    2005-03-01

    This volume offers a solid foundation for understanding the most important devices used in the hottest areas of electronic engineering today, from semiconductor fundamentals to state-of-the-art semiconductor devices in the telecommunications and computing industries. Kevin Brennan describes future approaches to computing hardware and RF power amplifiers, and explains how emerging trends and system demands of computing and telecommunications systems influence the choice, design and operation of semiconductor devices. In addition, he covers MODFETs and MOSFETs, short channel effects, and the challenges faced by continuing miniaturization. His book is both an excellent senior/graduate text and a valuable reference for practicing engineers and researchers.

  19. Development of semiconductor electronics

    International Nuclear Information System (INIS)

    Bardeen, John.

    1977-01-01

    In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

  20. The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

    Science.gov (United States)

    Choi, Edward

    Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the

  1. Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

    Science.gov (United States)

    Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

    2008-01-01

    A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

  2. Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

    Science.gov (United States)

    Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

    2016-01-01

    Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

  3. Prototype detection unit for the CHIPS experiment

    Science.gov (United States)

    Pfützner, Maciej M.

    2017-09-01

    CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

  4. Metal-semiconductor, composite radiation detectors

    International Nuclear Information System (INIS)

    Orvis, W.J.; Yee, J.H.; Fuess, D.

    1992-12-01

    In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with the good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high-efficiency, room temperature gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, the authors have procured and tested a commercial device with operating characteristics similar to those of a single layer of the composite device. They have modeled the radiation transport in a multi-layered device, to verify the initial calculations of layer thickness and composition. They have modeled the electrostatic field in different device designs to locate and remove high-field regions that can cause device breakdown. They have fabricated 14 single layer prototypes

  5. Pavement system with rubber tire chips in subgrade

    Energy Technology Data Exchange (ETDEWEB)

    Ashtakala, B.; Hoque, A.K.M.M. [Concordia Univ., Montreal, PQ (Canada). Dept. of Civil Engineering

    1995-12-31

    A pavement design method was developed in which shredded rubber tire chips mixed with sand were used as a material for pavement subgrade. Rubber tire chips are highly compressible and produce both elastic and plastic deformations under the application of loads. Sand was added to fill the void between the tire chips and make the mixture a strong material. The design method considered the vertical compressive strain produced by the design life traffic load 18k (80 KN) repetitions. The equivalent thicknesses of the layers above the subgrade corresponding to this vertical compressive strain were determined using contour charts. From this equivalent thickness, the thicknesses for asphalt pavement, base, and sub-base were determined by Odemark`s method. 3 refs., 1 tab., 3 figs.

  6. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  7. Thiophene-Based Organic Semiconductors.

    Science.gov (United States)

    Turkoglu, Gulsen; Cinar, M Emin; Ozturk, Turan

    2017-10-24

    Thiophene-based π-conjugated organic small molecules and polymers are the research subject of significant current interest owing to their potential use as organic semiconductors in material chemistry. Despite simple and similar molecular structures, the hitherto reported properties of thiophene-based organic semiconductors are rather diverse. Design of high performance organic semiconducting materials requires a thorough understanding of inter- and intra-molecular interactions, solid-state packing, and the influence of both factors on the charge carrier transport. In this chapter, thiophene-based organic semiconductors, which are classified in terms of their chemical structures and their structure-property relationships, are addressed for the potential applications as organic photovoltaics (OPVs), organic field-effect transistors (OFETs) and organic light emitting diodes (OLEDs).

  8. Optically pumped semiconductor lasers for atomic and molecular physics

    Science.gov (United States)

    Burd, S.; Leibfried, D.; Wilson, A. C.; Wineland, D. J.

    2015-03-01

    Experiments in atomic, molecular and optical (AMO) physics rely on lasers at many different wavelengths and with varying requirements on spectral linewidth, power and intensity stability. Optically pumped semiconductor lasers (OPSLs), when combined with nonlinear frequency conversion, can potentially replace many of the laser systems currently in use. We are developing a source for laser cooling and spectroscopy of Mg+ ions at 280 nm, based on a frequency quadrupled OPSL with the gain chip fabricated at the ORC at Tampere Univ. of Technology, Finland. This OPSL system could serve as a prototype for many other sources used in atomic and molecular physics.

  9. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  10. Opening of K+ channels by capacitive stimulation from silicon chip

    Science.gov (United States)

    Ulbrich, M. H.; Fromherz, P.

    2005-10-01

    The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

  11. Design of nanophotonic, hot-electron solar-blind ultraviolet detectors with a metal-oxide-semiconductor structure

    International Nuclear Information System (INIS)

    Wang, Zhiyuan; Wang, Xiaoxin; Liu, Jifeng

    2014-01-01

    Solar-blind ultraviolet (UV) detection refers to photon detection specifically in the wavelength range of 200 nm–320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. The most commonly used solid state devices for this application are wide band gap (WBG) semiconductor photodetectors (Eg > 3.5 eV). However, WBG semiconductors are difficult to grow and integrate with Si readout integrated circuits (ROICs). In this paper, we design a nanophotonic metal-oxide-semiconductor structure on Si for solar-blind UV detectors. Instead of using semiconductors as the active absorber, we use Sn nano-grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between the metal and the n-type Si region upon UV excitation. Moreover, the transported hot electron has an excess kinetic energy >3 eV, large enough to induce impact ionization and generate another free electron in the conduction band of n-Si. This process doubles the quantum efficiency. On the other hand, the large metal/oxide interfacial energy barrier (>3.5 eV) also enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, ∼75% UV absorption and hot electron excitation can be achieved within the mean free path of ∼20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. The simple geometry of the Sn nano-gratings and the MOS structure make it easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices. (paper)

  12. Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

    Science.gov (United States)

    Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

    2018-03-01

    This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

  13. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  14. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  15. Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC)

    International Nuclear Information System (INIS)

    Celik, Cihangir; Unlue, Kenan; Narayanan, Vijaykrishnan; Irwin, Mary J.

    2011-01-01

    Soft errors are transient errors caused due to excess charge carriers induced primarily by external radiations in the semiconductor devices. Soft error phenomena could be used to detect thermal neutrons with a neutron monitoring/detection system by enhancing soft error occurrences in the memory devices. This way, one can convert all semiconductor memory devices into neutron detection systems. Such a device is being developed at The Pennsylvania State University and named Neutron Intercepting Silicon Chip (NISC). The NISC is envisioning a miniature, power efficient, and active/passive operation neutron sensor/detector system. NISC aims to achieve this goal by introducing 10 B-enriched Borophosphosilicate Glass (BPSG) insulation layers in the semiconductor memories. In order to model and analyze the NISC, an analysis tool using Geant4 as the transport and tracking engine is developed for the simulation of the charged particle interactions in the semiconductor memory model, named NISC Soft Error Analysis Tool (NISCSAT). A simple model with 10 B-enriched layer on top of the lumped silicon region is developed in order to represent the semiconductor memory node. Soft error probability calculations were performed via the NISCSAT with both single node and array configurations to investigate device scaling by using different node dimensions in the model. Mono-energetic, mono-directional thermal and fast neutrons are used as the neutron sources. Soft error contribution due to the BPSG layer is also investigated with different 10 B contents and the results are presented in this paper.

  16. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  17. Ag-based semiconductor photocatalysts in environmental purification

    Energy Technology Data Exchange (ETDEWEB)

    Li, Jiade; Fang, Wen [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); Yu, Changlin, E-mail: yuchanglinjx@163.com [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); School of Environment Engineering and biology Engineering, Guangdong University of Petrochemical Technology, Maoming, 525000 Guangdong Province (China); Zhou, Wanqin [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); State Key Laboratory of Photocatalysis on Energy and Environment, Fuzhou University, Fuzhou, 350002 (China); Zhu, Lihua [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); Xie, Yu, E-mail: xieyu_121@163.com [College of Environment and Chemical Engineering, Nanchang Hangkong University, Nanchang 330063, Jiangxi (China)

    2015-12-15

    Graphical abstract: Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Formation of heterojunction could largely promote the electron/hole pair separation, resulting in highly photocatalytic activity and stability. - Highlights: • Recent research progress in the fabrication and application of Ag-based semiconductor photocatalyts. • The advantages and disadvantages of Ag-based semiconductor as photocatalysts. • Strategies in design Ag-based semiconductor photocatalysts with high performance. - Abstract: Over the past decades, with the fast development of global industrial development, various organic pollutants discharged in water have become a major source of environmental pollution in waste fields. Photocatalysis, as green and environmentally friendly technology, has attracted much attention in pollutants degradation due to its efficient degradation rate. However, the practical application of traditional semiconductor photocatalysts, e.g. TiO{sub 2}, ZnO, is limited by their weak visible light adsorption due to their wide band gaps. Nowadays, the study in photocatalysts focuses on new and narrow band gap semiconductors. Among them, Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Most of Ag-based semiconductors could exhibit high initial photocatalytic activity. But they easy suffer from poor stability because of photochemical corrosion. Design heterojunction, increasing specific surface area, enriching pore structure, regulating morphology, controlling crystal facets, and producing plasmonic effects were considered as the effective strategies to improve the photocatalytic performance of Ag-based photocatalyts. Moreover, combining the superior properties of carbon materials (e.g. carbon quantum dots, carbon nano-tube, carbon nanofibers, graphene) with Ag

  18. Ag-based semiconductor photocatalysts in environmental purification

    International Nuclear Information System (INIS)

    Li, Jiade; Fang, Wen; Yu, Changlin; Zhou, Wanqin; Zhu, Lihua; Xie, Yu

    2015-01-01

    Graphical abstract: Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Formation of heterojunction could largely promote the electron/hole pair separation, resulting in highly photocatalytic activity and stability. - Highlights: • Recent research progress in the fabrication and application of Ag-based semiconductor photocatalyts. • The advantages and disadvantages of Ag-based semiconductor as photocatalysts. • Strategies in design Ag-based semiconductor photocatalysts with high performance. - Abstract: Over the past decades, with the fast development of global industrial development, various organic pollutants discharged in water have become a major source of environmental pollution in waste fields. Photocatalysis, as green and environmentally friendly technology, has attracted much attention in pollutants degradation due to its efficient degradation rate. However, the practical application of traditional semiconductor photocatalysts, e.g. TiO 2 , ZnO, is limited by their weak visible light adsorption due to their wide band gaps. Nowadays, the study in photocatalysts focuses on new and narrow band gap semiconductors. Among them, Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Most of Ag-based semiconductors could exhibit high initial photocatalytic activity. But they easy suffer from poor stability because of photochemical corrosion. Design heterojunction, increasing specific surface area, enriching pore structure, regulating morphology, controlling crystal facets, and producing plasmonic effects were considered as the effective strategies to improve the photocatalytic performance of Ag-based photocatalyts. Moreover, combining the superior properties of carbon materials (e.g. carbon quantum dots, carbon nano-tube, carbon nanofibers, graphene) with Ag

  19. A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

    Directory of Open Access Journals (Sweden)

    Tharun Konduru

    2015-01-01

    Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

  20. Design of a passive UHF RFID tag for the ISO18000-6C protocol

    Energy Technology Data Exchange (ETDEWEB)

    Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong, E-mail: wangyao220597@yahoo.com.cn [RFIC Laboratory CICS, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731 (China)

    2011-05-15

    This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under {+-}4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 {mu}W with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 {mu}m CMOS technology and the chip size is 880 x 880 {mu}m{sup 2}. (semiconductor integrated circuits)

  1. Design of a passive UHF RFID tag for the ISO18000-6C protocol

    International Nuclear Information System (INIS)

    Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong

    2011-01-01

    This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under ±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μW with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μm CMOS technology and the chip size is 880 x 880 μm 2 . (semiconductor integrated circuits)

  2. Chip-Level Electromigration Reliability for Cu Interconnects

    International Nuclear Information System (INIS)

    Gall, M.; Oh, C.; Grinshpon, A.; Zolotov, V.; Panda, R.; Demircan, E.; Mueller, J.; Justison, P.; Ramakrishna, K.; Thrasher, S.; Hernandez, R.; Herrick, M.; Fox, R.; Boeck, B.; Kawasaki, H.; Haznedar, H.; Ku, P.

    2004-01-01

    Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The traditional method of verifying EM reliability only through current density limit checks is proving to be inadequate in general, or quite expensive at the best. A Statistical EM Budgeting (SEB) methodology has been proposed to assess more realistic chip-level EM reliability from the complex statistical distribution of currents in a chip. To be valuable, this approach requires accurate estimation of currents for all interconnect segments in a chip. However, no efficient technique to manage the complexity of such a task for very large chip designs is known. We present an efficient method to estimate currents exhaustively for all interconnects in a chip. The proposed method uses pre-characterization of cells and macros, and steps to identify and filter out symmetrically bi-directional interconnects. We illustrate the strength of the proposed approach using a high-performance microprocessor design for embedded applications as a case study

  3. Radiation effects in semiconductors

    CERN Document Server

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  4. Device Physics of Narrow Gap Semiconductors

    CERN Document Server

    Chu, Junhao

    2010-01-01

    Narrow gap semiconductors obey the general rules of semiconductor science, but often exhibit extreme features of these rules because of the same properties that produce their narrow gaps. Consequently these materials provide sensitive tests of theory, and the opportunity for the design of innovative devices. Narrow gap semiconductors are the most important materials for the preparation of advanced modern infrared systems. Device Physics of Narrow Gap Semiconductors offers descriptions of the materials science and device physics of these unique materials. Topics covered include impurities and defects, recombination mechanisms, surface and interface properties, and the properties of low dimensional systems for infrared applications. This book will help readers to understand not only the semiconductor physics and materials science, but also how they relate to advanced opto-electronic devices. The last chapter applies the understanding of device physics to photoconductive detectors, photovoltaic infrared detector...

  5. Manipulating semiconductor colloidal stability through doping.

    Science.gov (United States)

    Fleharty, Mark E; van Swol, Frank; Petsev, Dimiter N

    2014-10-10

    The interface between a doped semiconductor material and electrolyte solution is of considerable fundamental interest, and is relevant to systems of practical importance. Both adjacent domains contain mobile charges, which respond to potential variations. This is exploited to design electronic and optoelectronic sensors, and other enabling semiconductor colloidal materials. We show that the charge mobility in both phases leads to a new type of interaction between semiconductor colloids suspended in aqueous electrolyte solutions. This interaction is due to the electrostatic response of the semiconductor interior to disturbances in the external field upon the approach of two particles. The electrostatic repulsion between two charged colloids is reduced from the one governed by the charged groups present at the particles surfaces. This type of interaction is unique to semiconductor particles and may have a substantial effect on the suspension dynamics and stability.

  6. The GenoChip: a new tool for genetic anthropology.

    Science.gov (United States)

    Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G; Greenspan, Bennett; Spencer Wells, R

    2013-01-01

    The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project's new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic

  7. The GenoChip: A New Tool for Genetic Anthropology

    Science.gov (United States)

    Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G.; Greenspan, Bennett; Spencer Wells, R.

    2013-01-01

    The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project’s new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic

  8. Technology-design-manufacturing co-optimization for advanced mobile SoCs

    Science.gov (United States)

    Yang, Da; Gan, Chock; Chidambaram, P. R.; Nallapadi, Giri; Zhu, John; Song, S. C.; Xu, Jeff; Yeap, Geoffrey

    2014-03-01

    How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

  9. ChIP on SNP-chip for genome-wide analysis of human histone H4 hyperacetylation

    Directory of Open Access Journals (Sweden)

    Porter Christopher J

    2007-09-01

    Full Text Available Abstract Background SNP microarrays are designed to genotype Single Nucleotide Polymorphisms (SNPs. These microarrays report hybridization of DNA fragments and therefore can be used for the purpose of detecting genomic fragments. Results Here, we demonstrate that a SNP microarray can be effectively used in this way to perform chromatin immunoprecipitation (ChIP on chip as an alternative to tiling microarrays. We illustrate this novel application by mapping whole genome histone H4 hyperacetylation in human myoblasts and myotubes. We detect clusters of hyperacetylated histone H4, often spanning across up to 300 kilobases of genomic sequence. Using complementary genome-wide analyses of gene expression by DNA microarray we demonstrate that these clusters of hyperacetylated histone H4 tend to be associated with expressed genes. Conclusion The use of a SNP array for a ChIP-on-chip application (ChIP on SNP-chip will be of great value to laboratories whose interest is the determination of general rules regarding the relationship of specific chromatin modifications to transcriptional status throughout the genome and to examine the asymmetric modification of chromatin at heterozygous loci.

  10. A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

    Science.gov (United States)

    Santoli, S.

    The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

  11. Property-driven functional verification technique for high-speed vision system-on-chip processor

    Science.gov (United States)

    Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

    2017-04-01

    The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

  12. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    (clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic......Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

  13. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  14. Integrated potentiometric detector for use in chip-based flow cells

    Science.gov (United States)

    Tantra; Manz

    2000-07-01

    A new kind of potentiometric chip sensor for ion-selective electrodes (ISE) based on a solvent polymeric membrane is described. The chip sensor is designed to trap the organic cocktail inside the chip and to permit sample solution to flow past the membrane. The design allows the sensor to overcome technical problems of ruggedness and would therefore be ideal for industrial processes. The sensor performance for a Ba2+-ISE membrane based on a Vogtle ionophore showed electrochemical behavior similar to that observed in conventional electrodes and microelectrode arrangements.

  15. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  16. Rational design of organic semiconductors for texture control and self-patterning on halogenated surfaces

    KAUST Repository

    Ward, Jeremy W.

    2014-05-15

    Understanding the interactions at interfaces between the materials constituting consecutive layers within organic thin-film transistors (OTFTs) is vital for optimizing charge injection and transport, tuning thin-film microstructure, and designing new materials. Here, the influence of the interactions at the interface between a halogenated organic semiconductor (OSC) thin film and a halogenated self-assembled monolayer on the formation of the crystalline texture directly affecting the performance of OTFTs is explored. By correlating the results from microbeam grazing incidence wide angle X-ray scattering (μGIWAXS) measurements of structure and texture with OTFT characteristics, two or more interaction paths between the terminating atoms of the semiconductor and the halogenated surface are found to be vital to templating a highly ordered morphology in the first layer. These interactions are effective when the separating distance is lower than 2.5 dw, where dw represents the van der Waals distance. The ability to modulate charge carrier transport by several orders of magnitude by promoting "edge-on" versus "face-on" molecular orientation and crystallographic textures in OSCs is demonstrated. It is found that the "edge-on" self-assembly of molecules forms uniform, (001) lamellar-textured crystallites which promote high charge carrier mobility, and that charge transport suffers as the fraction of the "face-on" oriented crystallites increases. The role of interfacial halogenation in mediating texture formation and the self-patterning of organic semiconductor films, as well as the resulting effects on charge transport in organic thin-film transistors, are explored. The presence of two or more anchoring sites between a halogenated semiconductor and a halogenated self-assembled monolayer, closer than about twice the corresponding van der Waals distance, alter the microstructure and improve electrical properties. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  17. Semiconductor devices for entangled photon pair generation: a review

    Science.gov (United States)

    Orieux, Adeline; Versteegh, Marijn A. M.; Jöns, Klaus D.; Ducci, Sara

    2017-07-01

    Entanglement is one of the most fascinating properties of quantum mechanical systems; when two particles are entangled the measurement of the properties of one of the two allows the properties of the other to be instantaneously known, whatever the distance separating them. In parallel with fundamental research on the foundations of quantum mechanics performed on complex experimental set-ups, we assist today with bourgeoning of quantum information technologies bound to exploit entanglement for a large variety of applications such as secure communications, metrology and computation. Among the different physical systems under investigation, those involving photonic components are likely to play a central role and in this context semiconductor materials exhibit a huge potential in terms of integration of several quantum components in miniature chips. In this article we review the recent progress in the development of semiconductor devices emitting entangled photons. We will present the physical processes allowing the generation of entanglement and the tools to characterize it; we will give an overview of major recent results of the last few years and highlight perspectives for future developments.

  18. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...

  19. Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

    International Nuclear Information System (INIS)

    Mishra, Vijay; Kataria, S.K.

    2005-01-01

    A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

  20. Lab-on a-Chip

    Science.gov (United States)

    1999-01-01

    Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

  1. Modeling, analysis and optimization of network-on-chip communication architectures

    CERN Document Server

    Ogras, Umit Y

    2013-01-01

    Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

  2. Semiconductor X-ray spectrometers

    International Nuclear Information System (INIS)

    Muggleton, A.H.F.

    1978-02-01

    An outline is given of recent developments in particle and photon induced x-ray fluorescence (XRF) analysis. Following a brief description of the basic mechanism of semiconductor detector operation a comparison is made between semiconductor detectors, scintillators and gas filled proportional devices. Detector fabrication and cryostat design are described in more detail and the effects of various device parameters on system performance, such as energy resolution, count rate capability, efficiency, microphony, etc. are discussed. The main applications of these detectors in x-ray fluorescence analysis, electron microprobe analysis, medical and pollution studies are reviewed

  3. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  4. Solving wood chip transport problems with computer simulation.

    Science.gov (United States)

    Dennis P. Bradley; Sharon A. Winsauer

    1976-01-01

    Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

  5. Offshoring in the Semiconductor Industry: Historical Perspectives

    OpenAIRE

    Brown, Clair; Linden, Greg

    2005-01-01

    Semiconductor design is a frequently-cited example of the new wave of offshoring and foreign-outsourcing of service sector jobs. It is certainly a concern to U.S. design engineers themselves. In addition to the current wave of white-collar outsourcing, the industry also has a rich experience with offshoring of manufacturing activity. Semiconductor companies were among the first to invest in offshore facilities to manufacture goods for imports back to the U.S. A brief review of these earlie...

  6. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  7. Dynamic On-Chip micro Temperature and Flow Sensor for miniaturized lab-on-a-chip instruments

    Data.gov (United States)

    National Aeronautics and Space Administration — The purpose of this project is to design, fabricate, and characterize a Dynamic On-Chip Flow and Temperature Sensor (DOCFlaTS) to mature and enable miniaturized...

  8. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    International Nuclear Information System (INIS)

    Trimpl, M.

    2005-12-01

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  9. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  10. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  11. Yarr: A PCIe based readout system for semiconductor tracking systems

    Energy Technology Data Exchange (ETDEWEB)

    Heim, Timon [Bergische Universitaet Wuppertal, Wuppertal (Germany); CERN, Geneva (Switzerland); Maettig, Peter [Bergische Universitaet Wuppertal, Wuppertal (Germany); Pernegger, Heinz [CERN, Geneva (Switzerland)

    2015-07-01

    The Yarr readout system is a novel DAQ concept, using an FPGA board connected via PCIe to a computer, to read out semiconductor tracking systems. The system uses the FPGA as a reconfigurable IO interface which, in conjunction with the very high speed of the PCIe bus, enables a focus of processing the data stream coming from the pixel detector in software. Modern computer system could potentially make the need of custom signal processing hardware in readout systems obsolete and the Yarr readout system showcases this for FE-I4 chips, which are state-of-the-art readout chips used in the ATLAS Pixel Insertable B-Layer and developed for tracking in high multiplicity environments. The underlying concept of the Yarr readout system tries to move intelligence from hardware into the software without the loss of performance, which is made possible by modern multi-core processors. The FPGA board firmware acts like a buffer and does no further processing of the data stream, enabling rapid integration of new hardware due to minimal firmware minimisation.

  12. Chemical engineering in the electronics industry: progress towards the rational design of organic semiconductor heterojunctions

    KAUST Repository

    Clancy, Paulette

    2012-05-01

    We review the current status of heterojunction design for combinations of organic semiconductor materials, given its central role in affecting the device performance for electronic devices and solar cell applications. We provide an emphasis on recent progress towards the rational design of heterojunctions that may lead to higher performance of charge separation and mobility. We also play particular attention to the role played by computational approaches and its potential to help define the best choice of materials for solar cell development in the future. We report the current status of the field with respect to such goals. © 2012 Elsevier Ltd.

  13. Chemical engineering in the electronics industry: progress towards the rational design of organic semiconductor heterojunctions

    KAUST Repository

    Clancy, Paulette

    2012-01-01

    We review the current status of heterojunction design for combinations of organic semiconductor materials, given its central role in affecting the device performance for electronic devices and solar cell applications. We provide an emphasis on recent progress towards the rational design of heterojunctions that may lead to higher performance of charge separation and mobility. We also play particular attention to the role played by computational approaches and its potential to help define the best choice of materials for solar cell development in the future. We report the current status of the field with respect to such goals. © 2012 Elsevier Ltd.

  14. Building blocks for a polarimeter-on-a-chip

    International Nuclear Information System (INIS)

    Stevenson, Thomas R.; Hsieh, W.-T.; Schneider, Gideon; Travers, Douglas; Cao, Nga; Wollack, Edward; Limon, Michele; Kogut, Alan

    2006-01-01

    For the 'Primordial Anisotropy Polarization Pathfinder Array (PAPPA)' balloon flight project, we have designed and made thin-film niobium microstrip circuits as building blocks for a 'polarimeter-on-a-chip' in which superconducting transmission lines are used to couple millimeter wave signals from planar antennas to superconducting transition edge sensor (TES) detectors. Our goal is to demonstrate technology for precision measurements of the polarization of the cosmic microwave background. To enable characterization and verification of our microstrip components, we have incorporated waveguide probes on each chip that can bring millimeter wave signals from a room temperature vector network analyzer to the superconducting circuits on the chip and back again for S-parameter measurements. We have designed a planar antenna and RF choke on the probes to efficiently couple radiation between waveguide and thin-film microstrip. To support the probe antennas in waveguides, we sculpted thin silicon cantilevers that extend from an edge of each silicon chip into a pair of waveguides within a specially designed split-block mount. This technique will allow us to make calibrated measurements at low temperatures of the velocity, impedance, and loss properties of our niobium transmission lines, the frequency response of microstrip filters, hybrid couplers, or terminations, and the performance of integrated detectors

  15. Total Ionizing Dose Testing of the ABC130 ASIC for the ATLAS Phase-II Semiconductor Tracker Upgrade

    CERN Document Server

    Morningstar, Alan

    2015-01-01

    The Large Hadron Collider's (LHC) current inner detector was not built to withstand the radiation damage from the 3000 $\\text{fb}^{-1}$ of integrated luminosity that is planned for the high luminosity LHC (HL-LHC). Therefore, the ATLAS inner detector (ID) must be completely upgraded. As a part of this upgrade, the semiconductor tracker (SCT) and transition radiation tracker (TRT) will be replaced with new silicon microstrip sensors {[}1{]}. These silicon strips will be read out by the ABC130 chip and thus the ABC130 must be able to withstand an expected 30 Mrad of radiation over 10 years. The ABC130 chip was irradiated with 70 Mrad of x-ray radiation over the course of 2 days and the results are discussed in this report.

  16. Implantable Biomedical Signal Monitoring Using RF Energy Harvestingand On-Chip Antenna

    Directory of Open Access Journals (Sweden)

    Jiann-Shiun Yuan

    2015-08-01

    Full Text Available This paper presents the design of an energy harvesting wireless and battery-less silicon-on-chip (SoC device that can be implanted in the human body to monitor certain health conditions. The proposed architecture has been designed on TSMC 0.18μm CMOS ICs and is an integrated system with a rectenna (antenna and rectifier and transmitting circuit, all on a single chip powered by an external transmitter and that is small enough to be inserted in the human eye, heart or brain. The transmitting and receiving antennas operate in the 5.8- GHz ISM band and have a -10dB gain. The distinguishing feature of this design is the rectenna that comprises of a singlestage diode connected NMOS rectifier and a 3-D on-chip antenna that occupies only 2.5 × 1 × 2.8 mm3 of chip area and has the ability to communicate within proximity of 5 cm while giving 10% efficiency. The external source is a reader that powers up the RF rectifier in the implantable chip triggering it to start sending data back to the reader enabling an efficient method of health evaluation for the patient.

  17. The single chip microcomputer technique in an intelligent nuclear instrument

    International Nuclear Information System (INIS)

    Wang Tieliu; Sun Punan; Wang Ying

    1995-01-01

    The authors present that how to acquire and process the output signals from the nuclear detector adopting single chip microcomputer technique, including working principles and the designing method of the computer's software and hardware in the single chip microcomputer instrument

  18. Semiconductor apparatus and method of fabrication for a semiconductor apparatus

    NARCIS (Netherlands)

    2010-01-01

    The invention relates to a semiconductor apparatus (1) and a method of fabrication for a semiconductor apparatus (1), wherein the semiconductor apparatus (1) comprises a semiconductor layer (2) and a passivation layer (3), arranged on a surface of the semiconductor layer (2), for passivating the

  19. Molecular semiconductors photoelectrical properties and solar cells

    CERN Document Server

    Rees, Ch

    1985-01-01

    During the past thirty years considerable efforts have been made to design the synthesis and the study of molecular semiconductors. Molecular semiconductors - and more generally molecular materials - involve interactions between individual subunits which can be separately synthesized. Organic and metallo-organic derivatives are the basis of most of the molecular materials. A survey of the literature on molecular semiconductors leaves one rather confused. It does seem to be very difficult to correlate the molecular structure of these semiconductors with their experimental electrical properties. For inorganic materials a simple definition delimits a fairly homogeneous family. If an inorganic material has a conductivity intermediate between that of an 12 1 1 3 1 1 insulator « 10- n- cm- ) and that of a metal (> 10 n- cm- ), then it is a semiconductor and will exhibit the characteristic properties of this family, such as junction formation, photoconductivity, and the photovoltaic effect. For molecular compounds,...

  20. Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

    Directory of Open Access Journals (Sweden)

    Mitsumasa Koyanagi

    2011-02-01

    Full Text Available New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D and hetero integration of complementary metal-oxide semiconductors (CMOS and microelectromechanical systems (MEMS. By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

  1. EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

    Science.gov (United States)

    Gabor, Allen H.; Brendler, Andrew C.; Brunner, Timothy A.; Chen, Xuemei; Culp, James A.; Levinson, Harry J.

    2018-03-01

    The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term "EPE" has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of "Good Fields"1 and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma "value" design-rules need to be tested to ensure high yield. The "value" can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement

  2. Offshoring in the Semiconductor Industry: A Historical Perspective

    OpenAIRE

    Brown, Clair; Linden, Greg

    2005-01-01

    Semiconductor design is a frequently-cited example of the new wave of offshoring and foreign-outsourcing of service sector jobs. It is certainly a concern to U.S. design engineers themselves. In addition to the current wave of white-collar outsourcing, the industry also has a rich experience with offshoring of manufacturing activity. Semiconductor companies were among the first to invest in offshore facilities to manufacture goods for imports back to the U.S. A brief review of these...

  3. System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

    Directory of Open Access Journals (Sweden)

    Daniel D. Gajski

    2008-07-01

    Full Text Available The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

  4. High-performance, scalable optical network-on-chip architectures

    Science.gov (United States)

    Tan, Xianfang

    The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of

  5. The response of silicon PNCCD sensors with aluminium on-chip filter to visible light, UV- and X-ray radiation

    Energy Technology Data Exchange (ETDEWEB)

    Granato, Stefanie

    2012-10-18

    There are various scientific applications, from astronomical observations to free electron lasers, that make use of X-ray semiconductor detectors like PNCCDs. The PNCCD is a pixelized semiconductor detector for simultaneous X-ray imaging and spectroscopy. For the seven PNCCD cameras of the eROSITA space telescope, a radiation entrance window including an on-chip optical blocking filter has been designed. The blocking filter is a necessity to minimize electron generation by visible light and UV radiation affecting X-ray spectroscopy. A PNCCD with such a blocking filter has not been used so far in astronomy. The following work deals with the analysis of the response of PNCCDs with on-chip filter. This includes the study of photon absorption and emission processes as well as the transport of electrons inside the detector entrance window. Furthermore it comprises the experimental characterization of the detector properties regarding the attenuation of light as well as their X-ray spectral redistribution function and quantum efficiency. With the ability to reveal the involved physical processes, the PNCCD is subject of analysis and measurement device at the same time. In addition to the results of the measurements, simulations of the solid state physics inside the detector are presented. A Geant4 Monte-Carlo code is extended by the treatment of charge loss in the entrance window and is verified by comparison with experimental data. Reproducing the chain of processes from photon absorption to charge collection, this work provides a detailed understanding of the formation of PNCCD spectra. The spectral features observed in the measurements are attributed to their point of origin inside the detector volume and explained by the model. The findings of this work allow high precision analysis of spectra of silicon detectors, e.g. of the eROSITA data, based on the presented detailed spectral response model.

  6. The response of silicon PNCCD sensors with aluminium on-chip filter to visible light, UV- and X-ray radiation

    International Nuclear Information System (INIS)

    Granato, Stefanie

    2012-01-01

    There are various scientific applications, from astronomical observations to free electron lasers, that make use of X-ray semiconductor detectors like PNCCDs. The PNCCD is a pixelized semiconductor detector for simultaneous X-ray imaging and spectroscopy. For the seven PNCCD cameras of the eROSITA space telescope, a radiation entrance window including an on-chip optical blocking filter has been designed. The blocking filter is a necessity to minimize electron generation by visible light and UV radiation affecting X-ray spectroscopy. A PNCCD with such a blocking filter has not been used so far in astronomy. The following work deals with the analysis of the response of PNCCDs with on-chip filter. This includes the study of photon absorption and emission processes as well as the transport of electrons inside the detector entrance window. Furthermore it comprises the experimental characterization of the detector properties regarding the attenuation of light as well as their X-ray spectral redistribution function and quantum efficiency. With the ability to reveal the involved physical processes, the PNCCD is subject of analysis and measurement device at the same time. In addition to the results of the measurements, simulations of the solid state physics inside the detector are presented. A Geant4 Monte-Carlo code is extended by the treatment of charge loss in the entrance window and is verified by comparison with experimental data. Reproducing the chain of processes from photon absorption to charge collection, this work provides a detailed understanding of the formation of PNCCD spectra. The spectral features observed in the measurements are attributed to their point of origin inside the detector volume and explained by the model. The findings of this work allow high precision analysis of spectra of silicon detectors, e.g. of the eROSITA data, based on the presented detailed spectral response model.

  7. A microfluidic chip for electrochemical conversions in drug metabolism studies

    NARCIS (Netherlands)

    Odijk, Mathieu; Baumann, A.; Lohmann, W.; van den Brink, Floris Teunis Gerardus; Olthuis, Wouter; Karst, U.; van den Berg, Albert

    2009-01-01

    We have designed a microfluidic microreactor chip for electrochemical conversion of analytes, containing a palladium reference electrode and platinum working and counter electrodes. The counter electrode is placed in a separate side-channel on chip to prevent unwanted side-products appearing in the

  8. Operation of the ATLAS Semiconductor Tracker: commissioning and performance results with cosmic ray data

    OpenAIRE

    González-Sevilla, S

    2009-01-01

    The Semiconductor Tracker (SCT) is one of the three sub-systems of the ATLAS internal tracker. Its complete installation and sign-off took about 18 months and was finished at the beginning of 2008. Since then, the SCT has been run successfully taking data in combined mode with the other ATLAS sub-systems. The major problems related with cooling failures and the mortality of off-detector opto-chips have been solved. As in summer 2009, more than 99% of the main detector components are fully wor...

  9. Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

    Energy Technology Data Exchange (ETDEWEB)

    Ni, Jing [Iowa State Univ., Ames, IA (United States)

    2000-09-21

    This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

  10. A survey of research and practices of network-on-chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar

    2006-01-01

    The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures...

  11. Thienoacene-based organic semiconductors.

    Science.gov (United States)

    Takimiya, Kazuo; Shinamura, Shoji; Osaka, Itaru; Miyazaki, Eigo

    2011-10-11

    Thienoacenes consist of fused thiophene rings in a ladder-type molecular structure and have been intensively studied as potential organic semiconductors for organic field-effect transistors (OFETs) in the last decade. They are reviewed here. Despite their simple and similar molecular structures, the hitherto reported properties of thienoacene-based OFETs are rather diverse. This Review focuses on four classes of thienoacenes, which are classified in terms of their chemical structures, and elucidates the molecular electronic structure of each class. The packing structures of thienoacenes and the thus-estimated solid-state electronic structures are correlated to their carrier transport properties in OFET devices. With this perspective of the molecular structures of thienoacenes and their carrier transport properties in OFET devices, the structure-property relationships in thienoacene-based organic semiconductors are discussed. The discussion provides insight into new molecular design strategies for the development of superior organic semiconductors. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. A Low Cost Single Chip VDL Compatible Transceiver ASIC

    Science.gov (United States)

    Becker, Robert

    2004-01-01

    Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

  13. Reliability, Availability and Serviceability of Networks-on-Chip

    CERN Document Server

    Cota, Érika; Soares Lubaszewski, Marcelo

    2012-01-01

    This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

  14. Semiconductor Manufacturing equipment introduction

    International Nuclear Information System (INIS)

    Im, Jong Sun

    2001-02-01

    This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

  15. MCMII and the TriP chip

    Energy Technology Data Exchange (ETDEWEB)

    Juan Estrada et al.

    2003-12-19

    We describe the development of the electronics that will be used to read out the Fiber Tracker and Preshower detectors in Run IIb. This electronics is needed for operation at 132ns bunch crossing, and may provide a measurement of the z coordinate of the Fiber Tracker hits when operating at 396ns bunch crossing. Specifically, we describe the design and preliminary tests of the Trip chip, MCM IIa, MCM IIb and MCM IIc. This document also serves as a user manual for the Trip chip and the MCM.

  16. [Application of next-generation semiconductor sequencing technologies in genetic diagnosis of inherited cardiomyopathies].

    Science.gov (United States)

    Zhao, Yue; Zhang, Hong; Xia, Xue-shan

    2015-07-01

    Inherited cardiomyopathy is the most common hereditary cardiac disease. It also causes a significant proportion of sudden cardiac deaths in young adults and athletes. So far, approximately one hundred genes have been reported to be involved in cardiomyopathies through different mechanisms. Therefore, the identification of the genetic basis and disease mechanisms of cardiomyopathies are important for establishing a clinical diagnosis and genetic testing. Next-generation semiconductor sequencing (NGSS) technology platform is a high-throughput sequencer capable of analyzing clinically derived genomes with high productivity, sensitivity and specificity. It was launched in 2010 by Life Technologies of USA, and it is based on a high density semiconductor chip, which was covered with tens of thousands of wells. NGSS has been successfully used in candidate gene mutation screening to identify hereditary disease. In this review, we summarize these genetic variations, challenge and application of NGSS in inherited cardiomyopathy, and its value in disease diagnosis, prevention and treatment.

  17. Computational nano-materials design for high-TC ferromagnetism in wide-gap magnetic semiconductors

    International Nuclear Information System (INIS)

    Katayama-Yoshida, H.; Sato, K.; Fukushima, T.; Toyoda, M.; Kizaki, H.; Dinh, V.A.; Dederichs, P.H.

    2007-01-01

    We propose materials design of high-T C wide band-gap dilute magnetic semiconductors (DMSs) based on first-principles calculations by using the Korringa-Kohn-Rostoker coherent potential approximation (KKR-CPA) method. First, we discuss a unified physical picture of ferromagnetism in II-VI and III-V DMSs and show that DMS family is categorized into two groups depending on the electronic structure. One is the system where Zener's double exchange mechanism dominates in the ferromagnetic interaction, and in the other systems Zener's p-d exchange mechanism dominates. Next, we develop an accurate method for T C calculation for the DMSs and show that the mean field approximation completely fails to predict Curie temperature of DMS in particular for wide-gap DMS where the exchange interaction is short-ranged. The calculated T C of homogeneous DMSs by using the present method agrees very well with available experimental values. For more realistic material design, we simulate spinodal nano-decomposition by applying the Monte Carlo method to the Ising model with ab initio chemical pair interactions between magnetic impurities in DMS. It is found that by controlling the dimensionality of the decomposition various characteristic phases occur in DMS such as 3D Dairiseki-phase and 1D Konbu-phase, and it is suggested that super-paramagnetic blocking phenomena should be important to understand the magnetism of wide-gap DMS. Based on the present simulations for spinodal nano-decomposition, we propose a new crystal growth method of positioning by seeding and shape controlling method in 100 Tera-bit density of nano-magnets in the semiconductor matrix with high-T C (or high-T B )

  18. Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

    KAUST Repository

    Johansson, Johan R.

    2012-03-12

    We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

  19. Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

    KAUST Repository

    Johansson, Johan R.; Bosaeus, Niklas; Kann, Nina; Å kerman, Bjö rn; Nordé n, Bengt; Khalid, Waqas

    2012-01-01

    We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

  20. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  1. Experimental verification of on-chip CMOS fractional-order capacitor emulators

    KAUST Repository

    Tsirimokou, G.

    2016-06-13

    The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

  2. Experimental verification of on-chip CMOS fractional-order capacitor emulators

    KAUST Repository

    Tsirimokou, G.; Psychalinos, C.; Salama, Khaled N.; Elwakil, A.S.

    2016-01-01

    The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

  3. On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

    International Nuclear Information System (INIS)

    Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

    2010-01-01

    We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

  4. Designing Selectivity in Metal-Semiconductor Nanocrystals: Synthesis, Characterization, and Self-Assembly

    Science.gov (United States)

    Pavlopoulos, Nicholas George

    This dissertation contains six chapters detailing recent advances that have been made in the synthesis and characterization of metal-semiconductor hybrid nanocrystals (HNCs), and the applications of these materials. Primarily focused on the synthesis of well-defined II-VI semiconductor nanorod (NR) and tetrapod (TP) based constructs of interest for photocatalytic and solar energy applications, the research described herein discusses progress towards the realization of key design rules for the synthesis of functional semiconductor nanocrystals (NCs). As such, a blend of novel synthesis, advanced characterization, and direct application of heterostructured nanoparticles are presented. The first chapter is a review summarizing the design, synthesis, properties, and applications of multicomponent nanomaterials composed of disparate semiconductor and metal domains. By coupling two compositionally distinct materials onto a single nanocrystal, synergistic properties can arise that are not present in the isolated components, ranging from self-assembly to photocatalysis. For semiconductor nanomaterials, this was first realized in the ability to tune nanomaterial dimensions from 0-D quantum dot (QD) structures to cylindrical (NR) and branched (TP) structures by exploitation of advanced colloidal synthesis techniques and understandings of NC facet reactivities. The second chapter is focused on the synthesis and characterization of well-defined CdSe-seeded-CdS (CdSe CdS) NR systems synthesized by overcoating of wurtzite (W) CdSe quantum dots with W-CdS shells. 1-dimensional NRs have been interesting constructs for applications such as solar concentrators, optical gains, and photocatalysis. Through synthetic control over CdSe CdS NR systems, materials with small and large CdSe seeds were prepared, and for each seed size, multiple NR lengths were prepared. Through transient absorption studies, it was found that band alignment did not affect the efficiency of charge localization

  5. Electrical overstress (EOS) devices, circuits and systems

    CERN Document Server

    Voldman, Steven H

    2013-01-01

    Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics.  This bookteaches the fundamentals of electrical overstress  and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design.  It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in spe

  6. Conduit for high temperature transfer of molten semiconductor crystalline material

    Science.gov (United States)

    Fiegl, George (Inventor); Torbet, Walter (Inventor)

    1983-01-01

    A conduit for high temperature transfer of molten semiconductor crystalline material consists of a composite structure incorporating a quartz transfer tube as the innermost member, with an outer thermally insulating layer designed to serve the dual purposes of minimizing heat losses from the quartz tube and maintaining mechanical strength and rigidity of the conduit at the elevated temperatures encountered. The composite structure ensures that the molten semiconductor material only comes in contact with a material (quartz) with which it is compatible, while the outer layer structure reinforces the quartz tube, which becomes somewhat soft at molten semiconductor temperatures. To further aid in preventing cooling of the molten semiconductor, a distributed, electric resistance heater is in contact with the surface of the quartz tube over most of its length. The quartz tube has short end portions which extend through the surface of the semiconductor melt and which are lef bare of the thermal insulation. The heater is designed to provide an increased heat input per unit area in the region adjacent these end portions.

  7. Semiconductor physics an introduction

    CERN Document Server

    Seeger, Karlheinz

    1999-01-01

    Semiconductor Physics - An Introduction - is suitable for the senior undergraduate or new graduate student majoring in electrical engineering or physics. It will also be useful to solid-state scientists and device engineers involved in semiconductor design and technology. The text provides a lucid account of charge transport, energy transport and optical processes, and a detailed description of many devices. It includes sections on superlattices and quantum well structures, the effects of deep-level impurities on transport, the quantum Hall effect and the calculation of the influence of a magnetic field on the carrier distribution function. This 6th edition has been revised and corrected, and new sections have been added to different chapters.

  8. Wake on LAN over Internet as web service system on chip

    OpenAIRE

    Maciá Pérez, Francisco; Gil Martínez-Abarca, Juan Antonio; Ramos Morillo, Héctor; Mora Gimeno, Francisco José; Marcos Jorquera, Diego; Gilart Iglesias, Virgilio

    2009-01-01

    In this paper we introduce a System on Chip (SoC) designed to run a particular Web Service (WS) in an Application-Specific Integrated Circuit (ASIC). The system has been designed devoid of processor and software and conceived as a hardware pattern for a trouble-free design of network services offered as WS in Service-Oriented Architecture (SOA). Therefore, the chip is not only able to act as SOAP Service Provider but, it is also capable of registering the service on its own in an external Bro...

  9. A novel integrated circuit for semiconductor radiation detectors with sparse readout

    International Nuclear Information System (INIS)

    Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

    2008-01-01

    A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

  10. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  11. DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

    Directory of Open Access Journals (Sweden)

    A. KISHORE KUMAR

    2014-12-01

    Full Text Available Static Random Access Memory (SRAM has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST logic is proposed. The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability. The proposed design is simulated using 0.18 µm process technology and compared with conventional 6T cell. Simulation results show that the proposed memory cell achieves significant improvements in power consumption during read and write operations. It can retain data at a lower supply voltage of 300 mV. This new type of SRAM design can operate at a maximum frequency of 1 GHz at 1 V supply voltage. These qualities of the proposed design make it a best choice for high performance memory chips in the semiconductor industry where reliability and power consumption are of great interest.

  12. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard...... cell design. Our implementation is based on clockless circuit techniques, and thus inherently supports a modular, GALS-oriented design flow. Our router exploits virtual channels to provide connection-oriented GS, as well as connection-less best-effort (BE) routing. The architecture is highly flexible...

  13. Numerical investigation of thermal performance of a water-cooled mini-channel heat sink for different chip arrangement

    Energy Technology Data Exchange (ETDEWEB)

    Tikadar, Amitav, E-mail: amitav453@gmail.com; Hossain, Md. Mahamudul; Morshed, A. K. M. M. [Department of Mechanical Engineering, Bangladesh University of Engineering and Technology, Dhaka, 1000 (Bangladesh)

    2016-07-12

    Heat transfer from electronic chip is always challenging and very crucial for electronic industry. Electronic chips are assembled in various manners according to the design conditions and limitationsand thus the influence of chip assembly on the overall thermal performance needs to be understand for the efficient design of electronic cooling system. Due to shrinkage of the dimension of channel and continuous increment of thermal load, conventional heat extraction techniques sometimes become inadequate. Due to high surface area to volume ratio, mini-channel have the natural advantage to enhance convective heat transfer and thus to play a vital role in the advanced heat transfer devices with limited surface area and high heat flux. In this paper, a water cooled mini-channel heat sink was considered for electronic chip cooling and five different chip arrangements were designed and studied, namely: the diagonal arrangement, parallel arrangement, stacked arrangement, longitudinal arrangement and sandwiched arrangement. Temperature distribution on the chip surfaces was presented and the thermal performance of the heat sink in terms of overall thermal resistance was also compared. It is found that the sandwiched arrangement of chip provides better thermal performance compared to conventional in line chip arrangement.

  14. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H; Seppaenen, V

    1997-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  15. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H.; Seppaenen, V.

    1996-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  16. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  17. FISH & CHIPS: Single Chip Silicon MEMS CTDL Salinity, Temperature, Pressure and Light sensor for use in fisheries research

    DEFF Research Database (Denmark)

    Hyldgård, Anders; Hansen, Ole; Thomsen, Erik Vilain

    2005-01-01

    A single-chip silicon MEMS CTDL multi sensor for use in aqueous environments is presented. The new sensor chip consists of a conductivity sensor based on platinum electrodes (C), an ion-implanted thermistor temperature sensor (T), a piezoresistive pressure sensor (D for depth/pressure) and an ion......-implanted p-n junction light sensor (L). The design and fabrication process is described. A temperature sensitivity of 0.8 × 10-3K-1 has been measured and detailed analysis of conductivity measurement data shows a cell constant of 81 cm-1....

  18. Silicon microstrip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Masciocchi, S.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.S.; Timm, S.; Vorwalter, K.; Werding, R.

    1995-01-01

    A new silicon strip detector has been designed for the fixed target experiment WA89 at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into a FASTBUS memory. The detector provides a fast readout by offering zero-suppressed data extraction on the chip. The silicon counters are the largest detectors built on a monocrystal so far in order to achieve good transversal acceptance. Construction and performance during the 1993 data taking run are discussed. ((orig.))

  19. Semiconductor laser using multimode interference principle

    Science.gov (United States)

    Gong, Zisu; Yin, Rui; Ji, Wei; Wu, Chonghao

    2018-01-01

    Multimode interference (MMI) structure is introduced in semiconductor laser used in optical communication system to realize higher power and better temperature tolerance. Using beam propagation method (BPM), Multimode interference laser diode (MMI-LD) is designed and fabricated in InGaAsP/InP based material. As a comparison, conventional semiconductor laser using straight single-mode waveguide is also fabricated in the same wafer. With a low injection current (about 230 mA), the output power of the implemented MMI-LD is up to 2.296 mW which is about four times higher than the output power of the conventional semiconductor laser. The implemented MMI-LD exhibits stable output operating at the wavelength of 1.52 μm and better temperature tolerance when the temperature varies from 283.15 K to 293.15 K.

  20. Atomic layer deposited TiO2 for implantable brain-chip interfacing devices

    International Nuclear Information System (INIS)

    Cianci, E.; Lattanzio, S.; Seguini, G.; Vassanelli, S.; Fanciulli, M.

    2012-01-01

    In this paper we investigated atomic layer deposition (ALD) TiO 2 thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 °C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al 2 O 3 buffer layer between TiO 2 and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

  1. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  2. Self-powered integrated systems-on-chip (energy chip)

    Science.gov (United States)

    Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

    2010-04-01

    In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  3. Opto-electronic DNA chip-based integrated card for clinical diagnostics.

    Science.gov (United States)

    Marchand, Gilles; Broyer, Patrick; Lanet, Véronique; Delattre, Cyril; Foucault, Frédéric; Menou, Lionel; Calvas, Bernard; Roller, Denis; Ginot, Frédéric; Campagnolo, Raymond; Mallard, Frédéric

    2008-02-01

    Clinical diagnostics is one of the most promising applications for microfluidic lab-on-a-chip or lab-on-card systems. DNA chips, which provide multiparametric data, are privileged tools for genomic analysis. However, automation of molecular biology protocol and use of these DNA chips in fully integrated systems remains a great challenge. Simplicity of chip and/or card/instrument interfaces is amongst the most critical issues to be addressed. Indeed, current detection systems for DNA chip reading are often complex, expensive, bulky and even limited in terms of sensitivity or accuracy. Furthermore, for liquid handling in the lab-on-cards, many devices use complex and bulky systems, either to directly manipulate fluids, or to ensure pneumatic or mechanical control of integrated valves. All these drawbacks prevent or limit the use of DNA-chip-based integrated systems, for point-of-care testing or as a routine diagnostics tool. We present here a DNA-chip-based protocol integration on a plastic card for clinical diagnostics applications including: (1) an opto-electronic DNA-chip, (2) fluid handling using electrically activated embedded pyrotechnic microvalves with closing/opening functions. We demonstrate both fluidic and electric packaging of the optoelectronic DNA chip without major alteration of its electronical and biological functionalities, and fluid control using novel electrically activable pyrotechnic microvalves. Finally, we suggest a complete design of a card dedicated to automation of a complex biological protocol with a fully electrical fluid handling and DNA chip reading.

  4. Avaliação da aceitação de "chips" de mandioca Acceptance evaluation of cassava chips

    Directory of Open Access Journals (Sweden)

    Regina Kitagawa Grizotto

    2003-12-01

    block design. The results showed sensory acceptance of both the pre-cooked and non pre-cooked (control chips, with means of 5.1 (liked slightly for IAC Mantiqueira and 6.0 (liked moderately for IAC 576.70. The pre-fermented chips of both varieties were rejected. The agreeable attributes most cited by the judges were: "cassava flavour", "crispness" and "texture". The disagreeable attributes most cited were "hard texture", "lack of cassava flavour" and "oily taste". The appearance of the chips from both varieties was considered adequate, with slightly preferred to the IAC 576.70, with the exception of those cooked for 8 minutes and the fermented samples, which were rejected. The yellow colour of the IAC 576.70 cassava pulp may have influenced the acceptance of these chips. The proximate compositions and fibre contents of the in natura cassava roots and the fat contents of the chips, are also presented.

  5. Design and length optimization of an adiabatic coupler for on-chip vertical integration of rare-earth-doped double tungstate waveguide amplifiers

    NARCIS (Netherlands)

    Mu, Jinfeng; Sefünç, Mustafa; García Blanco, Sonia Maria

    2014-01-01

    The integration of rare-earth doped double tungstate waveguide amplifiers onto passive technology platforms enables the on-chip amplification of very high bit rate signals. In this work, a methodology for the optimized design of vertical adiabatic couplers between a passive Si3N4 waveguide and the

  6. Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

    International Nuclear Information System (INIS)

    Irmler, C.; Bauer, A.; Bergauer, T.; Adamczyk, K.; Bacher, S.; Aihara, H.; Angelini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Aziz, T.; Babu, V.; Bahinipati, S.; Barberio, E.; Baroncelli, Ti.; Baroncelli, To.; Basith, A.K.; Behera, P.K.; Bhuyan, B.; Bilka, T.

    2016-01-01

    The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests

  7. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  8. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  9. Organ-Tumor-on-a-Chip for Chemosensitivity Assay: A Critical Review

    Directory of Open Access Journals (Sweden)

    Navid Kashaninejad

    2016-07-01

    Full Text Available With a mortality rate over 580,000 per year, cancer is still one of the leading causes of death worldwide. However, the emerging field of microfluidics can potentially shed light on this puzzling disease. Unique characteristics of microfluidic chips (also known as micro-total analysis system make them excellent candidates for biological applications. The ex vivo approach of tumor-on-a-chip is becoming an indispensable part of personalized medicine and can replace in vivo animal testing as well as conventional in vitro methods. In tumor-on-a-chip, the complex three-dimensional (3D nature of malignant tumor is co-cultured on a microfluidic chip and high throughput screening tools to evaluate the efficacy of anticancer drugs are integrated on the same chip. In this article, we critically review the cutting edge advances in this field and mainly categorize each tumor-on-a-chip work based on its primary organ. Specifically, design, fabrication and characterization of tumor microenvironment; cell culture technique; transferring mechanism of cultured cells into the microchip; concentration gradient generators for drug delivery; in vitro screening assays of drug efficacy; and pros and cons of each microfluidic platform used in the recent literature will be discussed separately for the tumor of following organs: (1 Lung; (2 Bone marrow; (3 Brain; (4 Breast; (5 Urinary system (kidney, bladder and prostate; (6 Intestine; and (7 Liver. By comparing these microchips, we intend to demonstrate the unique design considerations of each tumor-on-a-chip based on primary organ, e.g., how microfluidic platform of lung-tumor-on-a-chip may differ from liver-tumor-on-a-chip. In addition, the importance of heart–liver–intestine co-culture with microvasculature in tumor-on-a-chip devices for in vitro chemosensitivity assay will be discussed. Such system would be able to completely evaluate the absorption, distribution, metabolism, excretion and toxicity (ADMET of

  10. Research and Design on a Product Data Definition System of Semiconductor Packaging Industry

    Science.gov (United States)

    Shi, Jinfei; Ma, Qingyao; Zhou, Yifan; Chen, Ruwen

    2017-12-01

    This paper develops a product data definition (PDD) system for a semiconductor packaging and testing company with independent intellectual property rights. The new PDD system can solve the problems such as, the effective control of production plans, the timely feedback of production processes, and the efficient schedule of resources. Firstly, this paper introduces the general requirements of the PDD system and depicts the operation flow and the data flow of the PDD system. Secondly, the overall design scheme of the PDD system is put forward. After that, the physical data model is developed using the Power Designer15.0 tool, and the database system is built. Finally, the function realization and running effects of the PDD system are analysed. The successful operation of the PDD system can realize the information flow among various production departments of the enterprise to meet the standard of the enterprise manufacturing integration and improve the efficiency of production management.

  11. Integrated microelectronic capacitive readout subsystem for lab-on-a-chip applications

    International Nuclear Information System (INIS)

    Spathis, Christos; Georgakopoulou, Konstantina; Petrellis, Nikos; Efstathiou, Konstantinos; Birbas, Alexios

    2014-01-01

    A mixed-signal capacitive biosensor readout system is presented with its main readout functionality embedded in an integrated circuit, compatible with complementary metal oxide semiconductor-type biosensors. The system modularity allows its usage as a consumable since it eventually leads to a system-on-chip where sensor and readout circuitry are hosted on the same die. In this work, a constant current source is used for measuring the input capacitance. Compared to most capacitive biosensor readout circuits, this method offers the convenience of adjusting both the range and the resolution, depending on the requirements dictated by the application. The chip consumes less than 5 mW of power and the die area is 0.06 mm 2 . It shows a broad input capacitance range (capable of measuring bio-capacitances from 6 pF to 9.8 nF), configurable resolution (down to 1 fF), robustness to various biological experiments and good linearity. The integrated nature of the readout system is proven to be sufficient both for one-time in situ (consumable-type) bio-measurements and its incorporation into a point-of-care system. (paper)

  12. Digital design update for a sun sensor on a chip

    NARCIS (Netherlands)

    Mert, O.

    2014-01-01

    In the beginning of one year project work at Moog-Bradford, the scope of my assignment was coordination of the firmware development activities as defined in the Sun Sensor on a Chip (SSOAC) proposal for ESA GSTP-5 program. As the time progressed in the proposal evaluation process, my project scope

  13. Integrated Materials Design of Organic Semiconductors for Field-Effect Transistors

    KAUST Repository

    Mei, Jianguo; Diao, Ying; Appleton, Anthony L.; Fang, Lei; Bao, Zhenan

    2013-01-01

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm2/(V s). In this perspective, we highlight

  14. Semiconductor physics

    CERN Document Server

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  15. On-chip patch antenna on InP substrate for short-range wireless communication at 140 GHz

    DEFF Research Database (Denmark)

    Dong, Yunfeng; Johansen, Tom Keinicke; Zhurbenko, Vitaliy

    2017-01-01

    This paper presents the design of an on-chip patch antenna on indium phosphide (InP) substrate for short-range wireless communication at 140 GHz. The antenna shows a simulated gain of 5.3 dBi with 23% bandwidth at 140 GHz and it can be used for either direct chip-to-chip communication or chip...

  16. Chips in banknotes for a banknote electronic signature

    Science.gov (United States)

    Perron, Maurice; Grimal, Jean-Michel; Beauchet, Frederic; Dell'Ova, Francis

    2004-06-01

    A lot of information can be found in the media about the possibility of using micro-chips in banknotes. This mostly comes from chip manufacturers whose technology is becoming mature for this application. A lot of patents have been applied therefore but what must be noticed is that all these patents concern the processes to insert chips in banknotes and not a lot is said about the product itself and for what use. The Banque de France is a Central Bank involved in all tasks concerning banknotes from design, production, issue, recirculation and sorting, action against counterfeiting and finally destruction. These activities concern, of course, the banknotes in circulation in France (formerly the French francs notes, presently the Euro notes as Banque de France is part of the Eurosystem) and in other countries in the world. The Banque de France approach in looking to the future of chips in banknotes is at first a product approach. Banknotes are means of payment for which security of authentication is fundamental. They could carry chips to provide more security in the transactions but without altering their nature: the anonyminity and immediacy of the transactions.

  17. STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

    Directory of Open Access Journals (Sweden)

    Ireneusz Zagórski

    2016-12-01

    Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

  18. Wood chip production technology and costs for fuel in Namibia

    Energy Technology Data Exchange (ETDEWEB)

    Leinonen, A.

    2007-12-15

    This work has been done in the project where the main target is to evaluate the technology and economy to use bush biomass for power production in Namibia. The project has been financed by the Ministry for Foreign Affairs of Finland and the Ministry of Agriculture, Water and Forestry of the Republic of Namibia. The target of this study is to calculate the production costs of bush chips at the power plant using the current production technology and to look possibilities to develop production technology in order to mechanize production technology and to decrease the production costs. The wood production costs are used in feasibility studies, in which the technology and economy of utilization of wood chips for power generation in 5, 10 and 20 MW electric power plants and for power generation in Van Eck coal fired power plant in Windhoek are evaluated. Field tests were made at Cheetah Conservation Farm (CCF) in Otjiwarongo region. CCF is producing wood chips for briquette factory in Otjiwarongo. In the field tests it has been gathered information about this CCF semi-mechanized wood chip production technology. Also new machines for bush biomass chip production have been tested. A new mechanized production chain has been designed on the basis of this information. The production costs for the CCF semi-mechanized and the new production chain have been calculated. The target in the moisture content to produce wood chips for energy is 20 w-%. In the semi-mechanized wood chip production chain the work is done partly manually, and the supply chain is organized into crews of 4.8 men. The production chain consists of manual felling and compiling, drying, chipping with mobile chipper and manual feeding and road transport by a tractor with two trailers. The CCF production chain works well. The chipping and road transport productivity in the semimechanized production chain is low. New production machines, such as chainsaw, brush cutter, lawn mover type cutter, rotator saw in skid

  19. Optic nerve signals in a neuromorphic chip II: Testing and results.

    Science.gov (United States)

    Zaghloul, Kareem A; Boahen, Kwabena

    2004-04-01

    Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

  20. Route to one-step microstructure mold fabrication for PDMS microfluidic chip

    Science.gov (United States)

    Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

    2018-04-01

    The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

  1. Measurement stand for diagnosis of semiconductor detectors based on IBM PC/XT computer (4-way spectrometric analysis of pulses)

    International Nuclear Information System (INIS)

    Gruszecki, M.

    1990-01-01

    The technical assumptions and partial realization of our technological stand for quality inspection of semiconductor detectors for ionizing radiation manufactured in the INP in Cracow are described. To increase the efficiency of the measurements simultaneous checking of 4 semiconductor chips or finished products is suggested. In order to justify this measurement technique a review of possible variants of the measurement apparatus is presented for the systems consisting of home made units. Comparative parameters for the component modules and for complete measuring systems are given. The construction and operation of data acquisition system based on IBM PC/XT are described. The system ensures simultaneous registration of pulses obtained from 4 detectors with maximal rate of up to 500 x 10 3 pulses/s. 42 refs., 6 figs., 3 tabs. (author)

  2. Towards a Chemiresistive Sensor-Integrated Electronic Nose: A Review

    Directory of Open Access Journals (Sweden)

    Kea-Tiong Tang

    2013-10-01

    Full Text Available Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip.

  3. High-Tc dc-SQUID gradiometers in flip-chip configuration

    International Nuclear Information System (INIS)

    Peiselt, K; Schmidl, F; Linzen, S; Anton, A S; Huebner, U; Seidel, P

    2003-01-01

    We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-T c superconductor YBa 2 Cu 3 O 7-x (YBCO). For the flip-chip antenna, a 40 mm x 10 mm SrTiO 3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm x 10 mm SrTiO 3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm -1 Hz -1/2 in the white noise region and of 310 fT cm -1 Hz -1/2 at 1 Hz in the unshielded laboratory environment

  4. High-Tc dc-SQUID gradiometers in flip-chip configuration

    Science.gov (United States)

    Peiselt, K.; Schmidl, F.; Linzen, S.; Anton, A. S.; Hübner, U.; Seidel, P.

    2003-12-01

    We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-Tc superconductor YBa2Cu3O7-x (YBCO). For the flip-chip antenna, a 40 mm × 10 mm SrTiO3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm × 10 mm SrTiO3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm-1 Hz-1/2 in the white noise region and of 310 fT cm-1 Hz-1/2 at 1 Hz in the unshielded laboratory environment.

  5. Fabrication and application of amorphous semiconductor devices

    International Nuclear Information System (INIS)

    Kumurdjian, Pierre.

    1976-01-01

    This invention concerns the design and manufacture of elecric switching or memorisation components with amorphous semiconductors. As is known some compounds, particularly the chalcogenides, have a resistivity of the semiconductor type in the amorphous solid state. These materials are obtained by the high temperature homogeneisation of several single elements such as tellurium, arsenic, germanium and sulphur, followed by water or air quenching. In particular these compounds have useful switching and memorisation properties. In particular they have the characteristic of not suffering deterioration when placed in an environment subjected to nuclear radiations. In order to know more about the nature and properties of these amorphous semiconductors the French patent No. 71 28048 of 30 June 1971 may be consulted with advantage [fr

  6. Modification of semiconductors with proton beams. A review

    International Nuclear Information System (INIS)

    Kozlovskii, V.V.; Lomasov, V.N.; Kozlov, V.A.

    2000-01-01

    Analysis is given of the progress in the modification of semiconductors by proton beams in fields such as proton-enhanced diffusion, ion-beam mixing, and formation of porous layers. This method of modification (doping) is shown to have high potential in monitoring the properties of semiconductor materials and designing devices of micro and nano electronics as compared to the conventional doping techniques such as thermal diffusion, epitaxy, and ion implantation

  7. Fundamentals of semiconductor manufacturing and process control

    CERN Document Server

    May, Gary S

    2006-01-01

    A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems. Readers are introduced to both the theory and practice of all basic manufacturing concepts. Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields. The discussion of statistical experimental design offers readers a powerful approach for systematically varying controllable p...

  8. Fully integrated optical system for lab-on-a-chip applications

    DEFF Research Database (Denmark)

    Balslev, Søren; Olsen, Brian Bilenberg; Geschke, Oliver

    2004-01-01

    We present a lab-on-a-chip device featuring a microfluidic dye laser, wave-guides, microfluidic components and photo-detectors integrated on the chip. The microsystem is designed for wavelength selective absorption measurements in the visible range on a fluidic sample, which can be prepared....../mixed on-chip. The laser structures, wave-guides and micro-fluidic handling system are defined in a single UV-lithography step on a 10 μm thick SU-8 layer on top of the substrate. The SU-8 structures are sealed by a Borofloat glass lid, using polymethylmethacrylate (PMMA) adhesive bonding....

  9. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  10. Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

    Science.gov (United States)

    Yashin, A. A.

    1985-04-01

    A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

  11. Atomic layer deposited TiO{sub 2} for implantable brain-chip interfacing devices

    Energy Technology Data Exchange (ETDEWEB)

    Cianci, E., E-mail: elena.cianci@mdm.imm.cnr.it [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (MB) (Italy); Lattanzio, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Dipartimento di Ingegneria dell' Informazione, Universita di Padova, 35131 Padova (Italy); Seguini, G. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Vassanelli, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Fanciulli, M. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano-Bicocca, 20126 Milano (Italy)

    2012-05-01

    In this paper we investigated atomic layer deposition (ALD) TiO{sub 2} thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 Degree-Sign C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al{sub 2}O{sub 3} buffer layer between TiO{sub 2} and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

  12. The Electrical Characteristics of The N-Organic Semiconductor/P-Inorganic Semiconductor Diode

    International Nuclear Information System (INIS)

    Aydin, M. E.

    2008-01-01

    n-organic semiconductor (PEDOT) / p-inorganic semiconductor Si diode was formed by deep coating method. The method has been achieved by coating n-inorganic semiconductor PEDOT on top of p-inorganic semiconductor. The n-organic semiconductor PEDOT/ p-inorganic semiconductor diode demonstrated rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The barrier height , ideality factor values were obtained as of 0.88 eV and 1.95 respectively. The diode showed non-ideal I-V behavior with an ideality factor greater than unity that could be ascribed to the interfacial layer

  13. An Associative Memory Chip for the Trigger System of the ATLAS Experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00380893; The ATLAS collaboration; Liberali, Valentino; Crescioli, Francesco; Beretta, Matteo; Frontini, Luca; Annovi, Alberto; Stabile, Alberto

    2017-01-01

    The AM06 is the 6th version of a large associative memory chip designed in 65 nm CMOS tech- nology. The AM06 operates as a highly parallel ASIC processor for pattern recognition in the ATLAS experiment at CERN. It is the core of the Fast TracKer electronic system, which is tai- lored for on-line track finding in the trigger system of the ATLAS experiment. The Fast TracKer system is able to process events up to 100 MHz in real time. The AM06 is a complex chip, and it has been designed combining full-custom memory arrays, standard logic cells and IP blocks. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called a pattern. The chip silicon area is 168 mm2; it contains 421 millions of transistors and it stores 217 patterns. Moreover, the associative memory is suitable also for other interdisciplinary appli- cations (i.e., general purpose image filtering and analysis). In the near future we plan to design a more powerful and flexible chip in 28 nm CMOS technology.

  14. Organic Donor-Acceptor Complexes as Novel Organic Semiconductors.

    Science.gov (United States)

    Zhang, Jing; Xu, Wei; Sheng, Peng; Zhao, Guangyao; Zhu, Daoben

    2017-07-18

    Organic donor-acceptor (DA) complexes have attracted wide attention in recent decades, resulting in the rapid development of organic binary system electronics. The design and synthesis of organic DA complexes with a variety of component structures have mainly focused on metallicity (or even superconductivity), emission, or ferroelectricity studies. Further efforts have been made in high-performance electronic investigations. The chemical versatility of organic semiconductors provides DA complexes with a great number of possibilities for semiconducting applications. Organic DA complexes extend the semiconductor family and promote charge separation and transport in organic field-effect transistors (OFETs) and organic photovoltaics (OPVs). In OFETs, the organic complex serves as an active layer across extraordinary charge pathways, ensuring the efficient transport of induced charges. Although an increasing number of organic semiconductors have been reported to exhibit good p- or n-type properties (mobilities higher than 1 or even 10 cm 2 V -1 s -1 ), critical scientific challenges remain in utilizing the advantages of existing semiconductor materials for more and wider applications while maintaining less complicated synthetic or device fabrication processes. DA complex materials have revealed new insight: their unique molecular packing and structure-property relationships. The combination of donors and acceptors could offer practical advantages compared with their unimolecular materials. First, growing crystals of DA complexes with densely packed structures will reduce impurities and traps from the self-assembly process. Second, complexes based on the original structural components could form superior mixture stacking, which can facilitate charge transport depending on the driving force in the coassembly process. Third, the effective use of organic semiconductors can lead to tunable band structures, allowing the operation mode (p- or n-type) of the transistor to be

  15. Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    Science.gov (United States)

    Hashida, Takushi; Nagata, Makoto

    Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

  16. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    Science.gov (United States)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

  17. Revenue sharing in semiconductor industry supply chain ...

    Indian Academy of Sciences (India)

    to reduce demand opportunities, inventory needs and production efficiencies, in addition to reducing .... design based on coalition structures in semiconductor supply chain. ..... supplier/contract manufacturer for a product/component category.

  18. Estimation of Bulk modulus and microhardness of tetrahedral semiconductors

    International Nuclear Information System (INIS)

    Gorai, Sanjay Kumar

    2012-01-01

    A general empirical formula was found for calculating of bulk modulus (B) and microhardness (H) from electronegativity and principal quantum number of II-VI, III-V semiconductors. Constant C1, appearing the in the expression of bulk modulus and constants C2 and C3, appearing in the expression of microhardness and the exponent M have following values respectively The numerical values of C1,C2, C3 and M are respectively 206.6, 8.234, 1.291, -1.10 for II-VI 72.4, 31.87, 7.592, -0.95 for III-V semiconductors. Both electro-negativity and principal quantum number can effectively reflect on the chemical bonding behaviour of constituent atoms in these semiconductors. The calculated values of bulk modulus and microhardness are in good agreement with the reported values in the literature. Present study helps in designing novel semiconductor materials, and to further explore the mechanical properties of these semiconductors.

  19. Suppressing molecular vibrations in organic semiconductors by inducing strain.

    Science.gov (United States)

    Kubo, Takayoshi; Häusermann, Roger; Tsurumi, Junto; Soeda, Junshi; Okada, Yugo; Yamashita, Yu; Akamatsu, Norihisa; Shishido, Atsushi; Mitsui, Chikahiko; Okamoto, Toshihiro; Yanagisawa, Susumu; Matsui, Hiroyuki; Takeya, Jun

    2016-04-04

    Organic molecular semiconductors are solution processable, enabling the growth of large-area single-crystal semiconductors. Improving the performance of organic semiconductor devices by increasing the charge mobility is an ongoing quest, which calls for novel molecular and material design, and improved processing conditions. Here we show a method to increase the charge mobility in organic single-crystal field-effect transistors, by taking advantage of the inherent softness of organic semiconductors. We compress the crystal lattice uniaxially by bending the flexible devices, leading to an improved charge transport. The mobility increases from 9.7 to 16.5 cm(2) V(-1) s(-1) by 70% under 3% strain. In-depth analysis indicates that compressing the crystal structure directly restricts the vibration of the molecules, thus suppresses dynamic disorder, a unique mechanism in organic semiconductors. Since strain can be easily induced during the fabrication process, we expect our method to be exploited to build high-performance organic devices.

  20. Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

    Science.gov (United States)

    Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

    2016-10-01

    The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

  1. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  2. Semiconductor Physical Electronics

    CERN Document Server

    Li, Sheng

    2006-01-01

    Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

  3. Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

    International Nuclear Information System (INIS)

    Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

    2015-01-01

    Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

  4. Fundamentals of semiconductor devices

    CERN Document Server

    Lindmayer, Joseph

    1965-01-01

    Semiconductor properties ; semiconductor junctions or diodes ; transistor fundamentals ; inhomogeneous impurity distributions, drift or graded-base transistors ; high-frequency properties of transistors ; band structure of semiconductors ; high current densities and mechanisms of carrier transport ; transistor transient response and recombination processes ; surfaces, field-effect transistors, and composite junctions ; additional semiconductor characteristics ; additional semiconductor devices and microcircuits ; more metal, insulator, and semiconductor combinations for devices ; four-pole parameters and configuration rotation ; four-poles of combined networks and devices ; equivalent circuits ; the error function and its properties ; Fermi-Dirac statistics ; useful physical constants.

  5. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Gwyn, C.W.

    1976-09-01

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  6. Identifying semiconductors by d.c. ionization conductivity

    International Nuclear Information System (INIS)

    Derenzo, Stephen E.; Bourret-Courchesne, Edith; James, Floyd J.; Klintenberg, Mattias K.; Porter-Chapman, Yetta; Wang, Jie; Weber, Marvin J.

    2006-01-01

    We describe a method for identifying semiconductor radiation detector materials based on the mobility of internally generated electrons and holes. It was designed for the early stages of exploration, when samples are not available as single crystals, but as crystalline powders. Samples are confined under pressure in an electric field and the increase in current resulting from exposure to a high-intensity source of 60Co gamma rays (i.e. the ionization current) is measured. We find that for known semiconductors the d.c. ionization current depends on voltage according to the Hecht equation, and for known insulators the d.c. ionization current is below our detection limits. This shows that the method can identify semiconductors in spite of significant carrier trapping. Using this method, we have determined that BiOI, PbIF,BiPbO2Cl, BiPbO2Br, BiPbO2I, Bi2GdO4Cl, Pb3O2I2, and Pb5O4I2 are semiconductors

  7. Wirebond crosstalk and cavity modes in large chip mounts for superconducting qubits

    Energy Technology Data Exchange (ETDEWEB)

    Wenner, J; Neeley, M; Bialczak, Radoslaw C; Lenander, M; Lucero, Erik; O' Connell, A D; Sank, D; Wang, H; Weides, M; Cleland, A N; Martinis, John M, E-mail: martinis@physics.ucsb.edu [Department of Physics, University of California, Santa Barbara, CA 93106 (United States)

    2011-06-15

    We analyze the performance of a microwave chip mount that uses wirebonds to connect the chip and mount grounds. A simple impedance ladder model predicts that transmission crosstalk between two feedlines falls off exponentially with distance at low frequencies, but rises to near unity above a resonance frequency set by the chip to ground capacitance. Using SPICE simulations and experimental measurements of a scale model, the basic predictions of the ladder model were verified. In particular, by decreasing the capacitance between the chip and box grounds, the resonance frequency increased and transmission decreased. This model then influenced the design of a new mount that improved the isolation to - 65 dB at 6 GHz, even though the chip dimensions were increased to 1 cm x 1 cm, three times as large as our previous devices. We measured a coplanar resonator in this mount as preparation for larger qubit chips, and were able to identify cavity, slotline, and resonator modes.

  8. Wirebond crosstalk and cavity modes in large chip mounts for superconducting qubits

    International Nuclear Information System (INIS)

    Wenner, J; Neeley, M; Bialczak, Radoslaw C; Lenander, M; Lucero, Erik; O'Connell, A D; Sank, D; Wang, H; Weides, M; Cleland, A N; Martinis, John M

    2011-01-01

    We analyze the performance of a microwave chip mount that uses wirebonds to connect the chip and mount grounds. A simple impedance ladder model predicts that transmission crosstalk between two feedlines falls off exponentially with distance at low frequencies, but rises to near unity above a resonance frequency set by the chip to ground capacitance. Using SPICE simulations and experimental measurements of a scale model, the basic predictions of the ladder model were verified. In particular, by decreasing the capacitance between the chip and box grounds, the resonance frequency increased and transmission decreased. This model then influenced the design of a new mount that improved the isolation to - 65 dB at 6 GHz, even though the chip dimensions were increased to 1 cm x 1 cm, three times as large as our previous devices. We measured a coplanar resonator in this mount as preparation for larger qubit chips, and were able to identify cavity, slotline, and resonator modes.

  9. Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

    2006-11-15

    The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

  10. Temperature dependent electronic conduction in semiconductors

    International Nuclear Information System (INIS)

    Roberts, G.G.; Munn, R.W.

    1980-01-01

    This review describes the temperature dependence of bulk-controlled electronic currents in semiconductors. The scope of the article is wide in that it contrasts conduction mechanisms in inorganic and organic solids and also single crystal and disordered semiconductors. In many experimental situations it is the metal-semiconductor contact or the interface between two dissimilar semiconductors that governs the temperature dependence of the conductivity. However, in order to keep the length of the review within reasonable bounds, these topics have been largely avoided and emphasis is therefore placed on bulk-limited currents. A central feature of electronic conduction in semiconductors is the concentrations of mobile electrons and holes that contribute to the conductivity. Various statistical approaches may be used to calculate these densities which are normally strongly temperature dependent. Section 1 emphasizes the relationship between the position of the Fermi level, the distribution of quantum states, the total number of electrons available and the absolute temperature of the system. The inclusion of experimental data for several materials is designed to assist the experimentalist in his interpretation of activation energy curves. Sections 2 and 3 refer to electronic conduction in disordered solids and molecular crystals, respectively. In these cases alternative approaches to the conventional band theory approach must be considered. For example, the velocities of the charge carriers are usually substantially lower than those in conventional inorganic single crystal semiconductors, thus introducing the possibility of an activated mobility. Some general electronic properties of these materials are given in the introduction to each of these sections and these help to set the conduction mechanisms in context. (orig.)

  11. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  12. Design and Characterization of CMOS On-Chip Antennas for 60 GHz Communications

    Directory of Open Access Journals (Sweden)

    D.Titz

    2012-04-01

    Full Text Available In this paper, we present the design and the measurement of two antennas realized on a 130nm CMOS process. They both radiate in the 60 GHz band and are dedicated to Wireless Personal Area Network (WPAN applications. The antennas are manufactured within the frame of a multi-wafer project with several surrounding microelectronic circuits. The first antenna is an Inverted-F antenna (IFA. It has a maximum gain of -8 dBi and a -10 dB matching bandwidth of 20%. The second radiator is a meandered dipole. It has a maximum gain of -14 dBi and a -10 dB matching bandwidth of 10%. The challenging measurement of their reflection coefficient and their gain radiation pattern are presented. Simulated versus measured curves are analyzed. We especially demonstrate the necessity to take into account the closest microelectronic circuits of the antennas for accurate modeling of the radiating performance of 60 GHz on-chip dies.

  13. Doping of organic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Luessem, B.; Riede, M.; Leo, K. [Institut fuer Angewandte Photophysik, TU Dresden (Germany)

    2013-01-15

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  14. Doping of organic semiconductors

    International Nuclear Information System (INIS)

    Luessem, B.; Riede, M.; Leo, K.

    2013-01-01

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  15. Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

    Science.gov (United States)

    Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

    2006-12-01

    We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

  16. Evolution of the Novalux extended cavity surface-emitting semiconductor laser (NECSEL)

    Science.gov (United States)

    McInerney, John G.

    2016-03-01

    Novalux Inc was an enterprise founded by Aram Mooradian in 1998 to commercialise a novel electrically pumped vertical extended cavity semiconductor laser platform, initially aiming to produce pump lasers for optical fiber telecommunication networks. Following successful major investment in 2000, the company developed a range of single- and multi-mode 980 nm pump lasers emitting from 100-500 mW with excellent beam quality and efficiency. This rapid development required solution of several significant problems in chip and external cavity design, substrate and DBR mirror optimization, thermal engineering and mode selection. Output coupling to single mode fiber was exceptional. Following the collapse of the long haul telecom market in late 2001, a major reorientation of effort was undertaken, initially to develop compact 60-100 mW hybrid monolithically integrated pumplets for metro/local amplified networks, then to frequency-doubled blue light emitters for biotech, reprographics and general scientific applications. During 2001-3 I worked at Novalux on a career break from University College Cork, first as R&D Director managing a small group tasked with producing new capabilities and product options based on the NECSEL platform, including high power, pulsed and frequency doubled versions, then in 2002 as Director of New Product Realization managing the full engineering team, leading the transition to frequency doubled products.

  17. A 24 GHz CMOS oscillator transmitter with an inkjet printed on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.; Yang, Shuai; Cheema, Hammad M.; Shamim, Atif

    2016-01-01

    implemented off chip or the designers work with the inefficient passives. This problem can be alleviated by using inkjet printing as a post process on CMOS chip. In this work, we demonstrate inkjet printing of a patterned polymer (SU8) layer on a 24 GHz

  18. Reduced filamentation in high power semiconductor lasers

    DEFF Research Database (Denmark)

    Skovgaard, Peter M. W.; McInerney, John; O'Brien, Peter

    1999-01-01

    High brightness semiconductor lasers have applications in fields ranging from material processing to medicine. The main difficulty associated with high brightness is that high optical power densities cause damage to the laser facet and thus require large apertures. This, in turn, results in spatio......-temporal instabilities such as filamentation which degrades spatial coherence and brightness. We first evaluate performance of existing designs with a “top-hat” shaped transverse current density profile. The unstable nature of highly excited semiconductor material results in a run-away process where small modulations...

  19. Chip compacting press; Jido kirikuzu asshukuki

    Energy Technology Data Exchange (ETDEWEB)

    Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

    1998-08-15

    The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

  20. Recent advances in lab-on-a-chip for biosensing applications

    DEFF Research Database (Denmark)

    Lafleur, Josiane P.; Jönsson, Alexander; Senkbeil, Silja

    2016-01-01

    The marriage of highly sensitive biosensor designs with the versatility in sample handling and fluidic manipulation offered by lab-on-a-chip systems promises to yield powerful tools for analytical and, in particular, diagnostic applications. The field where these two technologies meet is rapidly...... improvements to existing methods. Recent examples, showing a staggering variety of lab-on-a-chip systems for biosensing applications, are presented, tabularized for overview, and briefly discussed....

  1. Design and test of a prototype silicon detector module for ATLAS Semiconductor Tracker endcaps

    International Nuclear Information System (INIS)

    Clark, A.G.; Donega, M.; D'Onofrio, M.

    2005-01-01

    The ATLAS Semiconductor Tracker (SCT) will be a central part of the tracking system of the ATLAS experiment. The SCT consists of four concentric barrels of silicon detectors as well as two silicon endcap detectors formed by nine disks each. The layout of the forward silicon detector module presented in this paper is based on the approved layout of the silicon detectors of the SCT, their geometry and arrangement in disks, but uses otherwise components identical to the barrel modules of the SCT. The module layout is optimized for excellent thermal management and electrical performance, while keeping the assembly simple and adequate for a large scale module production. This paper summarizes the design and layout of the module and present results of a limited prototype production, which has been extensively tested in the laboratory and testbeam. The module design was not finally adopted for series production because a dedicated forward hybrid layout was pursued

  2. Development of γ dose rate monitor based on FPGA and single-chip microcomputer

    International Nuclear Information System (INIS)

    He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

    2009-01-01

    A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

  3. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  4. Compound Semiconductor Radiation Detector

    International Nuclear Information System (INIS)

    Kim, Y. K.; Park, S. H.; Lee, W. G.; Ha, J. H.

    2005-01-01

    In 1945, Van Heerden measured α, β and γ radiations with the cooled AgCl crystal. It was the first radiation measurement using the compound semiconductor detector. Since then the compound semiconductor has been extensively studied as radiation detector. Generally the radiation detector can be divided into the gas detector, the scintillator and the semiconductor detector. The semiconductor detector has good points comparing to other radiation detectors. Since the density of the semiconductor detector is higher than that of the gas detector, the semiconductor detector can be made with the compact size to measure the high energy radiation. In the scintillator, the radiation is measured with the two-step process. That is, the radiation is converted into the photons, which are changed into electrons by a photo-detector, inside the scintillator. However in the semiconductor radiation detector, the radiation is measured only with the one-step process. The electron-hole pairs are generated from the radiation interaction inside the semiconductor detector, and these electrons and charged ions are directly collected to get the signal. The energy resolution of the semiconductor detector is generally better than that of the scintillator. At present, the commonly used semiconductors as the radiation detector are Si and Ge. However, these semiconductor detectors have weak points. That is, one needs thick material to measure the high energy radiation because of the relatively low atomic number of the composite material. In Ge case, the dark current of the detector is large at room temperature because of the small band-gap energy. Recently the compound semiconductor detectors have been extensively studied to overcome these problems. In this paper, we will briefly summarize the recent research topics about the compound semiconductor detector. We will introduce the research activities of our group, too

  5. Solid spectroscopy: semiconductors

    International Nuclear Information System (INIS)

    Silva, C.E.T.G. da

    1983-01-01

    Photoemission as technique of study of the semiconductor electronic structure is shortly discussed. Homogeneous and heterogeneous semiconductors, where volume and surface electronic structure, core levels and O and H chemisorption in GaAs, Schottky barrier are treated, respectively. Amorphous semiconductors are also discussed. (L.C.) [pt

  6. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  7. Fiscal 2000 research achievement report on the research and development of advanced design technologies for system-on-chip; 2000 nendo system on chip sentan sekkei gijutsu no kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-05-01

    Efforts were made to develop technologies for rapid improvement in SoC (system on chip) design productivity. In concrete terms, the concept of V-core (virtual core) was introduced into SoC design for the establishment of reusing technology and design automation in the uppermost stream region of designing. Activities were conducted in the two fields of (1) research and development of V-core based design technology and (2) research and development of a V-core database. Efforts exerted in field (1) aimed at the research and development of system specifications description technology, architecture generation technology, soft V-core internal structure optimization technology, optimized RTL (register transfer level) description generation technology, and system performance verification technology. In field (2), efforts were made to develop core database technology, core development support tools, core verification technology, and design assets verification technology. The system specifications description technology is a technique to define SoC system level specifications (degree of model abstraction). (NEDO)

  8. Magma Design Automation : Component placement on chips; the "holey cheese" problem

    NARCIS (Netherlands)

    Brouwer, R.; Brouwer, T.; Hurkens, C.A.J.; Manen, van M.; Montijn, C.; Schreuder, J.; Williams, J.F.; Hek, G.M.

    2002-01-01

    The costs of the fabrication of a chip is partly determined by the wire length needed by the transistors to respect the wiring scheme. The transistors have to be placed without overlap into a prescribed configuration of blockades, i.e. parts of the chipthat are beforehand excluded from positioning

  9. On-chip spin-controlled orbital angular momentum directional coupling

    Science.gov (United States)

    Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

    2018-01-01

    Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

  10. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

    NARCIS (Netherlands)

    2008-01-01

    The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) which is provided with at least one semiconductor element, wherein on the surface of the semiconductor body (1) a mesa- shaped semiconductor region (2) is formed, a masking layer (3) is

  11. Advanced Semiconductor Heterostructures Novel Devices, Potential Device Applications and Basic Properties

    CERN Document Server

    Stroscio, Michael A

    2003-01-01

    This volume provides valuable summaries on many aspects of advanced semiconductor heterostructures and highlights the great variety of semiconductor heterostructures that has emerged since their original conception. As exemplified by the chapters in this book, recent progress on advanced semiconductor heterostructures spans a truly remarkable range of scientific fields with an associated diversity of applications. Some of these applications will undoubtedly revolutionize critically important facets of modern technology. At the heart of these advances is the ability to design and control the pr

  12. Description of the SAltro-16 chip for gas detector readout

    CERN Document Server

    Aspell, P; Garcia Garcia, E; de Gaspari, M; Mager, M; Musa, L; Rehman, A; Trampitsch, G

    2010-01-01

    The S-ALTRO prototype chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Its architecture is based in the ALTRO (ALICE TPC Read Out) chip, being its main difference the integration of the charge shaping amplifier in the same IC. Just like ALTRO chip, the prototype architecture and programmability make it suitable for the readout of a wider class of detectors. In one single chip, 16 analogue signals from the detector are shaped, digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate up to 40MHz. After digitisation, a pipelined Data Processor is able to remove from the input signal a wide range of perturbations, related to the non- ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Data Processor is able to suppress the pulse tail within 1�...

  13. Cytostretch, an Organ-on-Chip Platform

    NARCIS (Netherlands)

    Gaio, N.; van Meer, B.; Quiros Solano, W.F.; Bergers, L.; van de Stolpe, A; Mummery, CL; Sarro, P.M.; Dekker, R.

    2016-01-01

    Organ-on-Chips (OOCs) are micro-fabricated devices which are used to culture cells in order to mimic functional units of human organs. The devices are designed to simulate the physiological environment of tissues in vivo. Cells in some types of OOCs can be stimulated in situ by electrical and/or

  14. Detection and classification of ebola on microfluidic chips

    Science.gov (United States)

    Lin, Xue; Jin, Xiangyu; Fan, Yunqian; Huang, Qin; Kou, Yue; Zu, Guo; Huang, Shiguang; Liu, Xiaosheng; Huang, Guoliang

    2016-10-01

    Point-of-care testing (POCT) for an infectious diseases is the prerequisite to control of the disease and limitation of its spread. A microfluidic chip for detection and classification of four strains of Ebola virus was developed and evaluated. This assay was based on reverse transcription loop-mediated isothermal amplification (RT-LAMP) and specific primers for Ebola Zaire virus, Ebola Sudan virus, Ebola Tai Forest virus and Ebola Bundibugyo virus were designed. The sensitivity of the microfluidic chip was under 103 copies per milliliter, as determined by ten repeated tests. This assay is unique in its ability to enable diagnosis of the Ebola infections and simultaneous typing of Ebola virus on a single chip. It offers short reaction time, ease of use and high specificity. These features should enable POCT in remote area during outbreaks of Ebola virus.

  15. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  16. Semiconductor Quantum Electron Wave Transport, Diffraction, and Interference: Analysis, Device, and Measurement.

    Science.gov (United States)

    Henderson, Gregory Newell

    Semiconductor device dimensions are rapidly approaching a fundamental limit where drift-diffusion equations and the depletion approximation are no longer valid. In this regime, quantum effects can dominate device response. To increase further device density and speed, new devices must be designed that use these phenomena to positive advantage. In addition, quantum effects provide opportunities for a new class of devices which can perform functions previously unattainable with "conventional" semiconductor devices. This thesis has described research in the analysis of electron wave effects in semiconductors and the development of methods for the design, fabrication, and characterization of quantum devices based on these effects. First, an exact set of quantitative analogies are presented which allow the use of well understood optical design and analysis tools for the development of electron wave semiconductor devices. Motivated by these analogies, methods are presented for modeling electron wave grating diffraction using both an exact rigorous coupled-wave analysis and approximate analyses which are useful for grating design. Example electron wave grating switch and multiplexer designs are presented. In analogy to thin-film optics, the design and analysis of electron wave Fabry-Perot interference filters are also discussed. An innovative technique has been developed for testing these (and other) electron wave structures using Ballistic Electron Emission Microscopy (BEEM). This technique uses a liquid-helium temperature scanning tunneling microscope (STM) to perform spectroscopy of the electron transmittance as a function of electron energy. Experimental results show that BEEM can resolve even weak quantum effects, such as the reflectivity of a single interface between materials. Finally, methods are discussed for incorporating asymmetric electron wave Fabry-Perot filters into optoelectronic devices. Theoretical and experimental results show that such structures could

  17. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    Science.gov (United States)

    Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

    2012-01-01

    A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

  18. Spherical distribution structure of the semiconductor laser diode stack for pumping

    International Nuclear Information System (INIS)

    Zhao Tianzhuo; Yu Jin; Liu Yang; Zhang Xue; Ma Yunfeng; Fan Zhongwei

    2011-01-01

    A semiconductor laser diode stack is used for pumping and 8 semiconductor laser diode arrays of the stack are put on a sphere, and the output of every bar is specially off-axis compressed to realize high coupling efficiency. The output beam of this semiconductor laser diode stack is shaped by a hollow duct to the laser active medium. The efficiency of the hollow light pipe, which is used for semiconductor laser diode stack coupling, is analyzed by geometric optics and ray tracing. Geometric optics analysis diagnoses the reasons for coupling loss and guides the design of the structure. Ray tracing analyzes the relation between the structural parameters and the output characteristics of this pumping system, and guides parameter optimization. Simulation and analysis results show that putting the semiconductor laser diode arrays on a spherical surface can increase coupling efficiency, reduce the optimum duct length and improve the output energy field distribution. (semiconductor devices)

  19. Applications of nuclear microprobes in the semiconductor industry

    International Nuclear Information System (INIS)

    Takai, M.

    1996-01-01

    Possible nuclear microprobe applications in semiconductor industries are discussed. A unique technique using soft-error mapping and ion beam induced current measurements for reliability testing of dynamic random access memories such as soft-error immunity and noise carrier suppression has been developed for obtaining design parameters of future memory devices. Nano-probes and small installation areas are required for the use of microprobes in the semiconductor industry. Issues arising from microprobe applications such as damage induced by the probe beam are clarified. (orig.)

  20. Contacts to semiconductors

    International Nuclear Information System (INIS)

    Tove, P.A.

    1975-08-01

    Contacts to semiconductors play an important role in most semiconductor devices. These devices range from microelectronics to power components, from high-sensitivity light or radiation detectors to light-emitting of microwave-generating components. Silicon is the dominating material but compound semiconductors are increasing in importance. The following survey is an attempt to classify contact properties and the physical mechanisms involved, as well as fabrication methods and methods of investigation. The main interest is in metal-semiconductor type contacts where a few basic concepts are dealt with in some detail. (Auth.)

  1. Low-confinement high-power semiconductor lasers

    NARCIS (Netherlands)

    Buda, M.

    1999-01-01

    This thesis presents the results of studies related to optimisation of high power semiconductor laser diodes using the low confinement concept. This implies a different approach in designing the transversal layer structure before growth and in processing the wafer after growth, for providing the

  2. On-chip micro-power: three-dimensional structures for micro-batteries and micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Wang, Chunlei

    2010-04-01

    With the miniaturization of portable electronic devices, there is a demand for micro-power source which can be integrated on the semiconductor chips. Various micro-batteries have been developed in recent years to generate or store the energy that is needed by microsystems. Micro-supercapacitors are also developed recently to couple with microbatteries and energy harvesting microsystems and provide the peak power. Increasing the capacity per footprint area of micro-batteries and micro-supercapacitors is a great challenge. One promising route is the manufacturing of three dimensional (3D) structures for these micro-devices. In this paper, the recent advances in fabrication of 3D structure for micro-batteries and micro-supercapacitors are briefly reviewed.

  3. Soft X-ray spectromicroscopy and application to semiconductor microstructure characterization

    International Nuclear Information System (INIS)

    Gozzo, F.; Franck, K.; Howells, M.R.; Hussain, Z.; Warwick, A.; Padmore, H.A.; Triplett, B.B.

    1997-01-01

    The universal trend towards device miniaturization has driven the semiconductor industry to develop sophisticated and complex instrumentation for the characterization of microstructures. Many significant problems of relevance to the semiconductor industry cannot be solved by conventional analysis techniques, but can be addressed with soft x-ray spectromicroscopy. An active spectromicroscopy program is being developed at thr Advanced Light Source, attracting both the semiconductor industry and the materials science academic community. Examples of spectromicroscopy techniques are presented. An Advanced Light Source μ-XPS spectromicroscopy project is discussed, involving the first microscope completely dedicated and designed for microstructure analysis on patterned silicon wafers. (author)

  4. Design of Semiconductor-Based Back Reflectors for High Voc Monolithic Multijunction Solar Cells: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Garcia, I.; Geisz, J.; Steiner, M.; Olson, J.; Friedman, D.; Kurtz, S.

    2012-06-01

    State-of-the-art multijunction cell designs have the potential for significant improvement before going to higher number of junctions. For example, the Voc can be substantially increased if the photon recycling taking place in the junctions is enhanced. This has already been demonstrated (by Alta Devices) for a GaAs single-junction cell. For this, the loss of re-emitted photons by absorption in the underlying layers or substrate must be minimized. Selective back surface reflectors are needed for this purpose. In this work, different architectures of semiconductor distributed Bragg reflectors (DBR) are assessed as the appropriate choice for application in monolithic multijunction solar cells. Since the photon re-emission in the photon recycling process is spatially isotropic, the effect of the incident angle on the reflectance spectrum is of central importance. In addition, the DBR structure must be designed taking into account its integration into the monolithic multijunction solar cells, concerning series resistance, growth economics, and other issues. We analyze the tradeoffs in DBR design complexity with all these requirements to determine if such a reflector is suitable to improve multijunction solar cells.

  5. Semiconductor spintronics

    International Nuclear Information System (INIS)

    Fabian, J.; Abiague, A.M.; Ertler, Ch.; Stano, P.; Zutic, I.

    2007-01-01

    Spintronics refers commonly to phenomena in which the spin of electrons in a solid state environment plays the determining role. In a more narrow sense spintronics is an emerging research field of electronics: spintronics devices are based on a spin control of electronics, or on an electrical and optical control of spin of magnetism. While metal spintronics has already found its niche in the computer industry - giant magnetoresistance systems are used as hard disk read heads - semiconductor spintronics is vet demonstrate its full potential. This review presents selected themes of semiconductor spintronics, introducing important concepts in spin transport, spin transport, spin injection. Silsbee-Johnson spin-charge coupling, and spin-dependent tunneling, as well as spin relaxation and spin dynamics. The most fundamental spin-dependent interaction in nonmagnetic semiconductors is spin-orbit coupling. Depending on the crystal symmetries of the material, as well as on the structural properties of semiconductor based heterostructures, the spin-orbit coupling takes on different functional forms, giving a nice playground of effective spin-orbit Hamiltonians. The effective Hamiltonians for the most relevant classes of materials and heterostructures are derived here from realistic electronic band structure descriptions. Most semiconductor device systems are still theoretical concepts, waiting for experimental demonstrations. A review of selected proposed, and a few demonstrated devices is presented, with detailed description of two important classes: magnetic resonant tunnel structures and bipolar magnetic diodes and transistors. In view of the importance of ferromagnetic semiconductor material, a brief discussion of diluted magnetic semiconductors is included. In most cases the presentation is of tutorial style, introducing the essential theoretical formalism at an accessible level, with case-study-like illustrations of actual experimental results, as well as with brief

  6. Method of manufacturing a semiconductor sensor device and semiconductor sensor device

    NARCIS (Netherlands)

    2009-01-01

    The invention relates to a method of manufacturing a semiconductor sensor device (10) for sensing a substance comprising a plurality of mutually parallel mesa-shaped semiconductor regions (1) which are formed on a surface of a semiconductor body (11) and which are connected at a first end to a first

  7. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    2018-02-02

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  8. The ATLAS semiconductor tracker (SCT)

    International Nuclear Information System (INIS)

    Jackson, J.N.

    2005-01-01

    The ATLAS detector (CERN,LHCC,94-43 (1994)) is designed to study a wide range of physics at the CERN Large Hadron Collider (LHC) at luminosities up to 10 34 cm -2 s -1 with a bunch-crossing rate of 40 MHz. The Semiconductor Tracker (SCT) forms a key component of the Inner Detector (vol. 1, ATLAS TDR 4, CERN,LHCC 97-16 (1997); vol. 2, ATLAS TDR 5, CERN,LHCC 97-17 (1997)) which is situated inside a 2 T solenoid field. The ATLAS Semiconductor Tracker (SCT) utilises 4088 silicon modules with binary readout mounted on carbon fibre composite structures arranged in the forms of barrels in the central region and discs in the forward region. The construction of the SCT is now well advanced. The design of the SCT modules, services and support structures will be briefly outlined. A description of the various stages in the construction process will be presented with examples of the performance achieved and the main difficulties encountered. Finally, the current status of the construction is reviewed

  9. A 16X16 Discrete Cosine Transform Chip

    Science.gov (United States)

    Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

    1987-10-01

    Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

  10. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  11. Design of a DNA chip for detection of unknown genetically modified organisms (GMOs).

    Science.gov (United States)

    Nesvold, Håvard; Kristoffersen, Anja Bråthen; Holst-Jensen, Arne; Berdal, Knut G

    2005-05-01

    Unknown genetically modified organisms (GMOs) have not undergone a risk evaluation, and hence might pose a danger to health and environment. There are, today, no methods for detecting unknown GMOs. In this paper we propose a novel method intended as a first step in an approach for detecting unknown genetically modified (GM) material in a single plant. A model is designed where biological and combinatorial reduction rules are applied to a set of DNA chip probes containing all possible sequences of uniform length n, creating probes capable of detecting unknown GMOs. The model is theoretically tested for Arabidopsis thaliana Columbia, and the probabilities for detecting inserts and receiving false positives are assessed for various parameters for this organism. From a theoretical standpoint, the model looks very promising but should be tested further in the laboratory. The model and algorithms will be available upon request to the corresponding author.

  12. Controlled Quantum Operations of a Semiconductor Three-Qubit System

    Science.gov (United States)

    Li, Hai-Ou; Cao, Gang; Yu, Guo-Dong; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

    2018-02-01

    In a specially designed semiconductor device consisting of three capacitively coupled double quantum dots, we achieve strong and tunable coupling between a target qubit and two control qubits. We demonstrate how to completely switch on and off the target qubit's coherent rotations by presetting two control qubits' states. A Toffoli gate is, therefore, possible based on these control effects. This research paves a way for realizing full quantum-logic operations in semiconductor multiqubit systems.

  13. Optimal design of advanced distillation configuration for enhanced energy efficiency of waste solvent recovery process in semiconductor industry

    International Nuclear Information System (INIS)

    Chaniago, Yus Donald; Minh, Le Quang; Khan, Mohd Shariq; Koo, Kee-Kahb; Bahadori, Alireza; Lee, Moonyong

    2015-01-01

    Highlights: • Thermally coupled distillation process is proposed for waste solvent recovery. • A systematic optimization procedure is used to optimize distillation columns. • Response surface methodology is applied to optimal design of distillation column. • Proposed advanced distillation allows energy efficient waste solvent recovery. - Abstract: The semiconductor industry is one of the largest industries in the world. On the other hand, the huge amount of solvent used in the industry results in high production cost and potential environmental damage because most of the valuable chemicals discharged from the process are incinerated at high temperatures. A distillation process is used to recover waste solvent, reduce the production-related costs and protect the environment from the semiconductor industrial waste. Therefore, in this study, a distillation process was used to recover the valuable chemicals from semiconductor industry discharge, which otherwise would have been lost to the environment. The conventional sequence of distillation columns, which was optimized using the Box and sequential quadratic programming method for minimum energy objectives, was used. The energy demands of a distillation problem may have a substantial influence on the profitability of a process. A thermally coupled distillation and heat pump-assisted distillation sequence was implemented to further improve the distillation performance. Finally, a comparison was made between the conventional and advanced distillation sequences, and the optimal conditions for enhancing recovery were determined. The proposed advanced distillation configuration achieved a significant energy saving of 40.5% compared to the conventional column sequence

  14. Metal-core/semiconductor-shell nanocones for broadband solar absorption enhancement.

    Science.gov (United States)

    Zhou, Lin; Yu, Xiaoqiang; Zhu, Jia

    2014-02-12

    Nanostructure-based photovoltaic devices have exhibited several advantages, such as reduced reflection, extraordinary light trapping, and so forth. In particular, semiconductor nanostructures provide optical modes that have strong dependence on the size and geometry. Metallic nanostructures also attract a lot of attention because of the appealing plasmonic effect on the near-field enhancement. In this study, we propose a novel design, the metal-core/semiconductor-shell nanocones with the core radius varying in a linearly gradient style. With a thin layer of semiconductor absorber coated on a metallic cone, such a design can lead to significant and broadband absorption enhancement across the entire visible and near-infrared solar spectrum. As an example of demonstration, a layer of 16 nm thick crystalline silicon (c-Si) coated on a silver nanocone can absorb 27% of standard solar radiation across a broad spectral range of 300-1100 nm, which is equivalent to a 700 nm thick flat c-Si film. Therefore, the absorption enhancement factor approaching the Yablonovitch limit is achieved with this design. The significant absorption enhancement can be ascribed to three types of optical modes, that is, Fabry-Perot modes, plasmonic modes, and hybrid modes that combine the features of the previous two. In addition, the unique nanocone geometry enables the linearly gradient radius of the semiconductor shell, which can support multiple optical resonances, critical for the broadband absorption. Our design may find general usage as elements for the low cost, high efficiency solar conversion and water-splitting devices.

  15. A prototype pixel readout chip for asynchronous detection applications

    International Nuclear Information System (INIS)

    Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

    1991-01-01

    A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

  16. Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

    Science.gov (United States)

    Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

    2013-06-21

    We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

  17. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    Directory of Open Access Journals (Sweden)

    Chih-Ting Lin

    2012-08-01

    Full Text Available A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

  18. n-Type organic semiconductors in organic electronics.

    Science.gov (United States)

    Anthony, John E; Facchetti, Antonio; Heeney, Martin; Marder, Seth R; Zhan, Xiaowei

    2010-09-08

    Organic semiconductors have been the subject of intensive academic and commercial interest over the past two decades, and successful commercial devices incorporating them are slowly beginning to enter the market. Much of the focus has been on the development of hole transporting, or p-type, semiconductors that have seen a dramatic rise in performance over the last decade. Much less attention has been devoted to electron transporting, or so called n-type, materials, and in this paper we focus upon recent developments in several classes of n-type materials and the design guidelines used to develop them.

  19. Semiconductor laser shearing interferometer

    International Nuclear Information System (INIS)

    Ming Hai; Li Ming; Chen Nong; Xie Jiaping

    1988-03-01

    The application of semiconductor laser on grating shearing interferometry is studied experimentally in the present paper. The method measuring the coherence of semiconductor laser beam by ion etching double frequency grating is proposed. The experimental result of lens aberration with semiconductor laser shearing interferometer is given. Talbot shearing interferometry of semiconductor laser is also described. (author). 2 refs, 9 figs

  20. Functionalization and Characterization of Nanomaterial Gated Field-Effect Transistor-Based Biosensors and the Design of a Multi-Analyte Implantable Biosensing Platform

    Science.gov (United States)

    Croce, Robert A., Jr.

    Advances in semiconductor research and complementary-metal-oxide semiconductor fabrication allow for the design and implementation of miniaturized metabolic monitoring systems, as well as advanced biosensor design. The first part of this dissertation will focus on the design and fabrication of nanomaterial (single-walled carbon nanotube and quantum dot) gated field-effect transistors configured as protein sensors. These novel device structures have been functionalized with single-stranded DNA aptamers, and have shown sensor operation towards the protein Thrombin. Such advanced transistor-based sensing schemes present considerable advantages over traditional sensing methodologies in view of its miniaturization, low cost, and facile fabrication, paving the way for the ultimate realization of a multi-analyte lab-on-chip. The second part of this dissertation focuses on the design and fabrication of a needle-implantable glucose sensing platform which is based solely on photovoltaic powering and optical communication. By employing these powering and communication schemes, this design negates the need for bulky on-chip RF-based transmitters and batteries in an effort to attain extreme miniaturization required for needle-implantable/extractable applications. A complete single-sensor system coupled with a miniaturized amperometric glucose sensor has been demonstrated to exhibit reality of this technology. Furthermore, an optical selection scheme of multiple potentiostats for four different analytes (glucose, lactate, O 2 and CO2) as well as the optical transmission of sensor data has been designed for multi-analyte applications. The last part of this dissertation will focus on the development of a computational model for the amperometric glucose sensors employed in the aforementioned implantable platform. This model has been applied to single-layer single-enzyme systems, as well as multi-layer (single enzyme) systems utilizing glucose flux limiting layer-by-layer assembled

  1. Temperature control of power semiconductor devices in traction applications

    Science.gov (United States)

    Pugachev, A. A.; Strekalov, N. N.

    2017-02-01

    The peculiarity of thermal management of traction frequency converters of a railway rolling stock is highlighted. The topology and the operation principle of the automatic temperature control system of power semiconductor modules of the traction frequency converter are designed and discussed. The features of semiconductors as an object of temperature control are considered; the equivalent circuit of thermal processes in the semiconductors is suggested, the power losses in the two-level voltage source inverters are evaluated and analyzed. The dynamic properties and characteristics of the cooling fan induction motor electric drive with the scalar control are presented. The results of simulation in Matlab are shown for the steady state of thermal processes.

  2. On-chip enucleation of an oocyte by untethered microrobots

    International Nuclear Information System (INIS)

    Ichikawa, Akihiko; Sakuma, Shinya; Sugita, Masakuni; Shoda, Tatsuro; Tamakoshi, Takahiro; Arai, Fumihito; Akagi, Satoshi

    2014-01-01

    We propose a novel on-chip enucleation of an oocyte with zona pellucida by using a combination of untethered microrobots. To achieve enucleation within the closed space of a microfluidic chip, two microrobots, a microknife and a microgripper were integrated into the microfluidic chip. These microrobots were actuated by an external magnetic force produced by permanent magnets placed on the robotic stage. The tip of the microknife was designed by considering the biological geometric feature of an oocyte, i.e. the oocyte has a polar body in maturation stage II. Moreover, the microknife was fabricated by using grayscale lithography, which allows fabrication of three-dimensional microstructures. The microgripper has a gripping function that is independent of the driving mechanism. On-chip enucleation was demonstrated, and the enucleated oocytes are spherical, indicating that the cell membrane of the oocytes remained intact. To confirm successful enucleation using this method, we investigated the viability of oocytes after enucleation. The results show that the production rate, i.e. the ratio between the number of oocytes that reach the blastocyst stage and the number of bovine oocytes after nucleus transfer, is 100%. The technique will contribute to complex cell manipulation such as cell surgery in lab-on-a-chip devices. (paper)

  3. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  4. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  5. "Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

    Directory of Open Access Journals (Sweden)

    Krohn Knut

    2008-08-01

    Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

  6. Electro-mechanical control of an on-chip optical beam splitter containing an embedded quantum emitter.

    Science.gov (United States)

    Bishop, Z K; Foster, A P; Royall, B; Bentham, C; Clarke, E; Skolnick, M S; Wilson, L R

    2018-05-01

    We demonstrate electro-mechanical control of an on-chip GaAs optical beam splitter containing a quantum dot single-photon source. The beam splitter consists of two nanobeam waveguides, which form a directional coupler (DC). The splitting ratio of the DC is controlled by varying the out-of-plane separation of the two waveguides using electromechanical actuation. We reversibly tune the beam splitter between an initial state, with emission into both output arms, and a final state with photons emitted into a single output arm. The device represents a compact and scalable tuning approach for use in III-V semiconductor integrated quantum optical circuits.

  7. Electro-mechanical control of an on-chip optical beam splitter containing an embedded quantum emitter

    Science.gov (United States)

    Bishop, Z. K.; Foster, A. P.; Royall, B.; Bentham, C.; Clarke, E.; Skolnick, M. S.; Wilson, L. R.

    2018-05-01

    We demonstrate electro-mechanical control of an on-chip GaAs optical beam splitter containing a quantum dot single-photon source. The beam splitter consists of two nanobeam waveguides, which form a directional coupler (DC). The splitting ratio of the DC is controlled by varying the out-of-plane separation of the two waveguides using electro-mechanical actuation. We reversibly tune the beam splitter between an initial state, with emission into both output arms, and a final state with photons emitted into a single output arm. The device represents a compact and scalable tuning approach for use in III-V semiconductor integrated quantum optical circuits.

  8. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  9. Second-Generation Design of Micro-Spec: A Medium-Resolution, Submillimeter-Wavelength Spectrometer-on-a-Chip

    Science.gov (United States)

    Cataldo, G.; Barrentine, E. M.; Bulcha, B. T.; Ehsan, N.; Hess, L. A.; Noroozian, O.; Stevenson, T. R.; U-Yen, K.; Wollack, E. J.; Moseley, S. H.

    2018-04-01

    Micro-Spec (µ-Spec) is a direct-detection spectrometer which integrates all the components of a diffraction-grating spectrometer onto a ˜ 10-cm^2 chip through the use of superconducting microstrip transmission lines on a single-crystal silicon substrate. A second-generation µ-Spec is being designed to operate with a spectral resolution of 512 in the submillimeter (500-1000 µm, 300-600 GHz) wavelength range, a band of interest for several spectroscopic applications in astrophysics. High-altitude balloon missions would provide the first test bed to demonstrate the µ-Spec technology in a space-like environment and would be an economically viable venue for multiple observation campaigns. This work reports on the current status of the instrument design and will provide a brief overview of each instrument subsystem. Particular emphasis will be given to the design of the spectrometer's two-dimensional diffractive region, through which the light of different wavelengths is focused on the detectors along the focal plane. An optimization process is employed to generate geometrical configurations of the diffractive region that satisfy specific requirements on spectrometer size, operating spectral range, and performance. An optical design optimized for balloon missions will be presented in terms of geometric layout, spectral purity, and efficiency.

  10. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuelian [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Zang, Jianfeng [Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC 27708 (United States); Liu, Yingshuai; Lu, Zhisong [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); Li, Qing, E-mail: Qli@swu.edu.cn [School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Li, Chang Ming, E-mail: ecmli@swu.edu.cn [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China)

    2013-04-10

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

  11. Characterization of semiconductor and frontier materials by nuclear microprobe technology

    International Nuclear Information System (INIS)

    Zhu Jieqing; Li Xiaolin; Yang Changyi; Lu Rongrong; Wang Jiqing; Guo Panlin

    2002-01-01

    The nuclear microprobe technology is used to characterize the properties of semiconductor and other frontier materials at the stages of their synthesis, modification, integration and application. On the basis of the beam current being used, the analytical nuclear microprobe techniques being used in this project can be divided into two categories: high beam current (PIXE, RBS, PEB) or low beam current (IBIC, STIM) techniques. The material properties measured are the thickness and composition of a composite surface on a SiC ceramic, the sputtering-induced surface segregation and depth profile change in a Ag-Cu binary alloy, the irradiation effects on the CCE of CVD diamond, the CCE profile at a polycrystalline CVD diamond film and a GaAs diode at different voltage biases and finally, the characterization of individual sample on an integrated material chip. (author)

  12. Variable-Width Datapath for On-Chip Network Static Power Reduction

    Energy Technology Data Exchange (ETDEWEB)

    Michelogiannakis, George; Shalf, John

    2013-11-13

    With the tight power budgets in modern large-scale chips and the unpredictability of application traffic, on-chip network designers are faced with the dilemma of designing for worst- case bandwidth demands and incurring high static power overheads, or designing for an average traffic pattern and risk degrading performance. This paper proposes adaptive bandwidth networks (ABNs) which divide channels and switches into lanes such that the network provides just the bandwidth necessary in each hop. ABNs also activate input virtual channels (VCs) individually and take advantage of drowsy SRAM cells to eliminate false VC activations. In addition, ABNs readily apply to silicon defect tolerance with just the extra cost for detecting faults. For application traffic, ABNs reduce total power consumption by an average of 45percent with comparable performance compared to single-lane power-gated networks, and 33percent compared to multi-network designs.

  13. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  14. Mixed-signal early vision chip with embedded image and programming memories and digital I/O

    Science.gov (United States)

    Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

    2003-04-01

    From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

  15. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  16. Ultrasensitive NO2 gas sensors using hybrid heterojunctions of multi-walled carbon nanotubes and on-chip grown SnO2 nanowires

    Science.gov (United States)

    Nguyet, Quan Thi Minh; Van Duy, Nguyen; Manh Hung, Chu; Hoa, Nguyen Duc; Van Hieu, Nguyen

    2018-04-01

    Hybrid heterojunction devices are designed for ultrahigh response to NO2 toxic gas. The devices were constructed by assembling multi-walled carbon nanotubes (MWCNTs) on a microelectrode chip bridged bare Pt-electrode and a Pt-electrode with pre-grown SnO2 nanowires (NWs). All heterojunction devices were realized using different types of MWCNTs, which exhibit ultrahigh response to sub-ppm NO2 gas at 50 °C operated in the reverse bias mode. The response to 1 ppm NO2 gas reaches 11300, which is about 100 times higher than that of a back-to-back heterojunction device fabricated from SnO2 NWs and MWCNTs. In addition, the present device exhibits an ultralow detection limit of about 0.68 ppt. The modulation of trap-assisted tunneling current under reverse bias is the main gas-sensing mechanism. This principle device presents a concept for developing gas sensors made of a hybrid between semiconductor metal oxide NWs and CNTs.

  17. Design and Implementation of 8051 Single-Chip Microcontroller for Stationary 1.0 kW PEM Fuel Cell System

    Directory of Open Access Journals (Sweden)

    Pei-Hsing Huang

    2014-01-01

    Full Text Available Proton exchange membrane fuel cells (PEMFCs have attracted significant interest as a potential green energy source. However, if the performance of such systems is to be enhanced, appropriate control strategies must be applied. Accordingly, the present study proposes a sophisticated control system for a 1.0 kW PEMFC system comprising a fuel cell stack, an auxiliary power supply, a DC-DC buck converter, and a DC-AC inverter. The control system is implemented using an 8051 single-chip microcontroller and is designed to optimize the system performance and safety in both the startup phase and the long-term operation phase. The major features of the proposed control system are described and the circuit diagrams required for its implementation introduced. In addition, the touch-sensitive, intuitive human-machine interface is introduced and typical screens are presented. Finally, the electrical characteristics of the PEMFC system are briefly examined. Overall, the results confirm that the single-chip microcontroller presented in this study has significant potential for commercialization in the near future.

  18. Crossing the Resolution Limit in Near-Infrared Imaging of Silicon Chips: Targeting 10-nm Node Technology

    Directory of Open Access Journals (Sweden)

    Krishna Agarwal

    2015-05-01

    Full Text Available The best reported resolution in optical failure analysis of silicon chips is 120-nm half pitch demonstrated by Semicaps Private Limited, whereas the current and future industry requirement for 10-nm node technology is 100-nm half pitch. We show the first experimental evidence for resolution of features with 100-nm half pitch buried in silicon (λ/10.6, thus fulfilling the industry requirement. These results are obtained using near-infrared reflection-mode imaging using a solid immersion lens. The key novel feature of our approach is the choice of an appropriately sized collection pinhole. Although it is usually understood that, in general, resolution is improved by using the smallest pinhole consistent with an adequate signal level, it is found that in practice for silicon chips there is an optimum pinhole size, determined by the generation of induced currents in the sample. In failure analysis of silicon chips, nondestructive imaging is important to avoid disturbing the functionality of integrated circuits. High-resolution imaging techniques like SEM or TEM require the transistors to be exposed destructively. Optical microscopy techniques may be used, but silicon is opaque in the visible spectrum, mandating the use of near-infrared light and thus poor resolution in conventional optical microscopy. We expect our result to change the way semiconductor failure analysis is performed.

  19. Interfacing Lab-on-a-Chip Embryo Technology with High-Definition Imaging Cytometry.

    Science.gov (United States)

    Zhu, Feng; Hall, Christopher J; Crosier, Philip S; Wlodkowic, Donald

    2015-08-01

    To spearhead deployment of zebrafish embryo biotests in large-scale drug discovery studies, automated platforms are needed to integrate embryo in-test positioning and immobilization (suitable for high-content imaging) with fluidic modules for continuous drug and medium delivery under microperfusion to developing embryos. In this work, we present an innovative design of a high-throughput three-dimensional (3D) microfluidic chip-based device for automated immobilization and culture and time-lapse imaging of developing zebrafish embryos under continuous microperfusion. The 3D Lab-on-a-Chip array was fabricated in poly(methyl methacrylate) (PMMA) transparent thermoplastic using infrared laser micromachining, while the off-chip interfaces were fabricated using additive manufacturing processes (fused deposition modelling and stereolithography). The system's design facilitated rapid loading and immobilization of a large number of embryos in predefined clusters of traps during continuous microperfusion of drugs/toxins. It was conceptually designed to seamlessly interface with both upright and inverted fluorescent imaging systems and also to directly interface with conventional microtiter plate readers that accept 96-well plates. Compared with the conventional Petri dish assays, the chip-based bioassay was much more convenient and efficient as only small amounts of drug solutions were required for the whole perfusion system running continuously over 72 h. Embryos were spatially separated in the traps that assisted tracing single embryos, preventing interembryo contamination and improving imaging accessibility.

  20. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

    Science.gov (United States)

    Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

    2018-04-01

    Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

  1. Simulation and Performance Test Technology Development for Semiconductor Radiation Detection Instrument Fabrication

    International Nuclear Information System (INIS)

    Kim, Jong Kyung; Lee, W. G.; Kim, S. Y.; Shin, C. H.; Kim, K. O.; Park, J. M.; Jang, D. Y.; Kang, J. S.

    2010-06-01

    - Analysis on the Absorbed Dose and Electron Generation by Using MCNPX Code - Analysis on the Change of Measured Energy Spectrum As a Function of Bias Voltage Applied in Semiconductor Detector - Comparison of Monte Carlo Simulation Considering the Charge Collection Efficiency and Experimental Result - Development of Semiconductor Sensor Design Code Based on the Graphic User Interface - Analysis on Depth Profile of Ion-implanted Semiconductor Wafer Surface and Naturally Generated SiO2 Insulation Layer Using Auger Electron Spectroscopy - Measurement of AFM Images and Roughness to Abalyze Surface of Semiconductor Wafer with respect to Annealing and Cleaning Process - Measurement of Physical Properties for Semiconductor Detector Surface after CZT Passivation Process - Evaluation of Crystal Structure and Specific Resistance of CZT - Measurement/Analysis on Band Structure of CZT Crystal - Evaluation of Neutron Convertor Layer with respect to Change in Temperature - Measurement/Evaluation of physical characteristics for lattice parameter, specific resistance, and band structure of CZT crystal - Measurement/Evaluation of lattice transition of SiC semiconductor detector after radiation irradiation - Measurement/Evaluation of performance of semiconductor detector with respect to exposure in high temperature environment

  2. The simulation of air recirculation and fire/explosion phenomena within a semiconductor factory

    International Nuclear Information System (INIS)

    I, Yet-Pole; Chiu, Y.-L.; Wu, S.-J.

    2009-01-01

    The semiconductor industry is the collection of capital-intensive firms that employ a variety of hazardous chemicals and engage in the design and fabrication of semiconductor devices. Owing to its processing characteristics, the fully confined structure of the fabrication area (fab) and the vertical airflow ventilation design restrict the applications of traditional consequence analysis techniques that are commonly used in other industries. The adverse situation also limits the advancement of a fire/explosion prevention design for the industry. In this research, a realistic model of a semiconductor factory with a fab, sub-fabrication area, supply air plenum, and return air plenum structures was constructed and the computational fluid dynamics algorithm was employed to simulate the possible fire/explosion range and its severity. The semiconductor factory has fan module units with high efficiency particulate air filters that can keep the airflow uniform within the cleanroom. This condition was modeled by 25 fans, three layers of porous ceiling, and one layer of porous floor. The obtained results predicted very well the real airflow pattern in the semiconductor factory. Different released gases, leak locations, and leak rates were applied to investigate their influence on the hazard range and severity. Common mitigation measures such as a water spray system and a pressure relief panel were also provided to study their potential effectiveness to relieve thermal radiation and overpressure hazards within a fab. The semiconductor industry can use this simulation procedure as a reference on how to implement a consequence analysis for a flammable gas release accident within an air recirculation cleanroom

  3. Monolithic Inorganic ZnO/GaN Semiconductors Heterojunction White Light-Emitting Diodes.

    Science.gov (United States)

    Jeong, Seonghoon; Oh, Seung Kyu; Ryou, Jae-Hyun; Ahn, Kwang-Soon; Song, Keun Man; Kim, Hyunsoo

    2018-01-31

    Monolithic light-emitting diodes (LEDs) that can generate white color at the one-chip level without the wavelength conversion through packaged phosphors or chip integration for photon recycling are of particular importance to produce compact, cost-competitive, and smart lighting sources. In this study, monolithic white LEDs were developed based on ZnO/GaN semiconductor heterojunctions. The electroluminescence (EL) wavelength of the ZnO/GaN heterojunction could be tuned by a post-thermal annealing process, causing the generation of an interfacial Ga 2 O 3 layer. Ultraviolet, violet-bluish, and greenish-yellow broad bands were observed from n-ZnO/p-GaN without an interfacial layer, whereas a strong greenish-yellow band emission was the only one observed from that with an interfacial layer. By controlled integration of ZnO/GaN heterojunctions with different postannealing conditions, monolithic white LED was demonstrated with color coordinates in the range (0.3534, 0.3710)-(0.4197, 0.4080) and color temperatures of 4778-3349 K in the Commission Internationale de l'Eclairage 1931 chromaticity diagram. Furthermore, the monolithic white LED produced approximately 2.1 times higher optical output power than a conventional ZnO/GaN heterojunction due to the carrier confinement effect at the Ga 2 O 3 /n-ZnO interface.

  4. NEPP Evaluation of Automotive Grade Tantalum Chip Capacitors

    Science.gov (United States)

    Sampson, Mike; Brusse, Jay

    2018-01-01

    Automotive grade tantalum (Ta) chip capacitors are available at lower cost with smaller physical size and higher volumetric efficiency compared to military/space grade capacitors. Designers of high reliability aerospace and military systems would like to take advantage of these attributes while maintaining the high standards for long-term reliable operation they are accustomed to when selecting military-qualified established reliability tantalum chip capacitors (e.g., MIL-PRF-55365). The objective for this evaluation was to assess the long-term performance of off-the-shelf automotive grade Ta chip capacitors (i.e., manufacturer self-qualified per AEC Q-200). Two (2) lots of case size D manganese dioxide (MnO2) cathode Ta chip capacitors from 1 manufacturer were evaluated. The evaluation consisted of construction analysis, basic electrical parameter characterization, extended long-term (2000 hours) life testing and some accelerated stress testing. Tests and acceptance criteria were based upon manufacturer datasheets and the Automotive Electronics Council's AEC Q-200 qualification specification for passive electronic components. As-received a few capacitors were marginally above the specified tolerance for capacitance and ESR. X-ray inspection found that the anodes for some devices may not be properly aligned within the molded encapsulation leaving less than 1 mil thickness of the encapsulation. This evaluation found that the long-term life performance of automotive grade Ta chip capacitors is generally within specification limits suggesting these capacitors may be suitable for some space applications.

  5. The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

    Science.gov (United States)

    Nikolova, Silviya; Stearns, Sally

    2014-03-03

    Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

  6. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  7. Electronic properties of semiconductor heterostructures

    International Nuclear Information System (INIS)

    Einevoll, G.T.

    1991-02-01

    Ten papers on the electronic properties of semiconductors and semiconductor heterostructures constitute the backbone of this thesis. Four papers address the form and validity of the single-band effective mass approximation for semiconductor heterostructures. In four other papers properties of acceptor states in bulk semiconductors and semiconductor heterostructures are studied using the novel effective bond-orbital model. The last two papers deal with localized excitions. 122 refs

  8. Organic semiconductor crystals.

    Science.gov (United States)

    Wang, Chengliang; Dong, Huanli; Jiang, Lang; Hu, Wenping

    2018-01-22

    Organic semiconductors have attracted a lot of attention since the discovery of highly doped conductive polymers, due to the potential application in field-effect transistors (OFETs), light-emitting diodes (OLEDs) and photovoltaic cells (OPVs). Single crystals of organic semiconductors are particularly intriguing because they are free of grain boundaries and have long-range periodic order as well as minimal traps and defects. Hence, organic semiconductor crystals provide a powerful tool for revealing the intrinsic properties, examining the structure-property relationships, demonstrating the important factors for high performance devices and uncovering fundamental physics in organic semiconductors. This review provides a comprehensive overview of the molecular packing, morphology and charge transport features of organic semiconductor crystals, the control of crystallization for achieving high quality crystals and the device physics in the three main applications. We hope that this comprehensive summary can give a clear picture of the state-of-art status and guide future work in this area.

  9. Extracting hot carriers from photoexcited semiconductor nanocrystals

    Energy Technology Data Exchange (ETDEWEB)

    Zhu, Xiaoyang

    2014-12-10

    This research program addresses a fundamental question related to the use of nanomaterials in solar energy -- namely, whether semiconductor nanocrystals (NCs) can help surpass the efficiency limits, the so-called “Shockley-Queisser” limit, in conventional solar cells. In these cells, absorption of photons with energies above the semiconductor bandgap generates “hot” charge carriers that quickly “cool” to the band edges before they can be utilized to do work; this sets the solar cell efficiency at a limit of ~31%. If instead, all of the energy of the hot carriers could be captured, solar-to-electric power conversion efficiencies could be increased, theoretically, to as high as 66%. A potential route to capture this energy is to utilize semiconductor nanocrystals. In these materials, the quasi-continuous conduction and valence bands of the bulk semiconductor become discretized due to confinement of the charge carriers. Consequently, the energy spacing between the electronic levels can be much larger than the highest phonon frequency of the lattice, creating a “phonon bottleneck” wherein hot-carrier relaxation is possible via slower multiphonon emission. For example, hot-electron lifetimes as long as ~1 ns have been observed in NCs grown by molecular beam epitaxy. In colloidal NCs, long lifetimes have been demonstrated through careful design of the nanocrystal interfaces. Due to their ability to slow electronic relaxation, semiconductor NCs can in principle enable extraction of hot carriers before they cool to the band edges, leading to more efficient solar cells.

  10. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  11. Compound semiconductor device modelling

    CERN Document Server

    Miles, Robert

    1993-01-01

    Compound semiconductor devices form the foundation of solid-state microwave and optoelectronic technologies used in many modern communication systems. In common with their low frequency counterparts, these devices are often represented using equivalent circuit models, but it is often necessary to resort to physical models in order to gain insight into the detailed operation of compound semiconductor devices. Many of the earliest physical models were indeed developed to understand the 'unusual' phenomena which occur at high frequencies. Such was the case with the Gunn and IMPATI diodes, which led to an increased interest in using numerical simulation methods. Contemporary devices often have feature sizes so small that they no longer operate within the familiar traditional framework, and hot electron or even quantum­ mechanical models are required. The need for accurate and efficient models suitable for computer aided design has increased with the demand for a wider range of integrated devices for operation at...

  12. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  13. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  14. Compact semiconductor lasers

    CERN Document Server

    Yu, Siyuan; Lourtioz, Jean-Michel

    2014-01-01

    This book brings together in a single volume a unique contribution by the top experts around the world in the field of compact semiconductor lasers to provide a comprehensive description and analysis of the current status as well as future directions in the field of micro- and nano-scale semiconductor lasers. It is organized according to the various forms of micro- or nano-laser cavity configurations with each chapter discussing key technical issues, including semiconductor carrier recombination processes and optical gain dynamics, photonic confinement behavior and output coupling mechanisms, carrier transport considerations relevant to the injection process, and emission mode control. Required reading for those working in and researching the area of semiconductors lasers and micro-electronics.

  15. Tuning polarity and improving charge transport in organic semiconductors

    Science.gov (United States)

    Oh, Joon Hak; Han, A.-Reum; Yu, Hojeong; Lee, Eun Kwang; Jang, Moon Jeong

    2013-09-01

    Although state-of-the-art ambipolar polymer semiconductors have been extensively reported in recent years, highperformance ambipolar polymers with tunable dominant polarity are still required to realize on-demand, target-specific, high-performance organic circuitry. Herein, dithienyl-diketopyrrolopyrrole (TDPP)-based polymer semiconductors with engineered side-chains have been synthesized, characterized and employed in ambipolar organic field-effect transistors, in order to achieve controllable and improved electrical properties. Thermally removable tert-butoxycarbonyl (t-BOC) groups and hybrid siloxane-solubilizing groups are introduced as the solubilizing groups, and they are found to enable the tunable dominant polarity and the enhanced ambipolar performance, respectively. Such outstanding performance based on our molecular design strategies makes these ambipolar polymer semiconductors highly promising for low-cost, large-area, and flexible electronics.

  16. Neutron and gamma irradiation effects on power semiconductor switches

    International Nuclear Information System (INIS)

    Schwarze, G.E.; Frasca, A.J.

    1990-01-01

    The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN bipolar junction transistors (BJTs), and metal-oxide-semiconductor field effect transistors (MOSFETs)

  17. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  18. Experiment list: SRX122465 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

  19. Fermi level dependent native defect formation: Consequences for metal-semiconductor and semiconductor-semiconductor interfaces

    International Nuclear Information System (INIS)

    Walukiewicz, W.

    1988-02-01

    The amphoteric native defect model of the Schottky barrier formation is used to analyze the Fermi level pinning at metal/semiconductor interfaces for submonolayer metal coverages. It is assumed that the energy required for defect generation is released in the process of surface back-relaxation. Model calculations for metal/GaAs interfaces show a weak dependence of the Fermi level pinning on the thickness of metal deposited at room temperature. This weak dependence indicates a strong dependence of the defect formation energy on the Fermi level, a unique feature of amphoteric native defects. This result is in very good agreement with experimental data. It is shown that a very distinct asymmetry in the Fermi level pinning on p- and n-type GaAs observed at liquid nitrogen temperatures can be understood in terms of much different recombination rates for amphoteric native defects in those two types of materials. Also, it is demonstrated that the Fermi level stabilization energy, a central concept of the amphoteric defect system, plays a fundamental role in other phenomena in semiconductors such as semiconductor/semiconductor heterointerface intermixing and saturation of free carrier concentration. 33 refs., 6 figs

  20. Semiconductor spintronics

    CERN Document Server

    Xia, Jianbai; Chang, Kai

    2012-01-01

    Semiconductor Spintronics, as an emerging research discipline and an important advanced field in physics, has developed quickly and obtained fruitful results in recent decades. This volume is the first monograph summarizing the physical foundation and the experimental results obtained in this field. With the culmination of the authors' extensive working experiences, this book presents the developing history of semiconductor spintronics, its basic concepts and theories, experimental results, and the prospected future development. This unique book intends to provide a systematic and modern foundation for semiconductor spintronics aimed at researchers, professors, post-doctorates, and graduate students, and to help them master the overall knowledge of spintronics.