WorldWideScience

Sample records for semiconductor chip designs

  1. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  2. 76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

    Science.gov (United States)

    2011-12-21

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With... importation, and the sale within the United States after importation of certain semiconductor chips with DRAM.... 7,906,809 (``the `809 patent''). The complaint further alleges that an industry in the United States...

  3. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  4. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  5. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  6. Toward designing semiconductor-semiconductor heterojunctions for photocatalytic applications

    Science.gov (United States)

    Zhang, Liping; Jaroniec, Mietek

    2018-02-01

    Semiconductor photocatalysts show a great potential for environmental and energy-related applications, however one of the major disadvantages is their relatively low photocatalytic performance due to the recombination of electron-hole pairs. Therefore, intensive research is being conducted toward design of heterojunctions, which have been shown to be effective for improving the charge-transfer properties and efficiency of photocatalysts. According to the type of band alignment and direction of internal electric field, heterojunctions are categorized into five different types, each of which is associated with its own charge transfer characteristics. Since the design of heterojunctions requires the knowledge of band edge positions of component semiconductors, the commonly used techniques for the assessment of band edge positions are reviewed. Among them the electronegativity-based calculation method is applied for a large number of popular visible-light-active semiconductors, including some widely investigated bismuth-containing semiconductors. On basis of the calculated band edge positions and the type of component semiconductors reported, heterojunctions composed of the selected bismuth-containing semiconductors are proposed. Finally, the most popular synthetic techniques for the fabrication of heterojunctions are briefly discussed.

  7. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Directory of Open Access Journals (Sweden)

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  8. Where the chips fall: environmental health in the semiconductor industry.

    Science.gov (United States)

    Chepesiuk, R

    1999-09-01

    Three recent lawsuits are focusing public attention on the environmental and occupational health effects of the world's largest and fastest growing manufacturing sector-the $150 billion semiconductor industry. The suits allege that exposure to toxic chemicals in semiconductor manufacturing plants led to adverse health effects such as miscarriage and cancer among workers. To manufacture computer components, the semiconductor industry uses large amounts of hazardous chemicals including hydrochloric acid, toxic metals and gases, and volatile solvents. Little is known about the long-term health consequences of exposure to chemicals by semiconductor workers. According to industry critics, the semiconductor industry also adversely impacts the environment, causing groundwater and air pollution and generating toxic waste as a by-product of the semiconductor manufacturing process. In contrast, the U.S. Bureau of Statistics shows the semiconductor industry as having a worker illness rate of about one-third of the average of all manufacturers, and advocates defend the industry, pointing to recent research collaborations and product replacement as proof that semiconductor manufacturers adequately protect both their employees and the environment.

  9. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  10. Lab-on-a-chip for label free biological semiconductor analysis of Staphylococcal Enterotoxin B

    NARCIS (Netherlands)

    Yang, Minghui; Sun, Steven; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

    2010-01-01

    We describe a new lab-on-a-chip (LOC) which utilizes a biological semiconductor (BSC) transducer for label free analysis of Staphylococcal Enterotoxin B (SEB) (or other biological interactions) directly and electronically. BSCs are new transducers based on electrical percolation through a

  11. All-polymer organic semiconductor laser chips: Parallel fabrication and encapsulation

    DEFF Research Database (Denmark)

    Vannahme, Christoph; Klinkhammer, Sönke; Christiansen, Mads Brøkner

    2010-01-01

    Organic semiconductor lasers are of particular interest as tunable visible laser light sources. For bringing those to market encapsulation is needed to ensure practicable lifetimes. Additionally, fabrication technologies suitable for mass production must be used. We introduce all-polymer chips...... comprising encapsulated distributed feedback organic semiconductor lasers. Several chips are fabricated in parallel by thermal nanoimprint of the feedback grating on 4? wafer scale out of poly(methyl methacrylate) (PMMA) and cyclic olefin copolymer (COC). The lasers consisting of the organic semiconductor...... tris(8- hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2- methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM) are hermetically sealed by thermally bonding a polymer lid. The organic thin film is placed in a basin within the substrate and is not in direct contact to the lid...

  12. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

  13. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Science.gov (United States)

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

  14. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  15. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  16. Challenges in physical chip design

    NARCIS (Netherlands)

    Otten, R.H.J.M.; Stravers, P.

    2000-01-01

    On behalf of the ICCAD-2000 Executive and Technical Program Committees, I would like to welcome you tothe International Conference on Computer-Aided Design, which will take place between November 5-9 at theSan Jose DoubleTree Hotel. The technical program for ICCAD-2000 was assembled by a program

  17. Design of systems on a chip design and test

    CERN Document Server

    Reis, Ricardo; Jess, Jochen AG

    2007-01-01

    Addresses the design challenges associated with generations of the semiconductor technology. This book includes contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs.

  18. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  19. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  20. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  1. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  2. Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

    Science.gov (United States)

    Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

    2011-04-25

    Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

  3. A Designed Room Temperature Multilayered Magnetic Semiconductor

    Science.gov (United States)

    Bouma, Dinah Simone; Charilaou, Michalis; Bordel, Catherine; Duchin, Ryan; Barriga, Alexander; Farmer, Adam; Hellman, Frances; Materials Science Division, Lawrence Berkeley National Lab Team

    2015-03-01

    A room temperature magnetic semiconductor has been designed and fabricated by using an epitaxial antiferromagnet (NiO) grown in the (111) orientation, which gives surface uncompensated magnetism for an odd number of planes, layered with the lightly doped semiconductor Al-doped ZnO (AZO). Magnetization and Hall effect measurements of multilayers of NiO and AZO are presented for varying thickness of each. The magnetic properties vary as a function of the number of Ni planes in each NiO layer; an odd number of Ni planes yields on each NiO layer an uncompensated moment which is RKKY-coupled to the moments on adjacent NiO layers via the carriers in the AZO. This RKKY coupling oscillates with the AZO layer thickness, and it disappears entirely in samples where the AZO is replaced with undoped ZnO. The anomalous Hall effect data indicate that the carriers in the AZO are spin-polarized according to the direction of the applied field at both low temperature and room temperature. NiO/AZO multilayers are therefore a promising candidate for spintronic applications demanding a room-temperature semiconductor.

  4. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  5. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  6. Essential issues in SOC design designing complex systems-on-chip

    CERN Document Server

    Lin, Youn-long Steve

    2007-01-01

    Covers issues related to system-on-chip (SoC) design. This book covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.

  7. Overcoming Limitations in Semiconductor Alloy Design

    Science.gov (United States)

    Christian, Theresa Marie

    Inorganic semiconductors provide an astonishingly versatile, robust, and efficient platform for optoelectronic energy conversion devices. However, conventional alloys and growth regimes face materials challenges that restrict the full potential of these devices. Novel alloy designs based on isoelectronic co-doping, metamorphic growth and controllable atomic ordering offer new pathways to practical and ultra-high-efficiency optoelectronic devices including solar cells and light-emitting diodes. Abnormal isoelectronic alloys of GaP1-xBix, GaP 1-x-yBixNy, and GaAs1-xBix with unprecedented bismuth incorporation fractions and crystalline quality are explored in this thesis research. Comparative studies of several GaP1-xBix and GaP1-x-yBixNy alloys demonstrate that the site-specific incorporation of bismuth during epitaxial growth is sensitive to growth temperature and has dramatic effects on carrier transfer processes in these alloys. Additionally, distinctive bismuth-related localized states are spectrally identified for the first time in samples of GaAs1-xBix grown by laser-assisted epitaxial growth. These results address fundamental questions about the nature of bismuth-bismuth inter-impurity interactions. Finally, a metamorphic growth strategy for a novel light-emitting diode (LED) design is also discussed. This work utilized direct-bandgap AlxIn1-xP active layers with atomic ordering-based electron confinement to improve emission in the yellow and green spectral regions, where incumbent technologies are least effective, and demonstrated the feasibility of non-lattice-matched LED active materials for visible light emission.

  8. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  9. Semiconductor

    International Nuclear Information System (INIS)

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  10. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  11. Design of an on-chip reflectance map

    NARCIS (Netherlands)

    Terwisscha van Scheltinga, Jeroen; Smit, Jaap; Bosma, Marco

    1995-01-01

    A reflectance map design is described which uses a minimal amount of memory for the table, in order to be applicable as an on-chip shader. The shader is designed for use with the volumetric super resolution hardware, which performs shading at supersampled locations. However, the design may be used

  12. Design and Development of a Portable Metal Chip Baler using A System Design Approach

    Directory of Open Access Journals (Sweden)

    Hassan Mohd Fahrul

    2017-01-01

    Full Text Available A large amount of metal chips at workplace will result in untidy and unsafe condition thus measurements of safety are needed in some industries, where the metal chips will be collected and put into a container until the volume is sufficient to be recycled. Due to that reason, the metal chips require a lot of spaces for storage before going to recycle. In this study, a portable metal chip baler as a device for compacting those metal chips is presented based on a system approach of engineering design. Basically, the system design evolves through four phases of development that are started from conceptual design, preliminary system design, detail design and development to system test and evaluation. The portable metal chip baler uses current technology such as pneumatic cylinder to compress the metal chips so that the system capable to operate efficiently. The output from this system is the metal chips are compacted into a block shape and a working prototype was developed to prove the concept of the system. As a summary, the conceptual design of portable metal chip baler was proven and was presented using the philosophy of the systems design approach. This tool may assists workers especially in the Small-Medium Enterprise (SME manufacturing industries, school or universities’ workshops for managing metal chips easily and systematically.

  13. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  14. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  15. SEU tolerant memory design for the ATLAS pixel readout chip

    International Nuclear Information System (INIS)

    Menouni, M; Barbero, M; Breugnon, P; Fougeron, D; Gensolen, F; Arutinov, D; Backhaus, M; Gonella, L; Hemperek, T; Karagounis, M; Beccherle, R; Darbo, G; Caminada, L; Dube, S; Fleury, J; Garcia-Sciveres, M; Gnani, D; Jensen, F; Gromov, V; Kluit, R

    2013-01-01

    The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

  16. Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

    Energy Technology Data Exchange (ETDEWEB)

    Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-12-01

    Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

  17. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-05-05

    ... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

  18. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Directory of Open Access Journals (Sweden)

    Ho-Chiao Chuang

    2014-06-01

    Full Text Available This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments.

  19. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Science.gov (United States)

    Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

    2014-01-01

    This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

  20. Circuit design techniques for non-crystalline semiconductors

    CERN Document Server

    Sambandan, Sanjiv

    2012-01-01

    Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

  1. Design of an Enterobacteriaceae Pan-genome Microarray Chip

    DEFF Research Database (Denmark)

    Lukjancenko, Oksana; Ussery, David

    2010-01-01

    -density microarray chip has been designed, using 116 Enterobacteriaceae genome sequences, taking into account the enteric pan-genome. Probes for the microarray were checked in silico and performance of the chip, based on experimental strains from four different genera, demonstrate a relatively high ability...... to distinguish those strains on genus, species, and pathotype/serovar levels. Additionally, the microarray performed well when investigating which genes were found in a given strain of interest. The Enterobacteriaceae pan-genome microarray, based on 116 genomes, provides a valuable tool for determination...

  2. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Science.gov (United States)

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  3. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  4. Introduction to Open Core Protocol Fastpath to System-on-Chip Design

    CERN Document Server

    Schwaderer, W David

    2012-01-01

    This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

  5. Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

    Science.gov (United States)

    Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

    2006-01-01

    We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

  6. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2011-03-17

    ... existence of a domestic industry. The Commission's notice of investigation named several respondents...; Freescale Semiconductor Malaysia Sdn. Bhd. of Malaysia; Freescale Semiconductor Pte. Ltd. of Singapore; Mouser Electronics, Inc. of Mansfield, Texas; and Motorola Inc. of Schaumburg, Illinois. On August 16...

  7. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    -synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written...... to support an invited talk at the NORCHIP’2007 conference....

  8. Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

    Science.gov (United States)

    Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

    2018-02-01

    The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

  9. A new electrode design for ambipolar injection in organic semiconductors.

    Science.gov (United States)

    Kanagasekaran, Thangavel; Shimotani, Hidekazu; Shimizu, Ryota; Hitosugi, Taro; Tanigaki, Katsumi

    2017-10-17

    Organic semiconductors have attracted much attention for low-cost, flexible and human-friendly optoelectronics. However, achieving high electron-injection efficiency is difficult from air-stable electrodes and cannot be equivalent to that of holes. Here, we present a novel concept of electrode composed of a bilayer of tetratetracontane (TTC) and polycrystalline organic semiconductors (pc-OSC) covered by a metal layer. Field-effect transistors of single-crystal organic semiconductors with the new electrodes of M/pc-OSC/TTC (M: Ca or Au) show both highly efficient electron and hole injection. Contact resistance for electron injection from Au/pc-OSC/TTC and hole injection from Ca/pc-OSC/TTC are comparable to those for electron injection from Ca and hole injection from Au, respectively. Furthermore, the highest field-effect mobilities of holes (22 cm 2  V -1  s -1 ) and electrons (5.0 cm 2  V -1  s -1 ) are observed in rubrene among field-effect transistors with electrodes so far proposed by employing Ca/pc-OSC/TTC and Au/pc-OSC/TTC electrodes for electron and hole injection, respectively.One of technological challenges building organic electronics is efficient injection of electrons at metal-semiconductor interfaces compared to that of holes. The authors show an air-stable electrode design with induced gap states, which support Fermi level pinning and thus ambipolar carrier injection.

  10. Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

    Science.gov (United States)

    Michaelides, Stylianos

    Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

  11. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  12. Normalization and experimental design for ChIP-chip data

    Directory of Open Access Journals (Sweden)

    Alekseyenko Artyom A

    2007-06-01

    Full Text Available Abstract Background Chromatin immunoprecipitation on tiling arrays (ChIP-chip has been widely used to investigate the DNA binding sites for a variety of proteins on a genome-wide scale. However, several issues in the processing and analysis of ChIP-chip data have not been resolved fully, including the effect of background (mock control subtraction and normalization within and across arrays. Results The binding profiles of Drosophila male-specific lethal (MSL complex on a tiling array provide a unique opportunity for investigating these topics, as it is known to bind on the X chromosome but not on the autosomes. These large bound and control regions on the same array allow clear evaluation of analytical methods. We introduce a novel normalization scheme specifically designed for ChIP-chip data from dual-channel arrays and demonstrate that this step is critical for correcting systematic dye-bias that may exist in the data. Subtraction of the mock (non-specific antibody or no antibody control data is generally needed to eliminate the bias, but appropriate normalization obviates the need for mock experiments and increases the correlation among replicates. The idea underlying the normalization can be used subsequently to estimate the background noise level in each array for normalization across arrays. We demonstrate the effectiveness of the methods with the MSL complex binding data and other publicly available data. Conclusion Proper normalization is essential for ChIP-chip experiments. The proposed normalization technique can correct systematic errors and compensate for the lack of mock control data, thus reducing the experimental cost and producing more accurate results.

  13. An FPGA design flow for reconfigurable network-based multi-processor systems on chip

    NARCIS (Netherlands)

    Kumar, A.; Hansson, M.A; Huisken, J.; Corporaal, H.

    2007-01-01

    Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity

  14. Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

    International Nuclear Information System (INIS)

    Mishra, Vijay; Kataria, S.K.

    2005-01-01

    A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

  15. High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-07-30

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  16. Semiconductor-inspired design principles for superconducting quantum computing.

    Science.gov (United States)

    Shim, Yun-Pil; Tahan, Charles

    2016-03-17

    Superconducting circuits offer tremendous design flexibility in the quantum regime culminating most recently in the demonstration of few qubit systems supposedly approaching the threshold for fault-tolerant quantum information processing. Competition in the solid-state comes from semiconductor qubits, where nature has bestowed some very useful properties which can be utilized for spin qubit-based quantum computing. Here we begin to explore how selective design principles deduced from spin-based systems could be used to advance superconducting qubit science. We take an initial step along this path proposing an encoded qubit approach realizable with state-of-the-art tunable Josephson junction qubits. Our results show that this design philosophy holds promise, enables microwave-free control, and offers a pathway to future qubit designs with new capabilities such as with higher fidelity or, perhaps, operation at higher temperature. The approach is also especially suited to qubits on the basis of variable super-semi junctions.

  17. Design and construct of a tunable semiconductor laser

    Directory of Open Access Journals (Sweden)

    J. Sabbaghzadeh

    2000-06-01

    Full Text Available   In this paper we explain in detail the design of a semiconductor laser coupled with the reflected beams from a grating. Since the beams reflected are diffracted at different angles, only one component of them can be resonated in the cavity. This technique reduces the output frequency of the laser and increases its stability.   Since this system has various applications in the spectroscopy, gas concentrations, air pollution measurements, investigation of atomic and molecular structure, and so on, system is believed to be simple and accurate. This design is made for the first time in Iran and its reliability has been tested by the measurement of the rubidium atom, and the result is given.

  18. Chip Design Process Optimization Based on Design Quality Assessment

    Science.gov (United States)

    Häusler, Stefan; Blaschke, Jana; Sebeke, Christian; Rosenstiel, Wolfgang; Hahn, Axel

    2010-06-01

    Nowadays, the managing of product development projects is increasingly challenging. Especially the IC design of ASICs with both analog and digital components (mixed-signal design) is becoming more and more complex, while the time-to-market window narrows at the same time. Still, high quality standards must be fulfilled. Projects and their status are becoming less transparent due to this complexity. This makes the planning and execution of projects rather difficult. Therefore, there is a need for efficient project control. A main challenge is the objective evaluation of the current development status. Are all requirements successfully verified? Are all intermediate goals achieved? Companies often develop special solutions that are not reusable in other projects. This makes the quality measurement process itself less efficient and produces too much overhead. The method proposed in this paper is a contribution to solve these issues. It is applied at a German design house for analog mixed-signal IC design. This paper presents the results of a case study and introduces an optimized project scheduling on the basis of quality assessment results.

  19. Design and Characterisation of III-V Semiconductor Nanowire Lasers

    Science.gov (United States)

    Saxena, Dhruv

    The development of small, power-efficient lasers underpins many of the technologies that we utilise today. Semiconductor nanowires are promising for miniaturising lasers to even smaller dimensions. III-V semiconductors, such as Gallium Arsenide (GaAs) and Indium Phosphide (InP), are the most widely used materials for optoelectronic devices and so the development of nanowire lasers based on these materials is expected to have technologically significant outcomes. This PhD dissertation presents a comprehensive study of the design of III-V semiconductor nanowire lasers, with bulk and quantum confined active regions. Based on the design, various III-V semiconductor nanowire lasers are demonstrated, namely, GaAs nanowire lasers, GaAs/AlGaAs multi-quantum well (MQW) nanowire lasers and InP nanowire lasers. These nanowire lasers are shown to operate at room temperature, have low thresholds, and lase from different transverse modes. The structural and optoelectronic quality of nanowire lasers are characterised via electron microscopy and photoluminescence spectroscopic techniques. Lasing is characterised in all these devices by optical pumping. The lasing characteristics are analysed by rate equation modelling and the lasing mode(s) in these devices is characterised by threshold gain modelling, polarisation measurements and Fourier plane imaging. Firstly, GaAs nanowire lasers that operate at room temperature are demonstrated. This is achieved by determining the optimal nanowire diameter to reduce threshold gain and by passivating nanowires to improve their quantum efficiency (QE). High-quality surface passivated GaAs nanowires of suitable diameters are grown. The growth procedure is tailored to improve both QE and structural uniformity of nanowires. Room-temperature lasing is demonstrated from individual nanowires and lasing is characterised to be from TM01 mode by threshold gain modelling. To lower threshold even further, nanowire lasers with GaAs/AlGaAs coaxial multi

  20. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  1. A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

    Science.gov (United States)

    Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

    2012-01-01

    This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

  2. High-performance green semiconductor devices: materials, designs, and fabrication

    Science.gov (United States)

    Jung, Yei Hwan; Zhang, Huilong; Gong, Shaoqin; Ma, Zhenqiang

    2017-06-01

    From large industrial computers to non-portable home appliances and finally to light-weight portable gadgets, the rapid evolution of electronics has facilitated our daily pursuits and increased our life comforts. However, these rapid advances have led to a significant decrease in the lifetime of consumer electronics. The serious environmental threat that comes from electronic waste not only involves materials like plastics and heavy metals, but also includes toxic materials like mercury, cadmium, arsenic, and lead, which can leak into the ground and contaminate the water we drink, the food we eat, and the animals that live around us. Furthermore, most electronics are comprised of non-renewable, non-biodegradable, and potentially toxic materials. Difficulties in recycling the increasing amount of electronic waste could eventually lead to permanent environmental pollution. As such, discarded electronics that can naturally degrade over time would reduce recycling challenges and minimize their threat to the environment. This review provides a snapshot of the current developments and challenges of green electronics at the semiconductor device level. It looks at the developments that have been made in an effort to help reduce the accumulation of electronic waste by utilizing unconventional, biodegradable materials as components. While many semiconductors are classified as non-biodegradable, a few biodegradable semiconducting materials exist and are used as electrical components. This review begins with a discussion of biodegradable materials for electronics, followed by designs and processes for the manufacturing of green electronics using different techniques and designs. In the later sections of the review, various examples of biodegradable electrical components, such as sensors, circuits, and batteries, that together can form a functional electronic device, are discussed and new applications using green electronics are reviewed.

  3. Multimedia Terminal System-on-Chip Design and Simulation

    Directory of Open Access Journals (Sweden)

    Barbieri Ivano

    2005-01-01

    Full Text Available This paper proposes a design approach based on integrated architectural and system-on-chip (SoC simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW digital signal processors (DSPs, the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

  4. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  5. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

  6. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif; Arsalan, Muhammad; Roy, L; Salama, Khaled N.

    2012-01-01

    with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been

  7. Design and Performance of the CMS Pixel Detector Readout Chip

    CERN Document Server

    Kästli, H C; Erdmann, W; Hörmann, C; Horisberger, R P; Kotlinski, D; Meier, B; Hoermann, Ch.

    2006-01-01

    The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

  8. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  9. Origami chip-on-sensor design: progress and new developments

    International Nuclear Information System (INIS)

    Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

    2013-01-01

    The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

  10. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Science.gov (United States)

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  11. Robust design and thermal fatigue life prediction of anisotropic conductive film flip chip package

    International Nuclear Information System (INIS)

    Nam, Hyun Wook

    2004-01-01

    The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF(Anisotropic Conductive Film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue life of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear bi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design Of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2 nd DOE was conducted to obtain RSM equation for the choose 3 design parameter. The coefficient of determination (R 2 ) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for Feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430μm, and 78μm, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter

  12. Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

    Science.gov (United States)

    Holmes, Anna M.; Monaco, Lisa; Barnes, Cindy; Spearing, Scott; Jenkins, Andy; Johnson, Todd; Mayer, Derek; Cole, Helen

    2003-01-01

    The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

  13. Research on and design of key circuits in RFID tag chip for container management

    Directory of Open Access Journals (Sweden)

    Wang Wenjie

    2016-01-01

    Full Text Available This paper introduces the design of semi-passive RFID tag chip capable of monitoring container safety. A system framework complying with requirements by ISO/IEC 18000-6C is firstly presented, and then differences from the key units of common passive chip, such as switch-state monitoring circuit, power management unit and anti-shake design in baseband processor, are elaborated. The main function of such a chip is to record the container opening frequency during transportation. Finally, the realizations of each unit’s function are simulated.

  14. Rational Design of Semiconductor Nanostructures for Functional Subcellular Interfaces.

    Science.gov (United States)

    Parameswaran, Ramya; Tian, Bozhi

    2018-05-15

    these rationally designed materials either intra- or extracellularly. We last delve into the use of these materials in sensing mechanical forces and electrical signals in various cellular systems as well as in instructing cellular behaviors. Future research in this area may shift the paradigm in fundamental biophysical research and biomedical applications through (1) the design and synthesis of new semiconductor-based materials and devices that interact specifically with targeted cells, (2) the clarification of many developmental, physiological, and anatomical aspects of cellular communications, (3) an understanding of how signaling between cells regulates synaptic development (e.g., information like this would offer new insight into how the nervous system works and provide new targets for the treatment of neurological diseases), (4) and the creation of new cellular materials that have the potential to open up completely new areas of application, such as in hybrid information processing systems.

  15. DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

    NARCIS (Netherlands)

    Stefanov, T.; Pimentel, A.; Nikolov, H.; Ha, S.; Teich, J.

    2017-01-01

    The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design

  16. Digital design update for a sun sensor on a chip

    NARCIS (Netherlands)

    Mert, O.

    2014-01-01

    In the beginning of one year project work at Moog-Bradford, the scope of my assignment was coordination of the firmware development activities as defined in the Sun Sensor on a Chip (SSOAC) proposal for ESA GSTP-5 program. As the time progressed in the proposal evaluation process, my project scope

  17. Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

    Science.gov (United States)

    Celik, Cihangir

    -scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement

  18. n-Channel semiconductor materials design for organic complementary circuits.

    Science.gov (United States)

    Usta, Hakan; Facchetti, Antonio; Marks, Tobin J

    2011-07-19

    Organic semiconductors have unique properties compared to traditional inorganic materials such as amorphous or crystalline silicon. Some important advantages include their adaptability to low-temperature processing on flexible substrates, low cost, amenability to high-speed fabrication, and tunable electronic properties. These features are essential for a variety of next-generation electronic products, including low-power flexible displays, inexpensive radio frequency identification (RFID) tags, and printable sensors, among many other applications. Accordingly, the preparation of new materials based on π-conjugated organic molecules or polymers has been a central scientific and technological research focus over the past decade. Currently, p-channel (hole-transporting) materials are the leading class of organic semiconductors. In contrast, high-performance n-channel (electron-transporting) semiconductors are relatively rare, but they are of great significance for the development of plastic electronic devices such as organic field-effect transistors (OFETs). In this Account, we highlight the advances our team has made toward realizing moderately and highly electron-deficient n-channel oligomers and polymers based on oligothiophene, arylenediimide, and (bis)indenofluorene skeletons. We have synthesized and characterized a "library" of structurally related semiconductors, and we have investigated detailed structure-property relationships through optical, electrochemical, thermal, microstructural (both single-crystal and thin-film), and electrical measurements. Our results reveal highly informative correlations between structural parameters at various length scales and charge transport properties. We first discuss oligothiophenes functionalized with perfluoroalkyl and perfluoroarene substituents, which represent the initial examples of high-performance n-channel semiconductors developed in this project. The OFET characteristics of these compounds are presented with an

  19. Designing solution-processable air-stable liquid crystalline crosslinkable semiconductors

    DEFF Research Database (Denmark)

    McCulloch, I.; Bailey, C.; Genevicius, K.

    2006-01-01

    organic light emitting diode displays, low frequency radio frequency identification tag and other low performance electronics. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes...... the development of reactive mesogen semiconductors, which form large crosslinked LC domains on polymerization within mesophases. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed...

  20. Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

    Science.gov (United States)

    Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

    2015-09-01

    This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

  1. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  2. Introduction to semiconductor manufacturing technology

    CERN Document Server

    2012-01-01

    IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

  3. Driving the SID chip: Assembly language, composition, and sound design for the C64

    Directory of Open Access Journals (Sweden)

    James Newman

    2017-12-01

    Full Text Available The MOS6581, more commonly known as the Sound Interface Device, or SID chip, was the sonic heart of the Commodore 64 home computer. By considering the chip’s development, specification, uses and creative abuses by composers and programmers, alongside its continuing legacy, this paper argues that, more than any other device, the SID chip is responsible for shaping the sound of videogame music. Compared with the brutal atonality of chips such as Atari’s TIA, the SID chip offers a complex 3-channel synthesizer with dynamic waveform selection, per-channel ADSR envelopes, multi-mode filter, ring and cross modulation. However, while the specification is sophisticated, the exploitation of the vagaries and imperfections of the chip are just as significant to its sonic character. As such, the compositional, sound design and programming techniques developed by 1980s composer-coders like Rob Hubbard and Martin Galway are central in defining the distinctive sound of C64 gameplay. Exploring the affordances of the chip and the distinctive ways they were harnessed, the argument of this paper centers on the inexorable link between the technological and the musical. Crucially, composers like Hubbard et al. developed their own bespoke low-level drivers to interface with the SID chip to create pseudo-polyphony through rapid arpeggiation and channel sharing, drum synthesis through waveform manipulation, portamento, and even sample playback. This paper analyses the indivisibility of sound design, synthesis and composition in the birth of these musical forms and aesthetics, and assesses their impact on what would go on to be defined as chiptunes.

  4. Design and Construction of an Atomic Clock on an Atom Chip

    International Nuclear Information System (INIS)

    Reinhard, Friedemann

    2009-01-01

    We describe the design and construction of an atomic clock on an atom chip, intended as a secondary standard, with a stability in the range of few 10 -13 at 1 s. This clock is based on a two-photon transition between the hyperfine states |F = 1; m F = -1> and |2; 1> of the electronic ground state of the 87 Rb atom. This transition is interrogated using a Ramsey scheme, operating on either a cloud of thermal atoms or a Bose-Einstein condensate. In contrast to atomic fountain clocks, this clock is magnetically trapped on an atom chip. We describe a theoretical model of the clock stability and the design and construction of a dedicated apparatus. It is able to control the magnetic field at the relative 10 -5 level and features a hybrid atom chip, containing DC conductors as well as a microwave transmission line for the clock interrogation. (author)

  5. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  6. The Role of Custom Design in ASIC Chips

    National Research Council Canada - National Science Library

    Dally, William

    1998-01-01

    The performance of an ASIC can be greatly improved without increasing design time by judiciously employing a number of custom design techniques, including floorplanning, prerouting critical signals...

  7. Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

    Science.gov (United States)

    Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

    2011-01-01

    The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

  8. Development of a chip-based ingroove microplasma source: Design, characterization, and diagnostics

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuemei; Meng, Fanying; Yuan, Xin; Yan, Yanyue; Zhao, Zhongjun; Duan, Yixiang, E-mail: yduan@scu.edu.cn [Research Center of Analytical Instrumentation, College of Chemistry and College of Life Science Sichuan University, Chengdu (China); Tang, Jie [State Key Laboratory of Transient Optics and Photonics, Xi' an Institute of Optics and Precision Mechanics of CAS, Xi' an (China)

    2014-03-10

    A chip-based ingroove microplasma source was designed for molecular emission spectrometry by using a space-confined direct current duct in air. The voltage-current characteristics of different size generators, emission spectroscopy of argon were discussed, respectively. It is found that the emission intensity of excited Ar and N{sub 2} approaches its maximum near the cathode, while OH and O peaks most likely appear close to the anode. The electron density, electronic excitation temperature, rotational temperature, and vibrational temperature of the argon plasma were also calculated. More importantly, the chip-based ingroove microplasma shows much better stability compared with its counterparts.

  9. Embedded memory design for multi-core and systems on chip

    CERN Document Server

    Mohammad, Baker

    2014-01-01

    This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit ...

  10. Rational In Silico Design of an Organic Semiconductor with Improved Electron Mobility.

    Science.gov (United States)

    Friederich, Pascal; Gómez, Verónica; Sprau, Christian; Meded, Velimir; Strunk, Timo; Jenne, Michael; Magri, Andrea; Symalla, Franz; Colsmann, Alexander; Ruben, Mario; Wenzel, Wolfgang

    2017-11-01

    Organic semiconductors find a wide range of applications, such as in organic light emitting diodes, organic solar cells, and organic field effect transistors. One of their most striking disadvantages in comparison to crystalline inorganic semiconductors is their low charge-carrier mobility, which manifests itself in major device constraints such as limited photoactive layer thicknesses. Trial-and-error attempts to increase charge-carrier mobility are impeded by the complex interplay of the molecular and electronic structure of the material with its morphology. Here, the viability of a multiscale simulation approach to rationally design materials with improved electron mobility is demonstrated. Starting from one of the most widely used electron conducting materials (Alq 3 ), novel organic semiconductors with tailored electronic properties are designed for which an improvement of the electron mobility by three orders of magnitude is predicted and experimentally confirmed. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Science.gov (United States)

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  12. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...... to the transaction-level model. The thesis, as a whole makes contributions by describing a design methodology for networked multiprocessor embedded systems at three layers of abstraction from system-level through transaction-level to the cycle accurate level as well as demonstrating it practically by implementing...

  13. Design and evaluation of modelocked semiconductor lasers for low noise and high stability

    DEFF Research Database (Denmark)

    Yvind, Kresten; Larsson, David; Christiansen, Lotte Jin

    2005-01-01

    We present work on design of monolithic mode-locked semiconductor lasers with focus on the gain medium. The use of highly inverted quantum wells in a low-loss waveguide enables both low quantum noise, low-chirped pulses and a large stability region. Broadband noise measurements are performed...

  14. Performance of Multithreaded Chip Multiprocessors And Implications for Operating System Design

    OpenAIRE

    Fedorova, Alexandra; Seltzer, Margo I.; Small, Christopher A.; Nussbaum, Daniel

    2005-01-01

    An operating system’s design is often influenced by the architecture of the target hardware. While uniprocessor and multiprocessor architectures are well understood, such is not the case for multithreaded chip multiprocessors (CMT) – a new generation of processors designed to improve performance of memory-intensive applications. The first systems equipped with CMT processors are just becoming available, so it is critical that we now understand how to obtain the best performance from such syst...

  15. Design of an Elliptic Curve Cryptography processor for RFID tag chips.

    Science.gov (United States)

    Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

    2014-09-26

    Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

  16. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  17. A peek into the world of chip design

    CERN Document Server

    CERN. Geneva; Marquina, Miguel Angel

    2005-01-01

    This lecture will give some insight into how the Microprocessor Design Group approaches the daunting task of the design of a lead microprocessor as complex as the Pentium IV while under very specific schedule constraints. For a historical perspective, we will start with a quick comparison of the complexity/performance of the Willamette and Prescott (Pentium IV) class of microprocessor with the generations before the Pentium IV (Bob was a member of the design teams for a number of lead microprocessor projects including the 486DX2, Pentium Pr

  18. LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

    International Nuclear Information System (INIS)

    Heijne, E.H.M.; Antinori, F.; Barberis, D.

    1996-01-01

    The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

  19. Programmable System-on-Chip (PSoC) Embedded Readout Designs for Liquid Helium Level Sensors.

    Science.gov (United States)

    Parasakthi, C; Gireesan, K; Usha Rani, R; Sheela, O K; Janawadkar, M P

    2014-08-01

    This article reports the development of programmable system-on-chip (PSoC)-based embedded readout designs for liquid helium level sensors using resistive liquid vapor discriminators. The system has been built for the measurement of liquid helium level in a concave-bottomed, helmet-shaped, fiber-reinforced plastic cryostat for magnetoencephalography. This design incorporates three carbon resistors as cost-effective sensors, which are mounted at desired heights inside the cryostat and were used to infer the liquid helium level by measuring their temperature-dependent resistance. Localized electrical heating of the carbon resistors was used to discriminate whether the resistor is immersed in liquid helium or its vapor by exploiting the difference in the heat transfer rates in the two environments. This report describes a single PSoC chip for the design and development of a constant current source to drive the three carbon resistors, a multiplexer to route the sensor outputs to the analog-to-digital converter (ADC), a buffer to avoid loading of the sensors, an ADC for digitizing the data, and a display using liquid crystal display cum light-emitting diode modules. The level sensor readout designed with a single PSoC chip enables cost-effective and reliable measurement system design. © 2014 Society for Laboratory Automation and Screening.

  20. Semiconductor laser diodes and the design of a D.C. powered laser diode drive unit

    OpenAIRE

    Cappuccio, Joseph C., Jr.

    1988-01-01

    Approved for public release; distribution is unlimited This thesis addresses the design, development and operational analysis of a D.C. powered semiconductor laser diode drive unit. A laser diode requires an extremely stable power supply since a picosecond spike of current or power supply switching transient could result in permanent damage. The design offers stability and various features for operational protection of the laser diode. The ability to intensity modulate (analog) and pulse m...

  1. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  2. Recent advances in design and fabrication of on-chip micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Wang, Chunlei

    2012-06-01

    Recent development in miniaturized electronic devices has increased the demand for power sources that are sufficiently compact and can potentially be integrated on a chip with other electronic components. Miniaturized electrochemical capacitors (EC) or micro-supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. Recently, we have developed several types of micro-supercapacitors with different structural designs and active materials. Carbon-Microelectromechanical Systems (C-MEMS) with three dimensional (3D) interdigital structures are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of pseudo-capacitive materials. More recently, we have also developed microsupercapacitor based on hybrid graphene and carbon nanotube interdigital structures. In this paper, the recent advances in design and fabrication of on-chip micro-supercapacitors are reviewed.

  3. Design of Water Temperature Control System Based on Single Chip Microcomputer

    Science.gov (United States)

    Tan, Hanhong; Yan, Qiyan

    2017-12-01

    In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

  4. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  5. Design strategies for organic semiconductors beyond the molecular formula.

    Science.gov (United States)

    Henson, Zachary B; Müllen, Klaus; Bazan, Guillermo C

    2012-09-01

    Organic semiconducting materials based on polymers and molecular systems containing an electronically delocalized structure are the basis of emerging optoelectronic technologies such as plastic solar cells and flexible transistors. For isolated molecules, guidelines exist that rely on the molecular formula to tailor the frontier (highest occupied or lowest unoccupied) molecular orbital energy levels and optical absorption profiles. Much less control can be achieved over relevant properties, however, as one makes the transition to the ensemble behaviour characteristic of the solid state. Polymeric materials are also challenging owing to the statistical description of the average number of repeat units. Here we draw attention to the limitations of molecular formulae as predictive tools for achieving properties relevant to device performances. Illustrative examples highlight the relevance of organization across multiple length scales, and how device performances--although relevant for practical applications--poorly reflect the success of molecular design.

  6. Molecular Electrical Doping of Organic Semiconductors: Fundamental Mechanisms and Emerging Dopant Design Rules.

    Science.gov (United States)

    Salzmann, Ingo; Heimel, Georg; Oehzelt, Martin; Winkler, Stefanie; Koch, Norbert

    2016-03-15

    -Dirac occupation of which ultimately determines the doping efficiency, thus emerges as key challenge. As a first step, the formation of charge transfer complexes is identified as being detrimental to the doping efficiency, which suggests sterically shielding the functional core of dopant molecules as an additional design rule to complement the requirement of low ionization energies or high electron affinities in efficient n-type or p-type dopants, respectively. In an extended outlook, we finally argue that, to fully meet this challenge, an improved understanding is required of just how the admixture of dopant molecules to organic semiconductors does affect the density of states: compared with their inorganic counterparts, traps for charge carriers are omnipresent in organic semiconductors due to structural and chemical imperfections, and Coulomb attraction between ionized dopants and free charge carriers is typically stronger in organic semiconductors owing to their lower dielectric constant. Nevertheless, encouraging progress is being made toward developing a unifying picture that captures the entire range of doping induced phenomena, from ion-pair to complex formation, in both conjugated polymers and molecules. Once completed, such a picture will provide viable guidelines for synthetic and supramolecular chemistry that will enable further technological advances in organic and hybrid organic/inorganic devices.

  7. Global Production Networks, Innovation, and Work: Why Chip and System Design in the IT Industry are Moving to Asia

    OpenAIRE

    Dieter Ernst; Boy Luethje

    2003-01-01

    This paper was prepared as an issue paper, to be discussed at the Planning Meeting of the SSRC on "Emerging Pathways to Innovation in Asia," September 12-13, 2003. The paper describes a research project that explores why chip design is moving to Asia, despite its high knowledge-intensity. Trade economists would search for an answer by looking at differences in the cost of employing a chip design engineer and comparative factor and resource endowments. However, an analysis of Asia's comparativ...

  8. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  9. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  10. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    Energy Technology Data Exchange (ETDEWEB)

    Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  11. Blood cleaner on-chip design for artificial human kidney manipulation

    Directory of Open Access Journals (Sweden)

    Suwanpayak N

    2011-05-01

    Full Text Available N Suwanpayak1, MA Jalil2, MS Aziz3, FD Ismail3, J Ali3, PP Yupapin11Nanoscale Science and Engineering Research Alliance (N'SERA, Advanced Research Center for Photonics, Faculty of Science, King Mongkut's Institute of Technology, Ladkrabang, Bangkok, Thailand; 2Ibnu Sina Institute of Fundamental Science Studies (IIS, 3Institute of Advanced Photonics Science, Nanotechnology Research Alliance, Universiti Teknologi Malaysia, Johor Bahru, MalaysiaAbstract: A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney, and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.Keywords: optical trapping, blood dialysis, blood cleaner, human kidney manipulation

  12. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G.; Kosel, Jü rgen

    2016-01-01

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  13. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan

    2016-08-26

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  14. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Chinthaka P. Gooneratne

    2016-08-01

    Full Text Available The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA for the manipulation of superparamagnetic beads (SPBs, and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

  15. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...... routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower...

  16. Chemical engineering in the electronics industry: progress towards the rational design of organic semiconductor heterojunctions

    KAUST Repository

    Clancy, Paulette

    2012-01-01

    We review the current status of heterojunction design for combinations of organic semiconductor materials, given its central role in affecting the device performance for electronic devices and solar cell applications. We provide an emphasis on recent progress towards the rational design of heterojunctions that may lead to higher performance of charge separation and mobility. We also play particular attention to the role played by computational approaches and its potential to help define the best choice of materials for solar cell development in the future. We report the current status of the field with respect to such goals. © 2012 Elsevier Ltd.

  17. Chemical engineering in the electronics industry: progress towards the rational design of organic semiconductor heterojunctions

    KAUST Repository

    Clancy, Paulette

    2012-05-01

    We review the current status of heterojunction design for combinations of organic semiconductor materials, given its central role in affecting the device performance for electronic devices and solar cell applications. We provide an emphasis on recent progress towards the rational design of heterojunctions that may lead to higher performance of charge separation and mobility. We also play particular attention to the role played by computational approaches and its potential to help define the best choice of materials for solar cell development in the future. We report the current status of the field with respect to such goals. © 2012 Elsevier Ltd.

  18. Design and exploration of semiconductors from first principles: A review of recent advances

    Science.gov (United States)

    Oba, Fumiyasu; Kumagai, Yu

    2018-06-01

    Recent first-principles approaches to semiconductors are reviewed, with an emphasis on theoretical insight into emerging materials and in silico exploration of as-yet-unreported materials. As relevant theory and methodologies have developed, along with computer performance, it is now feasible to predict a variety of material properties ab initio at the practical level of accuracy required for detailed understanding and elaborate design of semiconductors; these material properties include (i) fundamental bulk properties such as band gaps, effective masses, dielectric constants, and optical absorption coefficients; (ii) the properties of point defects, including native defects, residual impurities, and dopants, such as donor, acceptor, and deep-trap levels, and formation energies, which determine the carrier type and density; and (iii) absolute and relative band positions, including ionization potentials and electron affinities at semiconductor surfaces, band offsets at heterointerfaces between dissimilar semiconductors, and Schottky barrier heights at metal–semiconductor interfaces, which are often discussed systematically using band alignment or lineup diagrams. These predictions from first principles have made it possible to elucidate the characteristics of semiconductors used in industry, including group III–V compounds such as GaN, GaP, and GaAs and their alloys with related Al and In compounds; amorphous oxides, represented by In–Ga–Zn–O transparent conductive oxides (TCOs), represented by In2O3, SnO2, and ZnO; and photovoltaic absorber and buffer layer materials such as CdTe and CdS among group II–VI compounds and chalcopyrite CuInSe2, CuGaSe2, and CuIn1‑ x Ga x Se2 (CIGS) alloys, in addition to the prototypical elemental semiconductors Si and Ge. Semiconductors attracting renewed or emerging interest have also been investigated, for instance, divalent tin compounds, including SnO and SnS; wurtzite-derived ternary compounds such as ZnSnN2 and Cu

  19. Chip-Oriented Fluorimeter Design and Detection System Development for DNA Quantification in Nano-Liter Volumes

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2009-12-01

    Full Text Available The chip-based polymerase chain reaction (PCR system has been developed in recent years to achieve DNA quantification. Using a microstructure and miniature chip, the volume consumption for a PCR can be reduced to a nano-liter. With high speed cycling and a low reaction volume, the time consumption of one PCR cycle performed on a chip can be reduced. However, most of the presented prototypes employ commercial fluorimeters which are not optimized for fluorescence detection of such a small quantity sample. This limits the performance of DNA quantification, especially low experiment reproducibility. This study discusses the concept of a chip-oriented fluorimeter design. Using the analytical model, the current study analyzes the sensitivity and dynamic range of the fluorimeter to fit the requirements for detecting fluorescence in nano-liter volumes. Through the optimized processes, a real-time PCR on a chip system with only one nano-liter volume test sample is as sensitive as the commercial real-time PCR machine using the sample with twenty micro-liter volumes. The signal to noise (S/N ratio of a chip system for DNA quantification with hepatitis B virus (HBV plasmid samples is 3 dB higher. DNA quantification by the miniature chip shows higher reproducibility compared to the commercial machine with respect to samples of initial concentrations from 103 to 105 copies per reaction.

  20. Rational design of organic semiconductors for texture control and self-patterning on halogenated surfaces

    KAUST Repository

    Ward, Jeremy W.

    2014-05-15

    Understanding the interactions at interfaces between the materials constituting consecutive layers within organic thin-film transistors (OTFTs) is vital for optimizing charge injection and transport, tuning thin-film microstructure, and designing new materials. Here, the influence of the interactions at the interface between a halogenated organic semiconductor (OSC) thin film and a halogenated self-assembled monolayer on the formation of the crystalline texture directly affecting the performance of OTFTs is explored. By correlating the results from microbeam grazing incidence wide angle X-ray scattering (μGIWAXS) measurements of structure and texture with OTFT characteristics, two or more interaction paths between the terminating atoms of the semiconductor and the halogenated surface are found to be vital to templating a highly ordered morphology in the first layer. These interactions are effective when the separating distance is lower than 2.5 dw, where dw represents the van der Waals distance. The ability to modulate charge carrier transport by several orders of magnitude by promoting "edge-on" versus "face-on" molecular orientation and crystallographic textures in OSCs is demonstrated. It is found that the "edge-on" self-assembly of molecules forms uniform, (001) lamellar-textured crystallites which promote high charge carrier mobility, and that charge transport suffers as the fraction of the "face-on" oriented crystallites increases. The role of interfacial halogenation in mediating texture formation and the self-patterning of organic semiconductor films, as well as the resulting effects on charge transport in organic thin-film transistors, are explored. The presence of two or more anchoring sites between a halogenated semiconductor and a halogenated self-assembled monolayer, closer than about twice the corresponding van der Waals distance, alter the microstructure and improve electrical properties. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  2. Design and FPGA-implementation of multilayer neural networks with on-chip learning

    International Nuclear Information System (INIS)

    Haggag, S.S.M.Y

    2008-01-01

    Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

  3. Integrated Materials Design of Organic Semiconductors for Field-Effect Transistors

    KAUST Repository

    Mei, Jianguo

    2013-05-08

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm2/(V s). In this perspective, we highlight some of the major milestones along the way to provide a historical view of OFET development, introduce the integrated molecular design concepts and process engineering approaches that lead to the current success, and identify the challenges ahead to make OFETs applicable in real applications. © 2013 American Chemical Society.

  4. Integrated materials design of organic semiconductors for field-effect transistors.

    Science.gov (United States)

    Mei, Jianguo; Diao, Ying; Appleton, Anthony L; Fang, Lei; Bao, Zhenan

    2013-05-08

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm(2)/(V s). In this perspective, we highlight some of the major milestones along the way to provide a historical view of OFET development, introduce the integrated molecular design concepts and process engineering approaches that lead to the current success, and identify the challenges ahead to make OFETs applicable in real applications.

  5. Design of automatic curtain controlled by wireless based on single chip 51 microcomputer

    Science.gov (United States)

    Han, Dafeng; Chen, Xiaoning

    2017-08-01

    In order to realize the wireless control of the domestic intelligent curtains, a set of wireless intelligent curtain control system based on 51 single chip microcomputer have been designed in this paper. The intelligent curtain can work in the manual mode, automatic mode and sleep mode and can be carried out by the button and mobile phone APP mode loop switch. Through the photosensitive resistance module and human pyroelectric infrared sensor to collect the indoor light value and the data whether there is the person in the room, and then after single chip processing, the motor drive module is controlled to realize the positive inversion of the asynchronous motor, the intelligent opening and closing of the curtain have been realized. The operation of the motor can be stopped under the action of the switch and the curtain opening and closing and timing switch can be controlled through the keys and mobile phone APP. The optical fiber intensity, working mode, curtain state and system time are displayed by LCD1602. The system has a high reliability and security under practical testing and with the popularity and development of smart home, the design has broad market prospects.

  6. Device reliability challenges for modern semiconductor circuit design – a review

    Directory of Open Access Journals (Sweden)

    C. Schlünder

    2009-05-01

    Full Text Available Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1. Degradation mechanisms like Negative Bias Temperature Instability (NBTI or Hot Carrier Injection (HCI lead to parameter drifts during operation adding on top of the process variations.

    The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

    An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

  7. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  8. Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

    CERN Document Server

    Liberali, Valentino; The ATLAS collaboration

    2016-01-01

    We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

  9. Design and simulation of MEMS microvalves for silicon photonic biosensor chip

    Science.gov (United States)

    Amemiya, Yoshiteru; Nakashima, Yuuto; Maeda, Jun; Yokoyama, Shin

    2018-04-01

    For the early and easy diagnosis of diseases, we have proposed a silicon photonic biosensor chip with two kinds of MEMS microvalves for a multiple-item detection system. The driving voltage of the vertical type with the circular-plate capacitor structure and that of the lateral type with the comb-shaped electrode are investigated. From mechanical calculations, the driving voltage of the vertical type is estimated to be 30 V and that of the lateral type to be 15 V. The propagation loss at the intersecting waveguides of arrayed ring-resonator biosensors is also estimated. In the case of optimized intersecting waveguides, more than 67% transmittance of TE-mode light is simulated for the series connection of 20 intersecting waveguides. It is confirmed that it is possible to fabricate an 8 × 12 arrayed biosensor chip in an area of 1 × 1.5 mm2 taking the device size of the microvalves into consideration. We have, for the first time, designed a whole system, including sensors and a fluid channel with MEMS microvalves.

  10. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    NARCIS (Netherlands)

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be

  11. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  12. Design and characterization of a 52K SNP chip for goats.

    Directory of Open Access Journals (Sweden)

    Gwenola Tosser-Klopp

    Full Text Available The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50-60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed: Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes, sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years.

  13. Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

    2017-09-01

    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

  14. Research and Design on a Product Data Definition System of Semiconductor Packaging Industry

    Science.gov (United States)

    Shi, Jinfei; Ma, Qingyao; Zhou, Yifan; Chen, Ruwen

    2017-12-01

    This paper develops a product data definition (PDD) system for a semiconductor packaging and testing company with independent intellectual property rights. The new PDD system can solve the problems such as, the effective control of production plans, the timely feedback of production processes, and the efficient schedule of resources. Firstly, this paper introduces the general requirements of the PDD system and depicts the operation flow and the data flow of the PDD system. Secondly, the overall design scheme of the PDD system is put forward. After that, the physical data model is developed using the Power Designer15.0 tool, and the database system is built. Finally, the function realization and running effects of the PDD system are analysed. The successful operation of the PDD system can realize the information flow among various production departments of the enterprise to meet the standard of the enterprise manufacturing integration and improve the efficiency of production management.

  15. Design and test of a prototype silicon detector module for ATLAS Semiconductor Tracker endcaps

    International Nuclear Information System (INIS)

    Clark, A.G.; Donega, M.; D'Onofrio, M.

    2005-01-01

    The ATLAS Semiconductor Tracker (SCT) will be a central part of the tracking system of the ATLAS experiment. The SCT consists of four concentric barrels of silicon detectors as well as two silicon endcap detectors formed by nine disks each. The layout of the forward silicon detector module presented in this paper is based on the approved layout of the silicon detectors of the SCT, their geometry and arrangement in disks, but uses otherwise components identical to the barrel modules of the SCT. The module layout is optimized for excellent thermal management and electrical performance, while keeping the assembly simple and adequate for a large scale module production. This paper summarizes the design and layout of the module and present results of a limited prototype production, which has been extensively tested in the laboratory and testbeam. The module design was not finally adopted for series production because a dedicated forward hybrid layout was pursued

  16. Design of a DNA chip for detection of unknown genetically modified organisms (GMOs).

    Science.gov (United States)

    Nesvold, Håvard; Kristoffersen, Anja Bråthen; Holst-Jensen, Arne; Berdal, Knut G

    2005-05-01

    Unknown genetically modified organisms (GMOs) have not undergone a risk evaluation, and hence might pose a danger to health and environment. There are, today, no methods for detecting unknown GMOs. In this paper we propose a novel method intended as a first step in an approach for detecting unknown genetically modified (GM) material in a single plant. A model is designed where biological and combinatorial reduction rules are applied to a set of DNA chip probes containing all possible sequences of uniform length n, creating probes capable of detecting unknown GMOs. The model is theoretically tested for Arabidopsis thaliana Columbia, and the probabilities for detecting inserts and receiving false positives are assessed for various parameters for this organism. From a theoretical standpoint, the model looks very promising but should be tested further in the laboratory. The model and algorithms will be available upon request to the corresponding author.

  17. Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link

    Science.gov (United States)

    Sangirov, Jamshid; Nguyen, Nga T. H.; Ngo, Trong-Hieu; Im, Dong-min; Ukaegbu, Augustine I.; Lee, Tae-Woo; Cho, Mu Hee; Park, Hyo-Hoon

    2010-02-01

    An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

  18. Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

    Science.gov (United States)

    Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

    2008-01-01

    A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

  19. Computational nano-materials design for high-TC ferromagnetism in wide-gap magnetic semiconductors

    International Nuclear Information System (INIS)

    Katayama-Yoshida, H.; Sato, K.; Fukushima, T.; Toyoda, M.; Kizaki, H.; Dinh, V.A.; Dederichs, P.H.

    2007-01-01

    We propose materials design of high-T C wide band-gap dilute magnetic semiconductors (DMSs) based on first-principles calculations by using the Korringa-Kohn-Rostoker coherent potential approximation (KKR-CPA) method. First, we discuss a unified physical picture of ferromagnetism in II-VI and III-V DMSs and show that DMS family is categorized into two groups depending on the electronic structure. One is the system where Zener's double exchange mechanism dominates in the ferromagnetic interaction, and in the other systems Zener's p-d exchange mechanism dominates. Next, we develop an accurate method for T C calculation for the DMSs and show that the mean field approximation completely fails to predict Curie temperature of DMS in particular for wide-gap DMS where the exchange interaction is short-ranged. The calculated T C of homogeneous DMSs by using the present method agrees very well with available experimental values. For more realistic material design, we simulate spinodal nano-decomposition by applying the Monte Carlo method to the Ising model with ab initio chemical pair interactions between magnetic impurities in DMS. It is found that by controlling the dimensionality of the decomposition various characteristic phases occur in DMS such as 3D Dairiseki-phase and 1D Konbu-phase, and it is suggested that super-paramagnetic blocking phenomena should be important to understand the magnetism of wide-gap DMS. Based on the present simulations for spinodal nano-decomposition, we propose a new crystal growth method of positioning by seeding and shape controlling method in 100 Tera-bit density of nano-magnets in the semiconductor matrix with high-T C (or high-T B )

  20. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  1. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  2. Design of Semiconductor-Based Back Reflectors for High Voc Monolithic Multijunction Solar Cells: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Garcia, I.; Geisz, J.; Steiner, M.; Olson, J.; Friedman, D.; Kurtz, S.

    2012-06-01

    State-of-the-art multijunction cell designs have the potential for significant improvement before going to higher number of junctions. For example, the Voc can be substantially increased if the photon recycling taking place in the junctions is enhanced. This has already been demonstrated (by Alta Devices) for a GaAs single-junction cell. For this, the loss of re-emitted photons by absorption in the underlying layers or substrate must be minimized. Selective back surface reflectors are needed for this purpose. In this work, different architectures of semiconductor distributed Bragg reflectors (DBR) are assessed as the appropriate choice for application in monolithic multijunction solar cells. Since the photon re-emission in the photon recycling process is spatially isotropic, the effect of the incident angle on the reflectance spectrum is of central importance. In addition, the DBR structure must be designed taking into account its integration into the monolithic multijunction solar cells, concerning series resistance, growth economics, and other issues. We analyze the tradeoffs in DBR design complexity with all these requirements to determine if such a reflector is suitable to improve multijunction solar cells.

  3. Structural Design Principle of Small-Molecule Organic Semiconductors for Metal-Free, Visible-Light-Promoted Photocatalysis.

    Science.gov (United States)

    Wang, Lei; Huang, Wei; Li, Run; Gehrig, Dominik; Blom, Paul W M; Landfester, Katharina; Zhang, Kai A I

    2016-08-08

    Herein, we report on the structural design principle of small-molecule organic semiconductors as metal-free, pure organic and visible light-active photocatalysts. Two series of electron-donor and acceptor-type organic semiconductor molecules were synthesized to meet crucial requirements, such as 1) absorption range in the visible region, 2) sufficient photoredox potential, and 3) long lifetime of photogenerated excitons. The photocatalytic activity was demonstrated in the intermolecular C-H functionalization of electron-rich heteroaromates with malonate derivatives. A mechanistic study of the light-induced electron transport between the organic photocatalyst, substrate, and the sacrificial agent are described. With their tunable absorption range and defined energy-band structure, the small-molecule organic semiconductors could offer a new class of metal-free and visible light-active photocatalysts for chemical reactions. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Designing Selectivity in Metal-Semiconductor Nanocrystals: Synthesis, Characterization, and Self-Assembly

    Science.gov (United States)

    Pavlopoulos, Nicholas George

    This dissertation contains six chapters detailing recent advances that have been made in the synthesis and characterization of metal-semiconductor hybrid nanocrystals (HNCs), and the applications of these materials. Primarily focused on the synthesis of well-defined II-VI semiconductor nanorod (NR) and tetrapod (TP) based constructs of interest for photocatalytic and solar energy applications, the research described herein discusses progress towards the realization of key design rules for the synthesis of functional semiconductor nanocrystals (NCs). As such, a blend of novel synthesis, advanced characterization, and direct application of heterostructured nanoparticles are presented. The first chapter is a review summarizing the design, synthesis, properties, and applications of multicomponent nanomaterials composed of disparate semiconductor and metal domains. By coupling two compositionally distinct materials onto a single nanocrystal, synergistic properties can arise that are not present in the isolated components, ranging from self-assembly to photocatalysis. For semiconductor nanomaterials, this was first realized in the ability to tune nanomaterial dimensions from 0-D quantum dot (QD) structures to cylindrical (NR) and branched (TP) structures by exploitation of advanced colloidal synthesis techniques and understandings of NC facet reactivities. The second chapter is focused on the synthesis and characterization of well-defined CdSe-seeded-CdS (CdSe CdS) NR systems synthesized by overcoating of wurtzite (W) CdSe quantum dots with W-CdS shells. 1-dimensional NRs have been interesting constructs for applications such as solar concentrators, optical gains, and photocatalysis. Through synthetic control over CdSe CdS NR systems, materials with small and large CdSe seeds were prepared, and for each seed size, multiple NR lengths were prepared. Through transient absorption studies, it was found that band alignment did not affect the efficiency of charge localization

  5. Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

    CERN Document Server

    Poikela, Tuomas; Paakkulainen, J

    2010-01-01

    The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

  6. Design methodology and results evaluation of a heating functionality in modular lab-on-chip systems

    Science.gov (United States)

    Streit, Petra; Nestler, Joerg; Shaporin, Alexey; Graunitz, Jenny; Otto, Thomas

    2018-06-01

    Lab-on-a-chip (LoC) systems offer the opportunity of fast and customized biological analyses executed at the ‘point-of-need’ without expensive lab equipment. Some biological processes need a temperature treatment. Therefore, it is important to ensure a defined and stable temperature distribution in the biosensor area. An integrated heating functionality is realized with discrete resistive heating elements including temperature measurement. The focus of this contribution is a design methodology and evaluation technique of the temperature distribution in the biosensor area with regard to the thermal-electrical behaviour of the heat sources. Furthermore, a sophisticated control of the biosensor temperature is proposed. A finite element (FE) model with one and more integrated heat sources in a polymer-based LoC system is used to investigate the impact of the number and arrangement of heating elements on the temperature distribution around the heating elements and in the biosensor area. Based on this model, various LOC systems are designed and fabricated. Electrical characterization of the heat sources and independent temperature measurements with infrared technique are performed to verify the model parameters and prove the simulation approach. The FE model and the proposed methodology is the foundation for optimization and evaluation of new designs with regard to temperature requirements of the biosensor. Furthermore, a linear dependency of the heater temperature on the electric current is demonstrated in the targeted temperature range of 20 °C to 70 °C enabling the usage of the heating functionality for biological reactions requiring a steady-state temperature up to 70 °C. The correlation between heater and biosensor area temperature is derived for a direct control through the heating current.

  7. RCP: a novel probe design bias correction method for Illumina Methylation BeadChip.

    Science.gov (United States)

    Niu, Liang; Xu, Zongli; Taylor, Jack A

    2016-09-01

    The Illumina HumanMethylation450 BeadChip has been extensively utilized in epigenome-wide association studies. This array and its successor, the MethylationEPIC array, use two types of probes-Infinium I (type I) and Infinium II (type II)-in order to increase genome coverage but differences in probe chemistries result in different type I and II distributions of methylation values. Ignoring the difference in distributions between the two probe types may bias downstream analysis. Here, we developed a novel method, called Regression on Correlated Probes (RCP), which uses the existing correlation between pairs of nearby type I and II probes to adjust the beta values of all type II probes. We evaluate the effect of this adjustment on reducing probe design type bias, reducing technical variation in duplicate samples, improving accuracy of measurements against known standards, and retention of biological signal. We find that RCP is statistically significantly better than unadjusted data or adjustment with alternative methods including SWAN and BMIQ. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website (https://www.bioconductor.org/packages/release/bioc/html/ENmix.html). niulg@ucmail.uc.edu Supplementary data are available at Bioinformatics online. Published by Oxford University Press 2016. This work is written by US Government employees and is in the public domain in the US.

  8. Design and measurements of low power multichannel chip for recording and stimulation of neural activity.

    Science.gov (United States)

    Zoladz, M; Kmon, P; Grybos, P; Szczygiel, R; Kleczek, R; Otfinowski, P; Rauza, J

    2012-01-01

    A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm² of silicon area and consumes only 25 µW/channel. A low cut-off frequency can be tuned in the 60 mHz-100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 µV rms in 100 Hz-12 kHz band and 7.6 µV rms in 3 Hz-12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA-512 µA range.

  9. Design and Characterization of CMOS On-Chip Antennas for 60 GHz Communications

    Directory of Open Access Journals (Sweden)

    D.Titz

    2012-04-01

    Full Text Available In this paper, we present the design and the measurement of two antennas realized on a 130nm CMOS process. They both radiate in the 60 GHz band and are dedicated to Wireless Personal Area Network (WPAN applications. The antennas are manufactured within the frame of a multi-wafer project with several surrounding microelectronic circuits. The first antenna is an Inverted-F antenna (IFA. It has a maximum gain of -8 dBi and a -10 dB matching bandwidth of 20%. The second radiator is a meandered dipole. It has a maximum gain of -14 dBi and a -10 dB matching bandwidth of 10%. The challenging measurement of their reflection coefficient and their gain radiation pattern are presented. Simulated versus measured curves are analyzed. We especially demonstrate the necessity to take into account the closest microelectronic circuits of the antennas for accurate modeling of the radiating performance of 60 GHz on-chip dies.

  10. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong

    2015-08-23

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  11. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong; Alouini, Mohamed-Slim

    2015-01-01

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  12. Design of a one-chip board microcontrol unit for active vibration control of a naval ship mounting system

    International Nuclear Information System (INIS)

    Oh, Jong-Seok; Choi, Seung-Bok; Han, Young-Min; Nguyen, Vien-Quoc; Moon, Seok-Jun

    2012-01-01

    This work presents an experimental implementation of a user-tunable one-chip board microcontrol unit which is specifically designed for vibration control of the active mounting system for naval ships. The proposed mounting system consists of four active mounts supporting vibration-sensitive equipment. Each active mount constitutes a rubber element, an inertial mass and the piezostack actuator. It is designed for particular applications that require effective isolation performance against wide frequency ranges, such as naval ship equipment. After describing the configuration of the active mount, dynamic characteristics of the rubber element and the piezostack actuator are experimentally identified. Accordingly, the proposed mounting system is constructed and the governing equations of motion are formulated. In order to attenuate the unwanted vibrations transferred from the upper mass, a feedforward controller with fast Fourier algorithm is designed and experimentally realized using the one-chip microcontrol board which is specially made for this practical application. In order to evaluate the performance of the one-chip microcontrol unit, vibration control results of the proposed active mounting system are presented in the frequency domain. (technical note)

  13. Rational design of organic semiconductors for texture control and self-patterning on halogenated surfaces

    KAUST Repository

    Ward, Jeremy W.; Li, Ruipeng; Obaid, Abdulmalik; Payne, Marcia M.; Smilgies, Detlef Matthias; Anthony, John Edward; Amassian, Aram; Jurchescu, Oana D.

    2014-01-01

    new materials. Here, the influence of the interactions at the interface between a halogenated organic semiconductor (OSC) thin film and a halogenated self-assembled monolayer on the formation of the crystalline texture directly affecting

  14. Dry etching technology for semiconductors

    CERN Document Server

    Nojiri, Kazuo

    2015-01-01

    This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

  15. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    International Nuclear Information System (INIS)

    Trimpl, M.

    2005-12-01

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  16. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  17. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  18. Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

    Science.gov (United States)

    Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

    2006-12-01

    We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

  19. A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

    Science.gov (United States)

    Santoli, S.

    The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

  20. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  1. Design, realization and test of a rad-hard 2D-compressor and packing chip for high energy physics experiments

    International Nuclear Information System (INIS)

    Antinori, Samuele; Falchieri, Davide; Gabrielli, Alessandro; Gandolfi, Enzo

    2004-01-01

    CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 μm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN

  2. Magma Design Automation : Component placement on chips; the "holey cheese" problem

    NARCIS (Netherlands)

    Brouwer, R.; Brouwer, T.; Hurkens, C.A.J.; Manen, van M.; Montijn, C.; Schreuder, J.; Williams, J.F.; Hek, G.M.

    2002-01-01

    The costs of the fabrication of a chip is partly determined by the wire length needed by the transistors to respect the wiring scheme. The transistors have to be placed without overlap into a prescribed configuration of blockades, i.e. parts of the chipthat are beforehand excluded from positioning

  3. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  4. Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

    2018-05-01

    Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

  5. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  6. The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

    CERN Document Server

    Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

  7. Integrated Materials Design of Organic Semiconductors for Field-Effect Transistors

    KAUST Repository

    Mei, Jianguo; Diao, Ying; Appleton, Anthony L.; Fang, Lei; Bao, Zhenan

    2013-01-01

    The past couple of years have witnessed a remarkable burst in the development of organic field-effect transistors (OFETs), with a number of organic semiconductors surpassing the benchmark mobility of 10 cm2/(V s). In this perspective, we highlight

  8. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  9. Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

    Science.gov (United States)

    Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

    2018-03-01

    This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

  10. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  11. Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

    2006-11-15

    The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

  12. Optimal design of advanced distillation configuration for enhanced energy efficiency of waste solvent recovery process in semiconductor industry

    International Nuclear Information System (INIS)

    Chaniago, Yus Donald; Minh, Le Quang; Khan, Mohd Shariq; Koo, Kee-Kahb; Bahadori, Alireza; Lee, Moonyong

    2015-01-01

    Highlights: • Thermally coupled distillation process is proposed for waste solvent recovery. • A systematic optimization procedure is used to optimize distillation columns. • Response surface methodology is applied to optimal design of distillation column. • Proposed advanced distillation allows energy efficient waste solvent recovery. - Abstract: The semiconductor industry is one of the largest industries in the world. On the other hand, the huge amount of solvent used in the industry results in high production cost and potential environmental damage because most of the valuable chemicals discharged from the process are incinerated at high temperatures. A distillation process is used to recover waste solvent, reduce the production-related costs and protect the environment from the semiconductor industrial waste. Therefore, in this study, a distillation process was used to recover the valuable chemicals from semiconductor industry discharge, which otherwise would have been lost to the environment. The conventional sequence of distillation columns, which was optimized using the Box and sequential quadratic programming method for minimum energy objectives, was used. The energy demands of a distillation problem may have a substantial influence on the profitability of a process. A thermally coupled distillation and heat pump-assisted distillation sequence was implemented to further improve the distillation performance. Finally, a comparison was made between the conventional and advanced distillation sequences, and the optimal conditions for enhancing recovery were determined. The proposed advanced distillation configuration achieved a significant energy saving of 40.5% compared to the conventional column sequence

  13. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  14. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  15. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

    OpenAIRE

    Goel, Sandeep Kumar

    2005-01-01

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

  16. Testing of modern semiconductor memory structures

    NARCIS (Netherlands)

    Gaydadjiev, G.N.

    2007-01-01

    In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

  17. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  18. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    OpenAIRE

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. P...

  19. Efficient On-chip Optical Microresonator for Optical Comb Generation: Design and Fabrication

    Science.gov (United States)

    Han, Kyunghun

    An optical frequency comb is a series of equally spaced frequency components. It has gained much attention since Nobel physics prize was awarded John L. Hall and Theodor W. Hansch for their contribution to the optical frequency comb technique in 2005. The optical frequency comb has been extensively studied because of its precision as a tool for spectroscopy, and is now widely used in bio- and chemical sensors, optical clocks, mode-locked dark pulse generation, soliton generation, and optical communication. Recently, thanks to the developments in nanotechnology, the optical frequency comb generation is made possible at a chip-scale level with microresonators. However, because the threshold power of the optical frequency comb generation is beyond the capability of the on-chip laser source, efficient microresonator is required. Here, we demonstrate an ultra-compact and highly efficient strip-slot direct mode coupler, aiming to achieve slotted silicon microresonator cladded with nonlinear polymer Poly-DDMEBT in SOI platform. As an application of the strip-slot direct mode coupling, a double slot fiber-to-chip edge coupler is demonstrated showing 2 dB insertion loss reduction compared to the conventional single tip edge coupler. For silicon nitride platform, we investigated evanescent wave coupling of microresonator, focusing on bus waveguide geometry optimization. The optimized waveguide width offers an efficient excitation of a fundamental mode in the resonator waveguide. This investigation can benefit low threshold comb generation by enhancing the extinction ratio. We experimentally demonstrated the high Q-factor micro-ring resonator with intrinsic Q of 12.6 million as well as the single FSR comb generation with 63 mW.

  20. SEMICONDUCTOR INTEGRATED CIRCUITS: An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

    Science.gov (United States)

    Fangxiong, Chen; Min, Lin; Heping, Ma; Hailong, Jia; Yin, Shi; Forster, Dai

    2009-08-01

    An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (IIP3) is 16.621 dBm, with 50 Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system) and Bluetooth systems.

  1. Towards high charge carrier mobilities by rational design of organic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Andrienko, Denis; Ruehle, Victor; Baumeier, Bjoern; Vehoff, Thorsten; Lukyanov, Alexander; Kremer, Kurt [Max Planck Institute for Polymer Research, Mainz (Germany); Marcon, Valentina [Technische Universitaet Darmstadt (Germany); Kirkpatrick, James; Nelson, Jenny [Imperial College London (United Kingdom); Lennartz, Christian [BASF AG, Ludwigshafen (Germany)

    2010-07-01

    The role of material morphology on charge carrier mobility in partially disordered organic semiconductors is discussed for several classes of materials: derivatives of hexabenzocoronenens, perylenediimides, triangularly-shaped polyaromatic hydrocarbons, and Alq{sub 3}. Simulations are performed using a package developed by Imperial College, London and Max Planck Institute for Polymer Research, Mainz (votca.org). This package combines several techniques into one scheme: quantum chemical methods for the calculation of molecular electronic structures and reorganization energies; molecular dynamics and systematic coarse-graining approaches for simulation of self-assembly and relative positions and orientations of molecules on large scales; kinetic Monte Carlo and master equation for studies of charge transport.

  2. Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2010-01-01

    Full Text Available Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design.

  3. Design of nanophotonic, hot-electron solar-blind ultraviolet detectors with a metal-oxide-semiconductor structure

    International Nuclear Information System (INIS)

    Wang, Zhiyuan; Wang, Xiaoxin; Liu, Jifeng

    2014-01-01

    Solar-blind ultraviolet (UV) detection refers to photon detection specifically in the wavelength range of 200 nm–320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. The most commonly used solid state devices for this application are wide band gap (WBG) semiconductor photodetectors (Eg > 3.5 eV). However, WBG semiconductors are difficult to grow and integrate with Si readout integrated circuits (ROICs). In this paper, we design a nanophotonic metal-oxide-semiconductor structure on Si for solar-blind UV detectors. Instead of using semiconductors as the active absorber, we use Sn nano-grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between the metal and the n-type Si region upon UV excitation. Moreover, the transported hot electron has an excess kinetic energy >3 eV, large enough to induce impact ionization and generate another free electron in the conduction band of n-Si. This process doubles the quantum efficiency. On the other hand, the large metal/oxide interfacial energy barrier (>3.5 eV) also enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, ∼75% UV absorption and hot electron excitation can be achieved within the mean free path of ∼20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. The simple geometry of the Sn nano-gratings and the MOS structure make it easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices. (paper)

  4. Semiconductor radiation detection systems

    CERN Document Server

    2010-01-01

    Covers research in semiconductor detector and integrated circuit design in the context of medical imaging using ionizing radiation. This book explores other applications of semiconductor radiation detection systems in security applications such as luggage scanning, dirty bomb detection and border control.

  5. System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

    Directory of Open Access Journals (Sweden)

    Daniel D. Gajski

    2008-07-01

    Full Text Available The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

  6. Key techniques for space-based solar pumped semiconductor lasers

    Science.gov (United States)

    He, Yang; Xiong, Sheng-jun; Liu, Xiao-long; Han, Wei-hua

    2014-12-01

    In space, the absence of atmospheric turbulence, absorption, dispersion and aerosol factors on laser transmission. Therefore, space-based laser has important values in satellite communication, satellite attitude controlling, space debris clearing, and long distance energy transmission, etc. On the other hand, solar energy is a kind of clean and renewable resources, the average intensity of solar irradiation on the earth is 1353W/m2, and it is even higher in space. Therefore, the space-based solar pumped lasers has attracted much research in recent years, most research focuses on solar pumped solid state lasers and solar pumped fiber lasers. The two lasing principle is based on stimulated emission of the rare earth ions such as Nd, Yb, Cr. The rare earth ions absorb light only in narrow bands. This leads to inefficient absorption of the broad-band solar spectrum, and increases the system heating load, which make the system solar to laser power conversion efficiency very low. As a solar pumped semiconductor lasers could absorb all photons with energy greater than the bandgap. Thus, solar pumped semiconductor lasers could have considerably higher efficiencies than other solar pumped lasers. Besides, solar pumped semiconductor lasers has smaller volume chip, simpler structure and better heat dissipation, it can be mounted on a small satellite platform, can compose satellite array, which can greatly improve the output power of the system, and have flexible character. This paper summarizes the research progress of space-based solar pumped semiconductor lasers, analyses of the key technologies based on several application areas, including the processing of semiconductor chip, the design of small and efficient solar condenser, and the cooling system of lasers, etc. We conclude that the solar pumped vertical cavity surface-emitting semiconductor lasers will have a wide application prospects in the space.

  7. Design, fabrication, and evaluation of on-chip micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Chen, Wei; Wang, Chunlei

    2011-06-01

    Development of miniaturized electronic systems has stimulated the demand for miniaturized power sources that can be integrated into such systems. Among the different micro power sources micro electrochemical energy storage and conversion devices are particularly attractive because of their high efficiency and relatively high energy density. Electrochemical micro-capacitors or micro-supercapacitors offer higher power density compared to micro-batteries and micro-fuel cells. In this paper, development of on-chip micro-supercapacitors based on interdigitated C-MEMS electrode microarrays is introduced. C-MEMS electrodes are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of EDLC or pseudo-capacitive materials. Recent advancements in fabrication methods of C-MEMS based micro-supercapacitors are discussed and electrochemical properties of C-MEMS electrodes and it composites are reviewed.

  8. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  9. Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

    Science.gov (United States)

    Yashin, A. A.

    1985-04-01

    A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

  10. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  11. The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

    International Nuclear Information System (INIS)

    Marconi, S; Christiansen, J; Conti, E; Placidi, P; Hemperek, T

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared

  12. MIS photodetectors on intrinsic semiconductors for thermal infrared imagery - A design aid for focal plane matrices

    Science.gov (United States)

    Farre, J.

    1980-12-01

    The physical mechanisms determining the operational behavior of an MIS photodetector for thermal infrared imagery based on a two-dimensional matrix of intrinsic semiconductors constituting a charge injection device are examined. The general principles of a thermal infrared imagery system composed of radiation source, atmosphere, sensor system with entrance optics, detector and environment, and data processing means are introduced, and the parameters of the system as a whole influencing detector characteristics are indicated. The properties of an ideal and a real MIS photodetector are discussed, with attention given to the physical properties of narrow bandgap materials such as InSb, operational properties in the dynamic regime, the carrier tunneling component and experimentally observed instability phenomena. The matrix organization of MIS photodetectors is then considered, with particular attention given to a simple model of charge transfer between two electrodes and the two principal reading mechanisms: charge injection and the floating potential method.

  13. Intelligent microchip networks: an agent-on-chip synthesis framework for the design of smart and robust sensor networks

    Science.gov (United States)

    Bosse, Stefan

    2013-05-01

    Sensorial materials consisting of high-density, miniaturized, and embedded sensor networks require new robust and reliable data processing and communication approaches. Structural health monitoring is one major field of application for sensorial materials. Each sensor node provides some kind of sensor, electronics, data processing, and communication with a strong focus on microchip-level implementation to meet the goals of miniaturization and low-power energy environments, a prerequisite for autonomous behaviour and operation. Reliability requires robustness of the entire system in the presence of node, link, data processing, and communication failures. Interaction between nodes is required to manage and distribute information. One common interaction model is the mobile agent. An agent approach provides stronger autonomy than a traditional object or remote-procedure-call based approach. Agents can decide for themselves, which actions are performed, and they are capable of flexible behaviour, reacting on the environment and other agents, providing some degree of robustness. Traditionally multi-agent systems are abstract programming models which are implemented in software and executed on program controlled computer architectures. This approach does not well scale to micro-chip level and requires full equipped computers and communication structures, and the hardware architecture does not consider and reflect the requirements for agent processing and interaction. We propose and demonstrate a novel design paradigm for reliable distributed data processing systems and a synthesis methodology and framework for multi-agent systems implementable entirely on microchip-level with resource and power constrained digital logic supporting Agent-On-Chip architectures (AoC). The agent behaviour and mobility is fully integrated on the micro-chip using pipelined communicating processes implemented with finite-state machines and register-transfer logic. The agent behaviour

  14. Design, Fabrication and Prototype testing of a Chip Integrated Micro PEM Fuel Cell Accumulator combined On-Board Range Extender

    International Nuclear Information System (INIS)

    Balakrishnan, A; Mueller, C; Reinecke, H

    2014-01-01

    In this work we present the design, fabrication and prototype testing of Chip Integrated Micro PEM Fuel Cell Accumulator (CIμ-PFCA) combined On-Board Range Extender (O-BRE). CIμ-PFCA is silicon based micro-PEM fuel cell system with an integrated hydrogen storage feature (palladium metal hydride), the run time of CIμ-PFCA is dependent on the stored hydrogen, and in order to extend its run time an O-BRE is realized (catalytic hydrolysis of chemical hydride, NaBH 4 . Combining the CIμ-PFCA and O-BRE on a system level have few important design requirements to be considered; hydrogen regulation, gas -liquid separator between the CIμ-PFCA and the O-RE. The usage of traditional techniques to regulate hydrogen (tubes), gas-liquid phase membranes (porous membrane separators) are less desirable in the micro domain, due to its space constraint. Our approach is to use a passive hydrogen regulation and gas-liquid phase separation concept; to use palladium membrane. Palladium regulates hydrogen by concentration diffusion, and its property to selectively adsorb only hydrogen is used as a passive gas-liquid phase separator. Proof of concept is shown by realizing a prototype system. The system is an assembly of CIμ-PFCA, palladium membrane and the O-BRE. The CIμ-PFCA consist of 2 individually processed silicon chips, copper supported palladium membrane realized by electroplating followed by high temperature annealing process under inter atmosphere and the O-BRE is realized out of a polymer substrate by micromilling process with platinum coated structures, which functions as a catalyst for the hydrolysis of NaBH 4 . The functionality of the assembled prototype system is demonstrated by the measuring a unit cell (area 1 mm 2 ) when driven by the catalytic hydrolysis of chemical hydride (NaBH 4 and the prototype system shows run time more than 15 hours

  15. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  16. Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

    Science.gov (United States)

    Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

    2017-10-01

    In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

  17. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  18. Design and length optimization of an adiabatic coupler for on-chip vertical integration of rare-earth-doped double tungstate waveguide amplifiers

    NARCIS (Netherlands)

    Mu, Jinfeng; Sefünç, Mustafa; García Blanco, Sonia Maria

    2014-01-01

    The integration of rare-earth doped double tungstate waveguide amplifiers onto passive technology platforms enables the on-chip amplification of very high bit rate signals. In this work, a methodology for the optimized design of vertical adiabatic couplers between a passive Si3N4 waveguide and the

  19. Second-Generation Design of Micro-Spec: A Medium-Resolution, Submillimeter-Wavelength Spectrometer-on-a-Chip

    Science.gov (United States)

    Cataldo, G.; Barrentine, E. M.; Bulcha, B. T.; Ehsan, N.; Hess, L. A.; Noroozian, O.; Stevenson, T. R.; U-Yen, K.; Wollack, E. J.; Moseley, S. H.

    2018-04-01

    Micro-Spec (µ-Spec) is a direct-detection spectrometer which integrates all the components of a diffraction-grating spectrometer onto a ˜ 10-cm^2 chip through the use of superconducting microstrip transmission lines on a single-crystal silicon substrate. A second-generation µ-Spec is being designed to operate with a spectral resolution of 512 in the submillimeter (500-1000 µm, 300-600 GHz) wavelength range, a band of interest for several spectroscopic applications in astrophysics. High-altitude balloon missions would provide the first test bed to demonstrate the µ-Spec technology in a space-like environment and would be an economically viable venue for multiple observation campaigns. This work reports on the current status of the instrument design and will provide a brief overview of each instrument subsystem. Particular emphasis will be given to the design of the spectrometer's two-dimensional diffractive region, through which the light of different wavelengths is focused on the detectors along the focal plane. An optimization process is employed to generate geometrical configurations of the diffractive region that satisfy specific requirements on spectrometer size, operating spectral range, and performance. An optical design optimized for balloon missions will be presented in terms of geometric layout, spectral purity, and efficiency.

  20. Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

    International Nuclear Information System (INIS)

    Irmler, C.; Bauer, A.; Bergauer, T.; Adamczyk, K.; Bacher, S.; Aihara, H.; Angelini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Aziz, T.; Babu, V.; Bahinipati, S.; Barberio, E.; Baroncelli, Ti.; Baroncelli, To.; Basith, A.K.; Behera, P.K.; Bhuyan, B.; Bilka, T.

    2016-01-01

    The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests

  1. Resistance transition assisted geometry enhanced magnetoresistance in semiconductors

    International Nuclear Information System (INIS)

    Luo, Zhaochu; Zhang, Xiaozhong

    2015-01-01

    Magnetoresistance (MR) reported in some non-magnetic semiconductors (particularly silicon) has triggered considerable interest owing to the large magnitude of the effect. Here, we showed that MR in lightly doped n-Si can be significantly enhanced by introducing two diodes and proper design of the carrier path [Wan, Nature 477, 304 (2011)]. We designed a geometrical enhanced magnetoresistance (GEMR) device whose room-temperature MR ratio reaching 30% at 0.065 T and 20 000% at 1.2 T, respectively, approaching the performance of commercial MR devices. The mechanism of this GEMR is: the diodes help to define a high resistive state (HRS) and a low resistive state (LRS) in device by their openness and closeness, respectively. The ratio of apparent resistance between HRS and LRS is determined by geometry of silicon wafer and electrodes. Magnetic field could induce a transition from LRS to HRS by reshaping potential and current distribution among silicon wafer, resulting in a giant enhancement of intrinsic MR. We expect that this GEMR could be also realized in other semiconductors. The combination of high sensitivity to low magnetic fields and large high-field response should make this device concept attractive to the magnetic field sensing industry. Moreover, because this MR device is based on a conventional silicon/semiconductor platform, it should be possible to integrate this MR device with existing silicon/semiconductor devices and so aid the development of silicon/semiconductor-based magnetoelectronics. Also combining MR devices and semiconducting devices in a single Si/semiconductor chip may lead to some novel devices with hybrid function, such as electric-magnetic-photonic properties. Our work demonstrates that the charge property of semiconductor can be used in the magnetic sensing industry, where the spin properties of magnetic materials play a role traditionally

  2. Semiconductor physics

    CERN Document Server

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  3. Design and operation of a 2-D thin-film semiconductor neutron detector array for use as a beamport monitor

    International Nuclear Information System (INIS)

    Unruh, Troy C.; Bellinger, Steven L.; Huddleston, David E.; McNeil, Walter J.; Patterson, Eric; Sobering, Tim J.; McGregor, Douglas S.

    2009-01-01

    Silicon-based diodes coated with a thin film of neutron reactive materials have been shown to produce excellent low-efficiency neutron detectors. This work employs the same technology, but groups 25 equally sized and spaced diodes on a single 29 mm by 29 mm substrate. A 5x5 array was fabricated and coated with a thin film of 6 LiF for use as a low-efficiency neutron beam monitor. The 5x5 neutron detector array is coupled to an array of amplifiers, allowing the response to be interpreted using a LabVIEW FPGA. The 5x5 array has been characterized in a diffracted neutron beam. This work is a part of on-going research to develop various designs of high- and low-efficiency semiconductor neutron detectors.

  4. Design of a 9K illumina BeadChip for polar bears (Ursus maritimus) from RAD and transcriptome sequencing.

    Science.gov (United States)

    Malenfant, René M; Coltman, David W; Davis, Corey S

    2015-05-01

    Single-nucleotide polymorphisms (SNPs) offer numerous advantages over anonymous markers such as microsatellites, including improved estimation of population parameters, finer-scale resolution of population structure and more precise genomic dissection of quantitative traits. However, many SNPs are needed to equal the resolution of a single microsatellite, and reliable large-scale genotyping of SNPs remains a challenge in nonmodel species. Here, we document the creation of a 9K Illumina Infinium BeadChip for polar bears (Ursus maritimus), which will be used to investigate: (i) the fine-scale population structure among Canadian polar bears and (ii) the genomic architecture of phenotypic traits in the Western Hudson Bay subpopulation. To this end, we used restriction-site associated DNA (RAD) sequencing from 38 bears across their circumpolar range, as well as blood/fat transcriptome sequencing of 10 individuals from Western Hudson Bay. Six-thousand RAD SNPs and 3000 transcriptomic SNPs were selected for the chip, based primarily on genomic spacing and gene function respectively. Of the 9000 SNPs ordered from Illumina, 8042 were successfully printed, and - after genotyping 1450 polar bears - 5441 of these SNPs were found to be well clustered and polymorphic. Using this array, we show rapid linkage disequilibrium decay among polar bears, we demonstrate that in a subsample of 78 individuals, our SNPs detect known genetic structure more clearly than 24 microsatellites genotyped for the same individuals and that these results are not driven by the SNP ascertainment scheme. Here, we present one of the first large-scale genotyping resources designed for a threatened species. © 2014 John Wiley & Sons Ltd.

  5. Optofluidic interferometry chip designs of differential NIR absorbance based sensors for identification and quantification of electrolytes

    NARCIS (Netherlands)

    Steen, Gerrit W.; Wexler, Adam D.; Offerhaus, Herman L.

    2014-01-01

    Design and optimization of integrated photonic NIR absorbance based sensors for identification and quantification of aqueous electrolytes was performed by simulation in MATLAB and Optodesigner. Ten designs are presented and compared for suitability.

  6. Optically coupled semiconductor device

    Energy Technology Data Exchange (ETDEWEB)

    Kumagaya, Naoki

    1988-11-18

    This invention concerns an optically coupled semiconductor device using the light as input signal and a MOS transistor for the output side in order to control on-off of the output side by the input signal which is insulated from the output. Concerning this sort of element, when a MOS transistor and a load resistance are planned to be accumulated on the same chip, a resistor and control of impurity concentration of the channel, etc. become necessary despite that the only formation of a simple P-N junction is enough, for a solar cell, hence cost reduction thereof cannot be done. In order to remove this defect, this invention offers an optically coupled semiconductor device featuring that two solar cells are connected in reverse parallel between the gate sources of the output MOS transistors and an operational light emitting element is individually set facing a respective solar cell. 4 figs.

  7. K-band single-chip electron spin resonance detector.

    Science.gov (United States)

    Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

    2012-04-01

    We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

  8. Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

    Science.gov (United States)

    McConkey, M. L.

    1984-12-01

    A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

  9. Design and simulation of a fast Josephson junction on-chip gated clock for frequency and time analysis

    International Nuclear Information System (INIS)

    Ruby, R.C.

    1991-01-01

    This paper reports that as the sophistication and speed of digital communication systems increase, there is a corresponding demand for more sophisticated and faster measurement instruments. One such instrument new on the market is the HP 5371A Frequency and Time Interval Analyzer (FTIA). Such an instrument is analogous to a conventional oscilloscope. Whereas the oscilloscope measures waveform amplitudes as a function of time, the FTIA measures phase, frequency, or timing events as functions of time. These applications are useful in such diverse areas as spread-spectrum radar, chirp filter designs, disk-head evaluation, and timing jitter analysis. The on-chip clock designed for this application uses a single Josephson Junction as the clock and a resonator circuit to fix the frequency. A zero-crossing detector is used to start and stop the clock. A SFQ counter is used to count the pulses generated by the clock and a reset circuit is used to reset the clock. Extensive simulations and modeling have been done based on measured values obtained from our Nb/Al 2 O 3 /Al/Nb process

  10. Easy simulation and design of on-chip inductors in standard CMOS processes

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jørgensen, Allan

    1998-01-01

    This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design...... close-to-optimal inductors without the use of electromagnetic simulators...

  11. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  12. Reliable CPS design for mitigating semiconductor and battery aging in electric vehicles

    NARCIS (Netherlands)

    Chang, W.; Proebstl, A.; Goswami, D.; Zamani, M.; Chakraborty, S.

    2015-01-01

    Reliability and performance of cyber-physical systems (CPS) in electric vehicles (EVs) are influenced by three design aspects: (i) controller design, (ii) battery usage, i.e., Battery rate capacity and aging effects, (iii) processor aging of the in-vehicle embedded platform. In this paper, we

  13. Introduction to Semiconductor Devices

    Science.gov (United States)

    Brennan, Kevin F.

    2005-03-01

    This volume offers a solid foundation for understanding the most important devices used in the hottest areas of electronic engineering today, from semiconductor fundamentals to state-of-the-art semiconductor devices in the telecommunications and computing industries. Kevin Brennan describes future approaches to computing hardware and RF power amplifiers, and explains how emerging trends and system demands of computing and telecommunications systems influence the choice, design and operation of semiconductor devices. In addition, he covers MODFETs and MOSFETs, short channel effects, and the challenges faced by continuing miniaturization. His book is both an excellent senior/graduate text and a valuable reference for practicing engineers and researchers.

  14. Physics of semiconductor lasers

    CERN Document Server

    Mroziewicz, B; Nakwaski, W

    2013-01-01

    Written for readers who have some background in solid state physics but do not necessarily possess any knowledge of semiconductor lasers, this book provides a comprehensive and concise account of fundamental semiconductor laser physics, technology and properties. The principles of operation of these lasers are therefore discussed in detail with the interrelations between their design and optical, electrical and thermal properties. The relative merits of a large number of laser structures and their parameters are described to acquaint the reader with the various aspects of the semiconductor l

  15. Drag &Drop, Mixed-Methodology-based Lab-on-Chip Design Optimization Software, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall objective is to develop a ?mixed-methodology?, drag and drop, component library (fluidic-lego)-based, system design and optimization tool for complex...

  16. Organic semiconductors in sensor applications

    CERN Document Server

    Malliaras, George; Owens, Róisín

    2008-01-01

    Organic semiconductors offer unique characteristics such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing, and facile integration with chemical and biological functionalities. These characteristics have prompted the application of organic semiconductors and their devices in physical, chemical, and biological sensors. This book covers this rapidly emerging field by discussing both optical and electrical sensor concepts. Novel transducers based on organic light-emitting diodes and organic thin-film transistors, as well as systems-on-a-chip architectures are presented. Functionalization techniques to enhance specificity are outlined, and models for the sensor response are described.

  17. Design and Research of Intelligent Remote Control Fan Based on Single Chip Microcomputer and Bluetooth Technology

    Directory of Open Access Journals (Sweden)

    Zhang Xue-Xia

    2017-01-01

    Full Text Available This paper is designed for intelligent remote control fans. The design of the microcontroller as the core, the sensor, Bluetooth and Andrews system applied to the design of intelligent remote control fan. According to the temperature sensor to achieve the indoor temperature collection, to achieve and set the temperature comparison, thus affecting the fan speed. At the same time, the system according to the infrared sensor components to detect external factors, in order to achieve the running or stopping of the fan, that is, to achieve intelligent control of the fan. In addition, the system achieve the Bluetooth and mobile phone Andrews system of effective combination, and through the software program to complete the fan remote operation and wind speed control.

  18. Radiation effects in semiconductors

    CERN Document Server

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  19. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  20. A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed For Evolvability

    DEFF Research Database (Denmark)

    Patou, François; Dimaki, Maria; Svendsen, Winnie Edith

    2015-01-01

    for this work. We introduce a smart-mobile and LoC-based system architecture designed for evolvability. By propagating LoC programmability, instrumentation, and control tools to the highlevel abstraction smart-mobile software layer, our architecture facilitates the realisation of new use...

  1. Design and Characterization of a 52K SNP Chip for Goats

    NARCIS (Netherlands)

    Tosser-klopp, G.; Bardou, P.; Bouchez, O.; Cabau, C.; Crooijmans, R.P.M.A.; Dong, Y.; Donnadieu-Tonon, C.; Eggen, A.; Heuven, H.C.M.; Jamli, S.; Jiken, A.J.; Klopp, C.; Lawley, C.T.; McEwen, J.; Martin, P.; Moreno, C.R.; Mulsant, P.; Nabihoudine, I.; Pailhoux, E.; Palhiere, I.; Rupp, R.; Sarry, J.; Sayre, B.L.; Tircazes, A.; Wang, J.; Wang, W.; Zhang, W.G.

    2014-01-01

    The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a

  2. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    Energy Technology Data Exchange (ETDEWEB)

    Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

    2005-02-11

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

  3. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    International Nuclear Information System (INIS)

    Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

    2005-01-01

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

  4. α-particle shielding of semiconductor device

    International Nuclear Information System (INIS)

    McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

    1981-01-01

    Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

  5. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind

    International Nuclear Information System (INIS)

    Pajuelo, L.

    2015-01-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  6. Design of indoor temperature and humidity detection system based on single chip microcomputer

    Science.gov (United States)

    Fu, Xiuwei; Fu, Li; Ma, Tianhui

    2018-03-01

    The indoor temperature and humidity detection system based on STC15F2K60S2 is designed in this paper. The temperature and humidity sensor DHT22 to monitor the indoor temperature and humidity are used, and the temperature and humidity data to the user's handheld device are wirelessly transmitted, when the temperature reaches or exceeds the user set the temperature alarm value, and the system sound and light alarm, to remind the user.

  7. Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

    International Nuclear Information System (INIS)

    Chen Haijin; Lu Shengli; Shi Longxing

    2009-01-01

    A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

  8. Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

    OpenAIRE

    Lee, Da-Sheng

    2010-01-01

    Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DN...

  9. [The system design of an intraperitoneal perfusion machine for hyperthermic chemotherapy based on single chip microcomputer].

    Science.gov (United States)

    Zhang, Zhiyong; Yang, Xuandong; Li, Kaiyang

    2005-06-01

    A new kind of method for intraperitoneal hyperthermic chemotherapy has been proved to be very effective for the therapy of gastrointestinal cancer. In this article is reported an intraperitoneal perfusion machine which is designed for instituting the treatment. The liquor of the chemotherapy drug is infused into the abdomen after being heated by heating system; the liquor flows out of the abdomen is abandoned. The temperature of heating and the velocity of flow are controlled by MCU, thus the temperature of the liquor of the chemotherapy drug in the abdomen can be adjusted to the most favarable temperature.

  10. Designing defect-based qubit candidates in wide-gap binary semiconductors for solid-state quantum technologies

    Science.gov (United States)

    Seo, Hosung; Ma, He; Govoni, Marco; Galli, Giulia

    2017-12-01

    The development of novel quantum bits is key to extending the scope of solid-state quantum-information science and technology. Using first-principles calculations, we propose that large metal ion-vacancy pairs are promising qubit candidates in two binary crystals: 4 H -SiC and w -AlN. In particular, we found that the formation of neutral Hf- and Zr-vacancy pairs is energetically favorable in both solids; these defects have spin-triplet ground states, with electronic structures similar to those of the diamond nitrogen-vacancy center and the SiC divacancy. Interestingly, they exhibit different spin-strain coupling characteristics, and the nature of heavy metal ions may allow for easy defect implantation in desired lattice locations and ensure stability against defect diffusion. To support future experimental identification of the proposed defects, we report predictions of their optical zero-phonon line, zero-field splitting, and hyperfine parameters. The defect design concept identified here may be generalized to other binary semiconductors to facilitate the exploration of new solid-state qubits.

  11. An efficient strategy for designing ambipolar organic semiconductor material: Introducing dehydrogenated phosphorus atoms into pentacene core

    Science.gov (United States)

    Tang, Xiao-Dan

    2017-09-01

    The charge transport properties of phosphapentacene (P-PEN) derivatives were systematically explored by theoretical calculation. The dehydrogenated P-PENs have reasonable frontier molecular orbital energy levels to facilitate both electron and hole injection. The reduced reorganization energies of dehydrogenated P-PENs could be intimately connected to the bonding nature of phosphorus atoms. From the idea of homology modeling, the crystal structure of TIPSE-4P-2p is constructed and fully optimized. Fascinatingly, TIPSE-4P-2p shows the intrinsic property of ambipolar transport in both hopping and band models. Thus, introducing dehydrogenated phosphorus atoms into pentacene core could be an efficient strategy for designing ambipolar material.

  12. Dynamic spin polarization by orientation-dependent separation in a ferromagnet-semiconductor hybrid

    Science.gov (United States)

    Korenev, V. L.; Akimov, I. A.; Zaitsev, S. V.; Sapega, V. F.; Langer, L.; Yakovlev, D. R.; Danilov, Yu. A.; Bayer, M.

    2012-07-01

    Integration of magnetism into semiconductor electronics would facilitate an all-in-one-chip computer. Ferromagnet/bulk semiconductor hybrids have been, so far, mainly considered as key devices to read out the ferromagnetism by means of spin injection. Here we demonstrate that a Mn-based ferromagnetic layer acts as an orientation-dependent separator for carrier spins confined in a semiconductor quantum well that is set apart from the ferromagnet by a barrier only a few nanometers thick. By this spin-separation effect, a non-equilibrium electron-spin polarization is accumulated in the quantum well due to spin-dependent electron transfer to the ferromagnet. The significant advance of this hybrid design is that the excellent optical properties of the quantum well are maintained. This opens up the possibility of optical readout of the ferromagnet's magnetization and control of the non-equilibrium spin polarization in non-magnetic quantum wells.

  13. Bacteria inside semiconductors as potential sensor elements: biochip progress.

    Science.gov (United States)

    Sah, Vasu R; Baier, Robert E

    2014-06-24

    It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

  14. Materials Design via Optimized Intramolecular Noncovalent Interactions for High-Performance Organic Semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Xiaojie; Liao, Qiaogan; Manley, Eric F.; Wu, Zishan; Wang, Yulun; Wang, Weida; Yang, Tingbin; Shin, Young-Eun; Cheng, Xing; Liang, Yongye; Chen, Lin X.; Baeg, Kang-Jun; Marks, Tobin J.; Guo, Xugang

    2016-03-15

    We report the design, synthesis, and implemention in semiconducting polymers of a novel head-to-head linkage containing the TRTOR (3-alkyl-3'-alkoxy-2,2'-bithiophene) donor subunit having a single strategically optimized, planarizing noncovalent S···O interaction. Diverse complementary thermal, optical, electrochemical, X-ray scattering, electrical, photovoltaic, and electron microscopic characterization techniques are applied to establish structure-property correlations in a TRTOR-based polymer series. In comparison to monomers having double S···O interactions, replacing one alkoxy substituent with a less electron-donating alkyl one yields TRTOR-based polymers with significantly depressed (0.2-0.3 eV) HOMOs. Furthermore, the weaker single S···O interaction and greater TRTOR steric encumberance enhances materials processability without sacrificing backbone planarity. From another perspective, TRTOR has comparable electronic properties to ring-fused 5Hdithieno[ 3,2-b:2',3'-d]pyran (DTP) subunits, but a centrosymmetric geometry which promotes a more compact and ordered structure than bulkier, axisymmetric DTP. Compared to monosubstituted TTOR (3-alkoxy-2,2'-bithiophene), alkylation at the TRTOR bithiophene 3-position enhances conjugation and polymer crystallinity with contracted π-π stacking. Grazing incidence wide-angle X-ray scattering (GIWAXS) data reveal that the greater steric hindrance and the weaker single S···O interaction are not detrimental to close packing and high crystallinity. As a proof of materials design, copolymerizing TRTOR with phthalimides yields copolymers with promising thin-film transistor mobility as high as 0.42 cm2/(V·s) and 6.3% power conversion efficiency in polymer solar cells, the highest of any phthalimide copolymers reported to date. The depressed TRTOR HOMOs imbue these polymers with substantially increased Ion/Ioff ratios and Voc’s versus analogous subunits with multiple electron donating

  15. Materials Design via Optimized Intramolecular Noncovalent Interactions for High-Performance Organic Semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Xiaojie [Shenzhen Key Laboratory; Liao, Qiaogan [Shenzhen Key Laboratory; Manley, Eric F. [Department; Chemical; Wu, Zishan [Shenzhen Key Laboratory; Wang, Yulun [Shenzhen Key Laboratory; Wang, Weida [Shenzhen Key Laboratory; Yang, Tingbin [Shenzhen Key Laboratory; Shin, Young-Eun [Department; Cheng, Xing [Shenzhen Key Laboratory; Liang, Yongye [Shenzhen Key Laboratory; Chen, Lin X. [Department; Chemical; Baeg, Kang-Jun [Department; Marks, Tobin J. [Department; Guo, Xugang [Shenzhen Key Laboratory

    2016-03-15

    We report the design, synthesis, and implemention in semiconducting polymers of a novel head-to-head linkage containing the TRTOR (3-alkyl-3'-alkoxy-2,2'-bithiophene) donor subunit having a single strategically optimized, planarizing noncovalent S···O interaction. Diverse complementary thermal, optical, electrochemical, X-ray scattering, electrical, photovoltaic, and electron microscopic characterization techniques are applied to establish structure–property correlations in a TRTOR-based polymer series. In comparison to monomers having double S···O interactions, replacing one alkoxy substituent with a less electron-donating alkyl one yields TRTOR-based polymers with significantly depressed (0.2–0.3 eV) HOMOs. Furthermore, the weaker single S···O interaction and greater TRTOR steric encumberance enhances materials processability without sacrificing backbone planarity. From another perspective, TRTOR has comparable electronic properties to ring-fused 5H-dithieno[3,2-b:2',3'-d]pyran (DTP) subunits, but a centrosymmetric geometry which promotes a more compact and ordered structure than bulkier, axisymmetric DTP. Compared to monosubstituted TTOR (3-alkoxy-2,2'-bithiophene), alkylation at the TRTOR bithiophene 3-position enhances conjugation and polymer crystallinity with contracted π–π stacking. Grazing incidence wide-angle X-ray scattering (GIWAXS) data reveal that the greater steric hindrance and the weaker single S···O interaction are not detrimental to close packing and high crystallinity. As a proof of materials design, copolymerizing TRTOR with phthalimides yields copolymers with promising thin-film transistor mobility as high as 0.42 cm2/(V·s) and 6.3% power conversion efficiency in polymer solar cells, the highest of any phthalimide copolymers reported to date. The depressed TRTOR HOMOs imbue these polymers with substantially increased Ion/Ioff ratios and Voc’s versus analogous subunits with multiple electron

  16. Monitoring bacterial biofilms with a microfluidic flow chip designed for imaging with white-light interferometry

    Energy Technology Data Exchange (ETDEWEB)

    Brann, Michelle; Suter, Jonathan D.; Addleman, R. Shane; Larimer, Curtis

    2017-07-01

    There is a need for imaging and sensing instrumentation that can monitor transitions in biofilm structure in order to better understand biofilm development and emergent properties such as anti-microbial resistance. Herein, we expanded on our previously reported technique for measuring and monitoring the thickness and topology of live biofilms using white-light interferometry (WLI). A flow cell designed for WLI enabled the use of this non-disruptive imaging method for the capture of high resolution three-dimensional profile images of biofilm growth over time. The fine axial resolution (3 nm) and wide field of view (>1 mm by 1 mm) enabled detection of biofilm formation as early as three hours after inoculation of the flow cell with a live bacterial culture (Pseudomonas fluorescens). WLI imaging facilitated monitoring the early stages of biofilm development and subtle variations in the structure of mature biofilms. Minimally-invasive imaging enabled monitoring of biofilm structure with surface metrology metrics (e.g., surface roughness). The system was used to observe a transition in biofilm structure that occurred in response to expsoure to a common antiseptic. In the future, WLI and the biofilm imaging cell described herein may be used to test the effectiveness of biofilm-specific therapies to combat common diseases associated with biofilm formation such as cystic fibrosis and periodontitis.

  17. Semiconductor Ion Implanters

    International Nuclear Information System (INIS)

    MacKinnon, Barry A.; Ruffell, John P.

    2011-01-01

    In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion! Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intel product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.

  18. Design and implementation of a hybrid circuit system for micro sensor signal processing

    International Nuclear Information System (INIS)

    Wang Zhuping; Chen Jing; Liu Ruqing

    2011-01-01

    This paper covers a micro sensor analog signal processing circuit system (MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board. The ultimate aim is to form a hybrid circuit used for mixed-signal processing, which can be applied to a micro sensor flow monitoring system. (semiconductor integrated circuits)

  19. Semiconductor Manufacturing equipment introduction

    International Nuclear Information System (INIS)

    Im, Jong Sun

    2001-02-01

    This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

  20. Hybrid Organic-Inorganic Perovskites: Structural Diversity and Opportunities for Semiconductor Design

    Science.gov (United States)

    Mitzi, David

    Photovoltaic (PV) devices based on three-dimensional perovskites, (Cs, MA, FA)Pb(I, Br)3 (MA =methylammonium, FA =formamidinium), have attracted substantial recent interest, because of the unprecedented rise in power conversion efficiency to values above 20%, which in turn is made possible by the near ideal band gap, strong optical absorption, high carrier mobilities, long minority carrier lifetimes, and relatively benign defects and grain boundaries for the absorbers. Some of the same properties that render these materials near-ideal for PV, also make them attractive for LED and other optoelectronic applications. Despite the high levels of device performance, the incorporation of the heavy metal lead, coupled with issues of device stability and electrical hysteresis pose challenges for commercializing these exciting technologies. This talk will provide a perspective on and discuss recent advances related to the broader perovskite family, focusing on the extraordinary structural/chemical diversity, including ability to control structural/electronic dimensionality, substitute on the organic cation, metal or halogen sites, and prospects of multi-functionality arising from separately engineered organic/inorganic structural components (e.g., see). Further exploration within this perovskite structural and chemical space offers exciting opportunities for future energy and electronic materials design. This work has been financially supported by the Office of Energy Efficiency and Renewable Energy (EERE), U.S. Dept. of Energy, under Award Number DE-EE0006712.

  1. The design and fabrication of supramolecular semiconductor nanowires formed by benzothienobenzothiophene (BTBT)-conjugated peptides.

    Science.gov (United States)

    Khalily, Mohammad Aref; Usta, Hakan; Ozdemir, Mehmet; Bakan, Gokhan; Dikecoglu, F Begum; Edwards-Gayle, Charlotte; Hutchinson, Jessica A; Hamley, Ian W; Dana, Aykutlu; Guler, Mustafa O

    2018-05-18

    π-Conjugated small molecules based on a [1]benzothieno[3,2-b]benzothiophene (BTBT) unit are of great research interest in the development of solution-processable semiconducting materials owing to their excellent charge-transport characteristics. However, the BTBT π-core has yet to be demonstrated in the form of electro-active one-dimensional (1D) nanowires that are self-assembled in aqueous media for potential use in bioelectronics and tissue engineering. Here we report the design, synthesis, and self-assembly of benzothienobenzothiophene (BTBT)-peptide conjugates, the BTBT-peptide (BTBT-C3-COHN-Ahx-VVAGKK-Am) and the C8-BTBT-peptide (C8-BTBT-C3-COHN-Ahx-VVAGKK-Am), as β-sheet forming amphiphilic molecules, which self-assemble into highly uniform nanofibers in water with diameters of 11-13(±1) nm and micron-size lengths. Spectroscopic characterization studies demonstrate the J-type π-π interactions among the BTBT molecules within the hydrophobic core of the self-assembled nanofibers yielding an electrical conductivity as high as 6.0 × 10-6 S cm-1. The BTBT π-core is demonstrated, for the first time, in the formation of self-assembled peptide 1D nanostructures in aqueous media for potential use in tissue engineering, bioelectronics and (opto)electronics. The conductivity achieved here is one of the highest reported to date in a non-doped state.

  2. Novel phase diagram behavior and materials design in heterostructural semiconductor alloys.

    Science.gov (United States)

    Holder, Aaron M; Siol, Sebastian; Ndione, Paul F; Peng, Haowei; Deml, Ann M; Matthews, Bethany E; Schelhas, Laura T; Toney, Michael F; Gordon, Roy G; Tumas, William; Perkins, John D; Ginley, David S; Gorman, Brian P; Tate, Janet; Zakutayev, Andriy; Lany, Stephan

    2017-06-01

    Structure and composition control the behavior of materials. Isostructural alloying is historically an extremely successful approach for tuning materials properties, but it is often limited by binodal and spinodal decomposition, which correspond to the thermodynamic solubility limit and the stability against composition fluctuations, respectively. We show that heterostructural alloys can exhibit a markedly increased range of metastable alloy compositions between the binodal and spinodal lines, thereby opening up a vast phase space for novel homogeneous single-phase alloys. We distinguish two types of heterostructural alloys, that is, those between commensurate and incommensurate phases. Because of the structural transition around the critical composition, the properties change in a highly nonlinear or even discontinuous fashion, providing a mechanism for materials design that does not exist in conventional isostructural alloys. The novel phase diagram behavior follows from standard alloy models using mixing enthalpies from first-principles calculations. Thin-film deposition demonstrates the viability of the synthesis of these metastable single-phase domains and validates the computationally predicted phase separation mechanism above the upper temperature bound of the nonequilibrium single-phase region.

  3. Designing small molecule polyaromatic p- and n-type semiconductor materials for organic electronics

    KAUST Repository

    Collis, Gavin E.

    2015-12-22

    By combining computational aided design with synthetic chemistry, we are able to identify core 2D polyaromatic small molecule templates with the necessary optoelectronic properties for p- and n-type materials. By judicious selection of the functional groups, we can tune the physical properties of the material making them amenable to solution and vacuum deposition. In addition to solubility, we observe that the functional group can influence the thin film molecular packing. By developing structure-property relationships (SPRs) for these families of compounds we observe that some compounds are better suited for use in organic solar cells, while others, varying only slightly in structure, are favoured in organic field effect transistor devices. We also find that the processing conditions can have a dramatic impact on molecular packing (i.e. 1D vs 2D polymorphism) and charge mobility; this has implications for material and device long term stability. We have developed small molecule p- and n-type materials for organic solar cells with efficiencies exceeding 2%. Subtle variations in the functional groups of these materials produces p- and ntype materials with mobilities higher than 0.3 cm2/Vs. We are also interested in using our SPR approach to develop materials for sensor and bioelectronic applications.

  4. Optimizing the design and analysis of cryogenic semiconductor dark matter detectors for maximum sensitivity

    Energy Technology Data Exchange (ETDEWEB)

    Pyle, Matt Christopher [Stanford Univ., CA (United States)

    2012-01-01

    In this thesis, we illustrate how the complex E- field geometry produced by interdigitated electrodes at alternating voltage biases naturally encodes 3D fiducial volume information into the charge and phonon signals and thus is a natural geometry for our next generation dark matter detectors. Secondly, we will study in depth the physics of import to our devices including transition edge sensor dynamics, quasi- particle dynamics in our Al collection fins, and phonon physics in the crystal itself so that we can both understand the performance of our previous CDMS II device as well as optimize the design of our future devices. Of interest to the broader physics community is the derivation of the ideal athermal phonon detector resolution and it's T3 c scaling behavior which suggests that the athermal phonon detector technology developed by CDMS could also be used to discover coherent neutrino scattering and search for non-standard neutrino interaction and sterile neutrinos. These proposed resolution optimized devices can also be used in searches for exotic MeV-GeV dark matter as well as novel background free searches for 8GeV light WIMPs.

  5. Semiconductor spintronics

    CERN Document Server

    Xia, Jianbai; Chang, Kai

    2012-01-01

    Semiconductor Spintronics, as an emerging research discipline and an important advanced field in physics, has developed quickly and obtained fruitful results in recent decades. This volume is the first monograph summarizing the physical foundation and the experimental results obtained in this field. With the culmination of the authors' extensive working experiences, this book presents the developing history of semiconductor spintronics, its basic concepts and theories, experimental results, and the prospected future development. This unique book intends to provide a systematic and modern foundation for semiconductor spintronics aimed at researchers, professors, post-doctorates, and graduate students, and to help them master the overall knowledge of spintronics.

  6. Fiscal 2000 research achievement report on the research and development of advanced design technologies for system-on-chip; 2000 nendo system on chip sentan sekkei gijutsu no kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-05-01

    Efforts were made to develop technologies for rapid improvement in SoC (system on chip) design productivity. In concrete terms, the concept of V-core (virtual core) was introduced into SoC design for the establishment of reusing technology and design automation in the uppermost stream region of designing. Activities were conducted in the two fields of (1) research and development of V-core based design technology and (2) research and development of a V-core database. Efforts exerted in field (1) aimed at the research and development of system specifications description technology, architecture generation technology, soft V-core internal structure optimization technology, optimized RTL (register transfer level) description generation technology, and system performance verification technology. In field (2), efforts were made to develop core database technology, core development support tools, core verification technology, and design assets verification technology. The system specifications description technology is a technique to define SoC system level specifications (degree of model abstraction). (NEDO)

  7. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  8. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  9. Microelectronics used for Semiconductor Imaging Detectors

    CERN Document Server

    Heijne, Erik H M

    2010-01-01

    Semiconductor crystal technology, microelectronics developments and nuclear particle detection have been in a relation of symbiosis, all the way from the beginning. The increase of complexity in electronics chips can now be applied to obtain much more information on the incident nuclear radiation. Some basic technologies are described, in order to acquire insight in possibilities and limitations for the most recent detectors.

  10. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  11. Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

    Science.gov (United States)

    Seiler, David G.

    1997-10-01

    A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

  12. Semiconductor spintronics

    International Nuclear Information System (INIS)

    Fabian, J.; Abiague, A.M.; Ertler, Ch.; Stano, P.; Zutic, I.

    2007-01-01

    Spintronics refers commonly to phenomena in which the spin of electrons in a solid state environment plays the determining role. In a more narrow sense spintronics is an emerging research field of electronics: spintronics devices are based on a spin control of electronics, or on an electrical and optical control of spin of magnetism. While metal spintronics has already found its niche in the computer industry - giant magnetoresistance systems are used as hard disk read heads - semiconductor spintronics is vet demonstrate its full potential. This review presents selected themes of semiconductor spintronics, introducing important concepts in spin transport, spin transport, spin injection. Silsbee-Johnson spin-charge coupling, and spin-dependent tunneling, as well as spin relaxation and spin dynamics. The most fundamental spin-dependent interaction in nonmagnetic semiconductors is spin-orbit coupling. Depending on the crystal symmetries of the material, as well as on the structural properties of semiconductor based heterostructures, the spin-orbit coupling takes on different functional forms, giving a nice playground of effective spin-orbit Hamiltonians. The effective Hamiltonians for the most relevant classes of materials and heterostructures are derived here from realistic electronic band structure descriptions. Most semiconductor device systems are still theoretical concepts, waiting for experimental demonstrations. A review of selected proposed, and a few demonstrated devices is presented, with detailed description of two important classes: magnetic resonant tunnel structures and bipolar magnetic diodes and transistors. In view of the importance of ferromagnetic semiconductor material, a brief discussion of diluted magnetic semiconductors is included. In most cases the presentation is of tutorial style, introducing the essential theoretical formalism at an accessible level, with case-study-like illustrations of actual experimental results, as well as with brief

  13. Hydrogen-bonding versus .pi.-.pi. stacking in the design of organic semiconductors: from dyes to oligomers

    Czech Academy of Sciences Publication Activity Database

    Gospodinova, Natalia; Tomšík, Elena

    2015-01-01

    Roč. 43, April (2015), s. 33-47 ISSN 0079-6700 R&D Projects: GA ČR(CZ) GA13-00270S; GA ČR GPP108/11/P763 Institutional support: RVO:61389013 Keywords : organic semiconductors * hydrogen bonds * nematic liquid crystals Subject RIV: CD - Macromolecular Chemistry Impact factor: 27.184, year: 2015

  14. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  15. How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

    International Nuclear Information System (INIS)

    Pfeiffer, K.F.G.

    2003-01-01

    Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

  16. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  17. Oxide semiconductors

    CERN Document Server

    Svensson, Bengt G; Jagadish, Chennupati

    2013-01-01

    Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scient

  18. Semiconductor statistics

    CERN Document Server

    Blakemore, J S

    1962-01-01

    Semiconductor Statistics presents statistics aimed at complementing existing books on the relationships between carrier densities and transport effects. The book is divided into two parts. Part I provides introductory material on the electron theory of solids, and then discusses carrier statistics for semiconductors in thermal equilibrium. Of course a solid cannot be in true thermodynamic equilibrium if any electrical current is passed; but when currents are reasonably small the distribution function is but little perturbed, and the carrier distribution for such a """"quasi-equilibrium"""" co

  19. Field testing for cosmic ray soft errors in semiconductor memories

    International Nuclear Information System (INIS)

    O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

    1996-01-01

    This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

  20. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  1. Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

    Science.gov (United States)

    Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

    1997-01-01

    The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

  2. Semiconductor Detectors

    International Nuclear Information System (INIS)

    Cortina, E.

    2007-01-01

    Particle detectors based on semiconductor materials are among the few devices used for particle detection that are available to the public at large. In fact we are surrounded by them in our daily lives: they are used in photoelectric cells for opening doors, in digital photographic and video camera, and in bar code readers at supermarket cash registers. (Author)

  3. Development of semiconductor electronics

    International Nuclear Information System (INIS)

    Bardeen, John.

    1977-01-01

    In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

  4. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  5. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  6. Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

    Directory of Open Access Journals (Sweden)

    Vasu R. Sah

    2014-06-01

    Full Text Available It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities’ features at the time of first production of these potential biochips.

  7. Embedded software design and programming of multiprocessor system-on-chip simulink and system C case studies

    CERN Document Server

    Popovici, Katalin; Jerraya, Ahmed A; Wolf, Marilyn

    2010-01-01

    Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access).Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tediou

  8. Analysis and simulation of semiconductor devices

    CERN Document Server

    Selberherr, Siegfried

    1984-01-01

    The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

  9. Electronic structure of semiconductor interfaces

    Energy Technology Data Exchange (ETDEWEB)

    Herman, F

    1983-02-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered.

  10. Electronic structure of semiconductor interfaces

    International Nuclear Information System (INIS)

    Herman, F.

    1983-01-01

    The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered. (Author) [pt

  11. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  12. Semiconductor sensors

    International Nuclear Information System (INIS)

    Hartmann, Frank

    2011-01-01

    Semiconductor sensors have been around since the 1950s and today, every high energy physics experiment has one in its repertoire. In Lepton as well as Hadron colliders, silicon vertex and tracking detectors led to the most amazing physics and will continue doing so in the future. This contribution tries to depict the history of these devices exemplarily without being able to honor all important developments and installations. The current understanding of radiation damage mechanisms and recent R and D topics demonstrating the future challenges and possible technical solutions for the SLHC detectors are presented. Consequently semiconductor sensor candidates for an LHC upgrade and a future linear collider are also briefly introduced. The work presented here is a collage of the work of many individual silicon experts spread over several collaborations across the world.

  13. Semiconductor Optics

    CERN Document Server

    Klingshirn, Claus F

    2012-01-01

    This updated and enlarged new edition of Semiconductor Optics provides an introduction to and an overview of semiconductor optics from the IR through the visible to the UV, including linear and nonlinear optical properties, dynamics, magneto and electrooptics, high-excitation effects and laser processes, some applications, experimental techniques and group theory. The mathematics is kept as elementary as possible, sufficient for an intuitive understanding of the experimental results and techniques treated. The subjects covered extend from physics to materials science and optoelectronics. Significantly updated chapters add coverage of current topics such as electron hole plasma, Bose condensation of excitons and meta materials. Over 120 problems, chapter introductions and a detailed index make it the key textbook for graduate students in physics. The mathematics is kept as elementary as possible, sufficient for an intuitive understanding of the experimental results and techniques treated. The subjects covered ...

  14. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  15. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    DEFF Research Database (Denmark)

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... and display ultrasensitive mass detection in air. A mass sensitivity of 4 ag/Hz has been determined in air by placing a single glycerine drop, having a measured weight of 57 fg, at the apex of a cantilever and subsequently measuring a frequency shift of 14.8 kHz. CMOS integration enables electrostatic...

  16. Semiconductor annealing

    International Nuclear Information System (INIS)

    Young, J.M.; Scovell, P.D.

    1982-01-01

    A process for annealing crystal damage in ion implanted semiconductor devices in which the device is rapidly heated to a temperature between 450 and 900 0 C and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device may be heated on a graphite element mounted between electrodes in an inert atmosphere in a chamber. (author)

  17. Design and Implementation of 8051 Single-Chip Microcontroller for Stationary 1.0 kW PEM Fuel Cell System

    Directory of Open Access Journals (Sweden)

    Pei-Hsing Huang

    2014-01-01

    Full Text Available Proton exchange membrane fuel cells (PEMFCs have attracted significant interest as a potential green energy source. However, if the performance of such systems is to be enhanced, appropriate control strategies must be applied. Accordingly, the present study proposes a sophisticated control system for a 1.0 kW PEMFC system comprising a fuel cell stack, an auxiliary power supply, a DC-DC buck converter, and a DC-AC inverter. The control system is implemented using an 8051 single-chip microcontroller and is designed to optimize the system performance and safety in both the startup phase and the long-term operation phase. The major features of the proposed control system are described and the circuit diagrams required for its implementation introduced. In addition, the touch-sensitive, intuitive human-machine interface is introduced and typical screens are presented. Finally, the electrical characteristics of the PEMFC system are briefly examined. Overall, the results confirm that the single-chip microcontroller presented in this study has significant potential for commercialization in the near future.

  18. Design strategy for air-stable organic semiconductors applicable to high-performance field-effect transistors

    Directory of Open Access Journals (Sweden)

    Kazuo Takimiya et al

    2007-01-01

    Full Text Available Electronic structure of air-stable, high-performance organic field-effect transistor (OFET material, 2,7-dipheneyl[1]benzothieno[3,2-b]benzothiophene (DPh-BTBT, was discussed based on the molecular orbital calculations. It was suggested that the stability is originated from relatively low-lying HOMO level, despite the fact that the molecule contains highly π-extended aromatic core ([1]benzothieno[3,2-b]benzothiophene, BTBT with four fused aromatic rings like naphthacene. This is rationalized by the consideration that the BTBT core is not isoelectronic with naphthacene but with chrysene, a cata-condensed phene with four benzene rings. It is well known that the acene-type compound is unstable among its structural isomers with the same number of benzene rings. Therefore, polycyclic aromatic compounds possessing the phene-substructure will be good candidates for stable organic semiconductors. Considering synthetic easiness, we suggest that the BTBT-substructure is the molecular structure of choice for developing air-stable organic semiconductors.

  19. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  20. The single chip microcomputer technique in an intelligent nuclear instrument

    International Nuclear Information System (INIS)

    Wang Tieliu; Sun Punan; Wang Ying

    1995-01-01

    The authors present that how to acquire and process the output signals from the nuclear detector adopting single chip microcomputer technique, including working principles and the designing method of the computer's software and hardware in the single chip microcomputer instrument

  1. Semiconductor annealing

    International Nuclear Information System (INIS)

    Young, J.M.; Scovell, P.D.

    1981-01-01

    A process for annealing crystal damage in ion implanted semiconductor devices is described in which the device is rapidly heated to a temperature between 450 and 600 0 C and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device may be heated on a graphite element mounted between electrodes in an inert atmosphere in a chamber. The process may be enhanced by the application of optical radiation from a Xenon lamp. (author)

  2. Miniature interferometer for refractive index measurement in microfluidic chip

    Science.gov (United States)

    Chen, Minghui; Geiser, Martial; Truffer, Frederic; Song, Chengli

    2012-12-01

    The design and development of the miniaturized interferometer for measurement of the refractive index or concentration of sub-microliter volume aqueous solution in microfludic chip is presented. It is manifested by a successful measurement of the refractive index of sugar-water solution, by utilizing a laser diode for light source and the small robust instrumentation for practical implementation. Theoretically, the measurement principle and the feasibility of the system are analyzed. Experimental device is constructed with a diode laser, lens, two optical plate and a complementary metal oxide semiconductor (CMOS). Through measuring the positional changes of the interference fringes, the refractive index change are retrieved. A refractive index change of 10-4 is inferred from the measured image data. The entire system is approximately the size of half and a deck of cards and can operate on battery power for long time.

  3. A CMOS G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor network application

    Energy Technology Data Exchange (ETDEWEB)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing, E-mail: zhiqunli@seu.edu.cn [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2011-05-15

    A G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 {mu}m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  4. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  5. Magnetic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Bihler, Christoph

    2009-04-15

    In this thesis we investigated in detail the properties of Ga{sub 1-x}Mn{sub x}As, Ga{sub 1-x}Mn{sub x}P, and Ga{sub 1-x}Mn{sub x}N dilute magnetic semiconductor thin films with a focus on the magnetic anisotropy and the changes of their properties upon hydrogenation. We applied two complementary spectroscopic techniques to address the position of H in magnetic semiconductors: (i) Electron paramagnetic resonance, which provides direct information on the symmetry of the crystal field of the Mn{sup 2+} atoms and (ii) x-ray absorption fine structure analysis which allows to probe the local crystallographic neighborhood of the absorbing Mn atom via analysing the fine structure at the Mn K absorption edge. Finally, we discussed the obstacles that have to be overcome to achieve Curie temperatures above the current maximum in Ga{sub 1-x}Mn{sub x}As of 185 K. Here, we outlined in detail the generic problem of the formation of precipitates at the example of Ge:MN. (orig.)

  6. Thermal Design of Power Electronic Circuits

    CERN Document Server

    Künzi, R.

    2015-06-15

    The heart of every switched mode converter consists of several switching semiconductor elements. Due to their non-ideal behaviour there are ON state and switching losses heating up the silicon chip. That heat must effectively be transferred to the environment in order to prevent overheating or even destruction of the element. For a cost-effective design, the semiconductors should be operated close to their thermal limits. Unfortunately the chip temperature cannot be measured directly. Therefore a detailed understanding of how losses arise, including their quantitative estimation, is required. Furthermore, the heat paths to the environment must be understood in detail. This paper describes the main issues of loss generation and its transfer to the environment and how it can be estimated by the help of datasheets and/or experiments.

  7. Semiconductor Laser Measurements Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Semiconductor Laser Measurements Laboratory is equipped to investigate and characterize the lasing properties of semiconductor diode lasers. Lasing features such...

  8. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    International Nuclear Information System (INIS)

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-01-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

  9. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    Energy Technology Data Exchange (ETDEWEB)

    Jovanović, B., E-mail: bojan.jovanovic@lirmm.fr, E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L. [LIRMM—University of Montpellier 2/UMR CNRS 5506, 161 Rue Ada, 34095 Montpellier (France)

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  10. Semiconductor physics an introduction

    CERN Document Server

    Seeger, Karlheinz

    1999-01-01

    Semiconductor Physics - An Introduction - is suitable for the senior undergraduate or new graduate student majoring in electrical engineering or physics. It will also be useful to solid-state scientists and device engineers involved in semiconductor design and technology. The text provides a lucid account of charge transport, energy transport and optical processes, and a detailed description of many devices. It includes sections on superlattices and quantum well structures, the effects of deep-level impurities on transport, the quantum Hall effect and the calculation of the influence of a magnetic field on the carrier distribution function. This 6th edition has been revised and corrected, and new sections have been added to different chapters.

  11. Compound semiconductor device modelling

    CERN Document Server

    Miles, Robert

    1993-01-01

    Compound semiconductor devices form the foundation of solid-state microwave and optoelectronic technologies used in many modern communication systems. In common with their low frequency counterparts, these devices are often represented using equivalent circuit models, but it is often necessary to resort to physical models in order to gain insight into the detailed operation of compound semiconductor devices. Many of the earliest physical models were indeed developed to understand the 'unusual' phenomena which occur at high frequencies. Such was the case with the Gunn and IMPATI diodes, which led to an increased interest in using numerical simulation methods. Contemporary devices often have feature sizes so small that they no longer operate within the familiar traditional framework, and hot electron or even quantum­ mechanical models are required. The need for accurate and efficient models suitable for computer aided design has increased with the demand for a wider range of integrated devices for operation at...

  12. Design of a new two-dimensional diluted magnetic semiconductor: Mn-doped GaN monolayer

    International Nuclear Information System (INIS)

    Zhao, Qian; Xiong, Zhihua; Luo, Lan; Sun, Zhenhui; Qin, Zhenzhen; Chen, Lanli; Wu, Ning

    2017-01-01

    Highlights: • It is found nonmagnetic GaN ML exhibits half-metallic FM behavior by Mn doping due to double exchange mechanism. • Interestingly, the FM coupling is enhanced with the increasing tensile strain due to stronger interaction between Mn-3d and N-2p state. • While, the FM interaction is weakened with the increasing compressive strain until it transforms into AFM under strain of −9.5%. • These results provide a feasible approach for the fabrication of 2D DMS based GaN ML. - Abstract: To meet the need of low-dimensional spintronic devices, we investigate the electronic structure and magnetic properties of Mn-doped GaN monolayer using first-principles method. We find the nonmagnetic GaN monolayer exhibits half-metallic ferromagnetism by Mn doping due to double-exchange mechanism. Interestingly, the ferromagnetic coupling in Mn-doped GaN monolayer is enhanced with tensile strain and weakened with compressive strain. What is more, the ferromagnetic–antiferromagnetic transformation occurs under compressive strain of −9.5%. These results provide a feasible approach for fabrication of a new GaN monolayer based diluted magnetic semiconductor.

  13. Design of a new two-dimensional diluted magnetic semiconductor: Mn-doped GaN monolayer

    Energy Technology Data Exchange (ETDEWEB)

    Zhao, Qian [Key Laboratory for Optoelectronics and Communication of Jiangxi Province, Jiangxi Science & Technology Normal University, Nanchang 330038 (China); Materials Genome Institute, Shanghai University, Shanghai 200444 (China); Xiong, Zhihua, E-mail: xiong_zhihua@126.com [Key Laboratory for Optoelectronics and Communication of Jiangxi Province, Jiangxi Science & Technology Normal University, Nanchang 330038 (China); Luo, Lan [School of Materials Science and Engineering, Nanchang University, Nanchang 330031 (China); Sun, Zhenhui [Key Laboratory for Optoelectronics and Communication of Jiangxi Province, Jiangxi Science & Technology Normal University, Nanchang 330038 (China); Qin, Zhenzhen [College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300071 (China); Chen, Lanli [Materials Genome Institute, Shanghai University, Shanghai 200444 (China); Wu, Ning [Key Laboratory for Optoelectronics and Communication of Jiangxi Province, Jiangxi Science & Technology Normal University, Nanchang 330038 (China)

    2017-02-28

    Highlights: • It is found nonmagnetic GaN ML exhibits half-metallic FM behavior by Mn doping due to double exchange mechanism. • Interestingly, the FM coupling is enhanced with the increasing tensile strain due to stronger interaction between Mn-3d and N-2p state. • While, the FM interaction is weakened with the increasing compressive strain until it transforms into AFM under strain of −9.5%. • These results provide a feasible approach for the fabrication of 2D DMS based GaN ML. - Abstract: To meet the need of low-dimensional spintronic devices, we investigate the electronic structure and magnetic properties of Mn-doped GaN monolayer using first-principles method. We find the nonmagnetic GaN monolayer exhibits half-metallic ferromagnetism by Mn doping due to double-exchange mechanism. Interestingly, the ferromagnetic coupling in Mn-doped GaN monolayer is enhanced with tensile strain and weakened with compressive strain. What is more, the ferromagnetic–antiferromagnetic transformation occurs under compressive strain of −9.5%. These results provide a feasible approach for fabrication of a new GaN monolayer based diluted magnetic semiconductor.

  14. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  15. Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

    Science.gov (United States)

    Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

    2014-09-01

    The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

  16. 75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

    Science.gov (United States)

    2010-03-02

    ... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

  17. Roadmap on semiconductor-cell biointerfaces

    Science.gov (United States)

    Tian, Bozhi; Xu, Shuai; Rogers, John A.; Cestellos-Blanco, Stefano; Yang, Peidong; Carvalho-de-Souza, João L.; Bezanilla, Francisco; Liu, Jia; Bao, Zhenan; Hjort, Martin; Cao, Yuhong; Melosh, Nicholas; Lanzani, Guglielmo; Benfenati, Fabio; Galli, Giulia; Gygi, Francois; Kautz, Rylan; Gorodetsky, Alon A.; Kim, Samuel S.; Lu, Timothy K.; Anikeeva, Polina; Cifra, Michal; Krivosudský, Ondrej; Havelka, Daniel; Jiang, Yuanwen

    2018-05-01

    This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world.

  18. Microeconomics of process control in semiconductor manufacturing

    Science.gov (United States)

    Monahan, Kevin M.

    2003-06-01

    Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

  19. Design of medium band gap Ag-Bi-Nb-O and Ag-Bi-Ta-O semiconductors for driving direct water splitting with visible light.

    Science.gov (United States)

    Wang, Limin; Cao, Bingfei; Kang, Wei; Hybertsen, Mark; Maeda, Kazuhiko; Domen, Kazunari; Khalifah, Peter G

    2013-08-19

    Two new metal oxide semiconductors belonging to the Ag-Bi-M-O (M = Nb, Ta) chemical systems have been synthesized as candidate compounds for driving overall water splitting with visible light on the basis of cosubstitution of Ag and Bi on the A-site position of known Ca2M2O7 pyrochlores. The low-valence band edge energies of typical oxide semiconductors prevents direct water splitting in compounds with band gaps below 3.0 eV, a limitation which these compounds are designed to overcome through the incorporation of low-lying Ag 4d(10) and Bi 6s(2) states into compounds of nominal composition "AgBiM2O7". It was found that the "AgBiTa2O7" pyrochlores are in fact a solid solution with an approximate range of Ag(x)Bi(5/6)Ta2O(6.25+x/2) with 0.5 semiconductors with the onset of strong direct absorption at 2.72 and 2.96 eV, respectively. Electronic structure calculations for an ordered AgBiNb2O7 structure show that the band gap reduction and the elevation of the valence band primarily result from hybridized Ag d(10)-O 2p orbitals that lie at higher energy than the normal O 2p states in typical pyrochlore oxides. While the minimum energy gap is direct in the band structure, the lowest energy dipole allowed optical transitions start about 0.2 eV higher in energy than the minimum energy transition and involve different bands. This suggests that the minimum electronic band gap in these materials is slightly smaller than the onset energy for strong absorption in the optical measurements. The elevated valence band energies of the niobate and tantalate compounds are experimentally confirmed by the ability of these compounds to reduce 2 H(+) to H2 gas when illuminated after functionalization with a Pt cocatalyst.

  20. Metal-semiconductor interface in extreme temperature conditions

    International Nuclear Information System (INIS)

    Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

    2008-01-01

    We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

  1. Semiconductor laser shearing interferometer

    International Nuclear Information System (INIS)

    Ming Hai; Li Ming; Chen Nong; Xie Jiaping

    1988-03-01

    The application of semiconductor laser on grating shearing interferometry is studied experimentally in the present paper. The method measuring the coherence of semiconductor laser beam by ion etching double frequency grating is proposed. The experimental result of lens aberration with semiconductor laser shearing interferometer is given. Talbot shearing interferometry of semiconductor laser is also described. (author). 2 refs, 9 figs

  2. Doping of organic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Luessem, B.; Riede, M.; Leo, K. [Institut fuer Angewandte Photophysik, TU Dresden (Germany)

    2013-01-15

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  3. Doping of organic semiconductors

    International Nuclear Information System (INIS)

    Luessem, B.; Riede, M.; Leo, K.

    2013-01-01

    The understanding and applications of organic semiconductors have shown remarkable progress in recent years. This material class has been developed from being a lab curiosity to the basis of first successful products as small organic LED (OLED) displays; other areas of application such as OLED lighting and organic photovoltaics are on the verge of broad commercialization. Organic semiconductors are superior to inorganic ones for low-cost and large-area optoelectronics due to their flexibility, easy deposition, and broad variety, making tailor-made materials possible. However, electrical doping of organic semiconductors, i.e. the controlled adjustment of Fermi level that has been extremely important to the success of inorganic semiconductors, is still in its infancy. This review will discuss recent work on both fundamental principles and applications of doping, focused primarily to doping of evaporated organic layers with molecular dopants. Recently, both p- and n-type molecular dopants have been developed that lead to efficient and stable doping of organic thin films. Due to doping, the conductivity of the doped layers increases several orders of magnitude and allows for quasi-Ohmic contacts between organic layers and metal electrodes. Besides reducing voltage losses, doping thus also gives design freedom in terms of transport layer thickness and electrode choice. The use of doping in applications like OLEDs and organic solar cells is highlighted in this review. Overall, controlled molecular doping can be considered as key enabling technology for many different organic device types that can lead to significant improvements in efficiencies and lifetimes. (Copyright copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  4. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  5. Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

    International Nuclear Information System (INIS)

    Anvar, Shebli; Château, Frédéric; Le Provost, Hervé; Louis, Frédéric; Manolopoulos, Konstantinos; Moudden, Yassir; Vallage, Bertrand; Zonca, Eric

    2014-01-01

    A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described

  6. Optical trapping with Bessel beams generated from semiconductor lasers

    International Nuclear Information System (INIS)

    Sokolovskii, G S; Dudelev, V V; Losev, S N; Soboleva, K K; Deryagin, A G; Kuchinskii, V I; Sibbett, W; Rafailov, E U

    2014-01-01

    In this paper, we study generation of Bessel beams from semiconductor lasers with high beam propagation parameter M 2 and their utilization for optical trapping and manipulation of microscopic particles including living cells. The demonstrated optical tweezing with diodegenerated Bessel beams paves the way to replace their vibronic-generated counterparts for a range of applications towards novel lab-on-a-chip configurations

  7. A microprocessor based on a two-dimensional semiconductor

    Science.gov (United States)

    Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

    2017-04-01

    The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

  8. Epitaxy of semiconductor-superconductor nanowires

    DEFF Research Database (Denmark)

    Krogstrup, P.; Ziino, N.L.B.; Chang, W.

    2015-01-01

    Controlling the properties of semiconductor/metal interfaces is a powerful method for designing functionality and improving the performance of electrical devices. Recently semiconductor/superconductor hybrids have appeared as an important example where the atomic scale uniformity of the interface...

  9. Semiconductor nanostructures

    Energy Technology Data Exchange (ETDEWEB)

    Marstein Erik Stensrud

    2003-07-01

    This thesis presents a study of two material systems containing semiconductor nanocrystals, namely porous silicon (PSi) films and germanium (Ge) nanocrystals embedded in silicon dioxide (SiO2) films. The PSi films were made by anodic etching of silicon (Si) substrates in an electrolyte containing hydrofluoric acid. The PSi films were doped with erbium (Er) using two different doping methods. electrochemical doping and doping by immersing the PSi films in a solution containing Er. The resulting Er concentration profiles were investigated using scanning electron microscopy (SEN1) combined with energy dispersive X-ray analysis (EDS). The main subject of the work on PSi presented in this thesis was investigating and comparing these two doping methods. Ge nanocrystals were made by implanting Ge ions into Si02 films that were subsequently annealed. However. nanocrystal formation occurred only for certain sets of processing parameters. The dependence of the microstructure of the Ge implanted Si02 films on the processing parameters were therefore investigated. A range of methods were employed for these investigations, including transmission electron microscopy (TEM) combined with EDS, X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). The observed structures, ranging from Ge nanocrystals to voids with diameters of several tens of nanometers and Ge rich Si02 films without any nanocrystals is described. A model explaining the void formation is also presented. For certain sets of processing parameters. An accumulation of Ge at the Si-Si02 interface was observed. The effect of this accumulation on the electrical properties of MOS structures made from Ge implanted SiO2 films was investigated using CV-measurements. (Author)

  10. Design, microfabrication, and characterization of a moulded PDMS/SU-8 inkjet dispenser for a Lab-on-a-Printer platform technology with disposable microfluidic chip.

    Science.gov (United States)

    Bsoul, Anas; Pan, Sheng; Cretu, Edmond; Stoeber, Boris; Walus, Konrad

    2016-08-16

    In this paper, we present a disposable inkjet dispenser platform technology and demonstrate the Lab-on-a-Printer concept, an extension of the ubiquitous Lab-on-a-Chip concept, whereby microfluidic modules are directly integrated into the printhead. The concept is demonstrated here through the integration of an inkjet dispenser and a microfluidic mixer enabling control over droplet composition from a single nozzle in real-time during printing. The inkjet dispenser is based on a modular design platform that enables the low-cost microfluidic component and the more expensive actuation unit to be easily separated, allowing for the optional disposal of the former and reuse of the latter. To limit satellite droplet formation, a hydrophobic-coated and tapered micronozzle was microfabricated and integrated with the fluidics to realize the dispenser. The microfabricated devices generated droplets with diameters ranging from 150-220 μm, depending mainly on the orifice diameter, with printing rates up to 8000 droplets per second. The inkjet dispenser is capable of dispensing materials with a viscosity up to ∼19 mPa s. As a demonstration of the inkjet dispenser function and application, we have printed type I collagen seeded with human liver carcinoma cells (cell line HepG2), to form patterned biological structures.

  11. An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar; Olsen, Rasmus Grøndahl

    2005-01-01

    decouples communication and computation, providing memory-mapped OCP transactions based on primitive message-passing services of the network. Also, it facilitates GALS-type systems, by adapting to the clockless network. This helps leverage a modular SoC design flow. We evaluate performance and cost of 0...

  12. Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

    NARCIS (Netherlands)

    Amory, A.M.; Goossens, K.G.W.; Marinissen, Erik Jan; Lubaszewski, M.; Moraes, F.

    2007-01-01

    A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new

  13. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  14. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind; El cerebro humano en un ordenador

    Energy Technology Data Exchange (ETDEWEB)

    Pajuelo, L.

    2015-07-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  15. 75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

    Science.gov (United States)

    2010-07-01

    ... Manufacturing A, Austin, Texas. The notice was published in the Federal Register on May 28, 2010 (75 FR 30070...Logic, Inc., Austin, TX; Amended Certification Regarding Eligibility To Apply for Worker Adjustment..., Design Solutions, Inc., Veriseo, SilconElite and MicroLogic, Inc. were employed on-site at the Austin...

  16. Fundamentals of semiconductor devices

    CERN Document Server

    Lindmayer, Joseph

    1965-01-01

    Semiconductor properties ; semiconductor junctions or diodes ; transistor fundamentals ; inhomogeneous impurity distributions, drift or graded-base transistors ; high-frequency properties of transistors ; band structure of semiconductors ; high current densities and mechanisms of carrier transport ; transistor transient response and recombination processes ; surfaces, field-effect transistors, and composite junctions ; additional semiconductor characteristics ; additional semiconductor devices and microcircuits ; more metal, insulator, and semiconductor combinations for devices ; four-pole parameters and configuration rotation ; four-poles of combined networks and devices ; equivalent circuits ; the error function and its properties ; Fermi-Dirac statistics ; useful physical constants.

  17. Design and characterization of downconversion mixers and the on-chip calibration techniques for monolithic direct conversion radio receivers

    OpenAIRE

    Kivekäs, Kalle

    2002-01-01

    This thesis consists of eight publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design of downconversion mixers and direct conversion radio receivers for UTRA/FDD WCDMA and GSM standards. The main interest of the work is in the 1-3 GHz frequency range and in the Silicon and Silicon-Germanium BiCMOS technologies. The RF front-end, and especially the mixer, limits the performance of direct conversion ...

  18. Semiconductor X-ray spectrometers

    International Nuclear Information System (INIS)

    Muggleton, A.H.F.

    1978-02-01

    An outline is given of recent developments in particle and photon induced x-ray fluorescence (XRF) analysis. Following a brief description of the basic mechanism of semiconductor detector operation a comparison is made between semiconductor detectors, scintillators and gas filled proportional devices. Detector fabrication and cryostat design are described in more detail and the effects of various device parameters on system performance, such as energy resolution, count rate capability, efficiency, microphony, etc. are discussed. The main applications of these detectors in x-ray fluorescence analysis, electron microprobe analysis, medical and pollution studies are reviewed

  19. Thiophene-Based Organic Semiconductors.

    Science.gov (United States)

    Turkoglu, Gulsen; Cinar, M Emin; Ozturk, Turan

    2017-10-24

    Thiophene-based π-conjugated organic small molecules and polymers are the research subject of significant current interest owing to their potential use as organic semiconductors in material chemistry. Despite simple and similar molecular structures, the hitherto reported properties of thiophene-based organic semiconductors are rather diverse. Design of high performance organic semiconducting materials requires a thorough understanding of inter- and intra-molecular interactions, solid-state packing, and the influence of both factors on the charge carrier transport. In this chapter, thiophene-based organic semiconductors, which are classified in terms of their chemical structures and their structure-property relationships, are addressed for the potential applications as organic photovoltaics (OPVs), organic field-effect transistors (OFETs) and organic light emitting diodes (OLEDs).

  20. Finite element modeling simulation-assisted design of integrated microfluidic chips for heavy metal ion stripping analysis

    International Nuclear Information System (INIS)

    Hong, Ying; Zou, Jianhua; Ge, Gang; Xiao, Wanyue; Shao, Jinjun; Dong, Xiaochen; Gao, Ling

    2017-01-01

    In this article, a transparent integrated microfluidic device composed of a 3D-printed thin-layer flow cell (3D-PTLFC) and an S-shaped screen-printed electrode (SPE) has been designed and fabricated for heavy metal ion stripping analysis. A finite element modeling (FEM) simulation is employed to optimize the shape of the electrode, the direction of the inlet pipeline, the thin-layer channel height and the sample flow rate to enhance the electron-enrichment efficiency for stripping analysis. The results demonstrate that the S-shaped SPE configuration matches the channel in 3D-PTLFC perfectly for the anodic stripping behavior of the heavy metal ions. Under optimized conditions, a wide linear range of 1–80 µ g l −1 is achieved for Pb 2+ detection with a limit of 0.3 µ g l −1 for the microfluidic device. Thus, the obtained integrated microfluidic device proves to be a promising approach for heavy metal ions stripping analysis with low cost and high performance. (paper)

  1. Solid spectroscopy: semiconductors

    International Nuclear Information System (INIS)

    Silva, C.E.T.G. da

    1983-01-01

    Photoemission as technique of study of the semiconductor electronic structure is shortly discussed. Homogeneous and heterogeneous semiconductors, where volume and surface electronic structure, core levels and O and H chemisorption in GaAs, Schottky barrier are treated, respectively. Amorphous semiconductors are also discussed. (L.C.) [pt

  2. Revenue sharing in semiconductor industry supply chain ...

    Indian Academy of Sciences (India)

    to reduce demand opportunities, inventory needs and production efficiencies, in addition to reducing .... design based on coalition structures in semiconductor supply chain. ..... supplier/contract manufacturer for a product/component category.

  3. Manipulating semiconductor colloidal stability through doping.

    Science.gov (United States)

    Fleharty, Mark E; van Swol, Frank; Petsev, Dimiter N

    2014-10-10

    The interface between a doped semiconductor material and electrolyte solution is of considerable fundamental interest, and is relevant to systems of practical importance. Both adjacent domains contain mobile charges, which respond to potential variations. This is exploited to design electronic and optoelectronic sensors, and other enabling semiconductor colloidal materials. We show that the charge mobility in both phases leads to a new type of interaction between semiconductor colloids suspended in aqueous electrolyte solutions. This interaction is due to the electrostatic response of the semiconductor interior to disturbances in the external field upon the approach of two particles. The electrostatic repulsion between two charged colloids is reduced from the one governed by the charged groups present at the particles surfaces. This type of interaction is unique to semiconductor particles and may have a substantial effect on the suspension dynamics and stability.

  4. Device Physics of Narrow Gap Semiconductors

    CERN Document Server

    Chu, Junhao

    2010-01-01

    Narrow gap semiconductors obey the general rules of semiconductor science, but often exhibit extreme features of these rules because of the same properties that produce their narrow gaps. Consequently these materials provide sensitive tests of theory, and the opportunity for the design of innovative devices. Narrow gap semiconductors are the most important materials for the preparation of advanced modern infrared systems. Device Physics of Narrow Gap Semiconductors offers descriptions of the materials science and device physics of these unique materials. Topics covered include impurities and defects, recombination mechanisms, surface and interface properties, and the properties of low dimensional systems for infrared applications. This book will help readers to understand not only the semiconductor physics and materials science, but also how they relate to advanced opto-electronic devices. The last chapter applies the understanding of device physics to photoconductive detectors, photovoltaic infrared detector...

  5. Molecular semiconductors photoelectrical properties and solar cells

    CERN Document Server

    Rees, Ch

    1985-01-01

    During the past thirty years considerable efforts have been made to design the synthesis and the study of molecular semiconductors. Molecular semiconductors - and more generally molecular materials - involve interactions between individual subunits which can be separately synthesized. Organic and metallo-organic derivatives are the basis of most of the molecular materials. A survey of the literature on molecular semiconductors leaves one rather confused. It does seem to be very difficult to correlate the molecular structure of these semiconductors with their experimental electrical properties. For inorganic materials a simple definition delimits a fairly homogeneous family. If an inorganic material has a conductivity intermediate between that of an 12 1 1 3 1 1 insulator « 10- n- cm- ) and that of a metal (> 10 n- cm- ), then it is a semiconductor and will exhibit the characteristic properties of this family, such as junction formation, photoconductivity, and the photovoltaic effect. For molecular compounds,...

  6. Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

    Science.gov (United States)

    Ashenafi, Emeshaw

    Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

  7. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  8. Superconducting detectors for semiconductor quantum photonics

    International Nuclear Information System (INIS)

    Reithmaier, Guenther M.

    2015-01-01

    In this thesis we present the first successful on-chip detection of quantum light, thereby demonstrating the monolithic integration of superconducting single photon detectors with individually addressable semiconductor quantum dots in a prototypical quantum photonic circuit. Therefore, we optimized both the deposition of high quality superconducting NbN thin films on GaAs substrates and the fabrication of superconducting detectors and successfully integrated these novel devices with GaAs/AlGaAs ridge waveguides loaded with self-assembled InGaAs quantum dots.

  9. Blasting detonators incorporating semiconductor bridge technology

    Energy Technology Data Exchange (ETDEWEB)

    Bickes, R.W. Jr.

    1994-05-01

    The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

  10. Semiconductor Laser Diode Pumps for Inertial Fusion Energy Lasers

    International Nuclear Information System (INIS)

    Deri, R.J.

    2011-01-01

    increased reliability. The high-level requirements on the semiconductor lasers involve reliability, price points on a price-per-Watt basis, and a set of technical requirements. The technical requirements for the amplifier design in reference 1 are discussed in detail and are summarized in Table 1. These values are still subject to changes as the overall laser system continues to be optimized. Since pump costs can be a significant fraction of the overall laser system cost, it is important to achieve sufficiently low price points for these components. At this time, the price target for tenth-of-akind IFE plant is $0.007/Watt for packaged devices. At this target level, the pumps account for approximately one third of the laser cost. The pump lasers should last for the life of the power plant, leading to a target component lifetime requirement of roughly 14 Ghosts, corresponding to a 30 year plant life and 15 Hz repetition rate. An attractive path forward involes pump operation at high output power levels, on a Watts-per-bar (Watts/chip) basis. This reduces the cost of pump power (price-per-Watt), since to first order the unit price does not increase with power/bar. The industry has seen a continual improvement in power output, with current 1 cm-wide bars emitting up to 500 W QCW (quasi-continuous wave). Increased power/bar also facilitates achieving high irradiance in the array plane. On the other hand, increased power implies greater heat loads and (possibly) higher current drive, which will require increased attention to thermal management and parasitic series resistance. Diode chips containing multiple p-n junctions and quantum wells (also called nanostack structures) may provide an additional approach to reduce the peak current.

  11. Semiconductor Nanostructures By Scientific Design

    Energy Technology Data Exchange (ETDEWEB)

    Galli, Guilia [Univ. of California, Davis, CA (United States)

    2015-02-12

    The goals and objectives of the present proposal are very much aligned with those of the previous award cycle. In the last three years we investigated semiconducting nanoparticles, nanowires and nanocomposites to understand and optimize their optical properties for solar applications and their heat transport properties for thermoelectric applications. We focused on understanding the role of surfaces and interfaces; our study included the investigation of surfactants, in particular of the role of van der Waals forces in binding surfactants to specific substrates. In addition to addressing specific nanoscience and materials science problems, we developed techniques and codes of general applicability. The investigations carried out in the past three years have resulted in 10 published papers in peer reviewed journals (including NL, ACS Nano and PRL) and in 3 papers submitted for publication in 2012 (now appeared).

  12. Ion implantation for semiconductors

    International Nuclear Information System (INIS)

    Grey-Morgan, T.

    1995-01-01

    Full text: Over the past two decades, thousands of particle accelerators have been used to implant foreign atoms like boron, phosphorus and arsenic into silicon crystal wafers to produce special embedded layers for manufacturing semiconductor devices. Depending on the device required, the atomic species, the depth of implant and doping levels are the main parameters for the implantation process; the selection and parameter control is totally automated. The depth of the implant, usually less than 1 micron, is determined by the ion energy, which can be varied between 2 and 600 keV. The ion beam is extracted from a Freeman or Bernas type ion source and accelerated to 60 keV before mass analysis. For higher beam energies postacceleration is applied up to 200 keV and even higher energies can be achieved by mass selecting multiplycharged ions, but with a corresponding reduction in beam output. Depending on the device to be manufactured, doping levels can range from 10 10 to 10 15 atoms/cm 2 and are controlled by implanter beam currents in the range up to 30mA; continuous process monitoring ensures uniformity across the wafer of better than 1 % . As semiconductor devices get smaller, additional sophistication is required in the design of the implanter. The silicon wafers charge electrically during implantation and this charge must be dissipated continuously to reduce the electrical stress in the device and avoid destructive electrical breakdown. Electron flood guns produce low energy electrons (below 10 electronvolts) to neutralize positive charge buildup and implanter design must ensure minimum contamination by other isotopic species and ensure low internal sputter rates. The pace of technology in the semiconductor industry is such that implanters are being built now for 256 Megabit circuits but which are only likely to be widely available five years from now. Several specialist companies manufacture implanter systems, each costing around US$5 million, depending on the

  13. Combination of Machining Parameters to Optimize Surface Roughness and Chip Thickness during End Milling Process on Aluminium 6351-T6 Alloy Using Taguchi Design Method

    Directory of Open Access Journals (Sweden)

    Reddy Sreenivasulu

    2016-12-01

    Full Text Available In any machining operations, quality is the important conflicting objective. In order to give assurance for high productivity, some extent of quality has to be compromised. Similarly productivity will be decreased while the efforts are channelized to enhance quality. In this study,  the experiments were carried out on a CNC vertical machining center  to perform 10mm slots on Al 6351-T6 alloy work piece by K10 carbide, four flute end milling cutter. Furthermore the cutting speed, the feed rate and depth of cut are regulated in this experiment. Each experiment was conducted three times and the surface roughness and chip thickness was measured by a surface analyser of Surf Test-211 series (Mitutoyo and Digital Micrometer (Mitutoyo with least count 0.001 mm respectively. The selection of orthogonal array is concerned with the total degree of freedom of process parameters. Total degree of freedom (DOF associated with three parameters is equal to 6 (3X2.The degree of freedom for the orthogonal array should be greater than or at least equal to that of the process parameters. There by, a L9 orthogonal array having degree of freedom equal to (9-1= 8 8 has been considered .But in present case each experiment is conducted three times, therefore total degree of freedom (9X3-1=26 26 has been considered. Finally, confirmation test (ANOVA was conducted to compare the predicted values with the experimental values confirm its effectiveness in the analysis of surface roughness and chip thickness. Surface Roughness (Ra is greatly reduced from 0.145 µm to 0.1326 µm and the chip thickness (Ct is slightly reduced from 0.1 mm to 0.085 mm, because of in the measurement collected the chips after machining of every experiment, from that randomly selected a few chips for measuring of their thickness using digital micrometer.

  14. Compound Semiconductor Radiation Detector

    International Nuclear Information System (INIS)

    Kim, Y. K.; Park, S. H.; Lee, W. G.; Ha, J. H.

    2005-01-01

    In 1945, Van Heerden measured α, β and γ radiations with the cooled AgCl crystal. It was the first radiation measurement using the compound semiconductor detector. Since then the compound semiconductor has been extensively studied as radiation detector. Generally the radiation detector can be divided into the gas detector, the scintillator and the semiconductor detector. The semiconductor detector has good points comparing to other radiation detectors. Since the density of the semiconductor detector is higher than that of the gas detector, the semiconductor detector can be made with the compact size to measure the high energy radiation. In the scintillator, the radiation is measured with the two-step process. That is, the radiation is converted into the photons, which are changed into electrons by a photo-detector, inside the scintillator. However in the semiconductor radiation detector, the radiation is measured only with the one-step process. The electron-hole pairs are generated from the radiation interaction inside the semiconductor detector, and these electrons and charged ions are directly collected to get the signal. The energy resolution of the semiconductor detector is generally better than that of the scintillator. At present, the commonly used semiconductors as the radiation detector are Si and Ge. However, these semiconductor detectors have weak points. That is, one needs thick material to measure the high energy radiation because of the relatively low atomic number of the composite material. In Ge case, the dark current of the detector is large at room temperature because of the small band-gap energy. Recently the compound semiconductor detectors have been extensively studied to overcome these problems. In this paper, we will briefly summarize the recent research topics about the compound semiconductor detector. We will introduce the research activities of our group, too

  15. Semiconductor apparatus and method of fabrication for a semiconductor apparatus

    NARCIS (Netherlands)

    2010-01-01

    The invention relates to a semiconductor apparatus (1) and a method of fabrication for a semiconductor apparatus (1), wherein the semiconductor apparatus (1) comprises a semiconductor layer (2) and a passivation layer (3), arranged on a surface of the semiconductor layer (2), for passivating the

  16. Semiconductor Physical Electronics

    CERN Document Server

    Li, Sheng

    2006-01-01

    Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

  17. On-chip patch antenna on InP substrate for short-range wireless communication at 140 GHz

    DEFF Research Database (Denmark)

    Dong, Yunfeng; Johansen, Tom Keinicke; Zhurbenko, Vitaliy

    2017-01-01

    This paper presents the design of an on-chip patch antenna on indium phosphide (InP) substrate for short-range wireless communication at 140 GHz. The antenna shows a simulated gain of 5.3 dBi with 23% bandwidth at 140 GHz and it can be used for either direct chip-to-chip communication or chip...

  18. Contacts to semiconductors

    International Nuclear Information System (INIS)

    Tove, P.A.

    1975-08-01

    Contacts to semiconductors play an important role in most semiconductor devices. These devices range from microelectronics to power components, from high-sensitivity light or radiation detectors to light-emitting of microwave-generating components. Silicon is the dominating material but compound semiconductors are increasing in importance. The following survey is an attempt to classify contact properties and the physical mechanisms involved, as well as fabrication methods and methods of investigation. The main interest is in metal-semiconductor type contacts where a few basic concepts are dealt with in some detail. (Auth.)

  19. Semiconductor Electrical Measurements Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Semiconductor Electrical Measurements Laboratory is a research laboratory which complements the Optical Measurements Laboratory. The laboratory provides for Hall...

  20. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  1. Possibilities for mixed mode chip manufacturing in EUROPRACTICE

    Science.gov (United States)

    Das, C.

    1997-02-01

    EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

  2. Solid-Phase Immunoassay of Polystyrene-Encapsulated Semiconductor Coreshells for Cardiac Marker Detection

    Directory of Open Access Journals (Sweden)

    Sanghee Kim

    2012-01-01

    Full Text Available A solid-phase immunoassay of polystyrene-encapsulated semiconductor nanoparticles was demonstrated for cardiac troponin I (cTnI detection. CdSe/ZnS coreshells were encapsulated with a carboxyl-functionalized polystyrene nanoparticle to capture the target antibody through a covalent bonding and to eliminate the photoblinking and toxicity of semiconductor luminescent immunosensor. The polystyrene-encapsulated CdSe/ZnS fluorophores on surface-modified glass chip identified cTnI antigens at the level of ~ng/mL. It was an initial demonstration of diagnostic chip for monitoring a cardiovascular disease.

  3. Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

    Energy Technology Data Exchange (ETDEWEB)

    Ni, Jing [Iowa State Univ., Ames, IA (United States)

    2000-09-21

    This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

  4. Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm−C loop filter

    International Nuclear Information System (INIS)

    Huang Jhin-Fang; Lai Wen-Cheng; Shin Chun-Wei; Hsu Chien-Ming; Liu Ron-Yi

    2012-01-01

    This paper proposes a novel G m −C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is −114.1 dBc/Hz with lower G m −C bandwidth and −111.7 dBm/C with higher G m −C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in G m −C filter, the chip area of the proposed frequency synthesizer is 1.06 mm 2 . The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  5. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  6. Electronics Industry Study Report: Semiconductors and Defense Electronics

    Science.gov (United States)

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  7. Semiconductors data handbook

    CERN Document Server

    Madelung, Otfried

    2004-01-01

    This volume Semiconductors: Data Handbook contains frequently used data from the corresponding larger Landolt-Börnstein handbooks in a low price book for the individual scientist working in the laboratory. The Handbook contain important information about a large number of semiconductors

  8. Spin physics in semiconductors

    CERN Document Server

    Dyakonov, Mikhail I

    2008-01-01

    This book describes beautiful optical and transport phenomena related to the electron and nuclear spins in semiconductors with emphasis on a clear presentation of the physics involved. Recent results on quantum wells and quantum dots are reviewed. The book is intended for students and researchers in the fields of semiconductor physics and nanoelectronics.

  9. Design and analysis of spiral inductors

    CERN Document Server

    Haobijam, Genemala

    2013-01-01

    The book addresses the critical challenges faced by the ever-expanding wireless communication market and the increasing frequency of operation due to continuous innovation of high performance integrated passive devices. The challenges like low quality factor, design complexity, manufacturability, processing cost, etc., are studied with examples and specifics. Silicon on-chip inductor was first reported in 1990 by Nguyen and Meyer in a 0.8 µm silicon bipolar complementary metal oxide semiconductor technology (BiCMOS). Since then, there has been an enormous progress in the research on the perfo

  10. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  11. Compound Semiconductor Radiation Detectors

    CERN Document Server

    Owens, Alan

    2012-01-01

    Although elemental semiconductors such as silicon and germanium are standard for energy dispersive spectroscopy in the laboratory, their use for an increasing range of applications is becoming marginalized by their physical limitations, namely the need for ancillary cooling, their modest stopping powers, and radiation intolerance. Compound semiconductors, on the other hand, encompass such a wide range of physical and electronic properties that they have become viable competitors in a number of applications. Compound Semiconductor Radiation Detectors is a consolidated source of information on all aspects of the use of compound semiconductors for radiation detection and measurement. Serious Competitors to Germanium and Silicon Radiation Detectors Wide-gap compound semiconductors offer the ability to operate in a range of hostile thermal and radiation environments while still maintaining sub-keV spectral resolution at X-ray wavelengths. Narrow-gap materials offer the potential of exceeding the spectral resolutio...

  12. Terahertz semiconductor nonlinear optics

    DEFF Research Database (Denmark)

    Turchinovich, Dmitry; Hvam, Jørn Märcher; Hoffmann, Matthias

    2013-01-01

    In this proceedings we describe our recent results on semiconductor nonlinear optics, investigated using single-cycle THz pulses. We demonstrate the nonlinear absorption and self-phase modulation of strong-field THz pulses in doped semiconductors, using n-GaAs as a model system. The THz...... nonlinearity in doped semiconductors originates from the near-instantaneous heating of free electrons in the ponderomotive potential created by electric field of the THz pulse, leading to ultrafast increase of electron effective mass by intervalley scattering. Modification of effective mass in turn leads...... to a decrease of plasma frequency in semiconductor and produces a substantial modification of THz-range material dielectric function, described by the Drude model. As a result, the nonlinearity of both absorption coefficient and refractive index of the semiconductor is observed. In particular we demonstrate...

  13. Organic semiconductor crystals.

    Science.gov (United States)

    Wang, Chengliang; Dong, Huanli; Jiang, Lang; Hu, Wenping

    2018-01-22

    Organic semiconductors have attracted a lot of attention since the discovery of highly doped conductive polymers, due to the potential application in field-effect transistors (OFETs), light-emitting diodes (OLEDs) and photovoltaic cells (OPVs). Single crystals of organic semiconductors are particularly intriguing because they are free of grain boundaries and have long-range periodic order as well as minimal traps and defects. Hence, organic semiconductor crystals provide a powerful tool for revealing the intrinsic properties, examining the structure-property relationships, demonstrating the important factors for high performance devices and uncovering fundamental physics in organic semiconductors. This review provides a comprehensive overview of the molecular packing, morphology and charge transport features of organic semiconductor crystals, the control of crystallization for achieving high quality crystals and the device physics in the three main applications. We hope that this comprehensive summary can give a clear picture of the state-of-art status and guide future work in this area.

  14. An integrated semiconductor device enabling non-optical genome sequencing.

    Science.gov (United States)

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  15. Prototype detection unit for the CHIPS experiment

    Science.gov (United States)

    Pfützner, Maciej M.

    2017-09-01

    CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

  16. A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

    Directory of Open Access Journals (Sweden)

    Tharun Konduru

    2015-01-01

    Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

  17. A microfluidic chip for electrochemical conversions in drug metabolism studies

    NARCIS (Netherlands)

    Odijk, Mathieu; Baumann, A.; Lohmann, W.; van den Brink, Floris Teunis Gerardus; Olthuis, Wouter; Karst, U.; van den Berg, Albert

    2009-01-01

    We have designed a microfluidic microreactor chip for electrochemical conversion of analytes, containing a palladium reference electrode and platinum working and counter electrodes. The counter electrode is placed in a separate side-channel on chip to prevent unwanted side-products appearing in the

  18. Solving wood chip transport problems with computer simulation.

    Science.gov (United States)

    Dennis P. Bradley; Sharon A. Winsauer

    1976-01-01

    Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

  19. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...

  20. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  1. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  2. Novel room temperature ferromagnetic semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Gupta, Amita [KTH Royal Inst. of Technology, Stockholm (Sweden)

    2004-06-01

    Today's information world, bits of data are processed by semiconductor chips, and stored in the magnetic disk drives. But tomorrow's information technology may see magnetism (spin) and semiconductivity (charge) combined in one 'spintronic' device that exploits both charge and 'spin' to carry data (the best of two worlds). Spintronic devices such as spin valve transistors, spin light emitting diodes, non-volatile memory, logic devices, optical isolators and ultra-fast optical switches are some of the areas of interest for introducing the ferromagnetic properties at room temperature in a semiconductor to make it multifunctional. The potential advantages of such spintronic devices will be higher speed, greater efficiency, and better stability at a reduced power consumption. This Thesis contains two main topics: In-depth understanding of magnetism in Mn doped ZnO, and our search and identification of at least six new above room temperature ferromagnetic semiconductors. Both complex doped ZnO based new materials, as well as a number of nonoxides like phosphides, and sulfides suitably doped with Mn or Cu are shown to give rise to ferromagnetism above room temperature. Some of the highlights of this work are discovery of room temperature ferromagnetism in: (1) ZnO:Mn (paper in Nature Materials, Oct issue, 2003); (2) ZnO doped with Cu (containing no magnetic elements in it); (3) GaP doped with Cu (again containing no magnetic elements in it); (4) Enhancement of Magnetization by Cu co-doping in ZnO:Mn; (5) CdS doped with Mn, and a few others not reported in this thesis. We discuss in detail the first observation of ferromagnetism above room temperature in the form of powder, bulk pellets, in 2-3 mu-m thick transparent pulsed laser deposited films of the Mn (<4 at. percent) doped ZnO. High-resolution transmission electron microscopy (HRTEM) and electron energy loss spectroscopy (EELS) spectra recorded from 2 to 200nm areas showed homogeneous

  3. Cancer and reproductive risks in the semiconductor industry.

    Science.gov (United States)

    LaDou, Joseph; Bailar, John C

    2007-01-01

    Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

  4. Monolithic integration of microfluidic channels and semiconductor lasers

    Science.gov (United States)

    Cran-McGreehin, Simon J.; Dholakia, Kishan; Krauss, Thomas F.

    2006-08-01

    We present a fabrication method for the monolithic integration of microfluidic channels into semiconductor laser material. Lasers are designed to couple directly into the microfluidic channel, allowing submerged particles pass through the output beams of the lasers. The interaction between particles in the channel and the lasers, operated in either forward or reverse bias, allows for particle detection, and the optical forces can be used to trap and move particles. Both interrogation and manipulation are made more amenable for lab-on-a-chip applications through monolithic integration. The devices are very small, they require no external optical components, have perfect intrinsic alignment, and can be created with virtually any planar configuration of lasers in order to perform a variety of tasks. Their operation requires no optical expertise and only low electrical power, thus making them suitable for computer interfacing and automation. Insulating the pn junctions from the fluid is the key challenge, which is overcome by using photo-definable SU8-2000 polymer.

  5. Defects in semiconductors

    International Nuclear Information System (INIS)

    Pimentel, C.A.F.

    1983-01-01

    Some problems openned in the study of defects in semiconductors are presented. In particular, a review is made of the more important problems in Si monocrystals of basic and technological interest: microdefects and the presence of oxigen and carbon. The techniques usually utilized in the semiconductor material characterization are emphatized according its potentialities. Some applications of x-ray techniques in the epitaxial shell characterization in heterostructures, importants in electronic optics, are shown. The increase in the efficiency of these defect analysis methods in semiconductor materials with the use of synchrotron x-ray sources is shown. (L.C.) [pt

  6. Spin physics in semiconductors

    CERN Document Server

    2017-01-01

    This book offers an extensive introduction to the extremely rich and intriguing field of spin-related phenomena in semiconductors. In this second edition, all chapters have been updated to include the latest experimental and theoretical research. Furthermore, it covers the entire field: bulk semiconductors, two-dimensional semiconductor structures, quantum dots, optical and electric effects, spin-related effects, electron-nuclei spin interactions, Spin Hall effect, spin torques, etc. Thanks to its self-contained style, the book is ideally suited for graduate students and researchers new to the field.

  7. Semiconductors bonds and bands

    CERN Document Server

    Ferry, David K

    2013-01-01

    As we settle into this second decade of the twenty-first century, it is evident that the advances in micro-electronics have truly revolutionized our day-to-day lifestyle. The technology is built upon semiconductors, materials in which the band gap has been engineered for special values suitable to the particular application. This book, written specifically for a one semester course for graduate students, provides a thorough understanding of the key solid state physics of semiconductors. It describes how quantum mechanics gives semiconductors unique properties that enabled the micro-electronics revolution, and sustain the ever-growing importance of this revolution.

  8. Defects in semiconductors

    CERN Document Server

    Romano, Lucia; Jagadish, Chennupati

    2015-01-01

    This volume, number 91 in the Semiconductor and Semimetals series, focuses on defects in semiconductors. Defects in semiconductors help to explain several phenomena, from diffusion to getter, and to draw theories on materials' behavior in response to electrical or mechanical fields. The volume includes chapters focusing specifically on electron and proton irradiation of silicon, point defects in zinc oxide and gallium nitride, ion implantation defects and shallow junctions in silicon and germanium, and much more. It will help support students and scientists in their experimental and theoret

  9. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  10. Use of a reflective semiconductor optical amplifier and dual-ring architecture design to produce a stable multi-wavelength fiber laser

    International Nuclear Information System (INIS)

    Yeh, Chien-Hung; Chow, Chi-Wai; Lu, Shao-Sheng

    2014-01-01

    In this work, we propose and demonstrate a multi-wavelength laser source produced by utilizing a C-band reflective semiconductor optical amplifier (RSOA) with a dual-ring fiber cavity. Here, the laser cavity consists of an RSOA, a 1 × 2 optical coupler, a 2 × 2 optical coupler and a polarization controller. As a result, thirteen to eighteen wavelengths around the L band could be generated simultaneously when the bias current of the C-band RSOA was driven at 30–70 mA. In addition, the output stabilities of the power and wavelength are also discussed. (paper)

  11. Use of a reflective semiconductor optical amplifier and dual-ring architecture design to produce a stable multi-wavelength fiber laser

    Science.gov (United States)

    Yeh, Chien-Hung; Chow, Chi-Wai; Lu, Shao-Sheng

    2014-05-01

    In this work, we propose and demonstrate a multi-wavelength laser source produced by utilizing a C-band reflective semiconductor optical amplifier (RSOA) with a dual-ring fiber cavity. Here, the laser cavity consists of an RSOA, a 1 × 2 optical coupler, a 2 × 2 optical coupler and a polarization controller. As a result, thirteen to eighteen wavelengths around the L band could be generated simultaneously when the bias current of the C-band RSOA was driven at 30-70 mA. In addition, the output stabilities of the power and wavelength are also discussed.

  12. Thienoacene-based organic semiconductors.

    Science.gov (United States)

    Takimiya, Kazuo; Shinamura, Shoji; Osaka, Itaru; Miyazaki, Eigo

    2011-10-11

    Thienoacenes consist of fused thiophene rings in a ladder-type molecular structure and have been intensively studied as potential organic semiconductors for organic field-effect transistors (OFETs) in the last decade. They are reviewed here. Despite their simple and similar molecular structures, the hitherto reported properties of thienoacene-based OFETs are rather diverse. This Review focuses on four classes of thienoacenes, which are classified in terms of their chemical structures, and elucidates the molecular electronic structure of each class. The packing structures of thienoacenes and the thus-estimated solid-state electronic structures are correlated to their carrier transport properties in OFET devices. With this perspective of the molecular structures of thienoacenes and their carrier transport properties in OFET devices, the structure-property relationships in thienoacene-based organic semiconductors are discussed. The discussion provides insight into new molecular design strategies for the development of superior organic semiconductors. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  14. Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

    Science.gov (United States)

    King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

    1998-04-01

    We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

  15. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  16. Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

    Science.gov (United States)

    Pechal, M.; Besse, J.-C.; Mondal, M.; Oppliger, M.; Gasparinetti, S.; Wallraff, A.

    2016-08-01

    A switch capable of routing microwave signals at cryogenic temperatures is a desirable component for state-of-the-art experiments in many fields of applied physics, including but not limited to quantum-information processing, communication, and basic research in engineered quantum systems. Conventional mechanical switches provide low insertion loss but disturb operation of dilution cryostats and the associated experiments by heat dissipation. Switches based on semiconductors or microelectromechanical systems have a lower thermal budget but are not readily integrated with current superconducting circuits. Here we design and test an on-chip switch built by combining tunable transmission-line resonators with microwave beam splitters. The device is superconducting and as such dissipates a negligible amount of heat. It is compatible with current superconducting circuit fabrication techniques, operates with a bandwidth exceeding 100 MHz, is capable of handling photon fluxes on the order of 1 05 μ s-1 , equivalent to powers exceeding -90 dBm , and can be switched within approximately 6-8 ns. We successfully demonstrate operation of the device in the quantum regime by integrating it on a chip with a single-photon source and using it to route nonclassical itinerant microwave fields at the single-photon level.

  17. Biggest semiconductor installed

    CERN Multimedia

    2008-01-01

    Scientists and technicians at the European Laboratory for Particle Physics, commonly known by its French acronym CERN (Centre Europen pour la Recherche Nuclaire), have completed the installation of the largest semiconductor silicon detector.

  18. Compact semiconductor lasers

    CERN Document Server

    Yu, Siyuan; Lourtioz, Jean-Michel

    2014-01-01

    This book brings together in a single volume a unique contribution by the top experts around the world in the field of compact semiconductor lasers to provide a comprehensive description and analysis of the current status as well as future directions in the field of micro- and nano-scale semiconductor lasers. It is organized according to the various forms of micro- or nano-laser cavity configurations with each chapter discussing key technical issues, including semiconductor carrier recombination processes and optical gain dynamics, photonic confinement behavior and output coupling mechanisms, carrier transport considerations relevant to the injection process, and emission mode control. Required reading for those working in and researching the area of semiconductors lasers and micro-electronics.

  19. Market survey of semiconductors

    International Nuclear Information System (INIS)

    Mackintosh, I.M.; Diegel, D.; Brown, A.; Brinker, C.S. den

    1977-06-01

    Examination of technology and product trends over the range of current and future products in integrated circuits and optoelectronic displays. Analysis and forecast of major economic influences that affect the production costs of integrated circuits and optoelectronic displays. Forecast of the applications and markets for integrated circuits up to 1985 in West Europe, the USA and Japan. Historic development of the semiconductor industry and the prevailing tendencies - factors which influence success in the semiconductor industry. (orig.) [de

  20. Offshoring in the Semiconductor Industry: Historical Perspectives

    OpenAIRE

    Brown, Clair; Linden, Greg

    2005-01-01

    Semiconductor design is a frequently-cited example of the new wave of offshoring and foreign-outsourcing of service sector jobs. It is certainly a concern to U.S. design engineers themselves. In addition to the current wave of white-collar outsourcing, the industry also has a rich experience with offshoring of manufacturing activity. Semiconductor companies were among the first to invest in offshore facilities to manufacture goods for imports back to the U.S. A brief review of these earlie...

  1. Electronic properties of semiconductor heterostructures

    International Nuclear Information System (INIS)

    Einevoll, G.T.

    1991-02-01

    Ten papers on the electronic properties of semiconductors and semiconductor heterostructures constitute the backbone of this thesis. Four papers address the form and validity of the single-band effective mass approximation for semiconductor heterostructures. In four other papers properties of acceptor states in bulk semiconductors and semiconductor heterostructures are studied using the novel effective bond-orbital model. The last two papers deal with localized excitions. 122 refs

  2. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  3. Sensor development at the semiconductor laboratory of the Max-Planck-Society

    Science.gov (United States)

    Bähr, A.; Lechner, P.; Ninkovic, J.

    2017-12-01

    For more than twenty years the semiconductor laboratory of the Max-Planck Society (MPG-HLL) is developing high-performing, specialised, scientific silicon sensors including the integration of amplifying electronics on the sensor chip. This paper summarises the actual status of these devices like pnCCDs and DePFET Active Pixel Sensors and their applications.

  4. Cytostretch, an Organ-on-Chip Platform

    NARCIS (Netherlands)

    Gaio, N.; van Meer, B.; Quiros Solano, W.F.; Bergers, L.; van de Stolpe, A; Mummery, CL; Sarro, P.M.; Dekker, R.

    2016-01-01

    Organ-on-Chips (OOCs) are micro-fabricated devices which are used to culture cells in order to mimic functional units of human organs. The devices are designed to simulate the physiological environment of tissues in vivo. Cells in some types of OOCs can be stimulated in situ by electrical and/or

  5. Silicon microstrip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Masciocchi, S.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.S.; Timm, S.; Vorwalter, K.; Werding, R.

    1995-01-01

    A new silicon strip detector has been designed for the fixed target experiment WA89 at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into a FASTBUS memory. The detector provides a fast readout by offering zero-suppressed data extraction on the chip. The silicon counters are the largest detectors built on a monocrystal so far in order to achieve good transversal acceptance. Construction and performance during the 1993 data taking run are discussed. ((orig.))

  6. MCMII and the TriP chip

    Energy Technology Data Exchange (ETDEWEB)

    Juan Estrada et al.

    2003-12-19

    We describe the development of the electronics that will be used to read out the Fiber Tracker and Preshower detectors in Run IIb. This electronics is needed for operation at 132ns bunch crossing, and may provide a measurement of the z coordinate of the Fiber Tracker hits when operating at 396ns bunch crossing. Specifically, we describe the design and preliminary tests of the Trip chip, MCM IIa, MCM IIb and MCM IIc. This document also serves as a user manual for the Trip chip and the MCM.

  7. The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

    Science.gov (United States)

    Choi, Edward

    Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the

  8. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  9. Photonics-on-a-chip: recent advances in integrated waveguides as enabling detection elements for real-world, lab-on-a-chip biosensing applications.

    Science.gov (United States)

    Washburn, Adam L; Bailey, Ryan C

    2011-01-21

    By leveraging advances in semiconductor microfabrication technologies, chip-integrated optical biosensors are poised to make an impact as scalable and multiplexable bioanalytical measurement tools for lab-on-a-chip applications. In particular, waveguide-based optical sensing technology appears to be exceptionally amenable to chip integration and miniaturization, and, as a result, the recent literature is replete with examples of chip-integrated waveguide sensing platforms developed to address a wide range of contemporary analytical challenges. As an overview of the most recent advances within this dynamic field, this review highlights work from the last 2-3 years in the areas of grating-coupled, interferometric, photonic crystal, and microresonator waveguide sensors. With a focus towards device integration, particular emphasis is placed on demonstrations of biosensing using these technologies within microfluidically controlled environments. In addition, examples of multiplexed detection and sensing within complex matrices--important features for real-world applicability--are given special attention.

  10. A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2018-01-01

    Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

  11. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  12. Optimal selection of TLD chips

    International Nuclear Information System (INIS)

    Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

    1996-01-01

    Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

  13. X-ray imaging with photon counting hybrid semiconductor pixel detectors

    CERN Document Server

    Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

    1999-01-01

    Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

  14. Conductivity in transparent oxide semiconductors.

    Science.gov (United States)

    King, P D C; Veal, T D

    2011-08-24

    conductivity in TCOs. We discuss models that attempt to explain both the bulk and surface conductivity on the basis of bulk band structure features common across the TCOs, and compare these materials to other semiconductors. Finally, we briefly consider transparency in these materials, and its interplay with conductivity. Understanding this interplay, as well as the microscopic contenders for providing the conductivity of these materials, will prove essential to the future design and control of TCO semiconductors, and their implementation into novel multifunctional devices. © 2011 IOP Publishing Ltd

  15. The artificial satellite observation chronograph controlled by single chip microcomputer.

    Science.gov (United States)

    Pan, Guangrong; Tan, Jufan; Ding, Yuanjun

    1991-06-01

    The instrument specifications, hardware structure, software design, and other characteristics of the chronograph mounting on a theodolite used for artificial satellite observation are presented. The instrument is a real time control system with a single chip microcomputer.

  16. Digitally tunable dual wavelength emission from semiconductor ring lasers with filtered optical feedback

    International Nuclear Information System (INIS)

    Khoder, Mulham; Verschaffelt, Guy; Nguimdo, Romain Modeste; Danckaert, Jan; Leijtens, Xaveer; Bolk, Jeroen

    2013-01-01

    We report on a novel integrated approach to obtain dual wavelength emission from a semiconductor laser based on on-chip filtered optical feedback. Using this approach, we show experiments and numerical simulations of dual wavelength emission of a semiconductor ring laser. The filtered optical feedback is realized on-chip by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifiers are placed in the feedback loop in order to control the feedback strength of each wavelength channel independently. By tuning the current injected into each of the amplifiers, we can effectively cancel the gain difference between the wavelength channels due to fabrication and material dichroism, thus resulting in stable dual wavelength emission. We also explore the accuracy needed in the operational parameters to maintain this dual wavelength emission. (letter)

  17. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  18. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally...

  19. Method of doping a semiconductor

    International Nuclear Information System (INIS)

    Yang, C.Y.; Rapp, R.A.

    1983-01-01

    A method is disclosed for doping semiconductor material. An interface is established between a solid electrolyte and a semiconductor to be doped. The electrolyte is chosen to be an ionic conductor of the selected impurity and the semiconductor material and electrolyte are jointly chosen so that any compound formed from the impurity and the semiconductor will have a free energy no lower than the electrolyte. A potential is then established across the interface so as to allow the impurity ions to diffuse into the semiconductor. In one embodiment the semiconductor and electrolyte may be heated so as to increase the diffusion coefficient

  20. Dynamic On-Chip micro Temperature and Flow Sensor for miniaturized lab-on-a-chip instruments

    Data.gov (United States)

    National Aeronautics and Space Administration — The purpose of this project is to design, fabricate, and characterize a Dynamic On-Chip Flow and Temperature Sensor (DOCFlaTS) to mature and enable miniaturized...

  1. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  2. Self-powered integrated systems-on-chip (energy chip)

    Science.gov (United States)

    Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

    2010-04-01

    In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  3. Fundamentals of semiconductor lasers

    CERN Document Server

    Numai, Takahiro

    2015-01-01

    This book explains physics under the operating principles of semiconductor lasers in detail based on the experience of the author, dealing with the first manufacturing of phase-shifted DFB-LDs and recent research on transverse modes.   The book also bridges a wide gap between journal papers and textbooks, requiring only an undergraduate-level knowledge of electromagnetism and quantum mechanics, and helps readers to understand journal papers where definitions of some technical terms vary, depending on the paper. Two definitions of the photon density in the rate equations and two definitions of the phase-shift in the phase-shifted DFB-LD are explained, and differences in the calculated results are indicated, depending on the definitions.    Readers can understand the physics of semiconductor lasers and analytical tools for Fabry-Perot LDs, DFB-LDs, and VCSELs and will be stimulated to develop semiconductor lasers themselves.

  4. Coherent dynamics in semiconductors

    DEFF Research Database (Denmark)

    Hvam, Jørn Märcher

    1998-01-01

    enhanced in quantum confined lower-dimensional systems, where exciton and biexciton effects dominate the spectra even at room temperature. The coherent dynamics of excitons are at modest densities well described by the optical Bloch equations and a number of the dynamical effects known from atomic......Ultrafast nonlinear optical spectroscopy is used to study the coherent dynamics of optically excited electron-hole pairs in semiconductors. Coulomb interaction implies that the optical inter-band transitions are dominated, at least at low temperatures, by excitonic effects. They are further...... and molecular systems are found and studied in the exciton-biexciton system of semiconductors. At densities where strong exciton interactions, or many-body effects, become dominant, the semiconductor Bloch equations present a more rigorous treatment of the phenomena Ultrafast degenerate four-wave mixing is used...

  5. Hydrogen in semiconductors II

    CERN Document Server

    Nickel, Norbert H; Weber, Eicke R; Nickel, Norbert H

    1999-01-01

    Since its inception in 1966, the series of numbered volumes known as Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. The "Willardson and Beer" Series, as it is widely known, has succeeded in publishing numerous landmark volumes and chapters. Not only did many of these volumes make an impact at the time of their publication, but they continue to be well-cited years after their original release. Recently, Professor Eicke R. Weber of the University of California at Berkeley joined as a co-editor of the series. Professor Weber, a well-known expert in the field of semiconductor materials, will further contribute to continuing the series' tradition of publishing timely, highly relevant, and long-impacting volumes. Some of the recent volumes, such as Hydrogen in Semiconductors, Imperfections in III/V Materials, Epitaxial Microstructures, High-Speed Heterostructure Devices, Oxygen in Silicon, and others promise that this tradition ...

  6. Photoelectronic properties of semiconductors

    CERN Document Server

    Bube, Richard H

    1992-01-01

    The interaction between light and electrons in semiconductors forms the basis for many interesting and practically significant properties. This book examines the fundamental physics underlying this rich complexity of photoelectronic properties of semiconductors, and will familiarise the reader with the relatively simple models that are useful in describing these fundamentals. The basic physics is also illustrated with typical recent examples of experimental data and observations. Following introductory material on the basic concepts, the book moves on to consider a wide range of phenomena, including photoconductivity, recombination effects, photoelectronic methods of defect analysis, photoeffects at grain boundaries, amorphous semiconductors, photovoltaic effects and photoeffects in quantum wells and superlattices. The author is Professor of Materials Science and Electrical Engineering at Stanford University, and has taught this material for many years. He is an experienced author, his earlier books having fo...

  7. Ultranarrow polaritons in a semiconductor microcavity

    DEFF Research Database (Denmark)

    Jensen, Jacob Riis; Borri, Paola; Langbein, Wolfgang

    2000-01-01

    We have achieved a record high ratio (19) of the Rabi splitting (3.6 meV) to the polariton linewidth (190 mu eV), in a semiconductor lambda microcavity with a single 25 nm GaAs quantum well at the antinode. The narrow polariton lines are obtained with a special cavity design which reduces...

  8. Ballistic transport in semiconductor nanostructures: From quasi ...

    Indian Academy of Sciences (India)

    By suitable design it is possible to achieve quasi-ballistic transport in semiconductor nanostructures over times up to the ps-range. Monte-Carlo simulations reveal that under these conditions phase-coherent real-space oscillations of an electron ensemble, generated by fs-pulses become possible in wide potential wells.

  9. Metal-semiconductor, composite radiation detectors

    International Nuclear Information System (INIS)

    Orvis, W.J.; Yee, J.H.; Fuess, D.

    1992-12-01

    In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with the good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high-efficiency, room temperature gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, the authors have procured and tested a commercial device with operating characteristics similar to those of a single layer of the composite device. They have modeled the radiation transport in a multi-layered device, to verify the initial calculations of layer thickness and composition. They have modeled the electrostatic field in different device designs to locate and remove high-field regions that can cause device breakdown. They have fabricated 14 single layer prototypes

  10. FISH & CHIPS: Four Electrode Conductivity / Salinity Sensor on a Silicon Multi-sensor chip for Fisheries Research

    DEFF Research Database (Denmark)

    Hyldgård, Anders; Olafsdottir, Iris; Olesen, M.

    2005-01-01

    The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given......The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given...

  11. Bio-patch design and implementation based on a low-power system-on-chip and paper-based inkjet printing technology.

    Science.gov (United States)

    Yang, Geng; Xie, Li; Mantysalo, Matti; Chen, Jian; Tenhunen, Hannu; Zheng, L R

    2012-11-01

    This paper presents the prototype implementation of a Bio-Patch using fully integrated low-power System-on-Chip (SoC) sensor and paper-based inkjet printing technology. The SoC sensor is featured with programmable gain and bandwidth to accommodate a variety of bio-signals. It is fabricated in a 0.18-ìm standard CMOS technology, with a total power consumption of 20 ìW from a 1.2 V supply. Both the electrodes and interconnections are implemented by printing conductive nano-particle inks on a flexible photo paper substrate using inkjet printing technology. A Bio-Patch prototype is developed by integrating the SoC sensor, a soft battery, printed electrodes and interconnections on a photo paper substrate. The Bio-Patch can work alone or operate along with other patches to establish a wired network for synchronous multiple-channel bio-signals recording. The measurement results show that electrocardiogram and electromyogram are successfully measured in in-vivo tests using the implemented Bio-Patch prototype.

  12. Reduced filamentation in high power semiconductor lasers

    DEFF Research Database (Denmark)

    Skovgaard, Peter M. W.; McInerney, John; O'Brien, Peter

    1999-01-01

    High brightness semiconductor lasers have applications in fields ranging from material processing to medicine. The main difficulty associated with high brightness is that high optical power densities cause damage to the laser facet and thus require large apertures. This, in turn, results in spatio......-temporal instabilities such as filamentation which degrades spatial coherence and brightness. We first evaluate performance of existing designs with a “top-hat” shaped transverse current density profile. The unstable nature of highly excited semiconductor material results in a run-away process where small modulations...

  13. Lab-on a-Chip

    Science.gov (United States)

    1999-01-01

    Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

  14. The ATLAS semiconductor tracker (SCT)

    International Nuclear Information System (INIS)

    Jackson, J.N.

    2005-01-01

    The ATLAS detector (CERN,LHCC,94-43 (1994)) is designed to study a wide range of physics at the CERN Large Hadron Collider (LHC) at luminosities up to 10 34 cm -2 s -1 with a bunch-crossing rate of 40 MHz. The Semiconductor Tracker (SCT) forms a key component of the Inner Detector (vol. 1, ATLAS TDR 4, CERN,LHCC 97-16 (1997); vol. 2, ATLAS TDR 5, CERN,LHCC 97-17 (1997)) which is situated inside a 2 T solenoid field. The ATLAS Semiconductor Tracker (SCT) utilises 4088 silicon modules with binary readout mounted on carbon fibre composite structures arranged in the forms of barrels in the central region and discs in the forward region. The construction of the SCT is now well advanced. The design of the SCT modules, services and support structures will be briefly outlined. A description of the various stages in the construction process will be presented with examples of the performance achieved and the main difficulties encountered. Finally, the current status of the construction is reviewed

  15. Advances in semiconductor lasers

    CERN Document Server

    Coleman, James J; Jagadish, Chennupati

    2012-01-01

    Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scien

  16. Superconductivity in doped semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Bustarret, E., E-mail: Etienne.bustarret@neel.cnrs.fr

    2015-07-15

    A historical survey of the main normal and superconducting state properties of several semiconductors doped into superconductivity is proposed. This class of materials includes selenides, tellurides, oxides and column-IV semiconductors. Most of the experimental data point to a weak coupling pairing mechanism, probably phonon-mediated in the case of diamond, but probably not in the case of strontium titanate, these being the most intensively studied materials over the last decade. Despite promising theoretical predictions based on a conventional mechanism, the occurrence of critical temperatures significantly higher than 10 K has not been yet verified. However, the class provides an enticing playground for testing theories and devices alike.

  17. Semiconductor opto-electronics

    CERN Document Server

    Moss, TS; Ellis, B

    1972-01-01

    Semiconductor Opto-Electronics focuses on opto-electronics, covering the basic physical phenomena and device behavior that arise from the interaction between electromagnetic radiation and electrons in a solid. The first nine chapters of this book are devoted to theoretical topics, discussing the interaction of electromagnetic waves with solids, dispersion theory and absorption processes, magneto-optical effects, and non-linear phenomena. Theories of photo-effects and photo-detectors are treated in detail, including the theories of radiation generation and the behavior of semiconductor lasers a

  18. Ternary chalcopyrite semiconductors

    CERN Document Server

    Shay, J L; Pamplin, B R

    2013-01-01

    Ternary Chalcopyrite Semiconductors: Growth, Electronic Properties, and Applications covers the developments of work in the I-III-VI2 and II-IV-V2 ternary chalcopyrite compounds. This book is composed of eight chapters that focus on the crystal growth, characterization, and applications of these compounds to optical communications systems. After briefly dealing with the status of ternary chalcopyrite compounds, this book goes on describing the crystal growth of II-IV-V2 and I-III-VI2 single crystals. Chapters 3 and 4 examine the energy band structure of these semiconductor compounds, illustrat

  19. Compound semiconductor device physics

    CERN Document Server

    Tiwari, Sandip

    2013-01-01

    This book provides one of the most rigorous treatments of compound semiconductor device physics yet published. A complete understanding of modern devices requires a working knowledge of low-dimensional physics, the use of statistical methods, and the use of one-, two-, and three-dimensional analytical and numerical analysis techniques. With its systematic and detailed**discussion of these topics, this book is ideal for both the researcher and the student. Although the emphasis of this text is on compound semiconductor devices, many of the principles discussed will also be useful to those inter

  20. Introductory semiconductor device physics

    CERN Document Server

    Parker, Greg

    2004-01-01

    ATOMS AND BONDINGThe Periodic TableIonic BondingCovalent BondingMetallic bondingvan der Waals BondingStart a DatabaseENERGY BANDS AND EFFECTIVE MASSSemiconductors, Insulators and MetalsSemiconductorsInsulatorsMetalsThe Concept of Effective MassCARRIER CONCENTRATIONS IN SEMICONDUCTORSDonors and AcceptorsFermi-LevelCarrier Concentration EquationsDonors and Acceptors Both PresentCONDUCTION IN SEMICONDUCTORSCarrier DriftCarrier MobilitySaturated Drift VelocityMobility Variation with TemperatureA Derivation of Ohm's LawDrift Current EquationsSemiconductor Band Diagrams with an Electric Field Presen

  1. Particles in Semiconductor Processing

    NARCIS (Netherlands)

    Knotter, D. Martin; Wali, F.; Kohli, Rajiv; Mittal, Kashmiri L.

    2010-01-01

    Advances in integrated circuits (ICs) have a high impact on society. These advances result in continuously increasing performance of home personal computers, higher density flash memory chips, faster wireless communication in combination with smaller antennas, and all kinds of combinations of the

  2. Extracting hot carriers from photoexcited semiconductor nanocrystals

    Energy Technology Data Exchange (ETDEWEB)

    Zhu, Xiaoyang

    2014-12-10

    This research program addresses a fundamental question related to the use of nanomaterials in solar energy -- namely, whether semiconductor nanocrystals (NCs) can help surpass the efficiency limits, the so-called “Shockley-Queisser” limit, in conventional solar cells. In these cells, absorption of photons with energies above the semiconductor bandgap generates “hot” charge carriers that quickly “cool” to the band edges before they can be utilized to do work; this sets the solar cell efficiency at a limit of ~31%. If instead, all of the energy of the hot carriers could be captured, solar-to-electric power conversion efficiencies could be increased, theoretically, to as high as 66%. A potential route to capture this energy is to utilize semiconductor nanocrystals. In these materials, the quasi-continuous conduction and valence bands of the bulk semiconductor become discretized due to confinement of the charge carriers. Consequently, the energy spacing between the electronic levels can be much larger than the highest phonon frequency of the lattice, creating a “phonon bottleneck” wherein hot-carrier relaxation is possible via slower multiphonon emission. For example, hot-electron lifetimes as long as ~1 ns have been observed in NCs grown by molecular beam epitaxy. In colloidal NCs, long lifetimes have been demonstrated through careful design of the nanocrystal interfaces. Due to their ability to slow electronic relaxation, semiconductor NCs can in principle enable extraction of hot carriers before they cool to the band edges, leading to more efficient solar cells.

  3. Fabrication and application of amorphous semiconductor devices

    International Nuclear Information System (INIS)

    Kumurdjian, Pierre.

    1976-01-01

    This invention concerns the design and manufacture of elecric switching or memorisation components with amorphous semiconductors. As is known some compounds, particularly the chalcogenides, have a resistivity of the semiconductor type in the amorphous solid state. These materials are obtained by the high temperature homogeneisation of several single elements such as tellurium, arsenic, germanium and sulphur, followed by water or air quenching. In particular these compounds have useful switching and memorisation properties. In particular they have the characteristic of not suffering deterioration when placed in an environment subjected to nuclear radiations. In order to know more about the nature and properties of these amorphous semiconductors the French patent No. 71 28048 of 30 June 1971 may be consulted with advantage [fr

  4. Semiconductor laser using multimode interference principle

    Science.gov (United States)

    Gong, Zisu; Yin, Rui; Ji, Wei; Wu, Chonghao

    2018-01-01

    Multimode interference (MMI) structure is introduced in semiconductor laser used in optical communication system to realize higher power and better temperature tolerance. Using beam propagation method (BPM), Multimode interference laser diode (MMI-LD) is designed and fabricated in InGaAsP/InP based material. As a comparison, conventional semiconductor laser using straight single-mode waveguide is also fabricated in the same wafer. With a low injection current (about 230 mA), the output power of the implemented MMI-LD is up to 2.296 mW which is about four times higher than the output power of the conventional semiconductor laser. The implemented MMI-LD exhibits stable output operating at the wavelength of 1.52 μm and better temperature tolerance when the temperature varies from 283.15 K to 293.15 K.

  5. Tunable radiation emitting semiconductor device

    NARCIS (Netherlands)

    2009-01-01

    A tunable radiation emitting semiconductor device includes at least one elongated structure at least partially fabricated from one or more semiconductor materials exhibiting a bandgap characteristic including one or more energy transitions whose energies correspond to photon energies of light

  6. Simulation of semiconductor devices

    International Nuclear Information System (INIS)

    Oriato, D.

    2001-09-01

    In this thesis a drift diffusion model coupled with self-consistent solutions of Poisson's and Schroedinger's equations, is developed and used to investigate the operation of Gunn diodes and GaN-based LEDs. The model also includes parameters derived from Monte Carlo calculations of the simulated devices. In this way the characteristics of a Monte Carlo approach and of a quantum solver are built into a fast and flexible drift-diffusion model that can be used for testing a large number of heterostructure designs in a time-effective way. The full model and its numerical implementation are described in chapter 2. In chapter 3 the theory of Gunn diodes is presented. A basic model of the dynamics of domain formation and domain transport is described with particular regard to accumulation and dipole domains. Several modes of operation of the Gunn device are described, varying from the resonance mode to the quenched mode. Details about transferred electron devices and negative differential resistance in semiconductor materials are given. In chapter 4 results from the simulation of a simple conventional gunn device confirm the importance of the doping condition at the cathode. Accumulation or dipole domains are achieved respectively with high and low doping densities. The limits of a conventional Gunn diode are explained and solved by introducing the heterostructure Gunn diode. This new design consists of a conventional GaAs transit region coupled with an electron launcher at the cathode, made using an AIGaAs heterostructure step. Simulations show the importance of the insertion of a thin highly-doped layer between the transit region and the electron launcher in order to improve device operation. Chapter 5 is an introduction to Ill-nitrides, in particular GaN and its alloy ln-GaN. We outline the discrepancy in the elastic and piezoelectric parameters found in the literature. Strain, dislocations and piezoelectricity are presented as the main features of a InGaN/GaN system

  7. Design of 20-44 GHz broadband doubler MMIC

    International Nuclear Information System (INIS)

    Li Qin; Wang Zhigong; Li Wei

    2010-01-01

    This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at V DD = 3.5 V, V SS = -3.5 V, I d = 200 mA and the chip size is 1.5 x 1.8 mm 2 . (semiconductor integrated circuits)

  8. SiliPET: Design of an ultra-high resolution small animal PET scanner based on stacks of semi-conductor detectors

    International Nuclear Information System (INIS)

    Cesca, N.; Auricchio, N.; Di Domenico, G.; Zavattini, G.; Malaguti, R.; Andritschke, R.; Kanbach, G.; Schopper, F.

    2007-01-01

    We studied with Monte Carlo simulations, using the EGSnrc code, a new scanner for small animal positron emission tomography (PET), based on stacks of double-sided semiconductor detectors. Each stack is composed of planar detectors with dimension 70x60x1 mm 3 and orthogonal strips on both sides with 500 μm pitch to read the two interaction coordinates, the third being the detector number in the stack. Multiple interactions in a stack are discarded. In this way, we achieve a precise determination of the first interaction point of the two 511 keV photons. The reduced dimensions of the scanner also improve the solid angle coverage resulting in a high sensitivity. Preliminary results of scanners based on Si planar detectors are presented and the initial tomographic reconstructions demonstrate very good spatial resolution limited only by the positron range. This suggests that, this is a promising new approach for small animal PET imaging. We are testing some double-sided silicon detectors, equipped with 128 orthogonal p and n strips on opposite sides using VATAGP3 ASIC by IDEAS

  9. Physical principles of semiconductor detectors

    International Nuclear Information System (INIS)

    Micek, S.L.

    1979-01-01

    The general properties of semiconductors with respect to the possibilities of their use as the ionization radiation detectors are discussed. Some chosen types of semiconductor junctions and their characteristics are briefly presented. There are also discussed the physical phenomena connected with the formation of barriers in various types of semiconductor counters. Finally, the basic properties of three main types of semiconductor detectors are given. (author)

  10. Metal semiconductor contacts and devices

    CERN Document Server

    Cohen, Simon S; Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 13: Metal-Semiconductor Contacts and Devices presents the physics, technology, and applications of metal-semiconductor barriers in digital integrated circuits. The emphasis is placed on the interplay among the theory, processing, and characterization techniques in the development of practical metal-semiconductor contacts and devices.This volume contains chapters that are devoted to the discussion of the physics of metal-semiconductor interfaces and its basic phenomena; fabrication procedures; and interface characterization techniques, particularl

  11. Handbook of luminescent semiconductor materials

    CERN Document Server

    Bergman, Leah

    2011-01-01

    Photoluminescence spectroscopy is an important approach for examining the optical interactions in semiconductors and optical devices with the goal of gaining insight into material properties. With contributions from researchers at the forefront of this field, Handbook of Luminescent Semiconductor Materials explores the use of this technique to study semiconductor materials in a variety of applications, including solid-state lighting, solar energy conversion, optical devices, and biological imaging. After introducing basic semiconductor theory and photoluminescence principles, the book focuses

  12. Metal-semiconductor, composite radiation detectors

    International Nuclear Information System (INIS)

    Orvis, W.J.; Yee, J.H.; Fuess, D.A.

    1991-12-01

    In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high- efficiency gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, we have modeled parts of the detector and have nearly completed a prototype device. 2 refs

  13. Depletion field focusing in semiconductors

    NARCIS (Netherlands)

    Prins, M.W.J.; Gelder, Van A.P.

    1996-01-01

    We calculate the three-dimensional depletion field profile in a semiconductor, for a planar semiconductor material with a spatially varying potential upon the surface, and for a tip-shaped semiconductor with a constant surface potential. The nonuniform electric field gives rise to focusing or

  14. Nonlinear Elasticity of Doped Semiconductors

    Science.gov (United States)

    2017-02-01

    AFRL-RY-WP-TR-2016-0206 NONLINEAR ELASTICITY OF DOPED SEMICONDUCTORS Mark Dykman and Kirill Moskovtsev Michigan State University...2016 4. TITLE AND SUBTITLE NONLINEAR ELASTICITY OF DOPED SEMICONDUCTORS 5a. CONTRACT NUMBER FA8650-16-1-7600 5b. GRANT NUMBER 5c. PROGRAM...vibration amplitude. 15. SUBJECT TERMS semiconductors , microresonators, microelectromechanical 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF

  15. Designing quantum-information-processing superconducting qubit circuits that exhibit lasing and other atomic-physics-like phenomena on a chip

    Science.gov (United States)

    Nori, Franco

    2008-03-01

    Superconducting (SC) circuits can behave like atoms making transitions between a few energy levels. Such circuits can test quantum mechanics at macroscopic scales and be used to conduct atomic-physics experiments on a silicon chip. This talk overviews a few of our theoretical studies on SC circuits and quantum information processing (QIP) including: SC qubits for single photon generation and for lasing; controllable couplings among qubits; how to increase the coherence time of qubits using a capacitor in parallel to one of the qubit junctions; hybrid circuits involving both charge and flux qubits; testing Bell's inequality in SC circuits; generation of GHZ states; quantum tomography in SC circuits; preparation of macroscopic quantum superposition states of a cavity field via coupling to a SC qubit; generation of nonclassical photon states using a SC qubit in a microcavity; scalable quantum computing with SC qubits; and information processing with SC qubits in a microwave field. Controllable couplings between qubits can be achieved either directly or indirectly. This can be done with and without coupler circuits, and with and without data-buses like EM fields in cavities (e.g., we will describe both the variable-frequency magnetic flux approach and also a generalized double-resonance approach that we introduced). It is also possible to ``turn a quantum bug into a feature'' by using microscopic defects as qubits, and the macroscopic junction as a controller of it. We have also studied ways to implement radically different approaches to QIP by using ``cluster states'' in SC circuits. For a general overview of this field, see, J.Q. You and F. Nori, Phys. Today 58 (11), 42 (2005)

  16. Semi-conductor rectifiers

    International Nuclear Information System (INIS)

    1981-01-01

    A method is described for treating a semiconductor rectifier, comprising: heating the rectifier to a temperature in the range of 100 0 C to 500 0 C, irradiating the rectifier while maintaining its temperature within the said range, and then annealing the rectifier at a temperature of between 280 0 C and 350 0 C for between two and ten hours. (author)

  17. Semiconductor detector physics

    International Nuclear Information System (INIS)

    Equer, B.

    1987-01-01

    Comprehension of semiconductor detectors follows comprehension of some elements of solid state physics. They are recalled here, limited to the necessary physical principles, that is to say the conductivity. P-n and MIS junctions are discussed in view of their use in detection. Material and structure (MOS, p-n, multilayer, ..) are also reviewed [fr

  18. Reconfigurable engineered motile semiconductor microparticles.

    Science.gov (United States)

    Ohiri, Ugonna; Shields, C Wyatt; Han, Koohee; Tyler, Talmage; Velev, Orlin D; Jokerst, Nan

    2018-05-03

    Locally energized particles form the basis for emerging classes of active matter. The design of active particles has led to their controlled locomotion and assembly. The next generation of particles should demonstrate robust control over their active assembly, disassembly, and reconfiguration. Here we introduce a class of semiconductor microparticles that can be comprehensively designed (in size, shape, electric polarizability, and patterned coatings) using standard microfabrication tools. These custom silicon particles draw energy from external electric fields to actively propel, while interacting hydrodynamically, and sequentially assemble and disassemble on demand. We show that a number of electrokinetic effects, such as dielectrophoresis, induced charge electrophoresis, and diode propulsion, can selectively power the microparticle motions and interactions. The ability to achieve on-demand locomotion, tractable fluid flows, synchronized motility, and reversible assembly using engineered silicon microparticles may enable advanced applications that include remotely powered microsensors, artificial muscles, reconfigurable neural networks and computational systems.

  19. High throughput semiconductor deposition system

    Science.gov (United States)

    Young, David L.; Ptak, Aaron Joseph; Kuech, Thomas F.; Schulte, Kevin; Simon, John D.

    2017-11-21

    A reactor for growing or depositing semiconductor films or devices. The reactor may be designed for inline production of III-V materials grown by hydride vapor phase epitaxy (HVPE). The operating principles of the HVPE reactor can be used to provide a completely or partially inline reactor for many different materials. An exemplary design of the reactor is shown in the attached drawings. In some instances, all or many of the pieces of the reactor formed of quartz, such as welded quartz tubing, while other reactors are made from metal with appropriate corrosion resistant coatings such as quartz or other materials, e.g., corrosion resistant material, or stainless steel tubing or pipes may be used with a corrosion resistant material useful with HVPE-type reactants and gases. Using HVPE in the reactor allows use of lower-cost precursors at higher deposition rates such as in the range of 1 to 5 .mu.m/minute.

  20. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    International Nuclear Information System (INIS)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm 2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is −10.7 dBm/−8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is −0.6 °C/0.5 °C (−1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (−30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode. (semiconductor integrated circuits)

  1. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  2. Semiconductor nanostructures for artificial photosynthesis

    Science.gov (United States)

    Yang, Peidong

    2012-02-01

    Nanowires, with their unique capability to bridge the nanoscopic and macroscopic worlds, have already been demonstrated as important materials for different energy conversion. One emerging and exciting direction is their application for solar to fuel conversion. The generation of fuels by the direct conversion of solar energy in a fully integrated system is an attractive goal, but no such system has been demonstrated that shows the required efficiency, is sufficiently durable, or can be manufactured at reasonable cost. One of the most critical issues in solar water splitting is the development of a suitable photoanode with high efficiency and long-term durability in an aqueous environment. Semiconductor nanowires represent an important class of nanostructure building block for direct solar-to-fuel application because of their high surface area, tunable bandgap and efficient charge transport and collection. Nanowires can be readily designed and synthesized to deterministically incorporate heterojunctions with improved light absorption, charge separation and vectorial transport. Meanwhile, it is also possible to selectively decorate different oxidation or reduction catalysts onto specific segments of the nanowires to mimic the compartmentalized reactions in natural photosynthesis. In this talk, I will highlight several recent examples in this lab using semiconductor nanowires and their heterostructures for the purpose of direct solar water splitting.

  3. Charge transport in organic semiconductors.

    Science.gov (United States)

    Bässler, Heinz; Köhler, Anna

    2012-01-01

    Modern optoelectronic devices, such as light-emitting diodes, field-effect transistors and organic solar cells require well controlled motion of charges for their efficient operation. The understanding of the processes that determine charge transport is therefore of paramount importance for designing materials with improved structure-property relationships. Before discussing different regimes of charge transport in organic semiconductors, we present a brief introduction into the conceptual framework in which we interpret the relevant photophysical processes. That is, we compare a molecular picture of electronic excitations against the Su-Schrieffer-Heeger semiconductor band model. After a brief description of experimental techniques needed to measure charge mobilities, we then elaborate on the parameters controlling charge transport in technologically relevant materials. Thus, we consider the influences of electronic coupling between molecular units, disorder, polaronic effects and space charge. A particular focus is given to the recent progress made in understanding charge transport on short time scales and short length scales. The mechanism for charge injection is briefly addressed towards the end of this chapter.

  4. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  5. Amdahl 470 Chip Package

    CERN Multimedia

    1975-01-01

    In the late 70s the larger IBM computers were water cooled. Amdahl, an IBM competitor, invented an air cooling technology for it's computers. His company worked hard, developing a computer that was faster and less expensive than the IBM System/360 mainframe computer systems. This object contains an actual Amdahl series 470 computer logic chip with an air cooling device mounted on top. The package leads and cooling tower are gold-plated.

  6. Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

    Science.gov (United States)

    Wysocki, Gerard (Inventor); Tittel, Frank K. (Inventor); Curl, Robert F. (Inventor)

    2010-01-01

    A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

  7. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  8. Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

    Science.gov (United States)

    Biyikli, Necmi; Haider, Ali

    2017-09-01

    In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

  9. Temperature dependent electronic conduction in semiconductors

    International Nuclear Information System (INIS)

    Roberts, G.G.; Munn, R.W.

    1980-01-01

    This review describes the temperature dependence of bulk-controlled electronic currents in semiconductors. The scope of the article is wide in that it contrasts conduction mechanisms in inorganic and organic solids and also single crystal and disordered semiconductors. In many experimental situations it is the metal-semiconductor contact or the interface between two dissimilar semiconductors that governs the temperature dependence of the conductivity. However, in order to keep the length of the review within reasonable bounds, these topics have been largely avoided and emphasis is therefore placed on bulk-limited currents. A central feature of electronic conduction in semiconductors is the concentrations of mobile electrons and holes that contribute to the conductivity. Various statistical approaches may be used to calculate these densities which are normally strongly temperature dependent. Section 1 emphasizes the relationship between the position of the Fermi level, the distribution of quantum states, the total number of electrons available and the absolute temperature of the system. The inclusion of experimental data for several materials is designed to assist the experimentalist in his interpretation of activation energy curves. Sections 2 and 3 refer to electronic conduction in disordered solids and molecular crystals, respectively. In these cases alternative approaches to the conventional band theory approach must be considered. For example, the velocities of the charge carriers are usually substantially lower than those in conventional inorganic single crystal semiconductors, thus introducing the possibility of an activated mobility. Some general electronic properties of these materials are given in the introduction to each of these sections and these help to set the conduction mechanisms in context. (orig.)

  10. Reliability, Availability and Serviceability of Networks-on-Chip

    CERN Document Server

    Cota, Érika; Soares Lubaszewski, Marcelo

    2012-01-01

    This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

  11. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  12. Optically pumped semiconductor lasers for atomic and molecular physics

    Science.gov (United States)

    Burd, S.; Leibfried, D.; Wilson, A. C.; Wineland, D. J.

    2015-03-01

    Experiments in atomic, molecular and optical (AMO) physics rely on lasers at many different wavelengths and with varying requirements on spectral linewidth, power and intensity stability. Optically pumped semiconductor lasers (OPSLs), when combined with nonlinear frequency conversion, can potentially replace many of the laser systems currently in use. We are developing a source for laser cooling and spectroscopy of Mg+ ions at 280 nm, based on a frequency quadrupled OPSL with the gain chip fabricated at the ORC at Tampere Univ. of Technology, Finland. This OPSL system could serve as a prototype for many other sources used in atomic and molecular physics.

  13. Integration of microelectronic chips in microfluidic systems on printed circuit board

    International Nuclear Information System (INIS)

    Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

    2012-01-01

    A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

  14. Design of a passive UHF RFID tag for the ISO18000-6C protocol

    International Nuclear Information System (INIS)

    Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong

    2011-01-01

    This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under ±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μW with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μm CMOS technology and the chip size is 880 x 880 μm 2 . (semiconductor integrated circuits)

  15. Design of a passive UHF RFID tag for the ISO18000-6C protocol

    Energy Technology Data Exchange (ETDEWEB)

    Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong, E-mail: wangyao220597@yahoo.com.cn [RFIC Laboratory CICS, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731 (China)

    2011-05-15

    This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under {+-}4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 {mu}W with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 {mu}m CMOS technology and the chip size is 880 x 880 {mu}m{sup 2}. (semiconductor integrated circuits)

  16. Rational design of monocrystalline (InP)(y)Ge(5-2y)/Ge/Si(100) semiconductors: synthesis and optical properties.

    Science.gov (United States)

    Sims, Patrick E; Chizmeshya, Andrew V G; Jiang, Liying; Beeler, Richard T; Poweleit, Christian D; Gallagher, James; Smith, David J; Menéndez, José; Kouvetakis, John

    2013-08-21

    In this work, we extend our strategy previously developed to synthesize functional, crystalline Si(5-2y)(AlX)y {X = N,P,As} semiconductors to a new class of Ge-III-V hybrid compounds, leading to the creation of (InP)(y)Ge(5-2y) analogues. The compounds are grown directly on Ge-buffered Si(100) substrates using gas source MBE by tuning the interaction between Ge-based P(GeH3)3 precursors and In atoms to yield nanoscale "In-P-Ge3" building blocks, which then confer their molecular structure and composition to form the target solids via complete elimination of H2. The collateral production of reactive germylene (GeH2), via partial decomposition of P(GeH3)3, is achieved by simple adjustment of the deposition conditions, leading to controlled Ge enrichment of the solid product relative to the stoichiometric InPGe3 composition. High resolution XRD, XTEM, EDX, and RBS indicate that the resultant monocrystalline (InP)(y)Ge(5-2y) alloys with y = 0.3-0.7 are tetragonally strained and fully coherent with the substrate and possess a cubic diamond-like structure. Molecular and solid-state ab initio density functional theory (DFT) simulations support the viability of "In-P-Ge3" building-block assembly of the proposed crystal structures, which consist of a Ge parent crystal in which the P atoms form a third-nearest-neighbor sublattice and "In-P" dimers are oriented to exclude energetically unfavorable In-In bonding. The observed InP concentration dependence of the lattice constant is closely reproduced by DFT simulation of these model structures. Raman spectroscopy and ellipsometry are also consistent with the "In-P-Ge3" building-block interpretation of the crystal structure, while the observation of photoluminescence suggests that (InP)(y)Ge(5-2y) may have important optoelectronic applications.

  17. Fundamentals of semiconductor manufacturing and process control

    CERN Document Server

    May, Gary S

    2006-01-01

    A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems. Readers are introduced to both the theory and practice of all basic manufacturing concepts. Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields. The discussion of statistical experimental design offers readers a powerful approach for systematically varying controllable p...

  18. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    Energy Technology Data Exchange (ETDEWEB)

    Ma Haifeng; Zhou Feng, E-mail: fengzhou@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-01-15

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 {mu}m CMOS technology and occupies an active area as small as 220 x 320 {mu}m{sup 2}, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 {mu}A quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  19. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    International Nuclear Information System (INIS)

    Ma Haifeng; Zhou Feng

    2010-01-01

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 x 320 μm 2 , which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  20. Single frequency semiconductor lasers

    CERN Document Server

    Fang, Zujie; Chen, Gaoting; Qu, Ronghui

    2017-01-01

    This book systematically introduces the single frequency semiconductor laser, which is widely used in many vital advanced technologies, such as the laser cooling of atoms and atomic clock, high-precision measurements and spectroscopy, coherent optical communications, and advanced optical sensors. It presents both the fundamentals and characteristics of semiconductor lasers, including basic F-P structure and monolithic integrated structures; interprets laser noises and their measurements; and explains mechanisms and technologies relating to the main aspects of single frequency lasers, including external cavity lasers, frequency stabilization technologies, frequency sweeping, optical phase locked loops, and so on. It paints a clear, physical picture of related technologies and reviews new developments in the field as well. It will be a useful reference to graduate students, researchers, and engineers in the field.

  1. Basic semiconductor physics

    CERN Document Server

    Hamaguchi, Chihiro

    2017-01-01

    This book presents a detailed description of basic semiconductor physics. The text covers a wide range of important phenomena in semiconductors, from the simple to the advanced. Four different methods of energy band calculations in the full band region are explained: local empirical pseudopotential, non-local pseudopotential, KP perturbation and tight-binding methods. The effective mass approximation and electron motion in a periodic potential, Boltzmann transport equation and deformation potentials used for analysis of transport properties are discussed. Further, the book examines experiments and theoretical analyses of cyclotron resonance in detail. Optical and transport properties, magneto-transport, two-dimensional electron gas transport (HEMT and MOSFET) and quantum transport are reviewed, while optical transition, electron-phonon interaction and electron mobility are also addressed. Energy and electronic structure of a quantum dot (artificial atom) are explained with the help of Slater determinants. The...

  2. Three dimensional strained semiconductors

    Science.gov (United States)

    Voss, Lars; Conway, Adam; Nikolic, Rebecca J.; Leao, Cedric Rocha; Shao, Qinghui

    2016-11-08

    In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

  3. Silicon-Chip-Based Optical Frequency Combs

    Science.gov (United States)

    2015-10-26

    fiber-based polarization controllers and a polarization beam splitter , and the output power is monitored with a sensitive photodiode. We use a...a single CW laser beam coupled to a microresonators can produce stabilized, octave-spanning combs through highly cascaded four-wave mixing (FWM...resonator designs , the resonator and the coupling waveguide are monolithically integrated. Thus, the entire on-chip configuration of CMOS-compatible

  4. Images through semiconductors

    International Nuclear Information System (INIS)

    Anon.

    1986-01-01

    Improved image processing techniques are constantly being developed for television and for scanners using X-rays or other radiation for industrial or medical applications, etc. As Erik Heijne of CERN explains here, particle physics too has its own special requirements for image processing. The increasing use of semiconductor techniques for handling measurements down to the level of a few microns provides another example of the close interplay between scientific research and technological development. (orig.).

  5. Muonium states in semiconductors

    International Nuclear Information System (INIS)

    Patterson, B.D.

    1987-01-01

    There is a brief summary of what is known about the muonium states isotropic, anisotropic and diamagnetic in diamond and zincblende semiconductors. The report deals with muonium spectroscopy, including the formation probabilities, hyperfine parameters and electronic g-factors of the states. The dynamics of the states is treated including a discussion of the transition from isotropic Mu to anisotropic Mu in diamond, temperature-dependent linewidthes in silicon and germanium and effects of daping and radiation damage

  6. Nonradiative recombination in semiconductors

    CERN Document Server

    Abakumov, VN; Yassievich, IN

    1991-01-01

    In recent years, great progress has been made in the understandingof recombination processes controlling the number of excessfree carriers in semiconductors under nonequilibrium conditions. As a result, it is now possible to give a comprehensivetheoretical description of these processes. The authors haveselected a number of experimental results which elucidate theunderlying physical problems and enable a test of theoreticalmodels. The following topics are dealt with: phenomenological theory ofrecombination, theoretical models of shallow and deep localizedstates, cascade model of carrier captu

  7. Isotopically controlled semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Haller, Eugene E.

    2006-06-19

    The following article is an edited transcript based on the Turnbull Lecture given by Eugene E. Haller at the 2005 Materials Research Society Fall Meeting in Boston on November 29, 2005. The David Turnbull Lectureship is awarded to recognize the career of a scientist who has made outstanding contributions to understanding materials phenomena and properties through research, writing, and lecturing, as exemplified by the life work of David Turnbull. Haller was named the 2005 David Turnbull Lecturer for his 'pioneering achievements and leadership in establishing the field of isotopically engineered semiconductors; for outstanding contributions to materials growth, doping and diffusion; and for excellence in lecturing, writing, and fostering international collaborations'. The scientific interest, increased availability, and technological promise of highly enriched isotopes have led to a sharp rise in the number of experimental and theoretical studies with isotopically controlled semiconductor crystals. This article reviews results obtained with isotopically controlled semiconductor bulk and thin-film heterostructures. Isotopic composition affects several properties such as phonon energies, band structure, and lattice constant in subtle, but, for their physical understanding, significant ways. Large isotope-related effects are observed for thermal conductivity in local vibrational modes of impurities and after neutron transmutation doping. Spectacularly sharp photoluminescence lines have been observed in ultrapure, isotopically enriched silicon crystals. Isotope multilayer structures are especially well suited for simultaneous self- and dopant-diffusion studies. The absence of any chemical, mechanical, or electrical driving forces makes possible the study of an ideal random-walk problem. Isotopically controlled semiconductors may find applications in quantum computing, nanoscience, and spintronics.

  8. Survey of semiconductor physics

    CERN Document Server

    Böer, Karl W

    1992-01-01

    Any book that covers a large variety of subjects and is written by one author lacks by necessity the depth provided by an expert in his or her own field of specialization. This book is no exception. It has been written with the encouragement of my students and colleagues, who felt that an extensive card file I had accumulated over the years of teaching solid state and semiconductor physics would be helpful to more than just a few of us. This file, updated from time to time, contained lecture notes and other entries that were useful in my research and permitted me to give to my students a broader spectrum of information than is available in typical textbooks. When assembling this material into a book, I divided the top­ ics into material dealing with the homogeneous semiconductor, the subject of the previously published Volume 1, and the inhomoge­ neous semiconductor, the subject of this Volume 2. In order to keep the book to a manageable size, sections of tutorial character which can be used as text for a g...

  9. The Physics of Semiconductors

    Science.gov (United States)

    Brennan, Kevin F.

    1999-02-01

    Modern fabrication techniques have made it possible to produce semiconductor devices whose dimensions are so small that quantum mechanical effects dominate their behavior. This book describes the key elements of quantum mechanics, statistical mechanics, and solid-state physics that are necessary in understanding these modern semiconductor devices. The author begins with a review of elementary quantum mechanics, and then describes more advanced topics, such as multiple quantum wells. He then disusses equilibrium and nonequilibrium statistical mechanics. Following this introduction, he provides a thorough treatment of solid-state physics, covering electron motion in periodic potentials, electron-phonon interaction, and recombination processes. The final four chapters deal exclusively with real devices, such as semiconductor lasers, photodiodes, flat panel displays, and MOSFETs. The book contains many homework exercises and is suitable as a textbook for electrical engineering, materials science, or physics students taking courses in solid-state device physics. It will also be a valuable reference for practicing engineers in optoelectronics and related areas.

  10. The GenoChip: A New Tool for Genetic Anthropology

    Science.gov (United States)

    Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G.; Greenspan, Bennett; Spencer Wells, R.

    2013-01-01

    The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project’s new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic

  11. The GenoChip: a new tool for genetic anthropology.

    Science.gov (United States)

    Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G; Greenspan, Bennett; Spencer Wells, R

    2013-01-01

    The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project's new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic

  12. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  13. Fundamentals of semiconductor processing technology

    CERN Document Server

    El-Kareh, Badih

    1995-01-01

    The drive toward new semiconductor technologies is intricately related to market demands for cheaper, smaller, faster, and more reliable circuits with lower power consumption. The development of new processing tools and technologies is aimed at optimizing one or more of these requirements. This goal can, however, only be achieved by a concerted effort between scientists, engineers, technicians, and operators in research, development, and manufac­ turing. It is therefore important that experts in specific disciplines, such as device and circuit design, understand the principle, capabil­ ities, and limitations of tools and processing technologies. It is also important that those working on specific unit processes, such as lithography or hot processes, be familiar with other unit processes used to manufacture the product. Several excellent books have been published on the subject of process technologies. These texts, however, cover subjects in too much detail, or do not cover topics important to modem tech­ n...

  14. Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

    Science.gov (United States)

    Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

    2016-01-01

    Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

  15. Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

    Science.gov (United States)

    Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

    2004-07-01

    A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

  16. Temperature control of power semiconductor devices in traction applications

    Science.gov (United States)

    Pugachev, A. A.; Strekalov, N. N.

    2017-02-01

    The peculiarity of thermal management of traction frequency converters of a railway rolling stock is highlighted. The topology and the operation principle of the automatic temperature control system of power semiconductor modules of the traction frequency converter are designed and discussed. The features of semiconductors as an object of temperature control are considered; the equivalent circuit of thermal processes in the semiconductors is suggested, the power losses in the two-level voltage source inverters are evaluated and analyzed. The dynamic properties and characteristics of the cooling fan induction motor electric drive with the scalar control are presented. The results of simulation in Matlab are shown for the steady state of thermal processes.

  17. Gigabit chips: A case history of a transfer of federal technology

    Energy Technology Data Exchange (ETDEWEB)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs. (JDH)

  18. Gigabit chips: A case history of a transfer of federal technology

    International Nuclear Information System (INIS)

    Marcuse, W.

    1987-01-01

    This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs

  19. Thermodynamic concepts in semiconductor quantum dot technology

    International Nuclear Information System (INIS)

    Shchukin, V.

    2001-01-01

    Major trends of the modern civilization are related to the changing of the industrial society into an information and knowledge-based society. This transformation is to a large extent based on the modern information and communication technology. The nobel prize-2000 in physics is a remarkable recognition of an extremely high significance of this kind of technology. The nobel prize has been awarded with one half jointly to Zhores I. Alferov and Herbert Kroemer for developing semiconductor heterostructures used in high-speed- and opto-electronics and one half to Jack St. Clair Kilby for this part in the invention of the integrated circuit. The development of the semiconductor heterostructures technology requires a profound understanding of the basic growth mechanisms involved in any technological process, including any type of epitaxy, either the liquid phase epitaxy (LPE), or the metalorganic vapor phase epitaxy (MOVPE), or the molecular beam epitaxy (MBE). Starting from this pioneering works on semiconductor heterostructures till present time, Professor Zh. Alferov has always paid much attention to complex and comprehensive study of the subject. This covers the growth - as well as the post-growth technology including the theoretical modeling of the technology, the characterization of the heterostructures, and the device design. Such complex approach has master mined the scientific and technological success of Abraham loffe Institute in the area of semiconductor heterostructures, and later, nano structures. (Orig../A.B.)

  20. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  1. 基于AU6850C芯片的智能家居背景音乐播放模块的设计%Design of intelligent Home Furnishing background music playing module based on AU6850C chip

    Institute of Scientific and Technical Information of China (English)

    蔡建聪

    2015-01-01

    This paper introduces the design of hardware and software of intelligent Home Furnishing background music to STC12C5A60S2 decoding chip and MP3 AU6850C as the core of the playing module.This module provides USB and SD card interface, with liquid crystal display,serial communication and power-off memory function,intelligent Home Furnishing control board can realize the background music playing through the control of the music playing module.%本文介绍了以STC12C5A60S2单片机和MP3解码芯片AU6850C为核心的智能家居背景音乐播放模块的硬件及软件设计。该模块提供了USB和SD卡的接口,具有液晶显示、串口通讯及断电记忆功能,智能家居控制板可通过对音乐播放模块的控制实现背景音乐的播放。

  2. Simultaneous Mutation Detection in 90 Retinal Disease Genes in Multiple Patients Using a Custom-designed 300-kb Retinal Resequencing Chip

    NARCIS (Netherlands)

    Booij, Judith C.; Bakker, Arne 1; Kulumbetova, Jamilia; Moutaoukil, Youssef; Smeets, Bert; Verheij, Joke; Kroes, Hester Y.; Klaver, Caroline C. W.; van Schooneveld, Mary; Bergen, Arthur A. B.; Florijn, Ralph J.

    Purpose: To develop a high-throughput, cost-effective diagnostic strategy for the identification of known and new mutations in 90 retinal disease genes. Design: Evidence-based study. Participants: Sixty patients with a variety of retinal disorders, including Leber's congenital amaurosis, ocular

  3. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  4. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  5. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  6. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    Directory of Open Access Journals (Sweden)

    Xin Wang

    2007-01-01

    Full Text Available Two network-on-chip (NoC designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

  7. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  8. Ag-based semiconductor photocatalysts in environmental purification

    Energy Technology Data Exchange (ETDEWEB)

    Li, Jiade; Fang, Wen [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); Yu, Changlin, E-mail: yuchanglinjx@163.com [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); School of Environment Engineering and biology Engineering, Guangdong University of Petrochemical Technology, Maoming, 525000 Guangdong Province (China); Zhou, Wanqin [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); State Key Laboratory of Photocatalysis on Energy and Environment, Fuzhou University, Fuzhou, 350002 (China); Zhu, Lihua [School of Metallurgy and Chemical Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, Jiangxi Province (China); Xie, Yu, E-mail: xieyu_121@163.com [College of Environment and Chemical Engineering, Nanchang Hangkong University, Nanchang 330063, Jiangxi (China)

    2015-12-15

    Graphical abstract: Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Formation of heterojunction could largely promote the electron/hole pair separation, resulting in highly photocatalytic activity and stability. - Highlights: • Recent research progress in the fabrication and application of Ag-based semiconductor photocatalyts. • The advantages and disadvantages of Ag-based semiconductor as photocatalysts. • Strategies in design Ag-based semiconductor photocatalysts with high performance. - Abstract: Over the past decades, with the fast development of global industrial development, various organic pollutants discharged in water have become a major source of environmental pollution in waste fields. Photocatalysis, as green and environmentally friendly technology, has attracted much attention in pollutants degradation due to its efficient degradation rate. However, the practical application of traditional semiconductor photocatalysts, e.g. TiO{sub 2}, ZnO, is limited by their weak visible light adsorption due to their wide band gaps. Nowadays, the study in photocatalysts focuses on new and narrow band gap semiconductors. Among them, Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Most of Ag-based semiconductors could exhibit high initial photocatalytic activity. But they easy suffer from poor stability because of photochemical corrosion. Design heterojunction, increasing specific surface area, enriching pore structure, regulating morphology, controlling crystal facets, and producing plasmonic effects were considered as the effective strategies to improve the photocatalytic performance of Ag-based photocatalyts. Moreover, combining the superior properties of carbon materials (e.g. carbon quantum dots, carbon nano-tube, carbon nanofibers, graphene) with Ag

  9. Ag-based semiconductor photocatalysts in environmental purification

    International Nuclear Information System (INIS)

    Li, Jiade; Fang, Wen; Yu, Changlin; Zhou, Wanqin; Zhu, Lihua; Xie, Yu

    2015-01-01

    Graphical abstract: Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Formation of heterojunction could largely promote the electron/hole pair separation, resulting in highly photocatalytic activity and stability. - Highlights: • Recent research progress in the fabrication and application of Ag-based semiconductor photocatalyts. • The advantages and disadvantages of Ag-based semiconductor as photocatalysts. • Strategies in design Ag-based semiconductor photocatalysts with high performance. - Abstract: Over the past decades, with the fast development of global industrial development, various organic pollutants discharged in water have become a major source of environmental pollution in waste fields. Photocatalysis, as green and environmentally friendly technology, has attracted much attention in pollutants degradation due to its efficient degradation rate. However, the practical application of traditional semiconductor photocatalysts, e.g. TiO 2 , ZnO, is limited by their weak visible light adsorption due to their wide band gaps. Nowadays, the study in photocatalysts focuses on new and narrow band gap semiconductors. Among them, Ag-based semiconductors as promising visible light-driven photocatalysts have aroused much interesting due to their strong visible light responsibility. Most of Ag-based semiconductors could exhibit high initial photocatalytic activity. But they easy suffer from poor stability because of photochemical corrosion. Design heterojunction, increasing specific surface area, enriching pore structure, regulating morphology, controlling crystal facets, and producing plasmonic effects were considered as the effective strategies to improve the photocatalytic performance of Ag-based photocatalyts. Moreover, combining the superior properties of carbon materials (e.g. carbon quantum dots, carbon nano-tube, carbon nanofibers, graphene) with Ag

  10. Electrodes for Semiconductor Gas Sensors

    Science.gov (United States)

    Lee, Sung Pil

    2017-01-01

    The electrodes of semiconductor gas sensors are important in characterizing sensors based on their sensitivity, selectivity, reversibility, response time, and long-term stability. The types and materials of electrodes used for semiconductor gas sensors are analyzed. In addition, the effect of interfacial zones and surface states of electrode–semiconductor interfaces on their characteristics is studied. This study describes that the gas interaction mechanism of the electrode–semiconductor interfaces should take into account the interfacial zone, surface states, image force, and tunneling effect. PMID:28346349

  11. Heat toxicant contaminant mitigation in potato chips

    DEFF Research Database (Denmark)

    Mariotti, Maria; Cortes, Pablo; Fromberg, Arvid

    2015-01-01

    Heating foods immersed in oil during frying provides many attractive sensorial attributes including taste, flavor and color. However, some toxic compounds formed during frying of potatoes such as furan and acrylamide may constitute an increased cancer risk for consumers. The objective of this work...... was to mitigate the furan and acrylamide formation in potato chips without increasing their oil uptake by optimizing the blanching treatment before final frying. Potato slices were blanched in order to simultaneously leach out ascorbic acid and reducing sugars, the most important precursors of furan...... and acrylamide generation in thermally treated starchy foods. A central composite design was implemented to optimize the temperature-time blanching conditions under which furan, acrylamide and oil content in potato chips were minimized. The optimum blanching conditions were 64 degrees C and 17 min in which...

  12. Controlled Quantum Operations of a Semiconductor Three-Qubit System

    Science.gov (United States)

    Li, Hai-Ou; Cao, Gang; Yu, Guo-Dong; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

    2018-02-01

    In a specially designed semiconductor device consisting of three capacitively coupled double quantum dots, we achieve strong and tunable coupling between a target qubit and two control qubits. We demonstrate how to completely switch on and off the target qubit's coherent rotations by presetting two control qubits' states. A Toffoli gate is, therefore, possible based on these control effects. This research paves a way for realizing full quantum-logic operations in semiconductor multiqubit systems.

  13. Modification of semiconductors with proton beams. A review

    International Nuclear Information System (INIS)

    Kozlovskii, V.V.; Lomasov, V.N.; Kozlov, V.A.

    2000-01-01

    Analysis is given of the progress in the modification of semiconductors by proton beams in fields such as proton-enhanced diffusion, ion-beam mixing, and formation of porous layers. This method of modification (doping) is shown to have high potential in monitoring the properties of semiconductor materials and designing devices of micro and nano electronics as compared to the conventional doping techniques such as thermal diffusion, epitaxy, and ion implantation

  14. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  15. Near-chip compliant layer for reducing perimeter stress during assembly process

    Energy Technology Data Exchange (ETDEWEB)

    Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

    2018-03-20

    A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

  16. Layered semiconductor neutron detectors

    Science.gov (United States)

    Mao, Samuel S; Perry, Dale L

    2013-12-10

    Room temperature operating solid state hand held neutron detectors integrate one or more relatively thin layers of a high neutron interaction cross-section element or materials with semiconductor detectors. The high neutron interaction cross-section element (e.g., Gd, B or Li) or materials comprising at least one high neutron interaction cross-section element can be in the form of unstructured layers or micro- or nano-structured arrays. Such architecture provides high efficiency neutron detector devices by capturing substantially more carriers produced from high energy .alpha.-particles or .gamma.-photons generated by neutron interaction.

  17. Basic properties of semiconductors

    CERN Document Server

    Landsberg, PT

    2013-01-01

    Since Volume 1 was published in 1982, the centres of interest in the basic physics of semiconductors have shifted. Volume 1 was called Band Theory and Transport Properties in the first edition, but the subject has broadened to such an extent that Basic Properties is now a more suitable title. Seven chapters have been rewritten by the original authors. However, twelve chapters are essentially new, with the bulk of this work being devoted to important current topics which give this volume an almost encyclopaedic form. The first three chapters discuss various aspects of modern band theory and the

  18. Electrowetting on semiconductors

    Science.gov (United States)

    Palma, Cesar; Deegan, Robert

    2015-01-01

    Applying a voltage difference between a conductor and a sessile droplet sitting on a thin dielectric film separating it from the conductor will cause the drop to spread. When the conductor is a good metal, the change of the drop's contact angle due to the voltage is given by the Young-Lippmann (YL) equation. Here, we report experiments with lightly doped, single crystal silicon as the conductive electrode. We derive a modified YL equation that includes effects due to the semiconductor and contact line pinning. We show that light induces a non-reversible wetting transition, and that our model agrees well with our experimental results.

  19. Semiconductor ionizino. radiation detectors

    International Nuclear Information System (INIS)

    1982-01-01

    Spectrometric semiconductor detectors of ionizing radiation with the electron-hole junction, based on silicon and germanium are presented. The following parameters are given for the individual types of germanium detectors: energy range of detected radiation, energy resolution given as full width at half maximum (FWHM) and full width at one tenth of maximum (FWTM) for 57 Co and 60 Co, detection sensitivity, optimal voltage, and electric capacitance at optimal voltage. For silicon detectors the value of FWHM for 239 Pu is given, the sensitive area and the depth of the sensitive area. (E.S.)

  20. Band structure of semiconductors

    CERN Document Server

    Tsidilkovski, I M

    2013-01-01

    Band Structure of Semiconductors provides a review of the theoretical and experimental methods of investigating band structure and an analysis of the results of the developments in this field. The book presents the problems, methods, and applications in the study of band structure. Topics on the computational methods of band structure; band structures of important semiconducting materials; behavior of an electron in a perturbed periodic field; effective masses and g-factors for the most commonly encountered band structures; and the treatment of cyclotron resonance, Shubnikov-de Haas oscillatio