Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

Science.gov (United States)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Self-aligned periodic Ni nano dots embedded in nano-oxide layer

International Nuclear Information System (INIS)

Doi, M.; Izumi, M.; Kawasaki, S.; Miyake, K.; Sahashi, M.

2007-01-01

The Ni nano constriction dots embedded in the Ta-nano-oxide layer (NOL) was prepared by the ion beam sputtering (IBS) method. After the various conditions of the oxidations, the structural analyses of the NOL were performed by RHEED, AES and in situ STM/AFM observations. From the current image of the conductive AFM for NOL, the periodically aligned metallic dots with the size around 5-10 nm were successfully observed. The mechanism of the formation of the self-organized aligned Ni nano constriction dots is discussed from the standpoint of the grain size, the crystal orientation, the preferred oxidation of Ta at the diffused interface

Tunneling spectroscopy of a germanium quantum dot in single-hole transistors with self-aligned electrodes

International Nuclear Information System (INIS)

Chen, G-L; Kuo, David M T; Lai, W-T; Li, P-W

2007-01-01

We have fabricated a Ge quantum dot (QD) (∼10 nm) single-hole transistor with self-aligned electrodes using thermal oxidation of a SiGe-on-insulator nanowire based on FinFET technology. This fabricated device exhibits clear Coulomb blockade oscillations with large peak-to-valley ratio (PVCR) of 250-750 and negative differential conductance with PVCR of ∼12 at room temperature. This reveals that the gate-induced tunneling barrier lowering is effectively suppressed due to the self-aligned electrode structure. The magnitude of tunneling current spectra also reveals the coupling strengths between the energy levels of the Ge QD and electrodes

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Planar self-aligned ion implanted InP MISFETS for fast logic applications

International Nuclear Information System (INIS)

Cameron, D.C.; Irving, L.D.; Whitehouse, C.R.; Woodward, J.; Lee, D.

1983-01-01

The first successful use of ion implantation to fabricate truly self-aligned planar n-channel enhancement-mode indium phosphide MISFITS is reported. The transistors have been fabricated on iron-doped semi-insulating material using PECVD-deposited SiO 2 as the gate dielectric and molybdenum gate electrodes. The self-aligned source and drain contact regions were produced by Si 29 ion implantation using each gate stripe as an implant mask. The devices fabricated to date have exhibited channel mobilities up to value of 2400 cm 2 v -1 s -1 , with excellent uniformity and stability of the device characteristics also being observed. (author)

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

Science.gov (United States)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Fabrication of GaAs nanowire devices with self-aligning W-gate electrodes using selective-area MOVPE

International Nuclear Information System (INIS)

Ooike, N.; Motohisa, J.; Fukui, T.

2004-01-01

We propose and demonstrate a novel self-aligning process for fabricating the tungsten (W) gate electrode of GaAs nanowire FETs by using selective-area metalorganic vapor phase epitaxy (SA-MOVPE) where SiO 2 /W composite films are used to mask the substrates. First, to study the growth process and its dependence on mask materials, GaAs wire structures were grown on masked substrates partially covered with a single W layer or SiO 2 /W composite films. We found that lateral growth over the masked regions could be suppressed when a wire along the [110] direction and a SiO 2 /W composite mask were used. Using this composite mask, we fabricated GaAs narrow channel FETs using W as a Schottky gate electrode, and we were able to observe FET characteristics at room temperature

Silicon on insulator self-aligned transistors

Science.gov (United States)

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

Science.gov (United States)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Electronic States of High-k Oxides in Gate Stack Structures

Science.gov (United States)

Zhu, Chiyu

In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO 2-La2O3/ZnO/SiO2/Si, and c) HfO 2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO 2/SiO2 are determined to be 3.4 +/- 0.1, 1.5 +/- 0.1, and 0.7 +/- 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

Science.gov (United States)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Process development of ITO source/drain electrode for the top-gate indium-gallium-zinc oxide transparent thin-film transistor

International Nuclear Information System (INIS)

Cheong, Woo-Seok; Yoon, Young-sun; Shin, Jae-Heon; Hwang, Chi-Sun; Chu, Hye Yong

2009-01-01

Indium-tin oxide (ITO) has been widely used as electrodes for LCDs and OLEDs. The applications are expanding to the transparent thin-film transistors (TTFT S ) for the versatile circuits or transparent displays. This paper is related with optimization of ITO source and drain electrode for TTFTs on glass substrates. For example, un-etched ITO remnants, which frequently found in the wet etching process, often originate from unsuitable ITO formation processes. In order to improve them, an ion beam deposition method is introduced, which uses for forming a seed layer before the main ITO deposition. We confirm that ITO films with seed layers are effective to obtain clean and smooth glass surfaces without un-etched ITO remnants, resulting in a good long-run electrical stability of the top-gate indium-gallium-zinc oxide-TTFT.

Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

Science.gov (United States)

Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

2016-08-23

We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

Semiconductor applications of plasma immersion ion implantation ...

Indian Academy of Sciences (India)

Unknown

cm2 top layer of silicon becomes fully nitrided and no oxidation takes place. These altered oxidation rates of silicon can be used to achieve multi thickness gate oxides in a self aligned manner, which are required for integration of different type of ...

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

Science.gov (United States)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Low-temperature formation of source–drain contacts in self-aligned amorphous oxide thin-film transistors

NARCIS (Netherlands)

Nag, M.; Muller, R.N.; Steudel, S.; Smout, S.; Bhoolokam, A.; Myny, K.; Schols, S.; Genoe, J.; Cobb, B.; Kumar, Abhishek; Gelinck, G.H.; Fukui, Y.; Groeseneken, G.; Heremans, P.

2015-01-01

We demonstrated self-aligned amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistors (TFTs) where the source–drain (S/D) regions were made conductive via chemical reduction of the a-IGZO via metallic calcium (Ca). Due to the higher chemical reactivity of Ca, the process can be operated at

Modeling Electrolytically Top-Gated Graphene

Directory of Open Access Journals (Sweden)

Mišković ZL

2010-01-01

Full Text Available Abstract We investigate doping of a single-layer graphene in the presence of electrolytic top gating. The interfacial phenomenon is modeled using a modified Poisson–Boltzmann equation for an aqueous solution of simple salt. We demonstrate both the sensitivity of graphene’s doping levels to the salt concentration and the importance of quantum capacitance that arises due to the smallness of the Debye screening length in the electrolyte.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

Science.gov (United States)

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Self-gated fat-suppressed cardiac cine MRI.

Science.gov (United States)

Ingle, R Reeve; Santos, Juan M; Overall, William R; McConnell, Michael V; Hu, Bob S; Nishimura, Dwight G

2015-05-01

To develop a self-gated alternating repetition time balanced steady-state free precession (ATR-SSFP) pulse sequence for fat-suppressed cardiac cine imaging. Cardiac gating is computed retrospectively using acquired magnetic resonance self-gating data, enabling cine imaging without the need for electrocardiogram (ECG) gating. Modification of the slice-select rephasing gradients of an ATR-SSFP sequence enables the acquisition of a one-dimensional self-gating readout during the unused short repetition time (TR). Self-gating readouts are acquired during every TR of segmented, breath-held cardiac scans. A template-matching algorithm is designed to compute cardiac trigger points from the self-gating signals, and these trigger points are used for retrospective cine reconstruction. The proposed approach is compared with ECG-gated ATR-SSFP and balanced steady-state free precession in 10 volunteers and five patients. The difference of ECG and self-gating trigger times has a variability of 13 ± 11 ms (mean ± SD). Qualitative reviewer scoring and ranking indicate no statistically significant differences (P > 0.05) between self-gated and ECG-gated ATR-SSFP images. Quantitative blood-myocardial border sharpness is not significantly different among self-gated ATR-SSFP ( 0.61±0.15 mm -1), ECG-gated ATR-SSFP ( 0.61±0.15 mm -1), or conventional ECG-gated balanced steady-state free precession cine MRI ( 0.59±0.15 mm -1). The proposed self-gated ATR-SSFP sequence enables fat-suppressed cardiac cine imaging at 1.5 T without the need for ECG gating and without decreasing the imaging efficiency of ATR-SSFP. © 2014 Wiley Periodicals, Inc.

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

Science.gov (United States)

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press

Method of making a self-aligned schottky metal semi-conductor field effect transistor with buried source and drain

International Nuclear Information System (INIS)

Bol, I.

1984-01-01

A semi-conductor structure and particularly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively. Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed

Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

Energy Technology Data Exchange (ETDEWEB)

Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 130-701 (Korea, Republic of)

2015-12-07

We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Directory of Open Access Journals (Sweden)

Minkyu Chun

2015-05-01

Full Text Available We investigated the effects of top gate voltage (VTG and temperature (in the range of 25 to 70 oC on dual-gate (DG back-channel-etched (BCE amorphous-indium-gallium-zinc-oxide (a-IGZO thin film transistors (TFTs characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

Self-Aligned Metal Electrodes in Fully Roll-to-Roll Processed Organic Transistors

Directory of Open Access Journals (Sweden)

Marja Vilkman

2016-01-01

Full Text Available We demonstrate the production of organic bottom gate transistors with self-aligned electrodes, using only continuous roll-to-roll (R2R techniques. The self-alignment allows accurate <5 µm layer-to-layer registration, which is usually a challenge in high-speed R2R environments as the standard registration methods are limited to the millimeter range—or, at best, to tens of µm if online cameras and automatic web control are utilized. The improved registration enables minimizing the overlap between the source/drain electrodes and the gate electrode, which is essential for minimizing the parasitic capacitance. The complete process is a combination of several techniques, including evaporation, reverse gravure, flexography, lift-off, UV exposure and development methods—all transferred to a continuous R2R pilot line. Altogether, approximately 80 meters of devices consisting of thousands of transistors were manufactured in a roll-to-roll fashion. Finally, a cost analysis is presented in order to ascertain the main costs and to predict whether the process would be feasible for the industrial production of organic transistors.

Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

International Nuclear Information System (INIS)

Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

2013-01-01

Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al 2 O 3 ) on a graphene channel through nitrogen plasma treatment. The deposited Al 2 O 3 thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al 2 O 3 as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics

Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

International Nuclear Information System (INIS)

Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

2001-01-01

We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 130-701 (Korea, Republic of)

2015-05-15

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

Gate-stack engineering for self-organized Ge-dot/SiO2/SiGe-shell MOS capacitors

Directory of Open Access Journals (Sweden)

Wei-Ting eLai

2016-02-01

Full Text Available We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm, the SiO2 thickness (3−4 nm, and as well the SiGe-shell thickness (2−15 nm has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5 in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge MOS nanoelectronic and nanophotonic applications.

Adiabatic Field-Free Alignment of Asymmetric Top Molecules with an Optical Centrifuge.

Science.gov (United States)

Korobenko, A; Milner, V

2016-05-06

We use an optical centrifuge to align asymmetric top SO_{2} molecules by adiabatically spinning their most polarizable O-O axis. The effective centrifugal potential in the rotating frame confines the sulfur atoms to the plane of the laser-induced rotation, leading to the planar molecular alignment that persists after the molecules are released from the centrifuge. The periodic appearance of the full three-dimensional alignment, typically observed only with linear and symmetric top molecules, is also detected. Together with strong in-plane centrifugal forces, which bend the molecules by up to 10 deg, permanent field-free alignment offers new ways of controlling molecules with laser light.

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Directory of Open Access Journals (Sweden)

Valeri V. Afanas'ev

2014-01-01

Full Text Available Evolution of the electron energy band alignment at interfaces between different semiconductors and wide-gap oxide insulators is examined using the internal photoemission spectroscopy, which is based on observations of optically-induced electron (or hole transitions across the semiconductor/insulator barrier. Interfaces of various semiconductors ranging from the conventional silicon to the high-mobility Ge-based (Ge, Si1-xGex, Ge1-xSnx and AIIIBV group (GaAs, InxGa1-xAs, InAs, GaP, InP, GaSb, InSb materials were studied revealing several general trends in the evolution of band offsets. It is found that in the oxides of metals with cation radii larger than ≈0.7 Å, the oxide valence band top remains nearly at the same energy (±0.2 eV irrespective of the cation sort. Using this result, it becomes possible to predict the interface band alignment between oxides and semiconductors as well as between dissimilar insulating oxides on the basis of the oxide bandgap width which are also affected by crystallization. By contrast, oxides of light elements, for example, Be, Mg, Al, Si, and Sc exhibit significant shifts of the valence band top. General trends in band lineup variations caused by a change in the composition of semiconductor photoemission material are also revealed.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

Energy Technology Data Exchange (ETDEWEB)

Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

2016-03-31

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

International Nuclear Information System (INIS)

Liao, Po-Yung; Chang, Ting-Chang; Hsieh, Tien-Yu; Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo; Chou, Cheng-Hsu; Chang, Jung-Fang

2016-01-01

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V T ) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V T shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V T shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V T shift increases with decreasing frequency of the top gate pulses.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Science.gov (United States)

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

The gate oxide integrity of CVD tungsten polycide

International Nuclear Information System (INIS)

Wu, N.W.; Su, W.D.; Chang, S.W.; Tseng, M.F.

1988-01-01

CVD tungsten polycide has been demonstrated as a good gate material in recent very large scale integration (VLSI) technology. CVD tungsten silicide offers advantages of low resistivity, high temperature stability and good step coverage. On the other hand, the polysilicon underlayer preserves most characteristics of the polysilicon gate and acts as a stress buffer layer to absorb part of the thermal stress origin from the large thermal expansion coefficient of tungsten silicide. Nevertheless, the gate oxide of CVD tungsten polycide is less stable or reliable than that of polysilicon gate. In this paper, the gate oxide integrity of CVD tungsten polycide with various thickness combinations and different thermal processes have been analyzed by several electrical measurements including breakdown yield, breakdown fluence, room temperature TDDB, I-V characteristics, electron traps and interface state density

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

Energy Technology Data Exchange (ETDEWEB)

Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-06-20

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Alignment of symmetric top molecules by short laser pulses

DEFF Research Database (Denmark)

Hamilton, Edward; Seideman, Tamar; Ejdrup, Tine

2005-01-01

-resolved photofragment imaging. Using methyliodide and tert-butyliodide as examples, we calculate and measure the alignment dynamics, focusing on the temporal structure and intensity of the revival patterns, including their dependence on the pulse duration, and their behavior at long times, where centrifugal distortion......Nonadiabatic alignment of symmetric top molecules induced by a linearly polarized, moderately intense picosecond laser pulse is studied theoretically and experimentally. Our studies are based on the combination of a nonperturbative solution of the Schrodinger equation with femtosecond time...

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

International Nuclear Information System (INIS)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

2014-01-01

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

International Nuclear Information System (INIS)

Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

2008-01-01

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

International Nuclear Information System (INIS)

Kobayashi, H.; Kim, W. B.; Matsumoto, T.

2011-01-01

We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

Ultrathin reduced graphene oxide films as transparent top-contacts for light switchable solid-state molecular junctions

DEFF Research Database (Denmark)

Li, Tao; Jevric, Martyn; Hauptmann, Jonas Rahlf

2013-01-01

A new type of solid-state molecular junction is introduced, which employs reduced graphene oxide as a transparent top contact that permits a self-assembled molecular monolayer to be photoswitched in situ, while simultaneously enabling charge-transport measurements across the molecules. The electr......A new type of solid-state molecular junction is introduced, which employs reduced graphene oxide as a transparent top contact that permits a self-assembled molecular monolayer to be photoswitched in situ, while simultaneously enabling charge-transport measurements across the molecules...

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Science.gov (United States)

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Instantons in Self-Organizing Logic Gates

Science.gov (United States)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

Alignment of the UMLS semantic network with BioTop: methodology and assessment.

Science.gov (United States)

Schulz, Stefan; Beisswanger, Elena; van den Hoek, László; Bodenreider, Olivier; van Mulligen, Erik M

2009-06-15

For many years, the Unified Medical Language System (UMLS) semantic network (SN) has been used as an upper-level semantic framework for the categorization of terms from terminological resources in biomedicine. BioTop has recently been developed as an upper-level ontology for the biomedical domain. In contrast to the SN, it is founded upon strict ontological principles, using OWL DL as a formal representation language, which has become standard in the semantic Web. In order to make logic-based reasoning available for the resources annotated or categorized with the SN, a mapping ontology was developed aligning the SN with BioTop. The theoretical foundations and the practical realization of the alignment are being described, with a focus on the design decisions taken, the problems encountered and the adaptations of BioTop that became necessary. For evaluation purposes, UMLS concept pairs obtained from MEDLINE abstracts by a named entity recognition system were tested for possible semantic relationships. Furthermore, all semantic-type combinations that occur in the UMLS Metathesaurus were checked for satisfiability. The effort-intensive alignment process required major design changes and enhancements of BioTop and brought up several design errors that could be fixed. A comparison between a human curator and the ontology yielded only a low agreement. Ontology reasoning was also used to successfully identify 133 inconsistent semantic-type combinations. BioTop, the OWL DL representation of the UMLS SN, and the mapping ontology are available at http://www.purl.org/biotop/.

Resonant Tunneling in Gated Vertical One- dimensional Structures

Science.gov (United States)

Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Webb, K. J.

1997-03-01

Vertical sub-micron transistors incorporating resonant tunneling multiple quantum well heterostructures are interesting in applications for both multi-valued logic devices and the study of quantization effects in vertical quasi- one-, zero- dimensional structures. Earlier we have demonstrated room temperature pinch-off of the resonant peak in sub-micron vertical resonant tunneling transistors structures using a self-aligned sidewall gating technique ( V.R. Kolagunta et. al., Applied Physics Lett., 69), 374(1996). In this paper we present the study of gating effects in vertical multiple quantum well resonant tunneling transistors. Multiple well quasi-1-D sidewall gated transistors with mesa dimensions of L_x=0.5-0.9μm and L_y=10-40μm were fabricated. The quantum heterostructure in these devices consists of two non-symmetric (180 ÅÅi-GaAs wells separated from each other and from the top and bottom n^+ GaAs/contacts region using Al_0.3Ga_0.7As tunneling barriers. Room temperature pinch-off of the multiple resonant peaks similar to that reported in the case of single well devices is observed in these devices^1. Current-voltage characteristics at liquid nitrogen temperatures show splitting of the resonant peaks into sub-bands with increasing negative gate bias indicative of quasi- 1-D confinement. Room-temperature and low-temperature current-voltage measurements shall be presented and discussed.

Cationic Reduced Graphene Oxide as Self-Aligned Nanofiller in the Epoxy Nanocomposite Coating with Excellent Anticorrosive Performance and Its High Antibacterial Activity.

Science.gov (United States)

Luo, Xiaohu; Zhong, Jiawen; Zhou, Qiulan; Du, Shuo; Yuan, Song; Liu, Yali

2018-05-17

The design and preparation of an excellent corrosion protection coating is still a grand challenge and is essential for large-scale practical application. Herein, a novel cationic reduced graphene oxide (denoted as RGO-ID + )-based epoxy coating was fabricated for corrosion protection. RGO-ID + was synthesized by in situ synthesis and salification reaction, which is stable dispersion in water and epoxy latex, and the self-aligned RGO-ID + -reinforced cathodic electrophoretic epoxy nanocomposite coating (denoted as RGO-ID + coating) at the surface of metal was prepared by electrodeposition. The self-alignment of RGO-ID + in the coatings is mainly attributed to the electric field force. The significantly enhanced anticorrosion performance of RGO-ID + coating is proved by a series of electrochemical measurements in different concentrated NaCl solutions and salt spray tests. This superior anticorrosion property benefits from the self-aligned RGO-ID + nanosheets and the quaternary-N groups present in the RGO-ID + nanocomposite coating. Interestingly, the RGO-ID + also exhibits a high antibacterial activity toward Escherichia coli with 83.4 ± 1.3% antibacterial efficiency, which is attributed to the synergetic effects of RGO-ID + and the electrostatic attraction and hydrogen bonding between RGO-ID + and E. coli. This work offers new opportunities for the successful development of effective corrosion protection and self-antibacterial coatings.

Non-classical polycrystalline silicon thin-film transistor with embedded block-oxide for suppressing the short channel effect

International Nuclear Information System (INIS)

Lin, Jyi-Tsong; Huang, Kuo-Dong; Hu, Shu-Fen

2008-01-01

In this paper, a polycrystalline silicon (polysilicon) thin-film transistor with a block oxide enclosing body, BTFT, is fabricated and investigated. By utilizing the block-oxide structure of thin-film transistors, the BTFT is shown to suppress the short channel effect. This proposed structure is formed by burying self-aligned oxide spacers along the sidewalls of the source and drain junctions, which reduces the P–N junction area, thereby reducing the junction capacitance and leakage current. Measurements demonstrate that the BTFT eliminates the punch-through effect even down to gate lengths of 1.5 µm, whereas the conventional TFT suffers serious short channel effects at this gate length

Simulation of dual-gate SOI MOSFET with different dielectric layers

Science.gov (United States)

Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

2016-04-01

The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

Looking behind the scenes: Raman spectroscopy of top-gated epitaxial graphene through the substrate

International Nuclear Information System (INIS)

Fromm, F; Wehrfritz, P; Seyller, Th; Hundhausen, M

2013-01-01

Raman spectroscopy is frequently used to study the properties of epitaxial graphene grown on silicon carbide (SiC). In this work, we present a confocal micro-Raman study of epitaxial graphene on SiC(0001) in top-down geometry, i.e. in a geometry where both the primary laser light beam as well as the back-scattered light is guided through the SiC substrate. Compared to the conventional top-up configuration, in which confocal micro-Raman spectra are measured from the air side, we observe a significant intensity enhancement in top-down configuration, indicating that most of the Raman-scattered light is emitted into the SiC substrate. The intensity enhancement is explained in terms of dipole radiation at a dielectric surface. The new technique opens the possibility to probe graphene layers in devices where the graphene layer is covered by non-transparent materials. We demonstrate this by measuring gate-modulated Raman spectra of a top-gated epitaxial graphene field effect device. Moreover, we show that these measurements enable us to disentangle the effects of strain and charge on the positions of the prominent Raman lines in epitaxial graphene on SiC. (paper)

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

Science.gov (United States)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

Science.gov (United States)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Towards Self-Clocked Gated OCDMA Receiver

Science.gov (United States)

Idris, S.; Osadola, T.; Glesk, I.

2013-02-01

A novel incoherent OCDMA receiver with incorporated all-optical clock recovery for self-synchronization of a time gate for the multi access interferences (MAI) suppression and minimizing the effect of data time jitter in incoherent OCDMA system was successfully developed and demonstrated. The solution was implemented and tested in a multiuser environment in an out of the laboratory OCDMA testbed with two-dimensional wavelength-hopping time-spreading coding scheme and OC-48 (2.5 Gbp/s) data rate. The self-clocked all-optical time gate uses SOA-based fibre ring laser optical clock, recovered all-optically from the received OCDMA traffic to control its switching window for cleaning the autocorrelation peak from the surrounding MAI. A wider eye opening was achieved when the all-optically recovered clock from received data was used for synchronization if compared to a static approach with the RF clock being generated by a RF synthesizer. Clean eye diagram was also achieved when recovered clock is used to drive time gating.

Fabrication of amorphous IGZO thin film transistor using self-aligned imprint lithography with a sacrificial layer

Science.gov (United States)

Kim, Sung Jin; Kim, Hyung Tae; Choi, Jong Hoon; Chung, Ho Kyoon; Cho, Sung Min

2018-04-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistor (TFT) was fabricated by a self-aligned imprint lithography (SAIL) method with a sacrificial photoresist layer. The SAIL is a top-down method to fabricate a TFT using a three-dimensional multilayer etch mask having all pattern information for the TFT. The sacrificial layer was applied in the SAIL process for the purpose of removing the resin residues that were inevitably left when the etch mask was thinned by plasma etching. This work demonstrated that the a-IGZO TFT could be fabricated by the SAIL process with the sacrificial layer. Specifically, the simple fabrication process utilized in this study can be utilized for the TFT with a plasma-sensitive semiconductor such as the a-IGZO and further extended for the roll-to-roll TFT fabrication.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Comparative studies of MOS-gate/oxide-passivated AlGaAs/InGaAs pHEMTs by using ozone water oxidation technique

International Nuclear Information System (INIS)

Lee, Ching-Sung; Hung, Chun-Tse; Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lai, Ying-Nan

2012-01-01

Al 0.22 Ga 0.78 As/In 0.24 Ga 0.76 As pseudomorphic high-electron-mobility transistors (pHEMTs) with metal-oxide-semiconductor (MOS)-gate structure or oxide passivation by using ozone water oxidation treatment have been comprehensively investigated. Annihilated surface states, enhanced gate insulating property and improved device gain have been achieved by the devised MOS-gate structure and oxide passivation. The present MOS-gated or oxide-passivated pHEMTs have demonstrated superior device performances, including superior breakdown, device gain, noise figure, high-frequency characteristics and power performance. Temperature-dependent device characteristics of the present designs at 300–450 K are also studied. (paper)

Orthodontics Align Crooked Teeth and Boost Self-Esteem

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Self-gated golden-angle spiral 4D flow MRI.

Science.gov (United States)

Bastkowski, Rene; Weiss, Kilian; Maintz, David; Giese, Daniel

2018-01-17

The acquisition of 4D flow magnetic resonance imaging (MRI) in cardiovascular applications has recently made large progress toward clinical feasibility. The need for simultaneous compensation of cardiac and breathing motion still poses a challenge for widespread clinical use. Especially, breathing motion, addressed by gating approaches, can lead to unpredictable and long scan times. The current work proposes a time-efficient self-gated 4D flow sequence that exploits up to 100% of the acquired data and operates at a predictable scan time. A self-gated golden-angle spiral 4D flow sequence was implemented and tested in 10 volunteers. Data were retrospectively binned into respiratory and cardiac states and reconstructed using a conjugate-gradient sensitivity encoding reconstruction. Net flow curves, stroke volumes, and peak flow in the aorta were evaluated and compared to a conventional Cartesian 4D flow sequence. Additionally, flow quantities reconstructed from 50% to 100% of the self-gated 4D flow data were compared. Self-gating signals for respiratory and cardiac motion were extracted for all volunteers. Flow quantities were in agreement with the standard Cartesian scan. Mean differences in stroke volumes and peak flow of 7.6 ± 11.5 and 4.0 ± 79.9 mL/s were obtained, respectively. By retrospectively increasing breathing navigator efficiency while decreasing acquisition times (15:06-07:33 minutes), 50% of the acquired data were sufficient to measure stroke volumes with errors under 9.6 mL. The feasibility to acquire respiratory and cardiac self-gated 4D flow data at a predictable scan time was demonstrated. Magn Reson Med, 2018. © 2018 International Society for Magnetic Resonance in Medicine. © 2018 International Society for Magnetic Resonance in Medicine.

Capillary Self-Alignment of Microchips on Soft Substrates

Directory of Open Access Journals (Sweden)

Bo Chang

2016-03-01

Full Text Available Soft micro devices and stretchable electronics have attracted great interest for their potential applications in sensory skins and wearable bio-integrated devices. One of the most important steps in building printed circuits is the alignment of assembled micro objects. Previously, the capillary self-alignment of microchips driven by surface tension effects has been shown to be able to achieve high-throughput and high-precision in the integration of micro parts on rigid hydrophilic/superhydrophobic patterned surfaces. In this paper, the self-alignment of microchips on a patterned soft and stretchable substrate, which consists of hydrophilic pads surrounded by a superhydrophobic polydimethylsiloxane (PDMS background, is demonstrated for the first time. A simple process has been developed for making superhydrophobic soft surface by replicating nanostructures of black silicon onto a PDMS surface. Different kinds of PDMS have been investigated, and the parameters for fabricating superhydrophobic PDMS have been optimized. A self-alignment strategy has been proposed that can result in reliable self-alignment on a soft PDMS substrate. Our results show that capillary self-alignment has great potential for building soft printed circuits.

Design and fabrication of carbon nanotube field-emission cathode with coaxial gate and ballast resistor.

Science.gov (United States)

Sun, Yonghai; Yeow, John T W; Jaffray, David A

2013-10-25

A low density vertically aligned carbon nanotube-based field-emission cathode with a ballast resistor and coaxial gate is designed and fabricated. The ballast resistor can overcome the non-uniformity of the local field-enhancement factor at the emitter apex. The self-aligned fabrication process of the coaxial gate can avoid the effects of emitter tip misalignment and height non-uniformity. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A neural mechanism of dynamic gating of task-relevant information by top-down influence in primary visual cortex.

Science.gov (United States)

Kamiyama, Akikazu; Fujita, Kazuhisa; Kashimori, Yoshiki

2016-12-01

Visual recognition involves bidirectional information flow, which consists of bottom-up information coding from retina and top-down information coding from higher visual areas. Recent studies have demonstrated the involvement of early visual areas such as primary visual area (V1) in recognition and memory formation. V1 neurons are not passive transformers of sensory inputs but work as adaptive processor, changing their function according to behavioral context. Top-down signals affect tuning property of V1 neurons and contribute to the gating of sensory information relevant to behavior. However, little is known about the neuronal mechanism underlying the gating of task-relevant information in V1. To address this issue, we focus on task-dependent tuning modulations of V1 neurons in two tasks of perceptual learning. We develop a model of the V1, which receives feedforward input from lateral geniculate nucleus and top-down input from a higher visual area. We show here that the change in a balance between excitation and inhibition in V1 connectivity is necessary for gating task-relevant information in V1. The balance change well accounts for the modulations of tuning characteristic and temporal properties of V1 neuronal responses. We also show that the balance change of V1 connectivity is shaped by top-down signals with temporal correlations reflecting the perceptual strategies of the two tasks. We propose a learning mechanism by which synaptic balance is modulated. To conclude, top-down signal changes the synaptic balance between excitation and inhibition in V1 connectivity, enabling early visual area such as V1 to gate context-dependent information under multiple task performances. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Energy Technology Data Exchange (ETDEWEB)

Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

2015-03-09

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

International Nuclear Information System (INIS)

Takano, H.; Hosogi, K.; Kato, T.

1995-01-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

Energy Technology Data Exchange (ETDEWEB)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.; Singh, G.; Malnou, M.; Lesueur, J.; Bergeal, N. [Laboratoire de Physique et d' Etude des Matériaux-CNRS-ESPCI ParisTech-UPMC, PSL Research University, 10 Rue Vauquelin - 75005 Paris (France); Lesne, E.; Reyren, N.; Barthélémy, A.; Bibes, M.; Villegas, J. E. [Unité Mixte de Physique CNRS-Thales, 1 Av. A. Fresnel, 91767 Palaiseau (France); Ulysse, C. [Laboratoire de Photonique et de Nanostructures LPN-CNRS, Route de Nozay, 91460 Marcoussis and Universit Paris Sud, 91405 Orsay (France); Pannetier-Lecoeur, M. [DSM/IRAMIS/SPEC - CNRS UMR 3680, CEA Saclay, F-91191 Gif-sur-Yvette Cedex (France)

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for a strong depletion of the 2-DEG.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

International Nuclear Information System (INIS)

Hu Shigang; Hao Yue; Cao Yanrong; Ma Xiaohua; Wu Xiaofeng; Chen Chi; Zhou Qingjun

2009-01-01

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on V d than on V g . The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

Accuracy and effectiveness of self-gating signals in free-breathing three-dimensional cardiac cine magnetic resonance imaging

International Nuclear Information System (INIS)

Li Shuo; Gao Song; Wang Lei; Zhu Yan-Chun; Yang Jie; Xie Yao-Qin; Fu Nan; Wang Yi

2016-01-01

Conventional multiple breath-hold two-dimensional (2D) balanced steady-state free precession (SSFP) presents many difficulties in cardiac cine magnetic resonance imaging (MRI). Recently, a self-gated free-breathing three-dimensional (3D) SSFP technique has been proposed as an alternative in many studies. However, the accuracy and effectiveness of self-gating signals have been barely studied before. Since self-gating signals are crucially important in image reconstruction, a systematic study of self-gating signals and comparison with external monitored signals are needed.Previously developed self-gated free-breathing 3D SSFP techniques are used on twenty-eight healthy volunteers. Both electrocardiographic (ECG) and respiratory bellow signals are also acquired during the scan as external signals. Self-gating signal and external signal are compared by trigger and gating window. Gating window is proposed to evaluate the accuracy and effectiveness of respiratory self-gating signal. Relative deviation of the trigger and root-mean-square-deviation of the cycle duration are calculated. A two-tailed paired t-test is used to identify the difference between self-gating and external signals. A Wilcoxon signed rank test is used to identify the difference between peak and valley self-gating triggers.The results demonstrate an excellent correlation ( P = 0, R > 0.99) between self-gating and external triggers. Wilcoxon signed rank test shows that there is no significant difference between peak and valley self-gating triggers for both cardiac ( H = 0, P > 0.10) and respiratory ( H = 0, P > 0.44) motions. The difference between self-gating and externally monitored signals is not significant (two-tailed paired-sample t-test: H = 0, P > 0.90).The self-gating signals could demonstrate cardiac and respiratory motion accurately and effectively as ECG and respiratory bellow. The difference between the two methods is not significant and can be explained. Furthermore, few ECG trigger errors

Submolecular Gates Self-Assemble for Hot-Electron Transfer in Proteins.

Science.gov (United States)

Filip-Granit, Neta; Goldberg, Eran; Samish, Ilan; Ashur, Idan; van der Boom, Milko E; Cohen, Hagai; Scherz, Avigdor

2017-07-27

Redox reactions play key roles in fundamental biological processes. The related spatial organization of donors and acceptors is assumed to undergo evolutionary optimization facilitating charge mobilization within the relevant biological context. Experimental information from submolecular functional sites is needed to understand the organization strategies and driving forces involved in the self-development of structure-function relationships. Here we exploit chemically resolved electrical measurements (CREM) to probe the atom-specific electrostatic potentials (ESPs) in artificial arrays of bacteriochlorophyll (BChl) derivatives that provide model systems for photoexcited (hot) electron donation and withdrawal. On the basis of computations we show that native BChl's in the photosynthetic reaction center (RC) self-assemble at their ground-state as aligned gates for functional charge transfer. The combined computational and experimental results further reveal how site-specific polarizability perpendicular to the molecular plane enhances the hot-electron transport. Maximal transport efficiency is predicted for a specific, ∼5 Å, distance above the center of the metalized BChl, which is in remarkably close agreement with the distance and mutual orientation of corresponding native cofactors. These findings provide new metrics and guidelines for analysis of biological redox centers and for designing charge mobilizing machines such as artificial photosynthesis.

Self-gating MR imaging of the fetal heart: comparison with real cardiac triggering

International Nuclear Information System (INIS)

Yamamura, Jin; Frisch, Michael; Ecker, Hannes; Adam, Gerhard; Wedegaertner, Ulrike; Graessner, Joachim; Hecher, Kurt

2011-01-01

To investigate the self-gating technique for MR imaging of the fetal heart in a sheep model. MR images of 6 fetal sheep heart were obtained at 1.5T. For self-gating MRI of the fetal heart a cine SSFP in short axis, two and four chamber view was used. Self-gated images were compared with real cardiac triggered MR images (pulse-wave triggering). MRI of the fetal heart was performed using both techniques simultaneously. Image quality was assessed and the left ventricular volume and function were measured and compared. Compared with pulse-wave triggering, the self-gating technique produced slightly inferior images with artifacts. Especially the atrial septum could not be so clearly depicted. The contraction of the fetal heart was shown in cine sequences in both techniques. The average blood volumes could be measured with both techniques with no significant difference: at end-systole 3.1 ml (SD± 0.2), at end-diastole 4.9 ml (±0.2), with ejection fractions at 38.6%, respectively 39%. Both self-gating and pulse-wave triggered cardiac MRI of the fetal heart allowed the evaluation of anatomical structures and functional information. Images obtained by self-gating technique were slightly inferior than the pulse-wave triggered MRI. (orig.)

Analyzing nitrogen concentration using carrier illumination (CI) technology for DPN ultra-thin gate oxide

International Nuclear Information System (INIS)

Li, W.S.; Wu, Bill; Fan, Aki; Kuo, C.W.; Segovia, M.; Kek, H.A.

2005-01-01

Nitrogen concentration in the gate oxide plays a key role for 90 nm and below ULSI technology. Techniques like secondary ionization mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS) are commonly used for understanding N concentration. This paper describes the application of the carrier illuminationTM (CI) technique to measure the nitrogen concentration in ultra-thin gate oxides. A set of ultra-thin gate oxide wafers with different DPN (decoupled plasma nitridation) treatment conditions were measured using the CI technique. The CI signal has excellent correlation with the N concentration as measured by XPS

Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond

Science.gov (United States)

Dunn, Derren; Sporre, John R.; Deshpande, Vaibhav; Oulmane, Mohamed; Gull, Ronald; Ventzek, Peter; Ranjan, Alok

2017-03-01

Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.1 When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.2

DNAzyme-Based Logic Gate-Mediated DNA Self-Assembly.

Science.gov (United States)

Zhang, Cheng; Yang, Jing; Jiang, Shuoxing; Liu, Yan; Yan, Hao

2016-01-13

Controlling DNA self-assembly processes using rationally designed logic gates is a major goal of DNA-based nanotechnology and programming. Such controls could facilitate the hierarchical engineering of complex nanopatterns responding to various molecular triggers or inputs. Here, we demonstrate the use of a series of DNAzyme-based logic gates to control DNA tile self-assembly onto a prescribed DNA origami frame. Logic systems such as "YES," "OR," "AND," and "logic switch" are implemented based on DNAzyme-mediated tile recognition with the DNA origami frame. DNAzyme is designed to play two roles: (1) as an intermediate messenger to motivate downstream reactions and (2) as a final trigger to report fluorescent signals, enabling information relay between the DNA origami-framed tile assembly and fluorescent signaling. The results of this study demonstrate the plausibility of DNAzyme-mediated hierarchical self-assembly and provide new tools for generating dynamic and responsive self-assembly systems.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Directory of Open Access Journals (Sweden)

Paul C. McIntyre

2012-07-01

Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Functional imaging of murine hearts using accelerated self-gated UTE cine MRI

NARCIS (Netherlands)

Motaal, Abdallah G.; Noorman, Nils; de Graaf, Wolter L.; Hoerr, Verena; Florack, Luc M. J.; Nicolay, Klaas; Strijkers, Gustav J.

2015-01-01

We introduce a fast protocol for ultra-short echo time (UTE) Cine magnetic resonance imaging (MRI) of the beating murine heart. The sequence involves a self-gated UTE with golden-angle radial acquisition and compressed sensing reconstruction. The self-gated acquisition is performed asynchronously

Coronary endothelial function assessment using self-gated cardiac cine MRI and k-t sparse SENSE.

Science.gov (United States)

Yerly, Jérôme; Ginami, Giulia; Nordio, Giovanna; Coristine, Andrew J; Coppo, Simone; Monney, Pierre; Stuber, Matthias

2016-11-01

Electrocardiogram (ECG)-gated cine MRI, paired with isometric handgrip exercise, can be used to accurately, reproducibly, and noninvasively measure coronary endothelial function (CEF). Obtaining a reliable ECG signal at higher field strengths, however, can be challenging due to rapid gradient switching and an increased heart rate under stress. To address these limitations, we present a self-gated cardiac cine MRI framework for CEF measurements that operates without ECG signal. Cross-sectional slices of the right coronary artery (RCA) were acquired using a two-dimensional golden angle radial trajectory. This sampling approach, combined with the k-t sparse SENSE algorithm, allows for the reconstruction of both real-time images for self-gating signal calculations and retrospectively reordered self-gated cine images. CEF measurements were quantitatively compared using both the self-gated and the standard ECG-gated approach. Self-gated cine images with high-quality, temporal, and spatial resolution were reconstructed for 18 healthy volunteers. CEF as measured in self-gated images was in good agreement (R 2  = 0.60) with that measured by its standard ECG-gated counterpart. High spatial and temporal resolution cross-sectional cine images of the RCA can be obtained without ECG signal. The coronary vasomotor response to handgrip exercise compares favorably with that obtained with the standard ECG-gated method. Magn Reson Med 76:1443-1454, 2015. © 2015 International Society for Magnetic Resonance in Medicine. © 2015 International Society for Magnetic Resonance in Medicine.

Wave drag reduction due to a self-aligning aerodisk

Science.gov (United States)

Schnepf, Ch.; Wysocki, O.; Schülein, E.

2015-06-01

The effect of a self-aligning aerodisk on the wave drag of a blunt slender body in a pitching maneuver has been numerically investigated. The self-alignment was realized by a coupling of the flow solver and a flight mechanics tool. The slender body was pitched with high repetition rate between α = 0° and 20° at M = 1.41. Even at high α, the concept could align the aerodisk to the oncoming flow. In comparison to the reference body without a self-aligning aerodisk, a distinct drag reduction is achieved. A comparison with existing experimental data shows a qualitatively good agreement considering the shock and separation structure and the kinematics of the aerodisk.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

Science.gov (United States)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Yi Zhao

2012-08-01

Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO₂ as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO₂ gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO₂ and La₂O₃. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La₂O₃, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

Top-gate microcrystalline silicon TFTs processed at low temperature (<200 deg. C)

International Nuclear Information System (INIS)

Saboundji, A.; Coulon, N.; Gorin, A.; Lhermite, H.; Mohammed-Brahim, T.; Fonrodona, M.; Bertomeu, J.; Andreu, J.

2005-01-01

N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 deg. C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2 -N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it =6.4x10 10 eV -1 cm -2 . High field effect mobility, 25 cm 2 /V s for electrons and 1.1 cm 2 /V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously

Accuracy and effectiveness of self-gating signals in free-breathing three-dimensional cardiac cine magnetic resonance imaging

Science.gov (United States)

Li, Shuo; Wang, Lei; Zhu, Yan-Chun; Yang, Jie; Xie, Yao-Qin; Fu, Nan; Wang, Yi; Gao, Song

2016-12-01

Conventional multiple breath-hold two-dimensional (2D) balanced steady-state free precession (SSFP) presents many difficulties in cardiac cine magnetic resonance imaging (MRI). Recently, a self-gated free-breathing three-dimensional (3D) SSFP technique has been proposed as an alternative in many studies. However, the accuracy and effectiveness of self-gating signals have been barely studied before. Since self-gating signals are crucially important in image reconstruction, a systematic study of self-gating signals and comparison with external monitored signals are needed. Previously developed self-gated free-breathing 3D SSFP techniques are used on twenty-eight healthy volunteers. Both electrocardiographic (ECG) and respiratory bellow signals are also acquired during the scan as external signals. Self-gating signal and external signal are compared by trigger and gating window. Gating window is proposed to evaluate the accuracy and effectiveness of respiratory self-gating signal. Relative deviation of the trigger and root-mean-square-deviation of the cycle duration are calculated. A two-tailed paired t-test is used to identify the difference between self-gating and external signals. A Wilcoxon signed rank test is used to identify the difference between peak and valley self-gating triggers. The results demonstrate an excellent correlation (P = 0, R > 0.99) between self-gating and external triggers. Wilcoxon signed rank test shows that there is no significant difference between peak and valley self-gating triggers for both cardiac (H = 0, P > 0.10) and respiratory (H = 0, P > 0.44) motions. The difference between self-gating and externally monitored signals is not significant (two-tailed paired-sample t-test: H = 0, P > 0.90). The self-gating signals could demonstrate cardiac and respiratory motion accurately and effectively as ECG and respiratory bellow. The difference between the two methods is not significant and can be explained. Furthermore, few ECG trigger errors

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

Directory of Open Access Journals (Sweden)

Xiaojun Cheng

2014-05-01

Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

Microchannel-flowed-plasma modification of octadecyltrichlorosilane self-assembled-monolayers for liquid crystal alignment

International Nuclear Information System (INIS)

Zheng, W.; Chiang, C.-Y.; Underwood, I.

2013-01-01

We report that a chemical patterning technique based on local plasma modification of self-assembled monolayers has been utilized to fabricate surfaces for domain liquid crystal alignment. Highly hydrophobic octadecyltrichlorosilane monolayers deposited on glass substrates coated with Indium-Tin-Oxide were brought into contact with elastomeric stamps comprising trenches on a micro scale, and then exposed to an oxygen plasma. In the regions exposed to the plasma the monolayer was etched away leaving a patterned surface that exhibited surface energy differences between surface domains. The surfaces that bear the micropatterns have been shown to be capable of producing patterned alignment of nematic liquid crystal. - Highlights: • Chemical surface-patterning is used to fabricate liquid crystal alignment surface. • Highly hydrophobic octadecyltrichlorosilane monolayer is deposited on substrate. • O 2 plasma flow is used to etch the monolayer to form patterned surface. • The patterned surface exhibits surface energy differences between surface domains. • The surface borne the micropatterns is capable of domain liquid crystal alignment

Self-alignment of RFID dies on four-pad patterns with water droplet for sparse self-assembly

International Nuclear Information System (INIS)

Chang, Bo; Routa, Iiris; Sariola, Veikko; Zhou, Quan

2011-01-01

This paper reports an in-depth study of a water-droplet-assisted self-alignment technique that self-aligns radio frequency identification (RFID) dies on four-pad patterns. The segmented structure of four hydrophilic pads on a hydrophobic substrate brings freedom to the design of the electrical functionality and the surface functionality. The paper investigates the influence of the key parameters that may affect the self-alignment in theory and experiment. The theoretical model justifies that RFID dies can be reliably aligned on the segmented four-pad pattern even when the initial placement error is as large as 50% of the size of the die and the gap between the four pads is about 10% of the size of the die. A method has been introduced to estimate the sufficient droplet volume for self-alignment. A series of experiments have been carried out to verify the results of the model. The experiments indicate that the self-alignment between the 730 × 730 µm RFID dies and the pattern occurs reliably when the releasing bias between the RFID die and antenna is less than 400 µm for patterns with 50 and 100 µm gaps, and successful self-alignment is possible even with greater bias of 500 µm

Design and fabrication of a self-aligned parallel-plate-type silicon micromirror minimizing the effect of misalignment

International Nuclear Information System (INIS)

Yoo, Byung-Wook; Jin, Joo-Young; Jang, Yun-Ho; Kim, Yong-Kweon; Park, Jae-Hyoung

2009-01-01

This paper describes a self-alignment method whereby a mirror actuation voltage, corresponding to a specific tilting angle, is unvarying in terms of misalignment during fabrication. A deep silicon etching process is proposed to penetrate the top silicon layer (the micromirror layer) and an amorphous silicon layer (the addressing electrode layer) together, through an aluminum mask pattern, in order to minimize the misalignment effect on the micromirror actuation. The size of a fabricated mirror plate is 250 × 250 × 4 µm 3 . A pair of amorphous silicon electrodes under the mirror plate is about half the size of the mirror plate individually. Numerical analysis associated with calculating the pull-in voltage and the bonding misalignment is performed to verify the self-alignment concepts focused upon in this paper. Curves of the applied voltage versus the tilt angle of the self-aligned micromirror are observed using a position sensing detector in order to compare the measurement results with MATLAB analysis of the expected static deflections. Although a 3.7 µm misalignment is found between the mirror plate and the electrodes, in the direction perpendicular to the shallow trench of the electrodes, before the self-alignment process, the measured pull-in voltage has been found to be 103.4 V on average; this differs from the pull-in voltage of a perfectly aligned micromirror by only 0.67%. Regardless of the unpredictable misalignments in repetitive photolithography and bonding, the tilting angles corresponding to the driving voltages are proved to be uniform along the single axis as well as conform to the results of analytical analysis

Effect of grain alignment on interface trap density of thermally oxidized aligned-crystalline silicon films

Science.gov (United States)

Choi, Woong; Lee, Jung-Kun; Findikoglu, Alp T.

2006-12-01

The authors report studies of the effect of grain alignment on interface trap density of thermally oxidized aligned-crystalline silicon (ACSi) films by means of capacitance-voltage (C-V) measurements. C-V curves were measured on metal-oxide-semiconductor (MOS) capacitors fabricated on ⟨001⟩-oriented ACSi films on polycrystalline substrates. From high-frequency C-V curves, the authors calculated a decrease of interface trap density from 2×1012to1×1011cm-2eV-1 as the grain mosaic spread in ACSi films improved from 13.7° to 6.5°. These results demonstrate the effectiveness of grain alignment as a process technique to achieve significantly enhanced performance in small-grained (⩽1μm ) polycrystalline Si MOS-type devices.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

Science.gov (United States)

Neudeck, Philip G. (Inventor)

2014-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Ballistic transport of graphene pnp junctions with embedded local gates

International Nuclear Information System (INIS)

Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan

2011-01-01

We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.

Top-down approach in protein RDC data analysis: de novo estimation of the alignment tensor

International Nuclear Information System (INIS)

Chen Kang; Tjandra, Nico

2007-01-01

In solution NMR spectroscopy the residual dipolar coupling (RDC) is invaluable in improving both the precision and accuracy of NMR structures during their structural refinement. The RDC also provides a potential to determine protein structure de novo. These procedures are only effective when an accurate estimate of the alignment tensor has already been made. Here we present a top-down approach, starting from the secondary structure elements and finishing at the residue level, for RDC data analysis in order to obtain a better estimate of the alignment tensor. Using only the RDCs from N-H bonds of residues in α-helices and CA-CO bonds in β-strands, we are able to determine the offset and the approximate amplitude of the RDC modulation-curve for each secondary structure element, which are subsequently used as targets for global minimization. The alignment order parameters and the orientation of the major principal axis of individual helix or strand, with respect to the alignment frame, can be determined in each of the eight quadrants of a sphere. The following minimization against RDC of all residues within the helix or strand segment can be carried out with fixed alignment order parameters to improve the accuracy of the orientation. For a helical protein Bax, the three components A xx , A yy and A zz , of the alignment order can be determined with this method in average to within 2.3% deviation from the values calculated with the available atomic coordinates. Similarly for β-sheet protein Ubiquitin they agree in average to within 8.5%. The larger discrepancy in β-strand parameters comes from both the diversity of the β-sheet structure and the lower precision of CA-CO RDCs. This top-down approach is a robust method for alignment tensor estimation and also holds a promise for providing a protein topological fold using limited sets of RDCs

Graphene-graphite oxide field-effect transistors.

Science.gov (United States)

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Chemical gating of epitaxial graphene through ultrathin oxide layers.

Science.gov (United States)

Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

2015-08-07

We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

Analgesia induced by self-initiated electrotactile sensation is mediated by top-down modulations.

Science.gov (United States)

Zhao, Ke; Tang, Zhengyu; Wang, Huiquan; Guo, Yifei; Peng, Weiwei; Hu, Li

2017-06-01

It is well known that sensory perception can be attenuated when sensory stimuli are controlled by self-initiated actions. This phenomenon is explained by the consistency between forward models of anticipated action effects and actual sensory feedback. Specifically, the brain state related to the binding between motor processing and sensory perception would have inhibitory function by gating sensory information via top-down control. Since the brain state could casually influence the perception of subsequent stimuli of different sensory modalities, we hypothesize that pain evoked by nociceptive stimuli following the self-initiated tactile stimulation would be attenuated as compared to that following externally determined tactile stimulation. Here, we compared psychophysical and neurophysiological responses to identical nociceptive-specific laser stimuli in two different conditions: self-initiated tactile sensation condition (STS) and nonself-initiated tactile sensation condition (N-STS). We observed that pain intensity and unpleasantness, as well as laser-evoked brain responses, were significantly reduced in the STS condition compared to the N-STS condition. In addition, magnitudes of alpha and beta oscillations prior to laser onset were significantly larger in the STS condition than in the N-STS condition. These results confirmed that pain perception and pain-related brain responses were attenuated when the tactile stimulation was initiated by subjects' voluntary actions, and exploited neural oscillations reflecting the binding between motor processing and sensory feedback. Thus, our study elaborated the understanding of underlying neural mechanisms related to top-down modulations of the analgesic effect induced by self-initiated tactile sensation, which provided theoretical basis to improve the analgesic effect in various clinical applications. © 2017 Society for Psychophysiological Research.

Static characteristics and short channel effect in enhancement-mode AlN/GaN/AlN N-polar MISFET with self-aligned source/drain regions

International Nuclear Information System (INIS)

Li Bin; Wei Lan; Wen Cai

2014-01-01

This paper aims to simulate the I–V static characteristic of the enhancement-mode (E-mode) N-polar GaN metal—insulator—semiconductor field effect transistor (MISFET) with self-aligned source/drain regions. Firstly, with SILVACO TCAD device simulation, the drain—source current as a function of the gate—source voltage is calculated and the dependence of the drain—source current on the drain—source voltage in the case of different gate—source voltages for the device with a 0.62 μm gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 μm and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a 100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously. (semiconductor devices)

AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

Science.gov (United States)

Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

2015-01-01

Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al2O3 gate oxides

International Nuclear Information System (INIS)

Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig

2008-01-01

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al 2 O 3 tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I DS -V GS ) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper

Reliability study of ultra-thin gate oxides on strained-Si/SiGe MOS structures

International Nuclear Information System (INIS)

Varzgar, John B.; Kanoun, Mehdi; Uppal, Suresh; Chattopadhyay, Sanatan; Tsang, Yuk Lun; Escobedo-Cousins, Enrique; Olsen, Sarah H.; O'Neill, Anthony; Hellstroem, Per-Erik; Edholm, Jonas; Ostling, Mikael; Lyutovich, Klara; Oehme, Michael; Kasper, Erich

2006-01-01

The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exhibit a shorter life time compared to that of bulk Si, which is attributed to higher bulk oxide charges (Q ox ) and increased surface roughness in the s-Si structures. The gate oxide in the s-Si structure exhibits a hard breakdown (HBD) at 1.9 x 10 4 s, whereas HBD is not observed in bulk Si up to a measurement period of 1.44 x 10 5 s. The shorter lifetime of the s-Si gate oxide is attributed to a larger injected charge (Q inj ) compared to Q inj in bulk Si. Current-voltage (I-V) measurements for bulk Si samples at different stress intervals show an increase in stress induced leakage current (SILC) of two orders in the low voltage regime from zero stress time to up to 5 x 10 4 s. In contrast, superior performance enhancements in terms of drain current, maximum transconductance and effective channel mobility are observed in s-Si MOSFET devices compared to bulk Si. The results from this study indicate that further improvement in gate oxide reliability is needed to exploit the sustained performance enhancement of s-Si devices over bulk Si

Impact of oxide thickness on gate capacitance – Modelling and ...

Indian Academy of Sciences (India)

Department of Electronics and Communication Engineering, National ... conventional HEMT, Schottky barrier diode is formed at the gate electrode. .... term corresponds to the energy required for the electric field in the oxide layer and the.

Planar self-aligned imprint lithography for coplanar plasmonic nanostructures fabrication

KAUST Repository

Wan, Weiwei; Lin, Liang; Xu, Yelong; Guo, Xu; Liu, Xiaoping; Ge, Haixiong; Lu, Minghui; Cui, Bo; Chen, Yanfeng

2014-01-01

manufacturing remains a challenge due to the high cost of achieving mechanical alignment precision. Although self-aligned imprint lithography was developed to avoid the need of alignment for the vertical layered structures, it has limited usage

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

Science.gov (United States)

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Impact of metal-ion contaminated silica particles on gate oxide integrity

NARCIS (Netherlands)

Rink, Ingrid; Wali, F.; Knotter, D.M.

2009-01-01

The impact of metal-ion contamination (present on wafer surface before oxidation) on gate oxide integrity (GOI) is well known in literature, which is not the case for clean silica particles [1, 2]. However, it is known that particles present in ultra-pure water (UPW) decrease the random yield in

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

Directory of Open Access Journals (Sweden)

Jingyu Shen

2018-01-01

Full Text Available The breakdown characteristics of ultra-thin gate oxide MOS capacitors fabricated in 65 nm CMOS technology under constant voltage stress and substrate hot-carrier injection are investigated. Compared to normal thick gate oxide, the degradation mechanism of time-dependent dielectric breakdown (TDDB of ultra-thin gate oxide is found to be different. It is found that the gate current (Ig of ultra-thin gate oxide MOS capacitor is more likely to be induced not only by Fowler-Nordheim (F-N tunneling electrons, but also by electrons surmounting barrier and penetrating electrons in the condition of constant voltage stress. Moreover it is shown that the time to breakdown (tbd under substrate hot-carrier injection is far less than that under constant voltage stress when the failure criterion is defined as a hard breakdown according to the experimental results. The TDDB mechanism of ultra-thin gate oxide will be detailed. The differences in TDDB characteristics of MOS capacitors induced by constant voltage stress and substrate hot-carrier injection will be also discussed.

Inner detector alignment and top-quark mass measurement with the ATLAS detector

CERN Document Server

Moles-Valls, Regina

This thesis is divided in two parts: one related with the alignment of the ATLAS Inner Detector tracking system and other with the measurement of the top-quark mass. Both topics are connected by the Globalχ2 fitting method. In order to measure the properties of the particles with high accuracy, the ID detector is composed by devices with high intrinsic resolution. If by any chance the position of the modules in the detector is known with worse precision than their intrinsic resolution this may introduce a distortion in the reconstructed trajectory of the particles or at least degrade the tracking resolution. The alignment is the responsible of determining the location of each module with high precision and avoiding therefore any bias in the physics results. During the commissioning of the detector, different alignment exercises were performed for preparing the Globalχ2 algorithm (the CSC , the FDR, weak modes studies,…). At the same time, the ATLAS detector was collecting million of cosmic rays which were...

Cascading of molecular logic gates for advanced functions: a self-reporting, activatable photosensitizer.

Science.gov (United States)

Erbas-Cakmak, Sundus; Akkaya, Engin U

2013-10-18

Logical progress: Independent molecular logic gates have been designed and characterized. Then, the individual molecular logic gates were coerced to work together within a micelle. Information relay between the two logic gates was achieved through the intermediacy of singlet oxygen. Working together, these concatenated logic gates result in a self-reporting and activatable photosensitizer. GSH=glutathione. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Kalman Filter for SINS Self-Alignment Based on Vector Observation.

Science.gov (United States)

Xu, Xiang; Xu, Xiaosu; Zhang, Tao; Li, Yao; Tong, Jinwu

2017-01-29

In this paper, a self-alignment method for strapdown inertial navigation systems based on the q -method is studied. In addition, an improved method based on integrating gravitational apparent motion to form apparent velocity is designed, which can reduce the random noises of the observation vectors. For further analysis, a novel self-alignment method using a Kalman filter based on adaptive filter technology is proposed, which transforms the self-alignment procedure into an attitude estimation using the observation vectors. In the proposed method, a linear psuedo-measurement equation is adopted by employing the transfer method between the quaternion and the observation vectors. Analysis and simulation indicate that the accuracy of the self-alignment is improved. Meanwhile, to improve the convergence rate of the proposed method, a new method based on parameter recognition and a reconstruction algorithm for apparent gravitation is devised, which can reduce the influence of the random noises of the observation vectors. Simulations and turntable tests are carried out, and the results indicate that the proposed method can acquire sound alignment results with lower standard variances, and can obtain higher alignment accuracy and a faster convergence rate.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-02-12

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

Science.gov (United States)

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

Acoustic logic gates and Boolean operation based on self-collimating acoustic beams

International Nuclear Information System (INIS)

Zhang, Ting; Xu, Jian-yi; Cheng, Ying; Liu, Xiao-jun; Guo, Jian-zhong

2015-01-01

The reveal of self-collimation effect in two-dimensional (2D) photonic or acoustic crystals has opened up possibilities for signal manipulation. In this paper, we have proposed acoustic logic gates based on the linear interference of self-collimated beams in 2D sonic crystals (SCs) with line-defects. The line defects on the diagonal of the 2D square SCs are actually functioning as a 3 dB splitter. By adjusting the phase difference between two input signals, the basic Boolean logic functions such as XOR, OR, AND, and NOT are achieved both theoretically and experimentally. Due to the non-diffracting property of self-collimation beams, more complex Boolean logic and algorithms such as NAND, NOR, and XNOR can be realized by cascading the basic logic gates. The achievement of acoustic logic gates and Boolean operation provides a promising approach for acoustic signal computing and manipulations

Synergistic toughening of composite fibres by self-alignment of reduced graphene oxide and carbon nanotubes

Science.gov (United States)

Shin, Min Kyoon; Lee, Bommy; Kim, Shi Hyeong; Lee, Jae Ah; Spinks, Geoffrey M.; Gambhir, Sanjeev; Wallace, Gordon G.; Kozlov, Mikhail E.; Baughman, Ray H.; Kim, Seon Jeong

2012-01-01

The extraordinary properties of graphene and carbon nanotubes motivate the development of methods for their use in producing continuous, strong, tough fibres. Previous work has shown that the toughness of the carbon nanotube-reinforced polymer fibres exceeds that of previously known materials. Here we show that further increased toughness results from combining carbon nanotubes and reduced graphene oxide flakes in solution-spun polymer fibres. The gravimetric toughness approaches 1,000 J g-1, far exceeding spider dragline silk (165 J g-1) and Kevlar (78 J g-1). This toughness enhancement is consistent with the observed formation of an interconnected network of partially aligned reduced graphene oxide flakes and carbon nanotubes during solution spinning, which act to deflect cracks and allow energy-consuming polymer deformation. Toughness is sensitive to the volume ratio of the reduced graphene oxide flakes to the carbon nanotubes in the spinning solution and the degree of graphene oxidation. The hybrid fibres were sewable and weavable, and could be shaped into high-modulus helical springs.

Synergistic toughening of composite fibres by self-alignment of reduced graphene oxide and carbon nanotubes.

Science.gov (United States)

Shin, Min Kyoon; Lee, Bommy; Kim, Shi Hyeong; Lee, Jae Ah; Spinks, Geoffrey M; Gambhir, Sanjeev; Wallace, Gordon G; Kozlov, Mikhail E; Baughman, Ray H; Kim, Seon Jeong

2012-01-31

The extraordinary properties of graphene and carbon nanotubes motivate the development of methods for their use in producing continuous, strong, tough fibres. Previous work has shown that the toughness of the carbon nanotube-reinforced polymer fibres exceeds that of previously known materials. Here we show that further increased toughness results from combining carbon nanotubes and reduced graphene oxide flakes in solution-spun polymer fibres. The gravimetric toughness approaches 1,000 J g(-1), far exceeding spider dragline silk (165 J g(-1)) and Kevlar (78 J g(-1)). This toughness enhancement is consistent with the observed formation of an interconnected network of partially aligned reduced graphene oxide flakes and carbon nanotubes during solution spinning, which act to deflect cracks and allow energy-consuming polymer deformation. Toughness is sensitive to the volume ratio of the reduced graphene oxide flakes to the carbon nanotubes in the spinning solution and the degree of graphene oxidation. The hybrid fibres were sewable and weavable, and could be shaped into high-modulus helical springs.

An oxide filled extended trench gate super junction MOSFET structure

International Nuclear Information System (INIS)

Cai-Lin, Wang; Jun, Sun

2009-01-01

This paper proposes an oxide filled extended trench gate super junction (SJ) MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Understanding the Structure of High-K Gate Oxides - Oral Presentation

Energy Technology Data Exchange (ETDEWEB)

Miranda, Andre [SLAC National Accelerator Lab., Menlo Park, CA (United States)

2015-08-25

Hafnium Oxide (HfO₂) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO₂ thin films which hasn’t been done with the technique of this study. In this study, two HfO₂ samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO₂ samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO₂ published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO₂ molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

Control rod housing alignment

International Nuclear Information System (INIS)

Dixon, R.C.; Deaver, G.A.; Punches, J.R.; Singleton, G.E.; Erbes, J.G.; Offer, H.P.

1990-01-01

This patent describes a process for measuring the vertical alignment between a hole in a core plate and the top of a corresponding control rod drive housing within a boiling water reactor. It comprises: providing an alignment apparatus. The alignment apparatus including a lower end for fitting to the top of the control rod drive housing; an upper end for fitting to the aperture in the core plate, and a leveling means attached to the alignment apparatus to read out the difference in angularity with respect to gravity, and alignment pin registering means for registering to the alignment pin on the core plate; lowering the alignment device on a depending support through a lattice position in the top guide through the hole in the core plate down into registered contact with the top of the control rod drive housing; registering the upper end to the sides of the hole in the core plate; registering the alignment pin registering means to an alignment pin on the core plate to impart to the alignment device the required angularity; and reading out the angle of the control rod drive housing with respect to the hole in the core plate through the leveling devices whereby the angularity of the top of the control rod drive housing with respect to the hole in the core plate can be determined

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

Science.gov (United States)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

Science.gov (United States)

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Assessing self-reported use of new psychoactive substances: The impact of gate questions.

Science.gov (United States)

Palamar, Joseph J; Acosta, Patricia; Calderón, Fermín Fernández; Sherman, Scott; Cleland, Charles M

2017-09-01

New psychoactive substances (NPS) continue to emerge; however, few surveys of substance use ask about NPS use. Research is needed to determine how to most effectively query use of NPS and other uncommon drugs. To determine whether prevalence of self-reported lifetime and past-year use differs depending on whether or not queries about NPS use are preceded by "gate questions." Gate questions utilize skip-logic, such that only a "yes" response to the use of specific drug class is followed by more extensive queries of drug use in that drug class. We surveyed 1,048 nightclub and dance festival attendees (42.6% female) entering randomly selected venues in New York City in 2016. Participants were randomized to gate vs. no gate question before each drug category. Analyses focus on eight categories classifying 145 compounds: NBOMe, 2C, DOx, "bath salts" (synthetic cathinones), other stimulants, tryptamines, dissociatives, and non-phenethylamine psychedelics. Participants, however, were asked about specific "bath salts" regardless of their response to the gate question to test reliability. We examined whether prevalence of use of each category differed by gate condition and whether gate effects were moderated by participant demographics. Prevalence of use of DOx, other stimulants, and non-phenethylamine psychedelics was higher without a gate question. Gate effects for other stimulants and non-phenethylamine psychedelics were larger among white participants and those attending parties less frequently. Almost one in ten (9.3%) participants reporting no "bath salt" use via the gate question later reported use of a "bath salt" such as mephedrone, methedrone, or methylone. Omitting gate questions may improve accuracy of data collected via self-report.

Self-gated golden angle spiral cine MRI for coronary endothelial function assessment.

Science.gov (United States)

Bonanno, Gabriele; Hays, Allison G; Weiss, Robert G; Schär, Michael

2018-08-01

Depressed coronary endothelial function (CEF) is a marker for atherosclerotic disease, an independent predictor of cardiovascular events, and can be quantified non-invasively with ECG-triggered spiral cine MRI combined with isometric handgrip exercise (IHE). However, MRI-CEF measures can be hindered by faulty ECG-triggering, leading to prolonged breath-holds and degraded image quality. Here, a self-gated golden angle spiral method (SG-GA) is proposed to eliminate the need for ECG during cine MRI. SG-GA was tested against retrospectively ECG-gated golden angle spiral MRI (ECG-GA) and gold-standard ECG-triggered spiral cine MRI (ECG-STD) in 10 healthy volunteers. CEF data were obtained from cross-sectional images of the proximal right and left coronary arteries in a 3T scanner. Self-gating heart rates were compared to those from simultaneous ECG-gating. Coronary vessel sharpness and cross-sectional area (CSA) change with IHE were compared among the 3 methods. Self-gating precision, accuracy, and correlation-coefficient were 7.7 ± 0.5 ms, 9.1 ± 0.7 ms, and 0.93 ± 0.01, respectively (mean ± standard error). Vessel sharpness by SG-GA was equal or higher than ECG-STD (rest: 63.0 ± 1.7% vs. 61.3 ± 1.3%; exercise: 62.6 ± 1.3% vs. 56.7 ± 1.6%, P < 0.05). CSA changes were in agreement among the 3 methods (ECG-STD = 8.7 ± 4.0%, ECG-GA = 9.6 ± 3.1%, SG-GA = 9.1 ± 3.5%, P = not significant). CEF measures can be obtained with the proposed self-gated high-quality cine MRI method even when ECG is faulty or not available. Magn Reson Med 80:560-570, 2018. © 2017 International Society for Magnetic Resonance in Medicine. © 2017 International Society for Magnetic Resonance in Medicine.

Self-Assembling Molecular Logic Gates Based on DNA Crossover Tiles.

Science.gov (United States)

Campbell, Eleanor A; Peterson, Evan; Kolpashchikov, Dmitry M

2017-07-05

DNA-based computational hardware has attracted ever-growing attention due to its potential to be useful in the analysis of complex mixtures of biological markers. Here we report the design of self-assembling logic gates that recognize DNA inputs and assemble into crossover tiles when the output signal is high; the crossover structures disassemble to form separate DNA stands when the output is low. The output signal can be conveniently detected by fluorescence using a molecular beacon probe as a reporter. AND, NOT, and OR logic gates were designed. We demonstrate that the gates can connect to each other to produce other logic functions. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

Energy Technology Data Exchange (ETDEWEB)

Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

2012-10-30

We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

Influence of implantation energy on the electrical properties of ultrathin gate oxides grown on nitrogen implanted Si substrates

International Nuclear Information System (INIS)

Kapetanakis, E.; Skarlatos, D.; Tsamis, C.; Normand, P.; Tsoukalas, D.

2003-01-01

Metal-oxide-semiconductor tunnel diodes with gate oxides, in the range of 2.5-3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) x10 15 cm -2 dose, respectively, are investigated. The dependence of N 2 + ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides

Free breathing whole-heart 3D CINE MRI with self-gated Cartesian trajectory.

Science.gov (United States)

Usman, M; Ruijsink, B; Nazir, M S; Cruz, G; Prieto, C

2017-05-01

To present a method that uses a novel free-running self-gated acquisition to achieve isotropic resolution in whole heart 3D Cartesian cardiac CINE MRI. 3D cardiac CINE MRI using navigator gating results in long acquisition times. Recently, several frameworks based on self-gated non-Cartesian trajectories have been proposed to accelerate this acquisition. However, non-Cartesian reconstructions are computationally expensive due to gridding, particularly in 3D. In this work, we propose a novel highly efficient self-gated Cartesian approach for 3D cardiac CINE MRI. Acquisition is performed using CArtesian trajectory with Spiral PRofile ordering and Tiny golden angle step for eddy current reduction (so called here CASPR-Tiger). Data is acquired continuously under free breathing (retrospective ECG gating, no preparation pulses interruption) for 4-5min and 4D whole-heart volumes (3D+cardiac phases) with isotropic spatial resolution are reconstructed from all available data using a soft gating technique combined with temporal total variation (TV) constrained iterative SENSE reconstruction. For data acquired on eight healthy subjects and three patients, the reconstructed images using the proposed method had good contrast and spatio-temporal variations, correctly recovering diastolic and systolic cardiac phases. Non-significant differences (P>0.05) were observed in cardiac functional measurements obtained with proposed 3D approach and gold standard 2D multi-slice breath-hold acquisition. The proposed approach enables isotropic 3D whole heart Cartesian cardiac CINE MRI in 4 to 5min free breathing acquisition. Copyright © 2017 The Authors. Published by Elsevier Inc. All rights reserved.

Self-aligning and compressed autosophy video databases

Science.gov (United States)

Holtz, Klaus E.

1993-04-01

Autosophy, an emerging new science, explains `self-assembling structures,' such as crystals or living trees, in mathematical terms. This research provides a new mathematical theory of `learning' and a new `information theory' which permits the growing of self-assembling data network in a computer memory similar to the growing of `data crystals' or `data trees' without data processing or programming. Autosophy databases are educated very much like a human child to organize their own internal data storage. Input patterns, such as written questions or images, are converted to points in a mathematical omni dimensional hyperspace. The input patterns are then associated with output patterns, such as written answers or images. Omni dimensional information storage will result in enormous data compression because each pattern fragment is only stored once. Pattern recognition in the text or image files is greatly simplified by the peculiar omni dimensional storage method. Video databases will absorb input images from a TV camera and associate them with textual information. The `black box' operations are totally self-aligning where the input data will determine their own hyperspace storage locations. Self-aligning autosophy databases may lead to a new generation of brain-like devices.

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al{sub 2}O{sub 3} gate oxides

Energy Technology Data Exchange (ETDEWEB)

Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig [Department of Electrical Engineering and Institute for Nano Science, Korea University, Seoul 136-701 (Korea, Republic of)], E-mail: sangsig@korea.ac.kr

2008-10-01

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al{sub 2}O{sub 3} tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I{sub DS}-V{sub GS}) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

International Nuclear Information System (INIS)

Shi-Gang, Hu; Yan-Rong, Cao; Yue, Hao; Xiao-Hua, Ma; Chi, Chen; Xiao-Feng, Wu; Qing-Jun, Zhou

2008-01-01

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

The top right coupling in the aligned two-Higgs-doublet model

Energy Technology Data Exchange (ETDEWEB)

Ayala, Cesar [Departament de Física Teòrica, Universitat de València & Instituto de Física Corpuscular (IFIC),Centro Mixto Universitat de València-CSIC,E-46100 Burjassot, València (Spain); Department of Physics, Universidad Técnica Federico Santa María,Casilla 110-V, Valparaíso (Chile); González-Sprinberg, Gabriel A. [Instituto de Física, Facultad de Ciencias, Universidad de la República,Iguá 4225, Montevideo 11600 (Uruguay); Martinez, R. [Departamento de Física, Universidad Nacional de Colombia,Bogotá Distrito Capital (Colombia); Vidal, Jordi [Departament de Física Teòrica, Universitat de València & Instituto de Física Corpuscular (IFIC),Centro Mixto Universitat de València-CSIC,E-46100 Burjassot, València (Spain)

2017-03-24

We compute the top quark right coupling in the aligned two-Higgs-doublet model. In the Standard Model the real part of this coupling is dominated by QCD-gluon-exchange diagram, but the imaginary part, instead, is purely electroweak at one loop. Within this model we show that values for the imaginary part of the coupling up to one order of magnitude larger than the electroweak prediction can be obtained. For the real part of the electroweak contribution we find that it can be of the order of 2×10{sup −4}. We also present detailed results of the one loop analytical computation.

Highly-accelerated self-gated free-breathing 3D cardiac cine MRI: validation in assessment of left ventricular function.

Science.gov (United States)

Liu, Jing; Feng, Li; Shen, Hsin-Wei; Zhu, Chengcheng; Wang, Yan; Mukai, Kanae; Brooks, Gabriel C; Ordovas, Karen; Saloner, David

2017-08-01

This work presents a highly-accelerated, self-gated, free-breathing 3D cardiac cine MRI method for cardiac function assessment. A golden-ratio profile based variable-density, pseudo-random, Cartesian undersampling scheme was implemented for continuous 3D data acquisition. Respiratory self-gating was achieved by deriving motion signal from the acquired MRI data. A multi-coil compressed sensing technique was employed to reconstruct 4D images (3D+time). 3D cardiac cine imaging with self-gating was compared to bellows gating and the clinical standard breath-held 2D cine imaging for evaluation of self-gating accuracy, image quality, and cardiac function in eight volunteers. Reproducibility of 3D imaging was assessed. Self-gated 3D imaging provided an image quality score of 3.4 ± 0.7 vs 4.0 ± 0 with the 2D method (p = 0.06). It determined left ventricular end-systolic volume as 42.4 ± 11.5 mL, end-diastolic volume as 111.1 ± 24.7 mL, and ejection fraction as 62.0 ± 3.1%, which were comparable to the 2D method, with bias ± 1.96 × SD of -0.8 ± 7.5 mL (p = 0.90), 2.6 ± 3.3 mL (p = 0.84) and 1.4 ± 6.4% (p = 0.45), respectively. The proposed 3D cardiac cine imaging method enables reliable respiratory self-gating performance with good reproducibility, and provides comparable image quality and functional measurements to 2D imaging, suggesting that self-gated, free-breathing 3D cardiac cine MRI framework is promising for improved patient comfort and cardiac MRI scan efficiency.

Printed indium gallium zinc oxide transistors. Self-assembled nanodielectric effects on low-temperature combustion growth and carrier mobility.

Science.gov (United States)

Everaerts, Ken; Zeng, Li; Hennek, Jonathan W; Camacho, Diana I; Jariwala, Deep; Bedzyk, Michael J; Hersam, Mark C; Marks, Tobin J

2013-11-27

Solution-processed amorphous oxide semiconductors (AOSs) are emerging as important electronic materials for displays and transparent electronics. We report here on the fabrication, microstructure, and performance characteristics of inkjet-printed, low-temperature combustion-processed, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) grown on solution-processed hafnia self-assembled nanodielectrics (Hf-SANDs). TFT performance for devices processed below 300 °C includes >4× enhancement in electron mobility (μFE) on Hf-SAND versus SiO2 or ALD-HfO2 gate dielectrics, while other metrics such as subthreshold swing (SS), current on:off ratio (ION:IOFF), threshold voltage (Vth), and gate leakage current (Ig) are unchanged or enhanced. Thus, low voltage IGZO/SAND TFT operation (IGZO combustion processing leaves the underlying Hf-SAND microstructure and capacitance intact. This work establishes the compatibility and advantages of all-solution, low-temperature fabrication of inkjet-printed, combustion-derived high-mobility IGZO TFTs integrated with self-assembled hybrid organic-inorganic nanodielectrics.

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

International Nuclear Information System (INIS)

Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

2009-01-01

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

International Nuclear Information System (INIS)

Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

2013-01-01

A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Planar self-aligned imprint lithography for coplanar plasmonic nanostructures fabrication

KAUST Repository

Wan, Weiwei

2014-03-01

Nanoimprint lithography (NIL) is a cost-efficient nanopatterning technology because of its promising advantages of high throughput and high resolution. However, accurate multilevel overlay capability of NIL required for integrated circuit manufacturing remains a challenge due to the high cost of achieving mechanical alignment precision. Although self-aligned imprint lithography was developed to avoid the need of alignment for the vertical layered structures, it has limited usage in the manufacture of the coplanar structures, such as integrated plasmonic devices. In this paper, we develop a new process of planar self-alignment imprint lithography (P-SAIL) to fabricate the metallic and dielectric structures on the same plane. P-SAIL transfers the multilevel imprint processes to a single-imprint process which offers higher efficiency and less cost than existing manufacturing methods. Such concept is demonstrated in an example of fabricating planar plasmonic structures consisting of different materials. © 2014 Springer-Verlag Berlin Heidelberg.

Dual-gate polysilicon nanoribbon biosensors enable high sensitivity detection of proteins

International Nuclear Information System (INIS)

Zeimpekis, I; Sun, K; Hu, C; Ditshego, N M J; De Planque, M R R; Chong, H M H; Morgan, H; Ashburn, P; Thomas, O

2016-01-01

We demonstrate the advantages of dual-gate polysilicon nanoribbon biosensors with a comprehensive evaluation of different measurement schemes for pH and protein sensing. In particular, we compare the detection of voltage and current changes when top- and bottom-gate bias is applied. Measurements of pH show that a large voltage shift of 491 mV pH"−"1 is obtained in the subthreshold region when the top-gate is kept at a fixed potential and the bottom-gate is varied (voltage sweep). This is an improvement of 16 times over the 30 mV pH"−"1 measured using a top-gate sweep with the bottom-gate at a fixed potential. A similar large voltage shift of 175 mV is obtained when the protein avidin is sensed using a bottom-gate sweep. This is an improvement of 20 times compared with the 8.8 mV achieved from a top-gate sweep. Current measurements using bottom-gate sweeps do not deliver the same signal amplification as when using bottom-gate sweeps to measure voltage shifts. Thus, for detecting a small signal change on protein binding, it is advantageous to employ a double-gate transistor and to measure a voltage shift using a bottom-gate sweep. For top-gate sweeps, the use of a dual-gate transistor enables the current sensitivity to be enhanced by applying a negative bias to the bottom-gate to reduce the carrier concentration in the nanoribbon. For pH measurements, the current sensitivity increases from 65% to 149% and for avidin sensing it increases from 1.4% to 2.5%. (paper)

Improvement of Self-Heating of Indium Gallium Zinc Aluminum Oxide Thin-Film Transistors Using Al2O3 Barrier Layer

Science.gov (United States)

Jian, Li-Yi; Lee, Hsin-Ying; Lin, Yung-Hao; Lee, Ching-Ting

2018-02-01

To study the self-heating effect, aluminum oxide (Al2O3) barrier layers of various thicknesses have been inserted between the channel layer and insulator layer in bottom-gate-type indium gallium zinc aluminum oxide (IGZAO) thin-film transistors (TFTs). Each IGZAO channel layer was deposited on indium tin oxide (ITO)-coated glass substrate by using a magnetron radiofrequency cosputtering system with dual targets composed of indium gallium zinc oxide (IGZO) and Al. The 3 s orbital of Al cation provided an extra transport pathway and widened the conduction-band bottom, thus increasing the electron mobility of the IGZAO films. The Al-O bonds were able to sustain the oxygen stability of the IGZAO films. The self-heating behavior of the resulting IGZAO TFTs was studied by Hall measurements on the IGZAO films as well as the electrical performance of the IGZAO TFTs with Al2O3 barrier layers of various thicknesses at different temperatures. IGZAO TFTs with 50-nm-thick Al2O3 barrier layer were stressed by positive gate bias stress (PGBS, at gate-source voltage V GS = 5 V and drain-source voltage V DS = 0 V); at V GS = 5 V and V DS = 10 V, the threshold voltage shifts were 0.04 V and 0.2 V, respectively, much smaller than for the other IGZAO TFTs without Al2O3 barrier layer, which shifted by 0.2 V and 1.0 V when stressed under the same conditions.

Liquid crystallinity driven highly aligned large graphene oxide composites

Energy Technology Data Exchange (ETDEWEB)

Lee, Kyung Eun; Oh, Jung Jae; Yun, Taeyeong [Center for Nanomaterials and Chemical Reactions, Institute for Basic Science (IBS), Daejeon 305-701 (Korea, Republic of); Department of Chemistry, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701 (Korea, Republic of); Kim, Sang Ouk, E-mail: sangouk.kim@kaist.ac.kr [Center for Nanomaterials and Chemical Reactions, Institute for Basic Science (IBS), Daejeon 305-701 (Korea, Republic of); Department of Chemistry, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701 (Korea, Republic of)

2015-04-15

Graphene is an emerging graphitic carbon materials, consisting of sp{sup 2} hybridized two dimensinal honeycomb structure. It has been widely studied to incorporate graphene with polymer to utilize unique property of graphene and reinforce electrical, mechanical and thermal property of polymer. In composite materials, orientation control of graphene significantly influences the property of composite. Until now, a few method has been developed for orientation control of graphene within polymer matrix. Here, we demonstrate facile fabrication of high aligned large graphene oxide (LGO) composites in polydimethylsiloxane (PDMS) matrix exploiting liquid crystallinity. Liquid crystalline aqueous dispersion of LGO is parallel oriented within flat confinement geometry. Freeze-drying of the aligned LGO dispersion and subsequent infiltration with PDMS produce highly aligned LGO/PDMS composites. Owing to the large shape anisotropy of LGO, liquid crystalline alignment occurred at low concentration of 2 mg/ml in aqueous dispersion, which leads to the 0.2 wt% LGO loaded composites. - Graphical abstract: Liquid crystalline LGO aqueous dispersions are spontaneous parallel aligned between geometric confinement for highly aligned LGO/polymer composite fabrication. - Highlights: • A simple fabrication method for highly aligned LGO/PDMS composites is proposed. • LGO aqueous dispersion shows nematic liquid crystalline phase at 0.8 mg/ml. • In nematic phase, LGO flakes are highly aligned by geometric confinement. • Infiltration of PDMS into freeze-dried LGO allows highly aligned LGO/PDMS composites.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.

2010-11-19

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

2010-01-01

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Capillary self-alignment of mesoscopic foil components for sensor-systems-in-foil

International Nuclear Information System (INIS)

Arutinov, Gari; Smits, Edsger C P; Van Heck, Gert; Van den Brand, Jeroen; Schoo, Herman F M; Mastrangeli, Massimo; Dietzel, Andreas

2012-01-01

This paper reports on the effective use of capillary self-alignment for low-cost and time-efficient assembly of heterogeneous foil components into a smart electronic identification label. Particularly, we demonstrate the accurate (better than 50 µm) alignment of cm-sized functional foil dies. We investigated the role played by the assembly liquid, by the size and the weight of assembling dies and by their initial offsets in the self-alignment performance. It was shown that there is a definite range of initial offsets allowing dies to align with high accuracy and within approximately the same time window, irrespective of their initial offset. (paper)

Top-down Fabrication and Enhanced Active Area Electronic Characteristics of Amorphous Oxide Nanoribbons for Flexible Electronics.

Science.gov (United States)

Jang, Hyun-June; Joong Lee, Ki; Jo, Kwang-Won; Katz, Howard E; Cho, Won-Ju; Shin, Yong-Beom

2017-07-18

Inorganic amorphous oxide semiconductor (AOS) materials such as amorphous InGaZnO (a-IGZO) possess mechanical flexibility and outstanding electrical properties, and have generated great interest for use in flexible and transparent electronic devices. In the past, however, AOS devices required higher activation energies, and hence higher processing temperatures, than organic ones to neutralize defects. It is well known that one-dimensional nanowires tend to have better carrier mobility and mechanical strength along with fewer defects than the corresponding two-dimensional films, but until now it has been difficult, costly, and impractical to fabricate such nanowires in proper alignments by either "bottom-up" growth techniques or by "top-down" e-beam lithography. Here we show a top-down, cost-effective, and scalable approach for the fabrication of parallel, laterally oriented AOS nanoribbons based on lift-off and nano-imprinting. High mobility (132 cm 2 /Vs), electrical stability, and transparency are obtained in a-IGZO nanoribbons, compared to the planar films of the same a-IGZO semiconductor.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

Energy Technology Data Exchange (ETDEWEB)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

2017-07-01

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Masamichi Suzuki

2012-03-01

Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

Energy Technology Data Exchange (ETDEWEB)

Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

2010-01-01

In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

Science.gov (United States)

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

The effect of barrier layer-mediated catalytic deactivation in vertically aligned carbon nanotube growth

International Nuclear Information System (INIS)

Patole, S P; Yu, Seong-Man; Shin, Dong-Wook; Yoo, Ji-Beom; Kim, Ha-Jin; Han, In-Taek; Kwon, Kee-Won

2010-01-01

The effect of Al-barrier layer-mediated Fe-catalytic deactivation in vertically aligned carbon nanotube (CNT) growth was studied. The substrate surface morphology, catalytic diffusion and barrier layer oxidation were found to be dependent on the annealing temperature of the barrier layer, which ultimately affects CNT growth. The annealed barrier layer without complete oxidation was found to be suitable for top to bottom super aligned CNT arrays. The highest average CNT growth rate of up to 3.88 μm s -1 was observed using this simple approach. Details of the analysis are also presented.

Modelling ionising radiation induced defect generation in bipolar oxides with gated diodes

International Nuclear Information System (INIS)

Barnaby, H.J.; Cirba, C.; Schrimpf, R.D.; Kosier, St.; Fouillat, P.; Montagner, X.

1999-01-01

Radiation-induced oxide defects that degrade electrical characteristics of bipolar junction transistor (BJTs) can be measured with the use of gated diodes. The buildup of defects and their effect on device radiation response are modeled with computer simulation. (authors)

Enhanced transconductance in a double-gate graphene field-effect transistor

Science.gov (United States)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

Teflon/SiO₂ Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process.

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Hung, Bohr-Ran

2015-04-13

This study proposes a two-photomask process for fabricating amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO₂ combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO₂ deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

Poly-silicon quantum-dot single-electron transistors

International Nuclear Information System (INIS)

Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook

2012-01-01

For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

Individual Style of Self-Regulation of the Top Quality Sportsmen

Directory of Open Access Journals (Sweden)

V. N. Potapov

2012-01-01

Full Text Available The paper deals with identifying the individual specifics of self- regulation style development by the top qualification biathletes – the members of the Russian Federation team. The research combines the theoretical analysis methods, idealization and modeling techniques, psychological diagnostics, medical and pedagogical testing, and pedagogic experiment. The methodology basis includes the ideas of self-regulation developed by O. A. Konopkin and V. I. Morosanova. The author has devised and substantiated the method of developing the individual style of self-regulation by the top category biathletes. It has been proved that the above style can be achieved by sportsmen in the process of developing socially adequate motivation and socially valued personality traits by using verbal auto-training methods. It is indicated that there is no fixed correlation between a success in sport training and personality type. However, each type has its inherent steady characteristic complex of self-regulation. The research findings can be implemented both in training the top achievement sportsmen and sport reserves. 

The effects of gate oxide thickness on radiation damage in MOS system

International Nuclear Information System (INIS)

Zhu Hui; Yan Rongliang; Wang Yu; He Jinming

1988-01-01

The dependences of the flatband voltage shift (ΔV FB ) and the threshold voltage shift (ΔV TH ) in MOS system on the oxide thickness (T ox ) and on total irradiated dose (D) of electron-beam and 60 Co γ-ray have been studied. It has been found that ΔV FB ∝ T ox 3 , with +10V of gate bias during irradiation for n-Si substrate MOS capacitors; ΔV TH ∝ T ox 3 D 2/3 , with 'on' gate bias during irradiation for n- and P-channel MOS transistors; ΔV TP ∝ T ox 2 D 2/3 , with 'off' gate bias during irradiation for P-channel MOS transistors. These results are explained by Viswanathan model. According to ∼T ox 3 dependence, the optimization of radiation hardening process for MOS system is also simply discussed

Leakage and field emission in side-gate graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.; Cucolo, A. M. [Physics Department “E.R. Caianiello,” University of Salerno, via G. Paolo II, 84084 Fisciano (Italy); CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Giubileo, F. [CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Russo, S.; Unal, S. [Physics Department, University of Exeter, Stocker Road 6, Exeter, Devon EX4 4QL (United Kingdom); Passacantando, M.; Grossi, V. [Department of Physical and Chemical Sciences, University of L' Aquila, Via Vetoio, 67100 Coppito, L' Aquila (Italy)

2016-07-11

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2015-01-01

Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

International Nuclear Information System (INIS)

Lin, Y. H.; Chou, J. C.

2015-01-01

We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

Gate-controlled quantum collimation in nanocolumn resonant tunnelling transistors

International Nuclear Information System (INIS)

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Lueth, H; Indlekofer, K M

2009-01-01

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n ++ /i/n ++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Hung, Bohr-Ran

2015-01-01

This study proposes a two-photomask process for fabricating amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity. PMID:28788026

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2015-04-01

Full Text Available This study proposes a two-photomask process for fabricating amorphous indium–gallium–zinc oxide (a-IGZO thin-film transistors (TFTs that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Self-assisted GaAs nanowires with selectable number density on Silicon without oxide layer

International Nuclear Information System (INIS)

Bietti, S; Somaschini, C; Esposito, L; Sanguinetti, S; Frigeri, C; Fedorov, A; Geelhaar, L

2014-01-01

We present the growth of self-assisted GaAs nanowires (NWs) with selectable number density on bare Si(1 1 1), not covered by the silicon oxide. We determine the number density of the NWs by initially self-assembling GaAs islands on whose top a single NW is nucleated. The number density of the initial GaAs base islands can be tuned by droplet epitaxy and the same degree of control is then transferred to the NWs. This procedure is completely performed during a single growth in an ultra-high vacuum environment and requires neither an oxide layer covering the substrate, nor any pre-patterning technique. (paper)

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

Science.gov (United States)

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Intradomain phase transitions in flexible block copolymers with self-aligning segments

Science.gov (United States)

Burke, Christopher J.; Grason, Gregory M.

2018-05-01

We study a model of flexible block copolymers (BCPs) in which there is an enlthalpic preference for orientational order, or local alignment, among like-block segments. We describe a generalization of the self-consistent field theory of flexible BCPs to include inter-segment orientational interactions via a Landau-de Gennes free energy associated with a polar or nematic order parameter for segments of one component of a diblock copolymer. We study the equilibrium states of this model numerically, using a pseudo-spectral approach to solve for chain conformation statistics in the presence of a self-consistent torque generated by inter-segment alignment forces. Applying this theory to the structure of lamellar domains composed of symmetric diblocks possessing a single block of "self-aligning" polar segments, we show the emergence of spatially complex segment order parameters (segment director fields) within a given lamellar domain. Because BCP phase separation gives rise to spatially inhomogeneous orientation order of segments even in the absence of explicit intra-segment aligning forces, the director fields of BCPs, as well as thermodynamics of lamellar domain formation, exhibit a highly non-linear dependence on both the inter-block segregation (χN) and the enthalpy of alignment (ɛ). Specifically, we predict the stability of new phases of lamellar order in which distinct regions of alignment coexist within the single mesodomain and spontaneously break the symmetries of the lamella (or smectic) pattern of composition in the melt via in-plane tilt of the director in the centers of the like-composition domains. We further show that, in analogy to Freedericksz transition confined nematics, the elastic costs to reorient segments within the domain, as described by the Frank elasticity of the director, increase the threshold value ɛ needed to induce this intra-domain phase transition.

Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide

International Nuclear Information System (INIS)

Qian Cong; Zhang Zhengxuan; Zhang Feng; Lin Chenglu

2008-01-01

In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si + and then annealed in N 2 , and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift ΔV th than B transistors under X-ray total close irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced ΔV th for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photo-luminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift. (authors)

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

Science.gov (United States)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Control rod housing alignment apparatus

International Nuclear Information System (INIS)

Dixon, R.C.; Deaver, G.A.; Punches, J.R.; Singleton, G.E.; Erbes, J.G.; Offer, H.P.

1991-01-01

This paper discusses an alignment device for precisely locating the position of the top of a control rod drive housing from an overlying and corresponding hole and alignment pin in a core plate within a boiling water nuclear reactor. It includes a shaft, the shaft having a length sufficient to extend from the vicinity of the top of the control rod drive housing up to and through the hole in the core plate; means for registering the top of the shaft to the hole in the core plate, the registering means including means for registering with an alignment pin in the core plate adjacent the hole

Analysis of chemical bond states and electrical properties of stacked AlON/HfO{sub 2} gate oxides formed by using a layer-by-layer technique

Energy Technology Data Exchange (ETDEWEB)

Choi, Wonjoon; Lee, Jonghyun; Yang, Jungyup; Kim, Chaeok; Hong, Jinpyo; Nahm, Tschanguh; Byun, Byungsub; Kim, Moseok [Hanyang University, Seoul (Korea, Republic of)

2006-06-15

Stacked AlON/HfO{sub 2} thin films for gate oxides in metal-oxide-semiconductor devices are successfully prepared on Si substrates by utilizing a layer-by-layer technique integrated with an off-axis RF remote plasma sputtering process at room temperature. This off-axis structure is designed to improve the uniformity and the quality of gate oxide films. Also, a layer-by-layer technique is used to control the interface layer between the gate oxide and the Si substrate. The electrical properties of our stacked films are characterized by using capacitance versus voltage and leakage current versus voltage measurements. The stacked AlON/HfO{sub 2} gate oxide exhibits a low leakage current of about 10{sup -6} A/cm{sup 2} and a high dielectric constant value of 14.26 by effectively suppressing the interface layer between gate oxide and Si substrate. In addition, the chemical bond states and the optimum thickness of each AlON and HfO{sub 2} thin film are analyzed using X-ray photoemission spectroscopy and transmission electron microscopy measurement.

Laser micro-machining of hydrophobic-hydrophilic patterns for fluid driven self-alignment in micro-assembly

NARCIS (Netherlands)

Römer, Gerardus Richardus, Bernardus, Engelina; Jorritsma, Mark; Arnaldo del Cerro, D.; Chang, Bo; Liimatainen, Ville; Zhou, Quan; Huis in 't Veld, Bert

2011-01-01

Fluid driven self-alignment is a low cost alternative to fast but relatively inaccurate robotic pickand-place assembly of micro-fabricated components. This fluidic self-alignment technique relies on a hydrophobic-hydrophilic pattern on the surface of the receiving substrate, which confines a fluid

In-Flight Self-Alignment Method Aided by Geomagnetism for Moving Basement of Guided Munitions

Directory of Open Access Journals (Sweden)

Shuang-biao Zhang

2015-01-01

Full Text Available Due to power-after-launch mode of guided munitions of high rolling speed, initial attitude of munitions cannot be determined accurately, and this makes it difficult for navigation and control system to work effectively and validly. An in-flight self-alignment method aided by geomagnetism that includes a fast in-flight coarse alignment method and an in-flight alignment model based on Kalman theory is proposed in this paper. Firstly a fast in-flight coarse alignment method is developed by using gyros, magnetic sensors, and trajectory angles. Then, an in-flight alignment model is derived by investigation of the measurement errors and attitude errors, which regards attitude errors as state variables and geomagnetic components in navigation frame as observed variables. Finally, fight data of a spinning projectile is used to verify the performance of the in-flight self-alignment method. The satisfying results show that (1 the precision of coarse alignment can attain below 5°; (2 the attitude errors by in-flight alignment model converge to 24′ at early of the latter half of the flight; (3 the in-flight alignment model based on Kalman theory has better adaptability, and show satisfying performance.

Formation of p-n-p junction with ionic liquid gate in graphene

International Nuclear Information System (INIS)

He, Xin; Tang, Ning; Duan, Junxi; Zhang, Yuewei; Lu, Fangchao; Xu, Fujun; Yang, Xuelin; Gao, Li; Wang, Xinqiang; Shen, Bo; Ge, Weikun

2014-01-01

Ionic liquid gating is a technique which is much more efficient than solid gating to tune carrier density. To observe the electronic properties of such a highly doped graphene device, a top gate made of ionic liquid has been used. By sweeping both the top and back gate voltage, a p-n-p junction has been created. The mechanism of forming the p-n-p junction has been discussed. Tuning the carrier density by ionic liquid gate can be an efficient method to be used in flexible electronics

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

Science.gov (United States)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

ALD TiO x as a top-gate dielectric and passivation layer for InGaZnO115 ISFETs

Science.gov (United States)

Pavlidis, S.; Bayraktaroglu, B.; Leedy, K.; Henderson, W.; Vogel, E.; Brand, O.

2017-11-01

The suitability of atomic layer deposited (ALD) titanium oxide (TiO x ) as a top gate dielectric and passivation layer for indium gallium zinc oxide (InGaZnO115) ion sensitive field effect transistors (ISFETs) is investigated. TiO x is an attractive barrier material, but reports of its use for InGaZnO thin film transistor (TFT) passivation have been conflicting thus far. In this work, it is found that the passivated TFT’s behavior depends on the TiO x deposition temperature, affecting critical device characteristics such as threshold voltage, field-effect mobility and sub-threshold swing. An O2 annealing step is required to recover TFT performance post passivation. It is also observed that the positive bias stress response of the passivated TFTs improves compared the original bare device. Secondary ion mass spectroscopy excludes the effects of hydrogen doping and inter-diffusion as sources of the temperature-dependent performance change, therefore indicating that oxygen gettering induced by TiO x passivation is the likely source of oxygen vacancies and, consequently, carriers in the InGaZnO film. It is also shown that potentiometric sensing using ALD TiO x exhibits a near Nernstian response to pH change, as well as minimizes V TH drift in TiO x passivated InGaZnO TFTs immersed in an acidic liquid. These results add to the understanding of InGaZnO passivation effects and underscore the potential for low-temperature fabricated InGaZnO ISFETs to be used as high-performance mobile chemical sensors.

A double-gate double-feedback JFET charge-sensitive preamplifier

International Nuclear Information System (INIS)

Fazzi, A.

1996-01-01

A new charge-sensitive preamplifier (CSP) without a physical resistance in the feedback is presented. The input device has to be a double-gate JFET. In this new preamplifier configuration the feedback capacitor is continuously discharged by means of a second DC current feedback loop closed through the bottom gate of the input JFET. The top gate-channel junction works as usual in reverse bias, the bottom gate-channel is forward biased. A fraction of the current injected by the bottom gate reaches the top gate discharging the feedback capacitor. The n-channel double-gate JFET is considered from the viewpoint of the restoring action as a parasitic p-n-p ''transversal'' bipolar junction transistor. The new preamplifier is also suited for detectors operating at room temperature with leakage current which may vary with time. The DC behaviour and the dynamic behaviour of the circuit is analyzed and new measurements presented. (orig.)

Self-aligning fixture used in lathe chuck jaw refacing

Science.gov (United States)

Linn, C. C.

1965-01-01

Self-aligning tool positions and rigidly holds lathe chuck jaws for refacing and truing of the clamping surface. The jaws clamp the fixture in the manner of clamping a workpiece. The fixture can be modified to accommodate four-jawed checks.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

Science.gov (United States)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

2016-11-30

Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

Terahertz modulation based on surface plasmon resonance by self-gated graphene

Science.gov (United States)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

Interfacial Engineering of Nanoporous Architectures in Ga2O3 Film toward Self-Aligned Tubular Nanostructure with an Enhanced Photocatalytic Activity on Water Splitting.

Science.gov (United States)

Shrestha, Nabeen K; Bui, Hoa Thi; Lee, Taegweon; Noh, Yong-Young

2018-04-17

The present work demonstrates the formation of self-aligned nanoporous architecture of gallium oxide by anodization of gallium metal film controlled at -15 °C in aqueous electrolyte consisting of phosphoric acid. SEM examination of the anodized film reveals that by adding ethylene glycol to the electrolyte and optimizing the ratio of phosphoric acid and water, chemical etching at the oxide/electrolyte interfaces can be controlled, leading to the formation of aligned nanotubular oxide structures with closed bottom. XPS analysis confirms the chemical composition of the oxide film as Ga 2 O 3 . Further, XRD and SAED examination reveals that the as-synthesized nanotubular structure is amorphous, and can be crystallized to β-Ga 2 O 3 phase by annealing the film at 600 °C. The nanotubular structured film, when used as photoanode for photoelectrochemical splitting of water, achieved a higher photocurrent of about two folds than that of the nanoporous film, demonstrating the rewarding effect of the nanotubular structure. In addition, the work also demonstrates the formation of highly organized nonporous Ga 2 O 3 structure on a nonconducting glass substrate coated with thin film of Ga-metal, highlighting that the current approach can be extended for the formation of self-organized nanoporous Ga 2 O 3 thin film even on nonconducting flexible substrates.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Gate-controlled current and inelastic electron tunneling spectrum of benzene: a self-consistent study.

Science.gov (United States)

Liang, Y Y; Chen, H; Mizuseki, H; Kawazoe, Y

2011-04-14

We use density functional theory based nonequilibrium Green's function to self-consistently study the current through the 1,4-benzenedithiol (BDT). The elastic and inelastic tunneling properties through this Au-BDT-Au molecular junction are simulated, respectively. For the elastic tunneling case, it is found that the current through the tilted molecule can be modulated effectively by the external gate field, which is perpendicular to the phenyl ring. The gate voltage amplification comes from the modulation of the interaction between the electrodes and the molecules in the junctions. For the inelastic case, the electron tunneling scattered by the molecular vibrational modes is considered within the self-consistent Born approximation scheme, and the inelastic electron tunneling spectrum is calculated.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Comparison of recessed gate-head structures on normally-off AlGaN/GaN high-electron-mobility transistor performance.

Science.gov (United States)

Khan, Mansoor Ali; Heo, Jun-Woo; Kim, Hyun-Seok; Park, Hyun-Chang

2014-11-01

In this work, different gate-head structures have been compared in the context of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). Field-plate (FP) technology self-aligned to the gate electrode leads to various gate-head structures, most likely gamma (γF)-gate, camel (see symbol)-gate, and mushroom-shaped (T)-gate. In-depth comparison of recessed gate-head structures demonstrated that key performance metrics such as transconductance, output current, and breakdown voltage are better with the T-gate head structure. The recessed T-gate with its one arm toward the source side not only reduces the source-access resistance (R(g) +R(gs)), but also minimizes the source-side dispersion and current leakage, resulting in high transconductance (G(m)) and output current (I(DS)). At the same time, the other arm toward the drain-side reduces the drain-side dispersion and tends to distribute electric field peaks uniformly, resulting in high breakdown voltage (V(BR)). DC and RF analysis showed that the recessed T-gate FP-HEMT is a suitable candidate not only for high-frequency operation, but also for high-power applications.

Self-aligned inkjet printing of highly conducting gold electrodes with submicron resolution

Science.gov (United States)

Zhao, Ni; Chiesa, Marco; Sirringhaus, Henning; Li, Yuning; Wu, Yiliang; Ong, Beng

2007-03-01

Self-aligned printing is a recently developed bottom-up printing technique which utilizes the unique droplet motion on heterogeneous surfaces to define sub-100-nm critical features and surpasses the resolution which can commonly be achieved by direct printing by two orders of magnitude. Here we extend this method, which was originally implemented with conductive polymer inks, to fabrication of functional conductive nanostructures with gold nanoparticle ink. We also designed a configuration where the ink was printed between two lithographically defined patterns to facilitate the study of the channel formation. Channel lengths from 4μm down to 60nm were achieved by controlling the surface tension and drying time of the ink. A fluid dynamical model is presented to explain the mechanism by which the channel forms in the self-aligned printing technique. Field-effect transistors fabricated using gold self-aligned printed source-drain electrodes exhibit significantly improved output currents than those using conducting polymers. Unambiguous evidence for the submicrometer channel dimension is obtained by imaging the potential drop along the channel using scanning Kelvin probe microscopy.

Fracton pairing mechanism for unconventional superconductors: Self-assembling organic polymers and copper-oxide compounds

DEFF Research Database (Denmark)

Milovanov, A.V.; Juul Rasmussen, J.

2002-01-01

Self-assembling organic polymers and copper-oxide compounds are two classes of unconventional superconductors, whose challenging behavior does not comply with the traditional picture of Bardeen-Cooper-Schrieffer (BCS) superconductivity in regular crystals. In this paper, we propose a theoretical...... or holes) exchange fracton excitations, quantum oscillations of fractal lattices that mimic the complex microscopic organization of the unconventional superconductors. For the copper oxides, the superconducting transition temperature T-c as predicted by the fracton mechanism is of the order of similar to......150 K. We suggest that the marginal ingredient of the high-temperature superconducting phase is provided by fracton coupled holes that condensate in the conducting copper-oxygen planes owing to the intrinsic field-effect-transistor configuration of the cuprate compounds. For the gate...

Rapid shear alignment of sub-10 nm cylinder-forming block copolymer films based on thermal expansion mismatch

Science.gov (United States)

Nicaise, Samuel M.; Gadelrab, Karim R.; G, Amir Tavakkoli K.; Ross, Caroline A.; Alexander-Katz, Alfredo; Berggren, Karl K.

2018-01-01

Directed self-assembly of block copolymers (BCPs) provided by shear-stress can produce aligned sub-10 nm structures over large areas for applications in integrated circuits, next-generation data storage, and plasmonic structures. In this work, we present a fast, versatile BCP shear-alignment process based on coefficient of thermal expansion mismatch of the BCP film, a rigid top coat and a substrate. Monolayer and bilayer cylindrical microdomains of poly(styrene-b-dimethylsiloxane) aligned preferentially in-plane and orthogonal to naturally-forming or engineered cracks in the top coat film, allowing for orientation control over 1 cm2 substrates. Annealing temperatures, up to 275 °C, provided low-defect alignment up to 2 mm away from cracks for rapid (<1 min) annealing times. Finite-element simulations of the stress as a function of annealing time, annealing temperature, and distance from cracks showed that shear stress during the cooling phase of the thermal annealing was critical for the observed microdomain alignment.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

Science.gov (United States)

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

Science.gov (United States)

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Self-Heating Effects In Polysilicon Source Gated Transistors

Science.gov (United States)

Sporea, R. A.; Burridge, T.; Silva, S. R. P.

2015-01-01

Source-gated transistors (SGTs) are thin-film devices which rely on a potential barrier at the source to achieve high gain, tolerance to fabrication variability, and low series voltage drop, relevant to a multitude of energy-efficient, large-area, cost effective applications. The current through the reverse-biased source barrier has a potentially high positive temperature coefficient, which may lead to undesirable thermal runaway effects and even device failure through self-heating. Using numerical simulations we show that, even in highly thermally-confined scenarios and at high current levels, self-heating is insufficient to compromise device integrity. Performance is minimally affected through a modest increase in output conductance, which may limit the maximum attainable gain. Measurements on polysilicon devices confirm the simulated results, with even smaller penalties in performance, largely due to improved heat dissipation through metal contacts. We conclude that SGTs can be reliably used for high gain, power efficient analog and digital circuits without significant performance impact due to self-heating. This further demonstrates the robustness of SGTs. PMID:26351099

Defense.gov Special Report: Travels with Gates - October 2010

Science.gov (United States)

- Secretary of State Hillary Rodham Clinton and Defense Secretary Robert M. Gates expressed support for the Travels Top Story Clinton, Gates Voice Support For Afghan Reconciliation BRUSSELS, Belgium, Oct. 14, 2010

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

International Nuclear Information System (INIS)

Miyoshi, Makoto; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

2015-01-01

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO 2 /Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO 2 /Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO 2 /Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm 2 /V s for electrons and 880 cm 2 /V s for holes, respectively

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Miyoshi, Makoto, E-mail: miyoshi.makoto@nitech.ac.jp; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Mizuno, Masaya [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Soga, Tetsuo [Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan)

2015-08-17

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

A novel micromachined shadow mask system with self-alignment and gap control capability

International Nuclear Information System (INIS)

Hong, Jung Moo; Zou Jun

2008-01-01

We present a novel micromachined shadow mask system, which is capable of accurate self-alignment and mask-substrate gap control. The shadow mask system consists of a silicon shadow mask and a silicon carrier wafer with pyramidal cavities fabricated with bulk micromachining. Self-alignment and gap control of the shadow mask and the fabrication substrate can readily be achieved by using matching pairs of pyramidal cavities and steel spheres placed between. The layer-to-layer alignment accuracy of the new shadow mask system has been experimentally characterized and verified using both optical and atomic force microscopic measurements. As an application of this new shadow mask system, an organic thin-film transistor (OTFT) using pentacene as the semiconductor layer has been successfully fabricated and tested

Functional imaging of murine hearts using accelerated self-gated UTE cine MRI.

Science.gov (United States)

Motaal, Abdallah G; Noorman, Nils; de Graaf, Wolter L; Hoerr, Verena; Florack, Luc M J; Nicolay, Klaas; Strijkers, Gustav J

2015-01-01

We introduce a fast protocol for ultra-short echo time (UTE) Cine magnetic resonance imaging (MRI) of the beating murine heart. The sequence involves a self-gated UTE with golden-angle radial acquisition and compressed sensing reconstruction. The self-gated acquisition is performed asynchronously with the heartbeat, resulting in a randomly undersampled kt-space that facilitates compressed sensing reconstruction. The sequence was tested in 4 healthy rats and 4 rats with chronic myocardial infarction, approximately 2 months after surgery. As a control, a non-accelerated self-gated multi-slice FLASH sequence with an echo time (TE) of 2.76 ms, 4.5 signal averages, a matrix of 192 × 192, and an acquisition time of 2 min 34 s per slice was used to obtain Cine MRI with 15 frames per heartbeat. Non-accelerated UTE MRI was performed with TE = 0.29 ms, a reconstruction matrix of 192 × 192, and an acquisition time of 3 min 47 s per slice for 3.5 averages. Accelerated imaging with 2×, 4× and 5× undersampled kt-space data was performed with 1 min, 30 and 15 s acquisitions, respectively. UTE Cine images up to 5× undersampled kt-space data could be successfully reconstructed using a compressed sensing algorithm. In contrast to the FLASH Cine images, flow artifacts in the UTE images were nearly absent due to the short echo time, simplifying segmentation of the left ventricular (LV) lumen. LV functional parameters derived from the control and the accelerated Cine movies were statistically identical.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Vertically aligned ZnO nanorods via self-assembled spray pyrolyzed nanoparticles for dye-sensitized solar cells

International Nuclear Information System (INIS)

Dwivedi, Charu; Dutta, V

2012-01-01

Well-aligned zinc oxide (ZnO) nanorods are fabricated on indium-tin-oxide (ITO) coated glass substrates via self-assembly of ZnO nanoparticles created using continuous spray pyrolysis (CoSP) technique. The method involves pre-treatment by dip-coating the substrate with a solution comprising of zinc salt for creating a seed layer, and then spray-pyrolyzed ZnO nanoparticles self-assemble on the pre-treated substrate. The effect of the substrate pre-treatment and the deposition time (t dep ) of nanoparticles is investigated. The results show that the substrate pre-treatment influences the growth of ZnO nanorods which are absent without the pre-treatment. Nanoparticle collection and nanorod growth on different substrates are done simultaneously. The thin films of as-grown nanorods are used as photoelectrode materials to fabricate dye-sensitized solar cells (DSSCs) and the effect of nanorods grown for different times has been studied. The best performance with this cell structure is found for the layer with t dep =15 min, which showed a conversion efficiency of 1.77% for the cell area of 0.25 cm 2

Tungsten oxide proton conducting films for low-voltage transparent oxide-based thin-film transistors

International Nuclear Information System (INIS)

Zhang, Hongliang; Wan, Qing; Wan, Changjin; Wu, Guodong; Zhu, Liqiang

2013-01-01

Tungsten oxide (WO x ) electrolyte films deposited by reactive magnetron sputtering showed a high room temperature proton conductivity of 1.38 × 10 −4 S/cm with a relative humidity of 60%. Low-voltage transparent W-doped indium-zinc-oxide thin-film transistors gated by WO x -based electrolytes were self-assembled on glass substrates by one mask diffraction method. Enhancement mode operation with a large current on/off ratio of 4.7 × 10 6 , a low subthreshold swing of 108 mV/decade, and a high field-effect mobility 42.6 cm 2 /V s was realized. Our results demonstrated that WO x -based proton conducting films were promising gate dielectric candidates for portable low-voltage oxide-based devices.

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

Energy Technology Data Exchange (ETDEWEB)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars [Solid State Physics, Nanometer Structure Consortium, Lund University, Box 118, S-221 00 Lund (Sweden)

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Self-aligned nanocrystalline ZnO hexagons by facile solid-state and co-precipitation route

International Nuclear Information System (INIS)

Thorat, J. H.; Kanade, K. G.; Nikam, L. K.; Chaudhari, P. D.; Panmand, R. P.; Kale, B. B.

2012-01-01

In this study, we report the synthesis of well-aligned nanocrystalline hexagonal zinc oxide (ZnO) nanoparticles by facile solid-state and co-precipitation method. The co-precipitation reactions were performed using aqueous and ethylene glycol (EG) medium using zinc acetate and adipic acid to obtain zinc adipate and further decomposition at 450 °C to confer nanocrystalline ZnO hexagons. XRD shows the hexagonal wurtzite structure of the ZnO. Thermal study reveals complete formation of ZnO at 430 °C in case of solid-state method, whereas in case of co-precipitation method complete formation was observed at 400 °C. Field emission scanning electron microscope shows spherical morphology for ZnO synthesized by solid-state method. The aqueous-mediated ZnO by co-precipitation method shows rod-like morphology. These rods are formed via self assembling of spherical nanoparticles, however, uniformly dispersed spherical crystallites were seen in EG-mediated ZnO. Transmission electron microscope (TEM) investigations clearly show well aligned and highly crystalline transparent and thin hexagonal ZnO. The particle size was measured using TEM and was observed to be 50–60 nm in case of solid-state method and aqueous-mediated co-precipitation method, while 25–50 nm in case of EG-mediated co-precipitation method. UV absorption spectra showed sharp absorption peaks with a blue shift for EG-mediated ZnO, which demonstrate the mono-dispersed lower particle size. The band gap of the ZnO was observed to be 3.4 eV which is higher than the bulk, implies nanocrystalline nature of the ZnO. The photoluminescence studies clearly indicate the strong violet and weak blue emission in ZnO nanoparticles which is quite unique. The process investigated may be useful to synthesize other oxide semiconductors and transition metal oxides.

Self-aligned nanocrystalline ZnO hexagons by facile solid-state and co-precipitation route

Energy Technology Data Exchange (ETDEWEB)

Thorat, J. H. [Mahatma Phule College, Department of Chemistry (India); Kanade, K. G. [Annasaheb Awate College (India); Nikam, L. K. [B.G. College (India); Chaudhari, P. D.; Panmand, R. P.; Kale, B. B., E-mail: kbbb1@yahoo.com [Center for Materials for Electronics Technology (C-MET) (India)

2012-02-15

In this study, we report the synthesis of well-aligned nanocrystalline hexagonal zinc oxide (ZnO) nanoparticles by facile solid-state and co-precipitation method. The co-precipitation reactions were performed using aqueous and ethylene glycol (EG) medium using zinc acetate and adipic acid to obtain zinc adipate and further decomposition at 450 Degree-Sign C to confer nanocrystalline ZnO hexagons. XRD shows the hexagonal wurtzite structure of the ZnO. Thermal study reveals complete formation of ZnO at 430 Degree-Sign C in case of solid-state method, whereas in case of co-precipitation method complete formation was observed at 400 Degree-Sign C. Field emission scanning electron microscope shows spherical morphology for ZnO synthesized by solid-state method. The aqueous-mediated ZnO by co-precipitation method shows rod-like morphology. These rods are formed via self assembling of spherical nanoparticles, however, uniformly dispersed spherical crystallites were seen in EG-mediated ZnO. Transmission electron microscope (TEM) investigations clearly show well aligned and highly crystalline transparent and thin hexagonal ZnO. The particle size was measured using TEM and was observed to be 50-60 nm in case of solid-state method and aqueous-mediated co-precipitation method, while 25-50 nm in case of EG-mediated co-precipitation method. UV absorption spectra showed sharp absorption peaks with a blue shift for EG-mediated ZnO, which demonstrate the mono-dispersed lower particle size. The band gap of the ZnO was observed to be 3.4 eV which is higher than the bulk, implies nanocrystalline nature of the ZnO. The photoluminescence studies clearly indicate the strong violet and weak blue emission in ZnO nanoparticles which is quite unique. The process investigated may be useful to synthesize other oxide semiconductors and transition metal oxides.

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

International Nuclear Information System (INIS)

Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

2011-01-01

An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

Understanding Interfacial Alignment in Solution Coated Conjugated Polymer Thin Films

International Nuclear Information System (INIS)

Qu, Ge; Zhao, Xikang; Newbloom, Gregory M.; Zhang, Fengjiao; Mohammadi, Erfan

2017-01-01

Domain alignment in conjugated polymer thin films can significantly enhance charge carrier mobility. However, the alignment mechanism during meniscus-guided solution coating remains unclear. Furthermore, interfacial alignment has been rarely studied despite its direct relevance and critical importance to charge transport. In this study, we uncover a significantly higher degree of alignment at the top interface of solution coated thin films, using a donor–acceptor conjugated polymer, poly(diketopyrrolopyrrole-co-thiopheneco- thieno[3,2-b]thiophene-co-thiophene) (DPP2T-TT), as the model system. At the molecular level, we observe in-plane π–π stacking anisotropy of up to 4.8 near the top interface with the polymer backbone aligned parallel to the coating direction. The bulk of the film is only weakly aligned with the backbone oriented transverse to coating. At the mesoscale, we observe a well-defined fibril-like morphology at the top interface with the fibril long axis pointing toward the coating direction. Significantly smaller fibrils with poor orientational order are found on the bottom interface, weakly aligned orthogonal to the fibrils on the top interface. The high degree of alignment at the top interface leads to a charge transport anisotropy of up to 5.4 compared to an anisotropy close to 1 on the bottom interface. We attribute the formation of distinct interfacial morphology to the skin-layer formation associated with high Peclet number, which promotes crystallization on the top interface while suppressing it in the bulk. As a result, we further infer that the interfacial fibril alignment is driven by the extensional flow on the top interface arisen from increasing solvent evaporation rate closer to the meniscus front.

A VHF Class E DC-DC Converter with Self-Oscillating Gate Driver

DEFF Research Database (Denmark)

Andersen, Toke Meyer; Christensen, Søren K.; Knott, Arnold

2011-01-01

, is inherently resonant, and switching losses are greatly reduced by ensuring Zero Voltage Switching (ZVS) of the power semiconductor devices. A design method to ensure ZVS operation when combining the inverter, rectifier, and gate driver is provided. Several parasitic effects and their influence on converter......This paper describes the analysis and design of a DC-DC converter topology which is operational at frequencies in the Very High Frequency (VHF) band ranging from 30 MHz − 300 MHz. The presented topology, which consists of a class E inverter, class E rectifier, and self-oscillating gate driver...... operation are discussed, and measurement results of a 100 MHz prototype converter are presented and evaluated. The designed prototype converter verifies the described topology....

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

International Nuclear Information System (INIS)

Usuda, R.; Uchida, K.; Nozaki, S.

2015-01-01

Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO x film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10 11  cm −2 eV −1 by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H 2 O molecules and facilitate dissociation of the molecules into H and OH − . The OH − ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H 2 O molecules. The ionization results in the electron stimulated dissociation of H 2 O molecules and the decreased interface trap density

Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

Energy Technology Data Exchange (ETDEWEB)

Usuda, R.; Uchida, K.; Nozaki, S., E-mail: nozaki@ee.uec.ac.jp [Graduate School of Informatics and Engineering, The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu-shi, Tokyo 182-1515 (Japan)

2015-11-02

Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

The precise self-assembly of individual carbon nanotubes using magnetic capturing and fluidic alignment

Energy Technology Data Exchange (ETDEWEB)

Shim, Joon S; Rust, Michael J; Do, Jaephil; Ahn, Chong H [Department of Electrical and Computer Engineering, Microsystems and BioMEMS Laboratory, University of Cincinnati, Cincinnati, OH 45221 (United States); Yun, Yeo-Heung; Schulz, Mark J [Department of Mechanical Engineering, University of Cincinnati, 45221 (United States); Shanov, Vesselin, E-mail: chong.ahn@uc.ed [Department of Chemical and Materials Engineering, University of Cincinnati, 45221 (United States)

2009-08-12

A new method for the self-assembly of a carbon nanotube (CNT) using magnetic capturing and fluidic alignment has been developed and characterized in this work. In this new method, the residual iron (Fe) catalyst positioned at one end of the CNT was utilized as a self-assembly driver to attract and position the CNT, while the assembled CNT was aligned by the shear force induced from the fluid flow through the assembly channel. The self-assembly procedures were successfully developed and the electrical properties of the assembled multi-walled carbon nanotube (MWNT) and single-walled carbon nanotube (SWNT) were fully characterized. The new assembly method developed in this work shows its feasibility for the precise self-assembly of parallel CNTs for electronic devices and nanobiosensors.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Digital power and performance analysis of inkjet printed ring oscillators based on electrolyte-gated oxide electronics

Science.gov (United States)

Cadilha Marques, Gabriel; Garlapati, Suresh Kumar; Dehm, Simone; Dasgupta, Subho; Hahn, Horst; Tahoori, Mehdi; Aghassi-Hagmann, Jasmin

2017-09-01

Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ≤2 V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ˜4 and 2.3 ms propagation delay time at 1 V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6 V with a frequency of ˜255 Hz and can reach frequencies up to ˜350 Hz at 2 V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits.

Measurement of top quark and W boson polarisation observables with t-channel single-top-quark events in the ATLAS experiment.

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00288626

This thesis presents two studies, one related with the alignment of the ATLAS Inner Detector tracking system and other with the measurement of top quark and W boson polarisation observables using t-channel single-top-quark events. The first topic describes the implementation of a monitoring tool, which is used to monitor the Level 1 alignment corrections obtained in the calibration loop, as well as the use of constraints on the momentum and impact parameters biases using $Z \\rightarrow\\mu\\mu$ events on the alignment algorithms. These techniques were developed during 2012 data taking campaign and provide the most accurate description of the ATLAS Inner Detector. The second topic presents a detailed measurement of top quark and W boson polarisation observables using the 20.3 $fb^{-1}$ of data collected by the ATLAS detector at $\\sqrt{s}$ = 8 TeV. The measurement is performed using $t$-channel single top quark events and exploits the feature that the produced top quark is highly polarised along the direction of ...

Gate Engineering in SOI LDMOS for Device Reliability

Directory of Open Access Journals (Sweden)

Aanand

2016-01-01

Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

Science.gov (United States)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Self-optimizing approach for automated laser resonator alignment

Science.gov (United States)

Brecher, C.; Schmitt, R.; Loosen, P.; Guerrero, V.; Pyschny, N.; Pavim, A.; Gatej, A.

2012-02-01

Nowadays, the assembly of laser systems is dominated by manual operations, involving elaborate alignment by means of adjustable mountings. From a competition perspective, the most challenging problem in laser source manufacturing is price pressure, a result of cost competition exerted mainly from Asia. From an economical point of view, an automated assembly of laser systems defines a better approach to produce more reliable units at lower cost. However, the step from today's manual solutions towards an automated assembly requires parallel developments regarding product design, automation equipment and assembly processes. This paper introduces briefly the idea of self-optimizing technical systems as a new approach towards highly flexible automation. Technically, the work focuses on the precision assembly of laser resonators, which is one of the final and most crucial assembly steps in terms of beam quality and laser power. The paper presents a new design approach for miniaturized laser systems and new automation concepts for a robot-based precision assembly, as well as passive and active alignment methods, which are based on a self-optimizing approach. Very promising results have already been achieved, considerably reducing the duration and complexity of the laser resonator assembly. These results as well as future development perspectives are discussed.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Self-aligned photolithography for the fabrication of fully transparent high-voltage devices

Science.gov (United States)

Zhang, Yonghui; Mei, Zengxia; Huo, Wenxing; Wang, Tao; Liang, Huili; Du, Xiaolong

2018-05-01

High-voltage devices, working in the range of hundreds of volts, are indispensable elements in the driving or readout circuits for various kinds of displays, integrated microelectromechanical systems and x-ray imaging sensors. However, the device performances are found hardly uniform or repeatable due to the misalignment issue, which are extremely common for offset drain high-voltage devices. To resolve this issue, this article reports a set of self-aligned photolithography technology for the fabrication of high-voltage devices. High-performance fully-transparent high-voltage thin film transistors, diodes and logic inverters are successfully fabricated with this technology. Unlike other self-aligned routes, opaque masks are introduced on the backside of the transparent substrate to facilitate proximity exposure method. The photolithography process is simulated and analyzed with technology computer aided design simulation to explain the working principle of the proximity exposure method. The substrate thickness is found to be vital for the implementation of this technology based on both simulation and experimental results. The electrical performance of high-voltage devices is dependent on the offset length, which can be delicately modulated by changing the exposure dose. The presented self-aligned photolithography technology is proved to be feasible in high-voltage circuits, demonstrating its huge potential in practical industrial applications.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2014-08-01

Full Text Available Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV exposure and backside-lift-off (BLO schemes can not only prevent the damage when etching the source/drain (S/D electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs exhibit comparable field-effect mobility (9.5 cm2/V·s, threshold voltage (3.39 V, and subthreshold swing (0.3 V/decade. The delay time of an inverter fabricated using the proposed process was considerably decreased.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme.

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der

2014-08-11

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.

Quantitative analysis of a fault tree with priority AND gates

International Nuclear Information System (INIS)

Yuge, T.; Yanagi, S.

2008-01-01

A method for calculating the exact top event probability of a fault tree with priority AND gates and repeated basic events is proposed when the minimal cut sets are given. A priority AND gate is an AND gate where the input events must occur in a prescribed order for the occurrence of the output event. It is known that the top event probability of such a dynamic fault tree is obtained by converting the tree into an equivalent Markov model. However, this method is not realistic for a complex system model because the number of states which should be considered in the Markov analysis increases explosively as the number of basic events increases. To overcome the shortcomings of the Markov model, we propose an alternative method to obtain the top event probability in this paper. We assume that the basic events occur independently, exponentially distributed, and the component whose failure corresponds to the occurrence of the basic event is non-repairable. First, we obtain the probability of occurrence of the output event of a single priority AND gate by Markov analysis. Then, the top event probability is given by a cut set approach and the inclusion-exclusion formula. An efficient procedure to obtain the probabilities corresponding to logical products in the inclusion-exclusion formula is proposed. The logical product which is composed of two or more priority AND gates having at least one common basic event as their inputs is transformed into the sum of disjoint events which are equivalent to a priority AND gate in the procedure. Numerical examples show that our method works well for complex systems

Feasibility of self-gated isotropic radial late-phase MR imaging of the liver

Energy Technology Data Exchange (ETDEWEB)

Weiss, Jakob; Taron, Jana; Othman, Ahmed E.; Kuendel, Matthias; Martirosian, Petros; Ruff, Christer; Schraml, Christina; Nikolaou, Konstantin; Notohamiprodjo, Mike [Eberhard Karls University Tuebingen, Department of Diagnostic and Interventional Radiology, Tuebingen (Germany); Grimm, Robert [Siemens Healthcare MR, Erlangen (Germany)

2017-03-15

To evaluate feasibility of a 3D-isotropic self-gated radial volumetric interpolated breath-hold examination (VIBE) for late-phase MRI of the liver. 70 patients were included and underwent liver MRI at 1.5 T. Depending on the diagnosis, either Gd-EOB-DTPA (35 patients) or gadobutrol (35 patients) were administered. During late (gadobutrol) or hepatocyte-specific phase (Gd-EOB-DTPA), a radial prototype sequence was acquired and reconstructed using (1) self-gating with 40 % acceptance (rVIBE{sub 40}); (2) with 100 % acceptance of the data (rVIBE{sub 100}) and compared to Cartesian VIBE (cVIBE). Images were assessed qualitatively (image quality, lesion conspicuity, artefacts; 5-point Likert-scale: 5 = excellent; two independent readers) and quantitatively (coefficient-of-variation (CV); contrast-ratio) in axial and coronal reformations. In eight cases only rVIBE provided diagnostic image quality. Image quality of rVIBE{sub 40} was rated significantly superior (p < 0.05) in Gd-EOB-DTPA-enhanced and coronal reformatted examinations as compared to cVIBE. Lesion conspicuity was significantly improved (p < 0.05) in coronal reformatted Gd-EOB-DTPA-enhanced rVIBE{sub 40} in comparison to cVIBE. CV was higher in rVIBE{sub 40} as compared to rVIBE{sub 100}/cVIBE (p < 0.01). Gadobutrol-enhanced rVIBE{sub 40} and cVIBE showed higher contrast-ratios than rVIBE{sub 100} (p < 0.001), whereas no differences were found in Gd-EOB-DTPA-enhanced examinations. Self-gated 3D-isotropic rVIBE provides significantly superior image quality compared to cVIBE, especially in multiplanar reformatted and Gd-EOB-DTPA-enhanced examinations. (orig.)

Feasibility of self-gated isotropic radial late-phase MR imaging of the liver

International Nuclear Information System (INIS)

Weiss, Jakob; Taron, Jana; Othman, Ahmed E.; Kuendel, Matthias; Martirosian, Petros; Ruff, Christer; Schraml, Christina; Nikolaou, Konstantin; Notohamiprodjo, Mike; Grimm, Robert

2017-01-01

To evaluate feasibility of a 3D-isotropic self-gated radial volumetric interpolated breath-hold examination (VIBE) for late-phase MRI of the liver. 70 patients were included and underwent liver MRI at 1.5 T. Depending on the diagnosis, either Gd-EOB-DTPA (35 patients) or gadobutrol (35 patients) were administered. During late (gadobutrol) or hepatocyte-specific phase (Gd-EOB-DTPA), a radial prototype sequence was acquired and reconstructed using (1) self-gating with 40 % acceptance (rVIBE_4_0); (2) with 100 % acceptance of the data (rVIBE_1_0_0) and compared to Cartesian VIBE (cVIBE). Images were assessed qualitatively (image quality, lesion conspicuity, artefacts; 5-point Likert-scale: 5 = excellent; two independent readers) and quantitatively (coefficient-of-variation (CV); contrast-ratio) in axial and coronal reformations. In eight cases only rVIBE provided diagnostic image quality. Image quality of rVIBE_4_0 was rated significantly superior (p < 0.05) in Gd-EOB-DTPA-enhanced and coronal reformatted examinations as compared to cVIBE. Lesion conspicuity was significantly improved (p < 0.05) in coronal reformatted Gd-EOB-DTPA-enhanced rVIBE_4_0 in comparison to cVIBE. CV was higher in rVIBE_4_0 as compared to rVIBE_1_0_0/cVIBE (p < 0.01). Gadobutrol-enhanced rVIBE_4_0 and cVIBE showed higher contrast-ratios than rVIBE_1_0_0 (p < 0.001), whereas no differences were found in Gd-EOB-DTPA-enhanced examinations. Self-gated 3D-isotropic rVIBE provides significantly superior image quality compared to cVIBE, especially in multiplanar reformatted and Gd-EOB-DTPA-enhanced examinations. (orig.)

A high performance gate drive for large gate turn off thyristors

Energy Technology Data Exchange (ETDEWEB)

Szilagyi, C.P.

1993-01-01

Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

High-κ gate dielectrics: Current status and materials properties considerations

Science.gov (United States)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Background suppression for a top quark mass measurement in the lepton+jets t anti t decay channel and alignment of the ATLAS silicon detectors with cosmic rays

International Nuclear Information System (INIS)

Goettfert, Tobias

2010-01-01

The investigation of top quark properties will be amongst the first measurements of observables of the Standard Model of particle physics at the Large Hadron Collider. This thesis deals with the suppression of background sources contributing to the event sample used for the determination of the top quark mass. Several techniques to reduce the contamination of the selected sample with events from W+jets production and combinatorial background from wrong jet associations are evaluated. The usage of the jet merging scales of a k T jet algorithm as event shapes is laid out and a multivariate technique (Fisher discriminant) is applied to discriminate signal from physics background. Several kinematic variables are reviewed upon their capability to suppress wrong jet associations. The second part presents the achievements on the alignment of the silicon part of the Inner Detector of the ATLAS experiment. A well-aligned tracking detector will be crucial for measurements that involve particle trajectories, e.g. for reliably identifying b-quark jets. Around 700,000 tracks from cosmic ray muons are used to infer the alignment of all silicon modules of ATLAS using the track-based local χ 2 alignment algorithm. Various additions to the method that deal with the peculiarities of alignment with cosmic rays are developed and presented. The achieved alignment precision is evaluated and compared to previous results. (orig.)

Background suppression for a top quark mass measurement in the lepton+jets t anti t decay channel and alignment of the ATLAS silicon detectors with cosmic rays

Energy Technology Data Exchange (ETDEWEB)

Goettfert, Tobias

2010-01-21

The investigation of top quark properties will be amongst the first measurements of observables of the Standard Model of particle physics at the Large Hadron Collider. This thesis deals with the suppression of background sources contributing to the event sample used for the determination of the top quark mass. Several techniques to reduce the contamination of the selected sample with events from W+jets production and combinatorial background from wrong jet associations are evaluated. The usage of the jet merging scales of a k{sub T} jet algorithm as event shapes is laid out and a multivariate technique (Fisher discriminant) is applied to discriminate signal from physics background. Several kinematic variables are reviewed upon their capability to suppress wrong jet associations. The second part presents the achievements on the alignment of the silicon part of the Inner Detector of the ATLAS experiment. A well-aligned tracking detector will be crucial for measurements that involve particle trajectories, e.g. for reliably identifying b-quark jets. Around 700,000 tracks from cosmic ray muons are used to infer the alignment of all silicon modules of ATLAS using the track-based local {chi}{sup 2} alignment algorithm. Various additions to the method that deal with the peculiarities of alignment with cosmic rays are developed and presented. The achieved alignment precision is evaluated and compared to previous results. (orig.)

Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning

Science.gov (United States)

Raley, Angélique; Lee, Joe; Smith, Jeffrey T.; Sun, Xinghua; Farrell, Richard A.; Shearer, Jeffrey; Xu, Yongan; Ko, Akiteru; Metz, Andrew W.; Biolsi, Peter; Devilliers, Anton; Arnold, John; Felix, Nelson

2018-04-01

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

Tuning the electronic properties of gated multilayer phosphorene: A self-consistent tight-binding study

Science.gov (United States)

Li, L. L.; Partoens, B.; Peeters, F. M.

2018-04-01

By taking account of the electric-field-induced charge screening, a self-consistent calculation within the framework of the tight-binding approach is employed to obtain the electronic band structure of gated multilayer phosphorene and the charge densities on the different phosphorene layers. We find charge density and screening anomalies in single-gated multilayer phosphorene and electron-hole bilayers in dual-gated multilayer phosphorene. Due to the unique puckered lattice structure, both intralayer and interlayer charge screenings are important in gated multilayer phosphorene. We find that the electric-field tuning of the band structure of multilayer phosphorene is distinctively different in the presence and absence of charge screening. For instance, it is shown that the unscreened band gap of multilayer phosphorene decreases dramatically with increasing electric-field strength. However, in the presence of charge screening, the magnitude of this band-gap decrease is significantly reduced and the reduction depends strongly on the number of phosphorene layers. Our theoretical results of the band-gap tuning are compared with recent experiments and good agreement is found.

Characteristics and infl uence factors of mold fi lling process in permanent mold with a slot gating system

Directory of Open Access Journals (Sweden)

Chen Changjun

2009-11-01

Full Text Available The main problems caused by improper gating are entrained aluminum oxide fi lms and entrapped gas. In this study, the slot gating system is employed to improve mold fi lling behavior and therefore, to improve the quality of aluminum castings produced in permanent molds. An equipment as well as operation procedures for real-time X-ray radiography of molten aluminum fl owing into permanent molds have been developed. Graphite molds transparent to X-rays are utilized which make it possible to observe the fl ow pattern through a number of vertically oriented gating systems. The investigation discovers that there are many infl uencing factors on the mold fi lling process. This paper focuses its research on some of the factors, such as the dimensions of the vertical riser and slot thickness, as well as roughness of the coating layer. The results indicate that molten metal can smoothly fi ll into casting cavity with a proper slot gating system. A bigger vertical riser, proper slot thickness and rougher coating can provide not only a better mold fi lling pattern, but also hot melt into the top of the cavity. A proper temperature gradient is obtainable, higher at the bottom and lower at the top of the casting cavity, which is in favor of feeding during casting solidifi cation.

Electrostatic control of the dynamics of lipid bilayer self-spreading using a nanogap gate

International Nuclear Information System (INIS)

Kashimura, Y; Sumitomo, K; Furukawa, K

2014-01-01

The electrostatic control of lipid bilayer self-spreading was investigated using a device equipped with a nanogap gate. A series of mixtures containing negatively charged and uncharged lipids were employed to tune the charge of a membrane. We found that when a voltage is applied on a lipid bilayer passing through a nanogap, the effect of a voltage application on the dynamics depended largely on the charge of the membrane. For rich charged lipid compositions (>10 mol%), the self-spreading was electrostatically controlled applying an electric field to the nanogap. The origin of the behaviour is the electrostatic trapping of charged lipids. The trapped lipids close the nanogap gate, thus preventing any lipid molecules from passing through it. For poor charged lipid compositions (∼1 mol%), no electrostatic trapping occurred even when a lipid bilayer reached the nanogap. Instead, we observed the cessation of self-spreading after a sufficient post-passage time interval, indicating that the translational flow force of self-spreading overcomes the trapping force. For uncharged lipid compositions, there was no electrostatic trapping throughout the measurement. The results suggest that the lipid charge plays a vital role in the electrostatic control mechanism and allow us to control lipid bilayer formation both spatially and temporally. (paper)

Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

International Nuclear Information System (INIS)

Nichau, Alexander

2013-01-01

. A lower limit found was EOT=5 Aa for Al doping inside TiN. The doping of TiN on LaLuO 3 is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO 2 /TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO 2 improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO 2 /TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.

Fabrication of Vertically Aligned Carbon Nanotube or Zinc Oxide Nanorod Arrays for Optical Diffraction Gratings.

Science.gov (United States)

Kim, Jeong; Kim, Sun Il; Cho, Seong-Ho; Hwang, Sungwoo; Lee, Young Hee; Hur, Jaehyun

2015-11-01

We report on new fabrication methods for a transparent, hierarchical, and patterned electrode comprised of either carbon nanotubes or zinc oxide nanorods. Vertically aligned carbon nanotubes or zinc oxide nanorod arrays were fabricated by either chemical vapor deposition or hydrothermal growth, in combination with photolithography. A transparent conductive graphene layer or zinc oxide seed layer was employed as the transparent electrode. On the patterned surface defined using photoresist, the vertically grown carbon nanotubes or zinc oxides could produce a concentrated electric field under applied DC voltage. This periodic electric field was used to align liquid crystal molecules in localized areas within the optical cell, effectively modulating the refractive index. Depending on the material and morphology of these patterned electrodes, the diffraction efficiency presented different behavior. From this study, we established the relationship between the hierarchical structure of the different electrodes and their efficiency for modulating the refractive index. We believe that this study will pave a new path for future optoelectronic applications.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

Science.gov (United States)

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

Directory of Open Access Journals (Sweden)

Mitsumasa Koyanagi

2011-02-01

Full Text Available New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D and hetero integration of complementary metal-oxide semiconductors (CMOS and microelectromechanical systems (MEMS. By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

Structural hierarchy in flow-aligned hexagonally self-organized microphases with parallel polyelectrolytic structures

NARCIS (Netherlands)

Ruotsalainen, T; Torkkeli, M; Serimaa, R; Makela, T; Maki-Ontto, R; Ruokolainen, J; ten Brinke, G; Ikkala, O; Mäkelä, Tapio; Mäki-Ontto, Riikka

2003-01-01

We report a novel structural hierarchy where a flow-aligned hexagonal self-organized structure is combined with a polyelectrolytic self-organization on a smaller length scale and where the two structures are mutually parallel. Polystyrene-block-poly(4-vinylpyridine) (PS-block-P4VP) is selected with

Synchrotron X-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

International Nuclear Information System (INIS)

Tanaka, Yuusuke; Tanabe, Akira; Suzuki, Katsumi

1998-01-01

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6,000 mJ/cm 2

Mild performic acid oxidation enhances chromatographic and top down mass spectrometric analyses of histones.

Science.gov (United States)

Pesavento, James J; Garcia, Benjamin A; Streeky, James A; Kelleher, Neil L; Mizzen, Craig A

2007-09-01

Recent developments in top down mass spectrometry have enabled closely related histone variants and their modified forms to be identified and quantitated with unprecedented precision, facilitating efforts to better understand how histones contribute to the epigenetic regulation of gene transcription and other nuclear processes. It is therefore crucial that intact MS profiles accurately reflect the levels of variants and modified forms present in a given cell type or cell state for the full benefit of such efforts to be realized. Here we show that partial oxidation of Met and Cys residues in histone samples prepared by conventional methods, together with oxidation that can accrue during storage or during chip-based automated nanoflow electrospray ionization, confounds MS analysis by altering the intact MS profile as well as hindering posttranslational modification localization after MS/MS. We also describe an optimized performic acid oxidation procedure that circumvents these problems without catalyzing additional oxidations or altering the levels of posttranslational modifications common in histones. MS and MS/MS of HeLa cell core histones confirmed that Met and Cys were the only residues oxidized and that complete oxidation restored true intact abundance ratios and significantly enhanced MS/MS data quality. This allowed for the unequivocal detection, at the intact molecule level, of novel combinatorially modified forms of H4 that would have been missed otherwise. Oxidation also enhanced the separation of human core histones by reverse phase chromatography and decreased the levels of salt-adducted forms observed in ESI-FTMS. This method represents a simple and easily automated means for enhancing the accuracy and sensitivity of top down analyses of combinatorially modified forms of histones that may also be of benefit for top down or bottom up analyses of other proteins.

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Energy Technology Data Exchange (ETDEWEB)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio [Consiglio Nazionale delle Ricerche-Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale 95121 Catania (Italy)

2016-07-04

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

Heavy-ion-induced, gate-rupture in power MOSFETs

International Nuclear Information System (INIS)

Fischer, T.A.

1987-01-01

A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods

Rat Aquaporin-5 Is pH-Gated Induced by Phosphorylation and Is Implicated in Oxidative Stress

Directory of Open Access Journals (Sweden)

Claudia Rodrigues

2016-12-01

Full Text Available Aquaporin-5 (AQP5 is a membrane water channel widely distributed in human tissues that was found up-regulated in different tumors and considered implicated in carcinogenesis in different organs and systems. Despite its wide distribution pattern and physiological importance, AQP5 short-term regulation was not reported and mechanisms underlying its involvement in cancer are not well defined. In this work, we expressed rat AQP5 in yeast and investigated mechanisms of gating, as well as AQP5’s ability to facilitate H2O2 plasma membrane diffusion. We found that AQP5 can be gated by extracellular pH in a phosphorylation-dependent manner, with higher activity at physiological pH 7.4. Moreover, similar to other mammalian AQPs, AQP5 is able to increase extracellular H2O2 influx and to affect oxidative cell response with dual effects: whereas in acute oxidative stress conditions AQP5 induces an initial higher sensitivity, in chronic stress AQP5 expressing cells show improved cell survival and resistance. Our findings support the involvement of AQP5 in oxidative stress and suggest AQP5 modulation by phosphorylation as a novel tool for therapeutics.

Self-adapting denoising, alignment and reconstruction in electron tomography in materials science

Energy Technology Data Exchange (ETDEWEB)

Printemps, Tony, E-mail: tony.printemps@cea.fr [Université Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Mula, Guido [Dipartimento di Fisica, Università di Cagliari, Cittadella Universitaria, S.P. 8km 0.700, 09042 Monserrato (Italy); Sette, Daniele; Bleuet, Pierre; Delaye, Vincent; Bernier, Nicolas; Grenier, Adeline; Audoit, Guillaume; Gambacorti, Narciso; Hervé, Lionel [Université Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

2016-01-15

An automatic procedure for electron tomography is presented. This procedure is adapted for specimens that can be fashioned into a needle-shaped sample and has been evaluated on inorganic samples. It consists of self-adapting denoising, automatic and accurate alignment including detection and correction of tilt axis, and 3D reconstruction. We propose the exploitation of a large amount of information of an electron tomography acquisition to achieve robust and automatic mixed Poisson–Gaussian noise parameter estimation and denoising using undecimated wavelet transforms. The alignment is made by mixing three techniques, namely (i) cross-correlations between neighboring projections, (ii) common line algorithm to get a precise shift correction in the direction of the tilt axis and (iii) intermediate reconstructions to precisely determine the tilt axis and shift correction in the direction perpendicular to that axis. Mixing alignment techniques turns out to be very efficient and fast. Significant improvements are highlighted in both simulations and real data reconstructions of porous silicon in high angle annular dark field mode and agglomerated silver nanoparticles in incoherent bright field mode. 3D reconstructions obtained with minimal user-intervention present fewer artefacts and less noise, which permits easier and more reliable segmentation and quantitative analysis. After careful sample preparation and data acquisition, the denoising procedure, alignment and reconstruction can be achieved within an hour for a 3D volume of about a hundred million voxels, which is a step toward a more routine use of electron tomography. - Highlights: • Goal: perform a reliable and user-independent 3D electron tomography reconstruction. • Proposed method: self-adapting denoising and alignment prior to 3D reconstruction. • Noise estimation and denoising are performed using wavelet transform. • Tilt axis determination is done automatically as well as projection alignment. �

SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

Science.gov (United States)

Chia-Song, Wu; Hsing-Chung, Liu

2009-11-01

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

Gate dielectric strength dependent performance of CNT MOSFET and CNT TFET: A tight binding study

Directory of Open Access Journals (Sweden)

Md. Shamim Sarker

Full Text Available This paper presents a comparative study between CNT MOSFET and CNT TFET taking into account of different dielectric strength of gate oxide materials. Here we have studied the transfer characteristics, on/off current (ION/IOFF ratio and subthreshold slope of the device using Non Equilibrium Greens Function (NEGF formalism in tight binding frameworks. The results are obtained by solving the NEGF and Poisson’s equation self-consistently in NanoTCADViDES environment and found that the ON state performance of CNT MOSFET and CNT TFET have significant dependency on the dielectric strength of the gate oxide materials. The figure of merits of the devices also demonstrates that the CNT TFET is promising for high-speed and low-power logic applications. Keywords: CNT TFET, Subthreshold slop, Barrier width, Conduction band (C.B and Valance band (V.B, Oxide dielectric strength, Tight binding approach

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

Science.gov (United States)

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

Science.gov (United States)

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Magnetic behavior of iron oxide nanoparticle-biomolecule assembly

International Nuclear Information System (INIS)

Kim, Taegyun; Reis, Lynn; Rajan, Krishna; Shima, Mutsuhiro

2005-01-01

Iron oxide nanoparticles of 8-20 nm in size were investigated as an assembly with biomolecules synthesized in an aqueous solution. The magnetic behavior of the biomolecule-nanoparticles assembly depends sensitively on the morphology and hence the distribution of the nanoparticles, where the dipole coupling between the nanoparticles governs the overall magnetic behavior. In assemblies of iron oxide nanoparticles with trypsin, we observe a formation of unusual self-alignment of nanoparticles within trypsin molecules. In such an assembly structure, the magnetic particles tend to exhibit a lower spin-glass transition temperature than as-synthesized bare iron oxide nanoparticles probably due to reduced interparticle couplings within the molecular matrix. The observed self-alignment of nanoparticles in biomolecules may be a useful approach for directed nanoparticles assembly

Capillary self-alignment dynamics for R2R manufacturing of mesoscopic system-in-foil devices

NARCIS (Netherlands)

Arutinov, G.; Quintero, A.V.; Smits, E.C.P.; Remoortere, B. van; Brand, J. van den; Schoo, H.F.M.; Briand, D.; Rooij, N.F. de; Dietzel, A.H.

2012-01-01

This paper reports a study on the dynamics of foil-based functional component self-alignment onto patterned test substrates and its demonstration when integrating a flexible sensor onto a printed circuitry. We investigate the dependence of alignment time and final precision of stacking of mm- and

Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

Directory of Open Access Journals (Sweden)

J. B. Kim

2012-03-01

Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

Science.gov (United States)

Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

2018-03-01

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

Control rod housing alignment and repair method

International Nuclear Information System (INIS)

Dixon, R.C.; Deaver, G.A.; Punches, J.R.; Singleton, G.E.; Erbes, J.G.; Offer, H.P.

1992-01-01

This patent describes a method for underwater welding of a control rod drive housing inserted through a stub tube to maintain requisite alignment and elevation of the top of the control rod drive housing to an overlying and corresponding aperture in a core plate as measured by an alignment device which determines the relative elevation and angularity with respect to the aperture. It comprises providing a welding cylinder dependent from the alignment device such that the elevation of the top of the welding cylinder is in a fixed relationship to the alignment device and is gas-proof; pressurizing the welding cylinder with inert welding gas sufficient to maintain the interior of the welding cylinder dry; lowering the welding cylinder through the aperture in the core plate by depending the cylinder with respect to the alignment device, the lowering including lowering through and adjusting the elevation relationship of the welding cylinder to the alignment device such that when the alignment device is in position to measure the elevation and angularity of the new control rod drive housing, the lower distal end of the welding cylinder extends below the upper periphery of the stub where welding is to occur; inserting a new control rod drive housing through the stub tube and positioning the control rod drive housing to a predetermined relationship to the anticipated final position of the control rod drive housing; providing welding implements transversely rotatably mounted interior of the welding cylinder relative to the alignment device such that the welding implements may be accurately positioned for dispensing weldment around the periphery of the top of the stub tube and at the side of the control rod drive housing; measuring the elevation and angularity of the control rod drive housing; and dispensing weldment along the top of the stub tube and at the side of the control rod drive housing

Mechanical Design, Simulation, and Testing of Self-Aligning Gaussian Telescope and Stand for ITER LFS Reflectometer Diagnostic

Science.gov (United States)

Broughton, Rachel; Gomez, Michael; Zolfaghari, Ali; Morris, Lewis

2016-10-01

A self-aligning Gaussian telescope has been designed to compensate for the effect of movement in the ITER vacuum vessel on the transmission line. The purpose of the setup is to couple microwaves into and out of the vessel across the vacuum windows while allowing for both slow movements of the vessel, due to thermal growth, and rapid movements, due to vibrations and disruptions. Additionally, a test stand has been designed specifically to hold this telescope in order to imitate these movements. Consequently, this will allow for the assessment of the efficacy in applying the self-aligning Gaussian telescope approach. The motions of the test stand, as well as the stress on the telescope mechanism, have been virtually simulated using ANSYS workbench. A prototype of this test stand and self-aligning telescope will be built using a combination of custom machined parts and ordered parts. The completed mechanism will be tested at the lab in four different ways: slow single- and multi-direction movements, rapid multi-direction movement, functional laser alignment and self-aligning tests, and natural frequency tests. Once the prototype successfully passes all requirements, it will be tested with microwaves in the LFSR transmission line test stand at General Atomics. This work is supported by US DOE Contract No. DE-AC02-09CH11466.

Thermal oxidation of Ni films for p-type thin-film transistors

KAUST Repository

Jiang, Jie; Wang, Xinghui; Zhang, Qing; Li, Jingqi; Zhang, Xixiang

2013-01-01

p-Type nanocrystal NiO-based thin-film transistors (TFTs) are fabricated by simply oxidizing thin Ni films at temperatures as low as 400 °C. The highest field-effect mobility in a linear region and the current on-off ratio are found to be 5.2 cm2 V-1 s-1 and 2.2 × 103, respectively. X-ray diffraction, transmission electron microscopy and electrical performances of the TFTs with "top contact" and "bottom contact" channels suggest that the upper parts of the Ni films are clearly oxidized. In contrast, the lower parts in contact with the gate dielectric are partially oxidized to form a quasi-discontinuous Ni layer, which does not fully shield the gate electric field, but still conduct the source and drain current. This simple method for producing p-type TFTs may be promising for the next-generation oxide-based electronic applications. © 2013 the Owner Societies.

Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

Science.gov (United States)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Bill Gates eyes healthcare market.

Science.gov (United States)

Dunbar, C

1995-02-01

The entrepreneurial spirit is still top in Bill Gates' mind as he look toward healthcare and other growth industries. Microsoft's CEO has not intention of going the way of other large technology companies that became obsolete before they could compete today.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

Science.gov (United States)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices.

Science.gov (United States)

Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

2016-09-30

New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm 2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

Self-assembled manganese oxide structures through direct oxidation

KAUST Repository

Zhao, Chao; Wang, Qingxiao; Yang, Yang; Zhang, Bei; Zhang, Xixiang

2012-01-01

The morphology and phase of self-assembled manganese oxides during different stages of thermal oxidation were studied. Very interesting morphological patterns of Mn oxide films were observed. At the initial oxidation stage, the surface was characterized by the formation of ring-shaped patterns. As the oxidation proceeded to the intermediate stage, concentric plates formed to relax the compressive stress. Our experimental results gave a clear picture of the evolution of the structures. We also examined the properties of the structures. © 2012 Elsevier B.V.

Self-assembled manganese oxide structures through direct oxidation

KAUST Repository

Zhao, Chao

2012-12-01

The morphology and phase of self-assembled manganese oxides during different stages of thermal oxidation were studied. Very interesting morphological patterns of Mn oxide films were observed. At the initial oxidation stage, the surface was characterized by the formation of ring-shaped patterns. As the oxidation proceeded to the intermediate stage, concentric plates formed to relax the compressive stress. Our experimental results gave a clear picture of the evolution of the structures. We also examined the properties of the structures. © 2012 Elsevier B.V.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

Science.gov (United States)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-12-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

Science.gov (United States)

Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

1998-06-01

Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

Nucleation, Growth Mechanism, and Controlled Coating of ZnO ALD onto Vertically Aligned N-Doped CNTs.

Science.gov (United States)

Silva, R M; Ferro, M C; Araujo, J R; Achete, C A; Clavel, G; Silva, R F; Pinna, N

2016-07-19

Zinc oxide thin films were deposited on vertically aligned nitrogen-doped carbon nanotubes (N-CNTs) by atomic layer deposition (ALD) from diethylzinc and water. The study demonstrates that doping CNTs with nitrogen is an effective approach for the "activation" of the CNTs surface for the ALD of metal oxides. Conformal ZnO coatings are already obtained after 50 ALD cycles, whereas at lower ALD cycles an island growth mode is observed. Moreover, the process allows for a uniform growth from the top to the bottom of the vertically aligned N-CNT arrays. X-ray photoelectron spectroscopy demonstrates that ZnO nucleation takes place at the N-containing species on the surface of the CNTs by the formation of the Zn-N bonds at the interface between the CNTs and the ZnO film.

Strain-driven alignment of In nanocrystals on InGaAs quantum dot arrays and coupled plasmon-quantum dot emission

International Nuclear Information System (INIS)

Urbanczyk, A.; Hamhuis, G. J.; Noetzel, R.

2010-01-01

We report the alignment of In nanocrystals on top of linear InGaAs quantum dot (QD) arrays formed by self-organized anisotropic strain engineering on GaAs (100) by molecular beam epitaxy. The alignment is independent of a thin GaAs cap layer on the QDs revealing its origin is due to local strain recognition. This enables nanometer-scale precise lateral and vertical site registration between the QDs and the In nanocrystals and arrays in a single self-organizing formation process. The plasmon resonance of the In nanocrystals overlaps with the high-energy side of the QD emission leading to clear modification of the QD emission spectrum.

Micropatterning stretched and aligned DNA for sequence-specific nanolithography

Science.gov (United States)

Petit, Cecilia Anna Paulette

Techniques for fabricating nanostructured materials can be categorized as either "top-down" or "bottom-up". Top-down techniques use lithography and contact printing to create patterned surfaces and microfluidic channels that can corral and organize nanoscale structures, such as molecules and nanorods in contrast; bottom-up techniques use self-assembly or molecular recognition to direct the organization of materials. A central goal in nanotechnology is the integration of bottom-up and top-down assembly strategies for materials development, device design; and process integration. With this goal in mind, we have developed strategies that will allow this integration by using DNA as a template for nanofabrication; two top-down approaches allow the placement of these templates, while the bottom-up technique uses the specific sequence of bases to pattern materials along each strand of DNA. Our first top-down approach, termed combing of molecules in microchannels (COMMIC), produces microscopic patterns of stretched and aligned molecules of DNA on surfaces. This process consists of passing an air-water interface over end adsorbed molecules inside microfabricated channels. The geometry of the microchannel directs the placement of the DNA molecules, while the geometry of the airwater interface directs the local orientation and curvature of the molecules. We developed another top-down strategy for creating micropatterns of stretched and aligned DNA using surface chemistry. Because DNA stretching occurs on hydrophobic surfaces, this technique uses photolithography to pattern vinyl-terminated silanes on glass When these surface-, are immersed in DNA solution, molecules adhere preferentially to the silanized areas. This approach has also proven useful in patterning protein for cell adhesion studies. Finally, we describe the use of these stretched and aligned molecules of DNA as templates for the subsequent bottom-up construction of hetero-structures through hybridization

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

KAUST Repository

Caraveo-Frescas, J. A.

2012-03-09

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Crystallization Behavior of Poly(ethylene oxide) in Vertically Aligned Carbon Nanotube Array.

Science.gov (United States)

Sheng, Jiadong; Zhou, Shenglin; Yang, Zhaohui; Zhang, Xiaohua

2018-03-27

We investigate the effect of the presence of vertically aligned multiwalled carbon nanotubes (CNTs) on the orientation of poly(ethylene oxide) (PEO) lamellae and PEO crystallinity. The high alignment of carbon nanotubes acting as templates probably governs the orientation of PEO lamellae. This templating effect might result in the lamella planes of PEO crystals oriented along a direction parallel to the long axis of the nanotubes. The presence of aligned carbon nanotubes also gives rise to the decreases in PEO crystallinity, crystallization temperature, and melting temperature due to the perturbation of carbon nanotubes to the crystallization of PEO. These effects have significant implications for controlling the orientation of PEO lamellae and decreasing the crystallinity of PEO and thickness of PEO lamellae, which have significant impacts on ion transport in PEO/CNT composite and the capacitive performance of PEO/CNT composite. Both the decreased PEO crystallinity and the orientation of PEO lamellae along the long axes of vertically aligned CNTs give rise to the decrease in the charge transfer resistance, which is associated with the improvements in the ion transport and capacitive performance of PEO/CNT composite.

Hybrid dual gate ferroelectric memory for multilevel information storage

KAUST Repository

Khan, Yasser

2015-01-01

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200°C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V-1 s-1, large memory window of ∼18 V, and a low sub-threshold swing ∼-4 V dec-1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.

Negative charge induced degradation of PMOSFETs with BF2-implanted p+-poly gate

International Nuclear Information System (INIS)

Lu, C.Y.; Sung, J.M.

1989-01-01

A new degradation phenomenon on thin gate oxide PMOS-FETs with BF 2 implanted p + -poly gate has been demonstrated and investigated. The cause of this type of degradation is a combination of the boron penetration through the gate oxide and charge trap generation due to the presence of fluorine in the gate oxide and some other processing-induced effects. The negative charge-induced degradation other than enhanced boron diffusion has been studied in detail here. The impact of this process-sensitive p + -poly gate structure on deep submicron CMOS process integration has been discussed. (author)

Superstructure of self-aligned hexagonal GaN nanorods formed on nitrided Si(111) surface

Energy Technology Data Exchange (ETDEWEB)

Kumar, Praveen; Tuteja, Mohit; Kesaria, Manoj; Waghmare, U. V.; Shivaprasad, S. M. [Jawaharlal Nehru Centre for Advanced Scientific Research, Jakkur, Bangalore 560 064 (India)

2012-09-24

We present here the spontaneous formation of catalyst-free, self-aligned crystalline (wurtzite) nanorods on Si(111) surfaces modified by surface nitridation. Nanorods grown by molecular beam epitaxy on bare Si(111) and non-stoichiometric silicon nitride interface are found to be single crystalline but disoriented. Those grown on single crystalline Si{sub 3}N{sub 4} intermediate layer are highly dense c-oriented hexagonal shaped nanorods. The morphology and the self-assembly of the nanorods shows an ordered epitaxial hexagonal superstructure, suggesting that they are nucleated at screw dislocations at the interface and grow spirally in the c-direction. The aligned nanorod assembly shows high-quality structural and optical emission properties.

Interfacial microstructure of NiSi x/HfO2/SiO x/Si gate stacks

International Nuclear Information System (INIS)

Gribelyuk, M.A.; Cabral, C.; Gusev, E.P.; Narayanan, V.

2007-01-01

Integration of NiSi x based fully silicided metal gates with HfO 2 high-k gate dielectrics offers promise for further scaling of complementary metal-oxide- semiconductor devices. A combination of high resolution transmission electron microscopy and small probe electron energy loss spectroscopy (EELS) and energy dispersive X-ray analysis has been applied to study interfacial reactions in the undoped gate stack. NiSi was found to be polycrystalline with the grain size decreasing from top to bottom of NiSi x film. Ni content varies near the NiSi/HfO x interface whereby both Ni-rich and monosilicide phases were observed. Spatially non-uniform distribution of oxygen along NiSi x /HfO 2 interface was observed by dark field Scanning Transmission Electron Microscopy and EELS. Interfacial roughness of NiSi x /HfO x was found higher than that of poly-Si/HfO 2 , likely due to compositional non-uniformity of NiSi x . No intermixing between Hf, Ni and Si beyond interfacial roughness was observed

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

MUON DETECTORS: ALIGNMENT

CERN Multimedia

G.Gomez

2011-01-01

The Muon Alignment work now focuses on producing a new track-based alignment with higher track statistics, making systematic studies between the results of the hardware and track-based alignment methods and aligning the barrel using standalone muon tracks. Currently, the muon track reconstruction software uses a hardware-based alignment in the barrel (DT) and a track-based alignment in the endcaps (CSC). An important task is to assess the muon momentum resolution that can be achieved using the current muon alignment, especially for highly energetic muons. For this purpose, cosmic ray muons are used, since the rate of high-energy muons from collisions is very low and the event statistics are still limited. Cosmics have the advantage of higher statistics in the pT region above 100 GeV/c, but they have the disadvantage of having a mostly vertical topology, resulting in a very few global endcap muons. Only the barrel alignment has therefore been tested so far. Cosmic muons traversing CMS from top to bottom are s...

Preparation of highly aligned silicon oxide nanowires with stable intensive photoluminescence

International Nuclear Information System (INIS)

Duraia, El-Shazly M.; Mansurov, Z.A.; Tokmolden, S.; Beall, Gary W.

2010-01-01

In this work we report the successful formation of highly aligned vertical silicon oxide nanowires. The source of silicon was from the substrate itself without any additional source of silicon. X-ray measurement demonstrated that our nanowires are amorphous. Photoluminescence measurements were conducted through 18 months and indicated that there is a very good intensive emission peaks near the violet regions. The FTIR measurements indicated the existence of peaks at 463, 604, 795 and a wide peak at 1111 cm -1 and this can be attributed to Si-O-Si and Si-O stretching vibrations. We also report the formation of the octopus-like silicon oxide nanowires and the growth mechanism of these structures was discussed.

Preparation of highly aligned silicon oxide nanowires with stable intensive photoluminescence

Energy Technology Data Exchange (ETDEWEB)

Duraia, El-Shazly M., E-mail: duraia_physics@yahoo.co [Suez Canal University, Faculty of Science, Physics Department, Ismailia (Egypt); Al-Farabi Kazakh National University, Almaty (Kazakhstan); Institute of Physics and Technology, 11 Ibragimov Street, 050032 Almaty (Kazakhstan); Mansurov, Z.A. [Al-Farabi Kazakh National University, Almaty (Kazakhstan); Tokmolden, S. [Institute of Physics and Technology, 11 Ibragimov Street, 050032 Almaty (Kazakhstan); Beall, Gary W. [Texas State University-San Marcos, Department of Chemistry and Biochemistry, 601 University Dr., San Marcos, TX 78666 (United States)

2010-02-15

In this work we report the successful formation of highly aligned vertical silicon oxide nanowires. The source of silicon was from the substrate itself without any additional source of silicon. X-ray measurement demonstrated that our nanowires are amorphous. Photoluminescence measurements were conducted through 18 months and indicated that there is a very good intensive emission peaks near the violet regions. The FTIR measurements indicated the existence of peaks at 463, 604, 795 and a wide peak at 1111 cm{sup -1} and this can be attributed to Si-O-Si and Si-O stretching vibrations. We also report the formation of the octopus-like silicon oxide nanowires and the growth mechanism of these structures was discussed.

Characterization, integration and reliability of HfO{sub 2} and LaLuO{sub 3} high-κ/metal gate stacks for CMOS applications

Energy Technology Data Exchange (ETDEWEB)

Nichau, Alexander

2013-07-15

gate electrode to decrease the EOT of HfO{sub 2} gate stacks. A lower limit found was EOT=5 Aa for Al doping inside TiN. The doping of TiN on LaLuO{sub 3} is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO{sub 2}/TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO{sub 2} improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO{sub 2}/TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.

Self-Terminating, Oxidative Radical Cyclizations

Directory of Open Access Journals (Sweden)

Uta Wille

2004-05-01

Full Text Available The recently discovered novel concept of self-terminating, oxidative radical cyclizations, through which alkynes can be converted into carbonyl compounds under very mild reaction conditions using O-centered inorganic and organic radicals as oxidants, is described

Ultra-fine metal gate operated graphene optical intensity modulator

Science.gov (United States)

Kou, Rai; Hori, Yosuke; Tsuchizawa, Tai; Warabi, Kaori; Kobayashi, Yuzuki; Harada, Yuichi; Hibino, Hiroki; Yamamoto, Tsuyoshi; Nakajima, Hirochika; Yamada, Koji

2016-12-01

A graphene based top-gate optical modulator on a standard silicon photonic platform is proposed for the future optical telecommunication networks. On the basis of the device simulation, we proposed that an electro-absorption light modulation can be realized by an ultra-narrow metal top-gate electrode (width less than 400 nm) directly located on the top of a silicon wire waveguide. The designed structure also provides excellent features such as carrier doping and waveguide-planarization free fabrication processes. In terms of the fabrication, we established transferring of a CVD-grown mono-layer graphene sheet onto a CMOS compatible silicon photonic sample followed by a 25-nm thick ALD-grown Al2O3 deposition and Source-Gate-Drain electrodes formation. In addition, a pair of low-loss spot-size converter for the input and output area is integrated for the efficient light source coupling. The maximum modulation depth of over 30% (1.2 dB) is observed at a device length of 50 μm, and a metal width of 300 nm. The influence of the initial Fermi energy obtained by experiment on the modulation performance is discussed with simulation results.

Thin concentrator photovoltaic module with micro-solar cells which are mounted by self-align method using surface tension of melted solder

Science.gov (United States)

Hayashi, Nobuhiko; Terauchi, Masaharu; Aya, Youichirou; Kanayama, Shutetsu; Nishitani, Hikaru; Nakagawa, Tohru; Takase, Michihiko

2017-09-01

We are developing a thin and lightweight CPV module using small size lens system made from poly methyl methacrylate (PMMA) with a short focal length and micro-solar cells to decrease the transporting and the installing costs of CPV systems. In order to achieve high conversion efficiency in CPV modules using micro-solar cells, the micro-solar cells need to be mounted accurately to the irradiated region of the concentrated sunlight. In this study, we have successfully developed self-align method thanks to the surface tension of the melted solder even utilizing commercially available surface-mounting technology (SMT). Solar cells were self-aligned to the specified positions of the circuit board by this self-align method with accuracy within ±10 µm. We actually fabricated CPV modules using this self-align method and demonstrated high conversion efficiency of our CPV module.

Participative Design With Top Management

DEFF Research Database (Denmark)

Simonsen, Jesper

2004-01-01

meetings aimed at aligning top management with the supplier’s analysis. The article describes the MUST method’s anchoring principle and the technique of problem mapping supporting this principle. This participatory approach resulted in mutual learning processes with top management which is rarely reported...... on in the PD community. Top management participated by reviewing, challenging, and reformulating the IT designers’ central suppositions, assumptions, and hypotheses related to the causal relation between identified problems and suggested solutions....

Aligning for Innovation - Alignment Strategy to Drive Innovation

Science.gov (United States)

Johnson, Hurel; Teltschik, David; Bussey, Horace, Jr.; Moy, James

2010-01-01

With the sudden need for innovation that will help the country achieve its long-term space exploration objectives, the question of whether NASA is aligned effectively to drive the innovation that it so desperately needs to take space exploration to the next level should be entertained. Authors such as Robert Kaplan and David North have noted that companies that use a formal system for implementing strategy consistently outperform their peers. They have outlined a six-stage management systems model for implementing strategy, which includes the aligning of the organization towards its objectives. This involves the alignment of the organization from the top down. This presentation will explore the impacts of existing U.S. industrial policy on technological innovation; assess the current NASA organizational alignment and its impacts on driving technological innovation; and finally suggest an alternative approach that may drive the innovation needed to take the world to the next level of space exploration, with NASA truly leading the way.

Oxidation and reduction kinetics of eutectic SnPb, InSn, and AuSn: a knowledge base for fluxless solder bonding applications

DEFF Research Database (Denmark)

Kuhmann, Jochen Friedrich; Preuss, A.; Adolphi, B.

1998-01-01

: (1) SnPb; (2) InSn; (3) AuSn. The studies of the oxidation kinetics show that the growth of the native oxide, which covers the solder surfaces from the start of all soldering operations is self-limiting. The rate of oxidation on the molten, metallic solder surfaces is significantly reduced...... and reduction kinetics, are applied to flip-chip (FC) bonding experiments in vacuum with and without the injection of H2. Wetting in vacuum is excellent but the self-alignment during flip-chip soldering is restricted. The desired, perfectly self-aligned FC-bonds have been only achieved, using evaporated...

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

Directory of Open Access Journals (Sweden)

D.Nirmal

2014-07-01

Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

Dielectrophoretic alignment of metal and metal oxide nanowires and nanotubes: a universal set of parameters for bridging prepatterned microelectrodes.

Science.gov (United States)

Maijenburg, A W; Maas, M G; Rodijk, E J B; Ahmed, W; Kooij, E S; Carlen, E T; Blank, D H A; ten Elshof, J E

2011-03-15

Nanowires and nanotubes were synthesized from metals and metal oxides using templated cathodic electrodeposition. With templated electrodeposition, small structures are electrodeposited using a template that is the inverse of the final desired shape. Dielectrophoresis was used for the alignment of the as-formed nanowires and nanotubes between prepatterned electrodes. For reproducible nanowire alignment, a universal set of dielectrophoresis parameters to align any arbitrary nanowire material was determined. The parameters include peak-to-peak potential and frequency, thickness of the silicon oxide layer, grounding of the silicon substrate, and nature of the solvent medium used. It involves applying a field with a frequency >10(5) Hz, an insulating silicon oxide layer with a thickness of 2.5 μm or more, grounding of the underlying silicon substrate, and the use of a solvent medium with a low dielectric constant. In our experiments, we obtained good results by using a peak-to-peak potential of 2.1 V at a frequency of 1.2 × 10(5) Hz. Furthermore, an indirect alignment technique is proposed that prevents short circuiting of nanowires after contacting both electrodes. After alignment, a considerably lower resistivity was found for ZnO nanowires made by templated electrodeposition (2.2-3.4 × 10(-3) Ωm) compared to ZnO nanorods synthesized by electrodeposition (10 Ωm) or molecular beam epitaxy (MBE) (500 Ωm). Copyright © 2010 Elsevier Inc. All rights reserved.

Alignment method for parabolic trough solar concentrators

Science.gov (United States)

Diver, Richard B [Albuquerque, NM

2010-02-23

A Theoretical Overlay Photographic (TOP) alignment method uses the overlay of a theoretical projected image of a perfectly aligned concentrator on a photographic image of the concentrator to align the mirror facets of a parabolic trough solar concentrator. The alignment method is practical and straightforward, and inherently aligns the mirror facets to the receiver. When integrated with clinometer measurements for which gravity and mechanical drag effects have been accounted for and which are made in a manner and location consistent with the alignment method, all of the mirrors on a common drive can be aligned and optimized for any concentrator orientation.

Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

Energy Technology Data Exchange (ETDEWEB)

Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

2015-12-21

Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

Flow-driven alignment of carbon nanotubes during floating evaporative self assembly

Science.gov (United States)

Berson, Arganthael; Jinkins, Katherine; Chan, Jason; Brady, Gerald; Gronski, Kjerstin; Gopalan, Padma; Evensen, Harold; Arnold, Michael

2017-11-01

Individual semi-conducting single-wall carbon nanotubes (s-SWCNTs) exhibit exceptional electronic properties, which makes them promising candidates for the next generation of semi-conductor electronics. In practice, field-effect transistors (FETs) are fabricated from arrays of s-SWCNTs deposited onto a substrate. In order to achieve high electronic performance, the s-SWCNTs in these arrays must be densely packed and well aligned. Floating Evaporative Self Assembly (FESA) is a new deposition technique developed at the UW-Madison that can achieve such high-quality s-SWCNT alignment. For example, it was used to fabricate the first s-SWCNT-based FETs to outperform gallium arsenide and silicon FETs. In FESA, a droplet of ink containing the s-SWCNTs is deposited onto a pool of water. The ink spreads on the water surface towards a substrate that is vertically pulled out of the water. A band of aligned s-SWCNTs is deposited with each drop of ink. High-speed imaging is combined with cross-polarized microscopy to elucidate the mechanisms behind the exceptional alignment of s-SWCNTs. Two key mechanisms are 1) the collection of s-SWCNTs at the ink-water interface and 2) the depinning of the air-ink-substrate contact line. Avenues for scaling up FESA will be presented.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

Science.gov (United States)

Nagaiah, Padmaja

on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

Image Captioning with Word Gate and Adaptive Self-Critical Learning

Directory of Open Access Journals (Sweden)

Xinxin Zhu

2018-06-01

Full Text Available Although the policy-gradient methods for reinforcement learning have shown significant improvement in image captioning, how to achieve high performance during the reinforcement optimizing process is still not a simple task. There are at least two difficulties: (1 The large size of vocabulary leads to a large action space, which makes it difficult for the model to accurately predict the current word. (2 The large variance of gradient estimation in reinforcement learning usually causes severe instabilities in the training process. In this paper, we propose two innovations to boost the performance of self-critical sequence training (SCST. First, we modify the standard long short-term memory (LSTMbased decoder by introducing a gate function to reduce the search scope of the vocabulary for any given image, which is termed the word gate decoder. Second, instead of only considering current maximum actions greedily, we propose a stabilized gradient estimation method whose gradient variance is controlled by the difference between the sampling reward from the current model and the expectation of the historical reward. We conducted extensive experiments, and results showed that our method could accelerate the training process and increase the prediction accuracy. Our method was validated on MS COCO datasets and yielded state-of-the-art performance.

A Framework for Evaluating and Enhancing Alignment in Self-Regulated Learning Research

Science.gov (United States)

Dent, Amy L.; Hoyle, Rick H.

2015-01-01

We discuss the articles of this special issue with reference to an important yet previously only implicit dimension of study quality: alignment across the theoretical and methodological decisions that collectively define an approach to self-regulated learning. Integrating and extending work by leaders in the field, we propose a framework for…

Pattern optimizing verification of self-align quadruple patterning

Science.gov (United States)

Yamato, Masatoshi; Yamada, Kazuki; Oyama, Kenichi; Hara, Arisa; Natori, Sakurako; Yamauchi, Shouhei; Koike, Kyohei; Yaegashi, Hidetami

2017-03-01

Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) have come to be used in memory devices, and they have also been adopted in logic devices to create constituent patterns in the formation of 1D layout designs. Multi-patterning has consequently become an indispensible technology in the fabrication of all advanced devices. In general, items that must be managed when using multi-patterning include critical dimension uniformity (CDU), line edge roughness (LER), and line width roughness (LWR). Recently, moreover, there has been increasing focus on judging and managing pattern resolution performance from a more detailed perspective and on making a right/wrong judgment from the perspective of edge placement error (EPE). To begin with, pattern resolution performance in spacer-type multi-patterning is affected by the process accuracy of the core (mandrel) pattern. Improving the controllability of CD and LER of the mandrel is most important, and to reduce LER, an appropriate smoothing technique should be carefully selected. In addition, the atomic layer deposition (ALD) technique is generally used to meet the need for high accuracy in forming the spacer film. Advances in scaling are accompanied by stricter requirements in the controllability of fine processing. In this paper, we first describe our efforts in improving controllability by selecting the most appropriate materials for the mandrel pattern and spacer film. Then, based on the materials selected, we present experimental results on a technique for improving etching selectivity.

New insight of high temperature oxidation on self-exfoliation capability of graphene oxide

Science.gov (United States)

Liu, Yuhang; Zeng, Jie; Han, Di; Wu, Kai; Yu, Bowen; Chai, Songgang; Chen, Feng; Fu, Qiang

2018-05-01

The preparation of graphene oxide (GO) via Hummers method is usually divided into two steps: low temperature oxidation at 35 °C (step I oxidation) and high temperature oxidation at 98 °C (step II oxidation). However, the effects of these two steps on the exfoliation capability and chemical structure of graphite oxide remain unclear. In this study, both the functional group content of graphite oxide and the entire evolution of interlayer spacing were investigated during the two steps. Step I oxidation is a slowly inhomogeneous oxidation step to remove unoxidized graphite flakes. The prepared graphite oxide can be easily self-exfoliated but contains a lot of organic sulfur. During the first 20 min of step II oxidation, the majority of organic sulfur can be efficiently removed and graphite oxide still remains a good exfoliation capability due to sharp increasing of carboxyl groups. However, with a longer oxidation time at step II oxidation, the decrease of organic sulfur content is slowed down apparently but without any carboxyl groups forming, then graphite oxide finally loses self-exfoliation capability. It is concluded that a short time of step II oxidation can produce purer and ultralarge GO sheets via self-exfoliation. The pure GO is possessed with better thermal stability and liquid crystal behavior. Besides, reduced GO films prepared from step II oxidation show better mechanical and electric properties after reducing compared with that obtained only via step I oxidation.

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

VKCDB: Voltage-gated potassium channel database

Directory of Open Access Journals (Sweden)

Gallin Warren J

2004-01-01

Full Text Available Abstract Background The family of voltage-gated potassium channels comprises a functionally diverse group of membrane proteins. They help maintain and regulate the potassium ion-based component of the membrane potential and are thus central to many critical physiological processes. VKCDB (Voltage-gated potassium [K] Channel DataBase is a database of structural and functional data on these channels. It is designed as a resource for research on the molecular basis of voltage-gated potassium channel function. Description Voltage-gated potassium channel sequences were identified by using BLASTP to search GENBANK and SWISSPROT. Annotations for all voltage-gated potassium channels were selectively parsed and integrated into VKCDB. Electrophysiological and pharmacological data for the channels were collected from published journal articles. Transmembrane domain predictions by TMHMM and PHD are included for each VKCDB entry. Multiple sequence alignments of conserved domains of channels of the four Kv families and the KCNQ family are also included. Currently VKCDB contains 346 channel entries. It can be browsed and searched using a set of functionally relevant categories. Protein sequences can also be searched using a local BLAST engine. Conclusions VKCDB is a resource for comparative studies of voltage-gated potassium channels. The methods used to construct VKCDB are general; they can be used to create specialized databases for other protein families. VKCDB is accessible at http://vkcdb.biology.ualberta.ca.

Electronic structure of indium-tungsten-oxide alloys and their energy band alignment at the heterojunction to crystalline silicon

Science.gov (United States)

Menzel, Dorothee; Mews, Mathias; Rech, Bernd; Korte, Lars

2018-01-01

The electronic structure of thermally co-evaporated indium-tungsten-oxide films is investigated. The stoichiometry is varied from pure tungsten oxide to pure indium oxide, and the band alignment at the indium-tungsten-oxide/crystalline silicon heterointerface is monitored. Using in-system photoelectron spectroscopy, optical spectroscopy, and surface photovoltage measurements, we show that the work function of indium-tungsten-oxide continuously decreases from 6.3 eV for tungsten oxide to 4.3 eV for indium oxide, with a concomitant decrease in the band bending at the hetero interface to crystalline silicon than indium oxide.

Gate-keeping in the Age of Information Society

DEFF Research Database (Denmark)

Andersen, Kim Normann; Medaglia, Rony; Henriksen, Helle Zinner

’ being reluctant to accept imposed standards and control from central level (top-down) but also avoiding demands from parents (and children) on transparency and accountability (bottom-up). The lack of accessibility of grades on the web can thus be seen as a classical gate-keeping mechanism evolving...... in the age of information society where expectations of end-of-gatekeeping by providing accessibility and transparency using information systems has been outnumbered by classical forces of gate-keeping....

Resilience of Self-Organised and Top-Down Planned Cities--A Case Study on London and Beijing Street Networks.

Directory of Open Access Journals (Sweden)

Jiaqiu Wang

Full Text Available The success or failure of the street network depends on its reliability. In this article, using resilience analysis, the author studies how the shape and appearance of street networks in self-organised and top-down planned cities influences urban transport. Considering London and Beijing as proxies for self-organised and top-down planned cities, the structural properties of London and Beijing networks first are investigated based on their primal and dual representations of planar graphs. The robustness of street networks then is evaluated in primal space and dual space by deactivating road links under random and intentional attack scenarios. The results show that the reliability of London street network differs from that of Beijing, which seems to rely more on its architecture and connectivity. It is found that top-down planned Beijing with its higher average degree in the dual space and assortativity in the primal space is more robust than self-organised London using the measures of maximum and second largest cluster size and network efficiency. The article offers an insight, from a network perspective, into the reliability of street patterns in self-organised and top-down planned city systems.

Uncertainty evaluation in the self-alignment test of the upper plate of a press

International Nuclear Information System (INIS)

Lourenço, Alexandre S; E Sousa, J Alves

2015-01-01

This paper describes a method to evaluate uncertainty of the self-alignment test of the upper plate of a press according to EN 12390-4:2000. The method, the algorithms and the sources of uncertainty are described

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

Science.gov (United States)

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

Science.gov (United States)

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

Science.gov (United States)

2016-08-19

limiters, MEMS, NEMS, field emission, cold cathodes (Some figures may appear in colour only in the online journal) 1. Introduction Dense arrays of silicon... attention has been given to densely packed, highly ordered, top-down fabricated, single crystal vertical silicon nanowire devices that are embedded

High-fidelity gates in quantum dot spin qubits.

Science.gov (United States)

Koh, Teck Seng; Coppersmith, S N; Friesen, Mark

2013-12-03

Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet-triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning [Symbol: see text], which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an f(opt)(g) that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound f(max) that is specific to the qubit-gate combination. We show that similar gate fidelities (~99:5%) should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins.

Origin of noise in liquid-gated Si nanowire troponin biosensors

Science.gov (United States)

Kutovyi, Y.; Zadorozhnyi, I.; Hlukhova, H.; Handziuk, V.; Petrychuk, M.; Ivanchuk, Andriy; Vitusevich, S.

2018-04-01

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

2010-01-01

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa

2010-12-20

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

Science.gov (United States)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Control rod housing alignment and repair apparatus

International Nuclear Information System (INIS)

Dixon, R.C.; Deaver, G.A.; Punches, J.R.; Singleton, G.E.; Erbes, J.G.; Offer, H.P.

1991-01-01

This patent describes a welding a repair device for precisely locating and welding the position of the top of a control rod drive housing attached from a stub tube from a corresponding aperture and alignment pin in a core plate within a boiling water nuclear reactor, the welding and repair device. It comprises: a shaft, the shaft extending from the vicinity of the top of the control rod drive housing up to and through the aperture in the core plate; means for registering to the aperture and the alignment pin on the core plate; a fixture attached to the bottom end of the shaft for mating to the top of the control rod drive housing in precise mating relationship; the fixture attached to the bottom end of the shaft whereby the fixture, when mated to the control rod drove housing and the registering means when registered to the alignment pin and aperture on the core plate imparts to the shaft, and angularity between the top of the control rod drive housing and the hole in the core plate; a hollow cylinder, the cylinder mounted for depending and sealed support with respect to the shaft above, about and below the control rod drive housing top; the cylinder depending down below the control rod drive housing to an elevation below the top of the sub tube; a rotating welding apparatus with a welding head for dispensing weldment mounted for rotation with respect to the shaft; the welding head disposed at the juncture between the side of the control rod drive housing and the stub tube; and means for flooding the cylinder with gas whereby the cylinder may be lowered. flooded in a gas environment and effect a weld between the top of the stub tube and the control rod drive housing

Long-Term Synaptic Plasticity Emulated in Modified Graphene Oxide Electrolyte Gated IZO-Based Thin-Film Transistors.

Science.gov (United States)

Yang, Yi; Wen, Juan; Guo, Liqiang; Wan, Xiang; Du, Peifu; Feng, Ping; Shi, Yi; Wan, Qing

2016-11-09

Emulating neural behaviors at the synaptic level is of great significance for building neuromorphic computational systems and realizing artificial intelligence. Here, oxide-based electric double-layer (EDL) thin-film transistors were fabricated using 3-triethoxysilylpropylamine modified graphene oxide (KH550-GO) electrolyte as the gate dielectrics. Resulting from the EDL effect and electrochemical doping between mobile protons and the indium-zinc-oxide channel layer, long-term synaptic plasticity was emulated in our devices. Synaptic functions including long-term memory, synaptic temporal integration, and dynamic filters were successfully reproduced. In particular, spike rate-dependent plasticity (SRDP), one of the basic learning rules of long-term plasticity in the neural network where the synaptic weight changes according to the rate of presynaptic spikes, was emulated in our devices. Our results may facilitate the development of neuromorphic computational systems.

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Uni- and tridimensional alignment of molecules by femto-second laser pulse

International Nuclear Information System (INIS)

Rouzee, Arnaud

2007-01-01

This thesis is devoted to the study of the alignment of linear and asymmetric top molecules generated by an intense laser pulse. In the case of short pulses with respect to molecular rotation, periodic alignment appears in field-free conditions after the extinction of the field. We study theoretically and experimentally the effects of intensity, temperature and polarization of the electric field on produced alignment. If the field is linearly polarized, the interaction leads to the alignment of the most polarizable axis of the molecule. If the field is elliptically polarized, the pulse can generate a simultaneous alignment of the three principal axes of inertia of an asymmetric top molecule (3-D alignment). This alignment can be characterized experimentally using pump-probe techniques which exploit the optical properties of the medium. They require the use of a second pulse of low intensity temporally delayed. Three techniques were exploited during this thesis. The first technique measures a depolarization due to the birefringence of the medium when the molecules are aligned. The second is based on the defocusing of the pulse on a gradient of index created following the space variation of alignment with respect to the spatial profile of the field. The last involves the creation of a grading of index to the intersection of two intense pulses, which causes the diffraction of the probe. Finally, we show experimentally that the birefringence technique can be used to quantify the 3-D alignment of an asymmetric top molecule like ethylene. (author) [fr

C-V analysis at variable frequency of MOS structures with different gates, containing Hf-Doped Ta2O5

International Nuclear Information System (INIS)

Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

2012-01-01

The quality of the interface between the insulating layer and the Si substrate in contemporary submicron MOS technology is a critical issue for device functioning. It is characterized through the electrically active defect centers, known as interface states. Their response to the frequency is discussed here, by analyzing capacitance-voltage and conductance-voltage curves. The C-V method is preferred in many cases, since it offers easy measurement, and it is applied to extract information about interface traps and fixed oxide charge, at different frequencies. This technique, related with frequency dependent G-V measurements, can be very useful in characterizing charge trapped in the dielectric and at the interface with Si. By extracting the value of frequency dependent flat band voltage, we have obtained the fixed oxide charges at flat band condition. A comparison between the results obtained by two different methods is made. The samples that are studied are metal-insulator-semiconductor (MIS) structures that include high-k dielectric as insulating layer (Hf doped Ta 2 O 5 ), with thickness of 8 nm, with different metal used as gate electrode. Here the influence of the top electrode on the generation and behavior of the traps in the oxide layer is discussed. The results show that the value of metal work function of the gate material is an issue that should be considered very carefully, especially in the case of high work function metal gates, when generation of extra positive charge than in the case of other metals is observed. (Author)

Fitting in and feeling good: the relationships among peer alignment, instructor connectedness, and self-efficacy in undergraduate satisfaction with engineering

Science.gov (United States)

Micari, Marina; Pazos, Pilar

2016-07-01

This study examined the relationships among peer alignment (the feeling that one is similar in important ways to one's engineering peers), instructor connectedness (the sense that one knows and looks up to academic staff/faculty members in the department), self-efficacy for engineering class work (confidence in one's ability to successfully complete engineering class work), and engineering students' satisfaction with the major. A total of 135 sophomore (second-year university students) and junior (third-year students) engineering students were surveyed to measure these three variables. A multiple regression analysis showed that self-efficacy, peer alignment, and instructor connectedness predicted student satisfaction with the major, and that self-efficacy acted as a mediator between both peer alignment and instructor connectedness on the one hand, and satisfaction on the other. The authors offer suggestions for practice based on the results.

Chemical solution route to self-assembled epitaxial oxide nanostructures.

Science.gov (United States)

Obradors, X; Puig, T; Gibert, M; Queraltó, A; Zabaleta, J; Mestres, N

2014-04-07

Self-assembly of oxides as a bottom-up approach to functional nanostructures goes beyond the conventional nanostructure formation based on lithographic techniques. Particularly, chemical solution deposition (CSD) is an ex situ growth approach very promising for high throughput nanofabrication at low cost. Whereas strain engineering as a strategy to define nanostructures with tight control of size, shape and orientation has been widely used in metals and semiconductors, it has been rarely explored in the emergent field of functional complex oxides. Here we will show that thermodynamic modeling can be very useful to understand the principles controlling the growth of oxide nanostructures by CSD, and some attractive kinetic features will also be presented. The methodology of strain engineering is applied in a high degree of detail to form different sorts of nanostructures (nanodots, nanowires) of the oxide CeO2 with fluorite structure which then is used as a model system to identify the principles controlling self-assembly and self-organization in CSD grown oxides. We also present, more briefly, the application of these ideas to other oxides such as manganites or BaZrO3. We will show that the nucleation and growth steps are essentially understood and manipulated while the kinetic phenomena underlying the evolution of the self-organized networks are still less widely explored, even if very appealing effects have been already observed. Overall, our investigation based on a CSD approach has opened a new strategy towards a general use of self-assembly and self-organization which can now be widely spread to many functional oxide materials.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

Science.gov (United States)

Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

2018-09-01

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Design, Fabrication and Characterization of Thin Film Structures through Oxidation Kinetics

Science.gov (United States)

Diaz Leon, Juan Jose

Materials science and engineering is devoted to the understanding of the physics and chemistry of materials at the mesoscale and to applying that knowledge into real-life applications. In this work, different oxide materials and different oxidation methods are studied from a materials science point of view and for specific applications. First, the deposition of complex metal oxides is explored for solar energy concentration. This requires a number of multi-cation oxide structures such as thin-film dielectric barriers, low loss waveguides or the use of continuously graded composition oxides for antireflection coatings and light concentration. Then, oxidation via Joule heating is used for the self-alignment of a selector on top of a memristor structure on a nanovia. Simulations are used to explore the necessary voltage for the insulator-to-metal transition temperature of NbO2 using finite element analysis, followed by the fabrication and the characterization of such a device. Finally, long-term copper oxidation at room temperature and pressure is studied using optical techniques. Alternative characterization techniques are used to confirm the growth rate and phase change, and an application of copper oxide as a volatile conductive bridge is shown. All these examples show how the combination of novel simulation, fabrication and characterization techniques can be used to understand physical mechanisms and enable disruptive technologies in fields such as solar cells, light emitting diodes, photodetectors or memory devices.

Improving Business-IT Alignment through Business Architecture

Science.gov (United States)

Li, Chingmei

2010-01-01

The business and Information Technology (IT) alignment issue has become one of the Top-10 IT management issues since 1980. IT has continually strived to achieve alignment with business goals and objectives. These IT efforts include ERP implementation to benefit from the best practices; data center consolidation and server virtualization to keep…

Directed self-assembly of nanorod networks: bringing the top down to the bottom up

International Nuclear Information System (INIS)

Einsle, Joshua F; Scheunert, Gunther; Murphy, Antony; Pollard, Robert; Bowman, Robert M; McPhillips, John; Zayats, Anatoly V

2012-01-01

Self-assembled electrodeposited nanorod materials have been shown to offer an exciting landscape for a wide array of research ranging from nanophotonics through to biosensing and magnetics. However, until now, the scope for site-specific preparation of the nanorods on wafers has been limited to local area definition. Further there is little or no lateral control of nanorod height. In this work we present a scalable method for controlling the growth of the nanorods in the vertical direction as well as their lateral position. A focused ion beam pre-patterns the Au cathode layer prior to the creation of the anodized aluminium oxide (AAO) template on top. When the pre-patterning is of the same dimension as the pore spacing of the AAO template, lines of single nanorods are successfully grown. Further, for sub-200 nm wide features, a relationship between the nanorod height and distance from the non-patterned cathode can be seen to follow a quadratic growth rate obeying Faraday’s law of electrodeposition. This facilitates lateral control of nanorod height combined with localized growth of the nanorods. (paper)

Directed self-assembly of nanorod networks: bringing the top down to the bottom up.

Science.gov (United States)

Einsle, Joshua F; Scheunert, Gunther; Murphy, Antony; McPhillips, John; Zayats, Anatoly V; Pollard, Robert; Bowman, Robert M

2012-12-21

Self-assembled electrodeposited nanorod materials have been shown to offer an exciting landscape for a wide array of research ranging from nanophotonics through to biosensing and magnetics. However, until now, the scope for site-specific preparation of the nanorods on wafers has been limited to local area definition. Further there is little or no lateral control of nanorod height. In this work we present a scalable method for controlling the growth of the nanorods in the vertical direction as well as their lateral position. A focused ion beam pre-patterns the Au cathode layer prior to the creation of the anodized aluminium oxide (AAO) template on top. When the pre-patterning is of the same dimension as the pore spacing of the AAO template, lines of single nanorods are successfully grown. Further, for sub-200 nm wide features, a relationship between the nanorod height and distance from the non-patterned cathode can be seen to follow a quadratic growth rate obeying Faraday's law of electrodeposition. This facilitates lateral control of nanorod height combined with localized growth of the nanorods.

Hybrid dual gate ferroelectric memory for multilevel information storage

KAUST Repository

Khan, Yasser; Caraveo-Frescas, Jesus Alfonso; Alshareef, Husam N.

2015-01-01

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field

The effect of gate length on SOI-MOSFETS operation | Baedi ...

African Journals Online (AJOL)

The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

Science.gov (United States)

Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

2015-12-01

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2014-01-01

Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

Science.gov (United States)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

OpenAIRE

Lin, Yu-Hsien; Chou, Jay-Chi

2014-01-01

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chem...

Temporal and voltage stress stability of high performance indium-zinc-oxide thin film transistors

Science.gov (United States)

Song, Yang; Katsman, Alexander; Butcher, Amy L.; Paine, David C.; Zaslavsky, Alexander

2017-10-01

Thin film transistors (TFTs) based on transparent oxide semiconductors, such as indium zinc oxide (IZO), are of interest due to their improved characteristics compared to traditional a-Si TFTs. Previously, we reported on top-gated IZO TFTs with an in-situ formed HfO2 gate insulator and IZO active channel, showing high performance: on/off ratio of ∼107, threshold voltage VT near zero, extracted low-field mobility μ0 = 95 cm2/V·s, and near-perfect subthreshold slope at 62 mV/decade. Since device stability is essential for technological applications, in this paper we report on the temporal and voltage stress stability of IZO TFTs. Our devices exhibit a small negative VT shift as they age, consistent with an increasing carrier density resulting from an increasing oxygen vacancy concentration in the channel. Under gate bias stress, freshly annealed TFTs show a negative VT shift during negative VG gate bias stress, while aged (>1 week) TFTs show a positive VT shift during negative VG stress. This indicates two competing mechanisms, which we identify as the field-enhanced generation of oxygen vacancies and the field-assisted migration of oxygen vacancies, respectively. A simplified kinetic model of the vacancy concentration evolution in the IZO channel under electrical stress is provided.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

International Nuclear Information System (INIS)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

2001-01-01

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

Alignment enhancement of a symmetric top molecule by two short laser pulses

DEFF Research Database (Denmark)

Bisgaard, Christer Z; Viftrup, Simon; Stapelfeldt, Henrik

2006-01-01

equation. It is shown that the strongest degree of one-dimensional (single axis) field-free alignment obtainable with a single pulse can be enhanced using the two-pulse sequence in a parallel polarization geometry. The conditions for alignment enhancement are: (1) The second pulse must be sent near...

An analytical gate tunneling current model for MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Kazerouni, Iman Abaspur, E-mail: imanabaspur@gmail.com; Hosseini, Seyed Ebrahim [Sabzevar Tarbiat Moallem University, Electrical and Computer Department (Iran, Islamic Republic of)

2012-03-15

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.

Oxide nanostructures through self-assembly

Science.gov (United States)

Aggarwal, S.; Ogale, S. B.; Ganpule, C. S.; Shinde, S. R.; Novikov, V. A.; Monga, A. P.; Burr, M. R.; Ramesh, R.; Ballarotto, V.; Williams, E. D.

2001-03-01

A prominent theme in inorganic materials research is the creation of uniformly flat thin films and heterostructures over large wafers, which can subsequently be lithographically processed into functional devices. This letter proposes an approach that will lead to thin film topographies that are directly counter to the above-mentioned philosophy. Recent years have witnessed considerable research activity in the area of self-assembly of materials, stimulated by observations of self-organized behavior in biological systems. We have fabricated uniform arrays of nonplanar surface features by a spontaneous assembly process involving the oxidation of simple metals, especially under constrained conditions on a variety of substrates, including glass and Si. In this letter we demonstrate the pervasiveness of this process through examples involving the oxidation of Pd, Cu, Fe, and In. The feature sizes can be controlled through the grain size and thickness of the starting metal thin film. Finally, we demonstrate how such submicron scale arrays can serve as templates for the design and development of self-assembled, nanoelectronic devices.

Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

Energy Technology Data Exchange (ETDEWEB)

Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi; Watanabe, Heiji [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Ogawa, Shingo [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Toray Research Center Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan); Yoshigoe, Akitaka; Teraoka, Yuden [Japan Atomic Energy Agency, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan)

2015-06-08

Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

Corner Office Interview: Gates Foundation's Deborah Jacobs

Science.gov (United States)

Miller, Rebecca

2010-01-01

U.S. libraries gave the world a top talent when Deborah Jacobs left her transformational role as City Librarian of Seattle in 2008 to head the Bill & Melinda Gates Foundation's Global Libraries program, the international sibling to the U.S. Libraries program. The initiative fosters national-scale projects with grantees in transitioning countries…

Separation of top and bottom surface conduction in Bi2Te3 thin films

International Nuclear Information System (INIS)

Yu Xinxin; He Liang; Lang Murong; Jiang Wanjun; Kou Xufeng; Tang Jianshi; Huang Guan; Wang, Kang L; Xiu Faxian; Liao Zhiming; Zou Jin; Wang Yong; Zhang Peng

2013-01-01

Quantum spin Hall (QSH) systems are insulating in the bulk with gapless edges or surfaces that are topologically protected and immune to nonmagnetic impurities or geometric perturbations. Although the QSH effect has been realized in the HgTe/CdTe system, it has not been accomplished in normal 3D topological insulators. In this work, we demonstrate a separation of two surface conductions (top/bottom) in epitaxially grown Bi 2 Te 3 thin films through gate dependent Shubnikov–de Haas (SdH) oscillations. By sweeping the gate voltage, only the Fermi level of the top surface is tuned while that of the bottom surface remains unchanged due to strong electric field screening effects arising from the high dielectric constant of Bi 2 Te 3 . In addition, the bulk conduction can be modulated from n- to p-type with a varying gate bias. Our results on the surface control hence pave a way for the realization of QSH effect in topological insulators which requires a selective control of spin transports on the top/bottom surfaces. (paper)

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-11-07

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.

Automated patient setup and gating using cone beam computed tomography projections

DEFF Research Database (Denmark)

Wan, Hanlin; Bertholet, Jenny; Ge, Jiajia

2016-01-01

In radiation therapy, fiducial markers are often implanted near tumors and used for patient positioning and respiratory gating purposes. These markers are then used to manually align the patients by matching the markers in the cone beam computed tomography (CBCT) reconstruction to those...

Scanning gate microscopy on graphene: charge inhomogeneity and extrinsic doping

International Nuclear Information System (INIS)

Jalilian, Romaneh; Tian Jifa; Chen, Yong P; Jauregui, Luis A; Lopez, Gabriel; Roecker, Caleb; Jovanovic, Igor; Yazdanpanah, Mehdi M; Cohn, Robert W

2011-01-01

We have performed scanning gate microscopy (SGM) on graphene field effect transistors (GFET) using a biased metallic nanowire coated with a dielectric layer as a contact mode tip and local top gate. Electrical transport through graphene at various back gate voltages is monitored as a function of tip voltage and tip position. Near the Dirac point, the response of graphene resistance to the tip voltage shows significant variation with tip position, and SGM imaging displays mesoscopic domains of electron-doped and hole-doped regions. Our measurements reveal substantial spatial fluctuation in the carrier density in graphene due to extrinsic local doping from sources such as metal contacts, graphene edges, structural defects and resist residues. Our scanning gate measurements also demonstrate graphene's excellent capability to sense the local electric field and charges.

Self-learning computers for surgical planning and prediction of postoperative alignment.

Science.gov (United States)

Lafage, Renaud; Pesenti, Sébastien; Lafage, Virginie; Schwab, Frank J

2018-02-01

In past decades, the role of sagittal alignment has been widely demonstrated in the setting of spinal conditions. As several parameters can be affected, identifying the driver of the deformity is the cornerstone of a successful treatment approach. Despite the importance of restoring sagittal alignment for optimizing outcome, this task remains challenging. Self-learning computers and optimized algorithms are of great interest in spine surgery as in that they facilitate better planning and prediction of postoperative alignment. Nowadays, computer-assisted tools are part of surgeons' daily practice; however, the use of such tools remains to be time-consuming. NARRATIVE REVIEW AND RESULTS: Computer-assisted methods for the prediction of postoperative alignment consist of a three step analysis: identification of anatomical landmark, definition of alignment objectives, and simulation of surgery. Recently, complex rules for the prediction of alignment have been proposed. Even though this kind of work leads to more personalized objectives, the number of parameters involved renders it difficult for clinical use, stressing the importance of developing computer-assisted tools. The evolution of our current technology, including machine learning and other types of advanced algorithms, will provide powerful tools that could be useful in improving surgical outcomes and alignment prediction. These tools can combine different types of advanced technologies, such as image recognition and shape modeling, and using this technique, computer-assisted methods are able to predict spinal shape. The development of powerful computer-assisted methods involves the integration of several sources of information such as radiographic parameters (X-rays, MRI, CT scan, etc.), demographic information, and unusual non-osseous parameters (muscle quality, proprioception, gait analysis data). In using a larger set of data, these methods will aim to mimic what is actually done by spine surgeons, leading

Laser-driven coating of vertically aligned carbon nanotubes with manganese oxide from metal organic precursors for energy storage

Science.gov (United States)

Pérez del Pino, A.; György, E.; Alshaikh, I.; Pantoja-Suárez, F.; Andújar, J. L.; Pascual, E.; Amade, R.; Bertran-Serra, E.

2017-09-01

Carbon nanotubes-transition metal oxide systems are intensively studied due to their excellent properties for electrochemical applications. In this work, an innovative procedure is developed for the synthesis of vertically aligned multi-walled carbon nanotubes (VACNTs) coated with transition metal oxide nanostructures. VACNTs are grown by plasma enhanced chemical vapor deposition and coated with a manganese-based metal organic precursor (MOP) film based on manganese acetate solution. Subsequent UV pulsed laser irradiation induces the effective heating-decomposition of the MOP leading to the crystallization of manganese oxide nanostructures on the VACNT surface. The study of the morphology, structure and composition of the synthesized materials shows the formation of randomly oriented MnO2 crystals, with few nanometers in size, and to their alignment in hundreds of nm long filament-like structures, parallel to the CNT’s long axis. Electrochemical measurements reveal a significant increase of the specific capacitance of the MnO2-VACNT system (100 F g-1) as compared to the initial VACNT one (21 F g-1).

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

Science.gov (United States)

Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

2015-09-01

In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

EPE analysis of sub-N10 BEoL flow with and without fully self-aligned via using Coventor SEMulator3D

Science.gov (United States)

Franke, Joern-Holger; Gallagher, Matt; Murdoch, Gayle; Halder, Sandip; Juncker, Aurelie; Clark, William

2017-03-01

During the last few decades, the semiconductor industry has been able to scale device performance up while driving costs down. What started off as simple geometrical scaling, driven mostly by advances in lithography, has recently been accompanied by advances in processing techniques and in device architectures. The trend to combine efforts using process technology and lithography is expected to intensify, as further scaling becomes ever more difficult. One promising component of future nodes are "scaling boosters", i.e. processing techniques that enable further scaling. An indispensable component in developing these ever more complex processing techniques is semiconductor process modeling software. Visualization of complex 3D structures in SEMulator3D, along with budget analysis on film thicknesses, CD and etch budgets, allow process integrators to compare flows before any physical wafers are run. Hundreds of "virtual" wafers allow comparison of different processing approaches, along with EUV or DUV patterning options for defined layers and different overlay schemes. This "virtual fabrication" technology produces massively parallel process variation studies that would be highly time-consuming or expensive in experiment. Here, we focus on one particular scaling booster, the fully self-aligned via (FSAV). We compare metal-via-metal (mevia-me) chains with self-aligned and fully-self-aligned via's using a calibrated model for imec's N7 BEoL flow. To model overall variability, 3D Monte Carlo modeling of as many variability sources as possible is critical. We use Coventor SEMulator3D to extract minimum me-me distances and contact areas and show how fully self-aligned vias allow a better me-via distance control and tighter via-me contact area variability compared with the standard self-aligned via (SAV) approach.

Electrical and materials properties of AlN/ HfO{sub 2} high-k stack with a metal gate

Energy Technology Data Exchange (ETDEWEB)

Reid, Kimberly G. [Tokyo Electron U.S., 14338 FM 1826, Austin, TX 78737 (United States)], E-mail: kim@ireid.com; Dip, Anthony [Tokyo Electron U.S., 2400 Grove Blvd., Austin, TX 78747 (United States)], E-mail: anthony.dip@us.tel.com; Sasaki, Sadao [Tokyo Electron U.S. (United States)], E-mail: Sadao.sasaki@us.tel.com; Triyoso, Dina [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Dina.Triyoso@freescale.com; Samavedam, Sri [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Sri.Samavedam@freescale.com; Gilmer, David [SEMATECH 2706 Montopolis Drive, Austin, TX 78741 (United States)], E-mail: David.Gilmer@sematech.org; Gondran, Carolyn F.H. [Process Characterization Laboratory, ATDF/SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741 (United States)], E-mail: Carolyn.Gondran@atdf.com

2009-02-27

In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO{sub 2} that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO{sub 2} using sequential exposures of trimethyl-aluminum and ammonia (NH{sub 3}) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 A for the AlN/HfO{sub 2} stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10{sup -5} to mid 10{sup -6} A/cm{sup 2} at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO{sub 2} with the MoN metal gate, even with a 1000 deg. C anneal.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

Science.gov (United States)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Bill Gates, If You're so Rich, How Come You're Not Smart? Point of View Essay

Science.gov (United States)

Bracey, Gerald

2005-01-01

Bill Gates and the governors were quite vague about what makes the schools obsolete or what to do about it. What is it, exactly, that schools are not teaching that they need to? Bill Gates also claimed that American kids were at the top in fourth grade, but at the bottom by 12th. The author congratulates Gates for focusing some attention on…

Observing the semiconducting band-gap alignment of MoS{sub 2} layers of different atomic thicknesses using a MoS{sub 2}/SiO{sub 2}/Si heterojunction tunnel diode

Energy Technology Data Exchange (ETDEWEB)

Nishiguchi, Katsuhiko, E-mail: nishiguchi.katsuhiko@lab.ntt.co.jp; Yamaguchi, Hiroshi; Fujiwara, Akira [NTT Basic Research Laboratories, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-0198 (Japan); Castellanos-Gomez, Andres; Zant, Herre S. J. van der; Steele, Gary A. [Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, 2628CJ Delft (Netherlands)

2015-08-03

We demonstrate a tunnel diode composed of a vertical MoS{sub 2}/SiO{sub 2}/Si heterostructure. A MoS{sub 2} flake consisting four areas of different thicknesses functions as a gate terminal of a silicon field-effect transistor. A thin gate oxide allows tunneling current to flow between the n-type MoS{sub 2} layers and p-type Si channel. The tunneling-current characteristics show multiple negative differential resistance features, which we interpret as an indication of different conduction-band alignments of the MoS{sub 2} layers of different thicknesses. The presented tunnel device can be also used as a hybrid-heterostructure device combining the advantages of two-dimensional materials with those of silicon transistors.

Achieving Business and IT Alignment from Organisational Learning Perspectives

OpenAIRE

Hamad Hussain Balhareth; Kecheng Liu; Sharm Manwani

2012-01-01

Business and IT alignment has continued as a top concern for business and IT executives for almost three decades. Many researchers have conducted empirical studies on the relationship between business-IT alignment and performance. Yet, these approaches, lacking a social perspective, have had little impact on sustaining performance and competitive advantage. In addition to the limited alignment literature that explores organisational learning that is represented in shared understanding, commun...

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

Science.gov (United States)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Identification of ultramodified proteins using top-down spectra

Energy Technology Data Exchange (ETDEWEB)

Liu, Xiaowen; Hengel, Shawna M.; Wu, Si; Tolic, Nikola; Pasa-Tolic, Ljiljana; Pevzner, Pavel A.

2013-04-10

Post-translational modifications (PTMs) play an important role in various biological processes through changing protein structure and function. Some ultramodified proteins (like histones) have multiple PTMs forming PTM patterns that define the functionality of a protein. While bottom-up mass spectrometry (MS) has been successful in identifying individual PTMs within short peptides, it is unable to identify PTM patterns spread along entire proteins in a coordinated fashion. In contrast, top-down MS analyzes intact proteins and reveals PTM patterns along the entire proteins. However, while recent advances in instrumentation have made top-down MS accessible to many laboratories, most computational tools for top-down MS focus on proteins with few PTMs and are unable to identify complex PTM patterns. We propose a new algorithm, MS-Align-E, that identifies both expected and unexpected PTMs in ultramodified proteins. We demonstrate that MS-Align-E identifies many protein forms of histone H4 and benchmark it against the currently accepted software tools.

Aligned carbon nanotube, graphene and graphite oxide thin films via substrate-directed rapid interfacial deposition

Science.gov (United States)

D'Arcy, Julio M.; Tran, Henry D.; Stieg, Adam Z.; Gimzewski, James K.; Kaner, Richard B.

2012-05-01

A procedure for depositing thin films of carbon nanostructures is described that overcomes the limitations typically associated with solution based methods. Transparent and conductively continuous carbon coatings can be grown on virtually any type of substrate within seconds. Interfacial surface tension gradients result in directional fluid flow and film spreading at the water/oil interface. Transparent films of carbon nanostructures are produced including aligned ropes of single-walled carbon nanotubes and assemblies of single sheets of chemically converted graphene and graphite oxide. Process scale-up, layer-by-layer deposition, and a simple method for coating non-activated hydrophobic surfaces are demonstrated.A procedure for depositing thin films of carbon nanostructures is described that overcomes the limitations typically associated with solution based methods. Transparent and conductively continuous carbon coatings can be grown on virtually any type of substrate within seconds. Interfacial surface tension gradients result in directional fluid flow and film spreading at the water/oil interface. Transparent films of carbon nanostructures are produced including aligned ropes of single-walled carbon nanotubes and assemblies of single sheets of chemically converted graphene and graphite oxide. Process scale-up, layer-by-layer deposition, and a simple method for coating non-activated hydrophobic surfaces are demonstrated. Electronic supplementary information (ESI) available: Droplet coalescence, catenoid formation, mechanism of film growth, scanning electron micrographs showing carbon nanotube alignment, flexible transparent films of SWCNTs, AFM images of a chemically converted graphene film, and SEM images of SWCNT free-standing thin films. See DOI: 10.1039/c2nr00010e

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

Gamma-ray irradiation and post-irradiation at room and elevated temperature response of pMOS dosimeters with thick gate oxides

Directory of Open Access Journals (Sweden)

Pejović Momčilo M.

2011-01-01

Full Text Available Gamma-ray irradiation and post-irradiation response at room and elevated temperature have been studied for radiation sensitive pMOS transistors with gate oxide thickness of 100 and 400 nm, respectively. Their response was followed based on the changes in the threshold voltage shift which was estimated on the basis of transfer characteristics in saturation. The presence of radiation-induced fixed oxide traps and switching traps - which lead to a change in the threshold voltage - was estimated from the sub-threshold I-V curves, using the midgap technique. It was shown that fixed oxide traps have a dominant influence on the change in the threshold voltage shift during gamma-ray irradiation and annealing.

Transport tensors in perfectly aligned low-density fluids: Self-diffusion and thermal conductivity

International Nuclear Information System (INIS)

Singh, G. S.; Kumar, B.

2001-01-01

The modified Taxman equation for the kinetic theory of low-density fluids composed of rigid aspherical molecules possessing internal degrees of freedom is generalized to obtain the transport tensors in a fluid of aligned molecules. The theory takes care of the shape of the particles exactly but the solution has been obtained only for the case of perfectly aligned hard spheroids within the framework of the first Sonine polynomial approximation. The expressions for the thermal-conductivity components have been obtained for the first time whereas the self-diffusion components obtained here turn out to be exactly the same as those derived by Kumar and Masters [Mol. Phys. >81, 491 (1994)] through the solution of the Lorentz-Boltzmann equation. All our expressions yield correct results in the hard-sphere limit

Self-centering fiber alignment structures for high-precision field installable single-mode fiber connectors

Science.gov (United States)

Van Erps, Jürgen; Ebraert, Evert; Gao, Fei; Vervaeke, Michael; Berghmans, Francis; Beri, Stefano; Watté, Jan; Thienpont, Hugo

2014-05-01

There is a steady increase in the demand for internet bandwidth, primarily driven by cloud services and high-definition video streaming. Europe's Digital Agenda states the ambitious objective that by 2020 all Europeans should have access to internet at speeds of 30Mb/s or above, with 50% or more of households subscribing to connections of 100Mb/s. Today however, internet access in Europe is mainly based on the first generation of broadband, meaning internet accessed over legacy telephone copper and TV cable networks. In recent years, Fiber-To-The-Home (FTTH) networks have been adopted as a replacement of traditional electrical connections for the `last mile' transmission of information at bandwidths over 1Gb/s. However, FTTH penetration is still very low (economies. The main reason for this is the high deployment cost of FTTH networks. Indeed, the success and adoption of optical access networks critically depend on the quality and reliability of connections between optical fibers. In particular a further reduction of insertion loss of field- installable connectors must be achieved without a significant increase in component cost. This requires precise alignment of fibers that can differ in terms of ellipticity, eccentricity or diameter and seems hardly achievable using today's widespread ferrule-based alignment systems. In this paper, we present a field-installable connector based on deflectable/compressible spring structures, providing a self-centering functionality for the fiber. This way, it can accommodate for possible fiber cladding diameter variations (the tolerance on the cladding diameter of G.652 fiber is typically +/-0.7μm). The mechanical properties of the cantilever are derived through an analytical approximation and a mathematical model of the spring constant, and finite element-based simulations are carried out to find the maximum first principal stress as well as the stress distribution distribution in the fiber alignment structure. Elastic

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

International Nuclear Information System (INIS)

Chang, Geng-Wei; Chang, Ting-Chang; Syu, Yong-En; Tsai, Tsung-Ming; Chang, Kuan-Chang; Tu, Chun-Hao; Jian, Fu-Yen; Hung, Ya-Chi; Tai, Ya-Hsiang

2011-01-01

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

Proposal for a dual-gate spin field effect transistor: A device with very small switching voltage and a large ON to OFF conductance ratio

Science.gov (United States)

Wan, J.; Cahay, M.; Bandyopadhyay, S.

2008-06-01

We propose a new dual gate spin field effect transistor (SpinFET) consisting of a quasi one-dimensional semiconductor channel sandwiched between two half-metallic contacts. The gate voltage aligns and de-aligns the incident electron energy with Ramsauer resonance levels in the channel, thereby modulating the source-to-drain conductance. The device can be switched from ON to OFF with a few mV change in the gate voltage, resulting in exceedingly low dynamic power dissipation during switching. The conductance ON/OFF ratio stays fairly large ( ∼60) up to a temperature of 10 K. This conductance ratio is comparable to that achievable with carbon nanotube transistors.

Belt Aligning Revisited

Directory of Open Access Journals (Sweden)

Yurchenko Vadim

2017-01-01

parts of the conveyor, the sides of the belt wear intensively. This results in reducing the life of the belt. The reasons for this phenomenon are well investigated, but the difficulty lies in the fact that they all act simultaneously. The belt misalignment prevention can be carried out in two ways: by minimizing the effect of causes and by aligning the belt. The construction of aligning devices and errors encountered in practice are considered in this paper. Self-aligning roller supports rotational in plan view are recommended as a means of combating the belt misalignment.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

Science.gov (United States)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Comparison of short-circuit characteristics of trench gate and planar gate U-shaped channel SOI-LIGBTs

Science.gov (United States)

Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

2017-09-01

Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.

In-Ga-Zn-oxide thin-film transistors with Sb2TeOx gate insulators fabricated by reactive sputtering using a metallic Sb2Te target

International Nuclear Information System (INIS)

Cheong, Woo-Seok

2011-01-01

Using reactive sputtering, we made transparent amorphous Sb 2 TeO x thin films from a metallic Sb 2 Te target in an oxidizing atmosphere. In-Ga-Zn-oxide thin-film transistors (IGZO TFTs) with Sb 2 TeO x gate insulators deposited at room temperature showed a large hysteresis with a counter clockwise direction, which was caused by mobile charges in the gate insulators. The problems of the mobile charges was solved by using Sb 2 TeO x films formed at 250 .deg. C. After the IGZO TFT had been annealed at 200 .deg. C for 1 hour in an O 2 ambient, the mobility of the IGZO TFT was 22.41 cm 2 /Vs, and the drain current on-off ratio was ∼10 8 .

Non-volatile nano-floating gate memory with Pt-Fe{sub 2}O{sub 3} composite nanoparticles and indium gallium zinc oxide channel

Energy Technology Data Exchange (ETDEWEB)

Hu, Quanli [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Lee, Seung Chang; Baek, Yoon-Jae [Myongji University, Department of Materials Science and Engineering (Korea, Republic of); Lee, Hyun Ho [Myongji University, Department of Chemical Engineering (Korea, Republic of); Kang, Chi Jung [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Kim, Hyun-Mi; Kim, Ki-Bum [Seoul National University, Department of Materials Science and Engineering (Korea, Republic of); Yoon, Tae-Sik, E-mail: tsyoon@mju.ac.kr [Myongji University, Department of Nano Science and Engineering (Korea, Republic of)

2013-02-15

Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe{sub 2}O{sub 3} composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe{sub 2}O{sub 3} nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of {approx}3 Multiplication-Sign 10{sup 11} cm{sup -2} by a solution-based dip-coating process. The Pt core ({approx}3 nm in diameter) and Fe{sub 2}O{sub 3}-shell ({approx}6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of {approx}4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of {approx}0.66 V after pulse programming at +20 V for 1 s with retention > {approx}65 % after 10{sup 4} s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

Improvement of in-plane alignment for surface oxidized NiO layer on textured Ni substrate by two-step heat-treatment

International Nuclear Information System (INIS)

Hasegawa, Katsuya; Izumi, Toru; Izumi, Teruo; Shiohara, Yuh; Maeda, Toshihiko

2004-01-01

Epitaxial growth of NiO on a textured Ni substrate as a template for an REBa 2 Cu 3 O y coated conductor was investigated. Highly in-plane aligned NiO layers were successfully fabricated using a new process of a two-step heat-treatment for oxidation. In the first-step, a highly in-plane aligned thin NiO layer was formed on a textured Ni substrate under a low driving force of oxidation. Then, in the second-step, a thick NiO layer was grown at a higher rate with maintaining its high in-plane grain alignment, as if the first NiO layer acts as a seed crystal layer. Further, growth rates and microstructures of the NiO layers were studied comparatively in the cases with and without the first layer. It was found that the oxidation rate in the case with the first layer was lower than that without the first layer. The microstructure observation revealed that the NiO without the first layer was poly-crystalline with many grain-boundaries. On the other hand, in the case with the first layer, grain-boundaries of the NiO were hardly observed. Hence, the reason for this difference of the growth rate and the microstructure of the NiO layers were discussed in view of a diffusivity path

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

Energy Technology Data Exchange (ETDEWEB)

Jo, Kwang-Won; Cho, Won-Ju, E-mail: chowj@kw.ac.kr [Department of Electronic Materials Engineering, Kwangwoon University, 447-1, Wolgye-dong, Nowon-gu, Seoul 139-701 (Korea, Republic of)

2014-11-24

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

International Nuclear Information System (INIS)

Jo, Kwang-Won; Cho, Won-Ju

2014-01-01

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV ON ) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress

Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

Science.gov (United States)

Kyoung, Sinsu; Hong, Young-sung; Lee, Myung-hwan; Nam, Tae-jin

2018-02-01

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

CERN Document Server

Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

2000-01-01

In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

2000-12-01

In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

A Generalizable Top-Down Nanostructuring Method of Bulk Oxides: Sequential Oxygen-Nitrogen Exchange Reaction.

Science.gov (United States)

Lee, Lanlee; Kang, Byungwuk; Han, Suyoung; Kim, Hee-Eun; Lee, Moo Dong; Bang, Jin Ho

2018-05-27

A thermal reaction route that induces grain fracture instead of grain growth is devised and developed as a top-down approach to prepare nanostructured oxides from bulk solids. This novel synthesis approach, referred to as the sequential oxygen-nitrogen exchange (SONE) reaction, exploits the reversible anion exchange between oxygen and nitrogen in oxides that is driven by a simple two-step thermal treatment in ammonia and air. Internal stress developed by significant structural rearrangement via the formation of (oxy)nitride and the creation of oxygen vacancies and their subsequent combination into nanopores transforms bulk solid oxides into nanostructured oxides. The SONE reaction can be applicable to most transition metal oxides, and when utilized in a lithium-ion battery, the produced nanostructured materials are superior to their bulk counterparts and even comparable to those produced by conventional bottom-up approaches. Given its simplicity and scalability, this synthesis method could open a new avenue to the development of high-performance nanostructured electrode materials that can meet the industrial demand of cost-effectiveness for mass production. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Thermally oxidized aluminum as catalyst-support layer for vertically aligned single-walled carbon nanotube growth using ethanol

Energy Technology Data Exchange (ETDEWEB)

Azam, Mohd Asyadi, E-mail: asyadi@jaist.ac.jp [School of Materials Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1 Asahidai, Nomi, Ishikawa 923-1292 (Japan); Fujiwara, Akihiko [Research and Utilization Division, Japan Synchrotron Radiation Research Institute (JASRI), 1-1-1, Kouto, Sayo-cho, Sayo, Hyogo 679-5198 (Japan); Shimoda, Tatsuya [School of Materials Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1 Asahidai, Nomi, Ishikawa 923-1292 (Japan)

2011-11-01

Characteristics and role of Al oxide (Al-O) films used as catalyst-support layer for vertical growth of single-walled carbon nanotubes (SWCNTs) were studied. EB-deposited Al films (20 nm) were thermally oxidized at 400 deg. C (10 min, static air) to produce the most appropriate surface structure of Al-O. Al-O catalyst-support layers were characterized using various analytical measurements, i.e., atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and spectroscopy ellipsometry (SE). The thermally oxidized Al-O has a highly roughened surface, and also has the most suitable surface chemical states compared to other type of Al-O support layers. We suggest that the surface of thermally oxidized Al-O characterized in this work enhanced Co catalyst activity to promote the vertically aligned SWCNT growth.

Capture and alignment of phi29 viral particles in sub-40 nanometer porous alumina membranes.

Science.gov (United States)

Moon, Jeong-Mi; Akin, Demir; Xuan, Yi; Ye, Peide D; Guo, Peixuan; Bashir, Rashid

2009-02-01

Bacteriophage phi29 virus nanoparticles and its associated DNA packaging nanomotor can provide for novel possibilities towards the development of hybrid bio-nano structures. Towards the goal of interfacing the phi29 viruses and nanomotors with artificial micro and nanostructures, we fabricated nanoporous Anodic Aluminum Oxide (AAO) membranes with pore size of 70 nm and shrunk the pores to sub 40 nm diameter using atomic layer deposition (ALD) of Aluminum Oxide. We were able to capture and align particles in the anodized nanopores using two methods. Firstly, a functionalization and polishing process to chemically attach the particles in the inner surface of the pores was developed. Secondly, centrifugation of the particles was utilized to align them in the pores of the nanoporous membranes. In addition, when a mixture of empty capsids and packaged particles was centrifuged at specific speeds, it was found that the empty capsids deform and pass through 40 nm diameter pores whereas the particles packaged with DNA were mainly retained at the top surface of the nanoporous membranes. Fluorescence microscopy was used to verify the selective filtration of empty capsids through the nanoporous membranes.

Dynamic Monte Carlo study of isolated-gate InAs/AlSb HEMTs

International Nuclear Information System (INIS)

Rodilla, H; González, T; Mateos, J; Moschetti, G; Grahn, J

2011-01-01

In this work, by means of Monte Carlo simulations, the static and dynamic behavior of isolated-gate InAs/AlSb high electron mobility transistors (Sb-HEMTs) has been studied and compared with experimental results. The influence of the existence of a native oxide under the gate, the value of the surface charges in the gate recess and the possible variation of electron sheet carrier density, n s , have been studied. A decrease in the gate-source capacitance, transconductance and intrinsic cutoff frequency is observed because of the presence of the native oxide, while changes in the value of the surface charges in the recess only introduce a threshold voltage shift. The increase of n s shifts the maximum of the transconductance and intrinsic cutoff frequency to higher values of drain current and improves the agreement with the experimental results

Dielectrophoretic alignment of metal and metal oxide nanowires and nanotubes: A universal set of parameters for bridging prepatterned microelectrodes

NARCIS (Netherlands)

Maijenburg, A.W.; Maas, M.G.; Rodijk, E.J.B.; Ahmed, W.; Kooij, Ernst S.; Carlen, Edwin; Blank, David H.A.; ten Elshof, Johan E.

2011-01-01

Nanowires and nanotubes were synthesized from metals and metal oxides using templated cathodic electrodeposition. With templated electrodeposition, small structures are electrodeposited using a template that is the inverse of the final desired shape. Dielectrophoresis was used for the alignment of

Nature-aligned approaches to form students’ system motivation

Directory of Open Access Journals (Sweden)

Marina V. Ulyanova

2017-01-01

Full Text Available Sustainable development of the society involves the transition of the society from the current evolutional stage to a higher stage without revolutionary destruction of the existing frames of society. An individual, playing a prominent role in human history from time to time, is able to provide for the evolution of consciousness of the whole community, appearing on the top of the evolutional cone in the moment of passing of the system to the qualitatively new stage of its development. Only an integral individual, a person-creator possessing a high potential of harmony is able to accomplish such transition. The golden proportion of the social structure of the society implies a certain correlation of ontological categories of people, having personality orientation that characterizes them as a creator, consumer or destroyer. The modern approaches to education involve motivating a human being to self-improvement all his/her lifelong. The question is that, how much pedagogical systems correspond to the laws of harmony, which provide formation of social strata golden proportion structure considered not from the perspective of class position, but from the perspective of creative personality orientation. The analysis of the existing educational approaches showed, that the best indices satisfying the set social problem belong to noospheric pedagogics, based on nature-aligned methodology of teaching academic disciplines. It is built on principles of health protection and health development, intellectual potential, system motivation of an individual to self-perfection. Nature-aligned educational methodology is personality oriented and enables the student to accomplish object-subject transformation in the process of education, as a result of which, following the receipt of special educational knowledge, abilities and skills, he/she gets common educational abilities and skills, on the basis of which the processes of self-actualization, self

Aligned Layers of Silver Nano-Fibers

Directory of Open Access Journals (Sweden)

Andrii B. Golovin

2012-02-01

Full Text Available We describe a new dichroic polarizers made by ordering silver nano-fibers to aligned layers. The aligned layers consist of nano-fibers and self-assembled molecular aggregates of lyotropic liquid crystals. Unidirectional alignment of the layers is achieved by means of mechanical shearing. Aligned layers of silver nano-fibers are partially transparent to a linearly polarized electromagnetic radiation. The unidirectional alignment and density of the silver nano-fibers determine degree of polarization of transmitted light. The aligned layers of silver nano-fibers might be used in optics, microwave applications, and organic electronics.

Orientation- and position-controlled alignment of asymmetric silicon microrod on a substrate with asymmetric electrodes

Science.gov (United States)

Shibata, Akihide; Watanabe, Keiji; Sato, Takuya; Kotaki, Hiroshi; Schuele, Paul J.; Crowder, Mark A.; Zhan, Changqing; Hartzell, John W.; Nakatani, Ryoichi

2014-03-01

In this paper, we demonstrate the orientation-controlled alignment of asymmetric Si microrods on a glass substrate with an asymmetric pair of electrodes. The Si microrods have the shape of a paddle with a blade and a shaft part, and the pair of electrodes consists of a narrow electrode and a wide electrode. By applying AC bias to the electrodes, the Si microrods suspended in a fluid align in such a way to settle across the electrode pair, and over 80% of the aligned Si microrods have an orientation with the blade and the shaft of the paddle on the wide and the narrow electrodes, respectively. When Si microrods have a shell of dielectric film and its thickness on the top face is thicker than that on the bottom face, 97.8% of the Si microrods are aligned with the top face facing upwards. This technique is useful for orientation-controlled alignment of nano- and microsized devices that have polarity or a distinction between the top and bottom faces.

Identification of Ultramodified Proteins Using Top-Down Mass Spectra

Energy Technology Data Exchange (ETDEWEB)

Liu, Xiaowen; Hengel, Shawna M.; Wu, Si; Tolic, Nikola; Pasa-Tolic, Ljiljana; Pevzner, Pavel A.

2013-11-05

Post-translational modifications (PTMs) play an important role in various biological processes through changing protein structure and function. Some ultramodified proteins (like histones) have multiple PTMs forming PTM patterns that define the functionality of a protein. While bottom-up mass spectrometry (MS) has been successful in identifying individual PTMs within short peptides, it is unable to identify PTM patterns spread along entire proteins in a coordinated fashion. In contrast, top-down MS analyzes intact proteins and reveals PTM patterns along the entire proteins. However, while recent advances in instrumentation have made top-down MS accessible to many laboratories, most computational tools for top-down MS focus on proteins with few PTMs and are unable to identify complex PTM patterns. We propose a new algorithm, MS-Align-E, that identifies both expected and unexpected PTMs in ultramodified proteins. We demonstrate that MS-Align-E identifies many protein forms of histone H4 and benchmark it against the currently accepted software tools.

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Effect of gate voltage polarity on the ionic liquid gating behavior of NdNiO3/NdGaO3 heterostructures

Directory of Open Access Journals (Sweden)

Yongqi Dong

2017-05-01

Full Text Available The effect of gate voltage polarity on the behavior of NdNiO3 epitaxial thin films during ionic liquid gating is studied using in situ synchrotron X-ray techniques. We show that while negative biases have no discernible effect on the structure or composition of the films, large positive gate voltages result in the injection of a large concentration of oxygen vacancies (∼3% and pronounced lattice expansion (0.17% in addition to a 1000-fold increase in sheet resistance at room temperature. Despite the creation of large defect densities, the heterostructures exhibit a largely reversible switching behavior when sufficient time is provided for the vacancies to migrate in and out of the thin film surface. The results confirm that electrostatic gating takes place at negative gate voltages for p-type complex oxides while positive voltages favor the electrochemical reduction of Ni3+. Switching between positive and negative gate voltages therefore involves a combination of electronic and ionic doping processes that may be utilized in future electrochemical transistors.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

Science.gov (United States)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

Science.gov (United States)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

Transparent conducting oxide top contacts for organic electronics

KAUST Repository

Franklin, Joseph B.

2014-01-01

A versatile method for the deposition of transparent conducting oxide (TCO) layers directly onto conjugated polymer thin film substrates is presented. Using pulsed laser deposition (PLD) we identify a narrow window of growth conditions that permit the deposition of highly transparent, low sheet resistance aluminium-doped zinc oxide (AZO) without degradation of the polymer film. Deposition on conjugated polymers mandates the use of low growth temperatures (<200°C), here we deposit AZO onto poly-3-hexylthiophene (P3HT) thin films at 150°C, and investigate the microstructural and electrical properties of the AZO as the oxygen pressure in the PLD chamber is varied (5-75 mTorr). The low oxygen pressure conditions previously optimized for AZO deposition on rigid substrates are shown to be unsuitable, resulting in catastrophic damage of the polymer films. By increasing the oxygen pressure, thus reducing the energy of the ablated species, we identify conditions that allow direct deposition of continuous, transparent AZO films without P3HT degradation. We find that uptake of oxygen into the AZO films reduces the intrinsic charge carriers and AZO films with a measured sheet resistance of approximately 500 Ω □-1 can be prepared. To significantly reduce this value we identify a novel process in which AZO is deposited over a range of oxygen pressures-enabling the deposition of highly transparent AZO with sheet resistances below 50 Ω □-1 directly onto P3HT. We propose these low resistivity films are widely applicable as transparent top-contacts in a range of optoelectronic devices and highlight this by demonstrating the operation of a semi-transparent photovoltaic device. © 2014 The Royal Society of Chemistry. 2014.

Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface

Science.gov (United States)

McKee, Rodney A.; Walker, Frederick J.

2003-11-25

A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film consists of a first epitaxial stratum of single atomic plane layers of an alkaline earth oxide designated generally as (AO).sub.n and a second stratum of single unit cell layers of an oxide material designated as (A'BO.sub.3).sub.m so that the multilayer film arranged upon the substrate surface is designated (AO).sub.n (A'BO.sub.3).sub.m wherein n is an integer repeat of single atomic plane layers of the alkaline earth oxide AO and m is an integer repeat of single unit cell layers of the A'BO.sub.3 oxide material. Within the multilayer film, the values of n and m have been selected to provide the structure with a desired electrical structure at the substrate/thin film interface that can be optimized to control band offset and alignment.

Self-gated fetal cardiac MRI with tiny golden angle iGRASP: A feasibility study.

Science.gov (United States)

Haris, Kostas; Hedström, Erik; Bidhult, Sebastian; Testud, Frederik; Maglaveras, Nicos; Heiberg, Einar; Hansson, Stefan R; Arheden, Håkan; Aletras, Anthony H

2017-07-01

To develop and assess a technique for self-gated fetal cardiac cine magnetic resonance imaging (MRI) using tiny golden angle radial sampling combined with iGRASP (iterative Golden-angle RAdial Sparse Parallel) for accelerated acquisition based on parallel imaging and compressed sensing. Fetal cardiac data were acquired from five volunteers in gestational week 29-37 at 1.5T using tiny golden angles for eddy currents reduction. The acquired multicoil radial projections were input to a principal component analysis-based compression stage. The cardiac self-gating (CSG) signal for cardiac gating was extracted from the acquired radial projections and the iGRASP reconstruction procedure was applied. In all acquisitions, a total of 4000 radial spokes were acquired within a breath-hold of less than 15 seconds using a balanced steady-state free precession pulse sequence. The images were qualitatively compared by two independent observers (on a scale of 1-4) to a single midventricular cine image from metric optimized gating (MOG) and real-time acquisitions. For iGRASP and MOG images, good overall image quality (2.8 ± 0.4 and 2.6 ± 1.3, respectively, for observer 1; 3.6 ± 0.5 and 3.4 ± 0.9, respectively, for observer 2) and cardiac diagnostic quality (3.8 ± 0.4 and 3.4 ± 0.9, respectively, for observer 1; 3.6 ± 0.5 and 3.6 ± 0.9, respectively, for observer 2) were obtained, with visualized myocardial thickening over the cardiac cycle and well-defined myocardial borders to ventricular lumen and liver/lung tissue. For iGRASP, MOG, and real time, left ventricular lumen diameter (14.1 ± 2.2 mm, 14.2 ± 1.9 mm, 14.7 ± 1.1 mm, respectively) and wall thickness (2.7 ± 0.3 mm, 2.6 ± 0.3 mm, 3.0 ± 0.4, respectively) showed agreement and no statistically significant difference was found (all P > 0.05). Images with iGRASP tended to have higher overall image quality scores compared with MOG and particularly

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

Science.gov (United States)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Arrangement and method for attaching and reattaching a top nozzle in a reconstitutable nuclear fuel assembly

International Nuclear Information System (INIS)

Wilson, J.F.; Gjertsen, R.K.; Mayers, J.B.

1987-01-01

This patent describes a reconstitutable fuel assembly having at least one control rod guide thimble and a top nozzle. The guide thimble includes an upper end portion. The top nozzle includes a lower adapter plate and an upper hold-down plate. The lower and upper plates have respectively an opening and passageway defined therethrough and aligned with one another. The opening in the lower plate receiving the guide thimble therethrough with its upper end portion extends above the lower plate and towards the passageway of the upper plate. An improved arrangement for mounting the top nozzle on the guide thimble is described comprising: (a) alignment means extending between the plates and receiving the guide thimble upper end portion, (b) complementary means formed on and interconnecting the alignment means and the guide thimble upper end portion so as to connect the alignment means and the guide thimble together. (c) The complementary means further include a secondary interior annular groove formed on the alignment means at a location spaced below the primary annular groove; (d) The complementary means still further include a primary interior section on the alignment means which contains the primary annular groove and a secondary interior section on the alignment means which contains the secondary annular groove. The secondary section is disposed below the primary section and has an interior diameter larger than that of the primary section for facilitating receiving of the severed guide thimble upper end portion back into the alignment means for reconnection of the alignment means and the severed guide thimble together

Self-aligned metallization on organic semiconductor through 3D dual-layer thermal nanoimprint

International Nuclear Information System (INIS)

Jung, Y; Cheng, X

2014-01-01

High-resolution patterning of metal structures on organic semiconductors is important to the realization of high-performance organic transistors for organic integrated circuit applications. The traditional shadow mask technique has a limited resolution, precluding sub-micron metal structures on organic semiconductors. Thus organic transistors cannot benefit from scaling into the deep sub-micron region to improve their dc and ac performances. In this work, we report an efficient multiple-level metallization on poly (3-hexylthiophene) (P3HT) with a deep sub-micron lateral gap. By using a 3D nanoimprint mold in a dual-layer thermal nanoimprint process, we achieved self-aligned two-level metallization on P3HT. The 3D dual-layer thermal nanoimprint enables the first metal patterns to have suspending side-wings that can clearly define a distance from the second metal patterns. Isotropic and anisotropic side-wing structures can be fabricated through two different schemes. The process based on isotropic side-wings achieves a lateral-gap in the order of 100 nm (scheme 1). A gap of 60 nm can be achieved from the process with anisotropic side-wings (scheme 2). Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be utilized to fabricate high-performance organic metal semiconductor field-effect transistor. (paper)

Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

Science.gov (United States)

Li, Jia-dong; Cheng, Jun-jie; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Zhang, Jin-cheng; Zhang, Zhi-qiang; Wu, Dong-min

2014-07-01

In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening.

Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Li, Jia-dong; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Wu, Dong-min; Cheng, Jun-jie; Zhang, Jin-cheng; Zhang, Zhi-qiang

2014-01-01

In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening. (paper)

Synthesis, transfer printing, electrical and optical properties, and applications of materials composed of self-assembled, aligned single-walled carbon nanotubes

Science.gov (United States)

Pint, Cary L.

Super growth of single-walled carbon nanotubes (SWNTs) has emerged as a unique method for synthesizing self-assembled, pristine, aligned SWNT materials composed of ultra-long (millimeter-long) nanotubes. This thesis focuses on novel routes of synthesizing such self-assembled SWNTs and the challenges that arise in integrating this material into next-generation applications. First of all, this work provides unique insight into growth termination of aligned SWNTs, emphasizing the mechanism that inhibits the growth of infinitely long nanotubes. Exhaustive real-time growth studies, combined with ex-situ and in-situ TEM characterization emphasizes that Ostwald ripening and subsurface diffusion of catalyst particles play a key role in growth termination. As a result, rational steps to solving this problem can enhance growth, and may ultimately lead to the meter or kilometer-long SWNTs that are necessary for a number of applications. In addition, other novel synthesis routes are discussed, such as the ability to form macroscopic fibrils of SWNTs, called "flying carpets" from 40 nm thick substrates, and the ability to achieve supergrowth of SWNTs that are controllably doped with nitrogen. In the latter case, molecular heterojunctions of doped and undoped sections in a single strand of ultralong SWNTs are demonstrated Secondly, as supergrowth is conducted on alumina coated SiO2 substrates, any applications will require that one can transfer the SWNTs to host surfaces with minimal processing. This work demonstrates a unique contact transfer route by which both patterned arrays of SWNTs, or homogenous SWNT carpets, can be transferred to any host surface. In the first case, the SWNTs are grown vertically aligned, and transferred in patterns of horizontally aligned SWNT. This transfer process relies on simple water-vapor etching of amorphous carbons at the catalyst following growth, and strong van der Waals adhesion of the high surface-area SWNT to host surfaces (gecko effect

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

Science.gov (United States)

Han, Kefeng; Zhu, Lin

2017-09-01

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

Leveraging FPGAs for Accelerating Short Read Alignment.

Science.gov (United States)

Arram, James; Kaplan, Thomas; Luk, Wayne; Jiang, Peiyong

2017-01-01

One of the key challenges facing genomics today is how to efficiently analyze the massive amounts of data produced by next-generation sequencing platforms. With general-purpose computing systems struggling to address this challenge, specialized processors such as the Field-Programmable Gate Array (FPGA) are receiving growing interest. The means by which to leverage this technology for accelerating genomic data analysis is however largely unexplored. In this paper, we present a runtime reconfigurable architecture for accelerating short read alignment using FPGAs. This architecture exploits the reconfigurability of FPGAs to allow the development of fast yet flexible alignment designs. We apply this architecture to develop an alignment design which supports exact and approximate alignment with up to two mismatches. Our design is based on the FM-index, with optimizations to improve the alignment performance. In particular, the n-step FM-index, index oversampling, a seed-and-compare stage, and bi-directional backtracking are included. Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs. Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5-2640 CPUs, and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

International Nuclear Information System (INIS)

Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

2014-01-01

Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO 2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics

Functional alignments and self-tests for tilted and decentered optics

International Nuclear Information System (INIS)

Bauke, W.; Cross, E.W.

1983-01-01

The alignment of tilted and decentered optics is ordinarily difficult, because such optics have neither simple alignment points amenable to ordinary boresight methods, nor a simple alignment theory. Several different alignment examples which provide insight into a practical universal approach to all such systems are explored. The examples detailed are segments of the Antares Laser Fusion Project's optical train

Effect of laser pulse shaping parameters on the fidelity of quantum logic gates.

Science.gov (United States)

Zaari, Ryan R; Brown, Alex

2012-09-14

The effect of varying parameters specific to laser pulse shaping instruments on resulting fidelities for the ACNOT(1), NOT(2), and Hadamard(2) quantum logic gates are studied for the diatomic molecule (12)C(16)O. These parameters include varying the frequency resolution, adjusting the number of frequency components and also varying the amplitude and phase at each frequency component. A time domain analytic form of the original discretized frequency domain laser pulse function is derived, providing a useful means to infer the resulting pulse shape through variations to the aforementioned parameters. We show that amplitude variation at each frequency component is a crucial requirement for optimal laser pulse shaping, whereas phase variation provides minimal contribution. We also show that high fidelity laser pulses are dependent upon the frequency resolution and increasing the number of frequency components provides only a small incremental improvement to quantum gate fidelity. Analysis through use of the pulse area theorem confirms the resulting population dynamics for one or two frequency high fidelity laser pulses and implies similar dynamics for more complex laser pulse shapes. The ability to produce high fidelity laser pulses that provide both population control and global phase alignment is attributed greatly to the natural evolution phase alignment of the qubits involved within the quantum logic gate operation.

Impacts of gate bias and its variation on gamma-ray irradiation resistance of SiC MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Murata, Koichi; Mitomo, Satoshi; Matsuda, Takuma; Yokoseki, Takashi [Saitama University, Sakuraku (Japan); National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Makino, Takahiro; Onoda, Shinobu; Takeyama, Akinori; Ohshima, Takeshi [National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Okubo, Shuichi; Tanaka, Yuki; Kandori, Mikio; Yoshie, Toru [Sanken Electric Co., Ltd., Niiza, Saitama (Japan); Hijikata, Yasuto [Saitama University, Sakuraku (Japan)

2017-04-15

Gamma-ray irradiation into vertical type n-channel hexagonal (4H)-silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) was performed under various gate biases. The threshold voltage for the MOSFETs irradiated with a constant positive gate bias showed a large negative shift, and the shift slightly recovered above 100 kGy. For MOSFETs with non- and a negative constant biases, no significant change in threshold voltage, V{sub th}, was observed up to 400 kGy. By changing the gate bias from positive bias to either negative or non-bias, the V{sub th} significantly recovered from the large negative voltage shift induced by 50 kGy irradiation with positive gate bias after only 10 kGy irradiation with either negative or zero bias. It indicates that the positive charges generated in the gate oxide near the oxide-SiC interface due to irradiation were removed or recombined instantly by the irradiation under zero or negative biases. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Four-dimensional (4D) flow of the whole heart and great vessels using real-time respiratory self-gating

DEFF Research Database (Denmark)

Uribe, Sergio; Beerbaum, Philipp; Sørensen, Thomas Sangild

2009-01-01

Four-dimensional (4D) flow imaging has been used to study flow patterns and pathophysiology, usually focused on specific thoracic vessels and cardiac chambers. Whole-heart 4D flow at high measurement accuracy covering the entire thoracic cardiovascular system would be desirable to simplify...... and improve hemodynamic assessment. This has been a challenge because compensation of respiratory motion is difficult to achieve, but it is paramount to limit artifacts and improve accuracy. In this work we propose a self-gating technique for respiratory motion-compensation integrated into a whole-heart 4D...... flow acquisition that overcomes these challenges. Flow components are measured in all three directions for each pixel over the complete cardiac cycle, and 1D volume projections are obtained at certain time intervals for respiratory gating in real time during the acquisition. The technique was tested...

Dual-gate operation and carrier transport in SiGe p-n junction nanowires

Science.gov (United States)

Delker, C. J.; Yoo, J. Y.; Bussmann, E.; Swartzentruber, B. S.; Harris, C. T.

2017-11-01

We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.