Logic circuits from zero forcing.

Science.gov (United States)

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

Logic-type Schmitt circuit using multi-valued gates

Science.gov (United States)

Wakui, M.; Tanaka, M.

Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.

Fluid logic control circuit operates nutator actuator motor

Science.gov (United States)

1966-01-01

Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

Digital logic circuit test

Energy Technology Data Exchange (ETDEWEB)

Yun, Gil Jung; Yang, Hong Young

2011-03-15

This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

Design, Analysis and Test of Logic Circuits Under Uncertainty

CERN Document Server

Krishnaswamy, Smita; Hayes, John P

2013-01-01

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

A parity checker circuit based on microelectromechanical resonator logic elements

KAUST Repository

Hafiz, Md Abdullah Al

2017-01-11

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

A parity checker circuit based on microelectromechanical resonator logic elements

KAUST Repository

Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein

2017-01-01

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

Miniaturization of Josephson logic circuits

International Nuclear Information System (INIS)

Ko, H.; Van Duzer, T.

1985-01-01

The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

Logic circuits based on molecular spider systems.

Science.gov (United States)

Mo, Dandan; Lakin, Matthew R; Stefanovic, Darko

2016-08-01

Spatial locality brings the advantages of computation speed-up and sequence reuse to molecular computing. In particular, molecular walkers that undergo localized reactions are of interest for implementing logic computations at the nanoscale. We use molecular spider walkers to implement logic circuits. We develop an extended multi-spider model with a dynamic environment wherein signal transmission is triggered via localized reactions, and use this model to implement three basic gates (AND, OR, NOT) and a cascading mechanism. We develop an algorithm to automatically generate the layout of the circuit. We use a kinetic Monte Carlo algorithm to simulate circuit computations, and we analyze circuit complexity: our design scales linearly with formula size and has a logarithmic time complexity. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

LOGIC CIRCUIT

Science.gov (United States)

Strong, G.H.; Faught, M.L.

1963-12-24

A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Design of synthetic biological logic circuits based on evolutionary algorithm.

Science.gov (United States)

Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei

2013-08-01

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

Explicit logic circuits discriminate neural states.

Directory of Open Access Journals (Sweden)

Lane Yoder

Full Text Available The magnitude and apparent complexity of the brain's connectivity have left explicit networks largely unexplored. As a result, the relationship between the organization of synaptic connections and how the brain processes information is poorly understood. A recently proposed retinal network that produces neural correlates of color vision is refined and extended here to a family of general logic circuits. For any combination of high and low activity in any set of neurons, one of the logic circuits can receive input from the neurons and activate a single output neuron whenever the input neurons have the given activity state. The strength of the output neuron's response is a measure of the difference between the smallest of the high inputs and the largest of the low inputs. The networks generate correlates of known psychophysical phenomena. These results follow directly from the most cost-effective architectures for specific logic circuits and the minimal cellular capabilities of excitation and inhibition. The networks function dynamically, making their operation consistent with the speed of most brain functions. The networks show that well-known psychophysical phenomena do not require extraordinarily complex brain structures, and that a single network architecture can produce apparently disparate phenomena in different sensory systems.

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Park, Gun Jong; Lee, Ju Heon

2006-09-01

This book is composed of five parts. The first part has introduction of ALTERA MAX+PLUS II and graphic editor, text editor, compiler, waveform editor simulator and timing analyzer of it. The second part is about direction of digital logic circuit design with training kit. The third part has grammar and practice of VHDL in ALTERA MAX+PLUS II including example and history of VHDL. The fourth part shows the design example of digital logic circuit by VHDL of ALTERA MAX+PLUS II which lists designs of adder and subtractor, code converter, counter, state machine and LCD module. The last part explains design example of digital logic circuit by graphic editor in ALTERA MAX+PLUS II.

Superconducting push-pull flux quantum logic circuits

International Nuclear Information System (INIS)

Murphy, J.H.; Daniel, M.R.; Przybysz, J.X.

1993-01-01

A superconducting digital logic circuit is described comprising: a first circuit branch including first and second Josephson junctions electrically connected in series with each other; means for applying a positive bias voltage to a first end of said circuit branch; means for applying a negative bias voltage to a second end of said circuit branch; means for applying a first dual polarity input voltage signal to a first node in said circuit branch; and means for extracting a first output voltage signal from said first node in said circuit branch

Safety logic systems of PFBR

International Nuclear Information System (INIS)

Sambasivan, S. Ilango

2004-01-01

Full text : PFBR is provided with two independent, fast acting and diverse shutdown systems to detect any abnormalities and to initiate safety action. Each system consists of sensors, signal processing systems, logics, drive mechanisms and absorber rods. The absorber rods of the first system are Control and Safety Rods (CSR) and that of the second are called as Diverse Safety Rods (DSR). There are nine CSR and three DSR. While CSR are used for startup, control of reactor power, controlled shutdown and SCRAM, the DSR are used only for SCRAM. The respective drive mechanisms are called as CSRDM and DSRDM. Each of these two systems is capable of executing the shutdown satisfactorily with single failure criteria. Two independent safety logic systems based on diverse principles have been designed for the two shut down systems. The analog outputs of the sensors of Core Monitoring Systems comprising of reactor flux monitoring, core temperature monitoring, failed fuel detection and core flow monitoring systems are processed and converted into binary signals depending on their instantaneous values. Safety logic systems receive the binary signals from these core-monitoring systems and process them logically to protect the reactor against postulated initiating events. Neutronic and power to flow (P/Q) signals form the inputs to safety logic system-I and temperature signals are inputs to the safety logic system II. Failed fuel detection signals are processed by both the shut down systems. The two logic systems to actuate the safety rods are also based on two diverse designs and implemented with solid-state devices to meet all the requirements of safety systems. Safety logic system I that caters to neutronic and P/Q signals is designed around combinational logic and has an on-line test facility to detect struck at faults. The second logic system is based on dynamic logic and hence is inherently safe. This paper gives an overview of the two logic systems that have been

Designable DNA-binding domains enable construction of logic circuits in mammalian cells.

Science.gov (United States)

Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman

2014-03-01

Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.

Integrated circuits and logic operations based on single-layer MoS2.

Science.gov (United States)

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

Magnonic interferometric switch for multi-valued logic circuits

Science.gov (United States)

Balynsky, Michael; Kozhevnikov, Alexander; Khivintsev, Yuri; Bhowmick, Tonmoy; Gutierrez, David; Chiang, Howard; Dudko, Galina; Filimonov, Yuri; Liu, Guanxiong; Jiang, Chenglong; Balandin, Alexander A.; Lake, Roger; Khitun, Alexander

2017-01-01

We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-scale logic gates, and minimize energy per operation, which is limited only by the noise margin. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. We describe possible implementation of the three-value logic circuits based on the magnonic interferometric switches. The advantages and shortcomings inherent in interferometric switches are also discussed.

Pulse coded safety logic for PFBR

International Nuclear Information System (INIS)

Anwer, Md. Najam; Satheesh, N.; Nagaraj, C.P.; Krishnakumar, B.

2002-01-01

Full text: Reactor safety logic is designed to initiate safety action against design basis events. The reactor is shutdown by de-energizing electromagnets and dropping the absorber rods under gravity. In prototype fast breeder reactor (PFBR), shutdown is affected by two independent shutdown systems, viz., control and safety rod drive mechanism (CSRDM) and diverse safety rod drive mechanism (DSRDM). Two separate safety logics are proposed for CSRDM and DSRDM, i.e. solid state logic with on-line fine impulse test (FIT) for CSRDM and pulse coded safety logic (PCSL) for DSRDM. The PCSL primarily utilizes the fact that the vast majority of faults in the logic circuitry result in static conditions at the output. It is arranged such that the presence of pulses are required to hold the shutdown actuators and any DC logic state, either logic 0 or logic 1 releases them. It is a dynamic, self-testing logic and used in a number of reactors. This paper describes the principle of operation of PCSL, its advantages, the concept of guard line logic (GLL), detection of stuck at 0 and stuck at 1 faults, fail safe and diversity features. The implementation of PCSL using Altera Max+Plus II software for PFBR trip signals and the results of simulation are discussed. This paper also describes a test jig using 80186 based system for testing PCSL for various input parameter's combinations and monitoring the outputs

Explicit logic circuits predict local properties of the neocortex's physiology and anatomy.

Directory of Open Access Journals (Sweden)

Lane Yoder

Full Text Available BACKGROUND: Two previous articles proposed an explicit model of how the brain processes information by its organization of synaptic connections. The family of logic circuits was shown to generate neural correlates of complex psychophysical phenomena in different sensory systems. METHODOLOGY/PRINCIPAL FINDINGS: Here it is shown that the most cost-effective architectures for these networks produce correlates of electrophysiological brain phenomena and predict major aspects of the anatomical structure and physiological organization of the neocortex. The logic circuits are markedly efficient in several respects and provide the foundation for all of the brain's combinational processing of information. CONCLUSIONS/SIGNIFICANCE: At the local level, these networks account for much of the physical structure of the neocortex as well its organization of synaptic connections. Electronic implementations of the logic circuits may be more efficient than current electronic logic arrays in generating both Boolean and fuzzy logic.

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Nanoeletromechanical switch and logic circuits formed therefrom

Science.gov (United States)

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

International Nuclear Information System (INIS)

Lashin, A. V.; Kozyrev, A. V.

2015-01-01

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

Synthesis of logic circuits with evolutionary algorithms

Energy Technology Data Exchange (ETDEWEB)

JONES,JAKE S.; DAVIDSON,GEORGE S.

2000-01-26

In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Research on uranium resource models. Part IV. Logic: a computer graphics program to construct integrated logic circuits for genetic-geologic models. Progress report

International Nuclear Information System (INIS)

Scott, W.A.; Turner, R.M.; McCammon, R.B.

1981-01-01

Integrated logic circuits were described as a means of formally representing genetic-geologic models for estimating undiscovered uranium resources. The logic circuits are logical combinations of selected geologic characteristics judged to be associated with particular types of uranium deposits. Each combination takes on a value which corresponds to the combined presence, absence, or don't know states of the selected characteristic within a specified geographic cell. Within each cell, the output of the logic circuit is taken as a measure of the favorability of occurrence of an undiscovered deposit of the type being considered. In this way, geological, geochemical, and geophysical data are incorporated explicitly into potential uranium resource estimates. The present report describes how integrated logic circuits are constructed by use of a computer graphics program. A user's guide is also included

Magnetic Logic Circuits for Extreme Environments, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The program aims to demonstrate a new genre of all-magnetic logic circuits which are radiation-tolerant and capable of reliable operation in extreme environmental...

A logic circuit for solving linear function by digital method

International Nuclear Information System (INIS)

Ma Yonghe

1986-01-01

A mathematical method for determining the linear relation of physical quantity with rediation intensity is described. A logic circuit has been designed for solving linear function by digital method. Some applications and the circuit function are discussed

Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields

International Nuclear Information System (INIS)

Inoue, Kenta; Narama, Tatsuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki; Takeuchi, Naoki

2015-01-01

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells. (paper)

Experimental investigation of a four-qubit linear-optical quantum logic circuit.

Science.gov (United States)

Stárek, R; Mičuda, M; Miková, M; Straka, I; Dušek, M; Ježek, M; Fiurášek, J

2016-09-20

We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and several two-qubit and single-qubit gates. The C(3)Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.

A novel ternary logic circuit using Josephson junction

International Nuclear Information System (INIS)

Morisue, M.; Oochi, K.; Nishizawa, M.

1989-01-01

This paper describes a novel Josephson complementary ternary logic circuit named as JCTL. This fundamental circuit is constructed by combination of two SQUIDs, one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. The results of the simulation show that the reliable operations of these circuits can be achieved with a high performance

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Lee, Ju Heon

2006-03-01

Contents of this book are the kinds of integrated circuit, design process of integrated circuit, introduction of ALTERA MAX+PLUS II, designing logic circuit with VHDL of ALTERA MAX+PLUS II, grammar and practice of VHDL of ALTERA MAX+PLUS II, design for adder, subtractor, parallel binary subtractor, BCD design, CLA design, code converter design, ALU design, register design, counter design, accumulator design, state machine design, frequency divider design, circuit design with TENMILLION counter, LCD module, circuit design for control the outside RAM in training kit and introduction for HEB-DTK-20K-240/HBE-DTK-IOK.

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

Science.gov (United States)

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Designing reversible arithmetic, logic circuit to implement micro-operation in quantum computation

International Nuclear Information System (INIS)

Kalita, Gunajit; Saikia, Navajit

2016-01-01

The futuristic computing is desired to be more power full with low-power consumption. That is why quantum computing has been a key area of research for quite some time and is getting more and more attention. Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times. Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance. In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer. The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations. The quantum costs of these designs are comparable. Many of the implemented micro-operations are not seen in previous literatures. The performances of the proposed circuits are compared with existing designs wherever available. (paper)

Towards electromechanical computation: An alternative approach to realize complex logic circuits

KAUST Repository

Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.

2016-01-01

Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.

Towards electromechanical computation: An alternative approach to realize complex logic circuits

KAUST Repository

Hafiz, M. A. A.

2016-08-18

Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.

Reconfigurable chaotic logic gates based on novel chaotic circuit

International Nuclear Information System (INIS)

Behnia, S.; Pazhotan, Z.; Ezzati, N.; Akhshani, A.

2014-01-01

Highlights: • A novel method for implementing logic gates based on chaotic maps is introduced. • The logic gates can be implemented without any changes in the threshold voltage. • The chaos-based logic gates may serve as basic components of future computing devices. - Abstract: The logical operations are one of the key issues in today’s computer architecture. Nowadays, there is a great interest in developing alternative ways to get the logic operations by chaos computing. In this paper, a novel implementation method of reconfigurable logic gates based on one-parameter families of chaotic maps is introduced. The special behavior of these chaotic maps can be utilized to provide same threshold voltage for all logic gates. However, there is a wide interval for choosing a control parameter for all reconfigurable logic gates. Furthermore, an experimental implementation of this nonlinear system is presented to demonstrate the robustness of computing capability of chaotic circuits

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

Science.gov (United States)

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

Geometrical considerations in the transient ionization testing of digital logic circuits

International Nuclear Information System (INIS)

Johnston, A.

1982-01-01

Mechanisms are identified that can cause the transient response of digital logic circuits to depend on the logic state in which they are irradiated. Several of these mechanisms depend on surface topology, and for these cases the sensitive logic states can be determined by examining the topology. General approaches for transient radiation testing are also discussed for several MSI and LSI device technologies

Emergency Diesel: Safety-related instrumentation and control with programmable logic controllers

International Nuclear Information System (INIS)

Breidenich, G.; Luedtke, M.

2004-01-01

This report presents a new concept for the design of emergency diesel equipment protection circuits as a part of the safety related instrumentation in the nuclear power plant Biblis, units A and B. The concept was implemented with state of the art SIMATIC S7/316 programmable logic controllers (PLCs) and can be adapted to any system with high availability requirements (e.g. power plant turbines, aircraft engines, mining pumps etc). (orig.)

Nonlinear dynamics based digital logic and circuits.

Science.gov (United States)

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Methods and Tools for the Analysis, Verification and Synthesis of Genetic Logic Circuits,

DEFF Research Database (Denmark)

Baig, Hasan

2017-01-01

. This usually requires simulating the mathematical models of these genetic circuits and perceive whether or not the circuit behaves appropriately. Furthermore, synthetic biology utilizes the concepts from electronic design automation (EDA) of abstraction and automated construction to generate genetic circuits...... that the proposed approach is effective to determine the variation in the behavior of genetic circuits when the circuit’s parameters are changed. In addition, the thesis also attempts to propose a synthesis and technology mapping tool, called GeneTech, for genetic circuits. It allows users to construct a genetic...... important design characteristics. This thesis also introduces an automated approach to analyze the behavior of genetic logic circuits from the simulation data. With this capability, the boolean logic of complex genetic circuits can be analyzed and/or verified automatically. It is also shown in this thesis...

Time-space modal logic for verification of bit-slice circuits

Science.gov (United States)

Hiraishi, Hiromi

1996-03-01

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

Practical design of digital circuits basic logic to microprocessors

CERN Document Server

Kampel, Ian

1983-01-01

Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

Circuits design of action logics of the protection system of nuclear reactor IAN-R1 of Colombia

International Nuclear Information System (INIS)

Gonzalez M, J. L.; Rivero G, T.; Sainz M, E.

2014-10-01

Due to the obsolescence of the instrumentation and control system of the nuclear research reactor IAN-R1, the Institute of Geology and Mining of Colombia, IngeoMinas, launched an international convoking for renewal it which was won by the Instituto Nacional de Investigaciones Nucleares (ININ). Within systems to design, the reactor protection system is described as important for safety, because this carried out, among others two primary functions: 1) ensuring the reactor shutdown safely, and 2) controlling the interlocks to protect against operational errors if defined conditions have not been met. To fulfill these functions, the various subsystems related to the safety report the state in which they are using binary signals and are connected to the inputs of two redundant logic wiring circuits called action logics (Al) that are part of the reactor protection system. These Al also serve as logical interface to indicate at all times the status of subsystems, both the operator and other systems. In the event that any of the subsystems indicates a state of insecurity in the reactor, the Al generate signals off (or scram) of the reactor, maintaining the interlock until the operator sends a reset signal. In this paper the design, implementation, verification and testing of circuits that make up the Al 1 and 2 of IAN-R1 reactor is described, considering the fulfillment of the requirements that the different international standards imposed on this type of design. (Author)

Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

International Nuclear Information System (INIS)

Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

2010-01-01

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

A transition calculus for Boolean functions. [logic circuit analysis

Science.gov (United States)

Tucker, J. H.; Bennett, A. W.

1974-01-01

A transition calculus is presented for analyzing the effect of input changes on the output of logic circuits. The method is closely related to the Boolean difference, but it is more powerful. Both differentiation and integration are considered.

A novel three-input monomolecular logic circuit on a rhodamine inspired bio-compatible bi-compartmental molecular platform

International Nuclear Information System (INIS)

Mistri, Tarun; Bhowmick, Rahul; Katarkar, Atul; Chaudhuri, Keya; Ali, Mahammad

2017-01-01

Methodological synthesis of a new biocompatible bi-compartmental rhodamine based probe (L 3 ) provides a multi-inputs and multi-outputs molecular logic circuit based on simple chemosensing phenomena. Spectroscopic responses of Cu 2+ and Hg 2+ towards L 3 together with reversible binding of S 2- with L 3 -Cu 2+ and L 3 -Hg 2+ complexes help us to construct a thee-input molecular circuit on their control and sequential addition to a solution of L 3 in a mixed organo-aqueous medium. We have further successfully encoded binary digits out of these inputs and outputs which may convert a three-digit input string into a two-digit output string resulting a simple monomolecular logic circuit. Such a molecular ‘Boolean’ logic operation may improve the complexity of logic gate circuitry and computational speed and may be useful to employ in potential biocompatible molecular logic platforms. - Graphical abstract: A new bi-compartmental molecular system equipped with Rhodamine fluorophore unit provides a Multi-inputs and Multi-outputs Molecular Logic Circuit based on a very simple observation of chemosensing activities.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Science.gov (United States)

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Analysis and synthesis of a logic control circuit by binary analysis methods

International Nuclear Information System (INIS)

Chicheportiche, Armand

1974-06-01

The analytical study of the logic circuits described in this report clearly shows the fruitful efficiency of the methods proposed by Binary Analysis. This study is a very new approach in logic and these mathematical methods are systematically precise in their applications. The detailed operations of an automatic system are to be studied in a way which cannot be reached by other methods. The definition and utilization of transition equations allow the determination of the different commutations in the auxiliary switch functions of a sequential system. This new way of analysis digital circuits will certainly develop in a very near future [fr

Statistical analysis of error rate of large-scale single flux quantum logic circuit by considering fluctuation of timing parameters

International Nuclear Information System (INIS)

Yamanashi, Yuki; Masubuchi, Kota; Yoshikawa, Nobuyuki

2016-01-01

The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.

Statistical analysis of error rate of large-scale single flux quantum logic circuit by considering fluctuation of timing parameters

Energy Technology Data Exchange (ETDEWEB)

Yamanashi, Yuki, E-mail: yamanasi@ynu.ac.jp [Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501 (Japan); Masubuchi, Kota; Yoshikawa, Nobuyuki [Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501 (Japan)

2016-11-15

The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.

Science.gov (United States)

Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

2010-01-01

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Science.gov (United States)

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

A novel three-input monomolecular logic circuit on a rhodamine inspired bio-compatible bi-compartmental molecular platform

Energy Technology Data Exchange (ETDEWEB)

Mistri, Tarun; Bhowmick, Rahul [Department of Chemistry, Jadavpur University, 188 Raja S.C. Mullick Road, Kolkata 700032 (India); Katarkar, Atul; Chaudhuri, Keya [Molecular & Human Genetics Division, CSIR-Indian Institute of Chemical Biology, 4 Raja S.C. Mullick Road, Kolkata 700032 (India); Ali, Mahammad, E-mail: mali@chemistry.jdvu.ac.in [Department of Chemistry, Jadavpur University, 188 Raja S.C. Mullick Road, Kolkata 700032 (India)

2017-05-15

Methodological synthesis of a new biocompatible bi-compartmental rhodamine based probe (L{sup 3}) provides a multi-inputs and multi-outputs molecular logic circuit based on simple chemosensing phenomena. Spectroscopic responses of Cu{sup 2+} and Hg{sup 2+} towards L{sup 3} together with reversible binding of S{sup 2-} with L{sup 3}-Cu{sup 2+} and L{sup 3}-Hg{sup 2+} complexes help us to construct a thee-input molecular circuit on their control and sequential addition to a solution of L{sup 3} in a mixed organo-aqueous medium. We have further successfully encoded binary digits out of these inputs and outputs which may convert a three-digit input string into a two-digit output string resulting a simple monomolecular logic circuit. Such a molecular ‘Boolean’ logic operation may improve the complexity of logic gate circuitry and computational speed and may be useful to employ in potential biocompatible molecular logic platforms. - Graphical abstract: A new bi-compartmental molecular system equipped with Rhodamine fluorophore unit provides a Multi-inputs and Multi-outputs Molecular Logic Circuit based on a very simple observation of chemosensing activities.

Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)

Science.gov (United States)

Karmakar, Supriya

2014-10-01

This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.

Single-flux-quantum logic circuits exploiting collision-based fusion gates

International Nuclear Information System (INIS)

Asai, T.; Yamada, K.; Amemiya, Y.

2008-01-01

We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock

Digital logic circuit design with ALTERA Quartus II

International Nuclear Information System (INIS)

Lee, Seung Ho

2009-09-01

This book consists 31 chapters about digital logic circuit with ALTERA Quartus II. It includes the introduction of ALTERA Quartus II, ALTERA Quartus II schematic editor, ALTERA Quartus II compiler, ALTERA Quartus II simulator, ALTERA Quartus II timing analyzer, how to use HBE-COMBO II training and HBE-COMBO II training kit with schematic editor, VHDL grammar and practice of ALTERA Quartus II and HBE-COMBO II training kit with VHDL.

Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

International Nuclear Information System (INIS)

Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

2015-01-01

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

Design automation for integrated nonlinear logic circuits (Conference Presentation)

Science.gov (United States)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

Relaxation oscillation logic in Josephson junction circuits

International Nuclear Information System (INIS)

Fulton, T.A.

1981-01-01

A dc powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the dc bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed

Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates

Science.gov (United States)

Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda

2012-01-01

One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039

Complex logic functions implemented with quantum dot bionanophotonic circuits.

Science.gov (United States)

Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2014-03-26

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

Science.gov (United States)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

Synthesis of Ternary Quantum Logic Circuits by Decomposition

OpenAIRE

Khan, Faisal Shah; Perkowski, Marek

2005-01-01

Recent research in multi-valued logic for quantum computing has shown practical advantages for scaling up a quantum computer. Multivalued quantum systems have also been used in the framework of quantum cryptography, and the concept of a qudit cluster state has been proposed by generalizing the qubit cluster state. An evolutionary algorithm based synthesizer for ternary quantum circuits has recently been presented, as well as a synthesis method based on matrix factorization.In this paper, a re...

Integrated digital superconducting logic circuits for the quantum synthesizer. Report

International Nuclear Information System (INIS)

Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.

2006-11-01

This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-Al x O y /Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ

Regulatory Anatomy: How "Safety Logics" Structure European Transplant Medicine.

Science.gov (United States)

Hoeyer, Klaus

2015-07-01

This article proposes the term "safety logics" to understand attempts within the European Union (EU) to harmonize member state legislation to ensure a safe and stable supply of human biological material for transplants and transfusions. With safety logics, I refer to assemblages of discourses, legal documents, technological devices, organizational structures, and work practices aimed at minimizing risk. I use this term to reorient the analytical attention with respect to safety regulation. Instead of evaluating whether safety is achieved, the point is to explore the types of "safety" produced through these logics as well as to consider the sometimes unintended consequences of such safety work. In fact, the EU rules have been giving rise to complaints from practitioners finding the directives problematic and inadequate. In this article, I explore the problems practitioners face and why they arise. In short, I expose the regulatory anatomy of the policy landscape.

Boolean Reasoning and Informed Search in the Minimization of Logic Circuits

Science.gov (United States)

1992-03-01

between a symbolic representation of a PLA using Os and is and the physical layout of the function. 2. Computer-aided design (CAD) tools have made it easy...Svoboda, Antonin and Donnamaie White. Advanced Logical Circuit Design Tech- niques. New York: Garland STPM Press, 1979. [Tison 67] Tison, Pierre

Circuit Simulation of All-Spin Logic

KAUST Repository

Alawein, Meshal

2016-05-01

With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall

A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA.

Science.gov (United States)

Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool

2017-12-01

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

Calculation of the soft error rate of submicron CMOS logic circuits

International Nuclear Information System (INIS)

Juhnke, T.; Klar, H.

1995-01-01

A method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described. This method takes into account charge collection by drift and diffusion. The method is verified by comparison of calculated SER's to measurement results. Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 microm, 0.3 microm, and 0.12 microm technology, respectively. It has been found that the SER of such highly pipelined submicron CMOS circuits may become too high so that countermeasures have to be taken. Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs

Low latency asynchronous interface circuits

Science.gov (United States)

Sadowski, Greg

2017-06-20

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

MOS Current Mode Logic Near Threshold Circuits

Directory of Open Access Journals (Sweden)

Alexander Shapiro

2014-06-01

Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

Science.gov (United States)

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-01-01

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

Science.gov (United States)

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-04-13

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Safety valve opening and closing operation monitor

International Nuclear Information System (INIS)

Kodama, Kunio; Takeshima, Ikuo; Takahashi, Kiyokazu.

1981-01-01

Purpose: To enable the detection of the closing of a safety valve when the internal pressure in a BWR type reactor is a value which will close the safety valve, by inputting signals from a pressure detecting device mounted directly at a reactor vessel and a safety valve discharge pressure detecting device to an AND logic circuit. Constitution: A safety valve monitor is formed of a pressure switch mounted at a reactor pressure vessel, a pressure switch mounted at the exhaust pipe of the escape safety valve and a logic circuit and the lide. When the input pressure of the safety valve is raised so that the valve and the pressure switch mounted at the exhaust pipe are operated, an alarm is indicated, and the operation of the pressure switch mounted at a pressure vessel is eliminated. If the safety valve is not reclosed when the vessel pressure is decreased lower than the pressure at which it is to be reclosed after the safety valve is operated, an alarm is generated by the logic circuit since both the pressure switches are operated. (Sekiya, K.)

Generator of combined logical signals

International Nuclear Information System (INIS)

Laviron, Andre; Berard, Claude.

1982-01-01

The invention concerns a generator of combined logical signals to form combinations of two outputs at logical level 1 and N-2 outputs at logical level 0, among N generator outputs. This generator is characterized in that it includes a set of N means for storing combinations. Means enable the N storage means to be loaded with the logical levels corresponding to a pre-set starting combination, to control the operations for shifting the contents of the storage means and to control, by transfer facilities, the transfers of contents between these storage means. Controls enable the storage means to be actuated in order to obtain combinations of logical levels 1 and 0. The generation of combinations can be stopped after another pre-set combination. Application is for testing of safety circuits for nuclear power stations [fr

Safety of steel vessel Magnox pressure circuits

International Nuclear Information System (INIS)

Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

1991-01-01

The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

Implementation of Complex Biological Logic Circuits Using Spatially Distributed Multicellular Consortia

Science.gov (United States)

Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc

2016-01-01

Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit’s complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588

A molecular-sized optical logic circuit for digital modulation of a fluorescence signal

Science.gov (United States)

Nishimura, Takahiro; Tsuchida, Karin; Ogura, Yusuke; Tanida, Jun

2018-03-01

Fluorescence measurement allows simultaneous detection of multiple molecular species by using spectrally distinct fluorescence probes. However, due to the broad spectra of fluorescence emission, the multiplicity of fluorescence measurement is generally limited. To overcome this limitation, we propose a method to digitally modulate fluorescence output signals with a molecular-sized optical logic circuit by using optical control of fluorescence resonance energy transfer (FRET). The circuit receives a set of optical inputs represented with different light wavelengths, and then it switches high and low fluorescence intensity from a reporting molecule according to the result of the logic operation. By using combinational optical inputs in readout of fluorescence signals, the number of biomolecular species that can be identified is increased. To implement the FRET-based circuits, we designed two types of basic elements, YES and NOT switches. An YES switch produces a high-level output intensity when receiving a designated light wavelength input and a low-level intensity without the light irradiation. A NOT switch operates inversely to the YES switch. In experiments, we investigated the operation of the YES and NOT switches that receive a 532-nm light input and modulate the fluorescence intensity of Alexa Fluor 488. The experimental result demonstrates that the switches can modulate fluorescence signals according to the optical input.

A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

DEFF Research Database (Denmark)

Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

Energy Technology Data Exchange (ETDEWEB)

Mitra, Kalyan Yoti, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Martínez-Domingo, Carme [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra, Spain and Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Ramon, Eloi, E-mail: eloi.ramon@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Carrabina, Jordi, E-mail: jordi.carrabina@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Gomes, Henrique Leonel, E-mail: hgomes@ualg.pt [Universidade do Algarve, Institute of Telecommunications, Faro (Portugal); Baumann, Reinhard R., E-mail: reinhard.baumann@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Fraunhofer Institute for Electronic Nano Systems (ENAS), Department of Printed Functionalities, Chemnitz (Germany)

2015-02-17

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

International Nuclear Information System (INIS)

Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

2015-01-01

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Directory of Open Access Journals (Sweden)

Apangshu Das

2016-01-01

Full Text Available The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP based logic minimization.

Optical programmable Boolean logic unit.

Science.gov (United States)

Chattopadhyay, Tanay

2011-11-10

Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Energy Technology Data Exchange (ETDEWEB)

Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

Science.gov (United States)

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

International Nuclear Information System (INIS)

Li Shu; Zhang Tong

2008-01-01

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

The Limits of Logic-Based Inherent Safety of Social Robots

DEFF Research Database (Denmark)

Bentzen, Martin Mose

2017-01-01

Social robots can reason and act while taking into accountsocial and cultural structures, for instance by complying withsocial or ethical norms or values. As social robots are likely to becomemore common and advanced and thus likely to interact withhuman beings in increasingly complex situations......-based safety for ethical robots is shown. Afterwards,an empirical study is used to show that there is a clash betweendeontic reasoning and most formal deontic logics. I give anexample as to how this clash can cause problems in human-robot interaction.I conclude that deontic logics closer to natural...... languagereasoning are needed and that logic only should play a limited partin the overall safety architecture of a social robot, which should alsobe based on other principles of safe design....

Multi-purpose logical device with integrated circuit for the automation of mine water disposal

Energy Technology Data Exchange (ETDEWEB)

Pop, E.; Pasculescu, M.

1980-06-01

After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.

Science.gov (United States)

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

Science.gov (United States)

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Designing of all optical generalized circuit for two-input binary and multi-valued logical operations

Science.gov (United States)

Bhowmik, Panchatapa; Roy, Jitendra Nath; Chattopadhyay, Tanay

2014-11-01

This paper presents a generalized all optical circuit of two-input logical operation (both binary and multi-valued), using an optical nonlinear material (OPNLM) based switch. The inputs of the logic gates are represented by different polarization states of light. This model is simple, practical and very much useful for future all optical information processing. Proposed scheme can work for different wavelengths and for different materials. The simulation result with the nonlinear material gold nanoparticle embedded in optically transparent matrices alumina (Al2O3) is also presented in the paper.

Implementing conventional logic unconventionally: photochromic molecular populations as registers and logic gates.

Science.gov (United States)

Chaplin, J C; Russell, N A; Krasnogor, N

2012-07-01

In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

A fuzzy-logic-based approach to qualitative safety modelling for marine systems

International Nuclear Information System (INIS)

Sii, H.S.; Ruxton, Tom; Wang Jin

2001-01-01

Safety assessment based on conventional tools (e.g. probability risk assessment (PRA)) may not be well suited for dealing with systems having a high level of uncertainty, particularly in the feasibility and concept design stages of a maritime or offshore system. By contrast, a safety model using fuzzy logic approach employing fuzzy IF-THEN rules can model the qualitative aspects of human knowledge and reasoning processes without employing precise quantitative analyses. A fuzzy-logic-based approach may be more appropriately used to carry out risk analysis in the initial design stages. This provides a tool for working directly with the linguistic terms commonly used in carrying out safety assessment. This research focuses on the development and representation of linguistic variables to model risk levels subjectively. These variables are then quantified using fuzzy sets. In this paper, the development of a safety model using fuzzy logic approach for modelling various design variables for maritime and offshore safety based decision making in the concept design stage is presented. An example is used to illustrate the proposed approach

Tool for assistance in testing the safety logic section of nuclear plants

International Nuclear Information System (INIS)

Boulc'h, J.; Meur, M. le; Collart, J.M.; Segalard, J.; Uberschlag, J.

1986-01-01

The analysis of the protection system logic section (SPIN) of the PALUEL plant performed manually have led to the study of a logical tool for testing the safety logic section having or having not failures. It is a dynamic analyser which from a terminal in a sharing time system will be able to generate testing sequences, to simulate a processor and its environment and to analyse the logic sections with their workable code

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

A Safety Conundrum Illustrated: Logic, Mathematics, and Science Are Not Enough

Science.gov (United States)

Holloway, C. M.; Johnson, C. W.; Collins, Kristine R.

2010-01-01

In an ideal world, conversations about whether a particular system is safe, or whether a particular method or tool enhances safety, would be emotion-free discussions concentrating on the level of safety required, available evidence, and coherent logical, mathematical, or scientific arguments based on that evidence. In the real world, discussions about safety are often not emotion-free. Political and economic arguments may play a bigger role than logical, mathematical, and scientific arguments, and psychological factors may be as important, or even more important, than purely technical factors. This paper illustrates the conundrum that can result from this clash of the ideal and the real by means of an imagined conversation among a collection of fictional characters representing various types of people who may be participating in a safety discussion.

All optical programmable logic array (PLA)

Science.gov (United States)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Multi-channel logical circuit module used for high-speed, low amplitude signals processing and QDC gate signals generation

International Nuclear Information System (INIS)

Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu

2001-01-01

A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events

Performance Testing Methodology for Safety-Critical Programmable Logic Controller

International Nuclear Information System (INIS)

Kim, Chang Ho; Oh, Do Young; Kim, Ji Hyeon; Kim, Sung Ho; Sohn, Se Do

2009-01-01

The Programmable Logic Controller (PLC) for use in Nuclear Power Plant safety-related applications is being developed and tested first time in Korea. This safety-related PLC is being developed with requirements of regulatory guideline and industry standards for safety system. To test that the quality of the developed PLC is sufficient to be used in safety critical system, document review and various product testings were performed over the development documents for S/W, H/W, and V/V. This paper provides the performance testing methodology and its effectiveness for PLC platform conducted by KOPEC

Average output polarization dataset for signifying the temperature influence for QCA designed reversible logic circuits.

Science.gov (United States)

Abdullah-Al-Shafi, Md; Bahar, Ali Newaz; Bhuiyan, Mohammad Maksudur Rahman; Shamim, S M; Ahmed, Kawser

2018-08-01

Quantum-dot cellular automata (QCA) as nanotechnology is a pledging contestant that has incredible prospective to substitute complementary metal-oxide-semiconductor (CMOS) because of its superior structures such as intensely high device thickness, minimal power depletion with rapid operation momentum. In this study, the dataset of average output polarization (AOP) for fundamental reversible logic circuits is organized as presented in (Abdullah-Al-Shafi and Bahar, 2017; Bahar et al., 2016; Abdullah-Al-Shafi et al., 2015; Abdullah-Al-Shafi, 2016) [1-4]. QCADesigner version 2.0.3 has been utilized to survey the AOP of reversible circuits at separate temperature point in Kelvin (K) unit.

A functional language for describing reversible logic

DEFF Research Database (Denmark)

Thomsen, Michael Kirkedal

2012-01-01

Reversible logic is a computational model where all gates are logically reversible and combined in circuits such that no values are lost or duplicated. This paper presents a novel functional language that is designed to describe only reversible logic circuits. The language includes high....... Reversibility of descriptions is guaranteed with a type system based on linear types. The language is applied to three examples of reversible computations (ALU, linear cosine transformation, and binary adder). The paper also outlines a design flow that ensures garbage- free translation to reversible logic...... circuits. The flow relies on a reversible combinator language as an intermediate language....

Single OR molecule and OR atomic circuit logic gates interconnected on a Si(100)H surface

International Nuclear Information System (INIS)

Ample, F; Joachim, C; Duchemin, I; Hliwa, M

2011-01-01

Electron transport calculations were carried out for three terminal OR logic gates constructed either with a single molecule or with a surface dangling bond circuit interconnected on a Si(100)H surface. The corresponding multi-electrode multi-channel scattering matrix (where the central three terminal junction OR gate is the scattering center) was calculated, taking into account the electronic structure of the supporting Si(100)H surface, the metallic interconnection nano-pads, the surface atomic wires and the molecule. Well interconnected, an optimized OR molecule can only run at a maximum of 10 nA output current intensity for a 0.5 V bias voltage. For the same voltage and with no molecule in the circuit, the output current of an OR surface atomic scale circuit can reach 4 μA.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

Science.gov (United States)

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Microelectromechanical resonator based digital logic elements

KAUST Repository

Hafiz, Md Abdullah Al

2016-10-20

Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.

Microelectromechanical resonator based digital logic elements

KAUST Repository

Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.; Fariborzi, Hossein

2016-01-01

Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.

THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE

Science.gov (United States)

COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS

'Speedy' superconducting circuits

International Nuclear Information System (INIS)

Holst, T.

1994-01-01

The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

A reconfigurable NAND/NOR genetic logic gate.

Science.gov (United States)

Goñi-Moreno, Angel; Amos, Martyn

2012-09-18

Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.

Anticoincidence logic using PALs

International Nuclear Information System (INIS)

Bolanos, L.; Arista Romeu, E.

1997-01-01

This paper describes the functioning principle of an anticoincidence logic and a design of this based on programing logic. The circuit was included in a discriminator of an equipment for single-photon absorptiometry

Enhancement of a radiation safety system through the use of a microprocessor-controlled speech synthesizer

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.

1980-01-01

A speech synthesizer is being used to differentiate eight separate safety alarms on a high energy accelerator at Argonne National Laboratory. A single board microcomputer monitors eight signals from an existing radiation safety logic circuit. The microcomputer is programmed to output the proper code at the proper time and sequence to a speech synthesizer which supplies the audio input to a local public address system. This eliminates the requirement for eight different alarm tones and the personnel training required to differentiate among them. A twenty-word vocabulary was found adequate to supply the necessary safety announcements. The article describes the techniques used to interface the speech synthesizer into the existing safety logic circuit

Interactive effects of relay and circuit breaker aging in a safety-related system

International Nuclear Information System (INIS)

Toman, G.J.; Bacanskas, V.P.; Shook, T.A.; Ladlow, C.C.; Gunther, W.

1987-01-01

This paper provides an overview of the results of a program to evaluate the aging of circuit breakers and relays and the effects of that aging on the function of a safety system used in nuclear power plants. The program was performed under the Nuclear Plant Aging Research (NPAR) Program of the US Nuclear Regulatory Commission under subcontract to Brookhaven National Laboratory. There were two primary aspects to the program. In the first, the aging and failure modes of relays and circuit breakers were determined by evaluating the construction, design, and materials and the failure data related to nuclear power plant service. In the second, the interactions between a safety system and its relays and circuit breakers were evaluated to determine the effects of relay and circuit breaker aging on the function of the safety system. The aging of relays and circuit breakers was assessed through evaluation of failure data bases, discussions with utility personnel, and evaluation of equipment operating and maintenance manuals. The interaction study was based on an analysis of the safety injection system of a pressurized water reactor. The effects of stresses from the system were analyzed for the tendency to cause deterioration of the relays and circuit breakers in the system. Then the effect of the deterioration of relays and circuit breakers on the functional capability of the safety system was evaluated

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices

Directory of Open Access Journals (Sweden)

Tautvydas Brukštus

2016-06-01

Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.

Digital circuit boards mach 1 GHz

CERN Document Server

Morrison, Ralph

2012-01-01

A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

Low swing differential logic for mixed signal applications

International Nuclear Information System (INIS)

Fischer, P.; Kraft, E.

2004-01-01

Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power

Hybdrid integral circuit for proportional chambers

International Nuclear Information System (INIS)

Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

1978-01-01

Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

Orthogonal Algorithm of Logic Probability and Syndrome-Testable Analysis

Institute of Scientific and Technical Information of China (English)

无

1990-01-01

A new method,orthogonal algoritm,is presented to compute the logic probabilities(i.e.signal probabilities)accurately,The transfer properties of logic probabilities are studied first,which are useful for the calculation of logic probability of the circuit with random independent inputs.Then the orthogonal algoritm is described to compute the logic probability of Boolean function realized by a combinational circuit.This algorithm can make Boolean function “ORTHOGONAL”so that the logic probabilities can be easily calculated by summing up the logic probabilities of all orthogonal terms of the Booleam function.

Fuzzy logic as support for security and safety solution in soft targets

Directory of Open Access Journals (Sweden)

Ďuricová Lucia

2016-01-01

Full Text Available Security and safety situations in objects, which are categorized as soft targets, is difficult. The current solving is based on several different type of solving. Soft targets are specific objects, and it requires special software solution. The proposal is based on fuzzy logic. Fuzzy logic could apply more expert’s knowledges and it could help owners and managers with adequate responses in critical situation, and also definition of adequate preventive actions. System solving could help effectivity of proposed measures. The decision making is based on this fuzzy logic support and aim is explained in paper.

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Circuits design of action logics of the protection system of nuclear reactor IAN-R1 of Colombia; Diseno de los circuitos de la logica de actuacion del sistema de proteccion del reactor nuclear IAN-R1 de Colombia

Energy Technology Data Exchange (ETDEWEB)

Gonzalez M, J. L.; Rivero G, T.; Sainz M, E., E-mail: joseluis.gonzalez@inin.gob.mx [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2014-10-15

Due to the obsolescence of the instrumentation and control system of the nuclear research reactor IAN-R1, the Institute of Geology and Mining of Colombia, IngeoMinas, launched an international convoking for renewal it which was won by the Instituto Nacional de Investigaciones Nucleares (ININ). Within systems to design, the reactor protection system is described as important for safety, because this carried out, among others two primary functions: 1) ensuring the reactor shutdown safely, and 2) controlling the interlocks to protect against operational errors if defined conditions have not been met. To fulfill these functions, the various subsystems related to the safety report the state in which they are using binary signals and are connected to the inputs of two redundant logic wiring circuits called action logics (Al) that are part of the reactor protection system. These Al also serve as logical interface to indicate at all times the status of subsystems, both the operator and other systems. In the event that any of the subsystems indicates a state of insecurity in the reactor, the Al generate signals off (or scram) of the reactor, maintaining the interlock until the operator sends a reset signal. In this paper the design, implementation, verification and testing of circuits that make up the Al 1 and 2 of IAN-R1 reactor is described, considering the fulfillment of the requirements that the different international standards imposed on this type of design. (Author)

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

Science.gov (United States)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

Science.gov (United States)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Reversible logic gates on Physarum Polycephalum

International Nuclear Information System (INIS)

Schumann, Andrew

2015-01-01

In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

Rapid single flux quantum logic in high temperature superconductor technology

NARCIS (Netherlands)

Shunmugavel, K.

2006-01-01

A Josephson junction is the basic element of rapid single flux quantum logic (RSFQ) circuits. A high operating speed and low power consumption are the main advantages of RSFQ logic over semiconductor electronic circuits. To realize complex RSFQ circuits in HTS technology one needs a reproducible

Qualification of FPGA-Based Safety-Related PRM System

International Nuclear Information System (INIS)

Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

2011-01-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

Adiabatic logic future trend and system level perspective

CERN Document Server

Teichmann, Philip

2012-01-01

Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the p...

Assessment of safety engineering of circuits with dc micromotors

Energy Technology Data Exchange (ETDEWEB)

Pavlyuchenko, L.A.; Starchuk, S.E.

1986-01-01

Presents an assessment of safety engineering in d.c. micromotors operating as part of actuating devices in mining equipment. These micromotors should have RO (especially explosion proof) protection. The safety engineering should be assessed with an intermittent fault in the power line. Equations are given for calculation of the equivalent inductance of the micromotor circuit with an intermittent power line fault. If the circuit is not intrinsically safe, a diode in the forward direction is recommended for connection in series with the micromotor. If the power line is not intrinsically safe, a diode shunt is recommended. Comparative data for power sources (IBP) and micromotors (DPM, DPR, with permanent magnets) are given in tables. 4 refs.

Modern TTL circuits manual

CERN Document Server

Marston, R M

2013-01-01

Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

Testing Superconductor Logic Integrated Circuits

NARCIS (Netherlands)

Arun, A.J.; Kerkhoff, Hans G.

2005-01-01

Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Graphical approach for multiple values logic minimization

Science.gov (United States)

Awwal, Abdul Ahad S.; Iftekharuddin, Khan M.

1999-03-01

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

Wave Pipelining Using Self Reset Logic

Directory of Open Access Journals (Sweden)

Miguel E. Litvin

2008-01-01

Full Text Available This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations. To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID. These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT. These properties simplify the implementation of wave pipelined circuits. General timing analysis is provided and compared with previous implementations. Results of circuit implementation are presented together with conclusions and future work.

Electron spin for classical information processing: a brief survey of spin-based logic devices, gates and circuits

International Nuclear Information System (INIS)

Bandyopadhyay, Supriyo; Cahay, Marc

2009-01-01

In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information processing device invariably causes current flow and an associated dissipation. Replacing 'charge' with the 'spin' of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient 'green electronics'. This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation. (topical review)

PC based manual and safety logic card test setup for 235 MWe PHWRs

International Nuclear Information System (INIS)

Chandgadkar, G.M.; Kohli, A.K.; Agarwal, R.G.; Chandra, Rajesh

1992-01-01

Fuel handling controls for 235 MWe PHWR make use of Manual and Logic cards (MLCs) for providing safety interlocks. These cards consist of various type of logic blocks. By connecting these logic blocks all the safety interlocks required for fuel handling controls have been provided. Previously trouble shooting of these cards was done by means of logic probe. Since the method was manual, it was laborious and time consuming. PC based test setup has overcome this drawback and detects the fault at the component level within few seconds. It also gives printout of status of faulty MLC cards. Here motherboard has been designed having slots for insertion of MLC cards. The input/output connection of these cards are coming to two 50 pin FRC connectors. PC communicates through 144 line digital input/output card with MLC card under test. Software is user friendly and outputs suitable input patterns to the card under test and checks for output pattern. It compares this output pattern with compare pattern and detects the fault and displays the symptoms. This system is currently in use at test facility for fuelling machine for 235 MWe PHWR reactor at Refuelling Technology Division, Hall-7. This test setup has been proposed for use at NAPP and future reactors. (author). 4 figs., 1 annexure

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

Science.gov (United States)

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

K-maps: a vehicle to an optimal solution in combinational logic ...

African Journals Online (AJOL)

K-maps: a vehicle to an optimal solution in combinational logic design problems using digital multiplexers. ... Abstract. Application of Karnaugh maps (K-Maps) for the design of combinational logic circuits and sequential logic circuits is a subject that has been widely discussed. However, the use of K-Maps in the design of ...

Electronic logic to enhance switch reliability in detecting openings and closures of redundant switches

Science.gov (United States)

Cooper, James A.

1986-01-01

A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and failsafe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.

Classical Logic and Quantum Logic with Multiple and Common Lattice Models

Directory of Open Access Journals (Sweden)

Mladen Pavičić

2016-01-01

Full Text Available We consider a proper propositional quantum logic and show that it has multiple disjoint lattice models, only one of which is an orthomodular lattice (algebra underlying Hilbert (quantum space. We give an equivalent proof for the classical logic which turns out to have disjoint distributive and nondistributive ortholattices. In particular, we prove that both classical logic and quantum logic are sound and complete with respect to each of these lattices. We also show that there is one common nonorthomodular lattice that is a model of both quantum and classical logic. In technical terms, that enables us to run the same classical logic on both a digital (standard, two-subset, 0-1-bit computer and a nondigital (say, a six-subset computer (with appropriate chips and circuits. With quantum logic, the same six-element common lattice can serve us as a benchmark for an efficient evaluation of equations of bigger lattice models or theorems of the logic.

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Directory of Open Access Journals (Sweden)

Shipra Upadhyay

2013-01-01

Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

PM 3655 PHILIPS Logic analyzer

CERN Multimedia

A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.

HDL to verification logic translator

Science.gov (United States)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

Nanowire NMOS Logic Inverter Characterization.

Science.gov (United States)

Hashim, Yasir

2016-06-01

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Toward spin-based Magneto Logic Gate in Graphene

Science.gov (United States)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

Energy Technology Data Exchange (ETDEWEB)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

International Nuclear Information System (INIS)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

2013-01-01

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Logical design for computers and control

CERN Document Server

Dodd, Kenneth N

1972-01-01

Logical Design for Computers and Control Logical Design for Computers and Control gives an introduction to the concepts and principles, applications, and advancements in the field of control logic. The text covers topics such as logic elements; high and low logic; kinds of flip-flops; binary counting and arithmetic; and Boolean algebra, Boolean laws, and De Morgan's theorem. Also covered are topics such as electrostatics and atomic theory; the integrated circuit and simple control systems; the conversion of analog to digital systems; and computer applications and control. The book is recommend

Fast frequency divider circuit using combinational logic

Science.gov (United States)

Helinski, Ryan

2017-05-30

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.

System Guidelines for EMC Safety-Critical Circuits: Design, Selection, and Margin Demonstration

Science.gov (United States)

Lawton, R. M.

1996-01-01

Demonstration of safety margins for critical points (circuits) has traditionally been required since it first became a part of systems-level Electromagnetic Compatibility (EMC) requirements of MIL-E-6051C. The goal of this document is to present cost-effective guidelines for ensuring adequate Electromagnetic Effects (EME) safety margins on spacecraft critical circuits. It is for the use of NASA and other government agencies and their contractors to prevent loss of life, loss of spacecraft, or unacceptable degradation. This document provides practical definition and treatment guidance to contain costs within affordable limits.

Collective of mechatronics circuit

International Nuclear Information System (INIS)

1987-02-01

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Collective of mechatronics circuit

Energy Technology Data Exchange (ETDEWEB)

NONE

1987-02-15

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

Energy Technology Data Exchange (ETDEWEB)

Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

1984-01-01

Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

Logic functions and equations examples and exercises

CERN Document Server

Steinbach, Bernd

2009-01-01

With a free, downloadable software package available to help solve the exercises, this book focuses on practical and relevant problems that arise in the field of binary logics, with its two main applications - digital circuit design, and propositional logics.

A formalized design process for bacterial consortia that perform logic computing.

Directory of Open Access Journals (Sweden)

Weiyue Ji

Full Text Available The concept of microbial consortia is of great attractiveness in synthetic biology. Despite of all its benefits, however, there are still problems remaining for large-scaled multicellular gene circuits, for example, how to reliably design and distribute the circuits in microbial consortia with limited number of well-behaved genetic modules and wiring quorum-sensing molecules. To manage such problem, here we propose a formalized design process: (i determine the basic logic units (AND, OR and NOT gates based on mathematical and biological considerations; (ii establish rules to search and distribute simplest logic design; (iii assemble assigned basic logic units in each logic operating cell; and (iv fine-tune the circuiting interface between logic operators. We in silico analyzed gene circuits with inputs ranging from two to four, comparing our method with the pre-existing ones. Results showed that this formalized design process is more feasible concerning numbers of cells required. Furthermore, as a proof of principle, an Escherichia coli consortium that performs XOR function, a typical complex computing operation, was designed. The construction and characterization of logic operators is independent of "wiring" and provides predictive information for fine-tuning. This formalized design process provides guidance for the design of microbial consortia that perform distributed biological computation.

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Directory of Open Access Journals (Sweden)

Ravi S. P. Nair

2015-09-01

Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

Safety assurance logic techniques for evaluation of accident prevention and mitigation

International Nuclear Information System (INIS)

McWethy, L.M.; Hagan, J.W.

1976-01-01

Safety assurance methods have been developed and applied in reactor safety assessments of FFTF. These methods promote visibility of the total safety provided by the plant, both in prevention of off-normal or accident conditions as well as provision of various features which terminate conditions within acceptable bounds if such conditions should occur. One of the primary techniques applied in safety assurance is the development of safety assurance diagrams. These diagrams explicitly identify the multiple lines of defense which prevent accident progression. The diagrams graphically demonstrate the defense-in-depth provided by the plant for each postulated occurrence. Lines of defense are shown against ever having an occurrence in the first place; thus giving appropriate emphasis on accident prevention, and visibility to the designer's role in promoting this level of safety. These diagrams, or accident process trees, also show graphically the various paths of postulated accident progression to their logical termination. Evaluation of the importance and strength of each line-of-defense assures fulfillment of the safety objectives of the overall plant system

Heuristic Synthesis of Reversible Logic – A Comparative Study

Directory of Open Access Journals (Sweden)

Chua Shin Cheng

2014-01-01

Full Text Available Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based. All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1972-01-01

Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

Superconducting flux flow digital circuits

International Nuclear Information System (INIS)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

1993-01-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

High-speed dynamic domino circuit implemented with gaas mesfets

Science.gov (United States)

Yang, Long (Inventor); Long, Stephen I. (Inventor)

1990-01-01

A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.

"Glitch Logic" and Applications to Computing and Information Security

Science.gov (United States)

Stoica, Adrian; Katkoori, Srinivas

2009-01-01

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

Application of reliability analysis methods to the comparison of two safety circuits

International Nuclear Information System (INIS)

Signoret, J.-P.

1975-01-01

Two circuits of different design, intended for assuming the ''Low Pressure Safety Injection'' function in PWR reactors are analyzed using reliability methods. The reliability analysis of these circuits allows the failure trees to be established and the failure probability derived. The dependence of these results on test use and maintenance is emphasized as well as critical paths. The great number of results obtained may allow a well-informed choice taking account of the reliability wanted for the type of circuits [fr

A circuit design for multi-inputs stateful OR gate

Energy Technology Data Exchange (ETDEWEB)

Chen, Qiao; Wang, Xiaoping, E-mail: wangxiaoping@hust.edu.cn; Wan, Haibo; Yang, Ran; Zheng, Jian

2016-09-07

The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

A circuit design for multi-inputs stateful OR gate

International Nuclear Information System (INIS)

Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian

2016-01-01

The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

Multi-valued LSI/VLSI logic design

Science.gov (United States)

Santrakul, K.

A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

Synthesis of multivalued quantum logic circuits by elementary gates

Science.gov (United States)

Di, Yao-Min; Wei, Hai-Rui

2013-01-01

We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

A novel water-soluble 1,8-naphthalimide as a fluorescent pH-probe and a molecular logic circuit

International Nuclear Information System (INIS)

Georgiev, Nikolai I.; Dimitrova, Margarita D.; Krasteva, Paoleta V.; Bojinov, Vladimir B.

2017-01-01

A novel highly water-soluble fluorescence sensing 1,8-naphthalimide is synthesized and investigated. The novel compound is designed on the “fluorophore-receptor 1 -spacer-receptor 2 ” model as a molecular fluorescence probe for determination of ions in 100% aqueous media. The novel probe comprising hydrazide and N-methylpiperazine substituents is capable of operating simultaneously via ICT and PET signaling mechanism and of recognizing selectively protons and hydroxyl anions over the representative metal ions and anions. Due to the remarkable fluorescence changes as a function of pH the system is able to act as a three output combinatorial logic circuit with two chemical inputs. Two INHIBIT gates in fluorescence and absorption mode as well as an IMPLICATION logic gate are obtained. Because of the parallel action of both INHIBIT gates a magnitude digital comparator is achieved for the first time in this way.

Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.

Science.gov (United States)

Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl

2010-09-13

Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).

All-optical symmetric ternary logic gate

Science.gov (United States)

Chattopadhyay, Tanay

2010-09-01

Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.

Automatic circuit analysis based on mask information

International Nuclear Information System (INIS)

Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

1976-01-01

The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

Logic design of Josephson network. II

International Nuclear Information System (INIS)

Nakajima, K.; Onodera, Y.

1978-01-01

By numerical calculations of the differential-difference sine-Gordon equation, we have discussed the discrete Josephson-junction transmission lines which are constructed of a series of small-area Josephson junctions connected by superconducting strips. It is shown that the discrete Josephson lines containing D lines, N lines, T turning points, and S turning points are elementarily characterized by the discreteness parameter (2πLI/sub c//Phi 0 )/sup 1/2/. On the discrete Josephson logic circuits there exists a region of forbidden propagation in the (2πLI/sub c//Phi 0 )/sup 1/2/-γ (bias-current parameter) plane for single flux quanta. A single flux quantum can be stuffed in a small area of the discrete Josephson logic circuits. The discrete circuits can be conveniently and easily linked to each other, in a practical fabrication of a Josephson network

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

Science.gov (United States)

Ayala, Christopher Lawrence

Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using

Design and experimentation of BSFQ logic devices

International Nuclear Information System (INIS)

Hosoki, T.; Kodaka, H.; Kitagawa, M.; Okabe, Y.

1999-01-01

Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic 'Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported. (author)

A single nano cantilever as a reprogrammable universal logic gate

International Nuclear Information System (INIS)

Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J

2017-01-01

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)

A single nano cantilever as a reprogrammable universal logic gate

KAUST Repository

Chappanda, K. N.

2017-02-24

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure

Directory of Open Access Journals (Sweden)

Hong-Quan ZHao

2012-01-01

Full Text Available One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD- based arithmetic logic unit (ALU is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.

Test generation for digital circuits using parallel processing

Science.gov (United States)

Hartmann, Carlos R.; Ali, Akhtar-Uz-Zaman M.

1990-12-01

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates.

Science.gov (United States)

Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar

2012-12-26

The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Energy Technology Data Exchange (ETDEWEB)

Kish, Laszlo B. [Texas A and M University, Department of Electrical and Computer Engineering, College Station, TX 77843-3128 (United States)], E-mail: laszlo.kish@ece.tamu.edu

2009-03-02

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

International Nuclear Information System (INIS)

Kish, Laszlo B.

2009-01-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Science.gov (United States)

Kish, Laszlo B.

2009-03-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case ( N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Nanomagnetic Logic

Science.gov (United States)

Carlton, David Bryan

The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly

Two- and three-input TALE-based AND logic computation in embryonic stem cells.

Science.gov (United States)

Lienert, Florian; Torella, Joseph P; Chen, Jan-Hung; Norsworthy, Michael; Richardson, Ryan R; Silver, Pamela A

2013-11-01

Biological computing circuits can enhance our ability to control cellular functions and have potential applications in tissue engineering and medical treatments. Transcriptional activator-like effectors (TALEs) represent attractive components of synthetic gene regulatory circuits, as they can be designed de novo to target a given DNA sequence. We here demonstrate that TALEs can perform Boolean logic computation in mammalian cells. Using a split-intein protein-splicing strategy, we show that a functional TALE can be reconstituted from two inactive parts, thus generating two-input AND logic computation. We further demonstrate three-piece intein splicing in mammalian cells and use it to perform three-input AND computation. Using methods for random as well as targeted insertion of these relatively large genetic circuits, we show that TALE-based logic circuits are functional when integrated into the genome of mouse embryonic stem cells. Comparing construct variants in the same genomic context, we modulated the strength of the TALE-responsive promoter to improve the output of these circuits. Our work establishes split TALEs as a tool for building logic computation with the potential of controlling expression of endogenous genes or transgenes in response to a combination of cellular signals.

Short circuit protection for a power distribution system

Science.gov (United States)

Owen, J. R., III

1969-01-01

Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

Science.gov (United States)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

Science.gov (United States)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

CMOS digital integrated circuits a first course

CERN Document Server

Hawkins, Charles; Zarkesh-Ha, Payman

2016-01-01

This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

Single-flux-quantum circuit technology for superconducting radiation detectors

International Nuclear Information System (INIS)

Fujimaki, Akira; Onogi, Masashi; Matsumoto, Tomohiro; Tanaka, Masamitsu; Sekiya, Akito; Hayakawa, Hisao; Yorozu, Shinichi; Terai, Hirotaka; Yoshikawa, Nobuyuki

2003-01-01

We discuss the application of the single-flux-quantum (SFQ) logic circuits to multi superconducting radiation detectors system. The SFQ-based analog-to-digital converters (ADCs) have the advantage in current sensitivity, which can reach less than 10 nA in a well-tuned ADC. We have also developed the design technology of the SFQ circuits. We demonstrate high-speed operation of large-scale integrated circuits such as a 2x2 cross/bar switch, arithmetic logic unit, indicating that our present SFQ technology is applicable to the multi radiation detectors system. (author)

MANUAL LOGIC CONTROLLER (MLC)

OpenAIRE

Claude Ziad Bayeh

2015-01-01

The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...

Reliability evaluation programmable logic devices

International Nuclear Information System (INIS)

Srivani, L.; Murali, N.; Thirugnana Murthy, D.; Satya Murty, S.A.V.

2014-01-01

Programmable Logic Devices (PLD) are widely used as basic building modules in high integrity systems, considering their robust features such as gate density, performance, speed etc. PLDs are used to implement digital design such as bus interface logic, control logic, sequencing logic, glue logic etc. Due to semiconductor evolution, new PLDs with state-of-the-art features are arriving to the market. Since these devices are reliable as per the manufacturer's specification, they were used in the design of safety systems. But due to their reduced market life, the availability of performance data is limited. So evaluating the PLD before deploying in a safety system is very important. This paper presents a survey on the use of PLDs in the nuclear domain and the steps involved in the evaluation of PLD using Quantitative Accelerated Life Testing. (author)

Construction safety monitoring based on the project's characteristic with fuzzy logic approach

Science.gov (United States)

Winanda, Lila Ayu Ratna; Adi, Trijoko Wahyu; Anwar, Nadjadji; Wahyuni, Febriana Santi

2017-11-01

Construction workers accident is the highest number compared with other industries and falls are the main cause of fatal and serious injuries in high rise projects. Generally, construction workers accidents are caused by unsafe act and unsafe condition that can occur separately or together, thus a safety monitoring system based on influencing factors is needed to achieve zero accident in construction industry. The dynamic characteristic in construction causes high mobility for workers while doing the task, so it requires a continuously monitoring system to detect unsafe condition and to protect workers from potential hazards. In accordance with the unique nature of project, fuzzy logic approach is one of the appropriate methods for workers safety monitoring on site. In this study, the focus of discussion is based on the characteristic of construction projects in analyzing "potential hazard" and the "protection planning" to be used in accident prevention. The data have been collected from literature review, expert opinion and institution of safety and health. This data used to determine hazard identification. Then, an application model is created using Delphi programming. The process in fuzzy is divided into fuzzification, inference and defuzzification, according to the data collection. Then, the input and final output data are given back to the expert for assessment as a validation of application model. The result of the study showed that the potential hazard of construction workers accident could be analysed based on characteristic of project and protection system on site and fuzzy logic approach can be used for construction workers accident analysis. Based on case study and the feedback assessment from expert, it showed that the application model can be used as one of the safety monitoring tools.

Logic verification system for power plant sequence diagrams

International Nuclear Information System (INIS)

Fukuda, Mitsuko; Yamada, Naoyuki; Teshima, Toshiaki; Kan, Ken-ichi; Utsunomiya, Mitsugu.

1994-01-01

A logic verification system for sequence diagrams of power plants has been developed. The system's main function is to verify correctness of the logic realized by sequence diagrams for power plant control systems. The verification is based on a symbolic comparison of the logic of the sequence diagrams with the logic of the corresponding IBDs (interlock Block Diagrams) in combination with reference to design knowledge. The developed system points out the sub-circuit which is responsible for any existing mismatches between the IBD logic and the logic realized by the sequence diagrams. Applications to the verification of actual sequence diagrams of power plants confirmed that the developed system is practical and effective. (author)

Assembly of Nanoscale Organic Single-Crystal Cross-Wire Circuits

DEFF Research Database (Denmark)

Bjørnholm, Thomas

2009-01-01

Organic single-crystal transistors and circuits can be assembled by nanomechanical manipulation of nanowires of CuPc, F(16)CuPc, and SnO(2):Sb. The crossed bar devices have low operational voltage, high mobility and are stable in air. They can be combined into circuits, providing varied functions...... including inverters and NOR and NAND logic gates, opening new opportunities for organic nanoelectronics and highly sophisticated integrated logic devices....

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

International Nuclear Information System (INIS)

Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.

2014-01-01

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

Science.gov (United States)

Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.

2014-01-01

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Flexible programmable logic module

Science.gov (United States)

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

Radiation tolerant combinational logic cell

Science.gov (United States)

Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

2009-01-01

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

Divide and control: split design of multi-input DNA logic gates.

Science.gov (United States)

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2015-01-18

Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

Science.gov (United States)

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

Graphene Oxide/Poly(3-hexylthiophene) Nanocomposite Thin-Film Phototransistor for Logic Circuit Applications

Science.gov (United States)

Mansouri, S.; Coskun, B.; El Mir, L.; Al-Sehemi, Abdullah G.; Al-Ghamdi, Ahmed; Yakuphanoglu, F.

2018-04-01

Graphene is a sheet-structured material that lacks a forbidden band, being a good candidate for use in radiofrequency applications. We have elaborated graphene-oxide-doped poly(3-hexylthiophene) nanocomposite to increase the interlayer distance and thereby open a large bandgap for use in the field of logic circuits. Graphene oxide/poly(3-hexylthiophene) (GO/P3HT) nanocomposite thin-film transistors (TFTs) were fabricated on silicon oxide substrate by spin coating method. The current-voltage ( I- V) characteristics of TFTs with various P3HT compositions were studied in the dark and under light illumination. The photocurrent, charge carrier mobility, subthreshold voltage, density of interface states, density of occupied states, and I ON/ I OFF ratio of the devices strongly depended on the P3HT weight ratio in the composite. The effects of white-light illumination on the electrical parameters of the transistors were investigated. The results indicated that GO/P3HT nanocomposite thin-film transistors have high potential for use in radiofrequency applications, and their feasibility for use in digital applications has been demonstrated.

Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

Science.gov (United States)

Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.

2018-05-01

Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.

Optical reversible programmable Boolean logic unit.

Science.gov (United States)

Chattopadhyay, Tanay

2012-07-20

Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

Study of the computer aided design of combinatory logical circuits

International Nuclear Information System (INIS)

Sisso, Robert

1969-01-01

This survey aims at obtaining, automatically, low costs circuits in NOR and NAND technology for completely and incompletely specified functions. Two methods are proposed; the first one (chain fusion and element combination method) aims at obtaining directly the circuits by applying synthesis algorithms, the automation of which is provided by a new notation which binds bi-univocally circuit and function. The second one (decomposition method) uses the principle of the simple disjoined decomposition and enables to determine within this scope the upper boundary evolution of the circuit minimum cost. (author) [fr

Effects of smoke on functional circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1997-10-01

Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs

Logical operations realized on the Ising chain of N qubits

International Nuclear Information System (INIS)

Asano, Masanari; Tateda, Norihiro; Ishii, Chikara

2004-01-01

Multiqubit logical gates are proposed as implementations of logical operations on N qubits realized physically by the local manipulation of qubits before and after the one-time evolution of an Ising chain. This construction avoids complicated tuning of the interactions between qubits. The general rules of the action of multiqubit logical gates are derived by decomposing the process into the product of two-qubit logical operations. The formalism is demonstrated by the construction of a special type of multiqubit logical gate that is simulated by a quantum circuit composed of controlled-NOT gates

The application of computer logic design in the trigger system

International Nuclear Information System (INIS)

Zhao Dixin; Ding Huiliang; Gu Jianhui

1996-01-01

The programmable logic devices PLD and FPGA, which are developing steadily recently, can be configured by user. Designers define the logic functions of the circuit and revise these functions when necessary. The application of these devices in the trigger system and development system is introduced

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

Science.gov (United States)

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering ; security; trusted electronics Introduction Integrated Circuit (IC) designs are... Circuit camouflage is hardware obfuscation technology that prevents reverse engineering of a fabricated device by utilizing a relatively small...obfuscated with circuit camouflage technology, this type of attack becomes much more difficult because a reverse engineer cannot extract a gate- level

Contribution of custom-designed integrated circuits to the electronic equipment of multiwire chambers

International Nuclear Information System (INIS)

Prunier, J.

1977-01-01

The first generations of circuits intended to equip the multiwire proportional chambers provided the user with logical type indications (absence or presence of a signal at a given place). This logical indication was soon associated with a semi-analog data (presence or absence of a signal above an analog threshold, i.e. the discrimination function) as with FILAS, RBA and RBB circuits. The evolution continued with the appearance of analog data capture (time, amplitude, charge) and the corresponding circuits: IFT circuits, analog-to-digital converters [fr

Digital Circuit Analysis Using an 8080 Processor.

Science.gov (United States)

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Superconducting digital logic amplifier

International Nuclear Information System (INIS)

Przybysz, J.X.

1989-01-01

This paper describes a superconducting digital logic amplifier for interfacing between a Josephson junction logic circuit having output current and a higher voltage semiconductor circuit input. The amplifier comprising: an input terminal for connection to a; an output terminal for connection to a semiconductor circuit input; an input, lower critical current, Josephson junction having first and second terminals; a first series string of at least three lower critical current Josephson junctions. The first series string being connected to the first terminal of the input Josephson junction such that the first series string is in series with the input Josephson junction to provide a series combination. The input terminal being connected to the first terminal of the input Josephson junction, and with the critical current of the lower critical current Josephson junctions of the input Josephson junction and the first series Josephson junctions being less than the output current of the low voltage Josephson junction circuit; a second series string of at least four higher critical current Josephson junctions. The second string being connected in parallel with the series combination to provide parallel strings having an upper common connection and a lower common connection. The lower common connection being connected to the second terminal of the input Josephson junction and the upper common connection being connected to the output terminal; and a pulsed DC current source connected the parallel strings at the upper common connection. The DC current source having a current at least equal to the critical current of the higher critical current Josephson junctions

Design, construction and implementation of two redundant circuits of the actuation logic of the protection system of the new control console of TRIGA Mark III reactor of ININ

International Nuclear Information System (INIS)

Celestino M, E.

2016-01-01

The Instituto Nacional de Investigaciones Nucleares (ININ) in Mexico has a nuclear reactor type TRIGA Mark III, which was put into operation in 1968. The reactor is used for staff training, radioisotope production, and for research projects of different areas. Over time and due to advances constantly has the electronics industry, maintenance of electronic systems is complicated because basically sometimes components that are no longer manufactured or no longer exist in the market, making it necessary to create projects required modernization. This is the case of the TRIGA reactor of ININ, so the Department of Automation and Instrumentation ININ is undertaking a new project to update the reactor control console. Systems that make up a nuclear reactor protection system (Ps) is relevant, since it is responsible for generating the necessary steps to shut down the reactor to an event of uncertainty which could affect the operators or the installation own actions. As part of the renovation project, this study design is presented to update the Logic of Action (La) of the Ps, whose final design must meet the requirements or specifications set by users and or regulations applicable to nuclear research reactors. One of the requirements established for the proposed new design La, is that it must be implemented with components and devices manufactured with latest technologies, and readily available on the market. The design which is operating currently uses TTL logic whose components are no longer available in the market, so for the new design you decide to use programmable circuits, and specifically, the CPLDs called (by the acronym Complex Programmable Logic Device). These CPLDs are electronic devices that solve complex logic equations and meeting the requirements of functionality and modernity for the new design of the La. In this work the criteria used for the selection of the CPLDs considering the availability and ease of software and hardware to use, and the design and

Integrated-Circuit Controller For Brushless dc Motor

Science.gov (United States)

Le, Dong Tuan

1994-01-01

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Design structure for in-system redundant array repair in integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

The design of charge measurement circuit of MWPC

International Nuclear Information System (INIS)

Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

2010-01-01

It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits

Energy Technology Data Exchange (ETDEWEB)

Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)

2014-01-21

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

Programmable Array Logic Design

International Nuclear Information System (INIS)

Demon Handoyo; Djen Djen Djainal

2007-01-01

Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)

Trinary arithmetic and logic unit (TALU) using savart plate and spatial light modulator (SLM) suitable for optical computation in multivalued logic

Science.gov (United States)

Ghosh, Amal K.; Bhattacharya, Animesh; Raul, Moumita; Basuray, Amitabha

2012-07-01

Arithmetic logic unit (ALU) is the most important unit in any computing system. Optical computing is becoming popular day-by-day because of its ultrahigh processing speed and huge data handling capability. Obviously for the fast processing we need the optical TALU compatible with the multivalued logic. In this regard we are communicating the trinary arithmetic and logic unit (TALU) in modified trinary number (MTN) system, which is suitable for the optical computation and other applications in multivalued logic system. Here the savart plate and spatial light modulator (SLM) based optoelectronic circuits have been used to exploit the optical tree architecture (OTA) in optical interconnection network.

Disjointness of Stabilizer Codes and Limitations on Fault-Tolerant Logical Gates

Science.gov (United States)

Jochym-O'Connor, Tomas; Kubica, Aleksander; Yoder, Theodore J.

2018-04-01

Stabilizer codes are among the most successful quantum error-correcting codes, yet they have important limitations on their ability to fault tolerantly compute. Here, we introduce a new quantity, the disjointness of the stabilizer code, which, roughly speaking, is the number of mostly nonoverlapping representations of any given nontrivial logical Pauli operator. The notion of disjointness proves useful in limiting transversal gates on any error-detecting stabilizer code to a finite level of the Clifford hierarchy. For code families, we can similarly restrict logical operators implemented by constant-depth circuits. For instance, we show that it is impossible, with a constant-depth but possibly geometrically nonlocal circuit, to implement a logical non-Clifford gate on the standard two-dimensional surface code.

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

Transistor and integrated circuit manufacture

Energy Technology Data Exchange (ETDEWEB)

Colman, D

1978-09-27

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

Simultaneous G-Quadruplex DNA Logic.

Science.gov (United States)

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

International Nuclear Information System (INIS)

Kanungo, Jitendra; Dasgupta, S.

2014-01-01

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator (PCG). The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder (RCA) and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic. (semiconductor integrated circuits)

Transistor and integrated circuit manufacture

International Nuclear Information System (INIS)

Colman, D.

1978-01-01

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

Software V and V methods for a safety - grade programmable logic controller

International Nuclear Information System (INIS)

Jang Yeol Kim; Young Jun Lee; Kyung Ho Cha; Se Woo Cheon; Jang Soo Lee; Kee Choon Kwon

2006-01-01

This paper addresses the Verification and Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety- grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines and procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects. (author)

Circuit board accident--organizational dimension hidden by prescribed safety.

Science.gov (United States)

de Almeida, Ildeberto Muniz; Buoso, Eduardo; do Amaral Dias, Maria Dionísia; Vilela, Rodolfo Andrade Gouveia

2012-01-01

This study analyzes an accident in which two maintenance workers suffered severe burns while replacing a circuit breaker panel in a steel mill, following model of analysis and prevention of accidents (MAPA) developed with the objective of enlarging the perimeter of interventions and contributing to deconstruction of blame attribution practices. The study was based on materials produced by a health service team in an in-depth analysis of the accident. The analysis shows that decisions related to system modernization were taken without considering their implications in maintenance scheduling and creating conflicts of priorities and of interests between production and safety; and also reveals that the lack of a systemic perspective in safety management was its principal failure. To explain the accident as merely non-fulfillment of idealized formal safety rules feeds practices of blame attribution supported by alibi norms and inhibits possible prevention. In contrast, accident analyses undertaken in worker health surveillance services show potential to reveal origins of these events incubated in the history of the system ignored in practices guided by the traditional paradigm.

Monolithic microwave integrated circuit with integral array antenna

International Nuclear Information System (INIS)

Stockton, R.J.; Munson, R.E.

1984-01-01

A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence

Automated Translation of Safety Critical Application Software Specifications into PLC Ladder Logic

Science.gov (United States)

Leucht, Kurt W.; Semmel, Glenn S.

2008-01-01

The numerous benefits of automatic application code generation are widely accepted within the software engineering community. A few of these benefits include raising the abstraction level of application programming, shorter product development time, lower maintenance costs, and increased code quality and consistency. Surprisingly, code generation concepts have not yet found wide acceptance and use in the field of programmable logic controller (PLC) software development. Software engineers at the NASA Kennedy Space Center (KSC) recognized the need for PLC code generation while developing their new ground checkout and launch processing system. They developed a process and a prototype software tool that automatically translates a high-level representation or specification of safety critical application software into ladder logic that executes on a PLC. This process and tool are expected to increase the reliability of the PLC code over that which is written manually, and may even lower life-cycle costs and shorten the development schedule of the new control system at KSC. This paper examines the problem domain and discusses the process and software tool that were prototyped by the KSC software engineers.

An Automated Test Framework for Experimenting with Stochastic Behavior in Reconfigurable Logic

DEFF Research Database (Denmark)

Birklykke, Alex Aaen; Le Moullec, Yannick; Alminde, Lars

2012-01-01

In this paper, we present an automated test frame- work for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate-level. As an exper......In this paper, we present an automated test frame- work for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate...... block subject to voltage/frequency scaling and Vdd -noise. The framework provides easy interfacing with laboratory equipment, design of experiment capabilities and automatic test execution, thus providing a powerful tool for characterizing stochastic behavior in reconfigurable logic....

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

New data structures and algorithms for logic synthesis and verification

CERN Document Server

Amaru, Luca Gaetano

2017-01-01

This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines. · Provides a comprehensive, theoretical study on majority and biconditional logic for logic synthesis; · Updates the current scenario in synthesis and verification – especially in light of emerging technologies; · Demonstrates applications to CMOS technology and emerging technologies.

Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

NARCIS (Netherlands)

Perkowski, M.A.; Foote, D.; Chen, Qihong; Al-Rabadi, A.; Jozwiak, L.

2002-01-01

For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design

Complex cellular logic computation using ribocomputing devices.

Science.gov (United States)

Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

2017-08-03

Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

Reversible logic synthesis methodologies with application to quantum computing

CERN Document Server

Taha, Saleem Mohammed Ridha

2016-01-01

This book opens the door to a new interesting and ambitious world of reversible and quantum computing research. It presents the state of the art required to travel around that world safely. Top world universities, companies and government institutions  are in a race of developing new methodologies, algorithms and circuits on reversible logic, quantum logic, reversible and quantum computing and nano-technologies. In this book, twelve reversible logic synthesis methodologies are presented for the first time in a single literature with some new proposals. Also, the sequential reversible logic circuitries are discussed for the first time in a book. Reversible logic plays an important role in quantum computing. Any progress in the domain of reversible logic can be directly applied to quantum logic. One of the goals of this book is to show the application of reversible logic in quantum computing. A new implementation of wavelet and multiwavelet transforms using quantum computing is performed for this purpose. Rese...

VHDL for logic synthesis

CERN Document Server

Rushton, Andrew

2011-01-01

Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types. This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features. Features to this edition include: * a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies...

30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

Science.gov (United States)

2010-07-01

... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

Electronic circuits fundamentals & applications

CERN Document Server

Tooley, Mike

2015-01-01

Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Science.gov (United States)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

Science.gov (United States)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

Science.gov (United States)

2010-07-01

... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

A Web-Based Visualization and Animation Platform for Digital Logic Design

Science.gov (United States)

Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.

2015-01-01

This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…

Realistic Realizations Of Threshold Circuits

Science.gov (United States)

Razavi, Hassan M.

1987-08-01

Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.

Logic designer's handbook circuits and systems

CERN Document Server

Parr, E A

2013-01-01

Easy-to-read, but nonetheless thorough, this book on digital circuits is for use by students and engineers, and is a readily accessible source of data on devices in the TTL and CMOS families. The book is written to be used as a Designer's Handbook and will spend its days on the designer's bench rather than their bookshelf. The basic theory is explained and then supported with specific practical examples.* Revised, enlarged, reduced price edition * Easy-to-read, jargon free book suitable for professionals and students * Plenty of basic theory and practical information * Based on authors practi

RSFQ logic arithmetic

International Nuclear Information System (INIS)

Mukhanov, O.A.; Rylov, S.V.; Semenov, V.K.; Vyshenskii, S.V.

1989-01-01

Several ways of local timing of the Josephson-junction RSFQ (Rapid Single Flux Quantum) logic elements are proposed, and their peculiarities are discussed. Several examples of serial and parallel pipelined arithmetic blocks using various types of timing are suggested and their possible performance is discussed. Serial devices enable one to perform n-bit functions relatively slowly but using integrated circuits of a moderate integration scale, while parallel pipelined devices are more hardware-wasteful but promise extremely high productivity

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

OpenAIRE

Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

2011-01-01

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling

International Nuclear Information System (INIS)

Lent, Craig S; Liu Mo; Lu Yuhui

2006-01-01

We examine power dissipation in different clocking schemes for molecular quantum-dot cellular automata (QCA) circuits. 'Landauer clocking' involves the adiabatic transition of a molecular cell from the null state to an active state carrying data. Cell layout creates devices which allow data in cells to interact and thereby perform useful computation. We perform direct solutions of the equation of motion for the system in contact with the thermal environment and see that Landauer's Principle applies: one must dissipate an energy of at least k B T per bit only when the information is erased. The ideas of Bennett can be applied to keep copies of the bit information by echoing inputs to outputs, thus embedding any logically irreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. A promising alternative which we term 'Bennett clocking' requires only altering the timing of the clocking signals so that bit information is simply held in place by the clock until a computational block is complete, then erased in the reverse order of computation. This approach results in ultralow power dissipation without additional circuit complexity. These results offer a concrete example in which to consider recent claims regarding the fundamental limits of binary logic scaling

Modeling a verification test system for mixed-signal circuits

NARCIS (Netherlands)

San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block

Synthesis of energy-efficient FSMs implemented in PLD circuits

Science.gov (United States)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

International Nuclear Information System (INIS)

Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

2010-01-01

Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

On Using Current Steering Logic in Mixed Analogue-digital Circuits

DEFF Research Database (Denmark)

Lehmann, Torsten

1998-01-01

The authors investigate power supply noise in mixed analogue-digital circuits, arising from communication between the analogue and digital parts of the circuit. Current steering techniques and proper buffering are used to show which noise currents can be reduced and which cannot. In addition......, a high-swing current steering buffer for driving analogue switches or external digital signals is proposed....

Memristor-based nanoelectronic computing circuits and architectures

CERN Document Server

Vourkas, Ioannis

2016-01-01

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today’s latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied t...

Modeling the critical safety functions status tree of a NPP using FPGA

International Nuclear Information System (INIS)

Farias, Marcos Santana; Oliveira, Mauro Vitor de; Jaime, Guilherme Dutra Gonzaga; Almeida, Jose Carlos Soares de; Augusto, Silas Cordeiro

2013-01-01

Field Programmable Gate Arrays (FPGAs) based systems and equipment are beginning to appear in new plants I and C applications, as well as in retrofits for operating plants, in particular for safety applications due to their capability to face the systems obsolescence since they are circuit independent. The circuits implemented can be portable to different FPGAs architectures. Moreover, they reduce complexity for regulatory approval as compared to conventional microprocessor-based systems. Critical safety function (CSF) is the most significant design concept for prioritize operator actions for NPP based on the potential threat to the three barriers (fuel cladding, primary coolant system boundary, and containment) and allows the operator to respond to these threats prior to event diagnosis. CSF has a hierarchical information structure that organizes the system variables affecting the plant safety in terms of goal-means relations. This paper describes the application of FPGA in the implementation of the CSFs status tree logic for a Westinghouse 3-loops NPP simulator. (author)

Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

Directory of Open Access Journals (Sweden)

Ruiping Cao

2014-01-01

Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Science.gov (United States)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Directory of Open Access Journals (Sweden)

Fabrizio Riente

2017-05-01

Full Text Available Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Micromagnetic simulation of exploratory magnetic logic device with missing corner defect

Energy Technology Data Exchange (ETDEWEB)

Yang, Xiaokuo, E-mail: yangxk0123@163.com; Cai, Li; Zhang, Bin; Cui, Huanqing; Zhang, Mingliang

2015-11-15

Magnetic film nanostructures are attractive components of nonvolatile magnetoresistive memories and nanomagnet logic circuits. Recently, we studied switching properties (i.e., null logic preserving) of rectangle shape nanomagnet subjected to fabrication imperfections. Specifically, we presented typical missing corner material-related imperfections and adopted an isosceles triangle to model this defect for nanomagnets. Micromagnetic simulation shows that this kind of imperfections modeling method agrees well with previous experimental observations. Using the proposed defect modeling scheme, we investigate in detail the switching characteristics of different defective stand-alone and coupled nanomagnets. The results suggest that the state transition of defective nanomagnet element highly depends on defect type and device’s aspect ratio, and the defect type B{sub d} needs the largest coercive field, while the defect type D requires the largest null field for switching. These findings can provide key technical parameters and guides for nanomagnet logic circuit design. - Highlights: • We have modeled missing corner defect issue for nanomagnet logic device. • The logic state of defective NML element highly depends on defect type and AR. • The NML device with defect type B{sub d} needs the largest coercive field to reverse state. • The defect type D in the NML devices requires the largest null field to switch.

Programmable logic controller (PLC) for safety systems of nuclear plants

International Nuclear Information System (INIS)

Sen, S.K.; Karmakar, G.; Joseph, Jose; Patil, R.K.

2002-01-01

Full text: A programmable logic controller (PLC) has been developed by RCnD, BARC for use in the safety critical systems in nuclear power plants. This PLC uses qualified hardware developed in RCnD for use in NPP. The programming software conforms to IEC-61131 part 3. The application programming is done on function block diagram (FBD) editor and the FBD is automatically converted into code in high level language (C / C++). This feature makes the application easily decipherable and therefore easily subjected to reviews and other validation techniques. The key to make quality software for use in nuclear systems is to enforce various standards in the design and development of the software, something, which is not possible to do with a commercially available PLC. This PLC with its software completely transparent lends itself to rigorous verification and validation easily

Graphene-based non-Boolean logic circuits

Science.gov (United States)

Liu, Guanxiong; Ahsan, Sonia; Khitun, Alexander G.; Lake, Roger K.; Balandin, Alexander A.

2013-10-01

Graphene revealed a number of unique properties beneficial for electronics. However, graphene does not have an energy band-gap, which presents a serious hurdle for its applications in digital logic gates. The efforts to induce a band-gap in graphene via quantum confinement or surface functionalization have not resulted in a breakthrough. Here we show that the negative differential resistance experimentally observed in graphene field-effect transistors of "conventional" design allows for construction of viable non-Boolean computational architectures with the gapless graphene. The negative differential resistance—observed under certain biasing schemes—is an intrinsic property of graphene, resulting from its symmetric band structure. Our atomistic modeling shows that the negative differential resistance appears not only in the drift-diffusion regime but also in the ballistic regime at the nanometer-scale—although the physics changes. The obtained results present a conceptual change in graphene research and indicate an alternative route for graphene's applications in information processing.

Automatic test pattern generation for stuck-at and delay faults in combinational circuits

International Nuclear Information System (INIS)

Kim, Dae Sik

1998-02-01

The present studies are developed to propose the automatic test pattern generation (ATG) algorithms for combinational circuits. These ATG algorithms are realized in two ATG programs: One is the ATG program for stuck-at fault and the other one for delay faults. In order to accelerate the ATG process, these two ATG programs have a common feature (the search method based on the concept of the degree of freedom), whereas only ATG program for the delay fault utilizes the 19-valued logic, a type of composite valued logic. This difference between two ATG programs results from the difference of the target fault. Accelerating the ATG process is indispensable for improving the ATG algorithms. This acceleration is mainly achieved by reducing the number of the unnecessary backtrackings, making the earlier detection of the conflicts, and shortening the computation time between the implication. Because of this purpose, the developed ATG programs include the new search method based on the concept of the degree of freedom (DF). The DF concept, computed directly and easily from the system descriptions such as types of gates and their interconnections, is the criterion to decide which, among several alternate lines' logic values required along each path, promises to be the most effective in order to accelerate and improve the ATG process. This DF concept is utilized to develop and improve both of ATG programs for stuck-at and delay faults in combinational circuits. In addition to improving the ATG process, reducing number of test pattern is indispensable for testing the delay faults because the size of the delay faults grows rapidly as increasing the size of the circuit. In order to improve the compactness of the test set, 19-valued logic are derived. Unlike other TG logic systems, 19-valued logic is utilized to generate the robustly hazard-free test pattern. This is achieved by using the basic 5-valued logic, proposed in this work, where the transition with no hazard is

Synchronization circuit for shaping electron beam picosecond pulses

International Nuclear Information System (INIS)

Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

1985-01-01

A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Situation analysis of physical independence of the equipment and safety circuits of Almaraz NPP regarding R.G. 1.75 rev.3 (2005)

International Nuclear Information System (INIS)

Seijas Portela, S.

2010-01-01

Situation analysis of physical independence of the electrical equipment and circuits CN safety Almaraz about R.G. 1.75 rev. 3. (2005) The aim of this paper is to present the work done in the analysis of the physical separation of redundant safety electrical equipment (emergency diesel generators, medium voltage, electrical cabinets, etc.) and physical separation of circuits and electrical conduits.

Design and qualification of HPD based designs for safety systems

International Nuclear Information System (INIS)

Sharma, Mukesh Kr.; Chavan, Madhavi A.; Sawhney, Pratibha A.; Mohanty, Ashutos; John, Ajith K.; Ganesh, G.

2014-01-01

Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are increasingly being used in C and I system of NPPs. The function of such an integrated circuit is not defined by the supplier of the physical component or micro-electronic technology but by the C and I designer. The hardware subsystems implemented in these devices typically use Hardware Description Language (HDL) like VHDL or Verilog to describe the functionality at the design entry level. These circuits are commonly known as 'HDL-Programmed Devices', (HPD). RCnD has developed a set of hardware boards to be used in next generation C and I systems. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented in HPDs (FPGA/CPLD) using VHDL. Since these boards are used in the safety and safety related systems, they have undergone a rigorous V and V process and qualification tests. This paper discusses the design attributes and qualification of these HPD based designs for nuclear class safety systems. (author)

Spintronic logic design methodology based on spin Hall effect–driven magnetic tunnel junctions

International Nuclear Information System (INIS)

Kang, Wang; Zhang, Youguang; Zhao, Weisheng; Wang, Zhaohao; Klein, Jacques-Olivier; Lv, Weifeng

2016-01-01

Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau–Lifshitz–Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing. (paper)

A fluorescent combinatorial logic gate with Na+, H+-enabled OR and H+-driven low-medium-high ternary logic functions.

Science.gov (United States)

Spiteri, Jasmine M A; Mallia, Carl J; Scerri, Glenn J; Magri, David C

2017-12-06

A novel fluorescent molecular logic gate with a 'fluorophore-spacer 1 -receptor 1 -spacer 2 -receptor 2 ' format is demonstrated in 1 : 1 (v/v) methanol/water. The molecule consists of an anthracene fluorophore, and tertiary alkyl amine and N-(2-methoxyphenyl)aza-15-crown-5 ether receptors. In the presence of threshold concentrations of H + and Na + , the molecule switches 'on' as an AND logic gate with a fluorescence quantum yield of 0.21 with proton and sodium binding constants of log β H+ = 9.0 and log β Na+ = 3.2, respectively. At higher proton levels, protonation also occurs at the anilinic nitrogen atom ether with a log β H+ = 4.2, which allows for Na + , H + -enabled OR (OR + AND circuit) and H + -driven ternary logic functions. The reported molecule is compared and contrasted to classic anthracene-based Na + and H + logic gates. We propose that such logic-based molecules could be useful tools for probing the vicinity of Na + , H + antiporters in biological systems.

DMILL circuits. The hardened electronics decuples its performances

International Nuclear Information System (INIS)

Anon.

1998-01-01

Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)

Password Based Distribution Panel and Circuit Breaker Operation for the Safety of Lineman during Maintenance Work

OpenAIRE

Hudedmani, Mallikarjun G; Ummannanavar, Nitin; Mudaliar, Mani Dheeraj; Sooji, Chandana; Bogar, Mala

2017-01-01

Security is the prime concern in our day to day life while performing any activity. In the current scenario, accidental death of lineman is often read and evidenced. In this direction, a safety measure to safe guard the operator is found very necessary looking into the present working style. The electric lineman safety system is designed to control the control panel doors and circuit breaker by using a password for the safety. Critical electrical accidents to lineman are on the rise during el...

Wiring of electronic evaluation circuits

International Nuclear Information System (INIS)

Bauer, R.; Svoboda, Z.

1977-01-01

The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

Verification of FPGA-Signal using the test board which is applied to Safety-related controller

Energy Technology Data Exchange (ETDEWEB)

Chung, Youn-Hu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [SOOSAN ENS, Seoul (Korea, Republic of)

2016-10-15

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. Saftety-related PLC must meet the international standard specifications. With this reason, we use V and V according to an international standard in order to secure high reliability and safety. By using this, we are supposed to proceed to a variety of verification courses for extra reliability and safety analysis. In order to have efficient verification of test results, we propose the test using the newly changed BGA socket which can resolve the problems of the conventional socket on this paper. The Verification of processes is divided into verification of Hardware and firmware. That processes are carried out in the unit testing and integration testing. The proposed test method is simple, the effect of cost reductions by batch process. In addition, it is advantageous to measure the signal from the Hi-speed-IC due to its short length of the pins and it was plated with the copper around it. Further, it also to prevent abrasion on the IC ball because it has no direct contact with the PCB. Therefore, it can be actually applied is to the BGA package test and we can easily verify logic as well as easily checking the operation of the designed data.

Material Targets for Scaling All-Spin Logic

Science.gov (United States)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

Directory of Open Access Journals (Sweden)

Salah Bouzina

2016-12-01

Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Directory of Open Access Journals (Sweden)

Qutaiba Alasad

2017-09-01

Full Text Available The outsourcing of integrated circuit (IC fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs to replace the conventional Exclusive-OR (XOR-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

30 CFR 75.800-1 - Circuit breakers; location.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit breakers; location. 75.800-1 Section 75.800-1 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR COAL MINE SAFETY... § 75.800-1 Circuit breakers; location. Circuit breakers protecting high-voltage circuits entering an...

30 CFR 75.900-1 - Circuit breakers; location.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit breakers; location. 75.900-1 Section 75.900-1 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR COAL MINE SAFETY... Alternating Current Circuits § 75.900-1 Circuit breakers; location. Circuit breakers used to protect low-and...

V and V methods of a safety-critical software for a programmable logic controller

Energy Technology Data Exchange (ETDEWEB)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Kong, Seung Ju [Korea Hydro and Nuclear Power Co., Ltd, Daejeon (Korea, Republic of)

2005-11-15

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects.

V and V methods of a safety-critical software for a programmable logic controller

International Nuclear Information System (INIS)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon; Kong, Seung Ju

2005-01-01

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects

A study on implementation of dynamic safety system in programmable logic controller for pressurized water reactor

International Nuclear Information System (INIS)

Kim, Ung Soo

1997-02-01

The dynamic safety system (DSS) is a computer based reactor protection system that has dynamic self-testing feature and fail-safe nature inherently. The inherent dynamic self-testing feature and fail-safe design provide a high level of reliability and low spurious trip rate. We can also reduce the time and human efforts to maintain the system by virtue of those features. Therefore, the application of the DSS to PWR has many advantages. The DSS has been applied only to advanced gas-cooled reactor (AGR) in the UK. In order to apply the DSS for PWR, the DSS has to be modified because there exist many differences between PWR and AGR for which the DSS was tested and installed. These differences are trip algorithms, monitored parameters, trip logics, and other conditions. In this study, the DSS algorithm is modified for PWR first. The modified DSS has several new features : 1) The modified DSS tests and processes time-dependent parameters, while the original DSS does not. 2) It has flexibility for handling several types of voting logic but the original DSS handles the only one type of voting - 2 out of 4 coincidence logic. Then, in this study, the modified DSS is implemented in programmable logic controller (PLC) using the ladder logic. Finally, the modified DSS is tested in two ways in this work : 1) The manual test is performed using direct input through the human computer interface (HCI) system. 2) The scenario based test is performed using input from the FISA-2/WS simulator. From the test results, it is shown that the modified DSS operates correctly in all conditions

A Novel Reconfigurable Logic Unit Based on the DNA-Templated Potassium-Concentration-Dependent Supramolecular Assembly.

Science.gov (United States)

Yang, Chunrong; Zou, Dan; Chen, Jianchi; Zhang, Linyan; Miao, Jiarong; Huang, Dan; Du, Yuanyuan; Yang, Shu; Yang, Qianfan; Tang, Yalin

2018-03-15

Plenty of molecular circuits with specific functions have been developed; however, logic units with reconfigurability, which could simplify the circuits and speed up the information process, are rarely reported. In this work, we designed a novel reconfigurable logic unit based on a DNA-templated, potassium-concentration-dependent, supramolecular assembly, which could respond to the input stimuli of H + and K + . By inputting different concentrations of K + , the logic unit could implement three significant functions, including a half adder, a half subtractor, and a 2-to-4 decoder. Considering its reconfigurable ability and good performance, the novel prototypes developed here may serve as a promising proof of principle in molecular computers. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

Science.gov (United States)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

Multi-input and -output logic circuits based on bioelectrocatalysis with horseradish peroxidase and glucose oxidase immobilized in multi-responsive copolymer films on electrodes.

Science.gov (United States)

Yu, Xue; Lian, Wenjing; Zhang, Jiannan; Liu, Hongyun

2016-06-15

Herein, poly(N-isopropylacrylamide-co-N,N'-dimethylaminoethylmethacrylate) copolymer films were polymerized on electrode surface with a simple one-step method, and the enzyme horseradish peroxidase (HRP) was embedded in the films simultaneously, which were designated as P(NiPAAm-co-DMEM)-HRP. The films exhibited a reversible structure change with the external stimuli, such as pH, CO2, temperature and SO4(2-), causing the cyclic voltammetric (CV) response of electroactive K3Fe(CN)6 at the film electrodes to display the corresponding multi-stimuli sensitive ON-OFF behavior. Based on the switchable CV property of the system and the electrochemical reduction of H2O2 catalyzed by HRP in the films and mediated by Fe(CN)6(3-) in solution, a 5-input/3-output logic gate was established. To further increase the complexity of the logic system, another enzyme glucose oxidase (GOD) was added into the films, designated as P(NiPAAm-co-DMEM)-HRP-GOD. In the presence of oxygen, the oxidation of glucose in the solution was catalyzed by GOD in the films, and the produced H2O2 in situ was recognized and electrocatalytically reduced by HRP and mediated by Fe(CN)6(3-). Based on the bienzyme films, a cascaded or concatenated 4-input/3-output logic gate system was proposed. The present work combined the multi-responsive interface with bioelectrocatalysis to construct cascaded logic circuits, which might open a new avenue to develop biocomputing elements with more sophisticated functions and design novel glucose biosensors. Copyright © 2016 Elsevier B.V. All rights reserved.

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

Science.gov (United States)

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Molecular logic gates: the past, present and future.

Science.gov (United States)

Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U

2018-04-03

The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.

A cell-based design approach for RSFQ circuits using a binary decision diagram

International Nuclear Information System (INIS)

Yoshikawa, N.; Koshiyama, J.

1999-01-01

We propose a cell-based design approach for rapid single flux quantum (RSFQ) circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function using a directed graph which consists of binary switches having one input and two outputs. Since complex logic circuits can be implemented in the form of regular arrays of the BDD binary switches, we can use a cell-based layout methodology for the design of the RSFQ circuits. In this study, we implemented the BDD binary switches by a D 2 flip-flop. In the BDD design approach we made a cell library which contains a binary switch, pulse splitters, confluence buffers and Josephson transmission lines. All cell layouts in the library have identical widths and heights, so that any logic function can be laid out by simple connection of the library cells. As a case study, we implemented a 1-bit RSFQ half-adder and a 3-bit encoder for a flash AD converter. (author)

Energy efficient circuit design using nanoelectromechanical relays

Science.gov (United States)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Small circuits for cryptography.

Energy Technology Data Exchange (ETDEWEB)

Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

2005-10-01

This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

30 CFR 77.506-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... short circuit protection; minimum requirements. 77.506-1 Section 77.506-1 Mineral Resources MINE SAFETY...-1 Electric equipment and circuits; overload and short circuit protection; minimum requirements. Devices providing either short circuit protection or protection against overload shall conform to the...

Automatic ranging circuit for a digital panel meter

International Nuclear Information System (INIS)

Mueller, T.R.; Ross, H.H.

1976-01-01

This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to ensure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit. The system was designed for readout of a fluorescence analyzer for uranium analysis

From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

International Nuclear Information System (INIS)

Register, L.F.; Basu, D.; Reddy, D.

2011-01-01

Colleagues and we recently proposed a new type of transistor, a Bilayer Pseudo Spin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineer able device parameters on the formation and gating of interlayer coherent state.

Reliability concerns with logical constants in Xilinx FPGA designs

Energy Technology Data Exchange (ETDEWEB)

Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX

2009-01-01

In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

Study and simulation of the time behaviour of MOS transistor devices. Application to a logic assembly

International Nuclear Information System (INIS)

Barocas, Marcel

1974-01-01

The objective of this research thesis is to determine, by simulation, the time response of devices based on MOS transistors. After a theoretical study of the MOS element, the author develops a transistor model based on its physical components. This model is firstly used to obtain the transistor static characteristics. The author then studies the time response of the inverter logic circuit which is the basic operator of these circuits. Theoretical results are verified by simulation and by experiments. The author then reports a detailed study of the inverter input impedance, and the decoupling property between logic operators in cascade. The simulation confirms the obtained results. Based on this decoupling property, the output time response of a logic chain is studied by using a simulation software. A general method of determination of the output time response is developed with application to a logic assembly [fr

A plausible neural circuit for decision making and its formation based on reinforcement learning.

Science.gov (United States)

Wei, Hui; Dai, Dawei; Bu, Yijie

2017-06-01

A human's, or lower insects', behavior is dominated by its nervous system. Each stable behavior has its own inner steps and control rules, and is regulated by a neural circuit. Understanding how the brain influences perception, thought, and behavior is a central mandate of neuroscience. The phototactic flight of insects is a widely observed deterministic behavior. Since its movement is not stochastic, the behavior should be dominated by a neural circuit. Based on the basic firing characteristics of biological neurons and the neural circuit's constitution, we designed a plausible neural circuit for this phototactic behavior from logic perspective. The circuit's output layer, which generates a stable spike firing rate to encode flight commands, controls the insect's angular velocity when flying. The firing pattern and connection type of excitatory and inhibitory neurons are considered in this computational model. We simulated the circuit's information processing using a distributed PC array, and used the real-time average firing rate of output neuron clusters to drive a flying behavior simulation. In this paper, we also explored how a correct neural decision circuit is generated from network flow view through a bee's behavior experiment based on the reward and punishment feedback mechanism. The significance of this study: firstly, we designed a neural circuit to achieve the behavioral logic rules by strictly following the electrophysiological characteristics of biological neurons and anatomical facts. Secondly, our circuit's generality permits the design and implementation of behavioral logic rules based on the most general information processing and activity mode of biological neurons. Thirdly, through computer simulation, we achieved new understanding about the cooperative condition upon which multi-neurons achieve some behavioral control. Fourthly, this study aims in understanding the information encoding mechanism and how neural circuits achieve behavior control

Radiation damage to integrated injection logic cells

International Nuclear Information System (INIS)

Pease, R.L.; Galloway, K.F.; Stehlin, R.A.

1975-01-01

The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (l 2 L) cell and an l 2 L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed

Volumetric and chemical control auxiliary circuit for a PWR primary circuit

International Nuclear Information System (INIS)

Costes, D.

1990-01-01

The volumetric and chemical control circuit has an expansion tank with at least one water-steam chamber connected to the primary circuit by a sampling pipe and a reinjection pipe. The sampling pipe feeds jet pumps controlled by valves. An action on these valves and pumps regulates the volume of the water in the primary circuit. A safety pipe controlled by a flap automatically injects water from the chamber into the primary circuit in case of ruptures. The auxiliary circuit has also systems for purifying the water and controlling the boric acid and hydrogen content [fr

Use of Fuzzy Logic Systems for Assessment of Primary Faults

Science.gov (United States)

Petrović, Ivica; Jozsa, Lajos; Baus, Zoran

2015-09-01

In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.

30 CFR 75.518-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electric equipment and circuits; overload and short circuit protection; minimum requirements. 75.518-1 Section 75.518-1 Mineral Resources MINE SAFETY... short circuit protection; minimum requirements. A device to provide either short circuit protection or...

Microdroplet-based universal logic gates by electrorheological fluid

KAUST Repository

Zhang, Mengying

2011-01-01

We demonstrate a uniquely designed microfluid logic gate with universal functionality, which is capable of conducting all 16 logic operations in one chip, with different input voltage combinations. A kind of smart colloid, giant electrorheological (GER) fluid, functions as the translation media among fluidic, electronic and mechanic information, providing us with the capability of performing large integrations either on-chip or off-chip, while the on-chip hybrid circuit is formed by the interconnection of the electric components and fluidic channels, where the individual microdroplets travelling in a channel represents a bit. The universal logic gate reveals the possibilities of achieving a large-scale microfluidic processor with more complexity for on-chip processing for biological, chemical as well as computational experiments. © 2011 The Royal Society of Chemistry.

Instantons in Self-Organizing Logic Gates

Science.gov (United States)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

Science.gov (United States)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

Science.gov (United States)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Exact Synthesis of Reversible Circuits Using A* Algorithm

Science.gov (United States)

Datta, K.; Rathi, G. K.; Sengupta, I.; Rahaman, H.

2015-06-01

With the growing emphasis on low-power design methodologies, and the result that theoretical zero power dissipation is possible only if computations are information lossless, design and synthesis of reversible logic circuits have become very important in recent years. Reversible logic circuits are also important in the context of quantum computing, where the basic operations are reversible in nature. Several synthesis methodologies for reversible circuits have been reported. Some of these methods are termed as exact, where the motivation is to get the minimum-gate realization for a given reversible function. These methods are computationally very intensive, and are able to synthesize only very small functions. There are other methods based on function transformations or higher-level representation of functions like binary decision diagrams or exclusive-or sum-of-products, that are able to handle much larger circuits without any guarantee of optimality or near-optimality. Design of exact synthesis algorithms is interesting in this context, because they set some kind of benchmarks against which other methods can be compared. This paper proposes an exact synthesis approach based on an iterative deepening version of the A* algorithm using the multiple-control Toffoli gate library. Experimental results are presented with comparisons with other exact and some heuristic based synthesis approaches.

Stochastic p -Bits for Invertible Logic

Science.gov (United States)

Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo

2017-07-01

Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small

A new quantum flux parametron logic gate with large input margin

International Nuclear Information System (INIS)

Hioe, W.; Hosoya, M.; Goto, E.

1991-01-01

This paper reports on the Quantum Flux Parametron (QFP) which is a flux transfer, flux activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device its correct operation may be affected by coupling to other QFPs. The problems include backcoupling from active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which being a linear input logic, has low input margin. A new logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise and reaction hazard are substantially reduced. Moreover, the input have little interaction hence input margin is greatly improved

Automatic design of digital synthetic gene circuits.

Directory of Open Access Journals (Sweden)

Mario A Marchisio

2011-02-01

Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

All-spin logic operations: Memory device and reconfigurable computing

Science.gov (United States)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Logic in the curricula of Computer Science

Directory of Open Access Journals (Sweden)

Margareth Quindeless

2014-12-01

Full Text Available The aim of the programs in Computer Science is to educate and train students to understand the problems and build systems that solve them. This process involves applying a special reasoning to model interactions, capabilities, and limitations of the components involved. A good curriculum must involve the use of tools to assist in these tasks, and one that could be considered as a fundamental is the logic, because with it students develop the necessary reasoning. Besides, software developers analyze the behavior of the program during the designed, the depuration, and testing; hardware designers perform minimization and equivalence verification of circuits; designers of operating systems validate routing protocols, programing, and synchronization; and formal logic underlying all these activities. Therefore, a strong background in applied logic would help students to develop or potentiate their ability to reason about complex systems. Unfortunately, few curricula formed and properly trained in logic. Most includes only one or two courses of Discrete Mathematics, which in a few weeks covered truth tables and the propositional calculus, and nothing more. This is not enough, and higher level courses in which they are applied and many other logical concepts are needed. In addition, students will not see the importance of logic in their careers and need to modify the curriculum committees or adapt the curriculum to reverse this situation.

Boolean Logic Tree of Label-Free Dual-Signal Electrochemical Aptasensor System for Biosensing, Three-State Logic Computation, and Keypad Lock Security Operation.

Science.gov (United States)

Lu, Jiao Yang; Zhang, Xin Xing; Huang, Wei Tao; Zhu, Qiu Yan; Ding, Xue Zhi; Xia, Li Qiu; Luo, Hong Qun; Li, Nian Bing

2017-09-19

The most serious and yet unsolved problems of molecular logic computing consist in how to connect molecular events in complex systems into a usable device with specific functions and how to selectively control branchy logic processes from the cascading logic systems. This report demonstrates that a Boolean logic tree is utilized to organize and connect "plug and play" chemical events DNA, nanomaterials, organic dye, biomolecule, and denaturant for developing the dual-signal electrochemical evolution aptasensor system with good resettability for amplification detection of thrombin, controllable and selectable three-state logic computation, and keypad lock security operation. The aptasensor system combines the merits of DNA-functionalized nanoamplification architecture and simple dual-signal electroactive dye brilliant cresyl blue for sensitive and selective detection of thrombin with a wide linear response range of 0.02-100 nM and a detection limit of 1.92 pM. By using these aforementioned chemical events as inputs and the differential pulse voltammetry current changes at different voltages as dual outputs, a resettable three-input biomolecular keypad lock based on sequential logic is established. Moreover, the first example of controllable and selectable three-state molecular logic computation with active-high and active-low logic functions can be implemented and allows the output ports to assume a high impediment or nothing (Z) state in addition to the 0 and 1 logic levels, effectively controlling subsequent branchy logic computation processes. Our approach is helpful in developing the advanced controllable and selectable logic computing and sensing system in large-scale integration circuits for application in biomedical engineering, intelligent sensing, and control.

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

International Nuclear Information System (INIS)

Lee, Youngmin; Lee, Sejoon; Im, Hyunsik; Hiramoto, Toshiro

2015-01-01

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

Energy Technology Data Exchange (ETDEWEB)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik [Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715 (Korea, Republic of); Hiramoto, Toshiro [Institute of Industrial Science, University of Tokyo, Tokyo 153-8505 (Japan)

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

Plastic Logic quits e-reader market

Science.gov (United States)

Perks, Simon

2012-07-01

A UK firm spun out from the University of Cambridge that sought to be a world leader in flexible organic electronic circuits and displays has pulled out of the competitive e-reader market as it struggles to find a commercial outlet for its technology. Plastic Logic announced in May that it is to close its development facility in Mountain View, California, with the loss of around 40 jobs.

Fabrication and simulation of organic transistors and functional circuits

Energy Technology Data Exchange (ETDEWEB)

Taylor, D. Martin, E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Patchett, Eifion R.; Williams, Aled [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Ding, Ziqian; Assender, Hazel E. [Department of Materials, Oxford University, Parks Road, Oxford OX1 3PH (United Kingdom); Morrison, John J.; Yeates, Stephen G. [School of Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom)

2015-07-29

Highlights: • Development of roll-to-roll fabrication protocol for organic TFTs and circuits. • Bottom-gate polystyrene/DNTT TFTs much better than top-gate TFTs. • High-yield and high mobility with polystyrene-buffered TPGDA. • Fabrication of functional circuits – ring oscillators and logic gates. • New baseline process allows TFT parameter extraction and circuit simulation. - Abstract: We report the development of a vacuum-evaporation route for the roll-to-roll fabrication of functioning organic circuits. A number of key findings and observations are highlighted which influenced the eventual fabrication protocol adopted. Initially, the role of interface roughness in determining carrier mobility in thin film transistors (TFTs) is investigated. Then it is shown that TFT yield is higher for devices fabricated on a flash-evaporated-plasma-polymerised tri(propyleneglycol) diacrylate (TPGDA) gate dielectric than for TFTs based on a spin-coated polystyrene (PS) dielectric. However, a degradation in mobility is observed which is attributed to the highly polar TPGDA surface. It is shown that high mobility, low gate-leakage currents and excellent stability are restored when the surface of TPGDA was buffered with a thin, spin-coated PS film. The resulting baseline process allowed arrays of functional circuits such as ring oscillators, NOR/NAND logic gates and S–R latches to be fabricated with high yield and their performance to be simulated.

Compact representations for the design of quantum logic

CERN Document Server

Niemann, Philipp

2017-01-01

This book discusses modern approaches and challenges of computer-aided design (CAD) of quantum circuits with a view to providing compact representations of quantum functionality. Focusing on the issue of quantum functionality, it presents Quantum Multiple-Valued Decision Diagrams (QMDDs – a means of compactly and efficiently representing and manipulating quantum logic. For future quantum computers, going well beyond the size of present-day prototypes, the manual design of quantum circuits that realize a given (quantum) functionality on these devices is no longer an option. In order to keep up with the technological advances, methods need to be provided which, similar to the design and synthesis of conventional circuits, automatically generate a circuit description of the desired functionality. To this end, an efficient representation of the desired quantum functionality is of the essence. While straightforward representations are restricted due to their (exponentially) large matrix descriptions and other de...

Study of Reversible Logic Synthesis with Application in SOC: A Review

Science.gov (United States)

Sharma, Chinmay; Pahuja, Hitesh; Dadhwal, Mandeep; Singh, Balwinder

2017-08-01

The prime concern in today’s SOC designs is the power dissipation which increases with technology scaling. The reversible logic possesses very high potential in reducing power dissipation in these designs. It finds its application in latest research fields such as DNA computing, quantum computing, ultra-low power CMOS design and nanotechnology. The reversible circuits can be easily designed using the conventional CMOS technology at a cost of a garbage output which maintains the reversibility. The purpose of this paper is to provide an overview of the developments that have occurred till date in this concept and how the new reversible logic gates are used to design the logic functions.

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications

OpenAIRE

Pan, Chenyun; Naeemi, Azad

2017-01-01

The latest results of benchmarking research are presented for a variety of beyond-CMOS charge- and spin-based devices. In addition to improving the device-level models, several new device proposals and a few majorly modified devices are investigated. Deep pipelining circuits are employed to boost the throughput of low-power devices. Furthermore, the benchmarking methodology is extended to interconnect-centric analyses and non-Boolean logic applications. In contrast to Boolean circuits, non-Bo...

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

Science.gov (United States)

Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

2009-01-01

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Multi-valued and Fuzzy Logic Realization using TaOx Memristive Devices.

Science.gov (United States)

Bhattacharjee, Debjyoti; Kim, Wonjoo; Chattopadhyay, Anupam; Waser, Rainer; Rana, Vikas

2018-01-08

Among emerging non-volatile storage technologies, redox-based resistive switching Random Access Memory (ReRAM) is a prominent one. The realization of Boolean logic functionalities using ReRAM adds an extra edge to this technology. Recently, 7-state ReRAM devices were used to realize ternary arithmetic circuits, which opens up the computing space beyond traditional binary values. In this manuscript, we report realization of multi-valued and fuzzy logic operators with a representative application using ReRAM devices. Multi-valued logic (MVL), such as Łukasiewicz logic generalizes Boolean logic by allowing more than two truth values. MVL also permits operations on fuzzy sets, where, in contrast to standard crisp logic, an element is permitted to have a degree of membership to a given set. Fuzzy operations generally model human reasoning better than Boolean logic operations, which is predominant in current computing technologies. When the available information for the modelling of a system is imprecise and incomplete, fuzzy logic provides an excellent framework for the system design. Practical applications of fuzzy logic include, industrial control systems, robotics, and in general, design of expert systems through knowledge-based reasoning. Our experimental results show, for the first time, that it is possible to model fuzzy logic natively using multi-state memristive devices.

A programming language for composable DNA circuits.

Science.gov (United States)

Phillips, Andrew; Cardelli, Luca

2009-08-06

Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

Science.gov (United States)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Nuclear reactor safety protection device

International Nuclear Information System (INIS)

Okido, Fumiyasu; Noguchi, Atomi; Matsumiya, Shoichi; Furusato, Ken-ichiro; Arita, Setsuo.

1994-01-01

The device of the present invention extremely reduces a probability of causing unnecessary scram of a nuclear reactor. That is, four control devices receive signals from each of four sensors and output four trip signals respectively in a quardruplicated control device. Each of the trip signals and each of trip signals via a delay circuit are inputted to a logical sum element. The output of the logical sum circuit is inputted to a decision of majority circuit. The decision of majority circuit controls a scram pilot valve which conducts scram of the reactor by way of a solenoid coils. With such procedures, even if surge noises of a short pulse width are mixed to the sensor signals and short trip signals are outputted, there is no worry that the scram pilot valve is actuated. Accordingly, factors of lowering nuclear plant operation efficiency due to erroneous reactor scram can be reduced. (I.S.)

Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates

International Nuclear Information System (INIS)

Duce, A Del; Savory, S; Bayvel, P

2006-01-01

In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another

Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates

Energy Technology Data Exchange (ETDEWEB)

Duce, A Del; Savory, S; Bayvel, P [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London WC1E 7JE (United Kingdom)

2006-05-31

In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.

Implementation of a three-qubit refined Deutsch Jozsa algorithm using SFG quantum logic gates

Science.gov (United States)

DelDuce, A.; Savory, S.; Bayvel, P.

2006-05-01

In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.

Analysis of Electrical Safety Conditions Taking into Account Soil Conductivity Determined on the Basis of Fuzzy Logic

OpenAIRE

Manusov, V.Z.; Zaytseva, N.M.

2017-01-01

The goal of this work is to prove a possibility of determining soil parameters that influence its conductivity being the basis of grounding, step voltage and touch voltage calculation. This in its turn increases the safety level of electric equipment operation. The article is devoted to development of new, no conventional models of soil conductivity using the theory of fuzzy sets and fuzzy logic. The description of the solution includes the following sections: fuzzy models of specific electri...

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Elements configuration of the open lead test circuit

International Nuclear Information System (INIS)

Fukuzaki, Yumi; Ono, Akira

2016-01-01

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

Elements configuration of the open lead test circuit

Energy Technology Data Exchange (ETDEWEB)

Fukuzaki, Yumi, E-mail: 14514@sr.kagawa-nct.ac.jp [Advanced course of Electronics, Information and Communication Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan); Ono, Akira [Department of Communication Network Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan)

2016-07-06

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

Junction and circuit fabrication

International Nuclear Information System (INIS)

Jackel, L.D.

1980-01-01

Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

Science.gov (United States)

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Development of the signalling circuits for reactor emergency protection systems

International Nuclear Information System (INIS)

Volkov, A.V.; Nikiforov, B.N.; Ogon'kov, A.I.; Sychinskij, Yu.L.

1978-01-01

Construction of circuits for nuclear reactor emergency protection according to the power level and rate of power rise with the use of integrated microcircuits is discussed. Circuits of relay- and transformer-based logical signaling devices are presented. It is noted that disadvantages of a transformer-based loaical sianaling device are great power consumption (about 300 mW) and slow response limited by the time constant of the output smoothing filter. Further development of circuits under consideration is associated with the employment of new optronic elements intended to replace the transformers

Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

Directory of Open Access Journals (Sweden)

Liang Zhou

2015-10-01

Full Text Available This paper proposes a radiation hardened NULL Convention Logic (NCL architecture that can recover from a single event latchup (SEL or single event upset (SEU fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

International Nuclear Information System (INIS)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

2016-01-01

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

2016-10-15

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

An Intelligent and Fast Chaotic Encryption Using Digital Logic Circuits for Ad-Hoc and Ubiquitous Computing

Directory of Open Access Journals (Sweden)

Ankur Khare

2016-05-01

Full Text Available Delays added by the encryption process represent an overhead for smart computing devices in ad-hoc and ubiquitous computing intelligent systems. Digital Logic Circuits are faster than other computing techniques, so these can be used for fast encryption to minimize processing delays. Chaotic Encryption is more attack-resilient than other encryption techniques. One of the most attractive properties of cryptography is known as an avalanche effect, in which two different keys produce distinct cipher text for the same information. Important properties of chaotic systems are sensitivity to initial conditions and nonlinearity, which makes two similar keys that generate different cipher text a source of confusion. In this paper a novel fast and secure Chaotic Map-based encryption technique using 2’s Compliment (CET-2C has been proposed, which uses a logistic map which implies that a negligible difference in parameters of the map generates different cipher text. Cryptanalysis of the proposed algorithm shows the strength and security of algorithm and keys. Performance of the proposed algorithm has been analyzed in terms of running time, throughput and power consumption. It is to be shown in comparison graphs that the proposed algorithm gave better results compare to different algorithms like AES and some others.

Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams

DEFF Research Database (Denmark)

Hulgaard, Henrik; Williams, Poul Frederick; Andersen, Henrik Reif

1999-01-01

The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually...... or by a design automation tool).This paper introduces a data structure called Boolean Expression Diagrams (BEDs) and two algorithms for transforming a BED into a Reduced Ordered Binary Decision Diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural...... similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDDs (which are canonical).Based on a large number of combinational...

From Boolean logic to switching circuits and automata. Towards modern information technology

Energy Technology Data Exchange (ETDEWEB)

Stankovic, Radomir S. [Nis Univ. (RS). Dept. of Computer Science; Astola, Jaakko [Tampere Univ. of Technology (Finland). Dept. of Signal Processing

2011-07-01

Logic networks and automata are facets of digital systems. The change of the design of logic networks from skills and art into a scientific discipline was possible by the development of the underlying mathematical theory called the Switching Theory. The fundamentals of this theory come from the attempts towards an algebraic description of laws of thoughts presented in the works by George J. Boole and the works on logic by Augustus De Morgan. As often the case in engineering, when the importance of a problem and the need for solving it reach certain limits, the solutions are searched by many scholars in different parts of the word, simultaneously or at about the same time, however, quite independently and often unaware of the work by other scholars. The formulation and rise of Switching Theory is such an example. This book presents a brief account of the developments of Switching Theory and highlights some less known facts in the history of it. The readers will find the book a fresh look into the development of the field revealing how difficult it has been to arrive at many of the concepts that we now consider obvious. Researchers in the history or philosophy of computing will find this book a valuable source of information that complements the standard presentations of the topic. (orig.)

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

Science.gov (United States)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

KAUST Repository

Chappanda, K N

2018-02-16

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

KAUST Repository

Chappanda , K. N.; Ilyas, Saad; Younis, Mohammad I.

2018-01-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

Multi parametric card to personal computers interface based in ispLSI1016 circuits

International Nuclear Information System (INIS)

Osorio Deliz, J.F.; Toledo Acosta, R.B.; Arista Romeu, E.

1997-01-01

It is described the design and principal characteristic of the interface circuit for a 16 bit multi parametric add on card for IBM or compatible microcomputer which content two communication channels of direct memory access and bidirectional between the card and the computer, an interrupt controller, a programmable address register, a default add res register of the card, a four channels multiplexer, as well as the decoder logic of the 80C186 and computer. The circuit was designed with two programmable logic devices ispL1016, which allowed drastically to diminish the quantity of utilized components and get a more flexible design in less time better characteristics

Electromigration inside logic cells modeling, analyzing and mitigating signal electromigration in nanoCMOS

CERN Document Server

Posser, Gracieli; Reis, Ricardo

2017-01-01

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. .

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

Science.gov (United States)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Novel latch for adiabatic quantum-flux-parametron logic

International Nuclear Information System (INIS)

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki; Ortlepp, Thomas

2014-01-01

We herein propose the quantum-flux-latch (QFL) as a novel latch for adiabatic quantum-flux-parametron (AQFP) logic. A QFL is very compact and compatible with AQFP logic gates and can be read out in one clock cycle. Simulation results revealed that the QFL operates at 5 GHz with wide parameter margins of more than ±22%. The calculated energy dissipation was only ∼0.1 aJ/bit, which yields a small energy delay product of 20 aJ·ps. We also designed shift registers using QFLs to demonstrate more complex circuits with QFLs. Finally, we experimentally demonstrated correct operations of the QFL and a 1-bit shift register (a D flip-flop)

Power analysis dataset for QCA based multiplexer circuits

Directory of Open Access Journals (Sweden)

Md. Abdullah-Al-Shafi

2017-04-01

Full Text Available Power consumption in irreversible QCA logic circuits is a vital and a major issue; however in the practical cases, this focus is mostly omitted.The complete power depletion dataset of different QCA multiplexers have been worked out in this paper. At −271.15 °C temperature, the depletion is evaluated under three separate tunneling energy levels. All the circuits are designed with QCADesigner, a broadly used simulation engine and QCAPro tool has been applied for estimating the power dissipation.

30 CFR 75.601 - Short circuit protection of trailing cables.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection of trailing cables. 75... MINE SAFETY AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Trailing Cables § 75.601 Short circuit protection of trailing cables. [Statutory Provisions] Short circuit protection for trailing cables...

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Count-doubling time safety circuit

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.; Rusch, G.K.

1981-01-01

There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary

Count-doubling time safety circuit

Science.gov (United States)

Rusch, Gordon K.; Keefe, Donald J.; McDowell, William P.

1981-01-01

There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary.

Proposal of unilateral single-flux-quantum logic gate

International Nuclear Information System (INIS)

Mikaye, H.; Fukaya, N.; Okabe, Y.; Sugamo, T.

1985-01-01

A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

Science.gov (United States)

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

Low Power Consumption Complementary Inverters with n-MoS2 and p-WSe2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits.

Science.gov (United States)

Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil

2015-10-14

Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

High-voltage integrated transmitting circuit with differential driving for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

2016-01-01

In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

Microsphere-based immunoassay integrated with a microfluidic network to perform logic operations

International Nuclear Information System (INIS)

Sabhachandani, Pooja; Cohen, Noa; Sarkar, Saheli; Konry, Tania

2015-01-01

Lab on a chip (LOC) intelligent diagnostics can be described by molecular logic-based circuits. We report on the development of an LOC approach with logic capability for screening combinations of antigen and antibody in the same sample. A microsphere-based immunoassay was integrated with a microfluidic network device to perform the logic operations AND and INHIBIT. Using the clinically relevant biomarkers TNF-α cytokine and anti-TNF-α antibody, we obtained a fluorescent output in the presence of both inputs. This results in an AND operation, while the presence of only one specific input results in a different fluorescent signal, thereby indicating the INHIBIT operation. This approach demonstrates the effective use of molecular logic computation for developing portable, point-of-care technologies for diagnostic purposes due to fast detection times, minimal reagent consumption and low costs. This model system may be further expanded to screening of multiple disease markers, combinatorial logic applications, and developing “smart” sensors and therapeutic technologies. (author)

Circuit Simulation for Solar Power Maximum Power Point Tracking with Different Buck-Boost Converter Topologies

Directory of Open Access Journals (Sweden)

Jaw-Kuen Shiau

2014-08-01

Full Text Available The power converter is one of the essential elements for effective use of renewable power sources. This paper focuses on the development of a circuit simulation model for maximum power point tracking (MPPT evaluation of solar power that involves using different buck-boost power converter topologies; including SEPIC, Zeta, and four-switch type buck-boost DC/DC converters. The circuit simulation model mainly includes three subsystems: a PV model; a buck-boost converter-based MPPT system; and a fuzzy logic MPPT controller. Dynamic analyses of the current-fed buck-boost converter systems are conducted and results are presented in the paper. The maximum power point tracking function is achieved through appropriate control of the power switches of the power converter. A fuzzy logic controller is developed to perform the MPPT function for obtaining maximum power from the PV panel. The MATLAB-based Simulink piecewise linear electric circuit simulation tool is used to verify the complete circuit simulation model.

Toward a generalized and high-throughput enzyme screening system based on artificial genetic circuits.

Science.gov (United States)

Choi, Su-Lim; Rha, Eugene; Lee, Sang Jun; Kim, Haseong; Kwon, Kilkoang; Jeong, Young-Su; Rhee, Young Ha; Song, Jae Jun; Kim, Hak-Sung; Lee, Seung-Goo

2014-03-21

Large-scale screening of enzyme libraries is essential for the development of cost-effective biological processes, which will be indispensable for the production of sustainable biobased chemicals. Here, we introduce a genetic circuit termed the Genetic Enzyme Screening System that is highly useful for high-throughput enzyme screening from diverse microbial metagenomes. The circuit consists of two AND logics. The first AND logic, the two inputs of which are the target enzyme and its substrate, is responsible for the accumulation of a phenol compound in cell. Then, the phenol compound and its inducible transcription factor, whose activation turns on the expression of a reporter gene, interact in the other logic gate. We confirmed that an individual cell harboring this genetic circuit can present approximately a 100-fold higher cellular fluorescence than the negative control and can be easily quantified by flow cytometry depending on the amounts of phenolic derivatives. The high sensitivity of the genetic circuit enables the rapid discovery of novel enzymes from metagenomic libraries, even for genes that show marginal activities in a host system. The crucial feature of this approach is that this single system can be used to screen a variety of enzymes that produce a phenol compound from respective synthetic phenyl-substrates, including cellulase, lipase, alkaline phosphatase, tyrosine phenol-lyase, and methyl parathion hydrolase. Consequently, the highly sensitive and quantitative nature of this genetic circuit along with flow cytometry techniques could provide a widely applicable toolkit for discovering and engineering novel enzymes at a single cell level.

THE FUZZY LOGIC BASED POWER INJECTION INTO ROTOR CIRCUIT FOR INSTANTANEOUS HIGH TORQUE AND SPEED CONTROL IN INDUCTION MACHINES

Directory of Open Access Journals (Sweden)

Selami KESLER

2009-01-01

Full Text Available The power flow of the rotor circuit is controlled by different methods in induction machines used for producing high torque in applications involved great power and constant output power with constant frequency in wind turbines. The voltage with slip frequency can be applied on rotor windings to produce controlled high torque and obtain optimal power factor and speed control. In this study, firstly, the dynamic effects of the voltage applying on rotor windings through the rings in slip-ring induction machines are researched and undesirable aspects of the method are exposed with simulations supported by experiments. Afterwards, a fuzzy logic based inverter model on rotor side is proposed with a view to improving the dynamic effects, controlling high torque producing and adjusting machine speed in instantaneous forced conditions. For the simulation model of the system in which the stator side is directly connected to the grid in steady state operation, a C/C++ algorithm is developed and the results obtained for different load conditions are discussed.

Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.

Science.gov (United States)

Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek

2015-08-07

The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status.

Embedding Logics into Product Logic

Czech Academy of Sciences Publication Activity Database

Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David

1998-01-01

Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics

A formal safety analysis for PLC software-based safety critical system using Z

International Nuclear Information System (INIS)

Koh, Jung Soo; Seong, Poong Hyun

1997-01-01

This paper describes a formal safety analysis technique which is demonstrated by performing empirical formal safety analysis with the case study of beamline hutch door Interlock system that is developed by using PLC (Programmable Logic Controller) systems at the Pohang Accelerator Laboratory. In order to perform formed safety analysis, we have built the Z formal specifications representation from user requirement written in ambiguous natural language and target PLC ladder logic, respectively. We have also studied the effective method to express typical PLC timer component by using specific Z formal notation which is supported by temporal history. We present a formal proof technique specifying and verifying that the hazardous states are not introduced into ladder logic in the PLC-based safety critical system

Fundamental physics issues of multilevel logic in developing a parallel processor.

Science.gov (United States)

Bandyopadhyay, Anirban; Miki, Kazushi

2007-06-01

In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.

Feasibility study and uncertainties in the validation of an existing safety-related control circuit with the ISO 13849-1:2006 design standard

International Nuclear Information System (INIS)

Jocelyn, Sabrina; Baudoin, James; Chinniah, Yuvin; Charpentier, Philippe

2014-01-01

In industry, machine users and people who modify or integrate equipment often have to evaluate the safety level of a safety-related control circuit that they have not necessarily designed. The modifications or integrations may involve work to make an existing machine that does not comply with normative or regulatory specifications safe. However, how can a circuit performing a safety function be validated a posteriori? Is the validation exercise feasible? What are the difficulties and limitations of such a procedure? The aim of this article is to answer these questions by presenting a validation study of a safety function of an existing machine. A plastic injection molding machine is used for this study, as well as standard ISO 13849-1:2006. Validation consists of performing an a posteriori (post-design) estimation of the performance level of the safety function. The procedure is studied for two contexts of use of the machine: in industry, and in laboratory. The calculations required by the ISO standard were done using Excel, followed by SIStema software. It is shown that, based on the context of use, the estimated performance level was different for the same safety-related circuit. The variability in the results is explained by the assumptions made by the person undertaking the validation without the involvement of the machine designer. - Highlights: • Validation of the performance level of a safety function is undertaken. • An injection molding machine and ISO 13849-1:2006 standard are used for the procedure. • The procedure is undertaken for two contexts of use of the machine. • In this study, the performance level depends on the context of use. • The assumptions made throughout the study partially explain this difference

Surface confined assemblies and polymers for sensing and molecular logic

Science.gov (United States)

de Ruiter, Graham; Altman, Marc; Motiei, Leila; Lahav, Michal; van der Boom, Milko E.

2013-05-01

Since the development of molecule-based sensors and the introduction of molecules mimicking the behavior of the AND gate in solution by de Silva in 1993, molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. The molecular approach toward Boolean logic resulted in intriguing proofs of concepts in solution including logic gates, half-adders, multiplexers, and flip-flop logic circuits. Molecular assemblies can perform diverse logic tasks by reconfiguring their inputs. Our recent research activities focus on MBLC with electrochromic polymers and immobilized polypyridyl complexes on solid support. We have designed a series of coordination-based thin films that are formed linearly by stepwise wet-chemical deposition or by self-propagating molecular assembly. The electrochromic properties of these films can be used for (i) detecting various analytes in solution and in the air, (ii) MBLC, (iii) electron-transfer studies, and (iv) interlayers for efficient inverted bulk-heterojunction solar cells. Our concept toward MBLC with functionalized surfaces is applicable to electrochemical and chemical inputs coupled with optical readout. Using this approach, we demonstrated various logic architectures with redox-active functionalized surfaces. Electrochemically operated sequential logic systems (e.g., flip-flops), multi-valued logic, and multi-state memory have been designed, which can improve computational power without increasing spatial requirements. Applying multi-valued digits in data storage and information processing could exponentially increase memory capacity. Our approach is applicable to highly diverse electrochromic thin films that operate at practical voltages (< 1.5 V).

Optimally Fortifying Logic Reliability through Criticality Ranking

Directory of Open Access Journals (Sweden)

Yu Bai

2015-02-01

Full Text Available With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI and hot carrier injection (HCI. This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the VDD values of some LUTs based on their modular criticality values. Although the idea of scaling VDD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the VDD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table, which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT’s reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

30 CFR 57.4011 - Abandoned electric circuits.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Abandoned electric circuits. 57.4011 Section 57.4011 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL... and Control § 57.4011 Abandoned electric circuits. Abandoned electric circuits shall be deenergized...

Modeling and the analysis of control logic for a digital PWM controller based on a nano electronic single electron transistor

Directory of Open Access Journals (Sweden)

Rathnakannan Kailasam

2008-01-01

Full Text Available This paper describes the modelling and the analysis of control logic for a Nano-Device- based PWM controller. A comprehensive simple SPICE schematic model for Single Electron transistor has been proposed. The operation of basic Single Electron Transistor logic gates and SET flip flops were successfully designed and their performances analyzed. The proposed design for realizing the logic gates and flip-flops is used in constructing the PWM controller utilized for switching the buck converter circuit. The output of the converter circuit is compared with reference voltage, and when the error voltage and the reference are matched the latch is reset so as to generate the PWM signal. Due to the simplicity and accuracy of the compact model, the simulation time and speed are much faster, which makes it potentially applicable in large-scale circuit simulation. This study confirms that the SET-based PWM controller is small in size, consumes ultra low power and operates at high speeds without compromising any performance. In addition these devices are capable of measuring charges of extremely high sensitivity.

Logic computation in phase change materials by threshold and memory switching.

Science.gov (United States)

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Six-Correction Logic (SCL Gates in Quantum-dot Cellular Automata (QCA

Directory of Open Access Journals (Sweden)

Md. Anisur Rahman

2015-11-01

Full Text Available Quantum Dot Cellular Automata (QCA is a promising nanotechnology in Quantum electronics for its ultra low power consumption, faster speed and small size features. It has significant advantages over the Complementary Metal–Oxide–Semiconductor (CMOS technology. This paper present, a novel QCA representation of Six-Correction Logic (SCL gate based on QCA logic gates: the Maj3, Maj AND gate and Maj OR. In order to design and verify the functionality of the proposed layout, QCADesigner a familiar QCA simulator has been employed. The simulation results confirm correctness of the claims and its usefulness in designing a digital circuits.

Development of a multi-purpose logic module with the FPGA

International Nuclear Information System (INIS)

Nanbu, K.; Ishikawa, T.; Shimizu, H.

2008-01-01

We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

Science.gov (United States)

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Design Techniques for Power-Aware Combinational Logic SER Mitigation

Science.gov (United States)

Mahatme, Nihaar N.

The history of modern semiconductor devices and circuits suggests that technologists have been able to maintain scaling at the rate predicted by Moore's Law [Moor-65]. With improved performance, speed and lower area, technology scaling has also exacerbated reliability issues such as soft errors. Soft errors are transient errors that occur in microelectronic circuits due to ionizing radiation particle strikes on reverse biased semiconductor junctions. These radiation induced errors at the terrestrial-level are caused due to radiation particle strikes by (1) alpha particles emitted as decay products of packing material (2) cosmic rays that produce energetic protons and neutrons, and (3) thermal neutrons [Dodd-03], [Srou-88] and more recently muons and electrons [Ma-79] [Nara-08] [Siew-10] [King-10]. In the space environment radiation induced errors are a much bigger threat and are mainly caused by cosmic heavy-ions, protons etc. The effects of radiation exposure on circuits and measures to protect against them have been studied extensively for the past 40 years, especially for parts operating in space. Radiation particle strikes can affect memory as well as combinational logic. Typically when these particles strike semiconductor junctions of transistors that are part of feedback structures such as SRAM memory cells or flip-flops, it can lead to an inversion of the cell content. Such a failure is formally called a bit-flip or single-event upset (SEU). When such particles strike sensitive junctions part of combinational logic gates they produce transient voltage spikes or glitches called single-event transients (SETs) that could be latched by receiving flip-flops. As the circuits are clocked faster, there are more number of clocking edges which increases the likelihood of latching these transients. In older technology generations the probability of errors in flip-flops due to SETs being latched was much lower compared to direct strikes on flip-flops or SRAMs leading to

A formal safety analysis for PLC software-based safety critical system using Z

International Nuclear Information System (INIS)

Koh, Jung Soo

1997-02-01

This paper describes a formal safety analysis technique which is demonstrated by performing empirical formal safety analysis with the case study of beamline hutch door Interlock system that is developed by using PLC (Programmable Logic Controller) systems at the Pohang Accelerator Laboratory. In order to perform formal safety analysis, we have built the Z formal specifications representation from user requirement written in ambiguous natural language and target PLC ladder logic, respectively. We have also studied the effective method to express typical PLC timer component by using specific Z formal notation which is supported by temporal history. We present a formal proof technique specifying and verifying that the hazardous states are not introduced into ladder logic in the PLC-based safety critical system. And also, we have found that some errors or mismatches in user requirement and final implemented PLC ladder logic while analyzing the process of the consistency and completeness of Z translated formal specifications. In the case of relatively small systems like Beamline hutch door interlock system, a formal safety analysis including explicit proof is highly recommended so that the safety of PLC-based critical system may be enhanced and guaranteed. It also provides a helpful benefits enough to comprehend user requirement expressed by ambiguous natural language

Development of a diffuse element matrix in 'planar' technology. A particular application: logical gate with coupled emitter

International Nuclear Information System (INIS)

Rousseau, P.

1968-01-01

In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [fr

[Work accidents and automatic circuit reclosers in the electricity sector: beyond the immediate causes].

Science.gov (United States)

Silva, Alessandro Jose Nunes da; Almeida, Ildeberto Muniz de; Vilela, Rodolfo Andrade de Gouveia; Mendes, Renata Wey Berti; Hurtado, Sandra Lorena Beltran

2018-05-10

The Brazilian electricity sector has recorded high work-related mortality rates that have been associated with outsourcing, used to cut costs. In order to decrease the power outage time for consumers, the industry adopted the automatic circuit recloser as the technical solution. The device has hazardous implications for maintenance workers. The aim of this study was to analyze the origins and consequences of work accidents in power systems with automatic circuit recloser, using the Accident Analysis and Prevention (AAP) model. The AAP model was used to investigate two work accidents, aimed to explore the events' organizational origins. Case 1 - when changing a deenergized secondary line, a worker received a shock from the energized primary cable (13.8kV). The system reclosed three times, causing severe injury to the worker (amputation of a lower limb). Case 2 - a fatal work accident occurred during installation of a new crosshead on a partially insulated energized line. The tip of a metal cross arm section strap touched the energized secondary line and electrocuted the maintenance operator. The circuit breaker component of the automatic circuit recloser failed. The analyses revealed how business management logic can participate in the root causes of work accidents through failures in maintenance management, outsourced workforce management, and especially safety management in systems with reclosers. Decisions to adopt automation to guarantee power distribution should not overlook the risks to workers in overhead power lines or fail to acknowledge the importance of ensuring safe conditions.

Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

International Nuclear Information System (INIS)

Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik

2015-01-01

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)

Experience with the use of programmable logic controllers in nuclear safety applications. Final report

International Nuclear Information System (INIS)

Brown, E.M.; Stofko, M.J.

1995-03-01

This report describes the implementation and experience with Programmable Logic Controllers (PLC) for nuclear safety applications. Two applications are described. The first is an Anticipated Transient Without Scram (ATWS) mitigation system provided as a Diverse Auxiliary Feedwater Actuation System (DAFAS). It was implemented at Arizona Public Service's Palo Verde Nuclear Generating Station and has been in commercial operation since early 1992. The second system described is an Emergency Diesel Generator Bus Load Sequencer installed at Florida Power and Light's Turkey Point Nuclear Power Plant. This system was installed as part of an upgrade to the emergency power system in 1988. The experience gained in the design, development, implementation and qualification of these systems will be beneficial to utilities that are considering the utilization of PLCs for their plant applications

Safety considerations for various applications of remote multiplexing in nuclear power plants

International Nuclear Information System (INIS)

Leary, J.E.

1978-01-01

There is increasing interest in the application of remote multiplexing systems (RMS) for power plant applications. Remote multiplexing can replace the majority of conventional control and instrumentation signal cables. In addition, the RMS can perform control logic functions presently implemented by discrete hardwired circuit elements. The background and trends in the use of RMS and the attendant advantages and concerns are reviewed. Classifications of multiplexed digital systems are presented to show the evolution of this technology in power plant applications. Nuclear safety-related applications of RMS are discussed with emphasis on the impact of selected NRC Regulatory Guides on such applications. (author)

New reactor safety circuit for low-power-level operation

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

1978-01-01

In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

Digital integrated circuit design using Verilog and SystemVerilog

CERN Document Server

Mehler, Ronald W

2014-01-01

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

Concatenated logic circuits based on a three-way DNA junction: a keypad-lock security system with visible readout and an automatic reset function.

Science.gov (United States)

Chen, Junhua; Zhou, Shungui; Wen, Junlin

2015-01-07

Concatenated logic circuits operating as a biocomputing keypad-lock security system with an automatic reset function have been successfully constructed on the basis of toehold-mediated strand displacement and three-way-DNA-junction architecture. In comparison with previously reported keypad locks, the distinctive advantage of the proposed security system is that it can be reset and cycled spontaneously a large number of times without an external stimulus, thus making practical applications possible. By the use of a split-G-quadruplex DNAzyme as the signal reporter, the output of the keypad lock can be recognized readily by the naked eye. The "lock" is opened only when the inputs are introduced in an exact order. This requirement provides defense against illegal invasion to protect information at the molecular scale. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Loregic: A Method to Characterize the Cooperative Logic of Regulatory Factors

Science.gov (United States)

Wang, Daifeng; Yan, Koon-Kiu; Sisu, Cristina; Cheng, Chao; Rozowsky, Joel; Meyerson, William; Gerstein, Mark B.

2015-01-01

The topology of the gene-regulatory network has been extensively analyzed. Now, given the large amount of available functional genomic data, it is possible to go beyond this and systematically study regulatory circuits in terms of logic elements. To this end, we present Loregic, a computational method integrating gene expression and regulatory network data, to characterize the cooperativity of regulatory factors. Loregic uses all 16 possible two-input-one-output logic gates (e.g. AND or XOR) to describe triplets of two factors regulating a common target. We attempt to find the gate that best matches each triplet’s observed gene expression pattern across many conditions. We make Loregic available as a general-purpose tool (github.com/gersteinlab/loregic). We validate it with known yeast transcription-factor knockout experiments. Next, using human ENCODE ChIP-Seq and TCGA RNA-Seq data, we are able to demonstrate how Loregic characterizes complex circuits involving both proximally and distally regulating transcription factors (TFs) and also miRNAs. Furthermore, we show that MYC, a well-known oncogenic driving TF, can be modeled as acting independently from other TFs (e.g., using OR gates) but antagonistically with repressing miRNAs. Finally, we inter-relate Loregic’s gate logic with other aspects of regulation, such as indirect binding via protein-protein interactions, feed-forward loop motifs and global regulatory hierarchy. PMID:25884877

Research Tool to Evaluate the Safety Response of Lithium Batteries to an Internal Short Circuit

Energy Technology Data Exchange (ETDEWEB)

Keyser, Matthew; Darcy, Eric; Pesaran, Ahmad

2016-06-19

Li-ion cells provide the highest specific energy and energy density rechargeable battery with the longest life. Many safety incidents that take place in the field originate due to an internal short that was not detectable or predictable at the point of manufacture. NREL's internal short circuit (ISC) device is capable of simulating shorts and produces consistent and reproducible results. The cell behaves normally until the ISC device is activated wherein a latent defect (i.e., built into the cell during manufacturing) gradually moves into position to create an internal short while the battery is in use, providing relevant data to verify abuse models. The ISC device is an effective tool for studying the safety features of parts of Li-ion batteries.

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

Science.gov (United States)

Harper, Michael; Miller, Joseph; Shen, Yuzhong

2011-01-01

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology

International Nuclear Information System (INIS)

Zhao Hongquan; Kasai, Seiya; Shiratori, Yuta; Hashizume, Tamotsu

2009-01-01

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.

Synthesis and Analysis of a Quaternary Static RAM Using Quantizing Circuits

Science.gov (United States)

Syuto, Makoto; Magata, Hiroshi; Tanno, Koichi; Ishizuka, Okihiko

1999-09-01

In this paper, a voltage mode multiple valued static random access memory (MVSRAM) with a multiple valued quantizer is described. The proposed circuit has the merits of simplicity and low cost on fabrication, since it is implemented by standard CMOs process, instead of the conventional multi-level ion implantation usually applied in the voltage-mode multi-valued logic (MVL) circuit. The performance of the proposed MVSRAM is estimated by HSPICE simulations with MOSIS 2.0 microns CMOs process parameter.

Electronics circuits and systems

CERN Document Server

Bishop, Owen

2007-01-01

The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set

Electronics circuits and systems

CERN Document Server

Bishop, Owen

2011-01-01

The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea

Operating experiences with programmable logic controller (PLC) system of Indian Pressurised Heavy Water Reactors (PHWR)

International Nuclear Information System (INIS)

Ughade, A.V.; Singh, Ranjeet; Bhattacharya, P.K.; Kulkarni, R.K.; Chandra, Umesh

2005-01-01

PLC system was introduced for the first time in Kaiga-1,2 and RAPS-3,4 Nuclear Power Plants (NPPs) for Station Logic Control of Non Safety Related (NSR) and Safety related (SR) systems. However, the safety system logics are still relay based. The experience on the deployment of PLC system, which is computer-based, has brought out various implementation issues. This paper give details of such experiences, the solutions emerged and applied for plants under operation/construction. (author)

A deadtime reduction circuit for thermal neutron coincidence counters with Amptek preamplifiers

International Nuclear Information System (INIS)

Bourret, S.C.; Krick, M.S.

1994-01-01

We have developed a deadtime reduction circuit for thermal neutron coincidence counters using Amptek preamplifier/amplifier/discriminator circuits. The principle is to remove the overlap between the output pulses from the Amptek circuits by adding a derandomizer between the Amptek circuits and the shift-register coincidence electronics. We implemented the derandomizer as an Actel programmable logic array; the derandomizer board is small and can be mounted in the high-voltage junction box with the Amptek circuits, if desired. Up to 32 Amptek circuits can be used with one derandomizer. The derandomizer has seven outputs: four groups of eight inputs, two groups of 16 inputs, and one group of 32 inputs. We selected these groupings to facilitate detector ring-ratio measurements. The circuit was tested with the five-ring research multiplicity counter, which has five output signals-one for each ring. The counter's deadtime was reduced from 70 to 30 ns

Mathematical logic as a mean of solving the problems of power supply for buildings and constructions

Science.gov (United States)

Pryadko, Igor; Nozdrina, Ekaterina; Boltaevsky, Andrey

2017-10-01

The article analyzes the questions of application of mathematical logic in engineering design associated with machinery and construction. The aim of the work is to study the logical working-out of Russian electrical engineer V.I. Shestakov. These elaborations are considered in connection with the problem of analysis and synthesis of relay contact circuits of the degenerate (A) class which the scientist solved. The article proposes to use Shestakov’s elaborations for optimization of buildings and constructions of modern high-tech. In the second part of the article the events are actualized in association with the development of problems of application of mathematical logic in the analysis and synthesis of electric circuits, relay and bridging. The arguments in favor of the priority of the authorship of the elaborations of Russian electrical engineer V. I. Shestakov, K. Shannon - one of the founders of computer science, and Japanese engineer A. Nakashima are discussed. The issue of contradiction between V. I. Shestakov and representatives of the school of M. A. Gavrilov is touched on.

A fuzzy logic pitch angle controller for power system stabilization

Energy Technology Data Exchange (ETDEWEB)

Jauch, Clemens; Cronin, Tom; Sorensen, Poul [Wind Energy Department, Riso National Laboratory, PO Box 49, DK-4000 Roskilde, (Denmark); Jensen, Birgitte Bak [Institute of Energy Technology, Aalborg University, Pontoppidanstraede 101, DK-9220 Aalborg East, (Denmark)

2006-07-12

In this article the design of a fuzzy logic pitch angle controller for a fixed speed, active-stall wind turbine, which is used for power system stabilization, is presented. The system to be controlled, which is the wind turbine and the power system to which the turbine is connected, is described. The advantages of fuzzy logic control when applied to large-signal control of active-stall wind turbines are outlined. The general steps of the design process for a fuzzy logic controller, including definition of the controller inputs, set-up of the fuzzy rules and the method of defuzzification, are described. The performance of the controller is assessed by simulation, where the wind turbine's task is to dampen power system oscillations. In the scenario simulated for this work, the wind turbine has to ride through a transient short-circuit fault and subsequently contribute to the damping of the grid frequency oscillations that are caused by the transient fault. It is concluded that the fuzzy logic controller enables the wind turbine to dampen power system oscillations. It is also concluded that, owing to the inherent non-linearities in a wind turbine and the unpredictability of the whole system, the fuzzy logic controller is very suitable for this application. (Author).

A new high-voltage level-shifting circuit for half-bridge power ICs

International Nuclear Information System (INIS)

Kong Moufu; Chen Xingbi

2013-01-01

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well. (semiconductor integrated circuits)

Function of One Regular Separable Relation Set Decided for the Minimal Covering in Multiple Valued Logic

Directory of Open Access Journals (Sweden)

Liu Yu Zhen

2016-01-01

Full Text Available Multiple-valued logic is an important branch of the computer science and technology. Multiple-valued logic studies the theory, multiple-valued circuit & multiple-valued system, and the applications of multiple-valued logic included.In the theory of multiple-valued logic, one primary and important problem is the completeness of function sets, which can be solved depending on the decision for all the precomplete sets(also called maximal closed sets of K-valued function sets noted by PK*, and another is the decision for Sheffer function, which can be totally solved by picking out all of the minimal covering of the precomplete sets. In the function structure theory of multi-logic, decision on Sheffer function is an important role. It contains structure and decision of full multi-logic and partial multi-logic. Its decision is closely related to decision of completeness of function which can be done by deciding the minimal covering of full multi-logic and partial-logic. By theory of completeness of partial multi-logic, we prove that function of one regular separable relation is not minimal covering of PK* under the condition of m = 2, σ = e.

High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology

DEFF Research Database (Denmark)

Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid

This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared...... with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention...

Computer controlled motor vehicle battery circuit

Energy Technology Data Exchange (ETDEWEB)

Krueger, W.R.; McAuiliffe, G.N.; Schlageter, G.A.

1986-04-01

This patent consists of a motor vehicle having a DC motor, a pedal biased to a released position and depressed by the driver to increase speed. An alternate switching means affects the vehicle speed control, a foot switch is operated by the pedal and operative when the pedal is depressed to close a circuit enabling energization of the alternate switching means. A microprocessor includes a program for controlling operation of the alternate switching means, the foot switch is operative when the pedal is released to open the enabling circuit. The program includes a register which is incremented with each passage of the logic and is responsive to the incremented count in the register to instruct a change in position of the alternate switching means.

Microcontroller based Integrated Circuit Tester

OpenAIRE

Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

2015-01-01

The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

A study of switch circuits for use as safety devices in nuclear reactors; Etude de circuits de commutation destines a la securite des reacteurs nucleaires

Energy Technology Data Exchange (ETDEWEB)

Hantcherian, V [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1960-12-15

The author reviews briefly a few basic assemblies using electromagnetic relays for safety circuits in nuclear reactors; he then studies the use of static relays with a shorter time of response, based on impedance changes in a self-inductance consisting of a coil with a magnetic core having a rectangular hysteresis cycle. The author examines in particular the way in which it functions and the method of determining the parameters. (author) [French] L'auteur apres avoir examine sommairement en revue quelques montages de base des circuits de securite des reacteurs nucleaires utilisant des relais electromecaniques, etudie l'emploi des relais statiques a plus grande vitesse de reponse bases sur la variation d'impedance que presente une self-inductance realisee a l'aide d'une bobine enroulee autour d'un noyau magnetique a cycle d'hysteresis rectangulaire. En particulier, il en examine le mode de fonctionnement et la determination des parametres. (auteur)

Logic-based hierarchies for modeling behavior of complex dynamic systems with applications

International Nuclear Information System (INIS)

Hu, Y.S.; Modarres, M.

2000-01-01

Most complex systems are best represented in the form of a hierarchy. The Goal Tree Success Tree and Master Logic Diagram (GTST-MLD) are proven powerful hierarchic methods to represent complex snap-shot of plant knowledge. To represent dynamic behaviors of complex systems, fuzzy logic is applied to replace binary logic to extend the power of GTST-MLD. Such a fuzzy-logic-based hierarchy is called Dynamic Master Logic Diagram (DMLD). This chapter discusses comparison of the use of GTST-DMLD when applied as a modeling tool for systems whose relationships are modeled by either physical, binary logical or fuzzy logical relationships. This is shown by applying GTST-DMLD to the Direct Containment Heating (DCH) phenomenon at pressurized water reactors which is an important safety issue being addressed by the nuclear industry. (orig.)

Fuzzy Logic Controlled Solar Module for Driving Three- Phase Induction Motor

Science.gov (United States)

Afiqah Zainal, Nurul; Sooi Tat, Chan; Ajisman

2016-02-01

Renewable energy produced by solar module gives advantages for generated three- phase induction motor in remote area. But, solar module's ou tput is uncertain and complex. Fuzzy logic controller is one of controllers that can handle non-linear system and maximum power of solar module. Fuzzy logic controller used for Maximum Power Point Tracking (MPPT) technique to control Pulse-Width Modulation (PWM) for switching power electronics circuit. DC-DC boost converter used to boost up photovoltaic voltage to desired output and supply voltage source inverter which controlled by three-phase PWM generated by microcontroller. IGBT switched Voltage source inverter (VSI) produced alternating current (AC) voltage from direct current (DC) source to control speed of three-phase induction motor from boost converter output. Results showed that, the output power of solar module is optimized and controlled by using fuzzy logic controller. Besides that, the three-phase induction motor can be drive and control using VSI switching by the PWM signal generated by the fuzzy logic controller. This concluded that the non-linear system can be controlled and used in driving three-phase induction motor.

Tyramine Hydrochloride Based Label-Free System for Operating Various DNA Logic Gates and a DNA Caliper for Base Number Measurements.

Science.gov (United States)

Fan, Daoqing; Zhu, Xiaoqing; Dong, Shaojun; Wang, Erkang

2017-07-05