Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool
2017-12-01
Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.
Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Generating and checking control logic in the HDL-based design of reversible circuits
DEFF Research Database (Denmark)
Wille, Robert; Keszocze, Oliver; Othmer, Lars
2017-01-01
the required fi-conditions and check whether a reversible control flow indeed can be realized. The solution utilizes predicate transformer semantics based on Hoare logic. This has exemplary been implemented for the reversible HDL SyReC and evaluated with a variety of circuit description examples. The proposed......Although different from the conventional computing paradigm, reversible computation received significant interest due to its applications in various (emerging) technologies. Here, computations can be executed not only from the inputs to the outputs, but also in the reverse direction. This leads......, be provided with an additional fi-condition for backward computation. Unfortunately, deriving correct and consistent fi-conditions is often not obvious. Moreover, HDL descriptions exist which may not be realized with a reversible control flow at all. In this work, we propose automatic solutions which generate...
Bergstra, J.A.; Ponse, A.
2010-01-01
Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of
Reversible logic gates on Physarum Polycephalum
Energy Technology Data Exchange (ETDEWEB)
Schumann, Andrew [University of Information Technology and Management, Sucharskiego 2, Rzeszow, 35-225 (Poland)
2015-03-10
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.
A functional language for describing reversible logic
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal
2012-01-01
Reversible logic is a computational model where all gates are logically reversible and combined in circuits such that no values are lost or duplicated. This paper presents a novel functional language that is designed to describe only reversible logic circuits. The language includes high....... Reversibility of descriptions is guaranteed with a type system based on linear types. The language is applied to three examples of reversible computations (ALU, linear cosine transformation, and binary adder). The paper also outlines a design flow that ensures garbage- free translation to reversible logic...
Reversible gates and circuits descriptions
Gracki, Krzystof
2017-08-01
This paper presents basic methods of reversible circuit description. To design reversible circuit a set of gates has to be chosen. Most popular libraries are composed of three types of gates so called CNT gates (Control, NOT and Toffoli). The gate indexing method presented in this paper is based on the CNT gates set. It introduces a uniform indexing of the gates used during synthesis process of reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 and 3 a graphical representation of the reversible gates and circuits is described. Section 4 describes proposed uniform NCT gates indexing. The presented gate indexing method provides gate numbering scheme independent of lines number of the designed circuit. The solution for a circuit consisting of smaller number of lines is a subset of solution for a larger circuit.
Optically controllable molecular logic circuits
Energy Technology Data Exchange (ETDEWEB)
Nishimura, Takahiro, E-mail: t-nishimura@ist.osaka-u.ac.jp; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun [Graduate School of Information Science and Technology, Osaka University, 1-5 Yamadaoka, Suita, Osaka 565-0871 (Japan)
2015-07-06
Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.
A parity checker circuit based on microelectromechanical resonator logic elements
Energy Technology Data Exchange (ETDEWEB)
Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)
2017-03-03
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.
A parity checker circuit based on microelectromechanical resonator logic elements
Hafiz, Md Abdullah Al
2017-01-11
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
Designing Novel Quaternary Quantum Reversible Subtractor Circuits
Haghparast, Majid; Monfared, Asma Taheri
2018-01-01
Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.
Designing Novel Quaternary Quantum Reversible Subtractor Circuits
Haghparast, Majid; Monfared, Asma Taheri
2017-10-01
Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.
Reversible logic synthesis methodologies with application to quantum computing
Taha, Saleem Mohammed Ridha
2016-01-01
This book opens the door to a new interesting and ambitious world of reversible and quantum computing research. It presents the state of the art required to travel around that world safely. Top world universities, companies and government institutions are in a race of developing new methodologies, algorithms and circuits on reversible logic, quantum logic, reversible and quantum computing and nano-technologies. In this book, twelve reversible logic synthesis methodologies are presented for the first time in a single literature with some new proposals. Also, the sequential reversible logic circuitries are discussed for the first time in a book. Reversible logic plays an important role in quantum computing. Any progress in the domain of reversible logic can be directly applied to quantum logic. One of the goals of this book is to show the application of reversible logic in quantum computing. A new implementation of wavelet and multiwavelet transforms using quantum computing is performed for this purpose. Rese...
Ancilla-free Reversible Logic Synthesis via Sorting
Chattopadhyay, Anupam; Hossain, Sharif Md Khairul
2016-01-01
Reversible logic synthesis is emerging as a major research component for post-CMOS computing devices, in particular Quantum computing. In this work, we link the reversible logic synthesis problem to sorting algorithms. Based on our analysis, an alternative derivation of the worst-case complexity of generated reversible circuits is provided. Furthermore, a novel column-wise reversible logic synthesis method, termed RevCol, is designed with inspiration from radix sort. Extending the principles ...
Reversible logic gate using adiabatic superconducting devices
National Research Council Canada - National Science Library
Takeuchi, N; Yamanashi, Y; Yoshikawa, N
2014-01-01
.... However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices...
Heuristic Synthesis of Reversible Logic – A Comparative Study
Directory of Open Access Journals (Sweden)
Chua Shin Cheng
2014-01-01
Full Text Available Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based. All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.
Reversible logic gate using adiabatic superconducting devices.
Takeuchi, N; Yamanashi, Y; Yoshikawa, N
2014-09-15
Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage.
New Logic Circuit with DC Parametric Excitation
Sugahara, Masanori; Kaneda, Hisayoshi
1982-12-01
It is shown that dc parametric excitation is possible in a circuit named JUDO, which is composed of two resistively-connected Josephson junctions. Simulation study proves that the circuit has large gain and properties suitable for the construction of small, high-speed logic circuits.
Reversible logic gate using adiabatic superconducting devices
Takeuchi, N.; Y. Yamanashi; Yoshikawa, N.
2014-01-01
Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic...
Magnetic Logic Circuits for Extreme Environments Project
National Aeronautics and Space Administration — The program aims to demonstrate a new genre of all-magnetic logic circuits which are radiation-tolerant and capable of reliable operation in extreme environmental...
Optimized 4-bit Quantum Reversible Arithmetic Logic Unit
Ayyoub, Slimani; Achour, Benslama
2017-08-01
Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.
Describing and optimizing reversible logic using a functional language
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal
2012-01-01
This paper presents the design of a language for the description and optimisation of reversible logic circuits. The language is a combinator-style functional language designed to be close to the reversible logical gate-level. The combinators include high-level constructs such as ripples, but also...... the description of arbitrary sized circuits. The combination of the functional language and the restricted reversible model results in many arithmetic laws, which provide more possibilities for term rewriting and, thus, the opportunity for good optimisation....... the recognisable inversion combinator f^(-1), which defines the inverse function of f using an efficient semantics. It is important to ensure that all circuits descriptions are reversible, and furthermore we must require this to be done statically. This is en- sured by the type system, which also allows...
Experimental Device for Learning of Logical Circuit Design using Integrated Circuits
石橋, 孝昭
2012-01-01
This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.
An introduction to logic circuit testing
Lala, Parag K
2008-01-01
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)
Nanoeletromechanical switch and logic circuits formed therefrom
Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM
2010-05-18
A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
Explicit logic circuits discriminate neural states.
Directory of Open Access Journals (Sweden)
Lane Yoder
Full Text Available The magnitude and apparent complexity of the brain's connectivity have left explicit networks largely unexplored. As a result, the relationship between the organization of synaptic connections and how the brain processes information is poorly understood. A recently proposed retinal network that produces neural correlates of color vision is refined and extended here to a family of general logic circuits. For any combination of high and low activity in any set of neurons, one of the logic circuits can receive input from the neurons and activate a single output neuron whenever the input neurons have the given activity state. The strength of the output neuron's response is a measure of the difference between the smallest of the high inputs and the largest of the low inputs. The networks generate correlates of known psychophysical phenomena. These results follow directly from the most cost-effective architectures for specific logic circuits and the minimal cellular capabilities of excitation and inhibition. The networks function dynamically, making their operation consistent with the speed of most brain functions. The networks show that well-known psychophysical phenomena do not require extraordinarily complex brain structures, and that a single network architecture can produce apparently disparate phenomena in different sensory systems.
Basics of Verilog HDL and design of digital logic circuit
Energy Technology Data Exchange (ETDEWEB)
Beck, Ju Gi
2008-03-15
This book explains of the basic of Verilog HDL and design of digital logic circuit with ALTERA Quartus II and MAX + PLUS II. It comprised four charters, which include four chapters, introduction of ASIC, ALTERA design software and introduction, basic of Verilog HDL and making of download cable like parallel download, MAX 7000s device and FPGA circuit constitution and test, design of digital logic circuit with basic of Verilog HDL, design of combination logic circuit and order logic circuit, application circuit design such as 7 segment LED display design, LCD display device design and digital clocks.
Reversible arithmetic logic unit for quantum arithmetic
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal; Glück, Robert; Axelsen, Holger Bock
2010-01-01
and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n...
Simulation Approach for Timing Analysis of Genetic Logic Circuits
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
2017-01-01
in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior...... of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits......Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work...
On Multiplicative Linear Logic, Modality and Quantum Circuits
Directory of Open Access Journals (Sweden)
Ugo Dal Lago
2012-10-01
Full Text Available A logical system derived from linear logic and called QMLL is introduced and shown able to capture all unitary quantum circuits. Conversely, any proof is shown to compute, through a concrete GoI interpretation, some quantum circuits. The system QMLL, which enjoys cut-elimination, is obtained by endowing multiplicative linear logic with a quantum modality.
Simulation Approach for Timing Analysis of Genetic Logic Circuits
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
2017-01-01
in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior...... of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits...
Reversible Logic Elements with Memory and Their Universality
Directory of Open Access Journals (Sweden)
Kenichi Morita
2013-09-01
Full Text Available Reversible computing is a paradigm of computation that reflects physical reversibility, one of the fundamental microscopic laws of Nature. In this survey, we discuss topics on reversible logic elements with memory (RLEM, which can be used to build reversible computing systems, and their universality. An RLEM is called universal, if any reversible sequential machine (RSM can be realized as a circuit composed only of it. Since a finite-state control and a tape cell of a reversible Turing machine (RTM are formalized as RSMs, any RTM can be constructed from a universal RLEM. Here, we investigate 2-state RLEMs, and show that infinitely many kinds of non-degenerate RLEMs are all universal besides only four exceptions. Non-universality of these exceptional RLEMs is also argued.
Logic analysis and verification of n-input genetic logic circuits
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
2017-01-01
accordingly. As compared to electronic circuits, genetic circuits exhibit stochastic behavior and do not always behave as intended. Therefore, there is a growing interest in being able to analyze and verify the logical behavior of a genetic circuit model, prior to its physical implementation in a laboratory....... In this paper, we present an approach to analyze and verify the Boolean logic of a genetic circuit from the data obtained through stochastic analog circuit simulations. The usefulness of this analysis is demonstrated through different case studies illustrating how our approach can be used to verify the expected...... behavior of an n-input genetic logic circuit....
Circuit Simulation of All-Spin Logic
Alawein, Meshal
2016-05-01
With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall
Reversible Squaring Circuit for Low Power Digital Signal Processing
Directory of Open Access Journals (Sweden)
Pradeep Singla
2014-06-01
Full Text Available With the high demand of low power digital systems, energy dissipation in the digital system is one of the limiting factors. Reversible logic is one of the alternate to reduce heat/energy dissipation in the digital circuits and have a very significant importance in bioinformatics, optical information processing, CMOS design etc. In this paper the authors propose the design of new 2- bit binary Squaring circuit used in most of the digital signal processing hardware using Feynman & MUX gate. The proposed squaring circuit having less garbage outputs, constant inputs, Quantum cost and Total logical calculation i.e. less delay as compared to the traditional method of squaring operation by reversible multiplier. The simulating results and quantized results are also shown in the paper which shows the greatest improvement in the design against the previous methodology.
Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors
Yoo, H.; Ghittorelli, M.; Smits, E.C.P.; Gelinck, G.H.; Lee, H.K.; Torricelli, F.; Kim, J.J.
2016-01-01
Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they
MOS Current Mode Logic Near Threshold Circuits
Directory of Open Access Journals (Sweden)
Alexander Shapiro
2014-06-01
Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.
A reversible processor architecture and its reversible logic design
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal; Axelsen, Holger Bock; Glück, Robert
2012-01-01
an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language. All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable......We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed...
Timing Analysis of Genetic Logic Circuits using D-VASim
DEFF Research Database (Denmark)
Baig, Hasan; Madsen, Jan
delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing......A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to controlgene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electroniclogic circuits, timing and propagation...... and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...
Study of Reversible Logic Synthesis with Application in SOC: A Review
Sharma, Chinmay; Pahuja, Hitesh; Dadhwal, Mandeep; Singh, Balwinder
2017-08-01
The prime concern in today’s SOC designs is the power dissipation which increases with technology scaling. The reversible logic possesses very high potential in reducing power dissipation in these designs. It finds its application in latest research fields such as DNA computing, quantum computing, ultra-low power CMOS design and nanotechnology. The reversible circuits can be easily designed using the conventional CMOS technology at a cost of a garbage output which maintains the reversibility. The purpose of this paper is to provide an overview of the developments that have occurred till date in this concept and how the new reversible logic gates are used to design the logic functions.
Digital circuits using universal logic gates
Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)
2004-01-01
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin
2016-06-22
In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.
A simple circuit with dynamic logic architecture of basic logic gates
Campos-Canton, I.; Pecina-Sanchez, J. A.; Campos-Canton, E.; Rosu, H. C.
2010-01-01
We report experimental results obtained with a circuit possessing dynamic logic architecture based on one of the theoretical schemes proposed by H. Peng and collaborators in 2008. The schematic diagram of the electronic circuit and its implementation to get different basic logic gates are displayed and discussed. In particular, we show explicitly how to get the electronic NOR, NAND, and XOR gates. The proposed electronic circuit is easy to build because it employs only resistors, operational ...
Synthesizing genetic sequential logic circuit with clock pulse generator
National Research Council Canada - National Science Library
Chuang, Chia-Hua; Lin, Chun-Liang
2014-01-01
.... This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse...
A method of reversible circuits synthesis based on s-maps
Skorupski, Andrzej
2017-08-01
This paper presents an original method to designing reversible circuits. The main problem of reversible circuits synthesis is designing optimal reversible circuits i.e. circuits with minimal gates number implementing the given reversible function. To design reversible circuits a set of gates must be chosen. The most popular library is a set called CNT (Control, NOT and Toffoli) which contains three types of gates. The method presented in this paper is based on the CNT gates. A graphical representation of the reversible function called s-maps is introduced in the paper. This representation allows to find optimal solutions. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 a graphical representation of the reversible functions is presented. Section 3 describes the algorithm whereby any optimal solutions of the given function could be obtained.
National Research Council Canada - National Science Library
Yonghui Tian; Zilong Liu; Tonghe Ying; Huifu Xiao; Yinghao Meng; Lin Deng; Yongpeng Zhao; Anqi Guo; Miaomiao Liao; Guipeng Liu; Jianhong Yang
2018-01-01
Currently, the reversible logic circuit is a popular research topic in the field of information processing as it is a most effective approach to minimize power consumption, which can achieve the one...
Fast frequency divider circuit using combinational logic
Helinski, Ryan
2017-05-30
The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.
Kumar, Santosh; Chauhan, Chanderkanta; Bedi, Amna
2016-12-01
In recent years, it has been shown that reversible logic can play an important role in power optimization for computer design. The various reversible logic gates such as Feynman, Fredkin, Peres, and Toffoli gates have been discussed by researchers, but very little work has been done on reversible sequential circuits. Design of reversible sequential circuits using lithium-niobate-based Mach-Zehnder interferometers is proposed. Here, flip-flops are designed with the help of basic reversible logic gates such as Feynman, Fredkin, and Peres gates. Theoretical descriptions along with mathematical formulation of the devices are provided. The devices are also analyzed through finite difference-beam propagation method and MATLAB® simulation.
Reversible circuit synthesis by genetic programming using dynamic gate libraries
Abubakar, Mustapha Y.; Jung, Low Tang; Zakaria, Nordin; Younes, Ahmed; Abdel-Aty, Abdel-Haleem
2017-06-01
We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.
Timing-driven logic restructuring for nano-hybrid circuits
Chu, Zhufei; Xia, Yinshui; Hung, William N. N.; Song, Xiaoyu; Wang, Lunyao
2013-05-01
As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.
Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata.
Bahar, Ali Newaz; Rahman, Mohammad Maksudur; Nahid, Nur Mohammad; Hassan, Md Kamrul
2017-02-01
This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T=2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.
Reversible and quantum circuits optimization and complexity analysis
Abdessaied, Nabila
2016-01-01
This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.
Practical design of digital circuits basic logic to microprocessors
Kampel, Ian
1983-01-01
Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio
Logic designer's handbook circuits and systems
Parr, E A
2013-01-01
Easy-to-read, but nonetheless thorough, this book on digital circuits is for use by students and engineers, and is a readily accessible source of data on devices in the TTL and CMOS families. The book is written to be used as a Designer's Handbook and will spend its days on the designer's bench rather than their bookshelf. The basic theory is explained and then supported with specific practical examples.* Revised, enlarged, reduced price edition * Easy-to-read, jargon free book suitable for professionals and students * Plenty of basic theory and practical information * Based on authors practi
Reversibility and energy dissipation in adiabatic superconductor logic.
Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki
2017-03-06
Reversible computing is considered to be a key technology to achieve an extremely high energy efficiency in future computers. In this study, we investigated the relationship between reversibility and energy dissipation in adiabatic superconductor logic. We analyzed the evolution of phase differences of Josephson junctions in the reversible quantum-flux-parametron (RQFP) gate and confirmed that the phase differences can change time reversibly, which indicates that the RQFP gate is physically, as well as logically, reversible. We calculated energy dissipation required for the RQFP gate to perform a logic operation and numerically demonstrated that the energy dissipation can fall below the thermal limit, or the Landauer bound, by lowering operation frequencies. We also investigated the 1-bit-erasure gate as a logically irreversible gate and the quasi-RQFP gate as a physically irreversible gate. We calculated the energy dissipation of these irreversible gates and showed that the energy dissipation of these gate is dominated by non-adiabatic state changes, which are induced by unwanted interactions between gates due to logical or physical irreversibility. Our results show that, in reversible computing using adiabatic superconductor logic, logical and physical reversibility are required to achieve energy dissipation smaller than the Landauer bound without non-adiabatic processes caused by gate interactions.
Magnonic interferometric switch for multi-valued logic circuits
Balynsky, Michael; Kozhevnikov, Alexander; Khivintsev, Yuri; Bhowmick, Tonmoy; Gutierrez, David; Chiang, Howard; Dudko, Galina; Filimonov, Yuri; Liu, Guanxiong; Jiang, Chenglong; Balandin, Alexander A.; Lake, Roger; Khitun, Alexander
2017-01-01
We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-scale logic gates, and minimize energy per operation, which is limited only by the noise margin. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. We describe possible implementation of the three-value logic circuits based on the magnonic interferometric switches. The advantages and shortcomings inherent in interferometric switches are also discussed.
On Design of Parity Preserving Reversible Adder Circuits
Haghparast, Majid; Bolhassani, Ali
2016-12-01
In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.
Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits
Directory of Open Access Journals (Sweden)
Manoj Sharma
2015-01-01
Full Text Available Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, Cload, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff Cload 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.
Logic Synthesis of Recombinase-Based Genetic Circuits.
Chiu, Tai-Yin; Jiang, Jie-Hong R
2017-10-09
A synthetic approach to biology is a promising technique for various applications. Recent advancements have demonstrated the feasibility of constructing synthetic two-input logic gates in Escherichia coli cells with long-term memory based on DNA inversion induced by recombinases. Moreover, recent evidences indicate that DNA inversion mediated by genome editing tools is possible. Powerful genome editing technologies, such as CRISPR-Cas9 systems, have great potential to be exploited to implement large-scale recombinase-based circuits. What remains unclear is how to construct arbitrary Boolean functions based on these emerging technologies. In this paper, we lay the theoretical foundation formalizing the connection between recombinase-based genetic circuits and Boolean functions. It enables systematic construction of any given Boolean function using recombinase-based logic gates. We further develop a methodology leveraging existing electronic design automation (EDA) tools to automate the synthesis of complex recombinase-based genetic circuits with respect to area and delay optimization. In silico experimental results demonstrate the applicability of our proposed methods as a useful tool for recombinase-based genetic circuit synthesis and optimization.
Thomas, R.; Kaufman, M.
2001-03-01
(in the case of a negative circuit). The last sections deal with "more about time delays" and "reverse logic," an approach that aims to proceed rationally from facts to models.
Tian, Yonghui; Liu, Zilong; Ying, Tonghe; Xiao, Huifu; Meng, Yinghao; Deng, Lin; Zhao, Yongpeng; Guo, Anqi; Liao, Miaomiao; Liu, Guipeng; Yang, Jianhong
2018-01-01
Currently, the reversible logic circuit is a popular research topic in the field of information processing as it is a most effective approach to minimize power consumption, which can achieve the one-to-one mapping function to identify the input signals from its corresponding output signals. In this letter, we propose and experimentally demonstrate an optical Feynman gate for reversible logic operation using silicon micro-ring resonators (MRRs). Two electrical input signals (logic operands) are applied across the micro-heaters above MRRs to determine the switching states of MRRs, and the reversible logic operation results are directed to the output ports in the form of light, respectively. For proof of concept, the thermo-optic modulation scheme is used to achieve MRR's optical switching function. At last, a Feynman gate for reversible logic operation with the speed of 10 kbps is demonstrated successfully.
Directory of Open Access Journals (Sweden)
Tian Yonghui
2018-01-01
Full Text Available Currently, the reversible logic circuit is a popular research topic in the field of information processing as it is a most effective approach to minimize power consumption, which can achieve the one-to-one mapping function to identify the input signals from its corresponding output signals. In this letter, we propose and experimentally demonstrate an optical Feynman gate for reversible logic operation using silicon micro-ring resonators (MRRs. Two electrical input signals (logic operands are applied across the micro-heaters above MRRs to determine the switching states of MRRs, and the reversible logic operation results are directed to the output ports in the form of light, respectively. For proof of concept, the thermo-optic modulation scheme is used to achieve MRR’s optical switching function. At last, a Feynman gate for reversible logic operation with the speed of 10 kbps is demonstrated successfully.
Reverse engineering the lordosis behavior circuit.
Pfaff, D W; Kow, L-M; Loose, M D; Flanagan-Cato, L M
2008-08-01
Reverse engineering takes the facts we know about a device or a process and reasons backwards to infer the principles underlying the structure-function relations. The goal of this review is to apply this approach to a well-studied hormone-controlled behavior, namely the reproductive stance of female rodents, lordosis. We first provide a brief overview on the considerable amount of progress in the analysis of female reproductive behavior. Then, we propose an analysis of the mechanisms of this behavior from a reverse-engineering perspective with the goal of generating novel hypotheses about the properties of the circuitry elements. In particular, the previously proposed neuronal circuit modules, feedback signals, and genomic mechanisms are considered to make predictions in this manner. The lordosis behavior itself appears to proceed ballistically once initiated, but negative and positive hormonal feedback relations are evident in its endocrine controls. Both rapid membrane-initiated and slow genomic hormone effects contribute to the behavior's control. We propose that the value of the reverse-engineering approach is based on its ability to provide testable, mechanistic hypotheses that do not emerge from either traditional evolutionary or simple reductionistic perspectives, and several are proposed in this review. These novel hypotheses may generalize to brain functions beyond female reproductive behavior. In this way, the reverse-engineering perspective can further develop our conceptual frameworks for behavioral and systems neuroscience.
Complex logic functions implemented with quantum dot bionanophotonic circuits.
Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L
2014-03-26
We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.
Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata
Directory of Open Access Journals (Sweden)
Ali Newaz Bahar
2017-02-01
Full Text Available This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T=2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.
Reverse Engineering Integrated Circuits Using Finite State Machine Analysis
Energy Technology Data Exchange (ETDEWEB)
Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
2016-04-12
In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.
Design automation for integrated nonlinear logic circuits (Conference Presentation)
Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.
2016-05-01
A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite
Adaptive logic circuits with doping-free ambipolar carbon nanotube transistors.
Yu, Woo Jong; Kim, Un Jeong; Kang, Bo Ram; Lee, Il Ha; Lee, Eun-Hong; Lee, Young Hee
2009-04-01
A CMOS-like inverter was integrated by using ambipolar carbon nanotube (CNT) transistors without doping. The ambipolar CNT transistors automatically configure themselves to play a role as an n-type or p-type transistor in a logic circuit depending on the supply voltage (V(DD)) and ground. A NOR (NAND) gate is adaptively converted to a NAND (NOR) gate. This adaptiveness of logic gates exhibiting two logic gate functions in a single logic circuit offers a new opportunity for designing logic circuits with high integration density for next generation applications.
Performance Limits of Nanoelectromechanical Switches (NEMS-Based Adiabatic Logic Circuits
Directory of Open Access Journals (Sweden)
Samer Houri
2013-12-01
Full Text Available This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order model (ROM of the switch; the results given by this simplified model are compared to classical CMOS-based, and sub-threshold CMOS-based adiabatic logic circuits. NEMS-based circuits and CMOS-based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency.
Sheriff, Bonnie A; Wang, Dunwei; Heath, James R; Kurtin, Juanita N
2008-09-23
Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.
Three-input majority logic gate and multiple input logic circuit based on DNA strand displacement.
Li, Wei; Yang, Yang; Yan, Hao; Liu, Yan
2013-06-12
In biomolecular programming, the properties of biomolecules such as proteins and nucleic acids are harnessed for computational purposes. The field has gained considerable attention due to the possibility of exploiting the massive parallelism that is inherent in natural systems to solve computational problems. DNA has already been used to build complex molecular circuits, where the basic building blocks are logic gates that produce single outputs from one or more logical inputs. We designed and experimentally realized a three-input majority gate based on DNA strand displacement. One of the key features of a three-input majority gate is that the three inputs have equal priority, and the output will be true if any of the two inputs are true. Our design consists of a central, circular DNA strand with three unique domains between which are identical joint sequences. Before inputs are introduced to the system, each domain and half of each joint is protected by one complementary ssDNA that displays a toehold for subsequent displacement by the corresponding input. With this design the relationship between any two domains is analogous to the relationship between inputs in a majority gate. Displacing two or more of the protection strands will expose at least one complete joint and return a true output; displacing none or only one of the protection strands will not expose a complete joint and will return a false output. Further, we designed and realized a complex five-input logic gate based on the majority gate described here. By controlling two of the five inputs the complex gate can realize every combination of OR and AND gates of the other three inputs.
Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.
LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J
2014-06-02
We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Directory of Open Access Journals (Sweden)
Omnia S. Fadl
2016-01-01
Full Text Available Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model.
Fadl, Omnia S; Abu-Elyazeed, Mohamed F; Abdelhalim, Mohamed B; Amer, Hassanein H; Madian, Ahmed H
2016-01-01
Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes' toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
Explicit logic circuits predict local properties of the neocortex's physiology and anatomy.
Directory of Open Access Journals (Sweden)
Lane Yoder
Full Text Available BACKGROUND: Two previous articles proposed an explicit model of how the brain processes information by its organization of synaptic connections. The family of logic circuits was shown to generate neural correlates of complex psychophysical phenomena in different sensory systems. METHODOLOGY/PRINCIPAL FINDINGS: Here it is shown that the most cost-effective architectures for these networks produce correlates of electrophysiological brain phenomena and predict major aspects of the anatomical structure and physiological organization of the neocortex. The logic circuits are markedly efficient in several respects and provide the foundation for all of the brain's combinational processing of information. CONCLUSIONS/SIGNIFICANCE: At the local level, these networks account for much of the physical structure of the neocortex as well its organization of synaptic connections. Electronic implementations of the logic circuits may be more efficient than current electronic logic arrays in generating both Boolean and fuzzy logic.
Explicit Logic Circuits Predict Local Properties of the Neocortex's Physiology and Anatomy
Yoder, Lane
2010-01-01
Background Two previous articles proposed an explicit model of how the brain processes information by its organization of synaptic connections. The family of logic circuits was shown to generate neural correlates of complex psychophysical phenomena in different sensory systems. Methodology/Principal Findings Here it is shown that the most cost-effective architectures for these networks produce correlates of electrophysiological brain phenomena and predict major aspects of the anatomical structure and physiological organization of the neocortex. The logic circuits are markedly efficient in several respects and provide the foundation for all of the brain's combinational processing of information. Conclusions/Significance At the local level, these networks account for much of the physical structure of the neocortex as well its organization of synaptic connections. Electronic implementations of the logic circuits may be more efficient than current electronic logic arrays in generating both Boolean and fuzzy logic. PMID:20169077
DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS
2017-10-01
DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS UNIVERSITY OF SOUTHERN CALIFORNIA OCTOBER 2017 FINAL...Directorate This report is published in the interest of scientific and technical information exchange, and its publication does not constitute the...SUBTITLE DESIGN METHODOLOGIES AND TOOLS FOR SINGLE-FLUX QUANTUM LOGIC CIRCUITS 5a. CONTRACT NUMBER FA8750-15-C-0203 5b. GRANT NUMBER N/A 5c. PROGRAM
Sakui, Koji; Endoh, Tetsuo
2010-11-01
The asymmetric characteristics of the conventional vertical MOSFET are examined. To reduce the IR drop influences of the diffusion resistance for the vertical MOSFET, a new vertical MOSFET for the Vertical Logic Circuit (VLC) configuration, which separates the current paths of small currents from large currents, has been proposed.
Methods and Tools for the Analysis, Verification and Synthesis of Genetic Logic Circuits,
DEFF Research Database (Denmark)
Baig, Hasan
2017-01-01
Synthetic biology has emerged as an important discipline in which engineers and biologists are working together to design new and useful biological systems composed of genetic circuits. The purpose of developing genetic circuits is to carry out desired logical functions inside a living cell. This...
Integrated circuits and logic operations based on single-layer MoS2.
Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras
2011-12-27
Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.
Ones and zeros understanding Boolean algebra digital circuits and the logic of sets
Gregg, John
1998-01-01
"Ones and Zeros explains, in lay terms, Boolean algebra, the suprisingly simple system of mathematical logic used in digital computer circuitry. Ones and Zeros follows the development of this logic system from its origins in Victorian England to its rediscovery in this century as the foundation of all modern computing machinery. Readers will learn about the interesting history of the development of symbolic logic in particular, and the often misunderstood process of mathematical invention and scientific discovery, in general. Ones and Zeros also features practical exercises with answers, real-world examples of digital circuit design, and a reading list." "Ones and Zeros will be of particular interest to software engineers who want to gain a comprehensive understanding of computer hardware." "Outstanding features include: a history of mathematical logic, an explanation of the logic of digital circuits, and hands-on exercises and examples."--Jacket.
Redox Active Binary Logic Gate Circuit for Homeland Security.
Gaikwad, Pramod; Kadlag, Kavita; Nambiar, Manasa; Devendrachari, Mruthyunjayachari Chattanahalli; Aralekallu, Shambhulinga; Kottaichamy, Alagar Raja; Manzoor Bhat, Zahid; Thimmappa, Ravikumar; Shafi, Shahid Pottachola; Thotiyl, Musthafa Ottakam
2017-08-01
Bipolar junction transistors are at the frontiers of modern electronics owing to their discrete voltage regulated operational levels. Here we report a redox active binary logic gate (RLG) which can store a "0" and "1" with distinct operational levels, albeit without an external voltage stimuli. In the RLG, a shorted configuration of half-cell electrodes provided the logic low level and decoupled configuration relaxed the system to the logic high level due to self-charge injection into the redox active polymeric system. Galvanostatic intermittent titration and electrochemical quartz crystal microbalance studies indicate the kinetics of self-charge injection are quite faster and sustainable in polypyrrole based RLG, recovering more than 70% signal in just 14 s with minor signal reduction at the end of 10000 cycles. These remarkable properties of RLGs are extended to design a security sensor which can detect and count intruders in a locality with decent precision and switching speed.
Reversal of theta rhythm flow through intact hippocampal circuits.
Jackson, Jesse; Amilhon, Bénédicte; Goutagny, Romain; Bott, Jean-Bastien; Manseau, Frédéric; Kortleven, Christian; Bressler, Steven L; Williams, Sylvain
2014-10-01
Activity flow through the hippocampus is thought to arise exclusively from unidirectional excitatory synaptic signaling from CA3 to CA1 to the subiculum. Theta rhythms are important for hippocampal synchronization during episodic memory processing; thus, it is assumed that theta rhythms follow these excitatory feedforward circuits. To the contrary, we found that theta rhythms generated in the rat subiculum flowed backward to actively modulate spike timing and local network rhythms in CA1 and CA3. This reversed signaling involved GABAergic mechanisms. However, when hippocampal circuits were physically limited to a lamellar slab, CA3 outputs synchronized CA1 and the subiculum using excitatory mechanisms, as predicted by classic hippocampal models. Finally, analysis of in vivo recordings revealed that this reversed theta flow was most prominent during REM sleep. These data demonstrate that communication between CA3, CA1 and the subiculum is not exclusively unidirectional or excitatory and that reversed inhibitory theta signaling also contributes to intrahippocampal synchrony.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-27
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-01
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Hafiz, M. A. A.
2016-08-18
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Experimental investigation of a four-qubit linear-optical quantum logic circuit.
Stárek, R; Mičuda, M; Miková, M; Straka, I; Dušek, M; Ježek, M; Fiurášek, J
2016-09-20
We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and several two-qubit and single-qubit gates. The C(3)Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.
Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage
2017-03-01
It would be easier for the attacker to analyze the device as a black box with brute force. Power, Area, and Delay Overheads: Overhead for power...linear time with respect to the key length by applying input vectors to an unlocked fabricated device, observing device outputs, and using...Logic Enc tacks n is highly re key length can be arbitra ns, brute for wever, as sta has been show are aimed at i n unlocked fab Cells: Camo ic
CMOS-based carbon nanotube pass-transistor logic integrated circuits
Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao
2012-01-01
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080
Energy-Efficient and Secure S-Box circuit using Symmetric Pass Gate Adiabatic Logic
Energy Technology Data Exchange (ETDEWEB)
Kumar, Dinesh [University of Kentucky, Lexington; Thapliyal, Himanshu [ORNL; Mohammad, Azhar [University of Kentucky, Lexington; Singh, Vijay [University of Kentucky, Lexington; Perumalla, Kalyan S [ORNL
2016-01-01
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for lowpower portable electronic devices and Internet-of-Things (IoT) based electronic devices.
A Novel 3-Input AND/XOR Gate Circuit for Reed-Muller Logic Applications
Directory of Open Access Journals (Sweden)
Yang Yuan
2016-01-01
Full Text Available 3-input AND/XOR is the basic complex gate of Reed-Muller logic. Low energy consumption is important for Reed-Muller logic circuit implementation. Against the drawbacks of the published gate-level and transistor-level 3-input AND/XOR gate design in power and power delay product (PDP, a low energy consumption 3-input AND/XOR gate is proposed by employing multi-rails and hybrid-CMOS techniques to improve its speed and short the signal transimission path. Under 55nm CMOS process, post-simulations in different process corners are carried out by using HSPICE and compared with the published circuits. Simulation results show that the proposed circuit has advantages over published designs. For typical process corners, the improvement of the proposed circuit can be up to 27.21%, 19.23% and 35.39%, respectively, in terms of power, delay and power delay product.
Novel shift register eliminates logic gates and power switching circuits
Cliff, R. A.
1971-01-01
Register requiring two integrated circuits per stage has nominal power dissipation of 3.5 mW per stage, its use eliminates reset pulse, allowing data transfer to occur in less than 1 microsecond, and eliminates power application to both right and left portions of the register simultaneously.
Proposal for all-graphene monolithic logic circuits
Kang, Jiahao; Sarkar, Deblina; Khatami, Yasin; Banerjee, Kaustav
2013-08-01
Since the very inception of integrated circuits, dissimilar materials have been used for fabricating devices and interconnects. Typically, semiconductors are used for devices and metals are used for interconnecting them. This, however, leads to a "contact resistance" between them that degrades device and circuit performance, especially for nanoscale technologies. This letter introduces and explores an "all-graphene" device-interconnect co-design scheme, where a single 2-dimensional sheet of monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the use of external contacts is alleviated, resulting in substantial reduction in contact parasitics. Calculations based on tight-binding theory and Non-Equilibrium Green's Function (NEGF) formalism solved self-consistently with the Poisson's equation are used to analyze the intricate properties of the proposed structure. This constitutes the first NEGF simulation based demonstration that devices and interconnects can be built using the "same starting material" - graphene. Moreover, it is also shown that all-graphene circuits can surpass the static performances of the 22 nm complementary metal-oxide-semiconductor devices, including minimum operable supply voltage, static noise margin, and power consumption.
Waje, Ms. Manisha G.; Dakhole, Pravin, Dr.
2017-08-01
Quantum Dot Cellular Automata has attracted a lot of attention due to its extremely small feature size and ultra low power consumption. It is a possible alternative for transistor based technology. This paper presents the construction of Irreversible and reversible Logic Generator Block using quantum dot cellular automata. QCA based Irreversible and irreversible Logic generator block generates the logic of various devices like 1-Bit comparator, 1-Bit Half Adder, 1-Bit Half Subtractor, AND gate, XOR gate, NOR gate and XNOR gate. Proposed design of QCA based LGB is cost effective and easy to fabricate due to absence of wire crossings in irreversible LGB and no information loss in reversible LGB. This block can be made more efficient by using control lines. Depending on individual value on control line, logic of individual device will be generated. QCADesigner 2.0.3 tool is used for design and simulation of QCA based Logic Generator Block. Similarly here Reversible logic based Logic generator block is proposed which will be able to generate different logic. Area requirement of Reversible LGB is 85% less as compared to Irreversible LGB. Reversible logic provides ideally zero power dissipation that is no information loss is there.
Directory of Open Access Journals (Sweden)
Grazvydas Ziemys
2016-05-01
Full Text Available We have investigated the magnetization reversal of fabricated Co/Pt nanomagnets with perpendicular anisotropy within a wide range of magnetic field pulse widths. This experiment covers the pulse lengths from 700 ms to 20 ns. We observed that the commonly used Arrhenius model fits very well the experimental data with a single parameter set for pulse times above 100 ns (tp > 100 ns. However, below 100 ns (tp < 100 ns, a steep increase of the switching field amplitude is observed and the deviation from the Arrhenius model becomes unacceptable. For short pulse times the model can be adjusted by the reversal time term for the dynamic switching field which is only dependent on the pulse amplitude and not on temperature anymore. Precise modeling of the magnetization reversal in the sub-100 ns-range is crucially important to ensure reliable operation in the favored GHz-range as well as to explore and design new kinds of Nanomagnetic Logic circuits and architectures.
Rhee, Minsoung; Burns, Mark A
2009-11-07
We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.
Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic
DEFF Research Database (Denmark)
Lassen, Peter Stuhr; Long, S. I.; Nary, K. R.
1993-01-01
Two-phase dynamic FET logic (TDFL) gates are used in GaAs MESFET MSI circuits to implement very low power 4-b ripple carry adders and a variable modulus (2 to 31) prescaler. Operation of the adders is demonstrated at 500 MHz with an associated power dissipation of less than 1.0 mW and at 750 MHz...
Radiation Hardened NULL Convention Logic Asynchronous Circuit Design
Directory of Open Access Journals (Sweden)
Liang Zhou
2015-10-01
Full Text Available This paper proposes a radiation hardened NULL Convention Logic (NCL architecture that can recover from a single event latchup (SEL or single event upset (SEU fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.
Directory of Open Access Journals (Sweden)
Sukhdev Roy
2012-01-01
Full Text Available We present designs of all-optical reversible gates, namely, Feynman, Toffoli, Peres, and Feynman double gates, with optically controlled microresonators. To demonstrate the applicability, a bacteriorhodopsin protein-coated silica microcavity in contact between two tapered single-mode fibers has been used as an all-optical switch. Low-power control signals (<200 μW at 532 nm and at 405 nm control the conformational states of the protein to switch a near infrared signal laser beam at 1310 or 1550 nm. This configuration has been used as a template to design four-port tunable resonant coupler logic gates. The proposed designs are general and can be implemented in both fiber-optic and integrated-optic formats and with any other coated photosensitive material. Advantages of directed logic, high Q-factor, tunability, compactness, low-power control signals, high fan-out, and flexibility of cascading switches in 2D/3D architectures to form circuits make the designs promising for practical applications.
Directory of Open Access Journals (Sweden)
Liang Zhou
2015-05-01
Full Text Available This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL, also known as Sleep Convention Logic (SCL, which combines Multi-Threshold CMOS (MTCMOS with NULL Convention Logic (NCL, to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L slept, Bit-Wise MTNCL (BWMTNCL, MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster.
Tunable Radiative Thermal Rectifiers : Toward Thermal Logical Circuits
Nefzaoui, Elyes; Ezzahri, Younès; Joulain, Karl; Drevillon, Jérémie
2015-01-01
International audience; Thermal rectification can be defined as an asymmetry in the heat flux when the temperature difference between two interacting thermal reservoirs is reversed. We present a thermal rectifier concept based on far-field radiative heat transfer. The device is composed of two opaque thermal baths 1 and 2 at temperatures T 1 and T 2 respectively and exchanging heat through thermal radiation. The two interacting bodies are made of spectrally selective photonic structures with ...
Directory of Open Access Journals (Sweden)
Javier Macia
2016-02-01
Full Text Available Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit's complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined.
Fully Printed Stretchable Thin-Film Transistors and Integrated Logic Circuits.
Cai, Le; Zhang, Suoming; Miao, Jinshui; Yu, Zhibin; Wang, Chuan
2016-12-27
This paper reports intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits directly printed on elastomeric polydimethylsiloxane (PDMS) substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO3) nanoparticles. The BaTiO3/PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. This work may offer an entry into more sophisticated stretchable electronic systems with monolithically integrated sensors, actuators, and displays, fabricated by scalable and low-cost methods for real life applications.
Shin, SeungJun; Yu, YunSeop; Choi, JungBum
2008-10-01
New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.
Flux qubit interaction with rapid single-flux quantum logic circuits: Control and readout
Klenov, N. V.; Kuznetsov, A. V.; Soloviev, I. I.; Bakurskiy, S. V.; Denisenko, M. V.; Satanin, A. M.
2017-07-01
We present the results of an analytical study and numerical simulation of the dynamics of a superconducting three-Josephson-junction (3JJ) flux qubit magnetically coupled with rapid single-flux quantum (RSFQ) logic circuit, which demonstrate the fundamental possibility of implementing the simplest logic operations at picosecond times, as well as rapid non-destructive readout. It is shown that when solving optimization problems, the qubit dynamics can be conveniently interpreted as a precession of the magnetic moment vector around the direction of the magnetic field. In this case, the role of magnetic field components is played by combinations of the Hamiltonian matrix elements, and the role of the magnetic moment is played by the Bloch vector. Features of the 3JJ qubit model are discussed during the analysis of how the qubit is affected by exposure to a short control pulse, as are the similarities between the Bloch and Landau-Lifshitz-Gilbert equations. An analysis of solutions to the Bloch equations made it possible to develop recommendations for the use of readout RSFQ circuits in implementing an optimal interface between the classical and quantum parts of the computer system, as well as to justify the use of single-quantum logic in order to control superconducting quantum circuits on a chip.
Directory of Open Access Journals (Sweden)
D. V. Zakablukov
2014-01-01
Full Text Available The subject of study of this paper is reversible logic circuits. The irreversibility of computation can lead in the future to significant energy loss during the calculation process. Reversible circuits can be widely used in devices operating under conditions of limited computational resources.Presently, the problem of reversible logic synthesis is widely studied. The task a synthesis algorithm can face with is to reduce the gate complexity of synthesized circuit. One way to solve this problem is to use equivalent replacement tables for the gate compositions. The disadvantage of this approach is that it is necessary to build replacement tables, it takes a long time to find the replacement in the table, and there is no way to build an appropriate universal replacement table for arbitrary reversible circuit. The aim of this paper is to develop the solution for the problem of gate complexity reduction for the reversible circuits without using equivalent replacement tables for the gate compositions.This paper makes a generalization of the k-CNOT gate for the case of zero value at some of the gate control inputs. To describe such gates it suggests using a set of direct control inputs and a set of inverted ones. A definition of the independence of two reversible gates is introduced. Two independent gates standing next to each other in the circuit can be swapped without changing the circuit result transformation. Various conditions of the independence of two reversible gates are considered including conditions imposed to the set of direct control inputs and the set of inverted ones. It is proved that two gates are independent if there is, at least, one common control input, which differs only by the type (direct or inverted.Various equivalent replacements of two k-CNOT gates compositions and its conditions imposed to the set of direct control inputs and to the set of inverted ones are considered. The proof of correctness for such replacements is
Bias Reversal Technique in SQUID Bootstrap Circuit (SBC) Scheme
Rong, Liangliang; Zhang, Yi; Zhang, Guofeng; Wu, Jun; Dong, Hui; Qiu, Longqing; Xie, Xiaoming; Offenhüusser, Andreas
Recently, a SQUID direct readout scheme called voltage-biased SQUID Bootstrap Circuit (SBC) is introduced to reduce preamplifier noise contribution. In this paper, we describe a concept of SBC with bias reversal technique which can suppress SQUID intrinsic 1/f noise. When applying a symmetrically rectangular voltage across SBC, two I-Φ characteristics appear at the amplifier output. In order to return to one I - Φ curve, a demodulation technique is required. Because of the asymmetry of typical SBC I-Φ curve, the demodulation method is realized by using a flux compensation of one half Φ0 flux shift. The output signal is then filtered and returned to one I-Φ curve for ordinary FLL readout. It was found, the reversal frequency fR can be dramatically enhanced when using a preamplifier consisting of two operational amplifiers. A planar Nb SQUID magnetometer with a loop-inductance of 350 pH, fR =50 kHz and a second order low pass filter with 10 kHz cut off frequency was employed in our experiment. Results prove the feasibility of SBC bias reversal method. Comparative experiment on noise performance will be carried out in further studies.
Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits
Directory of Open Access Journals (Sweden)
Kwang-Jow Gan
2016-06-01
Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.
Li, Shu; Zhang, Tong
2008-05-07
Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
Energy Technology Data Exchange (ETDEWEB)
Mitra, Kalyan Yoti, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Martínez-Domingo, Carme [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra, Spain and Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Ramon, Eloi, E-mail: eloi.ramon@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Nanobioelectronics and Biosensors Group, Catalan Institute of Nanotechnology (ICN), Universitat Autònoma de Barcelona, Bellaterra, Catalonia (Spain); Carrabina, Jordi, E-mail: jordi.carrabina@uab.cat [Printed Microelectronics Group, CAIAC, Universitat Autònoma de Barcelona, Bellaterra (Spain); Gomes, Henrique Leonel, E-mail: hgomes@ualg.pt [Universidade do Algarve, Institute of Telecommunications, Faro (Portugal); Baumann, Reinhard R., E-mail: reinhard.baumann@mb.tu-chemnitz.de [Technische Universität Chemnitz, Department of Digital Printing and Imaging Technology, Chemnitz (Germany); Fraunhofer Institute for Electronic Nano Systems (ENAS), Department of Printed Functionalities, Chemnitz (Germany)
2015-02-17
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.
Genetic program based data mining to reverse engineer digital logic
Smith, James F., III; Nguyen, Thanh Vu H.
2006-04-01
A data mining based procedure for automated reverse engineering and defect discovery has been developed. The data mining algorithm for reverse engineering uses a genetic program (GP) as a data mining function. A genetic program is an algorithm based on the theory of evolution that automatically evolves populations of computer programs or mathematical expressions, eventually selecting one that is optimal in the sense it maximizes a measure of effectiveness, referred to as a fitness function. The system to be reverse engineered is typically a sensor. Design documents for the sensor are not available and conditions prevent the sensor from being taken apart. The sensor is used to create a database of input signals and output measurements. Rules about the likely design properties of the sensor are collected from experts. The rules are used to create a fitness function for the genetic program. Genetic program based data mining is then conducted. This procedure incorporates not only the experts' rules into the fitness function, but also the information in the database. The information extracted through this process is the internal design specifications of the sensor. Uncertainty related to the input-output database and the expert based rule set can significantly alter the reverse engineering results. Significant experimental and theoretical results related to GP based data mining for reverse engineering will be provided. Methods of quantifying uncertainty and its effects will be presented. Finally methods for reducing the uncertainty will be examined.
Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig
2013-05-01
ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.
Digital logic circuit based on two component molecular systems of BSA and salen
Hai-Bin, Lin; Feng, Chen; Hong-Xu, Guo
2018-02-01
A new fluorescent molecular probe 1 was designed and constructed by combining bovine serum albumin (BSA) and N,N‧-bis(salicylidene)ethylenediamine (salen). Stimulated by Zn2 +, tris, or EDTAH2Na2, the distance between BSA and salen was regulated, which was accompanied by an obvious change in the fluorescence intensity at 350 or 445 nm based on Förster resonance energy transfer. Moreover, based on the encoding binary digits in these inputs and outputs applying positive logic conventions, a monomolecular circuit integrating one OR, three NOT, and three YES gates, was successfully achieved.
High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes
Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried
2017-09-01
As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.
Design of programmable logic controller auto power reset circuit for FM transmitter
Directory of Open Access Journals (Sweden)
Adisak Pattanajakr
2016-06-01
Full Text Available The mono-stereo controller using audio mute clock is used at the International Broadcasting Bureau (IBB FM 106.6 MHz transmitter in Ulaan Baatar, Mongolia since 2010. The major problem of the FM broadcast station was from the frozen Programmable Logic Controller, PLC, which must be manually reset and the report by the VOA listeners. Then, the PLC auto power reset circuit is proposed and built in mono-stereo controller to monitor the operation of the PLC. The circuit is also used to restart the PLC whenever, it is frozen. The cloud router and Transmission Control Protocol/Internet Protocol (TCP/IP to Recommended Standard number 232 (RS-232 converter are used to synchronize the PLC time. From the results, this circuit can improve the transmitter availability and quality of the 24 hours/day broadcast program without affection to the listeners. The reliability of the cloud router is acceptable with low delay of data transfer via the internet connection between Thailand to Mongolia. The cloud router which the IBB leases cloud service from the provider that offers high speed internet up to 1000 Mb/s, via the remote terminal is used for the schedule program and the time synchronization of the PLC correctly. The proposed system is very stable and there is no problem of the frozen PLC whether it connects to the internet or not. Hence, the designed PLC auto power reset circuit can be used to eliminate the frozen PLC problem.
Directory of Open Access Journals (Sweden)
Md. Kamrul Hassan
2017-08-01
Full Text Available Quantum-dot cellular automata (QCA is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS technology. In this article, we present the dataset of average output polarization (AOP for basic reversible logic gates presented in Ali Newaz et al. (2016 [1]. QCADesigner 2.0.3 has been employed to analysis the AOP of reversible gates at different temperature levels in Kelvin (K unit.
An enzyme-based reversible CNOT logic gate realized in a flow system.
Moseley, Fiona; Halámek, Jan; Kramer, Friederike; Poghossian, Arshak; Schöning, Michael J; Katz, Evgeny
2014-04-21
An enzyme system organized in a flow device was used to mimic a reversible Controlled NOT (CNOT) gate with two input and two output signals. Reversible conversion of NAD(+) and NADH cofactors was used to perform a XOR logic operation, while biocatalytic hydrolysis of p-nitrophenyl phosphate resulted in an Identity operation working in parallel. The first biomolecular realization of a CNOT gate is promising for integration into complex biomolecular networks and future biosensor/biomedical applications.
DEFF Research Database (Denmark)
Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid
As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...... transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results...... obtained using the 70nm Berkeley predictive models, our proposed circuit increases the noise immunity by least 2times compared to previous circuits...
Chauhan, Chanderkanta; Bedi, Amna; Kumar, Santosh
2017-02-01
In this ultra fast computing era power optimization is a major technological challenge that requires new computing paradigms. Conservative and reversible logic opens up the possibility of ultralow power computing. In this paper, basic reversible logic gate (double Feynman gate) using the lithium-niobate based Mach-Zehnder interferometer is proposed. The results are verified using beam propagation method and MATLAB simulations.
Tian, Yonghui; Liu, Zilong; Xiao, Huifu; Zhao, Guolin; Liu, Guipeng; Yang, Jianhong; Ding, Jianfeng; Zhang, Lei; Yang, Lin
2017-07-25
We experimentally demonstrate a reconfigurable electro-optic directed logic circuit which can perform any combinatorial logic operation using cascaded carrier-injection micro-ring resonators (MRRs), and the logic circuit is fabricated on the silicon-on-insulator (SOI) substrate with the standard commercial Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process. PIN diodes embedded around MRRs are employed to achieve the carrier injection modulation. The operands are represented by electrical signals, which are applied to the corresponding MRRs to control their switching states. The operation result is directed to the output port in the form of light. For proof of principle, several logic operations of three-operand with the operation speed of 100 Mbps are demonstrated successfully.
A reversible fluorescent logic gate for sensing mercury and iodide ions based on a molecular beacon.
Wu, Xu; Chen, Jiao; Zhao, Julia Xiaojun
2013-09-21
A simple, rapid, and reversible fluorescent DNA INHIBIT logic gate has been developed for sensing mercury (Hg(2+)) and iodide (I(-)) ions based on a molecular beacon (MB). In this logic gate, a mercury ion was introduced as the first input into the MB logic gate system to assist in the hybridization of the MB with an assistant DNA probe through the thymine-Hg(2+)-thymine interaction, which eventually restored the fluorescence of MB as the output. With this signal-on process, mercury ions can be detected with a limit of detection as low as 7.9 nM. Furthermore, when iodide ions were added to the Hg(2+)/MB system as the second input, the fluorescence intensity decreased because Hg(2+) in the thymine-Hg(2+)-thymine complex was grabbed by I(-) due to a stronger binding force. Iodide ions can be detected with a limit of detection of 42 nM. Meanwhile, we studied the feasibility and basic performance of the DNA INHIBIT logic gate, optimized the logic gate conditions, and investigated its sensitivity and selectivity. The results showed that the MB based logic gate is highly selective and sensitive for the detection of Hg(2+) and I(-) over other interfering cations and anions.
Electro-optic directed XOR logic circuits based on parallel-cascaded micro-ring resonators.
Tian, Yonghui; Zhao, Yongpeng; Chen, Wenjie; Guo, Anqi; Li, Dezhao; Zhao, Guolin; Liu, Zilong; Xiao, Huifu; Liu, Guipeng; Yang, Jianhong
2015-10-05
We report an electro-optic photonic integrated circuit which can perform the exclusive (XOR) logic operation based on two silicon parallel-cascaded microring resonators (MRRs) fabricated on the silicon-on-insulator (SOI) platform. PIN diodes embedded around MRRs are employed to achieve the carrier injection modulation. Two electrical pulse sequences regarded as two operands of operations are applied to PIN diodes to modulate two MRRs through the free carrier dispersion effect. The final operation result of two operands is output at the Output port in the form of light. The scattering matrix method is employed to establish numerical model of the device, and numerical simulator SG-framework is used to simulate the electrical characteristics of the PIN diodes. XOR operation with the speed of 100Mbps is demonstrated successfully.
The ATPG Attack for Reverse Engineering of Combinational Hybrid Custom-Programmable Circuits
2017-03-23
The ATPG Attack for Reverse Engineering of Combinational Hybrid Custom- Programmable Circuits Raza Shafiq Hamid Mahmoodi Houman Homayoun Hassan... programmable circuits. While functionality of programmable cells are only known to trusted parties, effective techniques for activation and propagation...of the cells are introduced. The ATPG attack carefully studies dependency of programmable cells to develop their (partial) truth tables. Results
Yanin, AF; Kompaniets, KG; Amel'chakov, MB; Gorbacheva, EA; Dzaparova, IM; Kindin, VV; Novosel'tsev, YF; Striganov, PS
2004-01-01
A schematic diagram of a hodoscope with 3200 amplitude channels is described. The hodoscope is based on state-of-the-art programmable logic integral circuits (PLICs). Thanks to the use of PLICs, it is capable of measuring the lengths of input signals in each channel and monitoring their shape. In
VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate
Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab
2017-08-01
Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.
Sasamal, Trailokya Nath; Singh, Ashutosh Kumar; Ghanekar, Umesh
2017-12-01
Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for designing area and power efficient reversible logic gates. The proposed designs achieve superior performance by incorporating a compact 2-input XOR gate. The proposed design for Feynman, Toffoli, and Fredkin gates demonstrates 28.12, 24.4, and 7% reduction in cell count and utilizes 46, 24.4, and 7.6% less area, respectively over previous best designs. Regarding the cell count (area cover) that of the proposed Peres gate and Double Feynman gate are 44.32% (21.5%) and 12% (25%), respectively less than the most compact previous designs. Further, the delay of Fredkin and Toffoli gates is 0.75 clock cycles, which is equal to the delay of the previous best designs. While the Feynman and Double Feynman gates achieve a delay of 0.5 clock cycles, equal to the least delay previous one. Energy analysis confirms that the average energy dissipation of the developed Feynman, Toffoli, and Fredkin gates is 30.80, 18.08, and 4.3% (for 1.0 E k energy level), respectively less compared to best reported designs. This emphasizes the beneficial role of using proposed reversible gates to design complex and power efficient QCA circuits. The QCADesigner tool is used to validate the layout of the proposed designs, and the QCAPro tool is used to evaluate the energy dissipation.
Ding, Jianfeng; Yang, Lin; Chen, Qiaoshan; Zhang, Lei; Zhou, Ping
2017-07-01
We demonstrate a directed XNOR/XOR optical logic circuit based on silicon Mach-Zehnder interferometer. The device with the symmetric arm design is wavelength-insensitive in a wavelength range of 40 nm. The device has an electro-optical bandwidth of around 20 GHz. When the device is optically biased at the maximum or minimum transmission points by tuning the heater on one of its arms, it can perform the XNOR or XOR operations respectively at a speed up to 20 Gbps. The high-speed and reconfigurable abilities of the device make it suitable for the future programmable optical logic array.
Energy Technology Data Exchange (ETDEWEB)
Yang, Yong Suk [Electronics and Telecommunications Research Institute, Yuseong, Daejon 305-350 (Korea, Republic of)], E-mail: jullios@etri.re.kr; Chu, Hye Yong; Kim, Seong Hyun; Lim, Sang Chul; Koo, Jae Bon; Lee, Jung Hun; Ku, Chan Hoe; Lee, Jeong-Ik; Do, Lee-Mi; Hwang, Chi Sun; Park, Sang-He Ko; Kim, Gi Heon; Jung, Sung Mook [Electronics and Telecommunications Research Institute, Yuseong, Daejon 305-350 (Korea, Republic of)
2007-07-16
Organic electronic devices using a pentacene have improved importantly in the last several years. We fabricated pentacene organic thin-film transistors (OTFTs) with dielectric SiO{sub 2} and ferroelectric Pb(Zr{sub 0.3},Ti{sub 0.7})O{sub 3} (PZT) gate insulators. The organic devices using SiO{sub 2} and PZT films had the field-effect mobility of approximately 0.1 and 0.004 cm{sup 2}/V s, respectively. The drain current in the transfer curve of pentacene/PZT transistors showed a hysteresis behavior originated in a ferroelectric polarization switching. In order to investigate the polarization effect of PZT gate dielectrics in a logic circuit, the simple voltage inverter using SiO{sub 2} and PZT films was fabricated and measured by an output-input measurement. The gain of inverter at the poling-down state was approximately 7.2 and it was three times larger than the value measured at the poling-up state.
Directory of Open Access Journals (Sweden)
Mohammed Shoeb Mohiuddin
2014-09-01
Full Text Available It is often difficult to develop an accurate mathematical model of DC motor due to unknown load variation, unknown and unavoidable parameter variations or nonlinearities due to saturation temperature variations and system disturbances. Fuzzy logic application can handle such nonlinearities so that the controller design is fundamentally robust which is not possible in conventional controllers. The knowledge base of a fuzzy logic controller (FLC encapsulates expert knowledge and consists of the Data base (membership functions and Rule-Base of the controller. Optimization of both these knowledge base components is critical to the performance of the controller and has traditionally been achieved through a process of trial and error. Such an approach is convenient for FLCs having low numbers of input variables however for greater numbers of inputs, more formal methods of knowledge base optimization are required. In this work, we study the challenging task of controlling the speed of DC motor. The feasibility of such controller design is evaluated by simulation in the MATLAB/Simulink environment. In this study Conventional Proportional Integral Derivative controller, Fuzzy logic controller using a chopper circuit and Fuzzy tuned PID controller are analyzed and compared. Simulation software like MATLAB with Simulink has been used for modeling and simulation purpose. The performance comparison of conventional controller with Fuzzy logic controller using chopper circuit and Fuzzy tuned PID controller has been done in terms of several performance measures Such as Settling time, Rise time and Overshoot.
Bhardwaj, Shubhrajyotsna; Singh, Ashok Kumar
2015-10-15
A novel anion probe 3 (2,4-di-tert-butyl-6-((2(2,4-dinitrophenyl) hydrazono) methyl) phenol) has been unveiled as an effective ratiometric and colorimetric sensor for selective and rapid detection of cyanide. The sensing behavior was demonstrated by UV-vis experiments and NMR studies. This sensory system exhibited prominent visual color change toward cyanide ion over other testing anions in DMSO (90%) solvent, with a 1:1 binding stoichiometry and a detection limit down to 3.6×10(-8) mol L(-1). Sensor reveals specific anti-jamming activity and reversible in the presence of Cu(2+) ions. This concept has been applied to design a logic gate circuit at the molecular level. Further we developed coated graphite electrode using probe 3 as ionophore and studied the performance characteristics of electrode. The sensitivity of ratiometric-based colorimetric assay is below the 1.9 μM, accepted by the World Health Organization as the highest permissible cyanide concentration in drinking water. So it can be applied for both quantitative determination and qualitative supervising of cyanide concentrations in real samples. Copyright © 2015 Elsevier B.V. All rights reserved.
The investigation of reverse traction current influence on tone track circuit modes
Directory of Open Access Journals (Sweden)
E.I.Jasсhuk
2012-12-01
Full Text Available Introduction: With the introduction of high-speed traffic there is an increased consumption of traction current by new types of rolling stock. This issue is important, as high levels of traction currents can have not only prevents, but also a dangerous impact on the equipment of railway automation devices. It is necessary to investigate the propagation of traction currents and potentials along the rails. Objective: Investigate the propagation of traction currents and potentials along the rails, the determination of critical currents, which not executed tone track circuits modes. Methods: In order to investigate the mathematical model, and the method of calculation tone track circuits modes was used. Results: By means of mathematical model, which includes being several rolling-stocks at the feeder zone, different rail resistance and isolation, the diagrams of currents and potentials propagations for DC and AC electric traction have been obtained. A comparative analysis of the experimental data and the results of the investigation has been realized. Based on received levels of reverse traction current their influence on track circuit modes has been investigated. Conclusions: The reverse traction current level near the substation and rolling-stock can be more than 600A. Great reverse traction current levels have an influence on tonal track circuit functioning, namely normal and shunt modes. When the traction current arrives 200 A there is a reduction criteria of tonal track circuits.
Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor.
Murali, K; Sinha, Sudeshna; Ditto, William L; Bulsara, Adi R
2009-03-13
The response of a noisy nonlinear system to deterministic input signals can be enhanced by cooperative phenomena. We show that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the noise intensity. As one increases the noise (for fixed threshold or nonlinearity), the probability of the output reflecting a NOR/OR operation increases to unity and then decreases. Changing the nonlinearity (or the thresholds) of the system changes the output into another logic operation (NAND/AND) whose probability displays analogous behavior. The interplay of nonlinearity and noise can yield logic behavior, and the emergent outcome of such systems is a logic gate. This "logical stochastic resonance" is demonstrated via an experimental realization of a two-state system with two (adjustable) thresholds.
Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.
Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl
2010-09-13
Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).
Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu
2017-01-01
Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.
Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing
2017-10-11
The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.
On Using Current Steering Logic in Mixed Analogue-digital Circuits
DEFF Research Database (Denmark)
Lehmann, Torsten
1998-01-01
The authors investigate power supply noise in mixed analogue-digital circuits, arising from communication between the analogue and digital parts of the circuit. Current steering techniques and proper buffering are used to show which noise currents can be reduced and which cannot. In addition...
Parallelization of Reversible Ripple-carry Adders
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal; Axelsen, Holger Bock
2009-01-01
{O}(m\\cdot k)$. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures...... wherein $m$ parallel $k$-bit reversible ripple-carry adders are combined to form a reversible $mk$-bit \\emph{ripple-block carry adder} with logic depth $\\mathcal{O}(m+k)$ for a \\emph{minimal} logic depth $\\mathcal{O}(\\sqrt{mk})$, thus improving on the $mk$-bit ripple-carry adder logic depth $\\mathcal...
Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging
Adato, Ronen; Zangeneh, Mahmoud; Zhou, Boyou; Joshi, Ajay; Goldberg, Bennett; Unlu, M Selim
2016-01-01
Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to addres...
Logic design for array-based circuits a structured design methodology
White, D E
1992-01-01
This book will show you how to approach the design covering everything from the circuit specification to the final design acceptance, including what support you can expect, sizing, timing analysis, power and packaging, various simulations, design verification, and design submission.
Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits
Directory of Open Access Journals (Sweden)
Ph. Teichmann
2005-01-01
Full Text Available Losses due to gate-leakage-currents become more dominant in new technologies as gate leakage currents increase exponentially with decreasing gate oxide thickness. The most promising Adiabatic Logic (AL families use a clocked power supply with four states. Hence, the full VDD voltage drops over an AL gate only for a quarter of the clock cycle, causing a full gate leakage only for a quarter of the clock period. The rising and falling ramps of the clocked power supply lead to an additional energy consumption by gate leakage. This energy is smaller than the fraction caused by the constant VDD drop, because the gate leakage exponentially depends on the voltage across the oxide. To obtain smaller energy consumption, Improved Adiabatic Logic (IAL has been introduced. IAL swaps all n- and p-channel transistors. The logic blocks are built of p-channel devices which show gate tunneling currents significantly smaller than in n-channel devices. Using IAL instead of conventional AL allows an additional reduction of the energy consumption caused by gate leakage. Simulations based on a 90nm CMOS process show a lowering in gate leakage energy consumption for AL by a factor of 1.5 compared to static CMOS. For IAL the factor is up to 4. The achievable reduction varies depending on the considered AL family and the complexity of the gate.
From Boolean logic to switching circuits and automata. Towards modern information technology
Energy Technology Data Exchange (ETDEWEB)
Stankovic, Radomir S. [Nis Univ. (RS). Dept. of Computer Science; Astola, Jaakko [Tampere Univ. of Technology (Finland). Dept. of Signal Processing
2011-07-01
Logic networks and automata are facets of digital systems. The change of the design of logic networks from skills and art into a scientific discipline was possible by the development of the underlying mathematical theory called the Switching Theory. The fundamentals of this theory come from the attempts towards an algebraic description of laws of thoughts presented in the works by George J. Boole and the works on logic by Augustus De Morgan. As often the case in engineering, when the importance of a problem and the need for solving it reach certain limits, the solutions are searched by many scholars in different parts of the word, simultaneously or at about the same time, however, quite independently and often unaware of the work by other scholars. The formulation and rise of Switching Theory is such an example. This book presents a brief account of the developments of Switching Theory and highlights some less known facts in the history of it. The readers will find the book a fresh look into the development of the field revealing how difficult it has been to arrive at many of the concepts that we now consider obvious. Researchers in the history or philosophy of computing will find this book a valuable source of information that complements the standard presentations of the topic. (orig.)
Logical diagnosis model turbojet engine including double-circuit intermittent flow of his injuries
Directory of Open Access Journals (Sweden)
О.П. Стьопушкіна
2007-01-01
Full Text Available In this article is considered question of the change quantitative and qualitative factors of the technical condition constructive element running part of jet engine. As a result called on experimental studies diagnostic sign were definite sign with provision for intermittent damages and on base this is built expert model of the turbojet double-circuit engine.
Directory of Open Access Journals (Sweden)
Mohammed Alawad
2015-03-01
Full Text Available This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit’s overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon.
Persistent and reversible consequences of combat stress on the mesofrontal circuit and cognition
van Wingen, Guido A.; Geuze, Elbert; Caan, Matthan W. A.; Kozicz, Tamás; Olabarriaga, Silvia D.; Denys, Damiaan; Vermetten, Eric; Fernández, Guillén
2012-01-01
Prolonged stress can have long-lasting effects on cognition. Animal models suggest that deficits in executive functioning could result from alterations within the mesofrontal circuit. We investigated this hypothesis in soldiers before and after deployment to Afghanistan and a control group using functional and diffusion tensor imaging. Combat stress reduced midbrain activity and integrity, which was associated to compromised sustained attention. Long-term follow-up showed that the functional and structural changes had normalized within 1.5 y. In contrast, combat stress induced a persistent reduction in functional connectivity between the midbrain and prefrontal cortex. These results demonstrate that combat stress has adverse effects on the human mesofrontal circuit and suggests that these alterations are partially reversible. PMID:22949649
Chaplin, J C; Russell, N A; Krasnogor, N
2012-07-01
In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.
Multi-Valued Logic Gates, Continuous Sensitivity, Reversibility, and Threshold Functions
İlhan, Aslı Güçlükan; Ünlü, Özgün
2016-01-01
We define an invariant of a multi-valued logic gate by considering the number of certain threshold functions associated with the gate. We call this invariant the continuous sensitivity of the gate. We discuss a method for analysing continuous sensitivity of a multi-valued logic gate by using experimental data about the gate. In particular, we will show that this invariant provides a lower bound for the sensitivity of a boolean function considered as a multi-valued logic gate. We also discuss ...
Directory of Open Access Journals (Sweden)
Selami KESLER
2009-01-01
Full Text Available The power flow of the rotor circuit is controlled by different methods in induction machines used for producing high torque in applications involved great power and constant output power with constant frequency in wind turbines. The voltage with slip frequency can be applied on rotor windings to produce controlled high torque and obtain optimal power factor and speed control. In this study, firstly, the dynamic effects of the voltage applying on rotor windings through the rings in slip-ring induction machines are researched and undesirable aspects of the method are exposed with simulations supported by experiments. Afterwards, a fuzzy logic based inverter model on rotor side is proposed with a view to improving the dynamic effects, controlling high torque producing and adjusting machine speed in instantaneous forced conditions. For the simulation model of the system in which the stator side is directly connected to the grid in steady state operation, a C/C++ algorithm is developed and the results obtained for different load conditions are discussed.
Directory of Open Access Journals (Sweden)
Ankur Khare
2016-05-01
Full Text Available Delays added by the encryption process represent an overhead for smart computing devices in ad-hoc and ubiquitous computing intelligent systems. Digital Logic Circuits are faster than other computing techniques, so these can be used for fast encryption to minimize processing delays. Chaotic Encryption is more attack-resilient than other encryption techniques. One of the most attractive properties of cryptography is known as an avalanche effect, in which two different keys produce distinct cipher text for the same information. Important properties of chaotic systems are sensitivity to initial conditions and nonlinearity, which makes two similar keys that generate different cipher text a source of confusion. In this paper a novel fast and secure Chaotic Map-based encryption technique using 2’s Compliment (CET-2C has been proposed, which uses a logistic map which implies that a negligible difference in parameters of the map generates different cipher text. Cryptanalysis of the proposed algorithm shows the strength and security of algorithm and keys. Performance of the proposed algorithm has been analyzed in terms of running time, throughput and power consumption. It is to be shown in comparison graphs that the proposed algorithm gave better results compare to different algorithms like AES and some others.
Initial ideas for automatic design and verification of control logic in reversible HDLs
DEFF Research Database (Denmark)
Wille, Robert; Keszocze, Oliver; Othmer, Lars
2016-01-01
not obvious. Moreover, implementations exist which may not be realized with a reversible control flow at all. In this work, we propose automatic methods for descriptions in the reversible HDL SyReC that can generate the required fi-conditions and check whether a reversible control flow indeed can be realized......In imperative reversible languages the commonly used conditional statements must, in addition to the established if -condition for forward computation, be extended with an additional fi-condition for backward computation. Unfortunately, deriving correct and consistent fi-conditions is often...
Moustafa, Ahmed; Younes, Ahmed; Hassan, Yasser F
2015-01-01
Quantum-dot cellular automata (QCA) are nanoscale digital logic constructs that use electrons in arrays of quantum dots to carry out binary operations. In this paper, a basic building block for QCA will be proposed. The proposed basic building block can be customized to implement classical gates, such as XOR and XNOR gates, and reversible gates, such as CNOT and Toffoli gates, with less cell count and/or better latency than other proposed designs.
Recovery of metallic concentrations from waste printed circuit boards via reverse floatation.
He, Jingfeng; Duan, Chenlong
2017-02-01
Efficient disposal of waste printed circuit boards (PCBs) is favorable toward recovering valuable components and reducing pollution. Reverse floatation was used to recover metallic concentrations from waste PCBs. Basic properties and mineralogical characteristics of raw PCBs were tested and analyzed. Results indicated that the grade of metallic concentrations declined as the size fraction of PCBs decreased. The major metallic elements found in PCBs were Cu, Pb, and Sn, as well as trace elements were also found in fine PCB particles. Kerosene and terpenic oil were used as the collector and frother in the floatation experiments. The effects of various operational factors, including the feeding concentration, aeration rate, and agitation speed of floatation machine, on the floatation performance of -0.25mm PCBs were experimentally studied to determine optimal range. The floatation results suggested that the yield of sinks and grade of metallic concentrations diminished significantly with the decrease of size fraction of PCBs. The maximum yields of sinks and highest grades of metallic concentrations were 48.72% and 16.86%, 47.96% and 14.61%, 44.36% and 8.81%, with the optimum recoveries of metallic concentrations of 94.69%, 90.06%, and 75.96% for size fractions of 0.125-0.25mm, 0.074-0.125mm, and -0.074mm PCBs, respectively. The recovery efficiency of metallic concentrations declined as the size fraction decreased. The efficient overall recovery performance of metallic concentrations from waste PCBs was obtained via reverse floatation. This study provides an alternative approach for disposing waste PCBs. Copyright © 2016 Elsevier Ltd. All rights reserved.
A Reversible DNA Logic Gate Platform Operated by One- and Two-Photon Excitations.
Tam, Dick Yan; Dai, Ziwen; Chan, Miu Shan; Liu, Ling Sum; Cheung, Man Ching; Bolze, Frederic; Tin, Chung; Lo, Pik Kwan
2016-01-04
We demonstrate the use of two different wavelength ranges of excitation light as inputs to remotely trigger the responses of the self-assembled DNA devices (D-OR). As an important feature of this device, the dependence of the readout fluorescent signals on the two external inputs, UV excitation for 1 min and/or near infrared irradiation (NIR) at 800 nm fs laser pulses, can mimic function of signal communication in OR logic gates. Their operations could be reset easily to its initial state. Furthermore, these DNA devices exhibit efficient cellular uptake, low cytotoxicity, and high bio-stability in different cell lines. They are considered as the first example of a photo-responsive DNA logic gate system, as well as a biocompatible, multi-wavelength excited system in response to UV and NIR. This is an important step to explore the concept of photo-responsive DNA-based systems as versatile tools in DNA computing, display devices, optical communication, and biology. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Optimized reversible binary-coded decimal adders
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal; Glück, Robert
2008-01-01
Abstract Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272-282] recently proposed, in this journal, a reversible adder for binary-coded decimals. This paper corrects and optimizes....... Keywords: Reversible logic circuit; Full-adder; Half-adder; Parallel adder; Binary-coded decimal; Application of reversible logic synthesis......) BCD addition, the circuit delay of 49 gates is significantly lower than is the number of bits used for the BCD representation. A complete set of reversible half- and full-adders for n-bit binary numbers and m-decimal BCD numbers is presented. The results show that special-purpose design pays off...
Novel Parity-Preserving Designs of Reversible 4-Bit Comparator
Qi, Xue-mei; Chen, Fu-long; Wang, Hong-tao; Sun, Yun-xiang; Guo, Liang-min
2014-04-01
Reversible logic has attracted much attention in recent years especially when the calculation with minimum energy consumption is considered. This paper presents two novel approaches for designing reversible 4-bit comparator based on parity-preserving gates, which can detect any fault that affects no more than a single logic signal. In order to construct the comparator, three variable EX-OR gate (TVG), comparator gate (CPG), four variable EX-OR gate block (FVGB) and comparator gate block (CPGB) are designed, and they are parity-preserving and reversible. Their quantum equivalent implementations are also proposed. The design of two comparator circuits is completed by using existing reversible gates and the above new reversible circuits. All these comparators have been modeled and verified in Verilog hardware description language (Verilog HDL). The Quartus II simulation results indicate that their circuits' logic structures are correct. The comparative results are presented in terms of quantum cost, delay and garbage outputs.
National Research Council Canada - National Science Library
Cho, Young‐Kyun; Jeong, Yoon‐Ha
2004-01-01
.... The operation of a 3‐MTJ inverter circuit is simulated at 15 K with parameters C g =C T =C clk =1 aF, R T =5 MΩ, V clk =40 mV, and V in =20 mV. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ...
Novel Designs of Quantum Reversible Counters
Qi, Xuemei; Zhu, Haihong; Chen, Fulong; Zhu, Junru; Zhang, Ziyang
2016-11-01
Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits' logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.
Wang, Gong-Wu; Liu, Jian; Wang, Xiao-Qin
2017-01-01
The ventral hippocampus (VH) and the basolateral amygdala (BLA) are both crucial in inhibitory avoidance (IA) memory. However, the exact role of the VH-BLA circuit in IA memory consolidation is unclear. This study investigated the effect of post-training reversible disconnection of the VH-BLA circuit in IA memory consolidation. Male Wistar rats…
Directory of Open Access Journals (Sweden)
Shih-Yu Li
2013-01-01
Full Text Available We expose the chaotic attractors of time-reversed nonlinear system, further implement its behavior on electronic circuit, and apply the pragmatical asymptotically stability theory to strictly prove that the adaptive synchronization of given master and slave systems with uncertain parameters can be achieved. In this paper, the variety chaotic motions of time-reversed Lorentz system are investigated through Lyapunov exponents, phase portraits, and bifurcation diagrams. For further applying the complex signal in secure communication and file encryption, we construct the circuit to show the similar chaotic signal of time-reversed Lorentz system. In addition, pragmatical asymptotically stability theorem and an assumption of equal probability for ergodic initial conditions (Ge et al., 1999, Ge and Yu, 2000, and Matsushima, 1972 are proposed to strictly prove that adaptive control can be accomplished successfully. The current scheme of adaptive control—by traditional Lyapunov stability theorem and Barbalat lemma, which are used to prove the error vector—approaches zero, as time approaches infinity. However, the core question—why the estimated or given parameters also approach to the uncertain parameters—remains without answer. By the new stability theory, those estimated parameters can be proved approaching the uncertain values strictly, and the simulation results are shown in this paper.
Privman, Vladimir; Strack, Guinevere; Solenov, Dmitry; Pita, Marcos; Katz, Evgeny
2008-09-18
We report an experimental evaluation of the "input-output surface" for a biochemical AND gate. The obtained data are modeled within the rate-equation approach, with the aim to map out the gate function and cast it in the language of logic variables appropriate for analysis of Boolean logic for scalability. In order to minimize "analog" noise, we consider a theoretical approach for determining an optimal set for the process parameters to minimize "analog" noise amplification for gate concatenation. We establish that under optimized conditions, presently studied biochemical gates can be concatenated for up to order 10 processing steps. Beyond that, new paradigms for avoiding noise buildup will have to be developed. We offer a general discussion of the ideas and possible future challenges for both experimental and theoretical research for advancing scalable biochemical computing.
"Glitch Logic" and Applications to Computing and Information Security
Stoica, Adrian; Katkoori, Srinivas
2009-01-01
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
James, A. P.; Francis, L. R. V. J.; Kumar, D.
2013-01-01
We report a resistance based threshold logic family useful for mimicking brain like large variable logic functions in VLSI. A universal Boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors and provides output voltage as a summation of weighted product of input voltages. The output of resistive divider is converted into a binary value by a threshold operation implemented by CMOS inverter and/or O...
Energy Technology Data Exchange (ETDEWEB)
Bonacini, S
2007-11-15
The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.
Magnetic-field-controlled reconfigurable semiconductor logic.
Joo, Sungjung; Kim, Taeyueb; Shin, Sang Hoon; Lim, Ju Young; Hong, Jinki; Song, Jin Dong; Chang, Joonyeon; Lee, Hyun-Woo; Rhie, Kungwon; Han, Suk Hee; Shin, Kyung-Ho; Johnson, Mark
2013-02-07
Logic devices based on magnetism show promise for increasing computational efficiency while decreasing consumed power. They offer zero quiescent power and yet combine novel functions such as programmable logic operation and non-volatile built-in memory. However, practical efforts to adapt a magnetic device to logic suffer from a low signal-to-noise ratio and other performance attributes that are not adequate for logic gates. Rather than exploiting magnetoresistive effects that result from spin-dependent transport of carriers, we have approached the development of a magnetic logic device in a different way: we use the phenomenon of large magnetoresistance found in non-magnetic semiconductors in high electric fields. Here we report a device showing a strong diode characteristic that is highly sensitive to both the sign and the magnitude of an external magnetic field, offering a reversible change between two different characteristic states by the application of a magnetic field. This feature results from magnetic control of carrier generation and recombination in an InSb p-n bilayer channel. Simple circuits combining such elementary devices are fabricated and tested, and Boolean logic functions including AND, OR, NAND and NOR are performed. They are programmed dynamically by external electric or magnetic signals, demonstrating magnetic-field-controlled semiconductor reconfigurable logic at room temperature. This magnetic technology permits a new kind of spintronic device, characterized as a current switch rather than a voltage switch, and provides a simple and compact platform for non-volatile reconfigurable logic devices.
Reversible synthesis of incompletely specified Boolean functions using functional decomposition
Rawski, Mariusz; Szotkowski, Piotr
2017-08-01
Conventional microelectronic technology reaches its limits, and reversible logic circuits might address at least one of the problems: unwanted energy dissipation. Unfortunately, current methods of reversible function synthesis have certain limitations, including suboptimal handling of incompletely specified Boolean functions and yielding circuit sizes (and costs) that can be vastly improved upon. This paper presents the application of functional decomposition as a crucial step in synthesis of reversible logic that cost-efficiently implements incompletely specified Boolean functions. A decomposition of an incompletely specified Boolean function into a network of smaller sub-functions, subsequently synthesized into reversible blocks and composed into a reversible system, yields significantly better results than direct reversible synthesis of the original, incompletely specified Boolean function. The experimental results presented in this paper demonstrate the potential of the proposed approach.
Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder
DEFF Research Database (Denmark)
Thomsen, Michael Kirkedal; Axelsen, Holger Bock
2008-01-01
) ripple-carry adder. We optimize this design with a novel parallelization scheme wherein m parallel k-bit CDKM-adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth O(m+k) for a minimal logic depth O(\\sqrt{mk}), thus improving on the mk-bit CDKM-adder logic depth O......(mk). We also show designs for garbage-less reversible set-less-than circuits. We compare the circuit costs of the CDKM and parallel adder in measures of circuit delay, width, gate and transistor count, and find that the parallelized adder offers significant speedups at realistic word sizes with modest...
Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic
Directory of Open Access Journals (Sweden)
Akash Agrawal
2017-01-01
Full Text Available With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic, 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic, and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.
Henriques, David; Rocha, Miguel; Saez-Rodriguez, Julio; Banga, Julio R
2015-09-15
Systems biology models can be used to test new hypotheses formulated on the basis of previous knowledge or new experimental data, contradictory with a previously existing model. New hypotheses often come in the shape of a set of possible regulatory mechanisms. This search is usually not limited to finding a single regulation link, but rather a combination of links subject to great uncertainty or no information about the kinetic parameters. In this work, we combine a logic-based formalism, to describe all the possible regulatory structures for a given dynamic model of a pathway, with mixed-integer dynamic optimization (MIDO). This framework aims to simultaneously identify the regulatory structure (represented by binary parameters) and the real-valued parameters that are consistent with the available experimental data, resulting in a logic-based differential equation model. The alternative to this would be to perform real-valued parameter estimation for each possible model structure, which is not tractable for models of the size presented in this work. The performance of the method presented here is illustrated with several case studies: a synthetic pathway problem of signaling regulation, a two-component signal transduction pathway in bacterial homeostasis, and a signaling network in liver cancer cells. Supplementary data are available at Bioinformatics online. julio@iim.csic.es or saezrodriguez@ebi.ac.uk. © The Author 2015. Published by Oxford University Press.
Mukherjee, Soma; Talukder, Shrabani
2016-05-01
A new Schiff-base, HL luminescent chemosensor of 1-amino pyrene and 8-hydroxy quinoline-2-carboxaldehyde was synthesized which demonstrates selective fluorimetric detection of Fe(3+) in aqueous medium with detection limit of 2.52 × 10(-8) M. The receptor shows selective 'turn-on' response towards Fe(3+) over other metal ions. This gradual 'turn-on' fluorescence response for Fe(3+) may be induced via CHEF (chelation-enhanced fluorescence) through close proximity of pyrene rings. The stoichiometry and binding property of HL with Fe(3+) was examined by emission studies. In presence of Fe(3+), HL also exhibits reversible change in emission pattern with EDTA and thus offers an interesting property of molecular 'INHIBIT' logic gate with Fe(3+) and EDTA as chemical inputs.
DEFF Research Database (Denmark)
Nilsson, Jørgen Fischer
A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...
Energy Technology Data Exchange (ETDEWEB)
Gonzalez M, J. L.; Rivero G, T.; Sainz M, E., E-mail: joseluis.gonzalez@inin.gob.mx [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)
2014-10-15
Due to the obsolescence of the instrumentation and control system of the nuclear research reactor IAN-R1, the Institute of Geology and Mining of Colombia, IngeoMinas, launched an international convoking for renewal it which was won by the Instituto Nacional de Investigaciones Nucleares (ININ). Within systems to design, the reactor protection system is described as important for safety, because this carried out, among others two primary functions: 1) ensuring the reactor shutdown safely, and 2) controlling the interlocks to protect against operational errors if defined conditions have not been met. To fulfill these functions, the various subsystems related to the safety report the state in which they are using binary signals and are connected to the inputs of two redundant logic wiring circuits called action logics (Al) that are part of the reactor protection system. These Al also serve as logical interface to indicate at all times the status of subsystems, both the operator and other systems. In the event that any of the subsystems indicates a state of insecurity in the reactor, the Al generate signals off (or scram) of the reactor, maintaining the interlock until the operator sends a reset signal. In this paper the design, implementation, verification and testing of circuits that make up the Al 1 and 2 of IAN-R1 reactor is described, considering the fulfillment of the requirements that the different international standards imposed on this type of design. (Author)
Logic functions and equations examples and exercises
Steinbach, Bernd
2009-01-01
With a free, downloadable software package available to help solve the exercises, this book focuses on practical and relevant problems that arise in the field of binary logics, with its two main applications - digital circuit design, and propositional logics.
Timed Safety Automata and Logic Conformance
National Research Council Canada - National Science Library
Young, Frank
1999-01-01
Timed Logic Conformance (TLC) is used to verify the behavioral and timing properties of detailed digital circuits against abstract circuit specifications when both are modeled as Timed Safety Automata (TSA...
Wolfendale, E
2013-01-01
MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi
Microelectromechanical resonator based digital logic elements
Hafiz, Md Abdullah Al
2016-10-20
Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.
Electronic devices and circuits
Pridham, Gordon John
1972-01-01
Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of
PM 3655 PHILIPS Logic analyzer
A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.
Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling
Lent, Craig S.; Liu, Mo; Lu, Yuhui
2006-08-01
We examine power dissipation in different clocking schemes for molecular quantum-dot cellular automata (QCA) circuits. 'Landauer clocking' involves the adiabatic transition of a molecular cell from the null state to an active state carrying data. Cell layout creates devices which allow data in cells to interact and thereby perform useful computation. We perform direct solutions of the equation of motion for the system in contact with the thermal environment and see that Landauer's Principle applies: one must dissipate an energy of at least kBT per bit only when the information is erased. The ideas of Bennett can be applied to keep copies of the bit information by echoing inputs to outputs, thus embedding any logically irreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. A promising alternative which we term 'Bennett clocking' requires only altering the timing of the clocking signals so that bit information is simply held in place by the clock until a computational block is complete, then erased in the reverse order of computation. This approach results in ultralow power dissipation without additional circuit complexity. These results offer a concrete example in which to consider recent claims regarding the fundamental limits of binary logic scaling.
Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling.
Lent, Craig S; Liu, Mo; Lu, Yuhui
2006-08-28
We examine power dissipation in different clocking schemes for molecular quantum-dot cellular automata (QCA) circuits. 'Landauer clocking' involves the adiabatic transition of a molecular cell from the null state to an active state carrying data. Cell layout creates devices which allow data in cells to interact and thereby perform useful computation. We perform direct solutions of the equation of motion for the system in contact with the thermal environment and see that Landauer's Principle applies: one must dissipate an energy of at least k(B)T per bit only when the information is erased. The ideas of Bennett can be applied to keep copies of the bit information by echoing inputs to outputs, thus embedding any logically irreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. A promising alternative which we term 'Bennett clocking' requires only altering the timing of the clocking signals so that bit information is simply held in place by the clock until a computational block is complete, then erased in the reverse order of computation. This approach results in ultralow power dissipation without additional circuit complexity. These results offer a concrete example in which to consider recent claims regarding the fundamental limits of binary logic scaling.
Energy Technology Data Exchange (ETDEWEB)
Pluss Contino, J.; Simon Ruiz, J. L.; Hernandez, A.; Menendez Martinez, A.; Yaglian Steiner, E.; Menendez Fernandez, A.; Marcelo Cano, F.
2004-07-01
Frequently physical and chemical alteration that can suffer feed water composition and membranes behaviour of reverse osmosis desalination plants (RODP), define a vague nature system from the point of view of decision make process. In this work, we proposes the utilization of the approximate reasoning associated with the fuzzy logic, as an alternative to approach this problem and to make possible early corrective actions, that is, to do a proactive maintenance with Condition-based maintenance (CBM) technology. (Author) 21 refs.
Marston, R M
2013-01-01
Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com
Simple and universal platform for logic gate operations based on molecular beacon probes.
Park, Ki Soo; Seo, Myung Wan; Jung, Cheulhee; Lee, Joon Young; Park, Hyun Gyu
2012-07-23
A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
System Measures Logic-Gate Delays
Blaes, Brent R.
1988-01-01
Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.
Reversible computing fundamentals, quantum computing, and applications
De Vos, Alexis
2010-01-01
Written by one of the few top internationally recognized experts in the field, this book concentrates on those topics that will remain fundamental, such as low power computing, reversible programming languages, and applications in thermodynamics. It describes reversible computing from various points of view: Boolean algebra, group theory, logic circuits, low-power electronics, communication, software, quantum computing. It is this multidisciplinary approach that makes it unique.Backed by numerous examples, this is useful for all levels of the scientific and academic community, from undergr
Tripathi, A.K.; Smits, E.C.P.; Putten, J.B.P.H. van der; Neer, M. van; Myny, K.; Nag, M.; Steudel, S.; Vicca, P.; O'Neill, K.; Veenendaal, E. van; Genoe, G.; Heremans, P.; Gelinck, G.H.
2011-01-01
In this work a technology to fabricate low-voltage amorphous gallium-indium-zinc oxide thin film transistors (TFTs) based integrated circuits on 25 µm foils is presented. High performance TFTs were fabricated at low processing temperatures (<150 °C) with field effect mobility around 17 cm2 /V s. The
Smullyan, Raymond
2008-01-01
This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T
Integrated devices in digital circuit design
Hope, G. S.
Aspects of combinational design are examined, taking into account logical operations, truth tables, Karnaugh maps as input output expressions, minimum forms, maximum forms, minterm forms, symbols, fundamental relationships, Karnaugh maps as design tools, the implementation of logic functions, logic and implementation, logic nor implementation, implementation examples, the exclusive or function, symmetrical forms, reduction, and practical circuits. Multiplexers and demultiplexers in combinational circuits are considered along with fundamental mode circuits, event-driven sequential circuits, event-driven circuit implementation using multiplexers, clock-driven sequential circuits, counters and multiplexers in clock-driven sequential circuits, state diagram construction, registers in logic design, a digital system, programming and programming aids, input and output techniques, operation and configuration of independent systems, and a definition of a Boolean algebra. Attention is also given to Intel's and Motorola's executable instructions.
Lengyel, Florian; St-Pierre, Benoit
2012-01-01
Denial Logic DL, a system of justification logic, is the logic of an agent whose justified beliefs are false, who cannot avow his own propositional attitudes or believe tautologies, but who can believe contradictions. Using Artemov's natural semantics for justification logic JL, in which justifications are interpreted as sets of formulas, we provide an inductive construction of models of DL, and show that DL is sound and complete. Some notions developed for JL, such as constant specifications...
The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations
Lee, Junwoo; Suh, Dong Ik; Park, Wanjun
2015-05-01
The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.
Kleene, Stephen Cole
1967-01-01
Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.
Rapid single flux quantum logic in high temperature superconductor technology
Shunmugavel, K.
2006-01-01
A Josephson junction is the basic element of rapid single flux quantum logic (RSFQ) circuits. A high operating speed and low power consumption are the main advantages of RSFQ logic over semiconductor electronic circuits. To realize complex RSFQ circuits in HTS technology one needs a reproducible
Marston, R M
1995-01-01
CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu
Rushton, Andrew
2011-01-01
Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types. This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features. Features to this edition include: * a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies...
K-maps: a vehicle to an optimal solution in combinational logic ...
African Journals Online (AJOL)
Application of Karnaugh maps (K-Maps) for the design of combinational logic circuits and sequential logic circuits is a subject that has been widely discussed. However, the use of K-Maps in the design of combinational logic circuits using medium scale integration (MSI) devices has not yet been widely explored.
Energy Technology Data Exchange (ETDEWEB)
Zadeh, L.A.
1988-01-01
The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived. 7 references.
Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata
Moharrami, Elham; Navimipour, Nima Jafari
2017-12-01
Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.
Digital circuit boards mach 1 GHz
Morrison, Ralph
2012-01-01
A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove
Tugué, Tosiyuki; Slaman, Theodore
1989-01-01
These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.
Fan, Daoqing; Shang, Changshuai; Gu, Wenling; Wang, Erkang; Dong, Shaojun
2017-08-09
Glutathione (GSH) plays crucial roles in various biological functions, the level alterations of which have been linked to varieties of diseases. Herein, we for the first time expanded the application of oxidase-like property of MnO2 nanosheet (MnO2 NS) to fluorescent substrates of peroxidase. Different from previously reported fluorescent quenching phenomena, we found that MnO2 NS could not only largely quench the fluorescence of highly fluorescent Scopoletin (SC) but also surprisingly enhance that of nonfluorescent Amplex Red (AR) via oxidation reaction. If MnO2 NS is premixed with GSH, it will be reduced to Mn2+ and lose the oxidase-like property, accompanied by subsequent increase in SC's fluorescence and decrease in AR's. On the basis of the above mechanism, we construct the first MnO2 NS-based ratiometric fluorescent sensor for ultrasensitive and selective detection of GSH. Notably, this ratiometric sensor is programmed by the cascade logic circuit (an INHIBIT gate cascade with a 1 to 2 decoder). And a linear relationship between ratiometric fluorescent intensities of the two substrates and logarithmic values of GSH's concentrations is obtained. The detection limit of GSH is as low as 6.7 nM, which is much lower than previous ratiometric fluorescent sensors, and the lowest MnO2 NS-based fluorescent GSH sensor reported so far. Furthermore, this sensor is simple, label-free, and low-cost; it also presents excellent applicability in human serum samples.
Construction of a reconfigurable dynamic logic cell
Indian Academy of Sciences (India)
Nonlinear circuits; logic gates; computer architecture. PACS No. 05.45.+b. 1. Introduction. Recently there has been a new theoretical direction in harnessing the richness of chaos, namely the exploitation of chaos to do flexible computations [1,2]. The aim is to use a single chaotic element to emulate different logic gates and ...
Towards Logical Designs In Biology
Indian Academy of Sciences (India)
Administrator
This article highlights an emerging field known as syn- thetic biology that envisions integrating designed circuits into living organisms in order to instruct them to make logical decisions based on the prevailing intracellular and extracellular conditions and produce a reliable behavior. The attempt is to design cells capable of ...
Introduction to logic circuits & logic design with VHDL
LaMeres, Brock J
2017-01-01
This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion...
Introduction to logic circuits & logic design with verilog
LaMeres, Brock J
2017-01-01
This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on ...
DEFF Research Database (Denmark)
Braüner, Torben
2011-01-01
Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....
Adaptive parallel logic networks
Martinez, Tony R.; Vidal, Jacques J.
1988-01-01
Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.
CMOS digital integrated circuits a first course
Hawkins, Charles; Zarkesh-Ha, Payman
2016-01-01
This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.
Classical Logic and Quantum Logic with Multiple and Common Lattice Models
Directory of Open Access Journals (Sweden)
Mladen Pavičić
2016-01-01
Full Text Available We consider a proper propositional quantum logic and show that it has multiple disjoint lattice models, only one of which is an orthomodular lattice (algebra underlying Hilbert (quantum space. We give an equivalent proof for the classical logic which turns out to have disjoint distributive and nondistributive ortholattices. In particular, we prove that both classical logic and quantum logic are sound and complete with respect to each of these lattices. We also show that there is one common nonorthomodular lattice that is a model of both quantum and classical logic. In technical terms, that enables us to run the same classical logic on both a digital (standard, two-subset, 0-1-bit computer and a nondigital (say, a six-subset computer (with appropriate chips and circuits. With quantum logic, the same six-element common lattice can serve us as a benchmark for an efficient evaluation of equations of bigger lattice models or theorems of the logic.
Directory of Open Access Journals (Sweden)
Otávio Bueno
2001-12-01
Full Text Available In this paper, I develop a new defense of logicism: one that combines logicism and nominalism. First, I defend the logicist approach from recent criticisms; in particular from the charge that a crucial principle in the logicist reconstruction of arithmetic, Hume's Principle, is not analytic. In order to do that, I argue, it is crucial to understand the overall logicist approach as a nominalist view. I then indicate a way of extending the nominalist logicist approach beyond arithmetic. Finally, I argue that nominalist can use the resulting approach to provide a nominalization strategy for mathematics. In this way, mathematical structures can be introduced without ontological costs. And so, if this proposal is correct, we can say that ultimately all the nominalist needs is logic (and, rather loosely, all the logicist needs is nominalism.
Genetic Synthesis of New Reversible/Quantum Ternary Comparator
Directory of Open Access Journals (Sweden)
DEIBUK, V.
2015-08-01
Full Text Available Methods of quantum/reversible logic synthesis are based on the use of the binary nature of quantum computing. However, multiple-valued logic is a promising choice for future quantum computer technology due to a number of advantages over binary circuits. In this paper we have developed a synthesis of ternary reversible circuits based on Muthukrishnan-Stroud gates using a genetic algorithm. The method of coding chromosome is presented, and well-grounded choice of algorithm parameters allowed obtaining better circuit schemes of one- and n-qutrit ternary comparators compared with other methods. These parameters are quantum cost of received reversible devices, delay time and number of constant input (ancilla lines. Proposed implementation of the genetic algorithm has led to reducing of the device delay time and the number of ancilla qutrits to 1 and 2n-1 for one- and n-qutrits full comparators, respectively. For designing of n-qutrit comparator we have introduced a complementary device which compares output functions of 1-qutrit comparators.
Reconfigurable Optical Directed-Logic Circuits
2015-11-20
and V. G. Oklobdzija,Microelectr J 31, 991- 998 (2000). 5. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, Nature 435, 325-327 (2005). 6. P. Dong, S. R...Biberman, and K. Bergman, Rep Prog Phys 75 (2012). 11. R. A. Soref, and B. R. Bennett, Ieee J Quantum Elect 23, 123-129 (1987). 12. F. Monifi, J. Friedlein...2006). 14. Y. Akazawa, N. Ishihara, T. Wakimoto, K. Kawarada, and S. Konaka, Ieee J Solid-St Circ 21, 417-423 (1986). 15. X. Chi, W. H. P
DEFF Research Database (Denmark)
Reynolds, John C.
2002-01-01
In joint work with Peter O'Hearn and others, based on early ideas of Burstall, we have developed an extension of Hoare logic that permits reasoning about low-level imperative programs that use shared mutable data structure. The simple imperative programming language is extended with commands (not...
Single molecule logical devices.
Renaud, Nicolas; Hliwa, Mohamed; Joachim, Christian
2012-01-01
After almost 40 years of development, molecular electronics has given birth to many exciting ideas that range from molecular wires to molecular qubit-based quantum computers. This chapter reviews our efforts to answer a simple question: how smart can a single molecule be? In our case a molecule able to perform a simple Boolean function is a child prodigy. Following the Aviram and Ratner approach, these molecules are inserted between several conducting electrodes. The electronic conduction of the resulting molecular junction is extremely sensitive to the chemical nature of the molecule. Therefore designing this latter correctly allows the implementation of a given function inside the molecular junction. Throughout the chapter different approaches are reviewed, from hybrid devices to quantum molecular logic gates. We particularly stress that one can implement an entire logic circuit in a single molecule, using either classical-like intramolecular connections, or a deformation of the molecular orbitals induced by a conformational change of the molecule. These approaches are radically different from the hybrid-device approach, where several molecules are connected together to build the circuit.
Electronic circuits fundamentals & applications
Tooley, Mike
2015-01-01
Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The
2014-01-01
congruence of bi-implication induced on the local word algebras by the local logics. The only operators not already covered in previous modal algebraic...above the local modal algebra carrier sets are necessary. Lemma 2.4.7 shows that the replacement property for the bi-implication congruence holds for...and J. Rosicky, “Locally Presentable and Accessible Categories,” London Mathe - matical Society, 1994, lecture Note Series 189. [2] Allwein, G. and J
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing
Wave Pipelining Using Self Reset Logic
Directory of Open Access Journals (Sweden)
Miguel E. Litvin
2008-01-01
Full Text Available This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations. To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID. These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT. These properties simplify the implementation of wave pipelined circuits. General timing analysis is provided and compared with previous implementations. Results of circuit implementation are presented together with conclusions and future work.
Matsumoto, Raymond T. (Inventor); Higashi, Stanley T. (Inventor)
1976-01-01
A driver circuit which has low power requirements, a relatively small number of components and provides flexibility in output voltage setting. The driver circuit comprises, essentially, two portions which are selectively activated by the application of input signals. The output signal is determined by which of the two circuit portions is activated. While each of the two circuit portions operates in a manner similar to silicon controlled rectifiers (SCR), the circuit portions are on only when an input signal is supplied thereto.
Bilayer avalanche spin-diode logic
Energy Technology Data Exchange (ETDEWEB)
Friedman, Joseph S., E-mail: joseph.friedman@u-psud.fr; Querlioz, Damien [Institut d’Electronique Fondamentale, Univ. Paris-Sud, CNRS, 91405 Orsay (France); Fadel, Eric R. [Department of Materials Science, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Wessels, Bruce W. [Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL 60208 (United States); Department of Materials Science & Engineering, Northwestern University, Evanston, IL 60208 (United States); Sahakian, Alan V. [Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL 60208 (United States); Department of Biomedical Engineering, Northwestern University, Evanston, IL 60208 (United States)
2015-11-15
A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.
Noise-aided logic in an electronic analog of synthetic genetic networks.
Hellen, Edward H; Dana, Syamal K; Kurths, Jürgen; Kehler, Elizabeth; Sinha, Sudeshna
2013-01-01
We report the experimental verification of noise-enhanced logic behaviour in an electronic analog of a synthetic genetic network, composed of two repressors and two constitutive promoters. We observe good agreement between circuit measurements and numerical prediction, with the circuit allowing for robust logic operations in an optimal window of noise. Namely, the input-output characteristics of a logic gate is reproduced faithfully under moderate noise, which is a manifestation of the phenomenon known as Logical Stochastic Resonance. The two dynamical variables in the system yield complementary logic behaviour simultaneously. The system is easily morphed from AND/NAND to OR/NOR logic.
DEFF Research Database (Denmark)
is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...
Gate-Controlled BP-WSe2Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.
Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing
2017-06-01
p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe 2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe 2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe 2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
General Decomposition and Its Use in Digital Circuit Synthesis
Jóźwiak, Lech
1995-01-01
Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circui...
Energy Technology Data Exchange (ETDEWEB)
Celestino M, E.
2016-07-01
The Instituto Nacional de Investigaciones Nucleares (ININ) in Mexico has a nuclear reactor type TRIGA Mark III, which was put into operation in 1968. The reactor is used for staff training, radioisotope production, and for research projects of different areas. Over time and due to advances constantly has the electronics industry, maintenance of electronic systems is complicated because basically sometimes components that are no longer manufactured or no longer exist in the market, making it necessary to create projects required modernization. This is the case of the TRIGA reactor of ININ, so the Department of Automation and Instrumentation ININ is undertaking a new project to update the reactor control console. Systems that make up a nuclear reactor protection system (Ps) is relevant, since it is responsible for generating the necessary steps to shut down the reactor to an event of uncertainty which could affect the operators or the installation own actions. As part of the renovation project, this study design is presented to update the Logic of Action (La) of the Ps, whose final design must meet the requirements or specifications set by users and or regulations applicable to nuclear research reactors. One of the requirements established for the proposed new design La, is that it must be implemented with components and devices manufactured with latest technologies, and readily available on the market. The design which is operating currently uses TTL logic whose components are no longer available in the market, so for the new design you decide to use programmable circuits, and specifically, the CPLDs called (by the acronym Complex Programmable Logic Device). These CPLDs are electronic devices that solve complex logic equations and meeting the requirements of functionality and modernity for the new design of the La. In this work the criteria used for the selection of the CPLDs considering the availability and ease of software and hardware to use, and the design and
Development of CMOS integrated circuits
Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.
1979-01-01
Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.
Adiabatic logic future trend and system level perspective
Teichmann, Philip
2012-01-01
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the p...
Doberkat, Ernst-Erich
2009-01-01
Combining coalgebraic reasoning, stochastic systems and logic, this volume presents the principles of coalgebraic logic from a categorical perspective. Modal logics are also discussed, including probabilistic interpretations and an analysis of Kripke models.
Man-machine interactive system simplifies computer-aided circuit design
Bavuso, S. J.
1970-01-01
Langley interactive computerized circuit analysis capability /LICCA/ enables designer to draw electronic circuit diagrams on cathode ray tube screen. This information is submitted as input to user-selected circuit analysis program. LICCA accommodates binary logic circuits and circuits with discrete components, and monitors operator's instructions to detect errors.
Paraconsistent Computational Logic
DEFF Research Database (Denmark)
Jensen, Andreas Schmidt; Villadsen, Jørgen
2012-01-01
In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study.......In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study....
Logic programming extensions of Horn clause logic
Directory of Open Access Journals (Sweden)
Ron Sigal
1988-11-01
Full Text Available Logic programming is now firmly established as an alternative programming paradigm, distinct and arguably superior to the still dominant imperative style of, for instance, the Algol family of languages. The concept of a logic programming language is not precisely defined, but it is generally understood to be characterized buy: a declarative nature; foundation in some well understood logical system, e.g., first order logic.
Three-valued logics in modal logic
Kooi, Barteld; Tamminga, Allard
2013-01-01
Every truth-functional three-valued propositional logic can be conservatively translated into the modal logic S5. We prove this claim constructively in two steps. First, we define a Translation Manual that converts any propositional formula of any three-valued logic into a modal formula. Second, we
A reconfigurable NAND/NOR genetic logic gate
Directory of Open Access Journals (Sweden)
Goñi-Moreno Angel
2012-09-01
Full Text Available Abstract Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a varying the meanings of inputs, and b using branch predictions (as in computer science to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.
A reconfigurable NAND/NOR genetic logic gate.
Goñi-Moreno, Angel; Amos, Martyn
2012-09-18
Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.
Hybrid Techniques for Quantum Circuit Simulation
2014-02-01
manufacture, use, or sell any patented invention that may relate to them. This report was cleared for public release by the 88th ABW, Wright-Patterson AFB...that, for any unitary stabilizer circuit, there exists an equivalent block-structured canonical circuit that applies a block of Hadamard (H) gates...operation, we map it to a conventional logic circuit that processes the SNs in an appropriate way. A quantum gate G corresponds to a 2n × 2n unitary
Dual Interlocked Logic for Single-Event Transient Mitigation
2017-03-01
tolerate SETs of any pulse width and incurs no additional delay when compared to the traditional cascode voltage switch logic family . The concepts...vanderbilt.edu Abstract: A novel combinational logic family incorporating interlocked feedback with cascode voltage switch logic has been developed and...CVSL circuit family and a RHBD technique using interlocked feedback, similar to dual interlocked storage cell (DICE) latches, to develop a new
An Initialization Technique for the Waveform-Relaxation Circuit Simulation
Habib, S. E.-D.; Al-Karim, G. J.
1999-01-01
This paper reports the development of the Cairo University Waveform Relaxation (CUWORX) simulator. In order to accelerate the convergence of the waveform relaxation (WR) in the presence of logic feedback, CUWORK is initialized via a logic simulator. This logic initialization scheme is shown to be highly effective for digital synchronous circuits. Additionally, this logic initialization scheme preserves fully the multi-rate properties of the WR algorithm.
Construction of a reconfigurable dynamic logic cell
Indian Academy of Sciences (India)
Abstract. We report the first experimental realization of all the fundamental logic gates, flexibly, using a chaotic circuit. In our scheme a simple threshold mechanism allows the chaotic unit to switch easily between behaviours emulating the different gates. We also demonstrate the combination of gates through a half-adder ...
Electronics circuits and systems
Bishop, Owen
2007-01-01
The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set
Electronics circuits and systems
Bishop, Owen
2011-01-01
The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea
Digital Optical Circuit Technology
Dove, B. L. (Editor)
1985-01-01
The Proceedings for the 48th Meeting of the AGARD Avionics Panel contain the 18 papers presented a Technical Evaluation Report, and discussions that followed the presentations of papers. Seven papers were presented in the session devoted to optical bistability. Optical logic was addressed by three papers. The session on sources, modulators and demodulators presented three papers. Five papers were given in the final session on all optical systems. The purpose of this Specialists' Meeting was to present the research and development status of digital optical circuit technology and to examine its relevance in the broad context of digital processing, communication, radar, avionics and flight control systems implementation.
Combinational Logic-Level Verification using Boolean Expression Diagrams
DEFF Research Database (Denmark)
Hulgaard, Henrik; Williams, Poul Frederick; Andersen, Henrik Reif
1997-01-01
of BDDs. This paper demonstrates that BEDs are well suited for solving the combinational logic-level verification problem which is, given two combinational circuits, to determine whether they implement the same Boolean functions. Based on all combinational circuits in the ISCAS 85 and LGSynth 91...
Metamathematics of fuzzy logic
Hájek, Petr
1998-01-01
This book presents a systematic treatment of deductive aspects and structures of fuzzy logic understood as many valued logic sui generis. Some important systems of real-valued propositional and predicate calculus are defined and investigated. The aim is to show that fuzzy logic as a logic of imprecise (vague) propositions does have well-developed formal foundations and that most things usually named `fuzzy inference' can be naturally understood as logical deduction.
Stephen Crain; Drew Khlentzos
2007-01-01
Arguments are presented supporting logical nativism: the conjecture that humans have an innate logic faculty. In making a case for logical nativism, this article concentrates on children’s acquisition of the logical concept of disjunction. Despite the widespread belief to the contrary, the interpretation of disjunction in human languages is arguably the same as it is in classical logic, namely inclusive–or. The argument proceeds with empirical support for the view that the inclusive–or is the...
New data structures and algorithms for logic synthesis and verification
Amaru, Luca Gaetano
2017-01-01
This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines. · Provides a comprehensive, theoretical study on majority and biconditional logic for logic synthesis; · Updates the current scenario in synthesis and verification – especially in light of emerging technologies; · Demonstrates applications to CMOS technology and emerging technologies.
Noise-aided Logic in an Electronic Analog of Synthetic Genetic Networks
Hellen, Edward H; Kurths, Jurgen; Sinha, Sudeshna
2012-01-01
We report the experimental verification of noise-enhanced logic behaviour in an electronic analog of a synthetic genetic network, composed of two repressors and two constructive promoters. We observe good agreement between circuit measurements and numerical prediction, with the circuit allowing for robust logic operations in an optimal window of noise. Namely, the input-output characteristics of a logic gate is reproduced faithfully under moderate noise, which is a manifestation of the phenomenon known as Logical Stochastic Resonance. Interestingly, the two dynamical variables in the system yield complementary logic behaviour simultaneously, indicating strong potential for parallel processing.
A Review on Energy Efficient CMOS Digital Logic
Directory of Open Access Journals (Sweden)
B. L. Dokic
2013-12-01
Full Text Available Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt and power supply voltage (Vdd on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL, complementary pass logic (CPL, push-pull pass logic (PPL and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.
A circuit design for multi-inputs stateful OR gate
Energy Technology Data Exchange (ETDEWEB)
Chen, Qiao; Wang, Xiaoping, E-mail: wangxiaoping@hust.edu.cn; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-09-07
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
DEFF Research Database (Denmark)
Berg Johansen, Christina; Waldorff, Susanne Boch
This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...
Indeterministic Temporal Logic
Directory of Open Access Journals (Sweden)
Trzęsicki Kazimierz
2015-09-01
Full Text Available The questions od determinism, causality, and freedom have been the main philosophical problems debated since the beginning of temporal logic. The issue of the logical value of sentences about the future was stated by Aristotle in the famous tomorrow sea-battle passage. The question has inspired Łukasiewicz’s idea of many-valued logics and was a motive of A. N. Prior’s considerations about the logic of tenses. In the scheme of temporal logic there are different solutions to the problem. In the paper we consider indeterministic temporal logic based on the idea of temporal worlds and the relation of accessibility between them.
Many-valued Logic and Fuzzy Logic
Czech Academy of Sciences Publication Activity Database
Hájek, Petr
2011-01-01
Roč. 27, č. 2 (2011), s. 315-324 ISSN 0970-7794 R&D Projects: GA ČR GEICC/08/E018 Institutional research plan: CEZ:AV0Z10300504 Keywords : many valued logic * fuzzy logic Subject RIV: BA - General Mathematics
Quantum logic as a dynamic logic
Baltag, Alexandru; Smets, Sonja
We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear "no".
Universal programmable logic gate and routing method
Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)
2009-01-01
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Shalack, V.
2013-01-01
The article offers a look at the combinatorial logic as the logic of signs operating in the most general sense. For this it is proposed slightly reformulate it in terms of introducing and replacement of the definitions.
Bolc, Leonard
1992-01-01
Many-valued logics were developed as an attempt to handle philosophical doubts about the "law of excluded middle" in classical logic. The first many-valued formal systems were developed by J. Lukasiewicz in Poland and E.Post in the U.S.A. in the 1920s, and since then the field has expanded dramatically as the applicability of the systems to other philosophical and semantic problems was recognized. Intuitionisticlogic, for example, arose from deep problems in the foundations of mathematics. Fuzzy logics, approximation logics, and probability logics all address questions that classical logic alone cannot answer. All these interpretations of many-valued calculi motivate specific formal systems thatallow detailed mathematical treatment. In this volume, the authors are concerned with finite-valued logics, and especially with three-valued logical calculi. Matrix constructions, axiomatizations of propositional and predicate calculi, syntax, semantic structures, and methodology are discussed. Separate chapters deal w...
Fuzzy logic controller optimization
Sepe, Jr., Raymond B; Miller, John Michael
2004-03-23
A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.
Newton-Smith, WH
2003-01-01
A complete introduction to logic for first-year university students with no background in logic, philosophy or mathematics. In easily understood steps it shows the mechanics of the formal analysis of arguments.
Inductive Temporal Logic Programming
Kolter, Robert
2009-01-01
We study the extension of techniques from Inductive Logic Programming (ILP) to temporal logic programming languages. Therefore we present two temporal logic programming languages and analyse the learnability of programs from these languages from finite sets of examples. In first order temporal logic the following topics are analysed: - How can we characterize the denotational semantics of programs? - Which proof techniques are best suited? - How complex is the learning task? In propositional ...
Institutional Logics in Action
DEFF Research Database (Denmark)
Lounsbury, Michael; Boxenbaum, Eva
2013-01-01
This double volume presents state-of-the-art research and thinking on the dynamics of actors and institutional logics. In the introduction, we briefly sketch the roots and branches of institutional logics scholarship before turning to the new buds of research on the topic of how actors engage ins...... prolific stream of research on institutional logics by deepening our insight into the active use of institutional logics in organizational action and interaction, including the institutional effects of such (inter)actions....
Design of a Ferroelectric Programmable Logic Gate Array
MacLeod, Todd C.; Ho, Fat Duen
2003-01-01
A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.
Indian Academy of Sciences (India)
andoh
input signals, consisting of random square waves. We find that, in an optimal band of noise, the output consistently is a logical combination of the input signals: Logical Stochastic Resonance. (LSR) with K. Murali, W.L. Ditto, A. Bulsara. Physical Review Letters, March 2009. Sudeshna Sinha. Logical Stochastic Resonance ...
Ciardelli, I.A.
2016-01-01
This dissertation pursues two tightly interwoven goals: to bring out the relevance of questions for the field of logic, and to establish a solid theory of the logic of questions within a classical logical setting. These enterprises feed into each other: on the one hand, the development of our formal
Nonintrusive System for Replication of interlayer Printed Circuit Patterns
National Research Council Canada - National Science Library
Chai, M
1998-01-01
... verified the feasibility of reverse engineering the circuit board. An algorithm using 2-D projection and Compton scattering data was proposed for image reconstruction of the layout of the printed circuit board, layer by layer...
A novel, efficient CNTFET Galois design as a basic ternary-valued logic field.
Keshavarzian, Peiman; Mirzaee, Mahla Mohammad
2012-01-01
This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption.
Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices
Directory of Open Access Journals (Sweden)
Tautvydas Brukštus
2016-06-01
Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.
Directory of Open Access Journals (Sweden)
Stephen Crain
2007-12-01
Full Text Available Arguments are presented supporting logical nativism: the conjecture that humans have an innate logic faculty. In making a case for logical nativism, this article concentrates on children’s acquisition of the logical concept of disjunction. Despite the widespread belief to the contrary, the interpretation of disjunction in human languages is arguably the same as it is in classical logic, namely inclusive–or. The argument proceeds with empirical support for the view that the inclusive–or is the meaning of disjunction in human languages, from studies of child language development and from cross-linguistic research. Evidence is presented showing that young children adhere to universal semantic principles that characterize adult linguistic competence across languages. Several a priori arguments are also offered in favour of logical nativism. These arguments show that logic, like Socratic virtue and like certain aspects of language, is not learned and cannot be taught — thus supporting a strong form of innateness.
Logic gates based on ion transistors.
Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus
2012-05-29
Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.
Supply Voltage Glitches Effects on CMOS Circuits
Djellid-Ouar, Anissa; Cathébras, Guy; Bancel, Frédéric
2006-01-01
International audience; Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers. . . ) ...
Integrated-Circuit Controller For Brushless dc Motor
Le, Dong Tuan
1994-01-01
Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.
Reliability concerns with logical constants in Xilinx FPGA designs
Energy Technology Data Exchange (ETDEWEB)
Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX
2009-01-01
In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.
Dalen, Dirk
1983-01-01
A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...
Directory of Open Access Journals (Sweden)
Schang Fabien
2017-03-01
Full Text Available An analogy is made between two rather different domains, namely: logic, and football (or soccer. Starting from a comparative table between the two activities, an alternative explanation of logic is given in terms of players, ball, goal, and the like. Our main thesis is that, just as the task of logic is preserving truth from premises to the conclusion, footballers strive to keep the ball as far as possible until the opposite goal. Assuming this analogy may help think about logic in the same way as in dialogical logic, but it should also present truth-values in an alternative sense of speech-acts occurring in a dialogue. The relativity of truth-values is focused by this way, thereby leading to an additional way of logical pluralism.
Digital Microfluidic Logic Gates
Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu
Microfluidic computing is an emerging application for microfluidics technology. We propose microfluidic logic gates based on digital microfluidics. Using the principle of electrowetting-on-dielectric, AND, OR, NOT and XOR gates are implemented through basic droplet-handling operations such as transporting, merging and splitting. The same input-output interpretation enables the cascading of gates to create nontrivial computing systems. We present a potential application for microfluidic logic gates by implementing microfluidic logic operations for on-chip HIV test.
Logical database design principles
Garmany, John; Clark, Terry
2005-01-01
INTRODUCTION TO LOGICAL DATABASE DESIGNUnderstanding a Database Database Architectures Relational Databases Creating the Database System Development Life Cycle (SDLC)Systems Planning: Assessment and Feasibility System Analysis: RequirementsSystem Analysis: Requirements Checklist Models Tracking and Schedules Design Modeling Functional Decomposition DiagramData Flow Diagrams Data Dictionary Logical Structures and Decision Trees System Design: LogicalSYSTEM DESIGN AND IMPLEMENTATION The ER ApproachEntities and Entity Types Attribute Domains AttributesSet-Valued AttributesWeak Entities Constraint
Du Fresne, E. R.; Dowler, W. L.
1985-01-01
Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.
DEFF Research Database (Denmark)
Blackburn, Patrick Rowan; Jørgensen, Klaus Frovin
2012-01-01
In this paper we explore the logic of now, yesterday, today and tomorrow by combining the semantic approach to indexicality pioneered by Hans Kamp [9] and refined by David Kaplan [10] with hybrid tense logic. We first introduce a special now nominal (our @now corresponds to Kamp’s original now...... operator N) and prove completeness results for both logical and contextual validity. We then add propositional constants to handle yesterday, today and tomorrow; our system correctly treats sentences like “Niels will die yesterday” as contextually unsatisfiable. Building on our completeness results for now......, we prove completeness for the richer language, again for both logical and contextual validity....
Howard, Ayanna
2005-01-01
The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.
Introduction to mathematical logic
Mendelson, Elliott
2015-01-01
The new edition of this classic textbook, Introduction to Mathematical Logic, Sixth Edition explores the principal topics of mathematical logic. It covers propositional logic, first-order logic, first-order number theory, axiomatic set theory, and the theory of computability. The text also discusses the major results of Gödel, Church, Kleene, Rosser, and Turing.The sixth edition incorporates recent work on Gödel's second incompleteness theorem as well as restoring an appendix on consistency proofs for first-order arithmetic. This appendix last appeared in the first edition. It is offered in th
DEFF Research Database (Denmark)
Jensen, Jonas Buhrkal; Birkedal, Lars
2012-01-01
, separation means physical separation. In this paper, we introduce \\emph{fictional separation logic}, which includes more general forms of fictional separating conjunctions P * Q, where "*" does not require physical separation, but may also be used in situations where the memory resources described by P and Q...... overlap. We demonstrate, via a range of examples, how fictional separation logic can be used to reason locally and modularly about mutable abstract data types, possibly implemented using sophisticated sharing. Fictional separation logic is defined on top of standard separation logic, and both the meta...
Crossley, J N; Brickhill, CJ; Stillwell, JC
2010-01-01
Although mathematical logic can be a formidably abstruse topic, even for mathematicians, this concise book presents the subject in a lively and approachable fashion. It deals with the very important ideas in modern mathematical logic without the detailed mathematical work required of those with a professional interest in logic.The book begins with a historical survey of the development of mathematical logic from two parallel streams: formal deduction, which originated with Aristotle, Euclid, and others; and mathematical analysis, which dates back to Archimedes in the same era. The streams beg
DEFF Research Database (Denmark)
Klose, Karl; Ostermann, Klaus
2010-01-01
In logic metaprogramming, programs are not stored as plain textfiles but rather derived from a deductive database. While the benefits of this approach for metaprogramming are obvious, its incompatibility with separate checking limits its applicability to large-scale projects. We analyze...... the problems inhibiting separate checking and propose a class of logics that reconcile logic metaprogramming and separate checking. We have formalized the resulting module system and have proven the soundness of separate checking. We validate its feasibility by presenting the design and implementation...... of a specific logic that is able to express many metaprogramming examples from the literature....
DEFF Research Database (Denmark)
Lopez, Hugo Andres; Carbone, Marco; Hildebrandt, Thomas
2010-01-01
We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for speciﬁcation and veriﬁcation of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL...... ), a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service speciﬁcations. Finally, we show that, despite GL is undecidable, there is a signiﬁcant decidable fragment which we provide with a sound and complete proof...
Design of reconfigurable logic controllers
Bukowiec, Arkadiusz; Doligalski, Michał; Tkacz, Jacek
2016-01-01
This book presents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the recon...
Digital Pulse-Width-Modulation Circuit
Wenzler, Carl J.; Eichenberg, Dennis J.
1995-01-01
Digital pulse-width-modulation circuit provides programmable duration from 1 microsecond to full on, at repetition rate of 1 kHz. Designed for use in controlling CO2 laser, also used in applications in which precision and flexibility of digital control of pulse durations needed. Circuit incorporates low-power Schottky transistor/transistor-logic (TTL) devices in critical high-speed parts. Designed in TTL to make it compatible with Pro-Log 7914 (or equivalent) decoder input/output (I/O) utility printed-circuit card.
Photonic encryption using all optical logic.
Energy Technology Data Exchange (ETDEWEB)
Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George
2003-12-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and
Towards a Formal Occurrence Logic based on Predicate Logic
DEFF Research Database (Denmark)
Badie, Farshad; Götzsche, Hans
2015-01-01
argumentation based on formal Occurrence Logic concerning events and occurrences, and illustrate the relations between Predicate Logic and Occurrence Logic. The relationships (and dependencies) is conducive to an approach that can analyse the occurrences of ”logical statements based on different logical...
Modeling a verification test system for mixed-signal circuits
San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.
In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block
Test results for SEU and SEL immune memory circuits
Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.
1993-01-01
Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
Computer circuit will fit on single silicon chip
Smith, C.
1964-01-01
A simplified computer logic circuit of two NAND/NOR gates and three additional inputs to accomplish the count and shift function is described. The circuit has capacity for parallel read-in, counting, serial shiftout, complement input and set and reset.
Design Techniques for Power-Aware Combinational Logic SER Mitigation
Mahatme, Nihaar N.
The history of modern semiconductor devices and circuits suggests that technologists have been able to maintain scaling at the rate predicted by Moore's Law [Moor-65]. With improved performance, speed and lower area, technology scaling has also exacerbated reliability issues such as soft errors. Soft errors are transient errors that occur in microelectronic circuits due to ionizing radiation particle strikes on reverse biased semiconductor junctions. These radiation induced errors at the terrestrial-level are caused due to radiation particle strikes by (1) alpha particles emitted as decay products of packing material (2) cosmic rays that produce energetic protons and neutrons, and (3) thermal neutrons [Dodd-03], [Srou-88] and more recently muons and electrons [Ma-79] [Nara-08] [Siew-10] [King-10]. In the space environment radiation induced errors are a much bigger threat and are mainly caused by cosmic heavy-ions, protons etc. The effects of radiation exposure on circuits and measures to protect against them have been studied extensively for the past 40 years, especially for parts operating in space. Radiation particle strikes can affect memory as well as combinational logic. Typically when these particles strike semiconductor junctions of transistors that are part of feedback structures such as SRAM memory cells or flip-flops, it can lead to an inversion of the cell content. Such a failure is formally called a bit-flip or single-event upset (SEU). When such particles strike sensitive junctions part of combinational logic gates they produce transient voltage spikes or glitches called single-event transients (SETs) that could be latched by receiving flip-flops. As the circuits are clocked faster, there are more number of clocking edges which increases the likelihood of latching these transients. In older technology generations the probability of errors in flip-flops due to SETs being latched was much lower compared to direct strikes on flip-flops or SRAMs leading to
E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion
Directory of Open Access Journals (Sweden)
Qutaiba Alasad
2017-02-01
Full Text Available Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX with two cases: (i we randomly insert MUXs equal to half of the output bit number (half MUX insertions; and (ii we insert MUXs equal to the number of output bits (full MUX insertions. Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique.
Three-Function Logic Gate Controlled by Analog Voltage
Zebulum, Ricardo; Stoica, Adrian
2006-01-01
The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If
Understanding Social Media Logic
Directory of Open Access Journals (Sweden)
José van Dijck
2013-08-01
Full Text Available Over the past decade, social media platforms have penetrated deeply into the mechanics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpinning its dynamics. This logic will be considered in light of what has been identified as mass media logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmability, popularity, connectivity, and datafication—and argue that these principles become increasingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance existing mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relatively simple to identify, but it is much harder to map the complex connections between platforms that distribute this logic: users that employ them, technologies that
Domino logic designs for high-performance and leakage-tolerant applications
DEFF Research Database (Denmark)
Moradi, Farshad; Vu Cao, Tuan; Vatajelu, Elena Ioana
2013-01-01
by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been......Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved...
A. Ponse (Alban); M.B. van der Zwaag
2002-01-01
textabstractWe distinguish two interpretations for the truth value `undefined' in Kleene's three-valued logic. Combining these two interpretations leads to a four-valued propositional logic that characterizes two particular ingredients of process algebra: ``choice' and ``inaction'. We study two
Directory of Open Access Journals (Sweden)
Evandro Agazzi
2011-06-01
Full Text Available Humans have used arguments for defending or refuting statements long before the creation of logic as a specialized discipline. This can be interpreted as the fact that an intuitive notion of "logical consequence" or a psychic disposition to articulate reasoning according to this pattern is present in common sense, and logic simply aims at describing and codifying the features of this spontaneous capacity of human reason. It is well known, however, that several arguments easily accepted by common sense are actually "logical fallacies", and this indicates that logic is not just a descriptive, but also a prescriptive or normative enterprise, in which the notion of logical consequence is defined in a precise way and then certain rules are established in order to maintain the discourse in keeping with this notion. Yet in the justification of the correctness and adequacy of these rules commonsense reasoning must necessarily be used, and in such a way its foundational role is recognized. Moreover, it remains also true that several branches and forms of logic have been elaborated precisely in order to reflect the structural features of correct argument used in different fields of human reasoning and yet insufficiently mirrored by the most familiar logical formalisms.
DEFF Research Database (Denmark)
Monica, Dario Della; Goranko, Valentin; Montanari, Angelo
2011-01-01
We discuss a family of modal logics for reasoning about relational structures of intervals over (usually) linear orders, with modal operators associated with the various binary relations between such intervals, known as Allen’s interval relations. The formulae of these logics are evaluated at int...
Lopez, Antonio M., Jr.
1989-01-01
Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)
NEVEN, Frank
2002-01-01
We survey some recent developments in the broad area of automata and logic which are motivated by the advent of XML. In particular, we consider unranked tree automata, tree-walking automata, and automata over infinite alphabets. We focus on their connection with logic and on questions imposed by XML.
CSIR Research Space (South Africa)
Klarman, S
2013-05-01
Full Text Available We introduce Description Logics of Context (DLCs) - an extension of Description Logics (DLs) for context-based reasoning. Our approach descends from J. McCarthy's tradition of treating contexts as formal objects over which one can quantify...
W. van der Hoek (Wiebe); J.O.M. Jaspars; E. Thijsse
1995-01-01
textabstractWe propose an epistemic logic in which knowledge is fully introspective and implies truth, although truth need not imply epistemic possibility. The logic is presented in sequential format and is interpreted in a natural class of partial models, called balloon models. We examine the
DEFF Research Database (Denmark)
Christiansen, Henning; Dahl, Veronica
2009-01-01
By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting...... the norm -- arbitrary (i.e., order-independent) derivations. We show that rich and accurate knowledge extraction from text can be achieved through the use of this new formalism......By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting....... We formalize these ideas, and exemplify them both within and outside first-order logic, and for both fixed and dynamic knowledge bases. Within the latter variety, we consider the usual left-to-right derivations that are traditional in logic grammars, but also -- in a significant departure from...
Reversible machine code and its abstract processor architecture
DEFF Research Database (Denmark)
Axelsen, Holger Bock; Glück, Robert; Yokoyama, Tetsuo
2007-01-01
A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building ...... on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper....
Heterogeneous logics of competition
DEFF Research Database (Denmark)
Mossin, Christiane
2015-01-01
The purpose of the article is to demonstrate that in order to understand competition as a socially organizing phenomenon, we should not examine competition in isolation, but as constellations of heterogeneous logics. More precisely, the article is based on two main theoretical points: (1) Logics...... of competition are only realized as particular forms of social organization by virtue of interplaying with other kinds of logics, like legal logics. (2) Competition logics enjoy a peculiar status in-between constructedness and givenness; although competition depends on laws and mechanisms of socialization, we...... still experience competition as an expression of spontaneous human activities. On the basis of these perspectives, a study of fundamental rights of EU law, springing from the principle of ‘free movement of people’, is conducted. The first part of the empirical analysis seeks to detect the presence...
Microelectromechanical reprogrammable logic device
Hafiz, Md Abdullah Al
2016-03-29
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.
Circuit for high resolution decoding of multi-anode microchannel array detectors
Kasle, David B. (Inventor)
1995-01-01
A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.
Reconfigurable Skyrmion Logic Gates.
Luo, Shijiang; Song, Min; Li, Xin; Zhang, Yue; Hong, Jeongmin; Yang, Xiaofei; Zou, Xuecheng; Xu, Nuo; You, Long
2018-02-14
Magnetic skyrmion, a nanosized spin texture with topological property, has become an area of significant interest due to the scientific insight that it can provide and also its potential impact on applications such as ultra-low-energy and ultra-high-density logic gates. In the quest for the reconfiguration of single logic device and the implementation of the complete logic functions, a novel reconfigurable skyrmion logic (RSL) is proposed and verified by micromagnetic simulations. Logic functions including AND, OR, NOT, NAND, NOR, XOR, and XNOR are implemented in the ferromagnetic (FM) nanotrack by virtue of various effects including spin orbit torque, skyrmion Hall effect, skyrmion-edge repulsions, and skyrmion-skyrmion collision. Different logic functions can be selected in an RSL by applying voltage to specific region(s) of the device, changing the local anisotropy energy of FM film. Material properties and geometrical scaling studies suggest RSL gates fit for energy-efficient computing as well as provide the guidelines for the design and optimization of this new logic family.
A Web-Based Visualization and Animation Platform for Digital Logic Design
Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.
2015-01-01
This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…
Logic in elementary mathematics
Exner, Robert M
2011-01-01
This applications-related introductory treatment explores facets of modern symbolic logic useful in the exposition of elementary mathematics. The authors convey the material in a manner accessible to those trained in standard elementary mathematics but lacking any formal background in logic. Topics include the statement calculus, proof and demonstration, abstract mathematical systems, and the restricted predicate calculus. The final chapter draws upon the methods of logical reasoning covered in previous chapters to develop solutions of linear and quadratic equations, definitions of order and
DEFF Research Database (Denmark)
Hendricks, Vincent Fella; Gierasimczuk, Nina; de Jong, Dick
2014-01-01
of information processing, but likewise helped bring logic and learning in close proximity. This proximity relation is examined with respect to learning and belief revision, updating and efficiency, and with respect to how learnability fits in the greater scheme of dynamic epistemic logic and scientific method.......Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study...
DEFF Research Database (Denmark)
Schürmann, Carsten; Sarnat, Jeffrey
2008-01-01
Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics, such as ......Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta...
DEFF Research Database (Denmark)
Filipiuk, Piotr; Nielson, Flemming; Nielson, Hanne Riis
2012-01-01
We present a logic for the specification of static analysis problems that goes beyond the logics traditionally used. Its most prominent feature is the direct support for both inductive computations of behaviors as well as co-inductive specifications of properties. Two main theoretical contributions...... are a Moore Family result and a parametrized worst case time complexity result. We show that the logic and the associated solver can be used for rapid prototyping of analyses and illustrate a wide variety of applications within Static Analysis, Constraint Satisfaction Problems and Model Checking. In all cases...
A Simple Memristor Model for Circuit Simulations
Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team
This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.
A single nano cantilever as a reprogrammable universal logic gate
Chappanda, K. N.; Ilyas, S.; Kazmi, S. N. R.; Holguin-Lerma, J.; Batra, N. M.; Costa, P. M. F. J.; Younis, M. I.
2017-04-01
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.
A single nano cantilever as a reprogrammable universal logic gate
Chappanda, K. N.
2017-02-24
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.
Gallium arsenide processing for gate array logic
Cole, Eric D.
1989-01-01
The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.
DEFF Research Database (Denmark)
to the intersecting streams of goods, people, ideas, and money as they circulate between African migrants and their kin who remain back home. They also show the complex ways that emotions become entangled in these exchanges. Examining how these circuits operate in domains of social life ranging from child fosterage...... to binational marriages, from coming-of-age to healing and religious rituals, the book also registers the tremendous impact of state officials, laws, and policies on migrant experience. Together these essays paint an especially vivid portrait of new forms of kinship at a time of both intense mobility and ever...
Nanoelectronic circuit design and test
Simsir, Muzaffer Orkun
address the above problem using device simulations and demonstrate that while fault models defined for CMOS show significant overlaps with those for double-gate CMOS, they are insufficient to encompass all regimes of operation. This implies that new fault models are needed to adequately capture the behavior of logic gates based on this new technology. Looking further into the future, simple extensions to CMOS will also reach scaling limitations and completely new technologies will be required to decrease the minimum feature size even further. Among many proposals, one-dimensional (1D) structures, especially nanowires, have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. It is expected that, initially, these technologies will coexist with CMOS. Therefore, researchers have been working on new architectures that integrate nanowires into CMOS. However, as the feature sizes get smaller, the fabrication process becomes defect-prone. Moreover, because of extreme device densities, it may not be possible to locate all defects. Hence, shipped chips may still be defective. Moreover, the devices in the nanometer range may be susceptible to transient faults which cause these circuits produce incorrect output values for a small period of time. Despite the above drawbacks, it is possible to make nanoscale architectures practical and realistic by introducing defect and fault tolerance. In this thesis, we propose and evaluate a hybrid nanowire-CMOS architecture that addresses all three problems---namely high defect rates, unlocated defects and transient faults---at the same time. This goal is achieved by using multiple levels of redundancy and majority voters. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. As the fabrication technology of nanowires evolves, it will be possible to build stand-alone nanowire-based circuits. Several small-sized stand
Henson, C Ward; Kechris, Alexander S; Odell, Edward; Finet, Catherine; Michaux, Christian; Cassels, J W S
2003-01-01
This volume comprises articles from four outstanding researchers who work at the cusp of analysis and logic. The emphasis is on active research topics; many results are presented that have not been published before and open problems are formulated.
Czech Academy of Sciences Publication Activity Database
Klev, Ansten
2017-01-01
Roč. 25, č. 3 (2017), s. 341-368 ISSN 0031-8019 Institutional support: RVO:67985955 Keywords : Philosophy of mathematics * logicism * Richard Dedekind Subject RIV: AA - Philosophy ; Religion Impact factor: 0.419, year: 2016
Levine, Shellie-helane; And Others
1986-01-01
Introduces questions and activities involving soap bubbles which provide students with experiences in prediction and logic. Examines commonly held false conceptions related to the shapes that bubbles take and provides correct explanations for the phenomenon. (ML)
DEFF Research Database (Denmark)
Friche, Nanna; Normann Andersen, Vibeke
and well-being of students enrolled in the VETs must be strengthened. We focus on target 1, 2 and 4. The reform is being implemented in a field of VET that can be characterized by four logics of governance. Firstly, a governance logic characterized by institutional independence of vocational colleges...... combined with state funding through a taximeter scheme (pay per student). Secondly, party governance system involving labor market partners at both national and local level formalized through a national Council for Vocational Training and 50 local trade committees as well as local education committees...... at each college. The third governance logic is based on a decentralized quality management system at each college. Each college has set up its own system of quality developments and quality assurances. The fourth governance logic is performance management conducted by the national level towards...
DNA computation in mammalian cells: microRNA logic operations.
Hemphill, James; Deiters, Alexander
2013-07-17
DNA computation can utilize logic gates as modules to create molecular computers with biological inputs. Modular circuits that recognize nucleic acid inputs through strand hybridization activate computation cascades to produce controlled outputs. This allows for the construction of synthetic circuits that can be interfaced with cellular environments. We have engineered oligonucleotide AND gates to respond to specific microRNA (miRNA) inputs in live mammalian cells. Both single and dual-sensing miRNA-based computation devices were synthesized for the cell-specific identification of endogenous miR-21 and miR-122. A logic gate response was observed with miRNA expression regulators, exhibiting molecular recognition of miRNA profile changes. Nucleic acid logic gates that are functional in a cellular environment and recognize endogenous inputs significantly expand the potential of DNA computation to monitor, image, and respond to cell-specific markers.
Yanushkevich, Svetlana N
2008-01-01
Preface Design Process and Technology Theory of logic design Analysis and synthesis Implementation technologies Predictable technologies Contemporary CAD of logic networks Number Systems Positional numbers Counting in a positional number system Basic arithmetic operations in various number systems Binary arithmetic Radix-complement representations Techniques for conversion of numbers in various radices Overflow Residue arithmetic Other binary codes Redundancy and reliability Graphical Data Structures Graphs in discrete devices and systems design Basic definitions T
Logic and declarative language
Downward, M
2004-01-01
Logic has acquired a reputation for difficulty, perhaps because many of the approaches adopted have been more suitable for mathematicians than computer scientists. This book shows that the subject is not inherently difficult and that the connections between logic and declarative language are straightforward. Many exercises have been included in the hope that these will lead to a much greater confidence in manual proofs, therefore leading to a greater confidence in automated proofs.
Logical Stochastic Optimization
Saad, Emad
2013-01-01
We present a logical framework to represent and reason about stochastic optimization problems based on probability answer set programming. This is established by allowing probability optimization aggregates, e.g., minimum and maximum in the language of probability answer set programming to allow minimization or maximization of some desired criteria under the probabilistic environments. We show the application of the proposed logical stochastic optimization framework under the probability answ...
DEFF Research Database (Denmark)
Nilsson, Jørgen Fischer
1999-01-01
Conceptual spaces have been proposed as topological or geometric means for establishing conceptual structures and models. This paper, after briey reviewing conceptual spaces, focusses on the relationship between conceptual spaces and logical concept languages with operations for combining concepts...... to form concepts. Speci cally is introduced an algebraic concept logic, for which conceptual spaces are installed as semantic domain as replacement for, or enrichment of, the traditional....
Strong Completeness for Markovian Logics
DEFF Research Database (Denmark)
Kozen, Dexter; Mardare, Radu Iulian; Panangaden, Prakash
2013-01-01
In this paper we present Hilbert-style axiomatizations for three logics for reasoning about continuous-space Markov processes (MPs): (i) a logic for MPs defined for probability distributions on measurable state spaces, (ii) a logic for MPs defined for sub-probability distributions and (iii) a logic...
Automatic design of digital synthetic gene circuits.
Directory of Open Access Journals (Sweden)
Mario A Marchisio
2011-02-01
Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.
Philosophical Foundations of Intuitionistic Logic
Directory of Open Access Journals (Sweden)
L Nabavi
2013-02-01
Full Text Available Intuitionistic logic, as a non-classical logic, encompasses the principles of logical reasoning which were used by L. E. J. Brouwer in developing his intuitionistic mathematics. Brouwer rejected the principle of the excluded middle on the basis of his philosophy. In his philosophical view, logic is the application of mathematics to the language of mathematics. In other words, logic studies the patterns that characterize valid inference. The resulting linguistic system of logic may be studied mathematically, even independently of the mathematical activities that it was originally abstracted from. In this paper, the philosophical basis of Brouwerâs view about Logic and Mathematics is explained.
Philosophical Foundations of Intuitionistic Logic
Directory of Open Access Journals (Sweden)
L Nabavi
2013-03-01
Full Text Available Intuitionistic logic, as a non-classical logic, encompasses the principles of logical reasoning which were used by L. E. J. Brouwer in developing his intuitionistic mathematics. Brouwer rejected the principle of the excluded middle on the basis of his philosophy. In his philosophical view, logic is the application of mathematics to the language of mathematics. In other words, logic studies the patterns that characterize valid inference. The resulting linguistic system of logic may be studied mathematically, even independently of the mathematical activities that it was originally abstracted from. In this paper, the philosophical basis of Brouwer’s view about Logic and Mathematics is explained.
DEFF Research Database (Denmark)
2010-01-01
signal. The control unit comprises a first signal processing unit, a second signal processing unit, and a combiner unit. The first signal processing unit has an output and is supplied with a first carrier signal and an input signal. The second signal processing unit has an output and is supplied...... with a second carrier signal and the input signal. The combiner unit is connected to the first and second signal processing units combining the outputs of the first and the second signal processing units to form a signal representative of the control signal......A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...
Genetic programs constructed from layered logic gates in single cells.
Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C; Voigt, Christopher A
2012-11-08
Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator-chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells.
Stacked resistive switches for AND/OR logic gates
Kim, Myung Ju; Son, Kyung Rock; Park, Ju Hyun; Kim, Tae Geun
2017-06-01
This paper reports the use of stacked resistive switches as logic gates for implementing the ;AND; and ;OR; operations. These stacked resistive switches consist of two resistive switches that share a middle electrode, and they operate based on the difference in resistance between the low and high resistance states indicating the logical states of ;0; and ;1;, respectively. The stacked resistive switches can perform either AND or OR operation, using two read schemes in one device. To perform the AND (or OR) operation, two resistive switches are arranged in a serial (or parallel) connection. AND and OR operations have been successfully demonstrated using the stacked resistive switches. The use of stacked resistive switches as logic gates that utilize the advantages of memristive devices shows the possibility of stateful logic circuits.
Cascaded spintronic logic with low-dimensional carbon
Friedman, Joseph S.; Girdhar, Anuj; Gelfand, Ryan M.; Memik, Gokhan; Mohseni, Hooman; Taflove, Allen; Wessels, Bruce W.; Leburton, Jean-Pierre; Sahakian, Alan V.
2017-06-01
Remarkable breakthroughs have established the functionality of graphene and carbon nanotube transistors as replacements to silicon in conventional computing structures, and numerous spintronic logic gates have been presented. However, an efficient cascaded logic structure that exploits electron spin has not yet been demonstrated. In this work, we introduce and analyse a cascaded spintronic computing system composed solely of low-dimensional carbon materials. We propose a spintronic switch based on the recent discovery of negative magnetoresistance in graphene nanoribbons, and demonstrate its feasibility through tight-binding calculations of the band structure. Covalently connected carbon nanotubes create magnetic fields through graphene nanoribbons, cascading logic gates through incoherent spintronic switching. The exceptional material properties of carbon materials permit Terahertz operation and two orders of magnitude decrease in power-delay product compared to cutting-edge microprocessors. We hope to inspire the fabrication of these cascaded logic circuits to stimulate a transformative generation of energy-efficient computing.
Non-logic devices in logic processes
Ma, Yanjun
2017-01-01
This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes. Readers will benefit from the author’s extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.
Logic and truth: Some logics without theorems
Directory of Open Access Journals (Sweden)
Jayanta Sen
2008-08-01
Full Text Available Two types of logical consequence are compared: one, with respect to matrix and designated elements and the other with respect to ordering in a suitable algebraic structure. Particular emphasis is laid on algebraic structures in which there is no top-element relative to the ordering. The significance of this special condition is discussed. Sequent calculi for a number of such structures are developed. As a consequence it is re-established that the notion of truth as such, not to speak of tautologies, is inessential in order to define validity of an argument.
New low power adders in Self Resetting Logic with Gate Diffusion Input Technique
Directory of Open Access Journals (Sweden)
R. Uma
2017-04-01
Full Text Available The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI. This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phases. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250 μm Complementary Metal Oxide Semiconductor (CMOS process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic logic (DY, CMOS, Self Resetting CMOS (SRCMOS and GDI.
Logic Programming for Linguistics
DEFF Research Database (Denmark)
Christiansen, Henning
2010-01-01
This article gives a short introduction on how to get started with logic pro- gramming in Prolog that does not require any previous programming expe- rience. The presentation is aimed at students of linguistics, but it does not go deeper into linguistics than any student who has some ideas of what...... a computer is, can follow the text. I cannot, of course, cover all aspects of logic programming in this text, and so we give references to other sources with more details. Students of linguistics must have a very good motivation to spend time on programming, and I show here how logic programming can be used...... for modelling different linguistic phenomena. When modelling language in this way, as opposed to using only paper and pencil, your models go live: you can run and test your models and you can use them as automatic language analyzers. This way you will get a better understanding of the dynamics of languages...
Carlsson, Christer; Fullér, Robert
2004-01-01
Fuzzy Logic in Management demonstrates that difficult problems and changes in the management environment can be more easily handled by bringing fuzzy logic into the practice of management. This explicit theme is developed through the book as follows: Chapter 1, "Management and Intelligent Support Technologies", is a short survey of management leadership and what can be gained from support technologies. Chapter 2, "Fuzzy Sets and Fuzzy Logic", provides a short introduction to fuzzy sets, fuzzy relations, the extension principle, fuzzy implications and linguistic variables. Chapter 3, "Group Decision Support Systems", deals with group decision making, and discusses methods for supporting the consensus reaching processes. Chapter 4, "Fuzzy Real Options for Strategic Planning", summarizes research where the fuzzy real options theory was implemented as a series of models. These models were thoroughly tested on a number of real life investments, and validated in 2001. Chapter 5, "Soft Computing Methods for Reducing...
Directory of Open Access Journals (Sweden)
Zoltan Erdei
2011-12-01
Full Text Available In this paper the authors present the usefulness of fuzzy logic in controlling engineering processes or applications. Although fuzzy logic does not represent a novelty for the scientific and engineering field, it enjoys a great appreciation from those involved in the two domains. The fact that fuzzy logic uses sentences kindred with the natural language make it easier to comprehend that a complex mathematical model required by the classic control theory. In MatLab software there are dedicated toolboxes to this subject that make the design of a fuzzy controller a facile one. In the paper design methods of a fuzzy controller are being presented both in Simulink and MatLab.
Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)
2017-01-01
A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.
Duration Calculus: Logical Foundations
DEFF Research Database (Denmark)
Hansen, Michael Reichhardt; Chaochen, Zhou
1997-01-01
The Duration Calculus (abbreviated DC) represents a logical approach to formal design of real-time systems, where real numbers are used to model time and Boolean valued functions over time are used to model states and events of real-time systems. Since it introduction, DC has been applied to many...... case studies and it has been extended in several directions. The aim of this paper is to provide a thorough presentation of the logic.......The Duration Calculus (abbreviated DC) represents a logical approach to formal design of real-time systems, where real numbers are used to model time and Boolean valued functions over time are used to model states and events of real-time systems. Since it introduction, DC has been applied to many...
Logical Theories for Agent Introspection
DEFF Research Database (Denmark)
Bolander, Thomas
2004-01-01
several such logical theories which we prove to be consistent. These theories are all based on first-order predicate logic. To prove our consistency results, we develop a general mathematical framework, suitable for proving a large number of consistency results concerning logical theories involving...... by developments within semantics for logic programming within computational logic and formal theories of truth within philosophical logic. The thesis provides a number of examples showing how the developed theories can be used as reasoning frameworks for agents with introspective abilities. In Danish...... by self-reference. In the standard approach taken in artificial intelligence, the model that an agent has of its environment is represented as a set of beliefs. These beliefs are expressed as logical formulas within a formal, logical theory. When the logical theory is expressive enough to allow...
Masuda, Tatsuya; Tanaka, Hiroshi; Hayashi, Yasumiki
We have already proposed a new automatic logic circuit design method using genetic algorithm based on the coexistence of heterogeneous populations. In this letter, we apply the proposed method to the design of the artificial ant control circuit, and clarify that the proposed method is effective also to the design of the logic circuit of which the I/O specification is not given beforehand.
Caicedo, Xavier; Rodriguez, Ricardo Oscar
2009-01-01
In this paper we consider an approach where both propositions and the accessibility relation are infinitely many-valued over G\\"{o}del algebras. In particular, we consider separately the $\\Box $-fragment and the $\\Diamond $-fragment of our G\\"{o}del modal logic and prove that both logics are complete with respect to the class of models with values in the linear Hetying algebra [0,1]. In addition, we show that the first fragment is uniquely determined by the class of models having crisp access...
Linear Logical Voting Protocols
DEFF Research Database (Denmark)
DeYoung, Henry; Schürmann, Carsten
2012-01-01
Current approaches to electronic implementations of voting protocols involve translating legal text to source code of an imperative programming language. Because the gap between legal text and source code is very large, it is difficult to trust that the program meets its legal specification....... In response, we promote linear logic as a high-level language for both specifying and implementing voting protocols. Our linear logical specifications of the single-winner first-past-the-post (SW- FPTP) and single transferable vote (STV) protocols demonstrate that this approach leads to concise...
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2011-01-01
We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML....... To guard against modelling artifacts we provide an alternative way of characterizing the policy combining algorithms and we formally prove the equivalence of these approaches. This allows us to pinpoint the shortcoming of previous approaches to formalization based either on Belnap logic or on D-algebra....
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2011-01-01
We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML....... To guard against modelling artefacts we provide an alternative way of characterizing the policy combining algorithms and we formally prove the equivalence of these approaches. This allows us to pinpoint the shortcoming of previous approaches to formalization based either on Belnap logic or on D -algebra....
DEFF Research Database (Denmark)
Mardare, Radu Iulian; Cardelli, Luca; Larsen, Kim Guldstrand
2012-01-01
Continuous Markovian Logic (CML) is a multimodal logic that expresses quantitative and qualitative properties of continuous-time labelled Markov processes with arbitrary (analytic) state-spaces, henceforth called continuous Markov processes (CMPs). The modalities of CML evaluate the rates...... of the exponentially distributed random variables that characterize the duration of the labeled transitions of a CMP. In this paper we present weak and strong complete axiomatizations for CML and prove a series of metaproperties, including the finite model property and the construction of canonical models. CML...
Introduction to mathematical logic
Mendelson, Elliott
2009-01-01
The Propositional CalculusPropositional Connectives. Truth TablesTautologies Adequate Sets of Connectives An Axiom System for the Propositional Calculus Independence. Many-Valued LogicsOther AxiomatizationsFirst-Order Logic and Model TheoryQuantifiersFirst-Order Languages and Their Interpretations. Satisfiability and Truth. ModelsFirst-Order TheoriesProperties of First-Order Theories Additional Metatheorems and Derived Rules Rule C Completeness Theorems First-Order Theories with EqualityDefinitions of New Function Letters and Individual Constants Prenex Normal Forms Isomorphism of Interpretati
Stoll, Robert R
1979-01-01
Set Theory and Logic is the result of a course of lectures for advanced undergraduates, developed at Oberlin College for the purpose of introducing students to the conceptual foundations of mathematics. Mathematics, specifically the real number system, is approached as a unity whose operations can be logically ordered through axioms. One of the most complex and essential of modern mathematical innovations, the theory of sets (crucial to quantum mechanics and other sciences), is introduced in a most careful concept manner, aiming for the maximum in clarity and stimulation for further study in
Evens, Aden
2015-01-01
Building a foundational understanding of the digital, Logic of the Digital reveals a unique digital ontology. Beginning from formal and technical characteristics, especially the binary code at the core of all digital technologies, Aden Evens traces the pathways along which the digital domain of abstract logic encounters the material, human world. How does a code using only 0s and 1s give rise to the vast range of applications and information that constitutes a great and growing portion of our world? Evens' analysis shows how any encounter between the actual and the digital must cross an ontolo
PERFORMANCE ANALYSIS OF POWER GATING TECHNIQUES IN 4-BIT SISO SHIFT REGISTER CIRCUITS
Directory of Open Access Journals (Sweden)
K. NEHRU
2017-12-01
Full Text Available The last few years have witnessed great deal of research activities in the area of reversible logic; the intrinsic functionality to reduce the power dissipation that has been the main requirement in the low power digital circuit design has garnered more attraction to this field. In this paper various power gating techniques for power minimization in adder and 4 bit serial in serial out (SISO shift register circuits is proposed. The work also analyze various leakage reduction approaches such as sleep approach, sleepy stack approach, dual sleep technique and zig-zag technique for gate diffusion input technique, self resetting gate diffusion input technique for complementary metal oxide semi conductor (CMOS technology and forced stack and multiplexer based SISO registers. A 4 bit SISO and full adder was designed in a cadence virtuoso 180 nm technology and the simulated results show the trade-off between power, delay and power for the sequential circuits and the results demonstrate that minimum power consumption can be achieved when the adder and SISO are designed for clock gating.
Analog circuit design designing dynamic circuit response
Feucht, Dennis
2010-01-01
This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.
Fluorescent nanoparticle beacon for logic gate operation regulated by strand displacement.
Yang, Jing; Shen, Lingjing; Ma, Jingjing; Schlaberg, H Inaki; Liu, Shi; Xu, Jin; Zhang, Cheng
2013-06-26
A mechanism is developed to construct a logic system by employing DNA/gold nanoparticle (AuNP) conjugates as a basic work unit, utilizing a fluorescent beacon probe to detect output signals. To implement the logic circuit, a self-assembly DNA structure is attached onto nanoparticles to form the fluorescent beacon. Moreover, assisted by regulation of multilevel strand displacement, cascaded logic gates are achieved. The computing results are detected by methods using fluorescent signals, gel electrophoresis and transmission electron microscope (TEM). This work is expected to demonstrate the feasibility of the cascaded logic system based on fluorescent nanoparticle beacons, suggesting applications in DNA computation and biotechnology.
Delay Insensitive Ternary CMOS Logic for Secure Hardware
Directory of Open Access Journals (Sweden)
Ravi S. P. Nair
2015-09-01
Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.
A programming language for composable DNA circuits.
Phillips, Andrew; Cardelli, Luca
2009-08-06
Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.
Querying Natural Logic Knowledge Bases
DEFF Research Database (Denmark)
Andreasen, Troels; Bulskov, Henrik; Jensen, Per Anker
2017-01-01
This paper describes the principles of a system applying natural logic as a knowledge base language. Natural logics are regimented fragments of natural language employing high level inference rules. We advocate the use of natural logic for knowledge bases dealing with querying of classes...... in ontologies and class-relationships such as are common in life-science descriptions. The paper adopts a version of natural logic with recursive restrictive clauses such as relative clauses and adnominal prepositional phrases. It includes passive as well as active voice sentences. We outline a prototype...... for partial translation of natural language into natural logic, featuring further querying and conceptual path finding in natural logic knowledge bases....
Analog circuit design designing waveform processing circuits
Feucht, Dennis
2010-01-01
The fourth volume in the set Designing Waveform-Processing Circuits builds on the previous 3 volumes and presents a variety of analog non-amplifier circuits, including voltage references, current sources, filters, hysteresis switches and oscilloscope trigger and sweep circuitry, function generation, absolute-value circuits, and peak detectors.
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic
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Shipra Upadhyay
2013-01-01
Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.
Kulikova, Olga
2016-01-01
This thesis was focused on the analysis of the concept of reverse logistics and actual reverse processes which are implemented in mining industry and finding solutions for the optimization of reverse logistics in this sphere. The objective of this paper was the assessment of the development of reverse logistics in mining industry on the example of potash production. The theoretical part was based on reverse logistics and mining waste related literature and provided foundations for further...
DEFF Research Database (Denmark)
Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming
2014-01-01
We study the international standard XACML 3.0 for describing security access control policies in a compositional way. Our main contributions are (i) to derive a logic that precisely captures the intentions of the standard, (ii) to formally define a semantics for the XACML 3.0 component evaluation...
Quantum probabilistic logic programming
Balu, Radhakrishnan
2015-05-01
We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.
DEFF Research Database (Denmark)
Birkedal, Lars; Sieczkowski, Filip; Thamsborg, Jacob Junker
2012-01-01
We present a logical relation for showing the correctness of program transformations based on a new type-and-eﬀect system for a concurrent extension of an ML-like language with higher-order functions, higher-order store and dynamic memory allocation. We show how to use our model to verify a number...
Logicism, intuitionism, and formalism
Symons, John
2008-01-01
Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.
Foundations of mathematical logic
Curry, Haskell B
2010-01-01
Written by a pioneer of mathematical logic, this comprehensive graduate-level text explores the constructive theory of first-order predicate calculus. It covers formal methods, including algorithms and epitheory, and offers a brief treatment of Markov's approach to algorithms, explains elementary facts about lattices and similar algebraic systems, and more. 1963 edition.
Benthem, Johan van; Bergstra, J.A.
1995-01-01
Labeled transition systems are key structures for modeling computation. In this paper, we show how they lend themselves to ordinary logical analysis (without any special new formalisms), by introducing their standard first-order theory. This perspective enables us to raise several
Literacy, Logic, and Intuition
Jaeger, Elizabeth
2007-01-01
The author calls into question whether learning to read and write is an exclusively logical and systematic process in which the child moves step-by-step from part to whole, as it is frequently presented in "scientific" reading research. She examines research on different types of intuitive behavior and suggests parallels in the development of…
Logical consequence for nominalists
Rossberg, Marcus; Cohnitz, Daniel|info:eu-repo/dai/nl/297859099
2009-01-01
It has repeatedly been argued that nominalistic programmes in the philosophy of mathematics fail, since they will at some point or other involve the notion of logical consequence which is unavailable to the nominalist. In this paper we will argue that this is not the case. Using an idea of Nelson
Expressivist Perspective on Logicality
Czech Academy of Sciences Publication Activity Database
Arazim, Pavel
2017-01-01
Roč. 11, č. 4 (2017), s. 409-419 ISSN 1661-8297 R&D Projects: GA ČR(CZ) GA17-15645S Institutional support: RVO:67985955 Keywords : logical constant * expressivism * topic-neutrality * proof-theory * conservativity Subject RIV: AA - Philosophy ; Religion
Bezhanishvili, G.; Bezhanishvili, N.; Ilin, J.
2016-01-01
We generalize the (∧,∨)-canonical formulas to (∧,∨)-canonical rules, and prove that each intuitionistic multi-conclusion consequence relation is axiomatizable by (∧,∨)-canonical rules. This yields a convenient characterization of stable superintuitionistic logics. The (∧,∨)-canonical formulas are
DEFF Research Database (Denmark)
Bentzen, Martin Mose
2014-01-01
are evaluated with respect to the benchmark cases. After that follows an informal introduction to the ideas behind the formal semantics, focussing on the distinction between action types and action tokens. Then the syntax and semantics of Action Type Deontic Logic is presented and it is shown to meet...
Greek, Indian and Arabic logic
Gabbay, Dov M
2004-01-01
Greek, Indian and Arabic Logic marks the initial appearance of the multi-volume Handbook of the History of Logic. Additional volumes will be published when ready, rather than in strict chronological order. Soon to appear are The Rise of Modern Logic: From Leibniz to Frege. Also in preparation are Logic From Russell to Gödel, Logic and the Modalities in the Twentieth Century, and The Many-Valued and Non-Monotonic Turn in Logic. Further volumes will follow, including Mediaeval and Renaissance Logic and Logic: A History of its Central. In designing the Handbook of the History of Logic, the Editors have taken the view that the history of logic holds more than an antiquarian interest, and that a knowledge of logic's rich and sophisticated development is, in various respects, relevant to the research programmes of the present day. Ancient logic is no exception. The present volume attests to the distant origins of some of modern logic's most important features, such as can be found in the claim by the authors of t...
Stochastic p-Bits for Invertible Logic
Directory of Open Access Journals (Sweden)
Kerem Yunus Camsari
2017-07-01
Full Text Available Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40–60 kT. In this paper, we show that unstable, stochastic units, which we call “p-bits,” can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p-bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p-bits, showing that p-bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM with a symmetric connection matrix [J] (J_{ij}=J_{ji} that implements a given truth table with p-bits. The [J] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (J_{ij}≠J_{ji} to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p-bits get precisely correlated such that the correct answer out of 2^{33} (≈8×10^{9} possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect
Stochastic p -Bits for Invertible Logic
Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo
2017-07-01
Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small
Photonic encryption : modeling and functional analysis of all optical logic.
Energy Technology Data Exchange (ETDEWEB)
Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.
2004-10-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple
Extending Value Logic Thinking to Value Logic Portfolios
DEFF Research Database (Denmark)
Ritter, Thomas; Andersen, Poul Houman
or transaction, an understanding of firms and transactions as a portfolio of value logics (i.e. an interconnected coexistence of different value creation logics) is proposed. These additions to the original value creation logic theory imply interesting avenues for both, strategic decision making in firms...
Multifunctional logic gates based on silicon hybrid plasmonic waveguides
Cui, Luna; Yu, Li
2018-01-01
Nano-scale Multifunctional Logic Gates based on Si hybrid plasmonic waveguides (HPWGs) are designed by utilizing the multimode interference (MMI) effect. The proposed device is composed of three input waveguides, three output waveguides and an MMI waveguide. The functional size of the device is only 1000 nm × 3200 nm, which is much smaller than traditional Si-based all-optical logic gates. By setting different input signals and selecting suitable threshold value, OR, AND, XOR and NOT gates are achieved simultaneously or individually in a single device. This may provide a way for ultrahigh speed signal processing and future nanophotonic integrated circuits.
Logical analysis of biological systems
DEFF Research Database (Denmark)
Mardare, Radu Iulian
2005-01-01
R. Mardare, Logical analysis of biological systems. Fundamenta Informaticae, N 64:271-285, 2005.......R. Mardare, Logical analysis of biological systems. Fundamenta Informaticae, N 64:271-285, 2005....
DEFF Research Database (Denmark)
Braüner, Torben
2011-01-01
Hybrid logic is an extension of modal logic which allows us to refer explicitly to points of the model in the syntax of formulas. It is easy to justify interest in hybrid logic on applied grounds, with the usefulness of the additional expressive power. For example, when reasoning about time one...... often wants to build up a series of assertions about what happens at a particular instant, and standard modal formalisms do not allow this. What is less obvious is that the route hybrid logic takes to overcome this problem often actually improves the behaviour of the underlying modal formalism....... For example, it becomes far simpler to formulate proof-systems for hybrid logic, and completeness results can be proved of a generality that is simply not available in modal logic. That is, hybridization is a systematic way of remedying a number of known deficiencies of modal logic. First-order hybrid logic...
Wansing, Heinrich; Willkommen, Caroline; Recent Trends in Philosophical Logic
2014-01-01
This volume presents recent advances in philosophical logic with chapters focusing on non-classical logics, including paraconsistent logics, substructural logics, modal logics of agency and other modal logics. The authors cover themes such as the knowability paradox, tableaux and sequent calculi, natural deduction, definite descriptions, identity, truth, dialetheism, and possible worlds semantics. The developments presented here focus on challenging problems in the specification of fundamental philosophical notions, as well as presenting new techniques and tools, thereby contributing to the development of the field. Each chapter contains a bibliography, to assist the reader in making connections in the specific areas covered. Thus this work provides both a starting point for further investigations into philosophical logic and an update on advances, techniques and applications in a dynamic field. The chapters originate from papers presented during the Trends in Logic XI conference at the Ruhr University ...
Resettable fluorescence logic gate based on calcein/layered double hydroxide ultrathin films.
Shi, Wenying; Ji, Xiaolan; Wei, Min; Evans, David G; Duan, Xue
2012-05-08
A fluorescent logic gate was fabricated based on calcein/layered double hydroxide ultrathin films (UTFs) via alternate assembly technique, which exhibits high stability, reversibility, and resettability. The logic gate was manipulated by utilizing pH value, Hg(2+) and Cl(-) ion as inputs, and the fluorescence emission of the (calcein/LDH)(16) UTF as output, serving as a three-input logic gate that combines the YES and INHIBIT operation.
Nguyen, Hung T
2005-01-01
THE CONCEPT OF FUZZINESS Examples Mathematical modeling Some operations on fuzzy sets Fuzziness as uncertainty Exercises SOME ALGEBRA OF FUZZY SETS Boolean algebras and lattices Equivalence relations and partitions Composing mappings Isomorphisms and homomorphisms Alpha-cuts Images of alpha-level sets Exercises FUZZY QUANTITIES Fuzzy quantities Fuzzy numbers Fuzzy intervals Exercises LOGICAL ASPECTS OF FUZZY SETS Classical two-valued logic A three-valued logic Fuzzy logic Fuzzy and Lukasiewi
Luo, Maokang; He, Wei
2015-01-01
Fuzziness and randomicity widespread exist in natural science, engineering, technology and social science. The purpose of this paper is to present a new logic - uncertain propositional logic which can deal with both fuzziness by taking truth value semantics and randomicity by taking probabilistic semantics or possibility semantics. As the first step for purpose of establishing a logic system which completely reflect the uncertainty of the objective world, this logic will lead to a set of logi...
Compact representations for the design of quantum logic
Niemann, Philipp
2017-01-01
This book discusses modern approaches and challenges of computer-aided design (CAD) of quantum circuits with a view to providing compact representations of quantum functionality. Focusing on the issue of quantum functionality, it presents Quantum Multiple-Valued Decision Diagrams (QMDDs – a means of compactly and efficiently representing and manipulating quantum logic. For future quantum computers, going well beyond the size of present-day prototypes, the manual design of quantum circuits that realize a given (quantum) functionality on these devices is no longer an option. In order to keep up with the technological advances, methods need to be provided which, similar to the design and synthesis of conventional circuits, automatically generate a circuit description of the desired functionality. To this end, an efficient representation of the desired quantum functionality is of the essence. While straightforward representations are restricted due to their (exponentially) large matrix descriptions and other de...
Memristor-based nanoelectronic computing circuits and architectures
Vourkas, Ioannis
2016-01-01
This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today’s latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied t...
Logical Characterisation of Ontology Construction using Fuzzy Description Logics
DEFF Research Database (Denmark)
Badie, Farshad; Götzsche, Hans
had the extension of ontologies with Fuzzy Logic capabilities which plan to make proper backgrounds for ontology driven reasoning and argumentation on vague and imprecise domains. This presentation conceptualises learning from fuzzy classes using the Inductive Logic Programming framework. Then......, employs Description Logics in characterising and analysing fuzzy statements. And finally, provides a conceptual framework describing fuzzy concept learning in ontologies using the Inductive Logic Programming.......Ontologies based on Description Logics (DLs) have proved to be effective in formally sharing knowledge across semantic technologies, e.g. Semantic Web, Natural Language Processing, Text Analytics, Business intelligence. Our main goal is analysing ontology construction considering vagueness. We have...
DEFF Research Database (Denmark)
Engberg, Uffe Henrik; Winskel, Glynn
This article shows how individual Petri nets form models of Girard's intuitionistic linear logic. It explores questions of expressiveness and completeness of linear logic with respect to this interpretation. An aim is to use Petri nets to give an understanding of linear logic and give some apprai...
A Paraconsistent Higher Order Logic
DEFF Research Database (Denmark)
Villadsen, Jørgen
2004-01-01
Abstract. Classical logic predicts that everything (thus nothing useful at all) follows from inconsistency. A paraconsistent logic is a logic where an inconsistency does not lead to such an explosion, and since in practice consistency is difficult to achieve there are many potential applications...
Flat coalgebraic fixed point logics
Schröder, L.; Venema, Y.
2010-01-01
Fixed point logics are widely used in computer science, in particular in artificial intelligence and concurrency. The most expressive logics of this type are the μ-calculus and its relatives. However, popular fixed point logics tend to trade expressivity for simplicity and readability, and in fact
A novel, efficient CNTFET Galois design as a basic ternary-valued logic field
Directory of Open Access Journals (Sweden)
Keshavarzian P
2012-01-01
Full Text Available Peiman Keshavarzian1, Mahla Mohammad Mirzaee21Kerman Branch, Computer Engineering Department, Islamic Azad University, Kerman, Iran; 2Science and Research Branch, Computer Engineering Department, IA University, Kerman, IranAbstract: This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs. Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption.Keywords: galois field, CNTFET, MVL circuit design
A formalized design process for bacterial consortia that perform logic computing.
Directory of Open Access Journals (Sweden)
Weiyue Ji
Full Text Available The concept of microbial consortia is of great attractiveness in synthetic biology. Despite of all its benefits, however, there are still problems remaining for large-scaled multicellular gene circuits, for example, how to reliably design and distribute the circuits in microbial consortia with limited number of well-behaved genetic modules and wiring quorum-sensing molecules. To manage such problem, here we propose a formalized design process: (i determine the basic logic units (AND, OR and NOT gates based on mathematical and biological considerations; (ii establish rules to search and distribute simplest logic design; (iii assemble assigned basic logic units in each logic operating cell; and (iv fine-tune the circuiting interface between logic operators. We in silico analyzed gene circuits with inputs ranging from two to four, comparing our method with the pre-existing ones. Results showed that this formalized design process is more feasible concerning numbers of cells required. Furthermore, as a proof of principle, an Escherichia coli consortium that performs XOR function, a typical complex computing operation, was designed. The construction and characterization of logic operators is independent of "wiring" and provides predictive information for fine-tuning. This formalized design process provides guidance for the design of microbial consortia that perform distributed biological computation.
Garcia-Escartin, Juan Carlos; Chamorro-Posada, Pedro
2011-01-01
Quantum algorithms and protocols are often presented as quantum circuits for a better understanding. We give a list of equivalence rules which can help in the analysis and design of quantum circuits. As example applications we study quantum teleportation and dense coding protocols in terms of a simple XOR swapping circuit and give an intuitive picture of a basic gate teleportation circuit.
Logic Locking Using Hybrid CMOS and Emerging SiNW FETs
Directory of Open Access Journals (Sweden)
Qutaiba Alasad
2017-09-01
Full Text Available The outsourcing of integrated circuit (IC fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs to replace the conventional Exclusive-OR (XOR-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.
Bera, Debajyoti; Fenner, Stephen; Green, Frederic; Homer, Steve
2008-01-01
We define and construct efficient depth-universal and almost-size-universal quantum circuits. Such circuits can be viewed as general-purpose simulators for central classes of quantum circuits and can be used to capture the computational power of the circuit class being simulated. For depth we construct universal circuits whose depth is the same order as the circuits being simulated. For size, there is a log factor blow-up in the universal circuits constructed here. We prove that this construc...
Santiago, John
2013-01-01
Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help
Pridham, G J
2013-01-01
Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided
Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model
MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.
2005-01-01
A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.
Pascal, Robert; Pross, Addy
2016-11-01
In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the 'regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both 'regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.
The development of an interim generalized gate logic software simulator
Mcgough, J. G.; Nemeroff, S.
1985-01-01
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
1981-01-01
Rapport, Groupe Intelligence Pasero, R., Artificielle , Universite d’Aix-Marseille, Roussel, P. Luminy, France, 1973. [Kowalski 1974] Kowalski, R. A...THIS PAGZ(Whan Doee Es tMord) Item 20 (Cont’d) ------ work in the area of artificial intelligence and those used in general program development into a...logic programming with LISP for implementing intelligent data base query systems. Continued developments will allow for enhancements to be made to the
Probabilistic Logical Characterization
DEFF Research Database (Denmark)
Hermanns, Holger; Parma, Augusto; Segala, Roberto
2011-01-01
Probabilistic automata exhibit both probabilistic and non-deterministic choice. They are therefore a powerful semantic foundation for modeling concurrent systems with random phenomena arising in many applications ranging from artificial intelligence, security, systems biology to performance...... modeling. Several variations of bisimulation and simulation relations have proved to be useful as means to abstract and compare different automata. This paper develops a taxonomy of logical characterizations of these relations on image-finite and image-infinite probabilistic automata....
Marketing Logics, Ambidexterity and Influence
DEFF Research Database (Denmark)
Tollin, Karin; Schmidt, Marcus
2012-01-01
in four CMOs have taken on this challenge, or adopted a marketing logic which could be referred to as ambidextrous. Furthermore, the study shows that this logic exerts a stronger impact on marketing's influence, compared to logics related to assuring brand consistency and measuring the performance...... of marketing processes. Three other ways to enact marketing management were also revealed, namely: an innovation; a communication; and a supporting marketing logic. This leads us to conclude that the influence of companies' marketing functions show up a heterogeneous picture within which the marketing logics...
A diagnostic expert system for digital circuits
Backlund, R. W.; Wilson, J. D.
1992-04-01
A scheme is presented for a diagnostic expert system which is capable of troubleshooting a faulty digital circuit or producing a reduced test vector set for a non-faulty digital circuit. It is based on practical fault-finding logic and utilizes artificial intelligence techniques. The program uses expert knowledge comprised of two components: that which is contained within the program in the form of rules and heuristics, and that which is derived from the circuit under test in the form of specific device information. Using both forward and backward tracking algorithms, signal paths comprised of device and gate interconnections are identified from each output pin to the primary input pins which have effect on them. Beginning at the output, the program proceeds to validate each device in each signal path by forward propagating test values through the device to the output, and backward propagating the same values to the primary inputs. All devices in the circuit are monitored for each test applied and their performance is recorded. Device or gate validation occurs when the recorded history shows that a device has been toggled successfully through all necessary states. When run on a circuit which does not contain a fault, the program determines a reduced test vector set for that circuit.
Energy efficient circuit design using nanoelectromechanical relays
Venkatasubramanian, Ramakrishnan
Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS
Analytic models of CMOS logic in various regimes
Directory of Open Access Journals (Sweden)
Dokić Branko
2014-01-01
Full Text Available In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.
Concrete Quantum Logics and Δ -Logics, States and Δ -States
Hroch, Michal; Pták, Pavel
2017-12-01
By a concrete quantum logic (in short, by a logic) we mean the orthomodular poset that is set-representable. If L=({Ω },L) is a logic and L is closed under the formation of symmetric difference, Δ , we call L a Δ -logic. In the first part we situate the known results on logics and states to the context of Δ -logics and Δ -states (the Δ -states are the states that are subadditive with respect to the symmetric difference). Moreover, we observe that the rather prominent logic E^{ {even}}_{Ω } of all even-coeven subsets of the countable set Ω possesses only Δ -states. Then we show when a state on the logics given by the divisibility relation allows for an extension as a state. In the next paragraph we consider the so called density logic and its Δ -closure. We find that the Δ -closure coincides with the power set. Then we investigate other properties of the density logic and its factor.
Posser, Gracieli; Reis, Ricardo
2017-01-01
This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. .
Liu, Shuang; Wang, Lei; Lian, Wenjing; Liu, Hongyun; Li, Chen-Zhong
2015-01-01
A logic-gate system with three outputs and three inputs was developed based on the bioelectrocatalysis of glucose by glucose oxidase (GOx) entrapped in chitosan films on the electrode surface by means of ferrocenedicarboxylic acid (Fc(COOH)2 ). Cyclic voltammetric (CV) signals of Fc(COOH)2 exhibited pH-triggered on/off behavior owing to electrostatic interactions between the film and the probe at different pH levels. The addition of glucose greatly increased the oxidation peak current (Ipa ) through the electrocatalytic reaction. pH and glucose were selected as two inputs. As a reversible inhibitor of GOx, Cu(2+) was chosen as the third input. The combination of three inputs led to Ipa with different values according to different mechanisms, which were defined as three outputs with two thresholds. The logic gate with three outputs by using one type of enzyme provided a novel model to build logic circuits based on biomacromolecules, which might be applied to the intelligent medical diagnostics as smart biosensors in the future. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Feasibility study for a generalized gate logic software simulator
Mcgough, J. G.
1983-01-01
Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.
Microdroplet-based universal logic gates by electrorheological fluid
Zhang, Mengying
2011-01-01
We demonstrate a uniquely designed microfluid logic gate with universal functionality, which is capable of conducting all 16 logic operations in one chip, with different input voltage combinations. A kind of smart colloid, giant electrorheological (GER) fluid, functions as the translation media among fluidic, electronic and mechanic information, providing us with the capability of performing large integrations either on-chip or off-chip, while the on-chip hybrid circuit is formed by the interconnection of the electric components and fluidic channels, where the individual microdroplets travelling in a channel represents a bit. The universal logic gate reveals the possibilities of achieving a large-scale microfluidic processor with more complexity for on-chip processing for biological, chemical as well as computational experiments. © 2011 The Royal Society of Chemistry.
Logical error rate in the Pauli twirling approximation.
Katabarwa, Amara; Geller, Michael R
2015-09-30
The performance of error correction protocols are necessary for understanding the operation of potential quantum computers, but this requires physical error models that can be simulated efficiently with classical computers. The Gottesmann-Knill theorem guarantees a class of such error models. Of these, one of the simplest is the Pauli twirling approximation (PTA), which is obtained by twirling an arbitrary completely positive error channel over the Pauli basis, resulting in a Pauli channel. In this work, we test the PTA's accuracy at predicting the logical error rate by simulating the 5-qubit code using a 9-qubit circuit with realistic decoherence and unitary gate errors. We find evidence for good agreement with exact simulation, with the PTA overestimating the logical error rate by a factor of 2 to 3. Our results suggest that the PTA is a reliable predictor of the logical error rate, at least for low-distance codes.
Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate
Directory of Open Access Journals (Sweden)
Maoqun Yao
2015-01-01
Full Text Available The resonant tunneling device (RTD has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate has become an important unit circuit of digital circuit design because of its powerful logic function, while the threshold logic gate is a suitable unit to design the universal logic gate, but the function synthesis algorithm for the n-variable logical function implemented by the RTD-based universal logic gate (UTLG is relatively deficient. In this paper, three-variable threshold functions are divided into four categories; based on the Reed-Muller expansion, two categories of these are analyzed, and a new decomposition algorithm of the three-variable nonthreshold functions is proposed. The proposed algorithm is simple and the decomposition results can be obtained by looking up the decomposition table. Then, based on the Reed-Muller algebraic system, the arbitrary n-variable function can be decomposed into three-variable functions, and a function synthesis algorithm for the n-variable logical function implemented by UTLG and XOR2 is proposed, which is a simple programmable implementation.
Design and implementation of a simple acousto optic dual control circuit
Li, Biqing; Li, Zhao
2017-04-01
This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.
Multi-valued and Fuzzy Logic Realization using TaOx Memristive Devices.
Bhattacharjee, Debjyoti; Kim, Wonjoo; Chattopadhyay, Anupam; Waser, Rainer; Rana, Vikas
2018-01-08
Among emerging non-volatile storage technologies, redox-based resistive switching Random Access Memory (ReRAM) is a prominent one. The realization of Boolean logic functionalities using ReRAM adds an extra edge to this technology. Recently, 7-state ReRAM devices were used to realize ternary arithmetic circuits, which opens up the computing space beyond traditional binary values. In this manuscript, we report realization of multi-valued and fuzzy logic operators with a representative application using ReRAM devices. Multi-valued logic (MVL), such as Łukasiewicz logic generalizes Boolean logic by allowing more than two truth values. MVL also permits operations on fuzzy sets, where, in contrast to standard crisp logic, an element is permitted to have a degree of membership to a given set. Fuzzy operations generally model human reasoning better than Boolean logic operations, which is predominant in current computing technologies. When the available information for the modelling of a system is imprecise and incomplete, fuzzy logic provides an excellent framework for the system design. Practical applications of fuzzy logic include, industrial control systems, robotics, and in general, design of expert systems through knowledge-based reasoning. Our experimental results show, for the first time, that it is possible to model fuzzy logic natively using multi-state memristive devices.
Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.
Liu, Yuanda; Ang, Kah-Wee
2017-07-25
Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10(3). Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.
New Proposal for MCML Based Three-Input Logic Implementation
Directory of Open Access Journals (Sweden)
Neeta Pandey
2016-01-01
Full Text Available This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.
Superconducting Complementary Output Switching Logic Operating at 10 - 18 GHz
Jeffery, Mark; van Duzer, T.; Perold, Willem
1998-03-01
We have developed a new type of superconducting voltage-state logic called Complementary Output Switching Logic (COSL)(M. Jeffery, W. Perold, and T. Van Duzer, Appl. Phys. Lett., 69) (18), 2746 (1996). The basic COSL gates have been demonstrated at 10 GHz and complex 2-bit encoder circuits have operated at 5 - 8 GHz. The COSL gates have extremely low power dissipation, of order 10 μW/gate, and we have measured bit error rates less than 10-12 at 2 GHz. For these results we used the HYPRES 1 kA/cm^2 critical current density Nb Josephson fabrication process. In the present work we describe our recent test results using the new HYPRES 2.5 kA/cm^2 process. The increased critical current density process significantly improves the switching speed of the COSL devices. We will describe the Monte Carlo method used to optimize the COSL gates for 20 - 30 GHz operation, and the optimal circuit layouts including moats, or ground plane holes, to shield the circuits from trapped magnetic flux. Experimental test results will be presented for the basic COSL devices operating at 10 - 18 GHz. These are the fastest superconducting voltage-state logic devices ever reported, and may have many applications in low power ultra-high-speed digital systems of the future.
Mizraji, Eduardo; Lin, Juan
2011-02-01
The ability of the human brain to carry out logical reasoning can be interpreted, in general, as a by-product of adaptive capacities of complex neural networks. Thus, we seek to base abstract logical operations in the general properties of neural networks designed as learning modules. We show that logical operations executable by McCulloch-Pitts binary networks can also be programmed in analog neural networks built with associative memory modules that process inputs as logical gates. These modules can interact among themselves to generate dynamical systems that extend the repertoire of logical operations. We demonstrate how the operations of the exclusive-OR or the implication appear as outputs of these interacting modules. In particular, we provide a model of the exclusive-OR that succeeds in evaluating an odd number of options (the exclusive-OR of classical logic fails in his case), thus paving the way for a more reasonable biological model of this important logical operator. We propose that a brain trained to compute can associate a complex logical operation to an orderly structured but temporary contingent episode by establishing a codified association among memory modules. This explanation offers an interpretation of complex logical processes (eventually learned) as associations of contingent events in memorized episodes. We suggest, as an example, a cognitive model that describes these "logical episodes".
Fast recharge circuit for q-switched lasers
Hansen, R. L.
1973-01-01
Cavity-dumped lasers employ electrooptic-effect cell to alternately block and release laser pulse. Cell requires high-speed switching circuit that can apply and remove high voltage. Solid-state circuit employs complementary transistor switches which can switch at rates greater than 5 kHz, eliminate warmup time, provide variable voltage wave-form, and allow polarity reversal.
Rational design of a fusion protein to exhibit disulfide-mediated logic gate behavior.
Choi, Jay H; Ostermeier, Marc
2015-04-17
Synthetic cellular logic gates are primarily built from gene circuits owing to their inherent modularity. Single proteins can also possess logic gate functions and offer the potential to be simpler, quicker, and less dependent on cellular resources than gene circuits. However, the design of protein logic gates that are modular and integrate with other cellular components is a considerable challenge. As a step toward addressing this challenge, we describe the design, construction, and characterization of AND, ORN, and YES logic gates built by introducing disulfide bonds into RG13, a fusion of maltose binding protein and TEM-1 β-lactamase for which maltose is an allosteric activator of enzyme activity. We rationally designed these disulfide bonds to manipulate RG13's allosteric regulation mechanism such that the gating had maltose and reducing agents as input signals, and the gates could be toggled between different gating functions using redox agents, although some gates performed suboptimally.
Controlled data storage for non-volatile memory cells embedded in nano magnetic logic
Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan
2017-05-01
Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.
Logic control of microfluidics with smart colloid
Wang, Limu
2010-01-01
We report the successful realization of a microfluidic chip with switching and corresponding inverting functionalities. The chips are identical logic control components incorporating a type of smart colloid, giant electrorheological fluid (GERF), which possesses reversible characteristics via a liquid-solid phase transition under external electric field. Two pairs of electrodes embedded on the sides of two microfluidic channels serve as signal input and output, respectively. One, located in the GERF micro-channel is used to control the flow status of GERF, while another one in the ither micro-fluidic channel is used to detect the signal generated with a passing-by droplet (defined as a signal droplet). Switching of the GERF from the suspended state (off-state) to the flowing state (on-state) or vice versa in the micro-channel is controlled by the appearance of signal droplets whenever they pass through the detection electrode. The output on-off signals can be easily demonstrated, clearly matching with GERF flow status. Our results show that such a logic switch is also a logic IF gate, while its inverter functions as a NOT gate. © The Royal Society of Chemistry 2010.
The circuit designer's companion
Williams, Tim
1991-01-01
The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll
Intuitive analog circuit design
Thompson, Marc
2013-01-01
Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi
Effects of smoke on functional circuits
Energy Technology Data Exchange (ETDEWEB)
Tanaka, T.J.
1997-10-01
Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs.
Reference counting for reversible languages
DEFF Research Database (Denmark)
Mogensen, Torben Ægidius
2014-01-01
Modern programming languages and operating systems use heap memory that allows allocation and deallocation of memory to be decoupled, so they don't follow a stack discipline. Axelsen and Glück have presented a reversible heap manager where allocation and deallocation are each other's logical...... inverses: Freeing a block of memory is done by running the allocation procedure backwards. Axelsen and Glück use this heap manager to sketch implementation of a simple reversible functional language where pattern matching a constructor is the inverse of construction, so pattern-matching implies...
Classical Mathematical Logic The Semantic Foundations of Logic
Epstein, Richard L
2011-01-01
In Classical Mathematical Logic, Richard L. Epstein relates the systems of mathematical logic to their original motivations to formalize reasoning in mathematics. The book also shows how mathematical logic can be used to formalize particular systems of mathematics. It sets out the formalization not only of arithmetic, but also of group theory, field theory, and linear orderings. These lead to the formalization of the real numbers and Euclidean plane geometry. The scope and limitations of modern logic are made clear in these formalizations. The book provides detailed explanations of all proo
Computability, complexity, logic
Börger, Egon
1989-01-01
The theme of this book is formed by a pair of concepts: the concept of formal language as carrier of the precise expression of meaning, facts and problems, and the concept of algorithm or calculus, i.e. a formally operating procedure for the solution of precisely described questions and problems. The book is a unified introduction to the modern theory of these concepts, to the way in which they developed first in mathematical logic and computability theory and later in automata theory, and to the theory of formal languages and complexity theory. Apart from considering the fundamental themes an
Krötzsch, M
2010-01-01
Ontological modelling today is applied in many areas of science and technology,including the Semantic Web. The W3C standard OWL defines one of the most important ontology languages based on the semantics of description logics. An alternative is to use rule languages in knowledge modelling, as proposed in the W3C's RIF standard. So far, it has often been unclear how to combine both technologies without sacrificing essential computational properties. This book explains this problem and presents new solutions that have recently been proposed. Extensive introductory chapters provide the necessary
T Atanassov, Krassimir
2017-01-01
The book offers a comprehensive survey of intuitionistic fuzzy logics. By reporting on both the author’s research and others’ findings, it provides readers with a complete overview of the field and highlights key issues and open problems, thus suggesting new research directions. Starting with an introduction to the basic elements of intuitionistic fuzzy propositional calculus, it then provides a guide to the use of intuitionistic fuzzy operators and quantifiers, and lastly presents state-of-the-art applications of intuitionistic fuzzy sets. The book is a valuable reference resource for graduate students and researchers alike.
Modern Logical Frameworks Design
DEFF Research Database (Denmark)
Murawska, Agata Anna
2017-01-01
design and provide the meta-theory of two new frameworks, HyLF and Lincx. The former aims to extend the expressiveness of LF to include proof irrelevance and some user-defined behaviours, using ideas from hybrid logics. The latter is a showcase for an easier to implement framework, while also allowing...... or a cryptographic protocol used in a voting system, we need the ability to model and reason about both the building blocks of these systems and the intricate connections between them. To this end, this dissertation is an investigation into LF-based formalisms that might help address the aforementioned issues. We...
DEFF Research Database (Denmark)
Øhrstrøm, Peter
2009-01-01
This paper deals with A.N. Prior's analysis of the concepts of dynamic and static time, i.e. McTaggart's so-called A- and B-concepts. The relations and mutual dependencies between these temporal concepts are investigated, and Prior's response to McTaggart's views is discussed. Futhermore, Prior......'s notion of branching time is analysed. It is argued that Prior can be criticized for identifying 'plain future'. Finally, Prior's four grades of tense-logical involvement are introduced and discussed. It is argued that the third grade is the most attractive form a philosophical point of view....
Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits
Chen, R. M.; Mahatme, N. N.; Diggins, Z. J.; Wang, L.; Zhang, E. X.; Chen, Y. P.; Liu, Y. N.; Narasimham, B.; Witulski, A. F.; Bhuva, B. L.; Fleetwood, D. M.
2017-08-01
Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.
Reversing cell polarity: evidence and hypothesis.
Kaiser, Dale; Yu, Rosa
2005-04-01
The long, rod-shaped cells of myxobacteria are polarized by their gliding engines. At the rear, A-engines push while pili pull the front end forward. An hypothesis is developed whereby both engines are partially dis-assembled, then re-assembled at the opposite pole when cells reverse their movement direction. Reversals are induced by an Mgl G-protein switch that controls engine polarity. The switch is driven by an oscillatory circuit of Frizzy proteins. In growing cells, the circuit gives rise to an occasional reversal that makes swarming possible. Then, as myxobacteria begin fruiting body development, a rising level of C-signal input drives the oscillator and changes the reversal pattern. Cells reverse regularly every eight minutes in traveling waves, the reversal period is then prolonged enabling cells to form streams that enlarge tiny random aggregates into fruiting bodies.
Garbageless reversible implementation of integer linear transformations
DEFF Research Database (Denmark)
Burignat, Stéphane; Vermeirsch, Kenneth; De Vos, Alexis
2013-01-01
Discrete linear transformations are important tools in information processing. Many such transforms are injective and therefore prime candidates for a physically reversible implementation into hardware. We present here reversible digital implementations of different integer transformations on four...... inputs. The resulting reversible circuit is able to perform both the forward transform and the inverse transform. Which of the two computations that actually is performed, simply depends on the orientation of the circuit when it is inserted in a computer board (if one takes care to provide...
Logical Framework for Normative Systems
Nakayama, Yasuo
2010-01-01
In this paper, I propose a new logical framework that can be used to analyze normative phenomena in general. I call this framework a Logic for Normative Systems (LNS). I also demonstrate how to solve some paradoxes of Standard Deontic Logic (SDL). A characteristic of LNS is its dynamic behavior. LNS is flexible, hence it can be applied to describe complex normative problems including ethical problems.
Algebraic Approach to Algorithmic Logic
Bancerek Grzegorz
2014-01-01
We introduce algorithmic logic - an algebraic approach according to [25]. It is done in three stages: propositional calculus, quantifier calculus with equality, and finally proper algorithmic logic. For each stage appropriate signature and theory are defined. Propositional calculus and quantifier calculus with equality are explored according to [24]. A language is introduced with language signature including free variables, substitution, and equality. Algorithmic logic requires a bialgebra st...
Optimization methods for logical inference
Chandru, Vijay
2011-01-01
Merging logic and mathematics in deductive inference-an innovative, cutting-edge approach. Optimization methods for logical inference? Absolutely, say Vijay Chandru and John Hooker, two major contributors to this rapidly expanding field. And even though ""solving logical inference problems with optimization methods may seem a bit like eating sauerkraut with chopsticks. . . it is the mathematical structure of a problem that determines whether an optimization model can help solve it, not the context in which the problem occurs."" Presenting powerful, proven optimization techniques for logic in
Admissibility of logical inference rules
Rybakov, VV
1997-01-01
The aim of this book is to present the fundamental theoretical results concerning inference rules in deductive formal systems. Primary attention is focused on: admissible or permissible inference rules the derivability of the admissible inference rules the structural completeness of logics the bases for admissible and valid inference rules. There is particular emphasis on propositional non-standard logics (primary, superintuitionistic and modal logics) but general logical consequence relations and classical first-order theories are also considered. The book is basically self-contained and
Algebraic Approach to Algorithmic Logic
Directory of Open Access Journals (Sweden)
Bancerek Grzegorz
2014-09-01
Full Text Available We introduce algorithmic logic - an algebraic approach according to [25]. It is done in three stages: propositional calculus, quantifier calculus with equality, and finally proper algorithmic logic. For each stage appropriate signature and theory are defined. Propositional calculus and quantifier calculus with equality are explored according to [24]. A language is introduced with language signature including free variables, substitution, and equality. Algorithmic logic requires a bialgebra structure which is an extension of language signature and program algebra. While-if algebra of generator set and algebraic signature is bialgebra with appropriate properties and is used as basic type of algebraic logic.
DEFF Research Database (Denmark)
By blending historical research with current research, this collection (loosely inspired by themes from the work of Arthur Prior) demonstrates the importance of Prior's writings and helps us to gain a deeper understanding of time, its logic(s), and its language(s).......By blending historical research with current research, this collection (loosely inspired by themes from the work of Arthur Prior) demonstrates the importance of Prior's writings and helps us to gain a deeper understanding of time, its logic(s), and its language(s)....
Popular lectures on mathematical logic
Wang, Hao
2014-01-01
A noted logician and philosopher addresses various forms of mathematical logic, discussing both theoretical underpinnings and practical applications. Author Hao Wang surveys the central concepts and theories of the discipline in a historical and developmental context, and then focuses on the four principal domains of contemporary mathematical logic: set theory, model theory, recursion theory and constructivism, and proof theory.Topics include the place of problems in the development of theories of logic and logic's relation to computer science. Specific attention is given to Gödel's incomplete
Digital systems from logic gates to processors
Deschamps, Jean-Pierre; Terés, Lluís
2017-01-01
This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop “traditional” Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, ...
REA, Editors of
2012-01-01
REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph
Synthesis of energy-efficient FSMs implemented in PLD circuits
Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz
2017-11-01
The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.
Wing, Omar
2008-01-01
Starting with the basic principles of circuits, this book derives their analytic properties in both the time and frequency domains. It develops an algorithmic method to design common and uncommon types of circuits, such as prototype filters, lumped delay lines, constant phase difference circuits, and delay equalizers.
Louwsma, S.M.; Vertregt, Maarten
2011-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital
Louwsma, S.M.; Vertregt, Maarten
2010-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital
Treu, Jr., Charles A.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.
DEFF Research Database (Denmark)
Hansen, Kristoffer Arnsfelt; Podolskii, Vladimir V.
2010-01-01
with the well-studied corresponding hierarchies defined using ordinary threshold gates. A major open problem in Boolean circuit complexity is to provide an explicit super-polynomial lower bound for depth two threshold circuits. We identify the class of depth two exact threshold circuits as a natural subclass...
DEFF Research Database (Denmark)
2009-01-01
A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...
Meta-Logical Reasoning in Higher-Order Logic
DEFF Research Database (Denmark)
Villadsen, Jørgen; Schlichtkrull, Anders; Hess, Andreas Viktor
The semantics of first-order logic (FOL) can be described in the meta-language of higher-order logic (HOL). Using HOL one can prove key properties of FOL such as soundness and completeness. Furthermore, one can prove sentences in FOL valid using the formalized FOL semantics. To aid...
Directory of Open Access Journals (Sweden)
Hong-Quan ZHao
2012-01-01
Full Text Available One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD- based arithmetic logic unit (ALU is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.
M.P. de Brito (Marisa); S.D.P. Flapper; R. Dekker (Rommert)
2002-01-01
textabstractThis paper gives an overview of scientific literature that describes and discusses cases of reverse logistics activities in practice. Over sixty case studies are considered. Based on these studies we are able to indicate critical factors for the practice of reverse logistics. In
Categorical Abstract Algebraic Logic: Meet-Combination of Logical Systems
Directory of Open Access Journals (Sweden)
George Voutsadakis
2013-01-01
properties inherited by the resulting combinations. One of the oldest such methods is fibring. In fibring the shared connectives of the combined logics inherit properties from both component logical systems, and this leads often to inconsistencies. To deal with such undesired effects, Sernadas et al. (2011, 2012 have recently introduced a novel way of combining logics, called meet-combination, in which the combined connectives share only the common logical properties they enjoy in the component systems. In their investigations they provide a sound and concretely complete calculus for the meet-combination based on available sound and complete calculi for the component systems. In this work, an effort is made to abstract those results to a categorical level amenable to categorical abstract algebraic logic techniques.
Towards an arithmetical logic the arithmetical foundations of logic
Gauthier, Yvon
2015-01-01
This book offers an original contribution to the foundations of logic and mathematics, and focuses on the internal logic of mathematical theories, from arithmetic or number theory to algebraic geometry. Arithmetical logic is the term used to refer to the internal logic of classical arithmetic, here called Fermat-Kronecker arithmetic, and combines Fermat’s method of infinite descent with Kronecker’s general arithmetic of homogeneous polynomials. The book also includes a treatment of theories in physics and mathematical physics to underscore the role of arithmetic from a constructivist viewpoint. The scope of the work intertwines historical, mathematical, logical and philosophical dimensions in a unified critical perspective; as such, it will appeal to a broad readership from mathematicians to logicians, to philosophers interested in foundational questions. Researchers and graduate students in the fields of philosophy and mathematics will benefit from the author’s critical approach to the foundations of l...
Finite state machine logic synthesis for complex programmable logic devices
Czerwinski, Robert
2013-01-01
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
2005-01-01
A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true
Biosensors with Built-In Biomolecular Logic Gates for Practical Applications
Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh
2014-01-01
Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423
Logical entropy of quantum dynamical systems
Directory of Open Access Journals (Sweden)
Ebrahimzadeh Abolfazl
2016-01-01
Full Text Available This paper introduces the concepts of logical entropy and conditional logical entropy of hnite partitions on a quantum logic. Some of their ergodic properties are presented. Also logical entropy of a quantum dynamical system is dehned and ergodic properties of dynamical systems on a quantum logic are investigated. Finally, the version of Kolmogorov-Sinai theorem is proved.
Questions and dependency in intuitionistic logic
Ciardelli, Ivano; Iemhoff, Rosalie; Yang, Fan
2017-01-01
In recent years, the logic of questions and dependencies has been investigated in the closely related frameworks of inquisitive logic and dependence logic. These investigations have assumed classical logic as the background logic of statements, and added formulas expressing questions and
A beginner's guide to mathematical logic
Smullyan, Raymond M
2014-01-01
Combining stories of great philosophers, quotations, and riddles with the fundamentals of mathematical logic, this new textbook for first courses in mathematical logic was written by the subject's creative master. Raymond Smullyan offers clear, incremental presentations of difficult logic concepts with creative explanations and unique problems related to proofs, propositional logic and first-order logic, undecidability, recursion theory, and other topics.
An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.
Kazemi, Mohammad
2017-11-10
The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.
Reconfigurable magnetic logic combined with non-volatile memory in silicon
Luo, Zhaochu; Zhang, Xiaozhong
Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.
Conventions and Institutional Logics
DEFF Research Database (Denmark)
Westenholz, Ann
Two theoretical approaches – Conventions and Institutional Logics – are brought together and the similarities and differences between the two are explored. It is not the intention to combine the approaches, but I would like to open both ‘boxes’ and make them available to each other with the purpose...... of creating a space for dialog. Both approaches were developed in the mid-1980s as a reaction to rational-choice economic theory and collectivistic sociological theory. These two theories were oversimplifying social life as being founded either in actor-micro level analyses or in structure-macro level...... by overcoming traditional micro-macro and actor-structure dimensions. However, they have also achieved this in different ways and I ask if there is a benefit to ‘importing’ some of these differences into the other approach....
Bisimulations, games, and logic
DEFF Research Database (Denmark)
Nielsen, Mogens; Clausen, Christian
1994-01-01
In a recent paper by Joyal, Nielsen, and Winskel, bisimulation is defined in an abstract and uniform way across a wide range of different models for concurrency. In this paper, following a recent trend in theoretical computer science, we characterize their abstract definition game-theoretically a......In a recent paper by Joyal, Nielsen, and Winskel, bisimulation is defined in an abstract and uniform way across a wide range of different models for concurrency. In this paper, following a recent trend in theoretical computer science, we characterize their abstract definition game......-theoretically and logically in a non-interleaving model. Our characterizations appear as surprisingly simple extensions of corresponding characterizations of interleaving bisimulation....
DEFF Research Database (Denmark)
Jensen, Lars Bang
The problematic this thesis investigates, through a specific kind of structuralism derived from a reading of Michel Foucault, Pierre Bourdieu and Gilles Deleuze, concerns how the subject becomes a science subject and potentially a scientist, with interest and literacy in science. The Logic...... of Science – a vivisection of monsters is thus an exploration of Being and Becoming in relation to Science and its Education. The investigation has been derived from, in, and connected to the Youth-to-Youth Project, a regional bridge building project in Northern Jutland in Denmark. The Youth-to-Youth Project...... (2011-2015) attempts to facilitate contact and provide a different kind of counselling and guidance between youths and youths who are ‘one step ahead’ in their educational trajectory. The meetings between the youths are both social and science subject oriented, and the intention is to establish...
Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)
2002-01-01
This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.
Lu, Jiao Yang; Zhang, Xin Xing; Huang, Wei Tao; Zhu, Qiu Yan; Ding, Xue Zhi; Xia, Li Qiu; Luo, Hong Qun; Li, Nian Bing
2017-09-19
The most serious and yet unsolved problems of molecular logic computing consist in how to connect molecular events in complex systems into a usable device with specific functions and how to selectively control branchy logic processes from the cascading logic systems. This report demonstrates that a Boolean logic tree is utilized to organize and connect "plug and play" chemical events DNA, nanomaterials, organic dye, biomolecule, and denaturant for developing the dual-signal electrochemical evolution aptasensor system with good resettability for amplification detection of thrombin, controllable and selectable three-state logic computation, and keypad lock security operation. The aptasensor system combines the merits of DNA-functionalized nanoamplification architecture and simple dual-signal electroactive dye brilliant cresyl blue for sensitive and selective detection of thrombin with a wide linear response range of 0.02-100 nM and a detection limit of 1.92 pM. By using these aforementioned chemical events as inputs and the differential pulse voltammetry current changes at different voltages as dual outputs, a resettable three-input biomolecular keypad lock based on sequential logic is established. Moreover, the first example of controllable and selectable three-state molecular logic computation with active-high and active-low logic functions can be implemented and allows the output ports to assume a high impediment or nothing (Z) state in addition to the 0 and 1 logic levels, effectively controlling subsequent branchy logic computation processes. Our approach is helpful in developing the advanced controllable and selectable logic computing and sensing system in large-scale integration circuits for application in biomedical engineering, intelligent sensing, and control.
Ochoa, Agustin
2016-01-01
This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...
Japanese Logic Puzzles and Proof
Wanko, Jeffrey J.
2009-01-01
An understanding of proof does not start in a high school geometry course. Rather, attention to logical reasoning throughout a student's school experience can help the development of proof readiness. In the spirit of problem solving, the author has begun to use some Japanese logic puzzles other than sudoku to help students develop additional…
DEFF Research Database (Denmark)
By blending historical research with current research, this collection (loosely inspired by themes from the work of Arthur Prior) demonstrates the importance of Prior's writings and helps us to gain a deeper understanding of time, its logic(s), and its language(s)....
Propositional inquisitive logic: a survey
Directory of Open Access Journals (Sweden)
Ivano Ciardelli
2016-12-01
Full Text Available This paper provides a concise survey of a body of recent work on propositional inquisitive logic. We review the conceptual foundations of inquisitive semantics, introduce the propositional system, discuss its relations with classical, intuitionistic, and dependence logic, and describe an important feature of inquisitive proofs.
Contextual Validity in Hybrid Logic
DEFF Research Database (Denmark)
Blackburn, Patrick Rowan; Jørgensen, Klaus Frovin
2013-01-01
Hybrid tense logic is an extension of Priorean tense logic in which it is possible to refer to times using special propositional sym- bols called nominals. Temporal indexicals are expressions such as now, yesterday, today, tomorrow and four days ago that have highly context- dependent interpretat...
Public communication in justification logic
Renne, Bryan
2011-01-01
Justification Logic is a framework for reasoning about evidence and justification in multi-agent systems. Most accounts of Justification Logic are essentially static, in that the (justified) beliefs of agents are immutable. In this article, we add public communication, a dynamic operation of belief
Methods in Logic Based Control
DEFF Research Database (Denmark)
Christensen, Georg Kronborg
1999-01-01
Desing and theory of Logic Based Control systems.Boolean Algebra, Karnaugh Map, Quine McClusky's algorithm. Sequential control design. Logic Based Control Method, Cascade Control Method. Implementation techniques: relay, pneumatic, TTL/CMOS,PAL and PLC- and Soft_PLC implementation. PLC...
Dynamic Logics of Belief Change
van Benthem, J.; Smets, S.; van Ditmarsch, H.; Halpern, J.; van der Hoek, W.; Kooi, B.
2015-01-01
This chapter gives an overview of current dynamic logics that describe belief update and revision, both for single agents and in multi-agent settings. We employ a mixture of ideas from AGM belief revision theory and dynamic-epistemic logics of information-driven agency. After describing the basic
Lectures on Logic and Computation
DEFF Research Database (Denmark)
The European Summer School in Logic, Language and Information (ESSLLI) is organized every year by the Association for Logic, Language and Information (FoLLI) in different sites around Europe. The main focus of ESSLLI is on the interface between linguistics, logic and computation. ESSLLI offers...... foundational, introductory and advanced courses, as well as workshops, covering a wide variety of topics within the three areas of interest: Language and Computation, Language and Logic, and Logic and Computation. During two weeks, around 50 courses and 10 workshops are offered to the attendants, each of 1...... and selected. The papers are organized in topical sections on computational complexity, multi-agant systems, natural language processing, strategies in games and formal semantics....
Logical independence and quantum randomness
Energy Technology Data Exchange (ETDEWEB)
Paterek, T; Kofler, J; Aspelmeyer, M; Zeilinger, A; Brukner, C [Institute for Quantum Optics and Quantum Information, Austrian Academy of Sciences, Boltzmanngasse 3, A-1090 Vienna (Austria); Prevedel, R; Klimek, P [Faculty of Physics, University of Vienna, Boltzmanngasse 5, A-1090 Vienna (Austria)], E-mail: tomasz.paterek@univie.ac.at
2010-01-15
We propose a link between logical independence and quantum physics. We demonstrate that quantum systems in the eigenstates of Pauli group operators are capable of encoding mathematical axioms and show that Pauli group quantum measurements are capable of revealing whether or not a given proposition is logically dependent on the axiomatic system. Whenever a mathematical proposition is logically independent of the axioms encoded in the measured state, the measurement associated with the proposition gives random outcomes. This allows for an experimental test of logical independence. Conversely, it also allows for an explanation of the probabilities of random outcomes observed in Pauli group measurements from logical independence without invoking quantum theory. The axiomatic systems we study can be completed and are therefore not subject to Goedel's incompleteness theorem.
Impossible Worlds and Logical Omniscience
DEFF Research Database (Denmark)
Bjerring, Jens Christian Krarup
2013-01-01
, and considerably less investigated challenge is to ensure that the resulting modal space can also be used to model moderately ideal agents that are not logically omniscient but nevertheless logically competent. Intuitively, while such agents may fail to rule out subtly impossible worlds that verify complex logical...... falsehoods, they are nevertheless able to rule out blatantly impossible worlds that verify obvious logical falsehoods. To model moderately ideal agents, I argue, the job is to construct a modal space that contains only possible and non-trivially impossible worlds where it is not the case that “anything goes......”. But I prove that it is impossible to develop an impossible-world framework that can do this job and that satisfies certain standard conditions. Effectively, I show that attempts to model moderately ideal agents in a world-involving framework collapse to modeling either logical omniscient agents...
Zalta on Unnecessary Logical Truths
Directory of Open Access Journals (Sweden)
MA Hojati
2013-09-01
Full Text Available According to a traditional view all logical truths are necessary however, this thesis recently has been faced with various critiques from different points of view. Introducing some logical operators, David Kaplan and Edward Zalta claim that there are logical truths regarding common definition ‒ that are not necessary. William Hanson objects Zalta's examples believing that they rely on unjustified presuppositions especially he does not accept real world validity as a proper notion for presenting logical truth. Nelson and Zalta reply to his objections claiming that they have unacceptable grounds. In this paper, we introduce logical truths, then present Kaplan's and Zalta's examples and explore Hanson's objections together with their replies. At last we try to show the metaphysical roots of the debates.
G4-FETs as Universal and Programmable Logic Gates
Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin
2007-01-01
An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.
Delay analysis of combinations of pass transistors and classical logic gates
Gibson, Jonathan S.
1993-01-01
Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.
Quantum error correction in superconducting circuits
Devoret, Michel
Can we prolong the coherence of a two-state manifold in a complex quantum system beyond the coherence of its longest-lived component? This question is the starting point of the main challenges in the construction of a scalable quantum computer, namely the implementation of quantum error correction. The presentation will review the experimental progress that recently occurred in the field of superconducting quantum circuits towards the correction, for a full logical qubit memory, of the combinations of bit flip and phase flip errors. Work supported by ARO and YINQE.
Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi
The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.
Thermal rectification in nonlinear quantum circuits
DEFF Research Database (Denmark)
Ruokola, T.; Ojanen, T.; Jauho, Antti-Pekka
2009-01-01
We present a theoretical study of radiative heat transport in nonlinear solid-state quantum circuits. We give a detailed account of heat rectification effects, i.e., the asymmetry of heat current with respect to a reversal of the thermal gradient, in a system consisting of two reservoirs at finite...... temperatures coupled through a nonlinear resonator. We suggest an experimentally feasible superconducting circuit employing the Josephson nonlinearity to realize a controllable low-temperature heat rectifier with a maximal asymmetry of the order of 10%. We also discover a parameter regime where...
Verification of Building Blocks for Asynchronous Circuits
Directory of Open Access Journals (Sweden)
Freek Verbeek
2013-04-01
Full Text Available Scalable formal verification constitutes an important challenge for the design of asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We present our approach to using ACL2 to verify necessary and sufficient conditions over asynchronous delay-insensitive primitives. These conditions are used to derive SAT/SMT instances from circuits built out of these primitives. These SAT/SMT instances help in establishing absence of deadlocks. Our verification effort consists of building an executable checker in the ACL2 logic tailored for our purpose. We prove that this checker is correct. This approach enables us to prove ACL2 theorems involving defun-sk constructs and free variables fully automatically.
Engineering embedded systems physics, programs, circuits
Hintenaus, Peter
2015-01-01
This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation. Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use. Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like ...
Silica-on-silicon waveguide quantum circuits.
Politi, Alberto; Cryan, Martin J; Rarity, John G; Yu, Siyuan; O'Brien, Jeremy L
2008-05-02
Quantum technologies based on photons will likely require an integrated optics architecture for improved performance, miniaturization, and scalability. We demonstrate high-fidelity silica-on-silicon integrated optical realizations of key quantum photonic circuits, including two-photon quantum interference with a visibility of 94.8 +/- 0.5%; a controlled-NOT gate with an average logical basis fidelity of 94.3 +/- 0.2%; and a path-entangled state of two photons with fidelity of >92%. These results show that it is possible to directly "write" sophisticated photonic quantum circuits onto a silicon chip, which will be of benefit to future quantum technologies based on photons, including information processing, communication, metrology, and lithography, as well as the fundamental science of quantum optics.
Indian Academy of Sciences (India)
ment of Civil Engineering and is presently the. Chairman of Center for. Sustainable Technologies,. Indian Institute of Science,. Bangalore. His research areas include, unsaturated soil behaviour, hazardous waste management, water quality and remediation of contaminated water. Keywords. Osmosis, reverse osmosis,.
Indian Academy of Sciences (India)
and is an Associate Faculty at Center for Sustainable. Technologies, Indian. Institute of Science,. Bangalore. His research areas include, unsaturated soil behaviour, hazardous waste management, water quality and remediation of contaminated water. Keywords. Osmosis, reverse osmosis, desalinatiion, seawater, water.
Indian Academy of Sciences (India)
/fulltext/reso/012/05/0037-0040. Keywords. Osmosis; reverse osmosis; desalinatiion; seawater; water purification. Author Affiliations. Sudhakar M Rao1. Department of Civil Engineering, Indian Institute of Science, Bangalore 560012, India.
Largey, Gale
1977-01-01
Notes that difficult questions arise concerning the use of sterilization for alleged eugenic and euthenic purposes. Thus, how reversible sterilization will be used with relation to the poor, mentally ill, mentally retarded, criminals, and minors, is questioned. (Author/AM)
Implicational (semilinear) logics III: completeness properties
Czech Academy of Sciences Publication Activity Database
Cintula, Petr; Noguera, Carles
First Online: 31 July 2017 (2018) ISSN 0933-5846 R&D Projects: GA ČR GA13-14654S EU Projects: European Commission(XE) 689176 - SYSMICS Institutional support: RVO:67985807 ; RVO:67985556 Keywords : abstract algebraic logic * protoalgebraic logics * implicational logics * disjunctional logics * semilinear logics * non-classical logics * completeness theorems * rational completeness Subject RIV: BA - General Mathematics; BA - General Mathematics (UTIA-B) Impact factor: 0.394, year: 2016
PPRM-based approach to synthesis of reversible functions
Jegier, Jerzy; Kerntopf, Paweł
2017-08-01
This work proposes a PPRM-based technique for the synthesis of reversible circuits with reduced quantum cost (QC) in generated circuits. Initially, a PPRM cube-list structure is provided as input. Next, the PPRM cubes shared by coordinate functions of a given reversible function are grouped together and each cube is translated to a group of Toffoli reversible gates, similarly to ESOP-based methods. Experimental results show that for important benchmarks with up to 17 variables the presented approach generates circuits with smaller QC than the most successful previous approaches.
Logic regression and its extensions.
Schwender, Holger; Ruczinski, Ingo
2010-01-01
Logic regression is an adaptive classification and regression procedure, initially developed to reveal interacting single nucleotide polymorphisms (SNPs) in genetic association studies. In general, this approach can be used in any setting with binary predictors, when the interaction of these covariates is of primary interest. Logic regression searches for Boolean (logic) combinations of binary variables that best explain the variability in the outcome variable, and thus, reveals variables and interactions that are associated with the response and/or have predictive capabilities. The logic expressions are embedded in a generalized linear regression framework, and thus, logic regression can handle a variety of outcome types, such as binary responses in case-control studies, numeric responses, and time-to-event data. In this chapter, we provide an introduction to the logic regression methodology, list some applications in public health and medicine, and summarize some of the direct extensions and modifications of logic regression that have been proposed in the literature. Copyright © 2010 Elsevier Inc. All rights reserved.
Design structure for in-system redundant array repair in integrated circuits
Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.
2008-11-25
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.
Voltage-driven spintronic logic gates in graphene nanoribbons.
Zhang, WenXing
2014-09-10
Electronic devices lose efficacy due to quantum effect when the line-width of gate decreases to sub-10 nm. Spintronics overcome this bottleneck and logic gates are building blocks of integrated circuits. Thus, it is essential to control electronic transport of opposite spins for designing a spintronic logic gate, and spin-selective semiconductors are natural candidates such as zigzag graphene nanoribbons (ZGNR) whose edges are ferromagnetically ordered and antiferromagnetically coupled with each other. Moreover, it is necessary to sandwich ZGNR between two ferromagnetic electrodes for making a spintronic logic gate and also necessary to apply magnetic field to change the spin orientation for modulating the spin transport. By first principle calculations, we propose a method to manipulate the spin transport in graphene nanoribbons with electric field only, instead of magnetic field. We find that metal gates with specific bias nearby edges of ZGNR build up an in-plane inhomogeneous electric field which modulates the spin transport by localizing the spin density in device. The specific manipulation of spin transport we have proposed doesn't need spin-charge conversion for output and suggests a possible base for designing spintronic integrated circuit in atomic scale.
Majority logic gate for 3D magnetic computing.
Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus
2014-08-22
For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.
Sabah, Nassir H
2007-01-01
Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...