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Sample records for readout chip designed

  1. Design and Performance of the CMS Pixel Detector Readout Chip

    CERN Document Server

    Kästli, H C; Erdmann, W; Hörmann, C; Horisberger, R P; Kotlinski, D; Meier, B; Hoermann, Ch.

    2006-01-01

    The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

  2. SEU tolerant memory design for the ATLAS pixel readout chip

    International Nuclear Information System (INIS)

    Menouni, M; Barbero, M; Breugnon, P; Fougeron, D; Gensolen, F; Arutinov, D; Backhaus, M; Gonella, L; Hemperek, T; Karagounis, M; Beccherle, R; Darbo, G; Caminada, L; Dube, S; Fleury, J; Garcia-Sciveres, M; Gnani, D; Jensen, F; Gromov, V; Kluit, R

    2013-01-01

    The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

  3. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  4. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  5. Programmable System-on-Chip (PSoC) Embedded Readout Designs for Liquid Helium Level Sensors.

    Science.gov (United States)

    Parasakthi, C; Gireesan, K; Usha Rani, R; Sheela, O K; Janawadkar, M P

    2014-08-01

    This article reports the development of programmable system-on-chip (PSoC)-based embedded readout designs for liquid helium level sensors using resistive liquid vapor discriminators. The system has been built for the measurement of liquid helium level in a concave-bottomed, helmet-shaped, fiber-reinforced plastic cryostat for magnetoencephalography. This design incorporates three carbon resistors as cost-effective sensors, which are mounted at desired heights inside the cryostat and were used to infer the liquid helium level by measuring their temperature-dependent resistance. Localized electrical heating of the carbon resistors was used to discriminate whether the resistor is immersed in liquid helium or its vapor by exploiting the difference in the heat transfer rates in the two environments. This report describes a single PSoC chip for the design and development of a constant current source to drive the three carbon resistors, a multiplexer to route the sensor outputs to the analog-to-digital converter (ADC), a buffer to avoid loading of the sensors, an ADC for digitizing the data, and a display using liquid crystal display cum light-emitting diode modules. The level sensor readout designed with a single PSoC chip enables cost-effective and reliable measurement system design. © 2014 Society for Laboratory Automation and Screening.

  6. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  7. Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

    Science.gov (United States)

    Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

    2006-12-01

    We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

  8. Digital column readout architectures for hybrid pixel detector readout chips

    International Nuclear Information System (INIS)

    Poikela, T; Plosila, J; Westerlund, T; Buytaert, J; Campbell, M; Gaspari, M De; Llopart, X; Wyllie, K; Gromov, V; Kluit, R; Beuzekom, M van; Zappon, F; Zivkovic, V; Brezina, C; Desch, K; Fu, Y; Kruth, A

    2014-01-01

    In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures

  9. Silicon microstrip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Masciocchi, S.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.S.; Timm, S.; Vorwalter, K.; Werding, R.

    1995-01-01

    A new silicon strip detector has been designed for the fixed target experiment WA89 at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into a FASTBUS memory. The detector provides a fast readout by offering zero-suppressed data extraction on the chip. The silicon counters are the largest detectors built on a monocrystal so far in order to achieve good transversal acceptance. Construction and performance during the 1993 data taking run are discussed. ((orig.))

  10. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    International Nuclear Information System (INIS)

    Trimpl, M.

    2005-12-01

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  11. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  12. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  13. LSST camera readout chip ASPIC: test tools

    International Nuclear Information System (INIS)

    Antilogus, P; Bailly, Ph; Juramy, C; Lebbolo, H; Martin, D; Jeglot, J; Moniez, M; Tocut, V; Wicek, F

    2012-01-01

    The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

  14. LSST camera readout chip ASPIC: test tools

    Science.gov (United States)

    Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

    2012-02-01

    The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

  15. The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

    CERN Document Server

    Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

  16. SVX3: A deadtimeless readout chip for silicon strip detectors

    International Nuclear Information System (INIS)

    Zimmerman, T.; Huffman, T.; Srage, J.; Stroehmer, R.; Yarema, R.; Garcia-Sciveras, M.; Luo, L.; Milgrome, O.

    1997-12-01

    A new silicon strip readout chip called the SVX3 has been designed for the 720,000 channel CDF silicon upgrade at Fermilab. SVX3 incorporates an integrator, analog delay pipeline, ADC, and data sparsification for each of 128 identical channels. Many of the operating parameters are programmable via a serial bit stream, which allows the chip to be used under a variety of conditions. Distinct features of SVX3 include use of a backside substrate contact for optimal ground referencing, and the capability of simultaneous signal acquisition and digital readout allowing deadtimeless operation in the Fermilab Tevatron

  17. Vertically integrated pixel readout chip for high energy physics

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Khalid, Farah; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2011-01-01

    We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 (micro)m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 (micro)m 2 pixels, laid out in an array of 48 x 48 pixels.

  18. Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

    International Nuclear Information System (INIS)

    Anvar, Shebli; Château, Frédéric; Le Provost, Hervé; Louis, Frédéric; Manolopoulos, Konstantinos; Moudden, Yassir; Vallage, Bertrand; Zonca, Eric

    2014-01-01

    A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described

  19. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  20. The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

    International Nuclear Information System (INIS)

    Marconi, S; Christiansen, J; Conti, E; Placidi, P; Hemperek, T

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared

  1. Radiation effects on the Viking-2 preamplifier-readout chip

    International Nuclear Information System (INIS)

    Fallot-Burghardt, W.; Hawblitzel, C.; Hofmann, W.; Knoepfle, K.T.; Seeger, M.; Brenner, R.; Nygaard, E.; Rudge, A.; Toker, O.; Weilhammer, P.; Yoshioka, K.

    1994-01-01

    We have studied the radiation sensitivity of the Viking-2 VLSI circuit which has been designed for the readout of silicon strip detectors and manufactured at Mietec in 1.5 μm CMOS technology. Both biased and unbiased chips have been irradiated with a 137 Cs γ source up to a total dose of 2 kGy (200 krad) after which all tested chips were still fully functional. We report the characteristic changes of device parameters with dose, including equivalent noise charge for different capacitive loads, and determine transistor threshold shifts and change of mobilities. ((orig.))

  2. Description of the SAltro-16 chip for gas detector readout

    CERN Document Server

    Aspell, P; Garcia Garcia, E; de Gaspari, M; Mager, M; Musa, L; Rehman, A; Trampitsch, G

    2010-01-01

    The S-ALTRO prototype chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Its architecture is based in the ALTRO (ALICE TPC Read Out) chip, being its main difference the integration of the charge shaping amplifier in the same IC. Just like ALTRO chip, the prototype architecture and programmability make it suitable for the readout of a wider class of detectors. In one single chip, 16 analogue signals from the detector are shaped, digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate up to 40MHz. After digitisation, a pipelined Data Processor is able to remove from the input signal a wide range of perturbations, related to the non- ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Data Processor is able to suppress the pulse tail within 1�...

  3. Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

    CERN Document Server

    Poikela, Tuomas; Paakkulainen, J

    2010-01-01

    The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

  4. MAROC, a generic photomultiplier readout chip

    International Nuclear Information System (INIS)

    Blin, S; Barrillon, P; La Taille, C de

    2010-01-01

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ∼ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ∼ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  5. MAROC, a generic photomultiplier readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Blin, S; Barrillon, P; La Taille, C de, E-mail: blin@lal.in2p3.f [CNRS/IN2p3/LAL-OMEGA, Universite Paris Sud, Bat.200, 91898 Orsay (France)

    2010-12-15

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( {approx} 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: {approx} 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  6. MAROC, a generic photomultiplier readout chip

    Science.gov (United States)

    Blin, S.; Barrillon, P.; de La Taille, C.

    2010-12-01

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ~ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ~ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  7. A prototype pixel readout chip for asynchronous detection applications

    International Nuclear Information System (INIS)

    Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

    1991-01-01

    A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

  8. Performance of the CAMEX64 silicon strip readout chip

    International Nuclear Information System (INIS)

    Yarema, R.J.

    1989-06-01

    The CAMEX64 is a 64 channel full custom CMOS chip designed specifically for the readout of silicon strip detectors. CAMEX which stands for CMOS Multichannel Analog MultiplEXer for Silicon Strip Detectors was designed by members of the Franhofer Institute for Microelectronic Circuits and Systems and the Max Planck Institute for Physics and Astrophysics. Each CAMEX channel has a switched capacitor charge sensitive amplifier with 4 sampling capacitors and a multiplexing scheme for reading out each of the channels on an analog bus. The device uses multiple sampling capacitors to filter and reduce input noise. Filtering is controlled through sampling techniques using external clocks. The device operates in a double correlated sampling mode and therefore cannot separate detector leakage current from a charge input. Normal operation of this device is similar to all other silicon readout chips designed and built thus far in that there is a data acquisition cycle during which charge is simultaneously accepted on all channels for a short period of time from a detector array, followed by a readout cycle where that charge or hit information is read out. This device works especially well for colliding beam experiments where the time of charge arrival is accurately known. However it can be used in fixed target or asynchronous mode where the time of charge arrival is not well known. In the asynchronous mode it appears that gain is somewhat dependent on the time interval required to decide whether or not to accept charge input information and thus the maximum signal to noise performance found with the synchronous mode may not be achieved in the asynchronous mode. 18 figs., 5 tabs

  9. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  10. TID-dependent current measurements of IBL readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Dette, Karola [TU Dortmund, Experimentelle Physik IV (Germany); CERN (Switzerland); Collaboration: ATLAS Pixel-Collaboration

    2016-07-01

    The ATLAS detector consists of several subsystems with a hybrid pixel detector as the innermost component of the tracking system. The pixel detector has been composed of three layers of silicon sensor assemblies during the first data taking run of the LHC and has been upgraded with a new 4th layer, the so-called Insertable B-Layer (IBL), in summer 2014. Each silicon sensor of the IBL is connected to a Front End readout chip (FE-I4) via bump bonds. During the first year of data taking an increase of the LV current produced by the readout chips was observed. This increase could be traced back to radiation damage inside the silicon. The dependence of the current on the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations and will be presented in this talk.

  11. Towards a new generation of pixel detector readout chips

    CERN Document Server

    Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

    2016-01-01

    The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

  12. Development and characterisation of a radiation hard readout chip for the LHCb experiment

    CERN Document Server

    Baumeister, Daniel; Stachel, Johanna

    2003-01-01

    Within this doctoral thesis parts of the radiation hard readout chip Beetle have been developed and characterised, before and after irradiation. The design work included the analogue memory with the corresponding readout amplifier as well as components of the digital control circuitry. An interface compatible with the I2C-standard and the control logic for event readout have been implemented. A scheme has been developed which ensures the robustness of the Beetle chip against Single-Event Upset (SEU). This includes the consistent use of triple-redundant memory devices together with a self-triggered correction in parts of the circuit. The Beetle ASIC is a 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier and a CR-RC pulse shaper. It features an equivalent noise charge of ENC = 497 e− +48.3 e−/pF·Cin. The analogue memory is a switched capacitor array, which provides a latency of max. 4 µs. The 128 channels are transmitted off chip in 9...

  13. SPAD array chips with full frame readout for crystal characterization

    Energy Technology Data Exchange (ETDEWEB)

    Fischer, Peter; Blanco, Roberto; Sacco, Ilaria; Ritzert, Michael [Heidelberg University (Germany); Weyers, Sascha [Fraunhofer Institute for Microelectronic Circuits and Systems (Germany)

    2015-05-18

    We present single photon sensitive 2D camera chips containing 88x88 avalanche photo diodes which can be read out in full frame mode with up to 400.000 frames per second. The sensors have an imaging area of ~5mm x 5mm covered by square pixels of ~56µm x 56µm with a ~55% fill factor in the latest chip generation. The chips contain a self triggering logic with selectable (column) multiplicities of up to >=4 hits within an adjustable coincidence time window. The photon accumulation time window is programmable as well. First prototypes have demonstrated low dark count rates of <50kHz/mm2 (SPAD area) at 10 degree C for 10% masked pixels. One chip version contains an automated readout of the photon cluster position. The readout of the detailed photon distribution for single events allows the characterization of light sharing, optical crosstalk etc., in crystals or crystal arrays as they are used in PET instrumentation. This knowledge could lead to improvements in spatial or temporal resolution.

  14. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    2018-02-02

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  15. XA readout chip characteristics and CdZnTe spectral measurements

    International Nuclear Information System (INIS)

    Barbier, L.M.; Birsa, F.; Odom, J.

    1999-01-01

    The authors report on the performance of a CdZnTe (CZT) array readout by an XA (X-ray imaging chip produced at the AMS foundry) application specific readout chip (ASIC). The array was designed and fabricated at NASA/Goddard Space Flight Center (GSFC) as a prototype for the Burst Arc-Second Imaging and Spectroscopy gamma-ray instrument. The XA ASIC was obtained from Integrated Detector and Electronics (IDE), in Norway. Performance characteristics and spectral data for 241 Am are presented both at room temperature and at -20 C. The measured noise (σ) was 2.5 keV at 60 keV at room temperature. This paper represents a progress report on work with the XA ASIC and CZT detectors. Work is continuing and in particular, larger arrays are planned for future NASA missions

  16. LHCb - SALT, a dedicated readout chip for strip detectors in the LHCb Upgrade experiment

    CERN Multimedia

    Swientek, Krzysztof Piotr

    2015-01-01

    Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout 128-channel ASIC called SALT. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analogue front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. A prototype of first 8-channel version of SALT chip, comprising all important functionalities, was submitted. Its design and possibly first tests results will be presented.

  17. Design and prototyping of a readout aggregation ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Lemke, Frank; Schatral, Sven; Bruening, Ulrich [ZITI, Universitaet Heidelberg (Germany); Som, Indranil; Bhattacharyya, Tarun [Indian Institute of Technology, Kharagpur (India); Collaboration: CBM-Collaboration

    2015-07-01

    In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.

  18. Silicon μ-strip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.; Timm, S.; Vorwalter, K.; Werding, R.

    1994-01-01

    A new silicon strip detector has been designed and constructed for a fixed target experiment at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into Fastbus memory. Construction and performance during the actual data taking run are discussed. ((orig.))

  19. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

    CERN Multimedia

    Saba, A

    2006-01-01

    2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

  20. Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

    Energy Technology Data Exchange (ETDEWEB)

    Peric, I.

    2004-08-01

    Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

  1. Implementation of a Customisable Readout Sequence for the ALICE ITS Upgrade Explorer Family Chips

    CERN Document Server

    Gazzari, Matthias

    2014-01-01

    Within the ALICE ITS upgrade R&D programme the Explorer family chips are developed featuring 11700 pixels which are split into 18 different sectors with different properties. These pixels are read out sequentially leading to a time span of 2.34ms between the first and last pixel. Due to the long readout time, shot noise induced by the leakage currents in the in-pixel analogue memories makes the comparison of different sensor implementations located in distant sectors on the Explorer family chips difficult. In order to reduce this noise contribution a customisable readout sequence is developed to read parts instead of the whole chip which reduces the overall readout time. This readout sequence is integrated in the existing characterisation framework in order to choose the best performing sensor implementation through pixel-by-pixel comparison without readout-induced effects.

  2. Evaluation of the x-ray response of a position-sensitive microstrip detector with an integrated readout chip

    International Nuclear Information System (INIS)

    Rossington, C.; Jaklevic, J.; Haber, C.; Spieler, H.; Reid, J.

    1990-08-01

    The performance of an SVX silicon microstrip detector and its compatible integrated readout chip have been evaluated in response to Rh Kα x-rays (average energy 20.5 keV). The energy and spatial discrimination capabilities, efficient data management and fast readout rates make it an attractive alternative to the CCD and PDA detectors now being offered for x-ray position sensitive diffraction and EXAFS work. The SVX system was designed for high energy physics applications and thus further development of the existing system is required to optimize it for use in practical x-ray experiments. For optimum energy resolution the system noise must be decreased to its previously demonstrated low levels of 2 keV FWHM at 60 keV or less, and the data handling rate of the computer must be increased. New readout chips are now available that offer the potential of better performance. 15 refs., 7 figs

  3. Analyses of test beam data for the ATLAS upgrade readout chip (ABC130)

    Energy Technology Data Exchange (ETDEWEB)

    Peschke, Richard [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

    2015-07-01

    As part of the ATLAS phase II upgrade it is planned to replace the current tracker with an all silicon tracker. The outer part of the new tracker will consist of silicon strip detectors. For the readout of the strip detector a new Analog to Binary Converter chip (ABC130) was designed. The chip is processed in the 130 nm technology. In laboratory measurements the preamplifier of the new ABC130 showed a significant lower gain than expected. From the measurements in the laboratory it was not possible to distinguish if the malfunction is in the preamplifier or in the test circuit. Therefore an unbiased test was mandatory. Among other measurements, one was a test beam campaign at the Stanford Linear Accelerator Collider (SLAC). The result of measurement is shown in the presentation.

  4. A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2018-01-01

    Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

  5. The GOTTHARD charge integrating readout detector: design and characterization

    International Nuclear Information System (INIS)

    Mozzanica, A; Bergamaschi, A; Dinapoli, R; Greiffenberg, D; Henrich, B; Johnson, I; Valeria, R; Schmitt, B; Xintian, S; Graafsma, H; Lohmann, M

    2012-01-01

    A charge integrating readout ASIC (Application Specific Integrated Circuit) for silicon strip sensors has been developed at PSI in collaboration with DESY. The goal of the project is to provide a charge integrating readout system able to cope with the pulsed beam of XFEL machines and at the same time to retain the high dynamic range and single photon resolution performances typical for photon counting systems. The ASIC, designed in IBM 130 nm CMOS technology, takes advantage of its three gain stages with automatic stage selection to achieve a dynamic range of 10000 12 keV photons and a noise better than 300 e.n.c.. The 4 analog outputs of the ASIC are optimized for speed, allowing frame rates higher than 1 MHz, without compromises on linearity and noise performances. This work presents the design features of the ASIC, and reports the characterization results of the chip itself.

  6. Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

    CERN Document Server

    AUTHOR|(SzGeCERN)394193

    2016-01-01

    A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

  7. D-Zero muon readout electronics design

    International Nuclear Information System (INIS)

    Baldin, B.; Hansen, S.; Los, S.; Matveev, M.; Vaniev, V.

    1996-11-01

    The readout electronics designed for the D null Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the D null Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16- bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed

  8. Readout electronic for multichannel detectors

    CERN Document Server

    Kulibaba, V I; Naumov, S V

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

  9. Readout electronic for multichannel detectors

    International Nuclear Information System (INIS)

    Kulibaba, V.I.; Maslov, N.I.; Naumov, S.V.

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc

  10. Qualification method for a 1 MGy-tolerant front-end chip designed in 65 nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER

    Energy Technology Data Exchange (ETDEWEB)

    Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Cao, Ying [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Casellas, Laura Mont; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy (F4E), c/Josep, no. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. (OTL), 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); Hamilton, David [ITER Organisation (IO), Route de Vinon-sur-Verdon, CS 90 046, 13067 St. Paul les Durance Cedex (France); Steyaert, Michiel [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KU Leuven, ESAT, Advanced Integrated Sensing Lab (AdvISe), Kleinhoefstraat 4, 2440 Geel (Belgium)

    2015-10-15

    This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10 kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.

  11. A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Irmler, C., E-mail: christian.irmler@oeaw.ac.at [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Bergauer, T.; Frankenberger, A.; Friedl, M.; Gfall, I. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Higuchi, T. [University of Tokyo, Kavli Institute for Physics and Mathematics of the Universe, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8583 (Japan); Ishikawa, A. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Joo, C. [Seoul National University, High Energy Physics Laboratory, 25-107 Shinlim-dong, Kwanak-gu, Seoul 151-742 (Korea, Republic of); Kah, D.H.; Kang, K.H. [Kyungpook National University, Department of Physics, 1370 Sankyuk Dong, Buk Gu, Daegu 702-701 (Korea, Republic of); Rao, K.K. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Kato, E. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Mohanty, G.B. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Negishi, K. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Onuki, Y.; Shimizu, N. [University of Tokyo, Department of Physics, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 (Japan); Tsuboyama, T. [KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Valentan, M. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria)

    2013-12-21

    B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure. In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor. This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO{sub 2} system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder. We present the concept and the assembly procedure of the Origami chip-on-sensor modules.

  12. A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

    International Nuclear Information System (INIS)

    Irmler, C.; Bergauer, T.; Frankenberger, A.; Friedl, M.; Gfall, I.; Higuchi, T.; Ishikawa, A.; Joo, C.; Kah, D.H.; Kang, K.H.; Rao, K.K.; Kato, E.; Mohanty, G.B.; Negishi, K.; Onuki, Y.; Shimizu, N.; Tsuboyama, T.; Valentan, M.

    2013-01-01

    B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure. In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor. This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO 2 system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder. We present the concept and the assembly procedure of the Origami chip-on-sensor modules

  13. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Science.gov (United States)

    Claus, R.; ATLAS Collaboration

    2016-07-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  14. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    International Nuclear Information System (INIS)

    Claus, R.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  15. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Science.gov (United States)

    Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R. T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A. J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Yildiz, S. C.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

  16. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    International Nuclear Information System (INIS)

    Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R.T.; Huffer, M.; Kocian, M.; Ruckman, L.; Russell, J.; Su, D.; Wittgen, M.; Iakovidis, G.; Iordanidou, K.; Moschovakos, P.; Ntekas, K.; Kwan, K.; Lankford, A.J.; Nelson, A.; Schernau, M.; Schlenker, S.; Valderanis, C.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2

  17. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Energy Technology Data Exchange (ETDEWEB)

    Claus, R., E-mail: claus@slac.stanford.edu

    2016-07-11

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  18. A 240-channel thick film multi-chip module for readout of silicon drift detectors

    International Nuclear Information System (INIS)

    Lynn, D.; Bellwied, R.; Beuttenmueller, R.; Caines, H.; Chen, W.; DiMassimo, D.; Dyke, H.; Elliott, D.; Grau, M.; Hoffmann, G.W.; Humanic, T.; Jensen, P.; Kleinfelder, S.A.; Kotov, I.; Kraner, H.W.; Kuczewski, P.; Leonhardt, B.; Li, Z.; Liaw, C.J.; LoCurto, G.; Middelkamp, P.; Minor, R.; Mazeh, N.; Nehmeh, S.; O'Conner, P.; Ott, G.; Pandey, S.U.; Pruneau, C.; Pinelli, D.; Radeka, V.; Rescia, S.; Rykov, V.; Schambach, J.; Sedlmeir, J.; Sheen, J.; Soja, B.; Stephani, D.; Sugarbaker, E.; Takahashi, J.; Wilson, K.

    2000-01-01

    We have developed a thick film multi-chip module for readout of silicon drift (or low capacitance ∼200 fF) detectors. Main elements of the module include a custom 16-channel NPN-BJT preamplifier-shaper (PASA) and a custom 16-channel CMOS Switched Capacitor Array (SCA). The primary design criteria of the module were the minimizations of the power (12 mW/channel), noise (ENC=490 e - rms), size (20.5 mmx63 mm), and radiation length (1.4%). We will discuss various aspects of the PASA design, with emphasis on the preamplifier feedback network. The SCA is a modification of an integrated circuit that has been previously described [1]; its design features specific to its application in the SVT (Silicon Vertex Tracker in the STAR experiment at RHIC) will be discussed. The 240-channel multi-chip module is a circuit with five metal layers fabricated in thick film technology on a beryllia substrate and contains 35 custom and commercial integrated circuits. It has been recently integrated with silicon drift detectors in both a prototype system assembly for the SVT and a silicon drift array for the E896 experiment at the Alternating Gradient Synchrotron at the Brookhaven National Laboratory. We will discuss features of the module's design and fabrication, report the test results, and emphasize its performance both on the bench and under experimental conditions

  19. The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2015-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

  20. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

  1. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    ATLAS CSC Collaboration; The ATLAS collaboration

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

  2. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)664042

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

  3. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    Claus, Richard; The ATLAS collaboration

    2015-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thro...

  4. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  5. Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

    Energy Technology Data Exchange (ETDEWEB)

    Loechner, S.

    2006-07-26

    The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

  6. Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

    International Nuclear Information System (INIS)

    Loechner, S.

    2006-01-01

    The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

  7. A self-adjusting delay circuit for pixel read-out chips

    International Nuclear Information System (INIS)

    Raith, B.

    1997-01-01

    A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

  8. Integration of the Omega-3 readout chip into a high energy physics experimental data acquisition system

    International Nuclear Information System (INIS)

    Beker, H.; Chesi, E.; Martinengo, P.

    1997-01-01

    The Omega-3 readout chip is presented in detail elsewhere in the same proceedings. We here describe the integration of the chip into present and future experiments describing both hardware and software aspects. We cover preliminary tests in the laboratory and on the beam. The WA97 experiment has already used a pixel telescope in the past and intends to upgrade to the Omega-3 chip. A newly proposed experiment at CERN studying strangeness production in heavy ion collisions also plans to use a similar telescope. Finally, we give an outlook on the ongoing developments in the pixel readout architecture in the context of ALICE, the heavy ion experiment at the LHC collider. (orig.)

  9. Integrated microelectronic capacitive readout subsystem for lab-on-a-chip applications

    International Nuclear Information System (INIS)

    Spathis, Christos; Georgakopoulou, Konstantina; Petrellis, Nikos; Efstathiou, Konstantinos; Birbas, Alexios

    2014-01-01

    A mixed-signal capacitive biosensor readout system is presented with its main readout functionality embedded in an integrated circuit, compatible with complementary metal oxide semiconductor-type biosensors. The system modularity allows its usage as a consumable since it eventually leads to a system-on-chip where sensor and readout circuitry are hosted on the same die. In this work, a constant current source is used for measuring the input capacitance. Compared to most capacitive biosensor readout circuits, this method offers the convenience of adjusting both the range and the resolution, depending on the requirements dictated by the application. The chip consumes less than 5 mW of power and the die area is 0.06 mm 2 . It shows a broad input capacitance range (capable of measuring bio-capacitances from 6 pF to 9.8 nF), configurable resolution (down to 1 fF), robustness to various biological experiments and good linearity. The integrated nature of the readout system is proven to be sufficient both for one-time in situ (consumable-type) bio-measurements and its incorporation into a point-of-care system. (paper)

  10. Radiation induced effects in the \\\\ATLAS Insertable B-Layer readout chip

    CERN Document Server

    The ATLAS collaboration

    2017-01-01

    The ATLAS Insertable B-Layer is the innermost pixel barrel layer of the ATLAS detector installed in 2014. During the first year of $pp$ collisions at $\\sqrt{s} = 13~{\\rm TeV}$ in 2015, an unusual increase was observed in the low voltage currents of the readout chips. This increase was found to be due to radiation damage to the chips. The dependence of the current on the total ionising dose and temperature has been studied using X-ray and proton beam sources, and will be presented in this note together with its possible parametrisation and operation guidelines for the detector.

  11. Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

    International Nuclear Information System (INIS)

    Flouzat, C.; Değerli, Y.; Guilloux, F.; Orsini, F.; Venault, P.

    2015-01-01

    In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R and D program has been performed on the design of MAPS in the 0.18 μ m CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 μ m CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision

  12. Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

    Science.gov (United States)

    Flouzat, C.; Değerli, Y.; Guilloux, F.; Orsini, F.; Venault, P.

    2015-05-01

    In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R&D program has been performed on the design of MAPS in the 0.18 μ m CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 μ m CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision.

  13. Emulation and Calibration of the SALT Read-out Chip for the Upstream Tracker for Modernised LHCb Detector

    CERN Document Server

    Dendek, Adam

    2015-01-01

    The LHCb is one of the four major experiments currently operating at CERN. The main reason for constructing the LHCb forward spectrometer was a precise measurement of the CP violation in heavy quarks section as well as search for a New Physics. To obtain interesting results, the LHCb is mainly focused on study of B meson decays. Unfortunately, due to the present data acquisition architecture, the LHCb experiment is statistically limited for collecting such events. This fact led the LHCb Collaboration to decide to perform far-reaching upgrade. Key part of this upgrade will be replacement of the TT detector. To perform this action, it was requited to design new tracking detector with entirely new front-end electronics. This detector will be called the Upstream Tracker (UT) and the read-out chip — SALT. This note presents an overall discussion on SALT chip. In particular, the emulation process of the SALT data preformed via the software written by the author.

  14. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  15. Development of Micromegas-like gaseous detectors using a pixel readout chip as collecting anode

    International Nuclear Information System (INIS)

    Chefdeville, M.

    2009-01-01

    This thesis reports on the fabrication and test of a new gaseous detector with a very large number of readout channels. This detector is intended for measuring the tracks of charged particles with an unprecedented sensitivity to single electrons of almost 100 %. It combines a metal grid for signal amplification called the Micromegas with a pixel readout chip as signal collecting anode and is dubbed GridPix. GridPix is a potential candidate for a sub-detector at a future electron linear collider (ILC) foreseen to work in parallel with the LHC around 2020--2030. The tracking capability of GridPix is best exploited if the Micromegas is integrated on the pixel chip. This integrated grid is called InGrid and is precisely fabricated by wafer post-processing. The various steps of the fabrication process and the measurements of its gain, energy resolution and ion back-flow property are reported in this document. Studies of the response of the complete detector formed by an InGrid and a TimePix pixel chip to X-rays and cosmic particles are also presented. In particular, the efficiency for detecting single electrons and the point resolution in the pixel plane are measured. Implications for a GridPix detector at ILC are discussed. (author)

  16. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  17. Design of a readout ASIC for gas detectors with self-amplification

    International Nuclear Information System (INIS)

    Deng Zhi; Liu Yinong

    2009-01-01

    A readout ASIC has been designed for gas detectors with self-amplification such as GEM and RPC. It provides amplification and shaping of the detector signals and buffers them to the free running ADCs. The charge gain and the shaping time can be adjusted. The programmability of gain and shaping time is very convenient for studying detector performance under different gas gain and also expands the application range of the chip. The ENC increases as charge gain decreases below 10 mV/fC because the noise from the shaper becomes significant. The chip is designed in Chartered 0.35μm 2P4M CMOS process. Detailed design and simulation results are described in the paper. (authors)

  18. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  19. Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Ching-Liang Dai

    2010-03-01

    Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

  20. Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

    International Nuclear Information System (INIS)

    Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

    2017-01-01

    We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

  1. Image processing system design for microcantilever-based optical readout infrared arrays

    Science.gov (United States)

    Tong, Qiang; Dong, Liquan; Zhao, Yuejin; Gong, Cheng; Liu, Xiaohua; Yu, Xiaomei; Yang, Lei; Liu, Weiyu

    2012-12-01

    Compared with the traditional infrared imaging technology, the new type of optical-readout uncooled infrared imaging technology based on MEMS has many advantages, such as low cost, small size, producing simple. In addition, the theory proves that the technology's high thermal detection sensitivity. So it has a very broad application prospects in the field of high performance infrared detection. The paper mainly focuses on an image capturing and processing system in the new type of optical-readout uncooled infrared imaging technology based on MEMS. The image capturing and processing system consists of software and hardware. We build our image processing core hardware platform based on TI's high performance DSP chip which is the TMS320DM642, and then design our image capturing board based on the MT9P031. MT9P031 is Micron's company high frame rate, low power consumption CMOS chip. Last we use Intel's company network transceiver devices-LXT971A to design the network output board. The software system is built on the real-time operating system DSP/BIOS. We design our video capture driver program based on TI's class-mini driver and network output program based on the NDK kit for image capturing and processing and transmitting. The experiment shows that the system has the advantages of high capturing resolution and fast processing speed. The speed of the network transmission is up to 100Mbps.

  2. Design of GRM phoswich detector readout system

    International Nuclear Information System (INIS)

    Liu Jiangtao; Dong Yongwei; Song Liming; Wu Bobing; Zhang Yongjie; Xu He

    2014-01-01

    A set of mixed-signal read out system was designed for the phoswich detectors of the γ-ray burst monitor in the SVOM satellite, which was used to obtain the amplitude and the width of the voltage pulse that came from the GRM phoswich detector, and classify the signals. The FPGA was used to control the timing in the system, high-speed peak holding circuit was used to get the peak of voltage pulse, and the RS232 interface was used to complete the data exchange between the system and the PC. The test results show that this design can achieve the data acquisition and the discrimination. (authors)

  3. Effect of gamma irradiation on leakage current in CMOS read-out chips for the ATLAS upgrade silicon strip tracker at the HL-LHC

    CERN Document Server

    Stucci, Stefania Antonia; Lynn, Dave; Kierstead, James; Kuczewski, Philip; van Nieuwenhuizen, Gerrit J; Rosin, Guy; Tricoli, Alessandro

    2017-01-01

    The increase of the leakage current of NMOS transistors in detector readout chips in certain 130 nm CMOS technologies during exposure to ionising radiation needs special consideration in the design of detector systems, as this can result in a large increase of the supply current and power dissipation. As part of the R&D; program for the upgrade of the ATLAS inner detector tracker for the High Luminosity upgrade of the LHC at CERN, a dedicated set of irradiations have been carried out with the $^60$Co gamma-ray source at the Brookhaven National Laboratory. Measurements will be presented that characterise the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips. The variation of the current as a function of time and total ionising dose has been studied under various conditions of dose rate, temperature and power applied to the chip. The range of variation of dose rates and temperatures has been set to be close to those expected at the High Luminosity LHC, i.e. in the range 0...

  4. Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

    2015-07-01

    The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

  5. Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

    International Nuclear Information System (INIS)

    Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

    2011-01-01

    Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

  6. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  7. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  8. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  9. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  10. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  11. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    International Nuclear Information System (INIS)

    Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

    1993-01-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

  12. A CMOS 130nm Evaluation digitzer chip for silicon strips readout

    CERN Document Server

    Da Silva, W; Dhellot, M; Fougeron, D; Genat, J F; Hermel, R; Huppert, J f; Kapusta, F; Lebbolo, H; Pham, T H; Rossel, F; Savoy-navarro, A; Sefri, R; Vilalte

    2007-01-01

    A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.

  13. Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

    International Nuclear Information System (INIS)

    Conti, E.; Marconi, S.; Christiansen, J.; Placidi, P.; Hemperek, T.

    2016-01-01

    The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified

  14. LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

    International Nuclear Information System (INIS)

    Heijne, E.H.M.; Antinori, F.; Barberis, D.

    1996-01-01

    The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

  15. A multi-channel time-to-digital converter chip for drift chamber readout

    International Nuclear Information System (INIS)

    Santos, D.M.; Chau, A.; DeBusshere, D.; Dow, S.; Flasck, J.; Levi, M.; Kirsten, F.; Su, E.

    1995-12-01

    A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8μ triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz

  16. A multi-channel time-to-digital converter chip for drift chamber readout

    International Nuclear Information System (INIS)

    Chau, A.; DeBusschere, D.; Dow, S.F.; Flasck, J.; Levi, M.E.; Kirsten, F.; Su, E.; Santos, D.M.

    1996-01-01

    A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e., 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 microm triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral nonlinearities of the TDC and the FADC are 230 ps and 9 mV, respectively

  17. Development and characterisation of a radiation hard readout chip for the LHCb outer tracker detector

    International Nuclear Information System (INIS)

    Stange, U.

    2005-01-01

    The reconstruction of charged particle tracks in the Outer Tracker detector of the LHCb experiment requires to measure the drift times of the straw tubes. A Time to Digital Converter (TDC) chip has been developed for this task. The chip integrates into the LHCb data acquisition schema and fulfils the requirements of the detector. The OTIS chip is manufactured in a commercial 0.25 μm CMOS process. A 32-channel TDC core drives the drift time measurement (25 ns measurement range, 390 ps nominal resolution) without introducing dead times. The resulting drift times are buffered until a trigger decision arrives after the fixed latency of 4 μs. In case of a trigger accept signal, the digital control core processes and transmits the corresponding data to the following data acquisition stage. Drift time measurement and data processing are independent from the detector occupancy. The digital control core of the OTIS chip has been developed within this doctoral thesis. It has been integrated into the TDC chip together with other constituents of the chip. Several test chips and prototype versions of the TDC chip have been characterised. The present version of the chip OTIS1.2 fulfils all requirements and is ready for mass production. (Orig.)

  18. Design of readout electronics for a scintillating plate calorimeter

    International Nuclear Information System (INIS)

    Crawley, H.B.; Meyer, W.T.; Rosenberg, E.I.; Thomas, W.D.; Blair, R.E.; Buehring, A.; Dawson, J.; Hill, N.; Noland, R.; Petereit, E.; Price, L.E.; Proudfoot, J.; Spinka, H.; Talaga, R.; Trost, H.J.; Underwood, D.; Wickland, A.B.; Hurlbut, C.; Hagopian, V.; Johnson, K.; Imlay, R.; McNeil, R.; Metcalf, W.; Bolen, L.; Cremaldi, L.; Reidy, J.; Summers, D.; Fu, P.; Gabriel, T.; Handler, T.; Ficenec, J.R.; Lu, B.; Mo, L.; Piilonen, L.E.; Nunamaker, T.; Burke, M.; Hackworth, D.T.; Porter, T.F.; Ravas, R.J.; Scherbarth, D.; Swensrud, R.; Carlsmith, D.; Foudas, C.; Lackey, J.; Loveless, D.; Reeder, D.; Robb, P.; Smith, W.H.

    1990-01-01

    A scintillator calorimeter produces unique problems for the designer of readout electronics. On the one hand the narrow time structure of scintillator pulses, ∼10 nsec, is well matched to the rf structure of the SSC and gives hope of isolating information from individual beam crossings. On the other hand, the compensation mechanism and the need to broaden the pulse shape for use with analog signal sampling devices gives a somewhat wider time structure, ∼50-100 nsec. Furthermore the granularity of such a device implies that the full energy of an electromagnetic shower may be totally contained within one readout channel. If the resolution of the electronics is not to compromise the intrinsic resolution of the calorimeter, assumed to be σ/E ∼ 15%/√E + 1% (E in Gev), coverage of the full dynamic range (40,000:1) requires at least two 12-bit devices with 7 bits of overlap for a linear front-end electronics chain. The positioning of the electronics also is a critical issue. At luminosities of 10 33 cm -2 sec -1 , electronics placed on the calorimeter must withstand doses of at least 10 10 neutron/cm 2 and 2,000 Rad per year at 90 degree. In the past year, the scintillating calorimeter collaboration has begun studying these and related issues. Among the work reported below is: a study related to remote location of the calorimeter electronics, a comprehensive program to evaluate the properties of FADCs capable of operation at 60-80 MHz, design of a analog memory unit and development of a benchmark system to help evaluate components under development both within and outside the authors' collaboration

  19. A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface

    Energy Technology Data Exchange (ETDEWEB)

    Chang, Hyejin; Jeong, Sinyoung; Ko, Eunbyeol; Jeong, Dae Hong, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of); Kang, Homan [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Yoon-Sik, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); School of Chemical and Biological Engineering, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Ho-Young, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Nuclear Medicine, Seoul National University Bundang Hospital, Seongnam 463-707 (Korea, Republic of)

    2015-05-15

    Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, we analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.

  20. Test and improvement of readout system based on APV25 chip for GEM detector

    International Nuclear Information System (INIS)

    Hu Shouyang; Jian Siyu; Zhou Jing; Shan Chao; Li Xinglong; Li Xia; Li Xiaomei; Zhou Yi

    2014-01-01

    Gas electron multiplier (GEM) is the most promising position sensitive gas detector. The new generation of readout electronics system includes APV25 front-end card, multi-purpose digitizer (MPD), VME controller and Linux-based acquisition software DAQ. The construction and preliminary test of this readout system were finished, and the ideal data with the system working frequency of 40 MHz and 20 MHz were obtained. The long time running test shows that the system has a very good time-stable ability. Through optimizing the software configuration and improving hardware quality, the noise level was reduced, and the signal noise ratio was improved. (authors)

  1. Design and performance of the new cathode readout proportional chambers in LASS

    International Nuclear Information System (INIS)

    Aiken, G.; Aston, D.; Dunwoodie, W.

    1980-10-01

    The design and construction of a new proportional chamber system for the LASS spectrometer are discussed. This system consists of planar and cylindrical chambers employing anode wire and cathode strip readout techniques. The good timing characteristics of anode readout combine with the excellent spatial resolution of cathode readout to provide powerful and compact detectors. Preliminary resolution data are presented along with operating characteristics of the various devices

  2. Radiation and Temperature Effects on the APV25 Readout Chip for the CMS Tracker

    CERN Document Server

    Messomo, Etam Albert Noah

    2002-01-01

    The Compact Muon Solenoid (CMS) is one of four particle detectors designed for use at the Large Hadron Collider (LHC) currently under construction at CERN, the European Laboratory for Particle Physics in Geneva. The LHC will accelerate two counterrotating beams of protons to energies of 7 TeV and produce 109 proton-proton collisions per second at a bunch-crossing frequency of 40 MHz. These collisions occuring at the centre of CMS will generate a very hostile radiation environment. The CMS sub-detector system closest to the collision point is the highly segmented Tracker, consisting of a silicon pixel detector with 45 million channels and a silicon microstrip detector with 10 million channels. The microstrip detector will be read out by the APV25, a custom-made chip manufactured in a commercial 0.25 µm CMOS microelectronics process. Radiation and temperature studies are required to ensure that the APV25 can operate reliably in the CMS environment. The radiation effects to which the APV25 could be susceptible ...

  3. Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

    Energy Technology Data Exchange (ETDEWEB)

    Harb, Ali, E-mail: ali.harb@desy.de; Mussgiller, Andreas; Hauk, Johannes

    2017-02-11

    The CMS Binary Chip (CBC) is a prototype version of the front-end read-out ASIC to be used in the silicon strip modules of the CMS outer tracking detector during the high luminosity phase of the LHC. The CBC is produced in 130 nm CMOS technology and bump-bonded to the hybrid of a double layer silicon strip module, the so-called 2S-p{sub T} module. It has 254 input channels and is designed to provide on-board trigger information to the first level trigger system of CMS, with the capability of cluster-width discrimination and high-p{sub T} track identification. In November 2013 the first 2S-p{sub T} module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2 to 4 GeV. In this paper the test setup and the results are presented.

  4. An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

    International Nuclear Information System (INIS)

    Fiorini, C.; Porro, M.

    2006-01-01

    We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

  5. Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

    2017-09-01

    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

  6. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  7. Challenges in physical chip design

    NARCIS (Netherlands)

    Otten, R.H.J.M.; Stravers, P.

    2000-01-01

    On behalf of the ICCAD-2000 Executive and Technical Program Committees, I would like to welcome you tothe International Conference on Computer-Aided Design, which will take place between November 5-9 at theSan Jose DoubleTree Hotel. The technical program for ICCAD-2000 was assembled by a program

  8. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  9. Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

    CERN Document Server

    Sivasubramaniyan, Sriram

    Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

  10. Study of Charge Diffusion in a Silicon Detector Using an Energy Sensitive Pixel Readout Chip

    CERN Document Server

    Schioppa, E. J.; van Beuzekom, M.; Visser, J.; Koffeman, E.; Heijne, E.; Engel, K. J.; Uher, J.

    2015-01-01

    A 300 μm thick thin p-on-n silicon sensor was connected to an energy sensitive pixel readout ASIC and exposed to a beam of highly energetic charged particles. By exploiting the spectral information and the fine segmentation of the detector, we were able to measure the evolution of the transverse profile of the charge carriers cloud in the sensor as a function of the drift distance from the point of generation. The result does not rely on model assumptions or electric field calculations. The data are also used to validate numerical simulations and to predict the detector spectral response to an X-ray fluorescence spectrum for applications in X-ray imaging.

  11. Origami chip-on-sensor design: progress and new developments

    International Nuclear Information System (INIS)

    Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

    2013-01-01

    The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

  12. A Fastbus-based silicon strip readout system

    International Nuclear Information System (INIS)

    Neoustroev, P.; Stepanov, V.; Svoiski, M.; Uvarov, L.; Matthew, P.; Russ, J.; Cooper, P.

    1995-01-01

    The readout system we describe here is built specifically to work with the LBL-designed SVX chip. It is typical of systems using a master sequencer module to direct the trigger and readout cycles of the sparse data source and to push data into a digitization and storage module. (orig.)

  13. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  14. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  15. Offset correction system for 128-channel self-triggering readout chip with in-channel 5-bit energy measurement functionality

    Energy Technology Data Exchange (ETDEWEB)

    Otfinowski, P., E-mail: potfin@agh.edu.pl; Grybos, P.; Szczygiel, R.; Kasinski, K.

    2015-04-21

    We report on a novel, two-stage 8-bit trimming solution dedicated for multichannel systems with reduced trim DAC area occupancy. The presented design was used for comparator offset correction in a 128-channel particle tracking, self-triggering readout system and manufactured in 180 nm CMOS process. The 8-bit trim DAC has a range of ±165 mV, current consumption of 3.2 µA and occupies an area of 37 µm×17 µm in each channel, which corresponds to a 6-bit conventional current steering DAC with similar linearity.

  16. Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

    2015-07-01

    Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

  17. Single event upset studies on the CMS tracker APV25 readout chip

    International Nuclear Information System (INIS)

    Noah, E.; Bauer, T.; Bisello, D.; Faccio, F.; Friedl, M.; Fulcher, J.R.; Hall, G.; Huhtinen, M.; Kaminsky, A.; Pernicka, M.; Raymond, M.; Wyss, J.

    2002-01-01

    The microstrip tracker for the CMS experiment at the CERN Large Hadron Collider will be read out using APV25 chips. During high luminosity running the tracker will be exposed to particle fluxes up to 10 7 cm -2 s -1 , which raises concerns that the APV25 could occasionally suffer Single Event Upsets (SEUs). The effect of SEU on the APV25 has been studied to investigate implications for CMS detector operation and from the viewpoint of detailed circuit operation, to improve the understanding of its origin and what factors affect its magnitude. Simulations were performed to reconstruct the effects created by highly ionising particles striking sensitive parts of the circuits, along with consideration of the underlying mechanisms of charge deposition, collection and the consequences. A model to predict the behaviour of the memory circuits in the APV25 has been developed and data collected from dedicated experiments using both heavy ions and hadrons have been shown to support it

  18. Evaluation of local radiation damage in silicon sensor via charge collection mapping with the Timepix read-out chip

    International Nuclear Information System (INIS)

    Platkevic, M; Jakubek, J; Jakubek, M; Pospisil, S; Zemlicka, J; Havranek, V; Semian, V

    2013-01-01

    Studies of radiation hardness of silicon sensors are standardly performed with single-pad detectors evaluating their global electrical properties. In this work we introduce a technique to visualize and determine the spatial distribution of radiation damage across the area of a semiconductor sensor. The sensor properties such as charge collection efficiency and charge diffusion were evaluated locally at many points of the sensor creating 2D maps. For this purpose we used a silicon sensor bump bonded to the pixelated Timepix read-out chip. This device, operated in Time-over-threshold (TOT) mode, allows for the direct energy measurement in each pixel. Selected regions of the sensor were intentionally damaged by defined doses (up to 10 12 particles/cm 2 ) of energetic protons (of 2.5 and 4 MeV). The extent of the damage was measured in terms of the detector response to the same ions. This procedure was performed either on-line during irradiation or off-line after it. The response of the detector to each single particle was analyzed determining the charge collection efficiency and lateral charge diffusion. We evaluated the changes of these parameters as a function of radiation dose. These features are related to the local properties such as the spatial homogeneity of the sensor. The effect of radiation damage was also independently investigated measuring local changes of signal response to γ, and X rays and alpha particles.

  19. Design of a hysteretic SQUID as the readout for a dc SQUID

    International Nuclear Information System (INIS)

    Gershenson, M.

    1991-01-01

    This paper present a design for an optimal hysteretic SQUID readout circuit for a DC SQUID, thus eliminating the need for bulky output transformers or resonance matching circuits. The hysteretic readout system, which is based in part on standard sampling theory, is compared to another similar system and shown to be superior in terms of slew rate and immunity of electromagnetic interference. The circuit will be useful in optimizing the performance of biomagnetic systems

  20. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    Seguin-Moreau, N.

    2013-01-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  1. Latest generation of ASICs for photodetector readout

    Science.gov (United States)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  2. Latest generation of ASICs for photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

  3. Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

    International Nuclear Information System (INIS)

    Snoeys, W.; Burns, M.; Campbell, M.; Cantatore, E.; Cencelli, V.; Dinapoli, R.; Heijne, E.; Jarron, P.; Lamanna, P.; Minervini, D.; Morel, M.; O'Shea, V.; Quiquempoix, V.; Bello, D.S.S.D.San Segundo; Van Koningsveld, B.; Wyllie, K.

    2001-01-01

    The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μmx425 μm pixel cells in the 256x32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32x32 array of 400 μmx425 μm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology

  4. Embedded Adaptive Optics for Ubiquitous Lab-on-a-Chip Readout on Intact Cell Phones

    Directory of Open Access Journals (Sweden)

    Pakorn Preechaburana

    2012-06-01

    Full Text Available The evaluation of disposable lab-on-a-chip (LOC devices on cell phones is an attractive alternative to migrate the analytical strength of LOC solutions to decentralized sensing applications. Imaging the micrometric detection areas of LOCs in contact with intact phone cameras is central to provide such capability. This work demonstrates a disposable and morphing liquid lens concept that can be integrated in LOC devices and refocuses micrometric features in the range necessary for LOC evaluation using diverse cell phone cameras. During natural evaporation, the lens focus varies adapting to different type of cameras. Standard software in the phone commands a time-lapse acquisition for best focal selection that is sufficient to capture and resolve, under ambient illumination, 50 μm features in regions larger than 500 × 500 μm2. In this way, the present concept introduces a generic solution compatible with the use of diverse and unmodified cell phone cameras to evaluate disposable LOC devices.

  5. Pixelized M-pi-n CdTe detector coupled to Medipix2 readout chip

    CERN Document Server

    Kalliopuska, J; Penttila, R; Andersson, H; Nenonen, S; Gadda, A; Pohjonen, H; Vanttajac, I; Laaksoc, P; Likonen, J

    2011-01-01

    We have realized a simple method for patterning an M-pi-n CdTe diode with a deeply diffused pn-junction, such as indium anode on CdTe. The method relies on removing the semiconductor material on the anode-side of the diode until the physical junction has been reached. The pixelization of the p-type CdTe diode with an indium anode has been demonstrated by patterning perpendicular trenches with a high precision diamond blade and pulsed laser. Pixelization or microstrip pattering can be done on both sides of the diode, also on the cathode-side to realize double sided detector configuration. The article compares the patterning quality of the diamond blade process, pulsed pico-second and femto-second lasers processes. Leakage currents and inter-strip resistance have been measured and are used as the basis of the comparison. Secondary ion mass spectrometry (SIMS) characterization has been done for a diode to define the pn-junction depth and to see the effect of the thermal loads of the flip-chip bonding process. Th...

  6. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  7. Design of fundamental building blocks for fast binary readout CMOS sensors used in high-energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Degerli, Yavuz [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France)], E-mail: degerli@cea.fr

    2009-04-21

    In this paper, design details of key building blocks for fast binary readout CMOS monolithic active pixel sensors developed for charged particle detection are presented. Firstly, an all-NMOS pixel architecture with in-pixel amplification and reset noise suppression which allows fast readout is presented. This pixel achieves high charge-to-voltage conversion factors (CVF) using a few number of transistors inside the pixel. It uses a pre-amplifying stage close to the detector and a simple double sampling (DS) circuitry to store the reset level of the detector. The DS removes the offset mismatches of amplifiers and the reset noise of the detector. Offset mismatches of the source follower are also corrected by a second column-level DS stage. The second important building block of these sensors, a low-power auto-zeroed column-level discriminator, is also presented. These two blocks transform the charge of the impinging particle into binary data. Finally, some experimental results obtained on CMOS chips designed using these blocks are presented.

  8. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

    CERN Document Server

    Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

    2000-01-01

    A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

  9. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  10. A low-power CMOS readout IC design for bolometer applications

    Science.gov (United States)

    Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

    2017-02-01

    A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

  11. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  12. Study of preamplifier, shaper and peak detector in readout ASIC for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Zhang Shengjun; Fan Lei; Li Xian

    2014-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout system and ASICs have been designed in China now. This project designed a multi-channel readout ASIC for general detector. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured, results will be reported in time. (authors)

  13. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  14. The design and test of VME clock distribution module of the Daya Bay RPC readout system

    International Nuclear Information System (INIS)

    Zhao Heng; Liang Hao; Zhou Yongzhao

    2011-01-01

    It describes the design of the VME Clock Distribution module of the Daya Bay RPC readout system, including the function and the hardware structure of the module and the logic design of the FPGA on the module. After the building and debugging of the module, a series of tests have been made to check its function and stability. (authors)

  15. Development and test results of a readout chip for the GERDA experiment

    CERN Document Server

    Smale, Nigel; Knöpfle, K T; Schwingenheuer, B; Trunk, U; Fallot-Burghardt, W

    2007-01-01

    This paper describes the F-CSA104 architecture and its measurement results. The F-CSA104 is for γ spectroscopy with Ge detectors. It is a low noise, fully integrated, four channel XFAB 0.6μm CMOS technology ASIC, that has been developed for the GERDA experiment. Each channel contains a charge sensitive preamplifier (CSA) followed by a 11.7MHz differential line driver. It has been particularly designed to operate in liquid argon (T = 87K/-186°C) and to have a measuring sensitivity of 660e- with an ENC of 110e-, after offline filtering with 10μs shaping, when connected to a 30pF load. Special techniques are used to improve the SNR such as a large input PMOS FET, an integrated 500MΩ CSA feedback resistor and a noise degeneration drain resistor.

  16. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  17. Essential issues in SOC design designing complex systems-on-chip

    CERN Document Server

    Lin, Youn-long Steve

    2007-01-01

    Covers issues related to system-on-chip (SoC) design. This book covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.

  18. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  19. The design and PCB layout of the CDF Run 2 calorimetry readout module

    International Nuclear Information System (INIS)

    Theresa Shaw

    1999-01-01

    The CDF Calorimetry Readout module, called the ADMEM, has been designed to contain both the analog circuitry which digitizes the phototube charge pulses, and the digital logic which supports the readout of the results through the CDF Run 2 DAQ system. The ADMEM module is a 9Ux400mm VMEbus module, which is housed in a CDF VMEbus VIPA crate. The ADMEM must support near deadtimeless operation, with data being digitized and stored for possible readout every 132ns or 7.6 Mhz. This paper will discuss the implementation of the analog and digital portions of the ADMEM module, and how the board was laid out to avoid the coupling of digital noise into the analog circuitry

  20. Design issues of a low cost lock-in amplifier readout circuit for an infrared detector

    Science.gov (United States)

    Scheepers, L.; Schoeman, J.

    2014-06-01

    In the past, high resolution thermal sensors required expensive cooling techniques making the early thermal imagers expensive to operate and cumbersome to transport, limiting them mainly to military applications. However, the introduction of uncooled microbolometers has overcome many of earlier problems and now shows great potential for commercial optoelectric applications. The structure of uncooled microbolometer sensors, especially their smaller size, makes them attractive in low cost commercial applications requiring high production numbers with relatively low performance requirements. However, the biasing requirements of these microbolometers cause these sensors to generate a substantial amount of noise on the output measurements due to self-heating. Different techniques to reduce this noise component have been attempted, such as pulsed biasing currents and the use of blind bolometers as common mode reference. These techniques proved to either limit the performance of the microbolometer or increase the cost of their implementation. The development of a low cost lock-in amplifier provides a readout technique to potentially overcome these challenges. High performance commercial lock-in amplifiers are very expensive. Using this as a readout circuit for a microbolometer will take away from the low manufacturing cost of the detector array. Thus, the purpose of this work was to develop a low cost readout circuit using the technique of phase sensitive detection and customizing this as a readout circuit for microbolometers. The hardware and software of the readout circuit was designed and tested for improvement of the signal-to-noise ratio (SNR) of the microbolometer signal. An optical modulation system was also developed in order to effectively identify the desired signal from the noise with the use of the readout circuit. A data acquisition and graphical user interface sub system was added in order to display the signal recovered by the readout circuit. The readout

  1. Development of a Timepix3 readout system based on the Merlin readout system

    International Nuclear Information System (INIS)

    Crevatin, G.; Carrato, S.; Horswell, I.; Omar, D.; Tartoni, N.; Cautero, G.

    2015-01-01

    Timepix3 chip is a new ASIC specifically designed to readout hybrid pixel detectors. The main purpose of Timepix3 is to measure the time of arrival of events. This characteristic can be exploited very effectively to develop detectors for time resolved experiments at synchrotron radiation facilities. In order to investigate how the ASIC can be applied to synchrotron experiments the Merlin readout system, developed at Diamond for the Medipix3 ASIC, has been adapted to readout the Timepix3 ASIC. The first tests of the ASIC with pulse injection and with alpha particles show that its behaviour is consistent with its nominal characteristics

  2. Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Zorzi, N. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy)]. E-mail: zorzi@itc.it; Bisogni, M.G. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Boscardin, M. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Dalla Betta, G.-F. [Dipartimento di Informatica e Telecomunicazioni, Universita di Trento, Via Sommarive 14, I-38050 Povo (Trento) (Italy); Gregori, P. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Novelli, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Piemonte, C. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Quattrocchi, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Ronchin, S. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Rosso, V. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy)

    2005-07-01

    Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 {mu}m thick silicon wafers adopting a double side n{sup +}-on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n{sup +}-pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances.

  3. Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

    International Nuclear Information System (INIS)

    Zorzi, N.; Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.-F.; Gregori, P.; Novelli, M.; Piemonte, C.; Quattrocchi, M.; Ronchin, S.; Rosso, V.

    2005-01-01

    Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 μm thick silicon wafers adopting a double side n + -on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n + -pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances

  4. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    International Nuclear Information System (INIS)

    Voronin, A; Malankin, E

    2016-01-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design. (paper)

  5. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  6. Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

    CERN Document Server

    Åkerstedt, Henrik; The ATLAS collaboration; Drake, Gary; Anderson, Kelby; Bohm, Christian; Oreglia, Mark; Tang, Fukun

    2015-01-01

    The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of ...

  7. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  8. Design and performance of TPC readout electronics for the NA49 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Bieser, F. [Lawrence Berkeley Lab., CA (United States); Cooper, G. [Lawrence Berkeley Lab., CA (United States); Cwienk, W. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Eckardt, V. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Fessler, H. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Fischer, H.G. [European Lab. for Particle Physics (CERN), Geneva (Switzerland); Gabler, F. [Frankfurt Univ. (Germany). Fachbereich 13 - Physik; Gornicki, E. [Institute of Nuclear Physics, Cracow (Poland); Hearn, W.E. [Lawrence Berkeley Lab., CA (United States); Heupke, W. [Frankfurt Univ. (Germany). Fachbereich 13 - Physik; Irmscher, D. [Lawrence Berkeley Lab., CA (United States); Jacobs, P. [Lawrence Berkeley Lab., CA (United States); Kleinfelder, S. [Lawrence Berkeley Lab., CA (United States); Lindenstruth, V. [Lawrence Berkeley Lab., CA (United States); Machowski, B. [Institute of Nuclear Physics, Cracow (Poland); Marks, K. [Lawrence Berkeley Lab., CA (United States); Milgrome, O. [Lawrence Berkeley Lab., CA (United States); Mock, A. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Noggle, T. [Lawrence Berkeley Lab., CA (United States); Pimpl, W. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Poskanzer, A.M. [Lawrence Berkeley Lab., CA (United States); Rauch, W. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Renfordt, R. [European Lab. for Particle Physics (CERN), Geneva (Switzerland)]|[Frankfurt Univ. (Germany). Fachbereich 13 -Physik; Ritter, H.G. [Lawrence Berkeley Lab., CA (United States)]|[European Lab. for Particle Physics (CERN), Geneva (Switzerland); Roehrich, D. [Frankfurt Univ. (Germany). Fachbereich 13 - Physik; Rudolph, H. [Lawrence Berkeley Lab., CA (United States); Rueschmann, G.W. [Frankfurt Univ. (Germany). Fachbereich 13 - Physik; Schaefer, E. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Seyboth, P. [Max-Planck-Institut fuer Physik, Muenchen (Germany); Seyerlein, J.

    1997-02-01

    Highly integrated readout electronics were developed and produced for the 182000 channels of the four TPCs of the NA49 heavy-ion fixed target experiment at the CERN SPS. The large number of channels, the high packing density and required cost minimization led to the choice of a custom electronics system. The requirements, the design and the performance of the electronics components are described. (orig.).

  9. Design of a trigger layout and the corresponding implementation of a 200 GB/s readout network for the ALICE transition radiation detector

    International Nuclear Information System (INIS)

    Schneider, Rolf

    2008-01-01

    Through the use of modern information technology, intelligent trigger systems are gaining more and more importance in high-energy physics. Particularly in heavy ion experiments, the large number of generated particles results in an enormous amount of data. By filtering the data at an early stage and discarding irrelevant events, the efficiency of the entire system can be raised significantly. The ALICE experiment at CERN breaks new ground in this respect. With the Transition Radiation Detector, the acquired signals are processed parallel right on the detector using more than 65 000 multi-chip modules. Via a readout network, the preprocessed data arrives at a global track reconstruction unit, which contributes to the decision whether an event is discarded or further processed. In this thesis, a trigger concept for the Transition Radiation Detector is developed and the readout network is implemented. A special challenge is to achieve an efficient interaction of the above processing stages. By means of simulations and analyses, the entire system is optimized in this regard. It turns out that the read-out process plays a decisive role. In this context, a design flow for the used ASIC is developed. The analyses show that through optimizations the extremely high demands made on this complex system can be met. During a beam time, first prototypes have successfully been tested. The entire system is currently being assembled and will be brought on line in 2008. (orig.)

  10. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  11. Design of an on-chip reflectance map

    NARCIS (Netherlands)

    Terwisscha van Scheltinga, Jeroen; Smit, Jaap; Bosma, Marco

    1995-01-01

    A reflectance map design is described which uses a minimal amount of memory for the table, in order to be applicable as an on-chip shader. The shader is designed for use with the volumetric super resolution hardware, which performs shading at supersampled locations. However, the design may be used

  12. Design and Development of a Portable Metal Chip Baler using A System Design Approach

    Directory of Open Access Journals (Sweden)

    Hassan Mohd Fahrul

    2017-01-01

    Full Text Available A large amount of metal chips at workplace will result in untidy and unsafe condition thus measurements of safety are needed in some industries, where the metal chips will be collected and put into a container until the volume is sufficient to be recycled. Due to that reason, the metal chips require a lot of spaces for storage before going to recycle. In this study, a portable metal chip baler as a device for compacting those metal chips is presented based on a system approach of engineering design. Basically, the system design evolves through four phases of development that are started from conceptual design, preliminary system design, detail design and development to system test and evaluation. The portable metal chip baler uses current technology such as pneumatic cylinder to compress the metal chips so that the system capable to operate efficiently. The output from this system is the metal chips are compacted into a block shape and a working prototype was developed to prove the concept of the system. As a summary, the conceptual design of portable metal chip baler was proven and was presented using the philosophy of the systems design approach. This tool may assists workers especially in the Small-Medium Enterprise (SME manufacturing industries, school or universities’ workshops for managing metal chips easily and systematically.

  13. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  14. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  15. Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

    2006-11-15

    The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

  16. Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

    2018-05-01

    Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

  17. Readout of the upgraded ALICE-ITS

    Science.gov (United States)

    Szczepankiewicz, A.; ALICE Collaboration

    2016-07-01

    The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb-Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

  18. Readout of the upgraded ALICE-ITS

    International Nuclear Information System (INIS)

    Szczepankiewicz, A.

    2016-01-01

    The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb–Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

  19. Readout of the upgraded ALICE-ITS

    Energy Technology Data Exchange (ETDEWEB)

    Szczepankiewicz, A., E-mail: Adam.Szczepankiewicz@cern.ch [CERN, Geneva (Switzerland); Institute of Computer Science, Warsaw University of Technology, Warsaw (Poland)

    2016-07-11

    The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb–Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

  20. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  1. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  2. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    Energy Technology Data Exchange (ETDEWEB)

    Erdinger, Florian

    2016-11-22

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  3. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  4. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Directory of Open Access Journals (Sweden)

    Ho-Chiao Chuang

    2014-06-01

    Full Text Available This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments.

  5. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Science.gov (United States)

    Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

    2014-01-01

    This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

  6. Study and optimization of the spatial resolution for detectors with binary readout

    Energy Technology Data Exchange (ETDEWEB)

    Yonamine, R., E-mail: ryo.yonamine@ulb.ac.be; Maerschalk, T.; Lentdecker, G. De

    2016-09-11

    Using simulations and analytical approaches, we have studied single hit resolutions obtained with a binary readout, which is often proposed for high granularity detectors to reduce the generated data volume. Our simulations considering several parameters (e.g. strip pitch) show that the detector geometry and an electronics parameter of the binary readout chips could be optimized for binary readout to offer an equivalent spatial resolution to the one with an analog readout. To understand the behavior as a function of simulation parameters, we developed analytical models that reproduce simulation results with a few parameters. The models can be used to optimize detector designs and operation conditions with regard to the spatial resolution.

  7. Design of an Enterobacteriaceae Pan-genome Microarray Chip

    DEFF Research Database (Denmark)

    Lukjancenko, Oksana; Ussery, David

    2010-01-01

    -density microarray chip has been designed, using 116 Enterobacteriaceae genome sequences, taking into account the enteric pan-genome. Probes for the microarray were checked in silico and performance of the chip, based on experimental strains from four different genera, demonstrate a relatively high ability...... to distinguish those strains on genus, species, and pathotype/serovar levels. Additionally, the microarray performed well when investigating which genes were found in a given strain of interest. The Enterobacteriaceae pan-genome microarray, based on 116 genomes, provides a valuable tool for determination...

  8. Study of multi-channel readout ASIC and its discrete module for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

    2013-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

  9. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    International Nuclear Information System (INIS)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-01-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e − +16.3e − /pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  10. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Zeng, Huiming; Wei, Tingcun, E-mail: weitc@nwpu.edu.cn; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e{sup −}+16.3e{sup −}/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  11. A multichannel compact readout system for single photon detection: Design and performances

    Energy Technology Data Exchange (ETDEWEB)

    Argentieri, A.G. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Cisbani, E.; Colilli, S.; Cusanno, F. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); De Leo, R. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); Marra, M. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Musico, Paolo, E-mail: Paolo.Musico@ge.infn.i [Istituto Nazionale di Fisica Nucleare, via Dodecaneso 33, 16146 Genova (Italy); Santavenere, F.; Torrioli, S. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy)

    2010-05-21

    Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested . The system can handle up to 4096 independent channels, covering an area of about 20x20cm{sup 2} with pixel size of 3x3mm{sup 2}, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3x3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

  12. A multichannel compact readout system for single photon detection: Design and performances

    Science.gov (United States)

    Argentieri, A. G.; Cisbani, E.; Colilli, S.; Cusanno, F.; De Leo, R.; Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M.; Marra, M.; Musico, Paolo; Santavenere, F.; Torrioli, S.

    2010-05-01

    Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20×20 cm2 with pixel size of 3×3 mm2, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3×3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

  13. CdTe layer structures for X-ray and gamma-ray detection directly grown on the Medipix readout-chip by MBE

    Science.gov (United States)

    Vogt, A.; Schütt, S.; Frei, K.; Fiederle, M.

    2017-11-01

    This work investigates the potential of CdTe semiconducting layers used for radiation detection directly deposited on the Medipix readout-chip by MBE. Due to the high Z-number of CdTe and the low electron-hole pair creation energy a thin layer suffices for satisfying photon absorption. The deposition takes place in a modified MBE system enabling growth rates up to 10 μm/h while the UHV conditions allow the required high purity for detector applications. CdTe sensor layers deposited on silicon substrates show resistivities up to 5.8 × 108 Ω cm and a preferred (1 1 1) orientation. However, the resistivity increases with higher growth temperature and the orientation gets more random. Additionally, the deposition of a back contact layer sequence in one process simplifies the complex production of an efficient contact on CdTe with aligned work functions. UPS measurements verify a decrease of the work function of 0.62 eV induced by Te doping of the CdTe.

  14. Readout scheme for the Baby-MIND detector

    CERN Document Server

    Noah, Etam; Cadoux, F; Favre, Y; Martinez, B; Nicola, L; Parsa, S; Rayner, M; Antonova, M; Fedotov, S; Izmaylov, A; Kleymenova, A; Khabibullin, M; Khotyantsev, A; Kudenko, Y; Likhacheva, V; Mefodiev, A; Mineev, O; Ovsiannikova, T; Shaykhiev, A; Suvorov, S; Yershov, N; Tsenov, R

    2016-01-01

    A readout scheme has been designed for the plastic scintillator bars of the Baby-MIND detector modules. This spectrometer will measure momentum and identify the charge of 1 GeV/c muons with magnetized iron plates interleaved with detector modules. One challenge the detector aims to address is that of keeping high charge identification efficiencies for momenta below 1 GeV/c where multiple scattering in the iron plates degrades momentum resolution. A front-end board has been developed, with 3 CITIROC readout chips per board and up to 96 channels. Hamamatsu MPPCs type S12571-025C photosensors were chosen for readout of wavelength shifting fibers embedded in plastic scintillators. Procurement of the MPPCs has been carried out to instrument 3000 channels in total. Design choices and first results of this readout scheme are presented.

  15. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    -synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written...... to support an invited talk at the NORCHIP’2007 conference....

  16. Three-dimensional cross point readout detector design for including depth information

    Science.gov (United States)

    Lee, Seung-Jae; Baek, Cheol-Ha

    2018-04-01

    We designed a depth-encoding positron emission tomography (PET) detector using a cross point readout method with wavelength-shifting (WLS) fibers. To evaluate the characteristics of the novel detector module and the PET system, we used the DETECT2000 to perform optical photon transport in the crystal array. The GATE was also used. The detector module is made up of four layers of scintillator arrays, the five layers of WLS fiber arrays, and two sensor arrays. The WLS fiber arrays in each layer cross each other to transport light to each sensor array. The two sensor arrays are coupled to the forward and left sides of the WLS fiber array, respectively. The identification of three-dimensional pixels was determined using a digital positioning algorithm. All pixels were well decoded, with the system resolution ranging from 2.11 mm to 2.29 mm at full width at half maximum (FWHM).

  17. A circuit design for front-end read-out electronics of beam homogeneity measurement

    International Nuclear Information System (INIS)

    She Qianshun; Su Hong; Xu Zhiguo; Ma Xiaoli; Hu Zhengguo; Mao Ruishi; Xu Hushan

    2011-01-01

    It introduces a circuit design of beam homogeneity measurement for heavy ion beam in the monitoring needs, which convert multichannel weak current from 10 pA to 100 nA of the output of parallel plate avalanche counter (PPAC) for large area with sensitive two-dimensional position to voltage signal from -2 V to -20 mV by current-voltage-converter (IVC) circuit which composed of T-feedback resistor networks, combined with data acquisition and processing system realized the beam homogeneity measurement in heavy ion tumor therapy of the Institute of Modern Physics. Experiments have shown that the circuit with speed and high precision. This circuit can be used for read-out of the beam for the Multiwire Proportional Chamber, Faraday Cup and other weak current sources. (authors)

  18. Pad readout for gas detectors using 128-channel integrated preamplifiers

    International Nuclear Information System (INIS)

    Fischer, P.; Drees, A.; Glassel, P.

    1988-01-01

    A novel two-dimensional readout scheme for gas detectors is presented which uses small metal pads with 2.54 mm pitch as an anode. The pads are read out via 128-channel VLSI low-noise preamplifier/multiplexer chips. These chips are mounted on 2.8x2.8 cm/sup 2/ modules which are directly plugged onto the detector backplane, daisy-chained with jumpers and read out sequentially. The readout has been successfully tested with a low-pressure, two-step, TMAE-filled UV-RICH detector prototype. A single electron efficiently of >90% was observed at moderate chamber gains (<10/sup 6/). The method offers high electronic amplification, low noise, and high readout speed with a very flexible and compact design, suited for space-limited applications

  19. The Retinal Readout System: a status report A Status Report

    CERN Document Server

    Litke, A M

    1999-01-01

    The 'Retinal Readout System' is being developed to study the language the eye uses to send information about the visual world to the brain. Its architecture is based on that of silicon microstrip detectors. An array of 512 microscopic electrodes picks up the signals generated by the output neurons of live retinal tissue in response to a dynamic image focused on the input neurons. These signals are amplified, filtered and multiplexed by a set of eight custom-designed VLSI readout chips, and digitized and recorded by a data acquisition system. This report describes the goals, design, and status of the system. (author)

  20. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  1. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  2. Indium phosphide-based monolithically integrated PIN waveguide photodiode readout for resonant cantilever sensors

    Energy Technology Data Exchange (ETDEWEB)

    Siwak, N. P. [Department of Electrical and Computer Engineering, Institute for Systems Research, University of Maryland, College Park, Maryland 20742 (United States); Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740 (United States); Fan, X. Z.; Ghodssi, R. [Department of Electrical and Computer Engineering, Institute for Systems Research, University of Maryland, College Park, Maryland 20742 (United States); Kanakaraju, S.; Richardson, C. J. K. [Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740 (United States)

    2014-10-06

    An integrated photodiode displacement readout scheme for a microelectromechanical cantilever waveguide resonator sensing platform is presented. III-V semiconductors are used to enable the monolithic integration of passive waveguides with active optical components. This work builds upon previously demonstrated results by measuring the displacement of cantilever waveguide resonators with on-chip waveguide PIN photodiodes. The on-chip integration of the readout provides an additional 70% improvement in mass sensitivity compared to off-chip photodetector designs due to measurement stability and minimized coupling loss. In addition to increased measurement stability, reduced packaging complexity is achieved due to the simplicity of the readout design. We have fabricated cantilever waveguides with integrated photodetectors and experimentally characterized these cantilever sensors with monolithically integrated PIN photodiodes.

  3. A compact readout system for multi-pixel hybrid photodiodes

    International Nuclear Information System (INIS)

    Datema, C.P.; Meng, L.J.; Ramsden, D.

    1999-01-01

    Although the first Multi-pixel Hybrid Photodiode (M-HPD) was developed in the early 1990s by Delft Electronic Products, the main obstacle to its application has been the lack of availability of a compact read-out system. A fast, parallel readout system has been constructed for use with the earlier 25-pixel tube with High-energy Physics applications in mind. The excellent properties of the recently developed multi-pixel hybrid photodiodes (M-HPD) will be easier to exploit following the development of the new hybrid read-out circuits described in this paper. This system will enable all of the required read-out functions to be accommodate on a single board into which the M-HPD is plugged. The design and performance of a versatile system is described in which a trigger-signal, derived from the common-side of the silicon anode in the M-HPD, is used to trigger the readout of the 60-anode pixels in the M-HPD. The multi-channel amplifier section is based on the use of a new, commercial VLSI chip, whilst the read-out sequencer uses a chip of its own design. The common anode signal is processed by a fast amplifier and discriminator to provide a trigger signal when a single event is detected. In the prototype version, the serial analogue output data-stream is processed using a PC-mounted, high speed ADC. Results obtained using the new read-out system in a compact gamma-camera and with a small muon tracking-chamber demonstrate the low-noise performance of the system. The application of this read-out system in other position-sensitive or multi-anode photomultiplier tube applications are also described

  4. Normalization and experimental design for ChIP-chip data

    Directory of Open Access Journals (Sweden)

    Alekseyenko Artyom A

    2007-06-01

    Full Text Available Abstract Background Chromatin immunoprecipitation on tiling arrays (ChIP-chip has been widely used to investigate the DNA binding sites for a variety of proteins on a genome-wide scale. However, several issues in the processing and analysis of ChIP-chip data have not been resolved fully, including the effect of background (mock control subtraction and normalization within and across arrays. Results The binding profiles of Drosophila male-specific lethal (MSL complex on a tiling array provide a unique opportunity for investigating these topics, as it is known to bind on the X chromosome but not on the autosomes. These large bound and control regions on the same array allow clear evaluation of analytical methods. We introduce a novel normalization scheme specifically designed for ChIP-chip data from dual-channel arrays and demonstrate that this step is critical for correcting systematic dye-bias that may exist in the data. Subtraction of the mock (non-specific antibody or no antibody control data is generally needed to eliminate the bias, but appropriate normalization obviates the need for mock experiments and increases the correlation among replicates. The idea underlying the normalization can be used subsequently to estimate the background noise level in each array for normalization across arrays. We demonstrate the effectiveness of the methods with the MSL complex binding data and other publicly available data. Conclusion Proper normalization is essential for ChIP-chip experiments. The proposed normalization technique can correct systematic errors and compensate for the lack of mock control data, thus reducing the experimental cost and producing more accurate results.

  5. An FPGA design flow for reconfigurable network-based multi-processor systems on chip

    NARCIS (Netherlands)

    Kumar, A.; Hansson, M.A; Huisken, J.; Corporaal, H.

    2007-01-01

    Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity

  6. Evaluation of mixed-signal noise effects in photon-counting X-ray image sensor readout circuits

    International Nuclear Information System (INIS)

    Lundgren, Jan; Abdalla, Suliman; O'Nils, Mattias; Oelmann, Bengt

    2006-01-01

    In readout electronics for photon-counting pixel detectors, the tight integration between analog and digital blocks causes the readout electronics to be sensitive to on-chip noise coupling. This noise coupling can result in faulty luminance values in grayscale X-ray images, or as color distortions in a color X-ray imaging system. An exploration of simulating noise coupling in readout circuits is presented which enables the discovery of sensitive blocks at as early a stage as possible, in order to avoid costly design iterations. The photon-counting readout system has been simulated for noise coupling in order to highlight the existing problems of noise coupling in X-ray imaging systems. The simulation results suggest that on-chip noise coupling should be considered and simulated in future readout electronics systems for X-ray detectors

  7. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  8. Frequency multiplexing for readout of spin qubits

    Energy Technology Data Exchange (ETDEWEB)

    Hornibrook, J. M.; Colless, J. I.; Mahoney, A. C.; Croot, X. G.; Blanvillain, S.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, University of Sydney, Sydney, NSW 2006 (Australia); Lu, H.; Gossard, A. C. [Materials Department, University of California, Santa Barbara, California 93106 (United States)

    2014-03-10

    We demonstrate a low loss, chip-level frequency multiplexing scheme for readout of scaled-up spin qubit devices. By integrating separate bias tees and resonator circuits on-chip for each readout channel, we realise dispersive gate-sensing in combination with charge detection based on two radio frequency quantum point contacts. We apply this approach to perform multiplexed readout of a double quantum dot in the few-electron regime and further demonstrate operation of a 10-channel multiplexing device. Limitations for scaling spin qubit readout to large numbers of multiplexed channels are discussed.

  9. Design and test of a high resolution plastic scintillating fiber detector with intensified CCD readout

    International Nuclear Information System (INIS)

    Rebourgeard, P.

    1991-01-01

    We present the design of a particle detector involving a coherent array of 100 000 plastic scintillating microfibers, with an individual core diameter around 50 micrometers, and an intensified bidimensional CCD array. We investigate both theoretically and experimentally the use of polystyrene based scintillators in optical multimodal fibers. The isotropic excitation of modes and the characteristics of energy transfers between the polystyrene matrix and the added fluorescent dyes are of particular interest. An experimental approach is proposed and applied to the development of a new binary scintillator. In order to study the transmission of the signal from the interaction area to the output face, we specify the loss factors, the resolution and the signal to noise ratio within the fiber array. The low light level at the output face of the detector leads us to use image intensifiers in photon counting mode. This requires a detailed analysis of resolutions, gain, noise and detectivity concepts. We propose to describe these strongly correlated notions by the moment generation formalism. Thus, a previous modelisation of the photoelectronic devices allows us to evaluate the performance of the readout chain. A complete detector has been assembled and tested on a high energy hadron beam; the measurements are in good agreement with the modelisation [fr

  10. Design of systems on a chip design and test

    CERN Document Server

    Reis, Ricardo; Jess, Jochen AG

    2007-01-01

    Addresses the design challenges associated with generations of the semiconductor technology. This book includes contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs.

  11. Design and characterization of the readout ASIC for the BESIII CGEM detector

    CERN Document Server

    Cossio, Fabio; Bugalho, Ricardo; Chai, Junying; Cheng, Weishuai; Da Rocha Rolo, Manuel Dionisio; Di Francesco, Agostino; Greco, Michela; Leng, Chongyang; Li, Huaishen; Maggiora, Marco; Marcello, Simonetta; Mignone, Marco; Rivetti, Angelo; Varela, Joao; Wheadon, Richard

    2018-01-01

    TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal time-of-arrival and charge measurement is provided by low-power TDCs, based on analogue interpolation techniques, and Wilkinson ADCs, with a fully-digital output. The silicon results of TIGER first prototype are presented showing its full functionality.

  12. The universal read-out controller for CBM at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Manz, Sebastian; Abel, Norbert; Gebelein, Jano [Kirchhoff-Institut fuer Physik, Heidelberg (Germany); Collaboration: CBM-Collaboration

    2011-07-01

    Since 2007 we design and develop the firmware for the read-out controller (ROC) for data acquisition of the CBM detector at FAIR. While our first implementation solely focused on the nXYTER chip, today we are also designing and implementing readout logic for the GET4 chip which is supposed to be part of the time of flight (TOF) detector. Furthermore, we fully support both Ethernet and Optical transport as two transparent solutions. This addresses the different requirements of a laboratory setup and the final detector setup respectively. The usage of a strict modularization of the Read Out Controller firmware enables us to provide an Universal ROC where front-end specific logic and transport logic can be combined in a very flexible way. Fault tolerance techniques are only required for some of those modules and hence are only implemented there.

  13. Test vehicles for CMS HGCAL readout ASIC

    CERN Document Server

    Thienpont, Damien

    2017-01-01

    This paper presents first measurement results of two test vehicles ASIC embedding some building blocks for the future CMS High Granularity CALorimeter (HGCAL) read-out ASIC. They were fabricated in CMOS 130 nm, in order to first design the Analog and Mixed-Signal blocks before going to a complete and complex chip. Such a circuit needs to achieve low noise high dynamic range charge measurement and 20 ps resolution timing capability. The results show good analog performance but with higher noise levels compared to simulations. We present the results of the preamplifiers, shapers and ADCs.

  14. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  15. The IBL Readout System

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Kugel, A; Maettig, P; Morettini, P; Polini, A; Schroer, N

    2010-01-01

    The first upgrade for the ATLAS pixel detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer having new electronics assembled an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth and also compatible with the existing system to be integrated into it. The talk will describe the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

  16. The IBL Readout System

    CERN Document Server

    Dopke, J; Flick, T; Gabrielli, A; Kugel, A; Maettig, P; Morettini, P; Polini, A; Schroer, N

    2011-01-01

    The first upgrade for the ATLAS Pixel Detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer, having new electronics, an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth, but also compatible with the existing system to be integrated into it. This paper will describe the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

  17. Chip Design Process Optimization Based on Design Quality Assessment

    Science.gov (United States)

    Häusler, Stefan; Blaschke, Jana; Sebeke, Christian; Rosenstiel, Wolfgang; Hahn, Axel

    2010-06-01

    Nowadays, the managing of product development projects is increasingly challenging. Especially the IC design of ASICs with both analog and digital components (mixed-signal design) is becoming more and more complex, while the time-to-market window narrows at the same time. Still, high quality standards must be fulfilled. Projects and their status are becoming less transparent due to this complexity. This makes the planning and execution of projects rather difficult. Therefore, there is a need for efficient project control. A main challenge is the objective evaluation of the current development status. Are all requirements successfully verified? Are all intermediate goals achieved? Companies often develop special solutions that are not reusable in other projects. This makes the quality measurement process itself less efficient and produces too much overhead. The method proposed in this paper is a contribution to solve these issues. It is applied at a German design house for analog mixed-signal IC design. This paper presents the results of a case study and introduces an optimized project scheduling on the basis of quality assessment results.

  18. Design, construction, quality checks and test results of first resistive-Micromegas read-out boards for the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00215943; The ATLAS collaboration; Kuger, Fabian

    2015-01-01

    The development work carried out at CERN to push the Micromegas technology to a new frontier is now coming to an end. The construction of the first read-out boards for the upgrade of the ATLAS muon system will demonstrate in full-scale the feasibility of this ambitious project. The read-out boards, representing the heart of the detector, are manufactured in industries, making the Micromegas for ATLAS the first MPGD for a large experiment with a relevant part industrially produced. The boards are 50 cm wide and up to 220 cm long, carrying copper strips 315 μm wide with 415 μm pitch. Interconnected resistive strips, having the same pattern as the copper strips, provide spark protection. The boards are completed by the creation of cylindrical pillars 128 μm high, 280 μm in diameter and arranged in a triangular array 7 mm aside. The total number of boards to be produced for ATLAS is 2048 of 32 different types. We will review the main design parameters of the read-out boards for the ATLAS Micromegas, following...

  19. Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

    International Nuclear Information System (INIS)

    Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

    2010-01-01

    A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

  20. A readout system for position sensitive measurements of X-ray using silicon strip detectors

    CERN Document Server

    Dabrowski, W; Grybos, P; Idzik, M; Kudlaty, J

    2000-01-01

    In this paper we describe the development of a readout system for X-ray measurements using silicon strip detectors. The limitation concerning the inherent spatial resolution of silicon strip detectors has been evaluated by Monte Carlo simulation and the results are discussed. The developed readout system is based on the binary readout architecture and consists of two ASICs: RX32 front-end chip comprising 32 channels of preamplifiers, shapers and discriminators, and COUNT32 counter chip comprising 32 20-bit asynchronous counters and the readout logic. This work focuses on the design and performance of the front-end chip. The RX32 chip has been optimised for a low detector capacitance, in the range of 1-3 pF, and high counting rate applications. It can be used with DC coupled detectors allowing the leakage current up to a few nA per strip. For the prototype chip manufactured in a CMOS process all basic parameters have been evaluated by electronic measurements. The noise below 140 el rms has been achieved for a ...

  1. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  2. Multimedia Terminal System-on-Chip Design and Simulation

    Directory of Open Access Journals (Sweden)

    Barbieri Ivano

    2005-01-01

    Full Text Available This paper proposes a design approach based on integrated architectural and system-on-chip (SoC simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW digital signal processors (DSPs, the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

  3. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  4. The readout system of the new H1 silicon detectors

    International Nuclear Information System (INIS)

    Buerger, J.; Hansen, K.; Lange, W.; Prell, S.; Zimmermann, W.; Henschel, H.; Haynes, W.J.; Noyes, G.W.; Joensson, L.; Gabathuler, K.; Horisberger, R.; Wagener, M.; Eichler, R.; Erdmann, W.; Niggli, H.; Pitzl, D.

    1995-03-01

    The H1 detector at HERA at DESY undergoes presently a major upgrade. In this context silicon strip detectors have been installed at beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 Silicon Detectors and performance data of the complete readout chain. (orig.)

  5. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif; Arsalan, Muhammad; Roy, L; Salama, Khaled N.

    2012-01-01

    with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been

  6. The rad-hard readout system of the BaBar silicon vertex tracker

    Science.gov (United States)

    Re, V.; DeWitt, J.; Dow, S.; Frey, A.; Johnson, R. P.; Kroeger, W.; Kipnis, I.; Leona, A.; Luo, L.; Mandelli, E.; Manfredi, P. F.; Nyman, M.; Pedrali-Noy, M.; Poplevin, P.; Perazzo, A.; Roe, N.; Spencer, N.

    1998-02-01

    This paper discusses the behaviour of a prototype rad-hard version of the chip developed for the readout of the BaBar silicon vertex tracker. A previous version of the chip, implemented in the 0.8 μm HP rad-soft version has been thoroughly tested in the recent times. It featured outstanding noise characteristics and showed that the specifications assumed as target for the tracker readout were met to a very good extent. The next step was the realization of a chip prototype in the rad-hard process that will be employed in the actual chip production. Such a prototype is structurally and functionally identical to its rad-soft predecessor. However, the process parameters being different, and not fully mastered at the time of design, some deviations in the behaviour were to be expected. The reasons for such deviations have been identified and some of them were removed by acting on the points that were left accessible on the chip. Other required small circuit modifications that will not affect the production schedule. The tests done so far on the rad-hard chip have shown that the noise behaviour is very close to that of the rad-soft version, that is fully adequate for the vertex detector readout.

  7. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  8. RD Collaboration Proposal: Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Chistiansen, J (CERN)

    2013-01-01

    This proposal describes a new RD collaboration to develop the next genrration of hybrid pixel readout chips for use in ATLAS and CMS PHase 2 upgrades. extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. Challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm2 ), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. This collaboration is specifically focused on design of hybrid pixel readout chips, and not on more general chip design or on other aspects of hybrid pixel technology. Participants include 7 institutes on ATLAS and 7 on CMS, plus 2 on both experiments.

  9. Design, construction and setting of a parallel plate avalanche detector with coordinate read-out

    International Nuclear Information System (INIS)

    Guillermet, C.

    1980-01-01

    This detector planned for heavy ion experiments has the following dimensions: 150x210 mm 2 . Each coordinate of the trajectory is obtained from a plane of read-out wires located half-way between the two electrodes of each gap. Position read-out is made by the delay line method. Interpolating properties cancel out the effects of quantization due to the wires. Two gaps sharing a common electrode, with their wire-planes at 90 0 , furnish the two coordinates. The common electrode (Anode) delivers a fast signal on each ion crossing. Formation of signals on the anode with their distortion by the associated circuit was calculated. Formation of signals on the wires and their distortion into the delay lines was also determined. This allowed to evaluate the influence of the various parameters leading to an optimum time and space resolution. With 252 Cf fission products, 500 ps and 0.6 mm were so obtained. Differential linearity is better than 75 μm. Pulse height analysis of the anode signals makes discrimination between lightly and heavily ionizing ions possible [fr

  10. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  11. Fast readout of the COMPASS RICH CsI-MWPC chambers

    CERN Document Server

    Abbon, P; Deschampbs, H; Kunne, F; Gerasimov, S; Ketzer, B; Konorov, I; Kravtchuk, N; Magnon, A; Neyret, D; Panebianco, S; Paul, S; Rebourgeard, P; Tessaroto, F

    2006-01-01

    A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with “slow” signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ∼3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5–6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficien...

  12. Fast readout of the COMPASS RICH CsI-MWPC photon chambers

    International Nuclear Information System (INIS)

    Abbon, P.; Delagnes, E.; Deschamps, H.; Kunne, F.; Gerasimov, S.; Ketzer, B.; Konorov, I.; Kravtchuk, N.; Magnon, A.; Neyret, D.; Panebianco, S.; Paul, S.; Rebourgeard, P.; Tessaroto, F.

    2006-01-01

    A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with 'slow' signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ∼3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5-6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficient data taking at higher trigger rate

  13. Robust design and thermal fatigue life prediction of anisotropic conductive film flip chip package

    International Nuclear Information System (INIS)

    Nam, Hyun Wook

    2004-01-01

    The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF(Anisotropic Conductive Film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue life of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear bi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design Of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2 nd DOE was conducted to obtain RSM equation for the choose 3 design parameter. The coefficient of determination (R 2 ) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for Feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430μm, and 78μm, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter

  14. Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

    Science.gov (United States)

    Holmes, Anna M.; Monaco, Lisa; Barnes, Cindy; Spearing, Scott; Jenkins, Andy; Johnson, Todd; Mayer, Derek; Cole, Helen

    2003-01-01

    The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

  15. Research on and design of key circuits in RFID tag chip for container management

    Directory of Open Access Journals (Sweden)

    Wang Wenjie

    2016-01-01

    Full Text Available This paper introduces the design of semi-passive RFID tag chip capable of monitoring container safety. A system framework complying with requirements by ISO/IEC 18000-6C is firstly presented, and then differences from the key units of common passive chip, such as switch-state monitoring circuit, power management unit and anti-shake design in baseband processor, are elaborated. The main function of such a chip is to record the container opening frequency during transportation. Finally, the realizations of each unit’s function are simulated.

  16. A novel readout integrated circuit for ferroelectric FPA detector

    Science.gov (United States)

    Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

    2017-11-01

    Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

  17. Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

    International Nuclear Information System (INIS)

    Braga, D; Hall, G; Pesaresi, M; Raymond, M; Jones, L; Murray, P; Prydderch, M

    2014-01-01

    The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version

  18. DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

    NARCIS (Netherlands)

    Stefanov, T.; Pimentel, A.; Nikolov, H.; Ha, S.; Teich, J.

    2017-01-01

    The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design

  19. Digital design update for a sun sensor on a chip

    NARCIS (Netherlands)

    Mert, O.

    2014-01-01

    In the beginning of one year project work at Moog-Bradford, the scope of my assignment was coordination of the firmware development activities as defined in the Sun Sensor on a Chip (SSOAC) proposal for ESA GSTP-5 program. As the time progressed in the proposal evaluation process, my project scope

  20. Readout electronics development for the ATLAS silicon tracker

    International Nuclear Information System (INIS)

    Borer, K.; Beringer, J.; Anghinolfi, F.; Aspell, P.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Bonino, R.; Clark, A.G.; Kambara, H.; La Marra, D.; Leger, A.; Wu, X.; Richeux, J.P.; Taylor, G.N.; Fedotov, M.; Kuper, E.; Velikzhanin, Yu.; Campbell, D.; Murray, P.; Seller, P.

    1995-01-01

    We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints. (orig.)

  1. Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

    CERN Document Server

    INSPIRE-00218480

    2016-01-01

    The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

  2. Reliable and redundat FPGAbased read-out design in the ATLAS TileCal Demonstrator

    CERN Document Server

    Akerstedt, H; The ATLAS collaboration

    2014-01-01

    The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases its luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but stays backwards compatible with the present detector system by providing analog trigger signals. The Demonstrator is comprised of 4 identical “mini-drawers”, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize the 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and detector operatio...

  3. An optical fiber-based flexible readout system for micro-pattern gas detectors

    Science.gov (United States)

    Li, C.; Feng, C. Q.; Zhu, D. Y.; Liu, S. B.; An, Q.

    2018-04-01

    This paper presents an optical fiber-based readout system that is intended to provide a general purpose multi-channel readout solution for various Micro-Pattern Gas Detectors (MPGDs). The proposed readout system is composed of several front-end cards (FECs) and a data collection module (DCM). The FEC exploits the capability of an existing 64-channel generic TPC readout ASIC chip, named AGET, to implement 256 channels readout. AGET offers FEC a large flexibility in gain range (4 options from 120 fC to 10 pC), peaking time (16 options from 50 ns to 1 us) and sampling freqency (100 MHz max.). The DCM contains multiple 1 Gbps optical fiber serial link interfaces that allow the system scaling up to 1536 channels with 6 FECs and 1 DCM. Further scaling up is possible through cascading of multiple DCMs, by configuring one DCM as a master while other DCMs in slave mode. This design offers a rapid readout solution for different application senario. Tests indicate that the nonlinearity of each channel is less than 1%, and the equivalent input noise charge is typically around 0.7 fC in RMS (root mean square), with a noise slope of about 0.01 fC/pF. The system level trigger rate limit is about 700 Hz in all channel readout mode. When in hit channel readout mode, supposing that typically 10 percent of channels are fired, trigger rate can go up to about 7 kHz. This system has been tested with Micromegas detector and GEM detector, confirming its capability in MPGD readout. Details of hardware and FPGA firmware design, as well as system performances, are described in the paper.

  4. Fundamental criteria for the design of high-performance Josephson nondestructive readout random access memory cells and experimental confirmation

    International Nuclear Information System (INIS)

    Henkels, W.H.

    1979-01-01

    Fundamental design criteria for Josephson nondestructive readout random access memory (NDRO RAM) cells are presented, within the context of an LSI array environment. Emphasis is placed upon principles which are relevant to high performance. The criteria are elucidated via a specific design which is simulated and then experimentally evaluated in a technology with a smallest critical dimension of 5 μm. The specific cell differs from previously tested Josephson NDRO cells in several respects; namely, the cell stores only approx.8Phi 0 , employs interferometer gates and an external damping resistor, allows switching into device resonances, and eliminates the need for a special initialization cycle. The cell-selection scheme, employing triple coincidence, results in larger operating margins and smaller operating currents than have previously been achieved. The large operating margins and all basic cell design criteria were experimentally verified. The experimental interferometer gate characteristics were analyzed in detail and found to be describable by simple models. In addition, it was discovered that single flux quantum transitions in the interferometer gates could be exploited beneficially in order to enhance the insensitivity of operating margins to fabrication tolerances

  5. Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

    Science.gov (United States)

    Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

    2015-09-01

    This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

  6. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  7. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.

    2017-12-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

  8. SPIDR, a general-purpose readout system for pixel ASICs

    International Nuclear Information System (INIS)

    Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

    2017-01-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

  9. Driving the SID chip: Assembly language, composition, and sound design for the C64

    Directory of Open Access Journals (Sweden)

    James Newman

    2017-12-01

    Full Text Available The MOS6581, more commonly known as the Sound Interface Device, or SID chip, was the sonic heart of the Commodore 64 home computer. By considering the chip’s development, specification, uses and creative abuses by composers and programmers, alongside its continuing legacy, this paper argues that, more than any other device, the SID chip is responsible for shaping the sound of videogame music. Compared with the brutal atonality of chips such as Atari’s TIA, the SID chip offers a complex 3-channel synthesizer with dynamic waveform selection, per-channel ADSR envelopes, multi-mode filter, ring and cross modulation. However, while the specification is sophisticated, the exploitation of the vagaries and imperfections of the chip are just as significant to its sonic character. As such, the compositional, sound design and programming techniques developed by 1980s composer-coders like Rob Hubbard and Martin Galway are central in defining the distinctive sound of C64 gameplay. Exploring the affordances of the chip and the distinctive ways they were harnessed, the argument of this paper centers on the inexorable link between the technological and the musical. Crucially, composers like Hubbard et al. developed their own bespoke low-level drivers to interface with the SID chip to create pseudo-polyphony through rapid arpeggiation and channel sharing, drum synthesis through waveform manipulation, portamento, and even sample playback. This paper analyses the indivisibility of sound design, synthesis and composition in the birth of these musical forms and aesthetics, and assesses their impact on what would go on to be defined as chiptunes.

  10. Design and Construction of an Atomic Clock on an Atom Chip

    International Nuclear Information System (INIS)

    Reinhard, Friedemann

    2009-01-01

    We describe the design and construction of an atomic clock on an atom chip, intended as a secondary standard, with a stability in the range of few 10 -13 at 1 s. This clock is based on a two-photon transition between the hyperfine states |F = 1; m F = -1> and |2; 1> of the electronic ground state of the 87 Rb atom. This transition is interrogated using a Ramsey scheme, operating on either a cloud of thermal atoms or a Bose-Einstein condensate. In contrast to atomic fountain clocks, this clock is magnetically trapped on an atom chip. We describe a theoretical model of the clock stability and the design and construction of a dedicated apparatus. It is able to control the magnetic field at the relative 10 -5 level and features a hybrid atom chip, containing DC conductors as well as a microwave transmission line for the clock interrogation. (author)

  11. Design of a large dynamics fast acquisition device: application to readout of the electromagnetic calorimeter in the ATLAS experiment

    International Nuclear Information System (INIS)

    Bussat, Jean-Marie

    1998-01-01

    The construction of the new particle accelerator, the LHC (Large Hadron Collider) at CERN is entails many research and development projects. It is the case in electronics where the problem of the acquisition of large dynamic range signals at high sampling frequencies occurs. Typically, the requirements are a dynamic range of about 65,000 (around 16 bits) at 40 MHz. Some solutions to this problem will be presented. One of them is using a commercial analog-to-digital converter. This case brings up the necessity of a signal conditioning equipment. This thesis describes a way of building such a system that will be called 'multi-gain system'. Then, an application of this method is presented. It involves the realization of an automatic gain switching integrated circuit. It is designed for the readout of the ATLAS electromagnetic calorimeter. The choice and the calculation of the components of this systems are described. They are followed by the results of some measurements done on a prototype made using the AMS 1.2μm BiCMOS foundry. Possible enhancements are also presented. We conclude on the feasibility of such a system and its various applications in a number of fields that are not restricted to particle physics. (author)

  12. Strip detectors read-out system user's guide

    International Nuclear Information System (INIS)

    Claus, G.; Dulinski, W.; Lounis, A.

    1996-01-01

    The Strip Detector Read-out System consists of two VME modules: SDR-Flash and SDR-seq completed by a fast logic SDR-Trig stand alone card. The system is a self-consistent, cost effective and easy use solution for the read-out of analog multiplexed signals coming from some of the front-end electronics chips (Viking/VA chips family, Premus 128 etc...) currently used together with solid (silicon) or gas microstrip detectors. (author)

  13. High-speed readout of high-Z pixel detectors with the LAMBDA detector

    International Nuclear Information System (INIS)

    Pennicard, D.; Smoljanin, S.; Sheviakov, I.; Xia, Q.; Rothkirch, A.; Yu, Y.; Struth, B.; Hirsemann, H.; Graafsma, H.

    2014-01-01

    High-frame-rate X-ray pixel detectors make it possible to perform time-resolved experiments at synchrotron beamlines, and to make better use of these sources by shortening experiment times. LAMBDA is a photon-counting hybrid pixel detector based on the Medipix3 chip, designed to combine a small pixel size of 55 μm, a large tileable module design, high speed, and compatibility with ''high-Z'' sensors for hard X-ray detection. This technical paper focuses on LAMBDA's high-speed-readout functionality, which allows a frame rate of 2000 frames per second with no deadtime between successive images. This takes advantage of the Medipix3 chip's ''continuous read-write'' function and highly parallelised readout. The readout electronics serialise this data and send it back to a server PC over two 10 Gigabit Ethernet links. The server PC controls the detector and receives, processes and stores the data using software designed for the Tango control system. As a demonstration of high-speed readout of a high-Z sensor, a GaAs LAMBDA detector was used to make a high-speed X-ray video of a computer fan

  14. Design of readout electronics for BES III online dose rate monitoring and protection system

    International Nuclear Information System (INIS)

    Yang Shiming; Gong Guanghua; Shao Beibei; Li Jin

    2006-01-01

    To protect the beam pipe of BES III, Si PIN diodes will be used as detectors to monitor the dose rate level near the IP area. Analog to digital conversion is selected to read out the current signals of Si PIN diodes. Several low current amplifying and measuring methods are compared, mainly describing the theory of operation, software and hardware design and performance of the A/D conversion circuit. (authors)

  15. The Role of Custom Design in ASIC Chips

    National Research Council Canada - National Science Library

    Dally, William

    1998-01-01

    The performance of an ASIC can be greatly improved without increasing design time by judiciously employing a number of custom design techniques, including floorplanning, prerouting critical signals...

  16. Design of a GaAs X-ray imaging sensor with integrated HEMT readout circuitry

    Energy Technology Data Exchange (ETDEWEB)

    Boardman, D

    2002-01-01

    A new monolithic semi-insulating (SI) GaAs sensor design for X-ray imaging applications between 10-100keV has been proposed. Monolithic pixel detectors offer a number of advantages over hybrid bump-bonded detectors, such as high device yield, low costs and are easier to produce large scale arrays. In this thesis, an investigation is made of the use of a SI GaAs wafer as both a detector element and substrate for the epitaxially grown High Electron Mobility Transistors (HEMTs). The design of the HEMT transistors, optimised for this application, were produced with the aid of the Silvaco 'Virtual Wafer Fab' simulation package. It was determined that the device characteristics would consist of a small positive threshold voltage, a low off-state drain current and high transconductance. The final HEMT transistor design, that would be integrated to a pixel detector, had a threshold voltage of 0.17V, an off-state leakage current of {approx}1nA and a transconductance of 7.4mS. A number of test detectors were characterised using an ion beam induced charge technique. Charge collection efficiency maps of the test detectors were produced to determine their quality as a X-ray detection material. From the results, the inhomogeneity of SI GaAs, homogeneity of epitaxial GaAs and granular nature of polycrystalline GaAs, were observed. The best of these detectors was used in conjunction with a commercial field effect transistor to produce a hybrid device. The charge switching nature of the hybrid device was shown and a sensitivity of 0.44pC/{mu}Gy mm{sup 2}, for a detector bias of 60V, was found. The functionality of the hybrid sensor was the same to that proposed for the monolithic sensor. The fabrication of the monolithic sensor, with an integrated HEMT transistor and external capacitor, was achieved. To reach the next stage of producing a monolithic sensor that integrates charge, requires further work in the design and the fabrication process. (author)

  17. Design of a GaAs X-ray imaging sensor with integrated HEMT readout circuitry

    International Nuclear Information System (INIS)

    Boardman, D.

    2002-01-01

    A new monolithic semi-insulating (SI) GaAs sensor design for X-ray imaging applications between 10-100keV has been proposed. Monolithic pixel detectors offer a number of advantages over hybrid bump-bonded detectors, such as high device yield, low costs and are easier to produce large scale arrays. In this thesis, an investigation is made of the use of a SI GaAs wafer as both a detector element and substrate for the epitaxially grown High Electron Mobility Transistors (HEMTs). The design of the HEMT transistors, optimised for this application, were produced with the aid of the Silvaco 'Virtual Wafer Fab' simulation package. It was determined that the device characteristics would consist of a small positive threshold voltage, a low off-state drain current and high transconductance. The final HEMT transistor design, that would be integrated to a pixel detector, had a threshold voltage of 0.17V, an off-state leakage current of ∼1nA and a transconductance of 7.4mS. A number of test detectors were characterised using an ion beam induced charge technique. Charge collection efficiency maps of the test detectors were produced to determine their quality as a X-ray detection material. From the results, the inhomogeneity of SI GaAs, homogeneity of epitaxial GaAs and granular nature of polycrystalline GaAs, were observed. The best of these detectors was used in conjunction with a commercial field effect transistor to produce a hybrid device. The charge switching nature of the hybrid device was shown and a sensitivity of 0.44pC/μGy mm 2 , for a detector bias of 60V, was found. The functionality of the hybrid sensor was the same to that proposed for the monolithic sensor. The fabrication of the monolithic sensor, with an integrated HEMT transistor and external capacitor, was achieved. To reach the next stage of producing a monolithic sensor that integrates charge, requires further work in the design and the fabrication process. (author)

  18. Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

    Science.gov (United States)

    Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

    2011-01-01

    The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

  19. Development of a chip-based ingroove microplasma source: Design, characterization, and diagnostics

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuemei; Meng, Fanying; Yuan, Xin; Yan, Yanyue; Zhao, Zhongjun; Duan, Yixiang, E-mail: yduan@scu.edu.cn [Research Center of Analytical Instrumentation, College of Chemistry and College of Life Science Sichuan University, Chengdu (China); Tang, Jie [State Key Laboratory of Transient Optics and Photonics, Xi' an Institute of Optics and Precision Mechanics of CAS, Xi' an (China)

    2014-03-10

    A chip-based ingroove microplasma source was designed for molecular emission spectrometry by using a space-confined direct current duct in air. The voltage-current characteristics of different size generators, emission spectroscopy of argon were discussed, respectively. It is found that the emission intensity of excited Ar and N{sub 2} approaches its maximum near the cathode, while OH and O peaks most likely appear close to the anode. The electron density, electronic excitation temperature, rotational temperature, and vibrational temperature of the argon plasma were also calculated. More importantly, the chip-based ingroove microplasma shows much better stability compared with its counterparts.

  20. Embedded memory design for multi-core and systems on chip

    CERN Document Server

    Mohammad, Baker

    2014-01-01

    This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit ...

  1. A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

    CERN Document Server

    Fiergolski, Adrian

    2017-01-01

    The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

  2. Power distribution and substrate noise coupling investigations on the behavioral level for photon counting imaging readout circuits

    International Nuclear Information System (INIS)

    Lundgren, Jan; Abdalla, Suliman; O'Nils, Mattias; Oelmann, Bengt

    2007-01-01

    In modern mixed-signal system design, there are increasing problems associated with noise coupling caused by switching digital parts to sensitive analog parts. As a consequence, there is a growing necessity to understand these problems. In order to avoid costly design iterations, noise coupling simulations should be initiated as early as possible in the design chain. The problems associated with on-chip noise coupling have been discovered in photon counting pixel detector readout systems, where the level of integration of analog and digital circuits is very high on a very small area, and it would appear that these problems will continue to increase for future system designs in this field. This paper deals with the functionality of utilizing behavioral level models for simulating noise coupling in these readout systems. The methods and models are described and simulation results are shown for a photon counting pixel detector readout system

  3. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Science.gov (United States)

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  4. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...... to the transaction-level model. The thesis, as a whole makes contributions by describing a design methodology for networked multiprocessor embedded systems at three layers of abstraction from system-level through transaction-level to the cycle accurate level as well as demonstrating it practically by implementing...

  5. Design of a trigger layout and the corresponding implementation of a 200 GB/s readout network for the ALICE transition radiation detector; Entwicklung des Triggerkonzepts und die entsprechende Implementierung eines 200-GB/s-Auslesenetzwerks fuer den ALICE-Uebergangsstrahlungsdetektor

    Energy Technology Data Exchange (ETDEWEB)

    Schneider, Rolf

    2008-05-19

    Through the use of modern information technology, intelligent trigger systems are gaining more and more importance in high-energy physics. Particularly in heavy ion experiments, the large number of generated particles results in an enormous amount of data. By filtering the data at an early stage and discarding irrelevant events, the efficiency of the entire system can be raised significantly. The ALICE experiment at CERN breaks new ground in this respect. With the Transition Radiation Detector, the acquired signals are processed parallel right on the detector using more than 65 000 multi-chip modules. Via a readout network, the preprocessed data arrives at a global track reconstruction unit, which contributes to the decision whether an event is discarded or further processed. In this thesis, a trigger concept for the Transition Radiation Detector is developed and the readout network is implemented. A special challenge is to achieve an efficient interaction of the above processing stages. By means of simulations and analyses, the entire system is optimized in this regard. It turns out that the read-out process plays a decisive role. In this context, a design flow for the used ASIC is developed. The analyses show that through optimizations the extremely high demands made on this complex system can be met. During a beam time, first prototypes have successfully been tested. The entire system is currently being assembled and will be brought on line in 2008. (orig.)

  6. Performance of Multithreaded Chip Multiprocessors And Implications for Operating System Design

    OpenAIRE

    Fedorova, Alexandra; Seltzer, Margo I.; Small, Christopher A.; Nussbaum, Daniel

    2005-01-01

    An operating system’s design is often influenced by the architecture of the target hardware. While uniprocessor and multiprocessor architectures are well understood, such is not the case for multithreaded chip multiprocessors (CMT) – a new generation of processors designed to improve performance of memory-intensive applications. The first systems equipped with CMT processors are just becoming available, so it is critical that we now understand how to obtain the best performance from such syst...

  7. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  8. Readout ASIC for ILC-FPCCD vertex detector

    International Nuclear Information System (INIS)

    Takubo, Yosuke; Miyamoto, Akiya; Ikeda, Hirokazu; Yamamoto, Hitoshi; Itagaki, Kennosuke; Nagamine, Tadashi; Sugimoto, Yasuhiro

    2010-01-01

    The concept of FPCCD (Fine Pixel CCD) whose pixel size is 5x5μm 2 has been proposed as vertex detector at ILC. Since FPCCD has 128 x20,000 pixels in one readout channel, its readout poses a considerable challenge. We have developed a prototype of readout ASIC to readout the large number of pixels during the inter-train gap of the ILC beam. In this paper, we report the design and performance of the readout ASIC.

  9. A peek into the world of chip design

    CERN Document Server

    CERN. Geneva; Marquina, Miguel Angel

    2005-01-01

    This lecture will give some insight into how the Microprocessor Design Group approaches the daunting task of the design of a lead microprocessor as complex as the Pentium IV while under very specific schedule constraints. For a historical perspective, we will start with a quick comparison of the complexity/performance of the Willamette and Prescott (Pentium IV) class of microprocessor with the generations before the Pentium IV (Bob was a member of the design teams for a number of lead microprocessor projects including the 486DX2, Pentium Pr

  10. Optimised cantilever biosensor with piezoresistive read-out

    DEFF Research Database (Denmark)

    Rasmussen, Peter; Thaysen, J.; Hansen, Ole

    2003-01-01

    We present a cantilever-based biochemical sensor with piezoresistive read-out which has been optimised for measuring surface stress. The resistors and the electrical wiring on the chip are encapsulated in low-pressure chemical vapor deposition (LPCVD) silicon nitride, so that the chip is well sui...

  11. A Design of a PET Detector Using Micro-Channel Plate Photomultipliers with Transmission-Line Readout.

    Science.gov (United States)

    Kim, H; Frisch, H; Chen, C-T; Genat, J-F; Tang, F; Moses, W W; Choong, W S; Kao, C-M

    2010-01-01

    A computer simulation study has been conducted to investigate the feasibility of a positron emission tomography (PET) detector design by using micro-channel plate (MCP) photomultiplier tubes (PMT) with transmission-line (TL) read-out and waveform sampling. The detector unit consisted of a 24×24 array of pixelated LSO crystals, each of which was 4×4×25 mm(3) in size, and two 102×102 mm(2) MCP-PMTs coupled to both sides of the scintillator array. The crystal (and TL) pitch was 4.25 mm and reflective medium was inserted between the crystals. The transport of the optical photons inside the scintillator were simulated by using the Geant4 package. The output pulses of the MCP-PMT/TL unit were formed by applying the measured single photo-electron response of the MCP-PMT/TL unit to each individual photon that interacts with the photo-cathode of the MCP-PMT. The waveforms of the pulses at both ends of the TL strips were measured and analyzed to produce energy and timing information for the detected event. An experimental setup was developed by employing a Photonis Planacon MCP-PMT (XP85022) and a prototype TL board for measuring the single photo-electron response of the MCP-PMT/TL. The simulation was validated by comparing the predicted output pulses to measurements obtained with a single MCP-PMT/TL coupled to an LSO crystal exposed to 511 keV gamma rays. The validated simulation was then used to investigate the performance of the proposed new detector design. Our simulation result indicates an energy resolution of ~11% at 511 keV. When using a 400-600 keV energy window, we obtain a coincidence timing resolution of ~323 ps FWHM and a coincidence detection efficiency of ~40% for normally-incident 511keV photons. For the positioning accuracy, it is determined by the pitch of the TLs (and crystals) in the direction normal to the TLs and measured to be ~2.5 mm in the direction parallel to the TLs. The energy and timing obtained at the front- and back-end of the scintillator

  12. Hybrid amplifier for calorimetry with photodiode readout

    Energy Technology Data Exchange (ETDEWEB)

    Sushkov, V V

    1994-12-31

    A hybrid surface mounted amplifier for the photodiode readout of the EM calorimeter has been developed. The main technical characteristics of the design are presented. The design able to math readout constraints for a high luminosity collider experiment is discussed. 10 refs., 2 tabs., 8 figs.

  13. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  14. Recent advances in design and fabrication of on-chip micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Wang, Chunlei

    2012-06-01

    Recent development in miniaturized electronic devices has increased the demand for power sources that are sufficiently compact and can potentially be integrated on a chip with other electronic components. Miniaturized electrochemical capacitors (EC) or micro-supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. Recently, we have developed several types of micro-supercapacitors with different structural designs and active materials. Carbon-Microelectromechanical Systems (C-MEMS) with three dimensional (3D) interdigital structures are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of pseudo-capacitive materials. More recently, we have also developed microsupercapacitor based on hybrid graphene and carbon nanotube interdigital structures. In this paper, the recent advances in design and fabrication of on-chip micro-supercapacitors are reviewed.

  15. Design of Water Temperature Control System Based on Single Chip Microcomputer

    Science.gov (United States)

    Tan, Hanhong; Yan, Qiyan

    2017-12-01

    In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

  16. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  17. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  18. Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

    Czech Academy of Sciences Publication Activity Database

    Campabadal, F.; Fleta, C.; Key, M.; Böhm, Jan; Mikeštíková, Marcela; Šťastný, Jan

    2005-01-01

    Roč. 552, - (2005), s. 292-328 ISSN 0168-9002 R&D Projects: GA MŠk 1P04LA212 Institutional research plan: CEZ:AV0Z10100502 Keywords : front-end electronics * binary readout * silicon strip detectors * application specific integrated circuits * quality assurance Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.224, year: 2005

  19. ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS

    International Nuclear Information System (INIS)

    DE GERONIMO, G.; O CONNOR, P.; KANDASAMY, A.; GROSHOLZ, J.

    2002-01-01

    A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 (micro)m CMOS and tested. Design concepts and experimental results are discussed

  20. Global Production Networks, Innovation, and Work: Why Chip and System Design in the IT Industry are Moving to Asia

    OpenAIRE

    Dieter Ernst; Boy Luethje

    2003-01-01

    This paper was prepared as an issue paper, to be discussed at the Planning Meeting of the SSRC on "Emerging Pathways to Innovation in Asia," September 12-13, 2003. The paper describes a research project that explores why chip design is moving to Asia, despite its high knowledge-intensity. Trade economists would search for an answer by looking at differences in the cost of employing a chip design engineer and comparative factor and resource endowments. However, an analysis of Asia's comparativ...

  1. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  2. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  3. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    Energy Technology Data Exchange (ETDEWEB)

    Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  4. Prototype detection unit for the CHIPS experiment

    Science.gov (United States)

    Pfützner, Maciej M.

    2017-09-01

    CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

  5. Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

    Science.gov (United States)

    Michaelides, Stylianos

    Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

  6. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    OpenAIRE

    Aliaga Varea, Ramón José; Herrero Bosch, Vicente; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo Pardo, C.; Gadea Gironés, Rafael; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-01-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz...

  7. Blood cleaner on-chip design for artificial human kidney manipulation

    Directory of Open Access Journals (Sweden)

    Suwanpayak N

    2011-05-01

    Full Text Available N Suwanpayak1, MA Jalil2, MS Aziz3, FD Ismail3, J Ali3, PP Yupapin11Nanoscale Science and Engineering Research Alliance (N'SERA, Advanced Research Center for Photonics, Faculty of Science, King Mongkut's Institute of Technology, Ladkrabang, Bangkok, Thailand; 2Ibnu Sina Institute of Fundamental Science Studies (IIS, 3Institute of Advanced Photonics Science, Nanotechnology Research Alliance, Universiti Teknologi Malaysia, Johor Bahru, MalaysiaAbstract: A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney, and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.Keywords: optical trapping, blood dialysis, blood cleaner, human kidney manipulation

  8. A custom readout electronics for the BESIII CGEM detector

    Science.gov (United States)

    Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

    2017-07-01

    For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

  9. A custom readout electronics for the BESIII CGEM detector

    International Nuclear Information System (INIS)

    Rolo, M. Da Rocha; Alexeev, M.; Amoroso, A.; Bianchi, F.; Cossio, F.; Mori, F. De; Destefanis, M.; Ferroli, R. Baldini; Chai, J.Y.; Bertani, M.; Calcaterra, A.; Capodiferro, M.; Cerioni, S.; Bettoni, D.; Canale, N.; Carassiti, V.; Chiozzi, S.; Cibinetto, G.; Ramusino, A. Cotta; Bugalho, R.

    2017-01-01

    For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM

  10. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G.; Kosel, Jü rgen

    2016-01-01

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  11. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka Pasan

    2016-08-26

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  12. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Chinthaka P. Gooneratne

    2016-08-01

    Full Text Available The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA for the manipulation of superparamagnetic beads (SPBs, and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

  13. Performance of 20:1 multiplexer for large area charge readouts in directional dark matter TPC detectors

    Science.gov (United States)

    Ezeribe, A. C.; Robinson, M.; Robinson, N.; Scarff, A.; Spooner, N. J. C.; Yuriev, L.

    2018-02-01

    More target mass is required in current TPC based directional dark matter detectors for improved detector sensitivity. This can be achieved by scaling up the detector volumes, but this results in the need for more analogue signal channels. A possible solution to reducing the overall cost of the charge readout electronics is to multiplex the signal readout channels. Here, we present a multiplexer system in expanded mode based on LMH6574 chips produced by Texas Instruments, originally designed for video processing. The setup has a capability of reducing the number of readouts in such TPC detectors by a factor of 20. Results indicate that the important charge distribution asymmetry along an ionization track is retained after multiplexed signals are demultiplexed.

  14. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...... routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower...

  15. Chip-Oriented Fluorimeter Design and Detection System Development for DNA Quantification in Nano-Liter Volumes

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2009-12-01

    Full Text Available The chip-based polymerase chain reaction (PCR system has been developed in recent years to achieve DNA quantification. Using a microstructure and miniature chip, the volume consumption for a PCR can be reduced to a nano-liter. With high speed cycling and a low reaction volume, the time consumption of one PCR cycle performed on a chip can be reduced. However, most of the presented prototypes employ commercial fluorimeters which are not optimized for fluorescence detection of such a small quantity sample. This limits the performance of DNA quantification, especially low experiment reproducibility. This study discusses the concept of a chip-oriented fluorimeter design. Using the analytical model, the current study analyzes the sensitivity and dynamic range of the fluorimeter to fit the requirements for detecting fluorescence in nano-liter volumes. Through the optimized processes, a real-time PCR on a chip system with only one nano-liter volume test sample is as sensitive as the commercial real-time PCR machine using the sample with twenty micro-liter volumes. The signal to noise (S/N ratio of a chip system for DNA quantification with hepatitis B virus (HBV plasmid samples is 3 dB higher. DNA quantification by the miniature chip shows higher reproducibility compared to the commercial machine with respect to samples of initial concentrations from 103 to 105 copies per reaction.

  16. Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

    International Nuclear Information System (INIS)

    Shen, Wei

    2012-01-01

    Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

  17. Test of the CMS microstrip silicon tracker readout and control system

    CERN Document Server

    Zghiche, A

    2001-01-01

    The Microstrip Silicon tracker of the CMS detector is designed to provide robust particle tracking and vertex reconstruction within a strong magnetic field in the high luminosity environment of the LHC. The Tracker readout system employs Front-End Driver cards to digitize and buffer the analogue data arriving via optical links from on detector pipeline chips. The control chain of the front-end electronic is built to operate via optical fibers in order to shield the communications from the outside noise. Components close to the final design have been assembled to be tested in the X5 beam area at CERN where a dedicated 25 ns temporal structure beam has been made available by the SPS. This paper describes the hardware and the software developed for readout and control of data acquired by the front-end electronics operating at 40 MHz, Some preliminary results of the tests performed in the 25 ns beam are also given. (8 refs).

  18. Resistive Plate Chambers for hadron calorimetry: Tests with analog readout

    Energy Technology Data Exchange (ETDEWEB)

    Drake, Gary [Argonne National Laboratory, 9700 S. Cass Avenue, Argonne, IL 60439 (United States); Repond, Jose [Argonne National Laboratory, 9700 S. Cass Avenue, Argonne, IL 60439 (United States)]. E-mail: repond@hep.anl.gov; Underwood, David [Argonne National Laboratory, 9700 S. Cass Avenue, Argonne, IL 60439 (United States); Xia, Lei [Argonne National Laboratory, 9700 S. Cass Avenue, Argonne, IL 60439 (United States)

    2007-07-21

    Resistive Plate Chambers (RPCs) are being developed for use in a hadron calorimeter with very fine segmentation of the readout. The design of the chambers and various tests with cosmic rays are described. This paper reports on the measurements with multi-bit (or analog) readout of either a single larger or multiple smaller readout pads.

  19. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    AUTHOR|(SzGeCERN)756402

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  20. Radiation tolerance studies using fault injection on the Readout Control FPGA design of the ALICE TPC detector

    Science.gov (United States)

    Alme, J.; Fehlker, D.; Lippmann, C.; Mager, M.; Rehman, A. U.; Røed, K.; Röhrich, D.; Ullaland, K.

    2013-01-01

    Single Event Upsets (SEUs) are a major concern for the TPC Readout Control Unit (RCU) of the ALICE experiment. A SEU is defined as a radiation related bit-flip in a memory cell, and a SEU in the onboard SRAM based FPGA of the RCU may lead to corrupted data or, even worse, a system malfunction. The latter situation will affect the operation of the ALICE detector since it causes a premature end of data taking. Active partial reconfiguration is utilized in a dedicated reconfiguration solution on the RCU, and this makes it possible to implement fault injection. Fault injection means inserting bit flips in the configuration memory of the FPGA in a controlled laboratory environment. This paper presents the results of the fault injection study and shows how this result can be combined with SEU measurements to estimate the functional failure rate as a function of luminosity.

  1. Design and FPGA-implementation of multilayer neural networks with on-chip learning

    International Nuclear Information System (INIS)

    Haggag, S.S.M.Y

    2008-01-01

    Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

  2. Design of automatic curtain controlled by wireless based on single chip 51 microcomputer

    Science.gov (United States)

    Han, Dafeng; Chen, Xiaoning

    2017-08-01

    In order to realize the wireless control of the domestic intelligent curtains, a set of wireless intelligent curtain control system based on 51 single chip microcomputer have been designed in this paper. The intelligent curtain can work in the manual mode, automatic mode and sleep mode and can be carried out by the button and mobile phone APP mode loop switch. Through the photosensitive resistance module and human pyroelectric infrared sensor to collect the indoor light value and the data whether there is the person in the room, and then after single chip processing, the motor drive module is controlled to realize the positive inversion of the asynchronous motor, the intelligent opening and closing of the curtain have been realized. The operation of the motor can be stopped under the action of the switch and the curtain opening and closing and timing switch can be controlled through the keys and mobile phone APP. The optical fiber intensity, working mode, curtain state and system time are displayed by LCD1602. The system has a high reliability and security under practical testing and with the popularity and development of smart home, the design has broad market prospects.

  3. Electronics and readout of a large area silicon detector for LHC

    International Nuclear Information System (INIS)

    Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.

    1994-01-01

    The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)

  4. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Multimedia

    Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Pacher, L; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Marconi, S; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

    The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

  5. High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-07-30

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  6. A volumetric meter chip for point-of-care quantitative detection of bovine catalase for food safety control

    Energy Technology Data Exchange (ETDEWEB)

    Cui, Xingye; Hu, Jie; Choi, Jane Ru; Huang, Yalin; Wang, Xuemin [The Key Laboratory of Biomedical Information Engineering of Ministry of Education, School of Life Science and Technology, Xi' an Jiaotong University, Xi' an, 710049 (China); Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China); Lu, Tian Jian, E-mail: tjlu@mail.xjtu.edu.cn [Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China); Xu, Feng, E-mail: fengxu@mail.xjtu.edu.cn [The Key Laboratory of Biomedical Information Engineering of Ministry of Education, School of Life Science and Technology, Xi' an Jiaotong University, Xi' an, 710049 (China); Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China)

    2016-09-07

    A volumetric meter chip was developed for quantitative point-of-care (POC) analysis of bovine catalase, a bioindicator of bovine mastitis, in milk samples. The meter chip displays multiplexed quantitative results by presenting the distance of ink bar advancement that is detectable by the naked eye. The meter chip comprises a poly(methyl methacrylate) (PMMA) layer, a double-sided adhesive (DSA) layer and a glass slide layer fabricated by the laser-etching method, which is typically simple, rapid (∼3 min per chip), and cost effective (∼$0.2 per chip). Specially designed “U shape” reaction cells are covered by an adhesive tape that serves as an on-off switch, enabling the simple operation of the assay. As a proof of concept, we employed the developed meter chip for the quantification of bovine catalase in raw milk samples to detect catalase concentrations as low as 20 μg/mL. The meter chip has great potential to detect various target analytes for a wide range of POC applications. - Highlights: • The meter chip is a standalone point-of-care diagnostic tool with visible readouts of quantification results. • A fast and low cost fabrication protocol (~3 min and ~$0.2 per chip) of meter chip was proposed. • The chip may hold the potential for rapid scaning of bovine mastitis in cattle farms for food safety control.

  7. A volumetric meter chip for point-of-care quantitative detection of bovine catalase for food safety control

    International Nuclear Information System (INIS)

    Cui, Xingye; Hu, Jie; Choi, Jane Ru; Huang, Yalin; Wang, Xuemin; Lu, Tian Jian; Xu, Feng

    2016-01-01

    A volumetric meter chip was developed for quantitative point-of-care (POC) analysis of bovine catalase, a bioindicator of bovine mastitis, in milk samples. The meter chip displays multiplexed quantitative results by presenting the distance of ink bar advancement that is detectable by the naked eye. The meter chip comprises a poly(methyl methacrylate) (PMMA) layer, a double-sided adhesive (DSA) layer and a glass slide layer fabricated by the laser-etching method, which is typically simple, rapid (∼3 min per chip), and cost effective (∼$0.2 per chip). Specially designed “U shape” reaction cells are covered by an adhesive tape that serves as an on-off switch, enabling the simple operation of the assay. As a proof of concept, we employed the developed meter chip for the quantification of bovine catalase in raw milk samples to detect catalase concentrations as low as 20 μg/mL. The meter chip has great potential to detect various target analytes for a wide range of POC applications. - Highlights: • The meter chip is a standalone point-of-care diagnostic tool with visible readouts of quantification results. • A fast and low cost fabrication protocol (~3 min and ~$0.2 per chip) of meter chip was proposed. • The chip may hold the potential for rapid scaning of bovine mastitis in cattle farms for food safety control.

  8. Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

    CERN Document Server

    Liberali, Valentino; The ATLAS collaboration

    2016-01-01

    We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

  9. Design and simulation of MEMS microvalves for silicon photonic biosensor chip

    Science.gov (United States)

    Amemiya, Yoshiteru; Nakashima, Yuuto; Maeda, Jun; Yokoyama, Shin

    2018-04-01

    For the early and easy diagnosis of diseases, we have proposed a silicon photonic biosensor chip with two kinds of MEMS microvalves for a multiple-item detection system. The driving voltage of the vertical type with the circular-plate capacitor structure and that of the lateral type with the comb-shaped electrode are investigated. From mechanical calculations, the driving voltage of the vertical type is estimated to be 30 V and that of the lateral type to be 15 V. The propagation loss at the intersecting waveguides of arrayed ring-resonator biosensors is also estimated. In the case of optimized intersecting waveguides, more than 67% transmittance of TE-mode light is simulated for the series connection of 20 intersecting waveguides. It is confirmed that it is possible to fabricate an 8 × 12 arrayed biosensor chip in an area of 1 × 1.5 mm2 taking the device size of the microvalves into consideration. We have, for the first time, designed a whole system, including sensors and a fluid channel with MEMS microvalves.

  10. Design of the new front-end electronics for the readout of the upgraded CMS electromagnetic calorimeter for the HL-LHC

    CERN Document Server

    Cometti, Simona

    2017-01-01

    The Compact Muon Solenoid detector was originally designed to operate for about ten years, for LHC instantaneous luminosities up to $1 \\cdot 10^{34}$ cm$^{-2}$ s$^{-1}$ and integrated luminosity of 500 fb$^{-1}$. The High Luminosity LHC will increase the instantaneous luminosity by about a factor of 5 from current levels and CMS will accumulate an integrated luminosity of 3000 fb$^{-1}$ by about 2035. With such high luminosity the electromagnetic calorimeter of CMS will have to cope with a challenging increase in the number of interactions per bunch crossing and in radiation levels. The front-end readout electronics will be completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a faster pre-amplifier, increase the sampling frequency from 40 MS/s to 160 MS/s and implement a trigger system that resides entirely off-detector.

  11. A novel integrated circuit for semiconductor radiation detectors with sparse readout

    International Nuclear Information System (INIS)

    Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

    2008-01-01

    A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

  12. A fast integrated readout system for a cathode pad photon detector

    Energy Technology Data Exchange (ETDEWEB)

    French, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Lovell, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Chesi, E. (CERN, ECP Div., Geneva (Switzerland)); Racz, A. (CERN, ECP Div., Geneva (Switzerland)); Seguinot, J. (Coll. de France, Paris (France)); Ypsilantis, T. (Coll. de France, Paris (France)); Arnold, R. (CRN, Louis Pasteur Univ., Strasbourg (France)); Guyonnet, J.L. (CRN, Louis Pasteur Univ., Strasbourg (France)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland))

    1994-04-01

    A fast integrated electronic chain is presented to read out the cathode pad array of a multiwire photon detector for a fast RICH counter. Two VLSI circuits have been designed and produced. An analog eight channel, low noise, fast, bipolar, current preamplifier and discriminator chip serves as front-end electronics. It has an rms equivalent noise current of 10 nA (2000 e[sup -]), 50 MHz bandwidth with 10 mW of power consumption per channel. Two analogue chips are coupled to a digital 16 channels CMOS readout chip, operating at 20 MHz, that provides a pipelined delay of 1.3 [mu]s and zero suppression with a power consumption of about 6 mW per channel. Readout of a 4000 pad sector requires 3-4 [mu]s depending on the number of hit pads. The full RICH counter is made up of many of such sectors (the prototype has three fully equipped sectors), read out in parallel. The minimum time to separate successive hits on the same pad is about 70 ns. The time skew of the full chain is about 15 ns. (orig.)

  13. Design and characterization of a 52K SNP chip for goats.

    Directory of Open Access Journals (Sweden)

    Gwenola Tosser-Klopp

    Full Text Available The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50-60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed: Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes, sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years.

  14. Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

    Science.gov (United States)

    Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

    2013-06-21

    We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

  15. Introduction to Open Core Protocol Fastpath to System-on-Chip Design

    CERN Document Server

    Schwaderer, W David

    2012-01-01

    This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

  16. Pixel detector readout electronics with two-level discriminator scheme

    International Nuclear Information System (INIS)

    Pengg, F.

    1998-01-01

    In preparation for a silicon pixel detector with more than 3,000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog front end of the readout electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.8 microm process but compatible with the design rules of the radiation hard Honeywell 0.8 microm bulk process. Each cell contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 microm by 140 microm. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900 mV for a minimum ionizing particle (MIP, about 24,000 e - for a 300 microm thick Si-detector) with a return to baseline within 750 ns for a 1 MIP input signal. The full readout chain (without detector) shows an equivalent noise charge to 60e - r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22 ns at a separation of 1,500 e - , which is adequate for the 40 MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40fF coupling capacitance, is less than 3%. A single cell consumes 35 microW at 3.5 V supply voltage

  17. Design of a DNA chip for detection of unknown genetically modified organisms (GMOs).

    Science.gov (United States)

    Nesvold, Håvard; Kristoffersen, Anja Bråthen; Holst-Jensen, Arne; Berdal, Knut G

    2005-05-01

    Unknown genetically modified organisms (GMOs) have not undergone a risk evaluation, and hence might pose a danger to health and environment. There are, today, no methods for detecting unknown GMOs. In this paper we propose a novel method intended as a first step in an approach for detecting unknown genetically modified (GM) material in a single plant. A model is designed where biological and combinatorial reduction rules are applied to a set of DNA chip probes containing all possible sequences of uniform length n, creating probes capable of detecting unknown GMOs. The model is theoretically tested for Arabidopsis thaliana Columbia, and the probabilities for detecting inserts and receiving false positives are assessed for various parameters for this organism. From a theoretical standpoint, the model looks very promising but should be tested further in the laboratory. The model and algorithms will be available upon request to the corresponding author.

  18. Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link

    Science.gov (United States)

    Sangirov, Jamshid; Nguyen, Nga T. H.; Ngo, Trong-Hieu; Im, Dong-min; Ukaegbu, Augustine I.; Lee, Tae-Woo; Cho, Mu Hee; Park, Hyo-Hoon

    2010-02-01

    An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

  19. Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

    Science.gov (United States)

    Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

    2008-01-01

    A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

  20. TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

    2011-08-11

    The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

  1. Intensity-based readout of resonant-waveguide grating biosensors: Systems and nanostructures

    Science.gov (United States)

    Paulsen, Moritz; Jahns, Sabrina; Gerken, Martina

    2017-09-01

    Resonant waveguide gratings (RWG) - also called photonic crystal slabs (PCS) - have been established as reliable optical transducers for label-free biochemical assays as well as for cell-based assays. Current readout systems are based on mechanical scanning and spectrometric measurements with system sizes suitable for laboratory equipment. Here, we review recent progress in compact intensity-based readout systems for point-of-care (POC) applications. We briefly introduce PCSs as sensitive optical transducers and introduce different approaches for intensity-based readout systems. Photometric measurements have been realized with a simple combination of a light source and a photodetector. Recently a 96-channel, intensity-based readout system for both biochemical interaction analyses as well as cellular assays was presented employing the intensity change of a near cut-off mode. As an alternative for multiparametric detection, a camera system for imaging detection has been implemented. A portable, camera-based system of size 13 cm × 4.9 cm × 3.5 cm with six detection areas on an RWG surface area of 11 mm × 7 mm has been demonstrated for the parallel detection of six protein binding kinetics. The signal-to-noise ratio of this system corresponds to a limit of detection of 168 M (24 ng/ml). To further improve the signal-to-noise ratio advanced nanostructure designs are investigated for RWGs. Here, results on multiperiodic and deterministic aperiodic nanostructures are presented. These advanced nanostructures allow for the design of the number and wavelengths of the RWG resonances. In the context of intensity-based readout systems they are particularly interesting for the realization of multi-LED systems. These recent trends suggest that compact point-of-care systems employing disposable test chips with RWG functional areas may reach market in the near future.

  2. Investigation of the readout electronics of DELPHI surround muon chamber

    International Nuclear Information System (INIS)

    Khovanskij, N.; Krumshtejn, Z.; Ol'shevskij, A.; Sadovskij, A.; Sedykh, Yu.; Molnar, J.; Sicho, P.; Tomsa, Z.

    1995-01-01

    The characteristics of the readout electronics of the DELPHI surround muon chambers with various AMPLEX chips (AMPLEX 16 and AMPLEX-SICAL) are presented. This electronics is studied in a cosmic rays test of the real surround muon chamber model. 4 refs., 6 figs., 1 tab

  3. A micromachined surface stress sensor with electronic readout

    NARCIS (Netherlands)

    Carlen, Edwin; Weinberg, M.S.; Zapata, A.M.; Borenstein, J.T.

    2008-01-01

    A micromachined surface stress sensor has been fabricated and integrated off chip with a low-noise, differential capacitance, electronic readout circuit. The differential capacitance signal is modulated with a high frequency carrier signal, and the output signal is synchronously demodulated and

  4. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  5. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Science.gov (United States)

    Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

    2014-01-01

    This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

  6. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  7. Status of readout integrated circuits for radiation detector

    International Nuclear Information System (INIS)

    Moon, B. S.; Hong, S. B.; Cheng, J. E. and others

    2001-09-01

    In this report, we describe the current status of readout integrated circuits developed for radiation detectors, along with new technologies being applied to this field. The current status of ASCIC chip development related to the readout electronics is also included in this report. Major sources of this report are from product catalogs and web sites of the related industries. In the field of semiconductor process technology in Korea, the current status of the multi-project wafer(MPW) of IDEC, the multi-project chip(MPC) of ISRC and other domestic semiconductor process industries is described. In the case of other countries, the status of the MPW of MOSIS in USA and the MPW of EUROPRACTICE in Europe is studied. This report also describes the technologies and products of readout integrated circuits of industries worldwide

  8. LHCb: Fast Readout Control for the upgraded readout architecture of the LHCb experiment at CERN

    CERN Multimedia

    Alessio, F

    2013-01-01

    The LHCb experiment at CERN has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity with an upgraded LHCb detector. As a consequence, the various LHCb sub-systems in the readout architecture will be upgraded to cope with higher sub-detector occupancies, higher rate, and higher readout load. The new architecture, new functionalities, and the first hardware implementation of a new LHCb Readout Control system (commonly referred to as S-TFC) for the upgraded LHCb experiment is here presented. Our attention is focused in describing solutions for the distribution of clock and timing information to control the entire upgraded readout architecture by profiting of a bidirectional optical network and powerful FPGAs, including a real-time mechanism to synchronize the entire system. Solutions and implementations are presented, together with first results on the simulation and the validation of the system.

  9. Prototype readout system for a multi Mpixels UV single-photon imaging detector capable of space flight operation

    Science.gov (United States)

    Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

    2018-02-01

    Our collaboration works on the development of a large aperture, high resolution, UV single-photon imaging detector, funded through NASA's Strategic Astrophysics Technology (SAT) program. The detector uses a microchannel plate for charge multiplication, and orthogonal cross strip (XS) anodes for charge readout. Our target is to make an advancement in the technology readiness level (TRL), which enables real scale prototypes to be tested for future NASA missions. The baseline detector has an aperture of 50×50 mm and requires 160 low-noise charge-sensitive channels, in order to extrapolate the incoming photon position with a spatial resolution of about 20 μm FWHM. Technologies involving space flight require highly integrated electronic systems operating at very low power. We have designed two ASICs which enable the construction of such readout system. First, a charge sensitive amplifier (CSAv3) ASIC provides an equivalent noise charge (ENC) of around 600 e-, and a baseline gain of 10 mV/fC. The second, a Giga Sample per Second (GSPS) ASIC, called HalfGRAPH, is a 12-bit analog to digital converter. Its architecture is based on waveform sampling capacitor arrays and has about 8 μs of analog storage memory per channel. Both chips encapsulate 16 measurement channels. Using these chips, a small scale prototype readout system has been constructed on a FPGA Mezzanine Board (FMC), equipped with 32 measurement channels for system evaluation. We describe the construction of HalfGRAPH ASIC, detector's readout system concept and obtained results from the prototype system. As part of the space flight qualification, these chips were irradiated with a Cobalt gamma-ray source, to verify functional operation under ionizing radiation exposure.

  10. A Medipix3 readout system based on the National Instruments FlexRIO card and using the LabVIEW programming environment

    Science.gov (United States)

    Horswell, I.; Gimenez, E. N.; Marchal, J.; Tartoni, N.

    2011-01-01

    Hybrid silicon photon-counting detectors are becoming standard equipment for many synchrotron applications. The latest in the Medipix family of read-out chips designed as part of the Medipix Collaboration at CERN is the Medipix3, which while maintaining the same pixel size as its predecessor, offers increased functionality and operating modes. The active area of the Medipix3 chip is approx 14mm × 14mm (containing 256 × 256 pixels) which is not large enough for many detector applications, this results in the need to tile many sensors and chips. As a first step on the road to develop such a detector, it was decided to build a prototype single chip readout system to gain the necessary experience in operating a Medipix3 chip. To provide a flexible learning and development tool it was decided to build an interface based on the recently released FlexRIOTM system from National Instruments and to use the LabVIEWTM graphical programming environment. This system and the achieved performance are described in this paper.

  11. Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

    CERN Document Server

    Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

    2014-01-01

    In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

  12. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  13. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  14. First performance results of the ALICE TPC Readout Control Unit 2

    OpenAIRE

    Zhao, Chengxin; Alme, Johan; Alt, Torsten; Appelshäuser, Harald; Bratrud, Lars Karlot Stubberud; Castro, Andrew; Costa, Filippo; David, Ernö; Gunji, Tako; Kirsch, S; Kiss, Tivadar; Langøy, Rune; Lien, Jørgen; Lippmann, C; Oskarsson, Anders

    2016-01-01

    - This paper presents the first performance results of the ALICE TPC Readout Control Unit 2 (RCU2). With the upgraded hardware typology and the new readout scheme in FPGA design, the RCU2 is designed to achieve twice the readout speed of the present Readout Control Unit. Design choices such as using the flash-based Microsemi Smartfusion2 FPGA and applying mitigation techniques in interfaces and FPGA design ensure a high degree of radiation tolerance. This paper presents the system level ir...

  15. 100 Gbps PCI-Express readout for the LHCb upgrade

    International Nuclear Information System (INIS)

    Durante, P.; Neufeld, N.; Schwemmer, R.; Balbi, G.; Marconi, U.

    2015-01-01

    We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-Express bus, on Altera Stratix 5 devices, using a DMA mechanism and different synchronization schemes between the FPGA and the readout unit. Finally we discuss hardware and software design considerations necessary to achieve a data throughput of 100 Gbps in the final readout board

  16. Design methodology and results evaluation of a heating functionality in modular lab-on-chip systems

    Science.gov (United States)

    Streit, Petra; Nestler, Joerg; Shaporin, Alexey; Graunitz, Jenny; Otto, Thomas

    2018-06-01

    Lab-on-a-chip (LoC) systems offer the opportunity of fast and customized biological analyses executed at the ‘point-of-need’ without expensive lab equipment. Some biological processes need a temperature treatment. Therefore, it is important to ensure a defined and stable temperature distribution in the biosensor area. An integrated heating functionality is realized with discrete resistive heating elements including temperature measurement. The focus of this contribution is a design methodology and evaluation technique of the temperature distribution in the biosensor area with regard to the thermal-electrical behaviour of the heat sources. Furthermore, a sophisticated control of the biosensor temperature is proposed. A finite element (FE) model with one and more integrated heat sources in a polymer-based LoC system is used to investigate the impact of the number and arrangement of heating elements on the temperature distribution around the heating elements and in the biosensor area. Based on this model, various LOC systems are designed and fabricated. Electrical characterization of the heat sources and independent temperature measurements with infrared technique are performed to verify the model parameters and prove the simulation approach. The FE model and the proposed methodology is the foundation for optimization and evaluation of new designs with regard to temperature requirements of the biosensor. Furthermore, a linear dependency of the heater temperature on the electric current is demonstrated in the targeted temperature range of 20 °C to 70 °C enabling the usage of the heating functionality for biological reactions requiring a steady-state temperature up to 70 °C. The correlation between heater and biosensor area temperature is derived for a direct control through the heating current.

  17. RCP: a novel probe design bias correction method for Illumina Methylation BeadChip.

    Science.gov (United States)

    Niu, Liang; Xu, Zongli; Taylor, Jack A

    2016-09-01

    The Illumina HumanMethylation450 BeadChip has been extensively utilized in epigenome-wide association studies. This array and its successor, the MethylationEPIC array, use two types of probes-Infinium I (type I) and Infinium II (type II)-in order to increase genome coverage but differences in probe chemistries result in different type I and II distributions of methylation values. Ignoring the difference in distributions between the two probe types may bias downstream analysis. Here, we developed a novel method, called Regression on Correlated Probes (RCP), which uses the existing correlation between pairs of nearby type I and II probes to adjust the beta values of all type II probes. We evaluate the effect of this adjustment on reducing probe design type bias, reducing technical variation in duplicate samples, improving accuracy of measurements against known standards, and retention of biological signal. We find that RCP is statistically significantly better than unadjusted data or adjustment with alternative methods including SWAN and BMIQ. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website (https://www.bioconductor.org/packages/release/bioc/html/ENmix.html). niulg@ucmail.uc.edu Supplementary data are available at Bioinformatics online. Published by Oxford University Press 2016. This work is written by US Government employees and is in the public domain in the US.

  18. Design and measurements of low power multichannel chip for recording and stimulation of neural activity.

    Science.gov (United States)

    Zoladz, M; Kmon, P; Grybos, P; Szczygiel, R; Kleczek, R; Otfinowski, P; Rauza, J

    2012-01-01

    A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm² of silicon area and consumes only 25 µW/channel. A low cut-off frequency can be tuned in the 60 mHz-100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 µV rms in 100 Hz-12 kHz band and 7.6 µV rms in 3 Hz-12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA-512 µA range.

  19. Design and Characterization of CMOS On-Chip Antennas for 60 GHz Communications

    Directory of Open Access Journals (Sweden)

    D.Titz

    2012-04-01

    Full Text Available In this paper, we present the design and the measurement of two antennas realized on a 130nm CMOS process. They both radiate in the 60 GHz band and are dedicated to Wireless Personal Area Network (WPAN applications. The antennas are manufactured within the frame of a multi-wafer project with several surrounding microelectronic circuits. The first antenna is an Inverted-F antenna (IFA. It has a maximum gain of -8 dBi and a -10 dB matching bandwidth of 20%. The second radiator is a meandered dipole. It has a maximum gain of -14 dBi and a -10 dB matching bandwidth of 10%. The challenging measurement of their reflection coefficient and their gain radiation pattern are presented. Simulated versus measured curves are analyzed. We especially demonstrate the necessity to take into account the closest microelectronic circuits of the antennas for accurate modeling of the radiating performance of 60 GHz on-chip dies.

  20. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong

    2015-08-23

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  1. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong; Alouini, Mohamed-Slim

    2015-01-01

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  2. Study on two-dimensional induced signal readout of MRPC

    International Nuclear Information System (INIS)

    Wu Yucheng; Yue Qian; Li Yuanjing; Ye Jin; Cheng Jianping; Wang Yi; Li Jin

    2012-01-01

    A kind of two-dimensional readout electrode structure for the induced signal readout of MRPC has been studied in both simulation and experiments. Several MRPC prototypes are produced and a series of test experiments have been done to compare with the result of simulation, in order to verify the simulation model. The experiment results are in good agreement with those of simulation. This method will be used to design the two-dimensional signal readout mode of MRPC in the future work.

  3. Yarr: A PCIe based readout system for semiconductor tracking systems

    Energy Technology Data Exchange (ETDEWEB)

    Heim, Timon [Bergische Universitaet Wuppertal, Wuppertal (Germany); CERN, Geneva (Switzerland); Maettig, Peter [Bergische Universitaet Wuppertal, Wuppertal (Germany); Pernegger, Heinz [CERN, Geneva (Switzerland)

    2015-07-01

    The Yarr readout system is a novel DAQ concept, using an FPGA board connected via PCIe to a computer, to read out semiconductor tracking systems. The system uses the FPGA as a reconfigurable IO interface which, in conjunction with the very high speed of the PCIe bus, enables a focus of processing the data stream coming from the pixel detector in software. Modern computer system could potentially make the need of custom signal processing hardware in readout systems obsolete and the Yarr readout system showcases this for FE-I4 chips, which are state-of-the-art readout chips used in the ATLAS Pixel Insertable B-Layer and developed for tracking in high multiplicity environments. The underlying concept of the Yarr readout system tries to move intelligence from hardware into the software without the loss of performance, which is made possible by modern multi-core processors. The FPGA board firmware acts like a buffer and does no further processing of the data stream, enabling rapid integration of new hardware due to minimal firmware minimisation.

  4. Development of a versatile readout and test system and characterization of a capacitively coupled active pixel sensor

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, Jens; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruher Institut fuer Technologie, Karlsruhe (Germany); Collaboration: ATLAS-Collaboration

    2015-07-01

    With the availability of high voltage and high resistivity CMOS processes, active pixel sensors are becoming increasingly interesting for radiation detection in high energy physics experiments. Although the pixel signal-to-noise ratio and the sensor radiation tolerance were improved, active pixel sensors cannot yet compete with state-of-the-art hybrid pixel detector in a high radiation environment. Hence, active pixel sensors are possible candidates for the outer tracking detector in HEP experiments where production cost plays a role. The investigation of numerous prototyping steps and different technologies is still ongoing and requires a versatile test and readout system, which will be presented in this talk. A capacitively coupled active pixel sensor fabricated in AMS 180 nm high voltage CMOS process is investigated. The sensor is designed to be glued to existing front-end pixel readout chips. Results from the characterization are presented in this talk.

  5. A new DOI detector design using discrete crystal array with depth-dependent reflector patterns and single-ended readout

    International Nuclear Information System (INIS)

    Lee, Seung-Jae; Lee, Chaeyeong; Kang, Jihoon; Chung, Yong Hyun

    2017-01-01

    We developed a depth of interaction (DOI) positron emission tomography (PET) detector using depth-dependent reflector patterns in a discrete crystal array. Due to the different reflector patterns at depth, light distribution was changed relative to depth. As a preliminary experiment, we measured DOI detector module crystal identification performance. The crystal consisted of a 9×9 array of 2 mmx2 mmx20 mm lutetium-yttrium oxyorthosilicate (LYSO) crystals. The crystal array was optically coupled to a 64-channel position-sensitive photomultiplier tube with a 2 mmx2 mm anode size and an 18.1 mmx18.1 mm effective area. We obtained the flood image with an Anger-type calculation. DOI layers and 9×9 pixels were well distinguished in the obtained images. Preclinical PET scanners based on this detector design offer the prospect of high and uniform spatial resolution.

  6. A new DOI detector design using discrete crystal array with depth-dependent reflector patterns and single-ended readout

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seung-Jae; Lee, Chaeyeong [Department of Radiological Science, Yonsei University, Wonju 26493 (Korea, Republic of); Kang, Jihoon, E-mail: ray.jihoon.kang@gmail.com [Department of Biomedical Engineering, Chonnam National University, 50 Daehak-ro, Yeosu, Jeonnam 59626 (Korea, Republic of); Chung, Yong Hyun, E-mail: ychung@yonsei.ac.kr [Department of Radiological Science, Yonsei University, Wonju 26493 (Korea, Republic of)

    2017-01-21

    We developed a depth of interaction (DOI) positron emission tomography (PET) detector using depth-dependent reflector patterns in a discrete crystal array. Due to the different reflector patterns at depth, light distribution was changed relative to depth. As a preliminary experiment, we measured DOI detector module crystal identification performance. The crystal consisted of a 9×9 array of 2 mmx2 mmx20 mm lutetium-yttrium oxyorthosilicate (LYSO) crystals. The crystal array was optically coupled to a 64-channel position-sensitive photomultiplier tube with a 2 mmx2 mm anode size and an 18.1 mmx18.1 mm effective area. We obtained the flood image with an Anger-type calculation. DOI layers and 9×9 pixels were well distinguished in the obtained images. Preclinical PET scanners based on this detector design offer the prospect of high and uniform spatial resolution.

  7. Design of a one-chip board microcontrol unit for active vibration control of a naval ship mounting system

    International Nuclear Information System (INIS)

    Oh, Jong-Seok; Choi, Seung-Bok; Han, Young-Min; Nguyen, Vien-Quoc; Moon, Seok-Jun

    2012-01-01

    This work presents an experimental implementation of a user-tunable one-chip board microcontrol unit which is specifically designed for vibration control of the active mounting system for naval ships. The proposed mounting system consists of four active mounts supporting vibration-sensitive equipment. Each active mount constitutes a rubber element, an inertial mass and the piezostack actuator. It is designed for particular applications that require effective isolation performance against wide frequency ranges, such as naval ship equipment. After describing the configuration of the active mount, dynamic characteristics of the rubber element and the piezostack actuator are experimentally identified. Accordingly, the proposed mounting system is constructed and the governing equations of motion are formulated. In order to attenuate the unwanted vibrations transferred from the upper mass, a feedforward controller with fast Fourier algorithm is designed and experimentally realized using the one-chip microcontrol board which is specially made for this practical application. In order to evaluate the performance of the one-chip microcontrol unit, vibration control results of the proposed active mounting system are presented in the frequency domain. (technical note)

  8. Laser Power Measurement Using Commercial MEMS Pressure Sensor along with PSoC Embedded Read-out

    Directory of Open Access Journals (Sweden)

    J. Jayapandian

    2011-06-01

    Full Text Available Solid-state, gas, semiconductor and other types of lasers are extensively employed in industry for producing laser beams used in such wide ranging fields as machining, medicine and communications. In such applications, it is necessary to be able to accurately measure the power of the laser beam that is emitted by the laser. This paper describes a novel design technique which uses the diaphragm of a commercial MEMS pressure sensor as a target surface on which laser beam impinge, transfer heat and causes change in piezo resistance. The measured change in resistance was proportional to the intensity of laser beam in the range of 0 to 300 mW. The ratio metric embedded read-out design using a single chip programmable system on chip (PSoC has been used to acquire the resistance.

  9. CBC2: A CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Hall, G., E-mail: g.hall@imperial.ac.uk [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Pesaresi, M.; Raymond, M. [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Braga, D.; Jones, L.; Murray, P.; Prydderch, M. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 OQX (United Kingdom); Abbaneo, D.; Blanchot, G.; Honma, A.; Kovacs, M.; Vasey, F. [CERN, CH-1211, Geneva (Switzerland)

    2014-11-21

    The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130 nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

  10. Beam test performance of the APV5 chip

    International Nuclear Information System (INIS)

    De Fez-Laso, M.D.M.; Gill, K.; MacEvoy, B.; Millmore, M.; Potts, A.; Raymond, M.

    1996-01-01

    The performance of the latest prototype of the radiation hard front end chip to be used by the CMS collaboration for analogue readout of the microstrip tracker has been evaluated with a silicon microstrip detector in a beam at CERN. The circuit, developed by the RD20 collaboration, consists of 128 channels of amplifier, pipeline memory, analogue signal processor and a serial multiplexer. As a result of these studies improvements in the circuit design have been devised which will be implemented in the next version. (orig.)

  11. Enhancements to a Superconducting Quantum Interference Device (SQUID) Multiplexer Readout and Control System

    Science.gov (United States)

    Forgione, J.; Benford, D. J.; Buchanan, E. D.; Moseley, S. H.; Rebar, J.; Shafer, R. A.

    2004-01-01

    Far-infrared detector arrays such as the 16x32 superconducting bolometer array for the SAFIRE instrument (flying on the SOFIA airborne observatory) require systems of readout and control electronics to provide translation between a user-driven, digital PC and the cold, analog world of the cryogenic detector. In 2001, the National Institute of Standards and Technology (NIST) developed their Mark III electronics for purposes of control and readout of their 1x32 SQUID Multiplexer chips. We at NASA s Goddard Space Flight Center acquired a Mark 111 system and subsequently designed upgrades to suit our and our collaborators purposes. We developed an arbitrary, programmable multiplexing system that allows the user to cycle through rows in a SQUID array in an infinite number of combinations. We provided hooks in the Mark III system to allow readout of signals from outside the Mark 111 system, such as telescope status information. Finally, we augmented the heart of the system with a new feedback algorithm implementation, flexible diagnostic tools, and informative telemetry.

  12. Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Xiaoliang Ge

    2018-02-01

    Full Text Available This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

  13. Microcontroller based four-channel current readout unit for beam slit monitor

    International Nuclear Information System (INIS)

    Holikatti, A.C.; Puntambekar, T.A.; Pithawa, C.K.

    2009-01-01

    This paper describes the design and development of a microcontroller based four-channel current readout unit for Beam Slit Monitor (BSM) installed in Transport Line-1 of Indus Accelerator Complex. BSM is a diagnostic device consisting of two horizontal and two vertical blades, which can be moved independently in to the beam pipe to cut the beam transversely. The readout unit employs switched integrators with reset, hold and select switches and timing and control unit. It integrates the current output of the four blades of BSM and produces an output corresponding to the beam charge intercepted by the blade. The integrator outputs are then multiplexed and digitized using 12-bit ADC. Acquired digital data from ADC is stored into on-chip RAM of the microcontroller. The readout sequence is synchronized with the Microtron beam-timing signal. The timing of integration, hold and reset cycles is controlled by the microcontroller. The unit is connected on a serial link to the host computer in main control room. This unit has been integrated with the BSM system and is being used to obtain the electron beam profile. (author)

  14. LHCb: A new Readout Control system for the LHCb Upgrade

    CERN Multimedia

    Alessio, F

    2012-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation of a new Readout Control system for the LHCb upgrade. The system is based on FPGAs and bi-directional links for the control of the entire readout architecture. First results on the validation of the system are also given.

  15. Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

    Science.gov (United States)

    Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

    2018-02-01

    The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

  16. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  17. A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

    Science.gov (United States)

    Santoli, S.

    The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

  18. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  19. Design, realization and test of a rad-hard 2D-compressor and packing chip for high energy physics experiments

    International Nuclear Information System (INIS)

    Antinori, Samuele; Falchieri, Davide; Gabrielli, Alessandro; Gandolfi, Enzo

    2004-01-01

    CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 μm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN

  20. Magma Design Automation : Component placement on chips; the "holey cheese" problem

    NARCIS (Netherlands)

    Brouwer, R.; Brouwer, T.; Hurkens, C.A.J.; Manen, van M.; Montijn, C.; Schreuder, J.; Williams, J.F.; Hek, G.M.

    2002-01-01

    The costs of the fabrication of a chip is partly determined by the wire length needed by the transistors to respect the wiring scheme. The transistors have to be placed without overlap into a prescribed configuration of blockades, i.e. parts of the chipthat are beforehand excluded from positioning

  1. Imaging achievements with the Vernier readout

    CERN Document Server

    Lapington, J S; Worth, L B C; Tandy, J A

    2002-01-01

    We describe the Vernier anode, a high resolution and charge division image readout for microchannel plate detectors. It comprises a planar structure of insulated electrodes deposited on an insulating substrate. The charge cloud from an event is divided amongst all nine electrodes and the charge ratio uniquely determines the two-dimensional position coordinate of the charge centroid. We discuss the design of the anode pattern and describe the advantages offered by this readout. The cyclic variation of the electrode structure allows the image resolution to exceed the charge measurement resolution and enables the entire active area of the readout to be utilized. In addition, fixed pattern noise is greatly reduced. We present results demonstrating the position resolution and image linearity. A position resolution of 10 mu m FWHM is demonstrated and the overall imaging performance is shown to be limited by the microchannel plate pore spacing. We present measurements of the image distortions and describe techniques...

  2. The NA60 experiment readout architecture

    CERN Document Server

    Floris, M; Usai, G L; David, A; Rosinsky, P; Ohnishi, H

    2004-01-01

    The NA60 experiment was designed to identify signatures of a new state of matter, the Quark Gluon Plasma, in heavy-ion collisions at the CERN Super Proton Synchroton. The apparatus is composed of four main detectors: a muon spectrometer (MS), a zero degree calorimeter (ZDC), a silicon vertex telescope (VT), and a silicon microstrip beam tracker (BT). The readout of the whole experiment is based on a PCI architecture. The basic unit is a general purpose PCI card, interfaced to the different subdetectors via custom mezzanine cards. This allowed us to successfully implement several completely different readout protocols (from the VME like protocol of the MS to the custom protocol of the pixel telescope). The system was fully tested with proton and ion beams, and several million events were collected in 2002 and 2003. This paper presents the readout architecture of NA60, with particular emphasis on the PCI layer common to all the subdetectors. (16 refs).

  3. CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    CERN Document Server

    Prydderch, Mark Lyndon; Bell, Stephen Jean-marc; Key-Charriere, M; Jones, Lawrence; Auzinger, Georg; Borg, Johan; Hall, Geoffrey; Pesaresi, Mark Franco; Raymond, David Mark; Uchida, Kirika; Goldstein, Joel; Seif El Nasr, Sarah

    2018-01-01

    The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips. On-chip logic identifies first level trigger primitives from high transverse-momentum tracks by selecting correlated hits in the two sensors. Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing. Results and performance are reported.

  4. A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

    International Nuclear Information System (INIS)

    Heuvelmans, S; Boerrigter, M

    2011-01-01

    Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

  5. A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

    Energy Technology Data Exchange (ETDEWEB)

    Heuvelmans, S; Boerrigter, M, E-mail: sander.heuvelmans@bruco.nl [Bruco integrated circuits BV, Oostermaat 2, 7623 CS (Netherlands)

    2011-01-15

    Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

  6. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  7. Evolution of the dual-readout calorimeter

    Indian Academy of Sciences (India)

    The 4th concept design is built upon calorimetry criteria that result in the DREAM prototype, read-out via two different types of longitudinal fibers, scintillator and quartz respectively, and therefore capable of determining for each shower the corresponding electromagnetic fraction, thus eliminating the strong effect of ...

  8. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. Author Affiliations. Wojciech Wierba1 on behalf of the FCAL Collaboration. The Henryk Niewodniczański ...

  9. Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

    Science.gov (United States)

    Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

    2015-06-01

    Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

  10. Wideband pulse amplifiers for the NECTAr chip

    Science.gov (United States)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

    2012-12-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  11. Wideband pulse amplifiers for the NECTAr chip

    International Nuclear Information System (INIS)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J-F.; Naumann, C.L.; Nayman, P.; Ribó, M.

    2012-01-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1–3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  12. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  13. A reconfigurable image tube using an external electronic image readout

    Science.gov (United States)

    Lapington, J. S.; Howorth, J. R.; Milnes, J. S.

    2005-08-01

    We have designed and built a sealed tube microchannel plate (MCP) intensifier for optical/NUV photon counting applications suitable for 18, 25 and 40 mm diameter formats. The intensifier uses an electronic image readout to provide direct conversion of event position into electronic signals, without the drawbacks associated with phosphor screens and subsequent optical detection. The Image Charge technique is used to remove the readout from the intensifier vacuum enclosure, obviating the requirement for additional electrical vacuum feedthroughs and for the readout pattern to be UHV compatible. The charge signal from an MCP intensifier is capacitively coupled via a thin dielectric vacuum window to the electronic image readout, which is external to the sealed intensifier tube. The readout pattern is a separate item held in proximity to the dielectric window and can be easily detached, making the system easily reconfigurable. Since the readout pattern detects induced charge and is external to the tube, it can be constructed as a multilayer, eliminating the requirement for narrow insulator gaps and allowing it to be constructed using standard PCB manufacturing tolerances. We describe two readout patterns, the tetra wedge anode (TWA), an optimized 4 electrode device similar to the wedge and strip anode (WSA) but with a factor 2 improvement in resolution, and an 8 channel high speed 50 ohm device, both manufactured as multilayer PCBs. We present results of the detector imaging performance, image resolution, linearity and stability, and discuss the development of an integrated readout and electronics device based on these designs.

  14. The FE-I4 pixel readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@bl.gov [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Arutinov, D.; Barbero, M. [University of Bonn, Bonn (Germany); Beccherle, R. [Istituto Nazionale di Fisica Nucleare Sezione di Genova, Genova (Italy); Dube, S.; Elledge, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Fleury, J. [Laboratoire de l' Accelerateur Lineaire, Orsay (France); Fougeron, D.; Gensolen, F. [Centre de Physique des Particules de Marseille, Marseille (France); Gnani, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Gromov, V. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Hemperek, T.; Karagounis, M. [University of Bonn, Bonn (Germany); Kluit, R. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Kruth, A. [University of Bonn, Bonn (Germany); Mekkaoui, A. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Menouni, M. [Centre de Physique des Particules de Marseille, Marseille (France); Schipper, J.-D. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands)

    2011-04-21

    A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

  15. Progress in the development of the DTMROC time measurement chip for the ATLAS transition radiation tracker (TRT)

    CERN Document Server

    Alexander, C; Dressnandt, N; Ekenberg, T; Farthouat, Philippe; Keener, P T; Lam, N; La Marra, D; Mann, J; Newcomer, F M; Ryzhov, V; Söderberg, M; Szczygiel, R; Van Berg, R; Williams, H H

    2001-01-01

    A 16-channel digital time-measurement readout chip (DTMROC) has been fabricated in the TEMIC/DM1LL left bracket 1 right bracket BI- CMOS radiation-hard process for the Large Hadron Collider's (LHC) Transition Radiation Tracker (ATLAS/TRT) at CERN left bracket 2 right bracket . The chip receives discriminated straw-drift-tube signals from bipolar amplifier-shaper-discriminator chips (ASDBLR). measures the arrival time in 3.125 ns increments ( plus or minus 1 ns), and stores the data in a pipeline for 3.3mus. A trigger signal (L1A) causes the data to be tagged with a time stamp and stored for readout- Up to 13 events may be stored in an on-chip buffer while data is being clocked out in a 40 MHz serial stream. The chip has been designed to function after exposure to 1x10**1**4 protons/cm**2 and 1 Mrad total dose. System beam-tests have demonstrated measurement of track positions with a resolution of 165mum and 85% efficiency at rates up to 18MHz. 6 Refs.

  16. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  17. Optical readout and control interface for the BTeV pixel vertex detector

    CERN Document Server

    Vergara-Limon, S; Sheaff, M; Vargas, M A

    2002-01-01

    Optical links will be used for sending data back and forth from the counting room to the detector in the data acquisition systems for future high energy physics experiments, including ATLAS and CMS in the LHC at CERN (Switzerland) and BTeV at Fermilab (USA). This is because they can be ultra-high speed and are relatively immune to electro-magnetic interference (EMI). The baseline design for the BTeV Pixel Vertex Detector includes two types of optical link, one to control and monitor and the other to read out the hit data from the multi-chip modules on each half-plane of the detector. The design and performance of the first prototype of the Optical Readout and Control Interface for the BTeV Pixel Vertex Detector is described.

  18. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  19. Development and simulation results of a sparsification and readout circuit for wide pixel matrices

    International Nuclear Information System (INIS)

    Gabrielli, A.; Giorgi, F.; Morsani, F.; Villa, M.

    2011-01-01

    In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: (http://www.pi.infn.it/SuperB)]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, (doi:10.1016/j.nima.2010.05.039)]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm 2 with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack . s -1 . cm -2 with a temporal resolution below 1 μs. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.

  20. Development and simulation results of a sparsification and readout circuit for wide pixel matrices

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, A.; Giorgi, F. [University and INFN of Bologna (Italy); Morsani, F. [University and INFN of Pisa (Italy); Villa, M. [University and INFN of Bologna (Italy)

    2011-06-15

    In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: (http://www.pi.infn.it/SuperB)]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, (doi:10.1016/j.nima.2010.05.039)]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm{sup 2} with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack . s{sup -1} . cm{sup -2} with a temporal resolution below 1 {mu}s. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.

  1. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

    2018-03-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

  2. A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

    Science.gov (United States)

    Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

    2012-01-01

    This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

  3. Digital readout alpha survey instrument

    International Nuclear Information System (INIS)

    Jacobs, M.E.

    1976-01-01

    A prototype solid-state digital readout alpha particle survey instrument has been designed and constructed. The meter incorporates a Ludlum alpha scintillator as a detector, digital logic circuits for control and timing, and a Digilin counting module with reflective liquid crystal display. The device is used to monitor alpha radiation from a surface. Sample counts are totalized over 10-second intervals and displayed digitally in counts per minute up to 19,999. Tests over source samples with counts to 15,600 cpm have shown the device to be rapid, versatile and accurate. The instrument can be fabricated in one man-week and requires about $835 in material costs. A complete set of drawings is included

  4. Development of an external readout electronics for a hybrid photon detector

    CERN Document Server

    Uyttenhove, Simon; Tichon, Jacques; Garcia, Salvador

    The pixel hybrid photon detectors currently installed in the LHCb Cherenkov system encapsulate readout electronics in the vacuum tube envelope. The LHCb upgrade and the new trigger system will require their replacement with new photon detectors. The baseline photon detector candidate is the multi-anode photomultiplier. A hybrid photon detector with external readout electronics has been proposed as a backup option. This master thesis covers a R & D phase to investigate this latter concept. Extensive studies of the initial electronics system underlined the noise contributions from the Beetle chip used as front-end readout ASIC and from the ceramic carrier of the photon detector. New front-end electronic boards have been developed and made fully compatible with the existing LHCb-RICH infrastructure. With this compact readout system, Cherenkov photons have been successfully detected in a real particle beam environment. The proof-of-concept of a hybrid photon detector with external readout electronics was val...

  5. The AMS silicon tracker readout, performance results with minimum ionizing particles

    CERN Document Server

    Alpat, B; Battiston, R; Bourquin, Maurice; Burger, W J; Extermann, Pierre; Chang, Y H; Hou, S R; Pauluzzi, M; Produit, N; Qiu, S; Rapin, D; Ribordy, R; Toker, O; Wu, S X

    2000-01-01

    First results for the AMS silicon tracker readout performance are presented. Small 20.0*20.0*0.300 mm/sup 3/ silicon microstrip detectors were installed in a 50 GeV electron beam at CERN. The detector readout consisted of prototypes of the tracker data reduction card equipped with a 12-bit ADC and the tracker frontend hybrid with VA_hdr readout chips. The system performance is assessed in terms of signal-to-noise, position resolution, and efficiency. (13 refs).

  6. Efficient On-chip Optical Microresonator for Optical Comb Generation: Design and Fabrication

    Science.gov (United States)

    Han, Kyunghun

    An optical frequency comb is a series of equally spaced frequency components. It has gained much attention since Nobel physics prize was awarded John L. Hall and Theodor W. Hansch for their contribution to the optical frequency comb technique in 2005. The optical frequency comb has been extensively studied because of its precision as a tool for spectroscopy, and is now widely used in bio- and chemical sensors, optical clocks, mode-locked dark pulse generation, soliton generation, and optical communication. Recently, thanks to the developments in nanotechnology, the optical frequency comb generation is made possible at a chip-scale level with microresonators. However, because the threshold power of the optical frequency comb generation is beyond the capability of the on-chip laser source, efficient microresonator is required. Here, we demonstrate an ultra-compact and highly efficient strip-slot direct mode coupler, aiming to achieve slotted silicon microresonator cladded with nonlinear polymer Poly-DDMEBT in SOI platform. As an application of the strip-slot direct mode coupling, a double slot fiber-to-chip edge coupler is demonstrated showing 2 dB insertion loss reduction compared to the conventional single tip edge coupler. For silicon nitride platform, we investigated evanescent wave coupling of microresonator, focusing on bus waveguide geometry optimization. The optimized waveguide width offers an efficient excitation of a fundamental mode in the resonator waveguide. This investigation can benefit low threshold comb generation by enhancing the extinction ratio. We experimentally demonstrated the high Q-factor micro-ring resonator with intrinsic Q of 12.6 million as well as the single FSR comb generation with 63 mW.

  7. The front-end chip of the SuperB SVT detector

    International Nuclear Information System (INIS)

    Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.

    2013-01-01

    The asymmetric e + e − collider SuperB is designed to deliver a high luminosity, greater than 10 36 cm −2 s −1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

  8. Design of an Elliptic Curve Cryptography processor for RFID tag chips.

    Science.gov (United States)

    Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

    2014-09-26

    Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

  9. Four-channel readout ASIC for silicon pad detectors

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Zamiatin, N.I.

    2000-01-01

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e - +18e - /pF at 30 ns peaking time for detector capacitance up to C d =400 pF. Rise time is 8 ns at input capacitance C d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

  10. Characterization of Medipix3 with the MARS readout and software

    CERN Document Server

    Ronaldson, J P; van Leeuwen, D; Doesburg, R M N; Ballabriga, R; Butler, A P H; Donaldson, J; Walsh, M; Nik, S J; Clyne, M N

    2011-01-01

    The Medipix3 x-ray imaging detector has been characterized using the MARS camera. This x-ray camera comprises custom built readout electronics and software libraries designed for the Medipix family of detectors. The performance of the Medipix3 and MARS camera system is being studied prior to use in real-world applications such as the recently developed MARS-CT3 spectroscopic micro-CT scanner. We present the results of characterization measurements, describe methods for optimizing performance and give examples of spectroscopic images acquired with Medipix3 and the MARS camera system. A limited number of operating modes of the Medipix3 chip have been characterized and single-pixel mode has been found to give acceptable performance in terms of energy response, image quality and stability over time. Spectroscopic performance is significantly better in charge-summing mode than single-pixel mode however image quality and stability over time are compromised. There are more modes of operation to be tested and further...

  11. Microwave multiplex readout for superconducting sensors

    Energy Technology Data Exchange (ETDEWEB)

    Ferri, E., E-mail: elena.ferri@mib.infn.it [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Becker, D.; Bennett, D. [NIST, Boulder, CO (United States); Faverzani, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Fowler, J.; Gard, J. [NIST, Boulder, CO (United States); Giachero, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Hays-Wehle, J.; Hilton, G. [NIST, Boulder, CO (United States); Maino, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Mates, J. [NIST, Boulder, CO (United States); Puiu, A.; Nucciotti, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Reintsema, C.; Schmidt, D.; Swetz, D.; Ullom, J.; Vale, L. [NIST, Boulder, CO (United States)

    2016-07-11

    The absolute neutrino mass scale is still an outstanding challenge in both particle physics and cosmology. The calorimetric measurement of the energy released in a nuclear beta decay is a powerful tool to determine the effective electron-neutrino mass. In the last years, the progress on low temperature detector technologies has allowed to design large scale experiments aiming at pushing down the sensitivity on the neutrino mass below 1 eV. Even with outstanding performances in both energy (~ eV on keV) and time resolution (~ 1 μs) on the single channel, a large number of detectors working in parallel is required to reach a sub-eV sensitivity. Microwave frequency domain readout is the best available technique to readout large array of low temperature detectors, such as Transition Edge Sensors (TESs) or Microwave Kinetic Inductance Detectors (MKIDs). In this way a multiplex factor of the order of thousands can be reached, limited only by the bandwidth of the available commercial fast digitizers. This microwave multiplexing system will be used to readout the HOLMES detectors, an array of 1000 microcalorimeters based on TES sensors in which the {sup 163}Ho will be implanted. HOLMES is a new experiment for measuring the electron neutrino mass by means of the electron capture (EC) decay of {sup 163}Ho. We present here the microwave frequency multiplex which will be used in the HOLMES experiment and the microwave frequency multiplex used to readout the MKID detectors developed in Milan as well.

  12. Monitoring the CMS strip tracker readout system

    International Nuclear Information System (INIS)

    Mersi, S; Bainbridge, R; Cripps, N; Fulcher, J; Wingham, M; Baulieu, G; Bel, S; Delaere, C; Drouhin, F; Mirabito, L; Cole, J; Giassi, A; Gross, L; Hahn, K; Nikolic, M; Tkaczyk, S

    2008-01-01

    The CMS Silicon Strip Tracker at the LHC comprises a sensitive area of approximately 200 m 2 and 10 million readout channels. Its data acquisition system is based around a custom analogue front-end chip. Both the control and the readout of the front-end electronics are performed by off-detector VME boards in the counting room, which digitise the raw event data and perform zero-suppression and formatting. The data acquisition system uses the CMS online software framework to configure, control and monitor the hardware components and steer the data acquisition. The first data analysis is performed online within the official CMS reconstruction framework, which provides many services, such as distributed analysis, access to geometry and conditions data, and a Data Quality Monitoring tool based on the online physics reconstruction. The data acquisition monitoring of the Strip Tracker uses both the data acquisition and the reconstruction software frameworks in order to provide real-time feedback to shifters on the operational state of the detector, archiving for later analysis and possibly trigger automatic recovery actions in case of errors. Here we review the proposed architecture of the monitoring system and we describe its software components, which are already in place, the various monitoring streams available, and our experiences of operating and monitoring a large-scale system

  13. Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

    Science.gov (United States)

    Celik, Cihangir

    -scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement

  14. A multichannel front end ASIC for PMT readout in LHAASO WCDA

    Science.gov (United States)

    Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

    2018-01-01

    Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

  15. Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

    Directory of Open Access Journals (Sweden)

    Da-Sheng Lee

    2010-01-01

    Full Text Available Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design.

  16. System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

    Directory of Open Access Journals (Sweden)

    Daniel D. Gajski

    2008-07-01

    Full Text Available The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

  17. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Directory of Open Access Journals (Sweden)

    Cheng-Chun Wu

    2016-10-01

    Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  18. Transparent Nanopore Cavity Arrays Enable Highly Parallelized Optical Studies of Single Membrane Proteins on Chip.

    Science.gov (United States)

    Diederichs, Tim; Nguyen, Quoc Hung; Urban, Michael; Tampé, Robert; Tornow, Marc

    2018-06-13

    Membrane proteins involved in transport processes are key targets for pharmaceutical research and industry. Despite continuous improvements and new developments in the field of electrical readouts for the analysis of transport kinetics, a well-suited methodology for high-throughput characterization of single transporters with nonionic substrates and slow turnover rates is still lacking. Here, we report on a novel architecture of silicon chips with embedded nanopore microcavities, based on a silicon-on-insulator technology for high-throughput optical readouts. Arrays containing more than 14 000 inverted-pyramidal cavities of 50 femtoliter volumes and 80 nm circular pore openings were constructed via high-resolution electron-beam lithography in combination with reactive ion etching and anisotropic wet etching. These cavities feature both, an optically transparent bottom and top cap. Atomic force microscopy analysis reveals an overall extremely smooth chip surface, particularly in the vicinity of the nanopores, which exhibits well-defined edges. Our unprecedented transparent chip design provides parallel and independent fluorescent readout of both cavities and buffer reservoir for unbiased single-transporter recordings. Spreading of large unilamellar vesicles with efficiencies up to 96% created nanopore-supported lipid bilayers, which are stable for more than 1 day. A high lipid mobility in the supported membrane was determined by fluorescent recovery after photobleaching. Flux kinetics of α-hemolysin were characterized at single-pore resolution with a rate constant of 0.96 ± 0.06 × 10 -3 s -1 . Here, we deliver an ideal chip platform for pharmaceutical research, which features high parallelism and throughput, synergistically combined with single-transporter resolution.

  19. Design, fabrication, and evaluation of on-chip micro-supercapacitors

    Science.gov (United States)

    Beidaghi, Majid; Chen, Wei; Wang, Chunlei

    2011-06-01

    Development of miniaturized electronic systems has stimulated the demand for miniaturized power sources that can be integrated into such systems. Among the different micro power sources micro electrochemical energy storage and conversion devices are particularly attractive because of their high efficiency and relatively high energy density. Electrochemical micro-capacitors or micro-supercapacitors offer higher power density compared to micro-batteries and micro-fuel cells. In this paper, development of on-chip micro-supercapacitors based on interdigitated C-MEMS electrode microarrays is introduced. C-MEMS electrodes are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of EDLC or pseudo-capacitive materials. Recent advancements in fabrication methods of C-MEMS based micro-supercapacitors are discussed and electrochemical properties of C-MEMS electrodes and it composites are reviewed.

  20. 100 Gbps PCI-Express Readout for the LHCb Upgrade

    CERN Document Server

    Durante, Paolo; Schwemmer, Rainer; Marconi, Umberto; Balbi, Gabriele; Lax, Ignazio

    2015-01-01

    We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new common readout board, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We describe a new high-performance DMA controller for data acquisition, implemented on an FPGA, coupled with a custom software module for the Linux kernel. Lastly, we describe how these components can be leveraged to achieve a throughput of 100 Gbit/s per readout board.

  1. Intelligent microchip networks: an agent-on-chip synthesis framework for the design of smart and robust sensor networks

    Science.gov (United States)

    Bosse, Stefan

    2013-05-01

    Sensorial materials consisting of high-density, miniaturized, and embedded sensor networks require new robust and reliable data processing and communication approaches. Structural health monitoring is one major field of application for sensorial materials. Each sensor node provides some kind of sensor, electronics, data processing, and communication with a strong focus on microchip-level implementation to meet the goals of miniaturization and low-power energy environments, a prerequisite for autonomous behaviour and operation. Reliability requires robustness of the entire system in the presence of node, link, data processing, and communication failures. Interaction between nodes is required to manage and distribute information. One common interaction model is the mobile agent. An agent approach provides stronger autonomy than a traditional object or remote-procedure-call based approach. Agents can decide for themselves, which actions are performed, and they are capable of flexible behaviour, reacting on the environment and other agents, providing some degree of robustness. Traditionally multi-agent systems are abstract programming models which are implemented in software and executed on program controlled computer architectures. This approach does not well scale to micro-chip level and requires full equipped computers and communication structures, and the hardware architecture does not consider and reflect the requirements for agent processing and interaction. We propose and demonstrate a novel design paradigm for reliable distributed data processing systems and a synthesis methodology and framework for multi-agent systems implementable entirely on microchip-level with resource and power constrained digital logic supporting Agent-On-Chip architectures (AoC). The agent behaviour and mobility is fully integrated on the micro-chip using pipelined communicating processes implemented with finite-state machines and register-transfer logic. The agent behaviour

  2. Analog readout for optical reservoir computers

    OpenAIRE

    Smerieri, Anteo; Duport, François; Paquot, Yvan; Schrauwen, Benjamin; Haelterman, Marc; Massar, Serge

    2012-01-01

    Reservoir computing is a new, powerful and flexible machine learning technique that is easily implemented in hardware. Recently, by using a time-multiplexed architecture, hardware reservoir computers have reached performance comparable to digital implementations. Operating speeds allowing for real time information operation have been reached using optoelectronic systems. At present the main performance bottleneck is the readout layer which uses slow, digital postprocessing. We have designed a...

  3. Readout ASIC of pair-monitor for international linear collider

    International Nuclear Information System (INIS)

    Sato, Yutaro; Ikeda, Hirokazu; Ito, Kazutoshi; Miyamoto, Akiya; Nagamine, Tadashi; Sasaki, Rei; Takubo, Yosuke; Tauchi, Toshiaki; Yamamoto, Hitoshi

    2010-01-01

    The pair-monitor is a beam profile monitor at the interaction point of the international linear collider. A prototype of the readout ASIC for the pair-monitor has been designed and tested. Since the pair-monitor uses the hit distribution of electrons and positrons generated by the beam-crossing to measure the beam profile, the readout ASIC is designed to count the number of hits. In a prototype ASIC, 36 readout cells were implemented by TSMC 0.25-μm CMOS process. Each readout cell is equipped with an amplifier, comparator, 8-bit counter and 16 count-registers. By the operation test, all the ASIC component were confirmed to work correctly. As the next step, we develop the prototype ASIC with the silicon on insulator technology. It is produced with OKI 0.2-μm FD-SOI CMOS process.

  4. Design, Fabrication and Prototype testing of a Chip Integrated Micro PEM Fuel Cell Accumulator combined On-Board Range Extender

    International Nuclear Information System (INIS)

    Balakrishnan, A; Mueller, C; Reinecke, H

    2014-01-01

    In this work we present the design, fabrication and prototype testing of Chip Integrated Micro PEM Fuel Cell Accumulator (CIμ-PFCA) combined On-Board Range Extender (O-BRE). CIμ-PFCA is silicon based micro-PEM fuel cell system with an integrated hydrogen storage feature (palladium metal hydride), the run time of CIμ-PFCA is dependent on the stored hydrogen, and in order to extend its run time an O-BRE is realized (catalytic hydrolysis of chemical hydride, NaBH 4 . Combining the CIμ-PFCA and O-BRE on a system level have few important design requirements to be considered; hydrogen regulation, gas -liquid separator between the CIμ-PFCA and the O-RE. The usage of traditional techniques to regulate hydrogen (tubes), gas-liquid phase membranes (porous membrane separators) are less desirable in the micro domain, due to its space constraint. Our approach is to use a passive hydrogen regulation and gas-liquid phase separation concept; to use palladium membrane. Palladium regulates hydrogen by concentration diffusion, and its property to selectively adsorb only hydrogen is used as a passive gas-liquid phase separator. Proof of concept is shown by realizing a prototype system. The system is an assembly of CIμ-PFCA, palladium membrane and the O-BRE. The CIμ-PFCA consist of 2 individually processed silicon chips, copper supported palladium membrane realized by electroplating followed by high temperature annealing process under inter atmosphere and the O-BRE is realized out of a polymer substrate by micromilling process with platinum coated structures, which functions as a catalyst for the hydrolysis of NaBH 4 . The functionality of the assembled prototype system is demonstrated by the measuring a unit cell (area 1 mm 2 ) when driven by the catalytic hydrolysis of chemical hydride (NaBH 4 and the prototype system shows run time more than 15 hours

  5. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  6. Timing and Readout Contorl in the LHCb Upgraded Readout System

    CERN Document Server

    Alessio, Federico

    2016-01-01

    In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

  7. The NA62 Gigatracker: Detector properties and pixel read-out architectures

    International Nuclear Information System (INIS)

    Fiorini, M.; Carassiti, V.; Ceccucci, A.; Cortina, E.; Cotta Ramusino, A.; Dellacasa, G.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Martoiu, S.; Mazza, G.; Noy, M.; Petrucci, F.; Riedler, P.; Rivetti, A.; Tiuraniemi, S.

    2010-01-01

    The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconstruction with unprecedented time resolution (150 ps rms) in a harsh radiation environment. To meet these requirements, and in order to reduce material budget to a minimum, three hybrid silicon pixel detector stations will be installed in vacuum. An adequate strategy to compensate for the discriminator time-walk must be implemented and R and D investigating two different options is ongoing. Two read-out chip prototypes have been designed in order to compare their performance: one approach is based on the use of a constant-fraction discriminator followed by an on-pixel TDC, while the other one is based on the use of a time-over-threshold circuit followed by a TDC shared by a group of pixels. This paper describes the Gigatracker system, presents the global architectures of both read-out ASICs and reviews the current status of the R and D project.

  8. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    International Nuclear Information System (INIS)

    Fabbri, A; Notaristefani, F De; Galasso, M; Cencelli, V Orsolini; Falco, M D; Marinelli, M; Tortora, L; Verona, C; Rinati, G Verona

    2013-01-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ''Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  9. A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

    Science.gov (United States)

    Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

    2017-01-10

    This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

  10. Design and length optimization of an adiabatic coupler for on-chip vertical integration of rare-earth-doped double tungstate waveguide amplifiers

    NARCIS (Netherlands)

    Mu, Jinfeng; Sefünç, Mustafa; García Blanco, Sonia Maria

    2014-01-01

    The integration of rare-earth doped double tungstate waveguide amplifiers onto passive technology platforms enables the on-chip amplification of very high bit rate signals. In this work, a methodology for the optimized design of vertical adiabatic couplers between a passive Si3N4 waveguide and the

  11. Second-Generation Design of Micro-Spec: A Medium-Resolution, Submillimeter-Wavelength Spectrometer-on-a-Chip

    Science.gov (United States)

    Cataldo, G.; Barrentine, E. M.; Bulcha, B. T.; Ehsan, N.; Hess, L. A.; Noroozian, O.; Stevenson, T. R.; U-Yen, K.; Wollack, E. J.; Moseley, S. H.

    2018-04-01

    Micro-Spec (µ-Spec) is a direct-detection spectrometer which integrates all the components of a diffraction-grating spectrometer onto a ˜ 10-cm^2 chip through the use of superconducting microstrip transmission lines on a single-crystal silicon substrate. A second-generation µ-Spec is being designed to operate with a spectral resolution of 512 in the submillimeter (500-1000 µm, 300-600 GHz) wavelength range, a band of interest for several spectroscopic applications in astrophysics. High-altitude balloon missions would provide the first test bed to demonstrate the µ-Spec technology in a space-like environment and would be an economically viable venue for multiple observation campaigns. This work reports on the current status of the instrument design and will provide a brief overview of each instrument subsystem. Particular emphasis will be given to the design of the spectrometer's two-dimensional diffractive region, through which the light of different wavelengths is focused on the detectors along the focal plane. An optimization process is employed to generate geometrical configurations of the diffractive region that satisfy specific requirements on spectrometer size, operating spectral range, and performance. An optical design optimized for balloon missions will be presented in terms of geometric layout, spectral purity, and efficiency.

  12. Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

    International Nuclear Information System (INIS)

    Irmler, C.; Bauer, A.; Bergauer, T.; Adamczyk, K.; Bacher, S.; Aihara, H.; Angelini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Aziz, T.; Babu, V.; Bahinipati, S.; Barberio, E.; Baroncelli, Ti.; Baroncelli, To.; Basith, A.K.; Behera, P.K.; Bhuyan, B.; Bilka, T.

    2016-01-01

    The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests

  13. First considerations for a readout system for the ILD TPC with the Timepix3

    Energy Technology Data Exchange (ETDEWEB)

    Schiffer, Tobias [Universitaet Bonn (Germany); Collaboration: LCTPC-Deutschland-Collaboration

    2016-07-01

    For the planned International Linear Collider (ILC) two detectors are proposed. One of them, the International Large Detector (ILD) uses a Time Projektion Chamber (TPC) as the main tracking device. As a readout system for this TPC, pixel chips are one of the considered options. An integrated Micromegas stage is foreseen as gas amplification stage, which is built directly on top of the chip. Since first tests of a Pixel-TPC with 160 Timepix ASICs showed promising results, one is interested in developing a detector using the Timepix3 ASIC. It has several advantages, first of all its feature to measure ToT and a ToA at the same time and its significantly increased readout rate. For this purpose a readout system needs to be developed which fulfils the requirements of the Timpix3 ASIC and also has a high scalability. The main challenges are the high speed readout with a clock of up to 640 MHz and the reliability of the system. Also, the data driven as well as the frame-based readout of the Timepix3 needs to be considered for the implementation. The main goal is to provide a fast and parallel readout of several million channels. An overview and the status of the planning is given. Also, the development challenges are discussed.

  14. The ALTRO Chip A 16-channel A/D Converter and Digital Processor for Gas Detectors

    CERN Document Server

    Esteve-Bosch, R; Mota, B; Musa, L

    2003-01-01

    The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40MHz. After digitisation, a pipelined hardwired Processor is able to remove from the input signal a wide range of systematic and non-systematic perturbations, related to the non-ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Processor is able to suppress the signal tail within 1mus after the pulse pea...

  15. Design of a 9K illumina BeadChip for polar bears (Ursus maritimus) from RAD and transcriptome sequencing.

    Science.gov (United States)

    Malenfant, René M; Coltman, David W; Davis, Corey S

    2015-05-01

    Single-nucleotide polymorphisms (SNPs) offer numerous advantages over anonymous markers such as microsatellites, including improved estimation of population parameters, finer-scale resolution of population structure and more precise genomic dissection of quantitative traits. However, many SNPs are needed to equal the resolution of a single microsatellite, and reliable large-scale genotyping of SNPs remains a challenge in nonmodel species. Here, we document the creation of a 9K Illumina Infinium BeadChip for polar bears (Ursus maritimus), which will be used to investigate: (i) the fine-scale population structure among Canadian polar bears and (ii) the genomic architecture of phenotypic traits in the Western Hudson Bay subpopulation. To this end, we used restriction-site associated DNA (RAD) sequencing from 38 bears across their circumpolar range, as well as blood/fat transcriptome sequencing of 10 individuals from Western Hudson Bay. Six-thousand RAD SNPs and 3000 transcriptomic SNPs were selected for the chip, based primarily on genomic spacing and gene function respectively. Of the 9000 SNPs ordered from Illumina, 8042 were successfully printed, and - after genotyping 1450 polar bears - 5441 of these SNPs were found to be well clustered and polymorphic. Using this array, we show rapid linkage disequilibrium decay among polar bears, we demonstrate that in a subsample of 78 individuals, our SNPs detect known genetic structure more clearly than 24 microsatellites genotyped for the same individuals and that these results are not driven by the SNP ascertainment scheme. Here, we present one of the first large-scale genotyping resources designed for a threatened species. © 2014 John Wiley & Sons Ltd.

  16. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    Michalowska, A.

    2013-01-01

    designed two ASICs. The first one, Caterpylar, is a test-chip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D 2 R 1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16 *16 array. Each channel fits into a layout area of 300 μm - 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW/channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV. (author) [fr

  17. FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

    International Nuclear Information System (INIS)

    Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

    1998-01-01

    We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

  18. Optofluidic interferometry chip designs of differential NIR absorbance based sensors for identification and quantification of electrolytes

    NARCIS (Netherlands)

    Steen, Gerrit W.; Wexler, Adam D.; Offerhaus, Herman L.

    2014-01-01

    Design and optimization of integrated photonic NIR absorbance based sensors for identification and quantification of aqueous electrolytes was performed by simulation in MATLAB and Optodesigner. Ten designs are presented and compared for suitability.

  19. The PAUCam readout electronics system

    Science.gov (United States)

    Jiménez, Jorge; Illa, José M.; Cardiel-Sas, Laia; de Vicente, Juan; Castilla, Javier; Casas, Ricard

    2016-08-01

    The PAUCam is an optical camera with a wide field of view of 1 deg x 1 deg and up to 46 narrow and broad band filters. The camera is already installed on the William Herschel Telescope (WHT) in the Canary Islands, Spain and successfully commissioned during the first period of 2015. The paper presents the main results from the readout electronics commissioning tests and include an overview of the whole readout electronics system, its configuration and current performance.

  20. IDeF-X ECLAIRs: A CMOS ASIC for the Readout of CdTe and CdZnTe Detectors for High Resolution Spectroscopy

    International Nuclear Information System (INIS)

    Gevin, O.; Baron, P.; Coppolani, X.; Delagnes, E.; Lugiez, F.; Daly, F.; Limousin, O.; Meuris, A.; Pinsard, F.; Renaud, D.

    2009-01-01

    The very last member of the IDeF-X ASIC family is presented: IDeF-X ECLAIRs is a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. Thanks to its noise performance (Equivalent Noise Charge floor of 33 e - rms) and to its radiation hardened design (Single Event Latch-up Linear Energy Transfer threshold of 56 MeV.cm 2 .mg -1 ), the chip is well suited for soft X-rays energy discrimination and high energy resolution, 'space proof', hard X-ray spectroscopy. We measured an energy low threshold of less than 4 keV with a 10 pF input capacitor and a minimal reachable sensitivity of the Equivalent Noise Charge (ENC) to input capacitance of less than 7e - /pF obtained with a 6 μs peak time. IDeF-X ECLAIRs will be used for the readout of 6400 CdTe Schottky mono-pixel detectors of the 2D coded mask imaging telescope ECLAIRs aboard the SVOM satellite. IDeF-X ECLAIRs (or IDeF-X V2) has also been designed for the readout of a pixelated CdTe detector in the miniature spectro-imager prototype Caliste 256 that is currently foreseen for the high energy detector module of the Simbol-X mission. (authors)

  1. IDeF-X ECLAIRs: A CMOS ASIC for the Readout of CdTe and CdZnTe Detectors for High Resolution Spectroscopy

    Science.gov (United States)

    Gevin, Olivier; Baron, Pascal; Coppolani, Xavier; Daly, FranÇois; Delagnes, Eric; Limousin, Olivier; Lugiez, Francis; Meuris, Aline; Pinsard, FrÉdÉric; Renaud, Diana

    2009-08-01

    The very last member of the IDeF-X ASIC family is presented: IDeF-X ECLAIRs is a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. Thanks to its noise performance (Equivalent Noise Charge floor of 33 e- rms) and to its radiation hardened design (Single Event Latchup Linear Energy Transfer threshold of 56 MeV.cm2.mg-1), the chip is well suited for soft X-rays energy discrimination and high energy resolution, ldquospace proof,rdquo hard X-ray spectroscopy. We measured an energy low threshold of less than 4 keV with a 10 pF input capacitor and a minimal reachable sensitivity of the Equivalent Noise Charge (ENC) to input capacitance of less than 7 e-/pF obtained with a 6 mus peak time. IDeF-X ECLAIRs will be used for the readout of 6400 CdTe Schottky monopixel detectors of the 2D coded mask imaging telescope ECLAIRs aboard the SVOM satellite. IDeF-X ECLAIRs (or IDeF-X V2) has also been designed for the readout of a pixelated CdTe detector in the miniature spectro-imager prototype Caliste 256 that is currently foreseen for the high energy detector module of the Simbol-X mission.

  2. The pipelined readout for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Hervas, L.

    1991-01-01

    The electron-proton storage ring complex HERA under construction at DESY in Hamburg is the first machine of a new generation of colliders. Since physics to be studied at HERA (covered in chapter 2) base on the precise measurement of kinematic variables over a very large range of energies, a foremost emphasis is set in calorimetry. After long studies and an ambitious test program, the ZEUS collaboration has built a high resolution depleted uranium-scintillator calorimeter with photomultiplier readout, the state of the art in detectors of this type. In chapter 3 the principles of calorimetry are reviewed and the construction of the ZEUS calorimeter is described. Mainly due to the large dynamic range and the short bunch crossing times a novel concept for the readout in an analog pipelined fashion had to be designed. This concept is explained in chapter 4. The solid state implementation of the pipeline required two integrated circuits which were developed specially for the ZEUS calorimeter in collaboration with an electronics research institute and produced by industry. The design and construction of these devices and the detailed testing which has been performed for properties critical in the readout is covered in chapters 5 and 6. The whole pipelined readout is a complicated setup with many steps and collaborating systems. Its implementation and the information to operate it are covered in chapter 7. Finally the concepts presented and the applications discussed have been installed and tested on a test beam calibration experiment. There, the modules of the calorimeter have been calibrated. Chapter 8 presents results from these measurements which show excellent performance of the electronics as well as optimal properties of the calorimeter modules. (orig./HSI)

  3. Design, Construction and Testing of the Digital Hadron Calorimeter (DHCAL) Electronics

    CERN Document Server

    Adams, C; Bilki, B; Butler, J; Corriveau, F; Cundiff, T; Drake, G; Francis, K; Guarino, V; Haberichter, B; Hazen, E; Hoff, J; Holm, S; Kreps, A; DeLurgio, P; Monte, L Dal; Mucia, N; Norbeck, E; Northacker, D; Onel, Y; Pollack, B; Repond, J; Schlereth, J; Smith, J R; Trojand, D; Underwood, D; Velasco, M; Walendziak, J; Wood, K; Wu, S; Xia, L; Zhang, Q; Zhao, A

    2016-01-01

    A novel hadron calorimeter is being developed for future lepton colliding beam detectors. The calorimeter is optimized for the application of Particle Flow Algorithms (PFAs) to the measurement of hadronic jets and features a very finely segmented readout with 1 x 1 cm2 cells. The active media of the calorimeter are Resistive Plate Chambers (RPCs) with a digital, i.e. one-bit, readout. To first order the energy of incident particles in this calorimeter is reconstructed as being proportional to the number of pads with a signal over a given threshold. A large-scale prototype calorimeter with approximately 500,000 readout channels has been built and underwent extensive testing in the Fermilab and CERN test beams. This paper reports on the design, construction, and commissioning of the electronic readout system of this prototype calorimeter. The system is based on the DCAL front-end chip and a VME-based back-end.

  4. A radiation-tolerant electronic readout system for portal imaging

    Science.gov (United States)

    Östling, J.; Brahme, A.; Danielsson, M.; Iacobaeus, C.; Peskov, V.

    2004-06-01

    A new electronic portal imaging device, EPID, is under development at the Karolinska Institutet and the Royal Institute of Technology. Due to considerable demands on radiation tolerance in the radiotherapy environment, a dedicated electronic readout system has been designed. The most interesting aspect of the readout system is that it allows to read out ˜1000 pixels in parallel, with all electronics placed outside the radiation beam—making the detector more radiation resistant. In this work we are presenting the function of a small prototype (6×100 pixels) of the electronic readout board that has been tested. Tests were made with continuous X-rays (10-60 keV) and with α particles. The results show that, without using an optimised gas mixture and with an early prototype only, the electronic readout system still works very well.

  5. Study for the LHCb upgrade read-out board

    CERN Document Server

    Cachemiche, J P; Hachon, F; Le Gac, R; Marin, F; 10.1088/1748-0221/5/12/C12036

    2010-01-01

    The LHCb experiment envisages to upgrade its readout electronics in order to increase the readout rate from 1 MHz to 40 MHz. This electronics upgrade is very challenging, since readout boards will have to handle a higher number of serial links with an increased bandwidth. In addition, the new communication protocol (GBT) developed by the CERN micro-electronics group mixes data acquisition, slow control and clock distribution on the same link. To explore the feasibility of such a readout system, elementary building blocks have been studied. Their goals are multiple: understand signal integrity when using highly integrated high speed serial links running at 8 - 10 Gbits/s; test the implementation of the GBT protocol within FPGAs; understand advantages and limitations of commercial standard with a predefined interconnection topology; validate ideas on how to control easily such a system. We designed two boards compliant with the xTCA standard which meets an increasing interest in the physics community. The first...

  6. FE-I4 pixel chip characterization with USBpix3 test system

    Energy Technology Data Exchange (ETDEWEB)

    Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2015-07-01

    The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

  7. How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

    International Nuclear Information System (INIS)

    Pfeiffer, K.F.G.

    2003-01-01

    Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

  8. Calibration of ALIBAVA readout system

    Energy Technology Data Exchange (ETDEWEB)

    Trofymov, Artur [DESY, Hamburg (Germany); Collaboration: ATLAS experiment-Collaboration

    2015-07-01

    The High Luminosity Large Hadron Collider (LH-LHC) is the upgrade of the LHC that foreseen to increase the instantaneous luminosity by a factor ten with a total integrated luminosity of 3000 fb{sup -1}. The ATLAS experiment will need to build a new tracker to operate in the new severe LH-LHC conditions (increasing detector granularity to cope with much higher channel occupancy, designing radiation-hard sensors and electronics to cope with radiation damage). Charge collection efficiency (CCE) of silicon strip sensors for the new ATLAS tracker can be done with ALIBAVA analog readout system (analog system gives more information about signal from all strips than digital). In this work the preliminary results of ALIBAVA calibration using two different methods (with ''source data'' and ''calibration data'') are presented. Calibration constant obtained by these methods is necessary for knowing collected charge on the silicon strip sensors and for having the ability to compare it with measurements done at the test beam.

  9. Medipix3 array high performance read-out board for synchrotron research

    International Nuclear Information System (INIS)

    Tartoni, N.; Horswell, I. C.; Marchal, J.; Gimenez, E. N.; Fearn, R. D.; Silfhout, R. G. van

    2010-01-01

    The Medipix3 ASIC is one of the most advanced chip that is presently available to build photon counting area detectors. The capabilities of the chip include adjacent pixels charge summing circuitry to sort out the distortion due to charge sharing, simultaneous counting and read-out that enables frames to be acquired without dead time, the colour mode of operation that enables up to eight energy bands to be acquired. In order to fully exploit the capabilities of the Medipix3 chip in synchrotron research, a high performance electronic board capable of driving large arrays of chips is necessary. We propose a parallel read-out board of Medipix3 chip arrays with a scalable architecture that allows driving the Medipix3 chip in all of its modes of operation. The board functions include the control of the chip arrays, data formatting and data compression, the management of the communications with the data storage devices, and operation in various trigger modes. In addition to this the board will have some 'intelligence' embedded. This will add some very important features to the final detector such as pattern recognition, capability of variable frame duration as a function of the photon flux, feedback to other equipment and real time calculations of data relevant to experiments such as the autocorrelation function.

  10. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  11. Design and simulation of a fast Josephson junction on-chip gated clock for frequency and time analysis

    International Nuclear Information System (INIS)

    Ruby, R.C.

    1991-01-01

    This paper reports that as the sophistication and speed of digital communication systems increase, there is a corresponding demand for more sophisticated and faster measurement instruments. One such instrument new on the market is the HP 5371A Frequency and Time Interval Analyzer (FTIA). Such an instrument is analogous to a conventional oscilloscope. Whereas the oscilloscope measures waveform amplitudes as a function of time, the FTIA measures phase, frequency, or timing events as functions of time. These applications are useful in such diverse areas as spread-spectrum radar, chirp filter designs, disk-head evaluation, and timing jitter analysis. The on-chip clock designed for this application uses a single Josephson Junction as the clock and a resonator circuit to fix the frequency. A zero-crossing detector is used to start and stop the clock. A SFQ counter is used to count the pulses generated by the clock and a reset circuit is used to reset the clock. Extensive simulations and modeling have been done based on measured values obtained from our Nb/Al 2 O 3 /Al/Nb process

  12. Easy simulation and design of on-chip inductors in standard CMOS processes

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jørgensen, Allan

    1998-01-01

    This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design...... close-to-optimal inductors without the use of electromagnetic simulators...

  13. Cryogenic readout techniques for germanium detectors

    Energy Technology Data Exchange (ETDEWEB)

    Benato, G. [University of Zurich, (Switzerland); Cattadori, C. [INFN - Milano Bicocca, (Italy); Di Vacri, A. [INFN LNGS, (Italy); Ferri, E. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy); D' Andrea, V.; Macolino, C. [GSSI/INFN LNGS, (Italy); Riboldi, S. [Universita degli Studi di Milano/INFN Milano, (Italy); Salamida, F. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy)

    2015-07-01

    High Purity Germanium detectors are used in many applications, from nuclear and astro-particle physics, to homeland security or environment protection. Although quite standard configurations are often used, with cryostats, charge sensitive amplifiers and analog or digital acquisition systems all commercially available, it might be the case that a few specific applications, e.g. satellites, portable devices, cryogenic physics experiments, etc. also require the development of a few additional or complementary techniques. An interesting case is for sure GERDA, the Germanium Detector Array experiment, searching for neutrino-less double beta decay of {sup 76}Ge at the Gran Sasso National Laboratory of INFN - Italy. In GERDA the entire detector array, composed of semi-coaxial and BEGe naked crystals, is operated suspended inside a cryostat filled with liquid argon, that acts not only as cooling medium and but also as an active shield, thanks to its scintillation properties. These peculiar circumstances, together with the additional requirement of a very low radioactive background from all the materials adjacent to the detectors, clearly introduce significant constraints on the design of the Ge front-end readout electronics. All the Ge readout solutions developed within the framework of the GERDA collaboration, for both Phase I and Phase II, will be briefly reviewed, with their relative strength and weakness compared together and with respect to ideal Ge readout. Finally, the digital processing techniques developed by the GERDA collaboration for energy estimation of Ge detector signals will be recalled. (authors)

  14. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  15. Drag &Drop, Mixed-Methodology-based Lab-on-Chip Design Optimization Software, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall objective is to develop a ?mixed-methodology?, drag and drop, component library (fluidic-lego)-based, system design and optimization tool for complex...

  16. On-chip integration of a superconducting microwave circulator and a Josephson parametric amplifier

    Science.gov (United States)

    Rosenthal, Eric I.; Chapman, Benjamin J.; Moores, Bradley A.; Kerckhoff, Joseph; Malnou, Maxime; Palken, D. A.; Mates, J. A. B.; Hilton, G. C.; Vale, L. R.; Ullom, J. N.; Lehnert, K. W.

    Recent progress in microwave amplification based on parametric processes in superconducting circuits has revolutionized the measurement of feeble microwave signals. These devices, which operate near the quantum limit, are routinely used in ultralow temperature cryostats to: readout superconducting qubits, search for axionic dark matter, and characterize astrophysical sensors. However, these amplifiers often require ferrite circulators to separate incoming and outgoing traveling waves. For this reason, measurement efficiency and scalability are limited. In order to facilitate the routing of quantum signals we have created a superconducting, on-chip microwave circulator without permanent magnets. We integrate our circulator on-chip with a Josephson parametric amplifier for the purpose of near quantum-limited directional amplification. In this talk I will present a design overview and preliminary measurements.

  17. A study of SEU-tolerant latches for the RD53A chip

    CERN Document Server

    Fougeron, Denis

    2018-01-01

    The RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process has been adopted in order to satisfy the high level of integration requirement. However, the SEU immunity should be carefully considered for a deep submicron process like the 65 nm. Indeed, the device dimensions are small and the capacitance of the storage nodes becomes very low. A chip prototype including different SEU tolerant structures was designed in a 65 nm technology. Several proton irradiation tests were carried out in order to estimate the SEU tolerance of the proposed structures and the level of improvement comparing with a standard architecture.

  18. Design and Research of Intelligent Remote Control Fan Based on Single Chip Microcomputer and Bluetooth Technology

    Directory of Open Access Journals (Sweden)

    Zhang Xue-Xia

    2017-01-01

    Full Text Available This paper is designed for intelligent remote control fans. The design of the microcontroller as the core, the sensor, Bluetooth and Andrews system applied to the design of intelligent remote control fan. According to the temperature sensor to achieve the indoor temperature collection, to achieve and set the temperature comparison, thus affecting the fan speed. At the same time, the system according to the infrared sensor components to detect external factors, in order to achieve the running or stopping of the fan, that is, to achieve intelligent control of the fan. In addition, the system achieve the Bluetooth and mobile phone Andrews system of effective combination, and through the software program to complete the fan remote operation and wind speed control.

  19. A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed For Evolvability

    DEFF Research Database (Denmark)

    Patou, François; Dimaki, Maria; Svendsen, Winnie Edith

    2015-01-01

    for this work. We introduce a smart-mobile and LoC-based system architecture designed for evolvability. By propagating LoC programmability, instrumentation, and control tools to the highlevel abstraction smart-mobile software layer, our architecture facilitates the realisation of new use...

  20. Design and Characterization of a 52K SNP Chip for Goats

    NARCIS (Netherlands)

    Tosser-klopp, G.; Bardou, P.; Bouchez, O.; Cabau, C.; Crooijmans, R.P.M.A.; Dong, Y.; Donnadieu-Tonon, C.; Eggen, A.; Heuven, H.C.M.; Jamli, S.; Jiken, A.J.; Klopp, C.; Lawley, C.T.; McEwen, J.; Martin, P.; Moreno, C.R.; Mulsant, P.; Nabihoudine, I.; Pailhoux, E.; Palhiere, I.; Rupp, R.; Sarry, J.; Sayre, B.L.; Tircazes, A.; Wang, J.; Wang, W.; Zhang, W.G.

    2014-01-01

    The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a

  1. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind

    International Nuclear Information System (INIS)

    Pajuelo, L.

    2015-01-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  2. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  3. Investigation of image distortion due to MCP electronic readout misalignment and correction via customized GUI application

    Science.gov (United States)

    Vitucci, G.; Minniti, T.; Tremsin, A. S.; Kockelmann, W.; Gorini, G.

    2018-04-01

    The MCP-based neutron counting detector is a novel device that allows high spatial resolution and time-resolved neutron radiography and tomography with epithermal, thermal and cold neutrons. Time resolution is possible by the high readout speeds of ~ 1200 frames/sec, allowing high resolution event counting with relatively high rates without spatial resolution degradation due to event overlaps. The electronic readout is based on a Timepix sensor, a CMOS pixel readout chip developed at CERN. Currently, a geometry of a quad Timepix detector is used with an active format of 28 × 28 mm2 limited by the size of the Timepix quad (2 × 2 chips) readout. Measurements of a set of high-precision micrometers test samples have been performed at the Imaging and Materials Science & Engineering (IMAT) beamline operating at the ISIS spallation neutron source (U.K.). The aim of these experiments was the full characterization of the chip misalignment and of the gaps between each pad in the quad Timepix sensor. Such misalignment causes distortions of the recorded shape of the sample analyzed. We present in this work a post-processing image procedure that considers and corrects these effects. Results of the correction will be discussed and the efficacy of this method evaluated.

  4. Design of indoor temperature and humidity detection system based on single chip microcomputer

    Science.gov (United States)

    Fu, Xiuwei; Fu, Li; Ma, Tianhui

    2018-03-01

    The indoor temperature and humidity detection system based on STC15F2K60S2 is designed in this paper. The temperature and humidity sensor DHT22 to monitor the indoor temperature and humidity are used, and the temperature and humidity data to the user's handheld device are wirelessly transmitted, when the temperature reaches or exceeds the user set the temperature alarm value, and the system sound and light alarm, to remind the user.

  5. 18k Channels single photon counting readout circuit for hybrid pixel detector

    International Nuclear Information System (INIS)

    Maj, P.; Grybos, P.; Szczygiel, R.; Zoladz, M.; Sakumura, T.; Tsuji, Y.

    2013-01-01

    We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm×20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96×192 pixels with 100 μm×100 μm pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 μW/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 μV/e − and the equivalent noise charge is 168 e − rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

  6. 18k Channels single photon counting readout circuit for hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Maj, P., E-mail: piotr.maj@agh.edu.pl [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Grybos, P.; Szczygiel, R.; Zoladz, M. [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Sakumura, T.; Tsuji, Y. [X-ray Analysis Division, Rigaku Corporation, Matsubara, Akishima, Tokyo 196-8666 (Japan)

    2013-01-01

    We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm Multiplication-Sign 20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96 Multiplication-Sign 192 pixels with 100 {mu}m Multiplication-Sign 100 {mu}m pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 {mu}W/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 {mu}V/e{sup -} and the equivalent noise charge is 168 e{sup -} rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

  7. Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

    OpenAIRE

    Lee, Da-Sheng

    2010-01-01

    Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DN...

  8. [The system design of an intraperitoneal perfusion machine for hyperthermic chemotherapy based on single chip microcomputer].

    Science.gov (United States)

    Zhang, Zhiyong; Yang, Xuandong; Li, Kaiyang

    2005-06-01

    A new kind of method for intraperitoneal hyperthermic chemotherapy has been proved to be very effective for the therapy of gastrointestinal cancer. In this article is reported an intraperitoneal perfusion machine which is designed for instituting the treatment. The liquor of the chemotherapy drug is infused into the abdomen after being heated by heating system; the liquor flows out of the abdomen is abandoned. The temperature of heating and the velocity of flow are controlled by MCU, thus the temperature of the liquor of the chemotherapy drug in the abdomen can be adjusted to the most favarable temperature.

  9. A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)

    International Nuclear Information System (INIS)

    Perktold, L; Rinella, G Aglieri; Noy, M; Kluge, A; Kloukinas, K; Kaplon, J; Jarron, P; Morel, M; Fiorini, M; Martin, E

    2012-01-01

    The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100 ps. Simulation results show that an average rms time resolution of 33 ps with a power consumption of the TDC better than 33 mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.

  10. A Readout Integrated Circuit (ROIC) employing self-adaptive background current compensation technique for Infrared Focal Plane Array (IRFPA)

    Science.gov (United States)

    Zhou, Tong; Zhao, Jian; He, Yong; Jiang, Bo; Su, Yan

    2018-05-01

    A novel self-adaptive background current compensation circuit applied to infrared focal plane array is proposed in this paper, which can compensate the background current generated in different conditions. Designed double-threshold detection strategy is to estimate and eliminate the background currents, which could significantly reduce the hardware overhead and improve the uniformity among different pixels. In addition, the circuit is well compatible to various categories of infrared thermo-sensitive materials. The testing results of a 4 × 4 experimental chip showed that the proposed circuit achieves high precision, wide application and high intelligence. Tape-out of the 320 × 240 readout circuit, as well as the bonding, encapsulation and imaging verification of uncooled infrared focal plane array, have also been completed.

  11. Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

    Science.gov (United States)

    Fossum, Eric R.

    The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

  12. The Belle II SVD data readout system

    Energy Technology Data Exchange (ETDEWEB)

    Thalmeier, R., E-mail: Richard.Thalmeier@oeaw.ac.at [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Adamczyk, K. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Aihara, H. [Department of Physics, University of Tokyo, Tokyo 113-0033 (Japan); Angelini, C. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Aziz, T.; Babu, V. [Tata Institute of Fundamental Research, Mumbai 400005 (India); Bacher, S. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Bahinipati, S. [Indian Institute of Technology Bhubaneswar, Satya Nagar (India); Barberio, E.; Baroncelli, Ti.; Baroncelli, To. [School of Physics, University of Melbourne, Melbourne, Victoria 3010 (Australia); Basith, A.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Batignani, G. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bauer, A. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Behera, P.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Bettarini, S. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bhuyan, B. [Indian Institute of Technolog y Guwahati, Assam 781039 (India); Bilka, T. [Faculty of Mathematics and Physics, Charles University, 12116 Prague (Czech Republic); Bosi, F. [INFN Sezione di Pisa, I-56127 Pisa (Italy); and others

    2017-02-11

    The Belle II Experiment at the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, will explore the asymmetry between matter and antimatter and search for new physics beyond the standard model. 172 double-sided silicon strip detectors are arranged cylindrically in four layers around the collision point to be part of a system which measures the tracks of the collision products of electrons and positrons. A total of 1748 radiation-hard APV25 chips read out 128 silicon strips each and send the analog signals by time-division multiplexing out of the radiation zone to 48 Flash Analog Digital Converter Modules (FADC). Each of them applies processing to the data; for example, it uses a digital finite impulse response filter to compensate line signal distortions, and it extracts the peak timing and amplitude from a set of several data points for each hit, using a neural network. We present an overview of the SVD data readout system, along with front-end electronics, cabling, power supplies and data processing.

  13. AVME readout module for multichannel ASIC characterization

    International Nuclear Information System (INIS)

    Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

    2004-01-01

    Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

  14. Tracker Readout ASIC for Proton Computed Tomography Data Acquisition.

    Science.gov (United States)

    Johnson, Robert P; Dewitt, Joel; Holcomb, Cole; Macafee, Scott; Sadrozinski, Hartmut F-W; Steinberg, David

    2013-10-01

    A unique CMOS chip has been designed to serve as the front-end of the tracking detector data acquisition system of a pre-clinical prototype scanner for proton computed tomography (pCT). The scanner is to be capable of measuring one to two million proton tracks per second, so the chip must be able to digitize the data and send it out rapidly while keeping the front-end amplifiers active at all times. One chip handles 64 consecutive channels, including logic for control, calibration, triggering, buffering, and zero suppression. It outputs a formatted cluster list for each trigger, and a set of field programmable gate arrays merges those lists from many chips to build the events to be sent to the data acquisition computer. The chip design has been fabricated, and subsequent tests have demonstrated that it meets all of its performance requirements, including excellent low-noise performance.

  15. A TDC integrated circuit for drift chamber readout

    International Nuclear Information System (INIS)

    Passaseo, M.; Petrolo, E.; Veneziano, S.

    1995-01-01

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

  16. A TDC integrated circuit for drift chamber readout

    Energy Technology Data Exchange (ETDEWEB)

    Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

    1995-12-11

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

  17. Development of radiation hard readout electronics for LHCb

    CERN Document Server

    Sexauer, Edgar; Lindenstruth, Volker

    2001-01-01

    The experiment LHCb is under development at CERN and aims to measure CP-violation in the B-Meson system at very high precision. The experiment makes use of a vertex detector that is equipped with silicon microstrip detectors. A chip suitable for the readout of this detector has been developed in a working group at the ASIC-laboratory Heidelberg. This readout chip 'Beetle-1.0' contains 128 analog input stages of a charge sensitive preamplifier, a pulse shaper and a buffer. The analog signal is fed into a comparator, from which a fast trigger signal can be derived. The following pipeline, realized as an array of gate capacitances, can be used to either store the analog output of the input amplifiers or to store the digital comparator output. External trigger signals mark events that have to be read out and the according pipeline location is stored in a derandomizing buffer. Pending events are read out from the pipeline via a charge-sensitive, resetable amplifier and an analog multiplexer, which serializes the s...

  18. Monitoring bacterial biofilms with a microfluidic flow chip designed for imaging with white-light interferometry

    Energy Technology Data Exchange (ETDEWEB)

    Brann, Michelle; Suter, Jonathan D.; Addleman, R. Shane; Larimer, Curtis

    2017-07-01

    There is a need for imaging and sensing instrumentation that can monitor transitions in biofilm structure in order to better understand biofilm development and emergent properties such as anti-microbial resistance. Herein, we expanded on our previously reported technique for measuring and monitoring the thickness and topology of live biofilms using white-light interferometry (WLI). A flow cell designed for WLI enabled the use of this non-disruptive imaging method for the capture of high resolution three-dimensional profile images of biofilm growth over time. The fine axial resolution (3 nm) and wide field of view (>1 mm by 1 mm) enabled detection of biofilm formation as early as three hours after inoculation of the flow cell with a live bacterial culture (Pseudomonas fluorescens). WLI imaging facilitated monitoring the early stages of biofilm development and subtle variations in the structure of mature biofilms. Minimally-invasive imaging enabled monitoring of biofilm structure with surface metrology metrics (e.g., surface roughness). The system was used to observe a transition in biofilm structure that occurred in response to expsoure to a common antiseptic. In the future, WLI and the biofilm imaging cell described herein may be used to test the effectiveness of biofilm-specific therapies to combat common diseases associated with biofilm formation such as cystic fibrosis and periodontitis.

  19. Multi-Anode Photomultplier (MAPMT) readout for High Granularity Calorimeters

    CERN Document Server

    Mkrtchyan, Tigran; The ATLAS collaboration

    2017-01-01

    Hadron calorimeter high performance in jet sub-structure measurements can be achieved for objects with $p_{T}$ greater than 1 TeV if the readout geometry is finely segmented in $\\Delta\\eta \\times \\Delta\\phi$. A feasibility study to increase the readout granularity of TileCal, the central hadron calorimeter of the ATLAS detector, is presented. We show a preliminary study exploring the possibility to increase by a factor 4 the present readout granularity of the inner layer cells of TileCal (0.1->0.025 in $\\Delta\\eta$) and to split into two layers the intermediate section of TileCal. The proposed solution is designed to cope with mechanical and readout bandwidth and power constraints. Assuming that the mechanics of the Tile modules cannot be changed, Multi-Anode PMTs with same boundary geometry of the present single-anode PMTs are considered to readout WLS bers, ideally one per pixel, carrying the signals from the individual scintillating tiles of each detector cells. The discussed challenges of the design are: ...

  20. A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

    Science.gov (United States)

    Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

    2010-12-01

    We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64×64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

  1. A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

    Energy Technology Data Exchange (ETDEWEB)

    Schanz, T., E-mail: schanz@astro.uni-tuebingen.d [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany); Tenzer, C., E-mail: tenzer@astro.uni-tuebingen.d [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany); Maier, D.; Kendziorra, E.; Santangelo, A. [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany)

    2010-12-11

    We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64x64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

  2. A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

    International Nuclear Information System (INIS)

    Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

    2010-01-01

    We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64x64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

  3. CASAGEM: a readout ASIC for micro pattern gas detectors

    International Nuclear Information System (INIS)

    He Li; Deng Zhi; Liu Yinong

    2012-01-01

    A readout ASIC for micro pattern gas detectors has been designed This ASIC integrates 16 channels for anode readout and 1 channel for cathode readout which can make use of the signal of detector's cathode to generate a trigger Every channel can provide amplification and shaping of detector signals. The ASIC can also provide adjustable gain which can be adjusted from 2 mV/fC to 40 mV/fC, and adjustable shaping time which can be adjusted from 20 ns to 80 ns; so this ASIC can be applied to detectors with wide range output signal and different counting rate. The ASIC is fabricated with Chartered 0.35 μm CMOS process More circuit design Details and test results will be presented. (authors)

  4. Readout Electronics Upgrades of the ATLAS Liquid Argon Calorimeter

    CERN Document Server

    Anelli, Christopher Ryan; The ATLAS collaboration

    2018-01-01

    The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. First prototypes of the front-end electronics components show good promise to match the stringent specifications. The off-detector electronics will make use of FPGAs connected through high-speed links to perform energy reconstruction, data reduction and buffering. Results of tests of the first prototypes of front-end components will be presented, along with design studies on the performance of the off-detector readout system.

  5. The ALICE Time of Flight Readout System AFRO

    CERN Document Server

    Kluge, A

    1999-01-01

    The ALICE Time of Flight Detector system comprises more than 100.000 channels and covers an area of more than 100 m2. The timing resolution should be better than 150 ps. This combination of requirements poses a major challenge to the readout system. All detector timing measurements are referenced to a unique start signal t0. This signal is generated at the time an event occurs. Timing measurements are performed using a multichannel TDC chip which requires a 40 MHz reference clock signal. The general concept of the readout system is based on a modular architecture. Detector cells are combined to modules of 1024 channels. Each of these modules can be read out and calibrated independently from each other. By distributing a reference signal, a timing relationship between the modules is established. This reference signal can either be the start signal t0 or the TDC-reference clock. The readout architecture is divided into three steps; the TDC controller, the module controller, and the time of flight controller. Th...

  6. General-purpose readout electronics for white neutron source at China Spallation Neutron Source.

    Science.gov (United States)

    Wang, Q; Cao, P; Qi, X; Yu, T; Ji, X; Xie, L; An, Q

    2018-01-01

    The under-construction White Neutron Source (WNS) at China Spallation Neutron Source is a facility for accurate measurements of neutron-induced cross section. Seven spectrometers are planned at WNS. As the physical objectives of each spectrometer are different, the requirements for readout electronics are not the same. In order to simplify the development of the readout electronics, this paper presents a general method for detector signal readout. This method has advantages of expansibility and flexibility, which makes it adaptable to most detectors at WNS. In the WNS general-purpose readout electronics, signals from any kinds of detectors are conditioned by a dedicated signal conditioning module corresponding to this detector, and then digitized by a common waveform digitizer with high speed and high precision (1 GSPS at 12-bit) to obtain the full waveform data. The waveform digitizer uses a field programmable gate array chip to process the data stream and trigger information in real time. PXI Express platform is used to support the functionalities of data readout, clock distribution, and trigger information exchange between digitizers and trigger modules. Test results show that the performance of the WNS general-purpose readout electronics can meet the requirements of the WNS spectrometers.

  7. Fiscal 2000 research achievement report on the research and development of advanced design technologies for system-on-chip; 2000 nendo system on chip sentan sekkei gijutsu no kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-05-01

    Efforts were made to develop technologies for rapid improvement in SoC (system on chip) design productivity. In concrete terms, the concept of V-core (virtual core) was introduced into SoC design for the establishment of reusing technology and design automation in the uppermost stream region of designing. Activities were conducted in the two fields of (1) research and development of V-core based design technology and (2) research and development of a V-core database. Efforts exerted in field (1) aimed at the research and development of system specifications description technology, architecture generation technology, soft V-core internal structure optimization technology, optimized RTL (register transfer level) description generation technology, and system performance verification technology. In field (2), efforts were made to develop core database technology, core development support tools, core verification technology, and design assets verification technology. The system specifications description technology is a technique to define SoC system level specifications (degree of model abstraction). (NEDO)

  8. Progress on the development of a detector mounted analog and digital readout system for the ATLAS TRT

    CERN Document Server

    Baxter, C; Dressnandt, N; Gay, C; Lundberg, B; Munar, A; Mayers, G; Newcomer, M; Van Berg, R; Williams, H H

    2004-01-01

    The 430,000 element ATLAS Transition Radiation straw tube Tracker (TRT) is divided into a central barrel tracker consisting of 104,000 axially mounted straws and two radially arranged end caps on either side of the barrel with 160,000 straws each. To achieve a track position resolution of 140 mu m, the front end electronics must operate at a low (2fC) threshold with a time marking capability of ~1ns. Two ASICs, the ASDBLR and DTMROC provide the complete pipelined readout chain. Custom designed FBGA packages for the ASICs provide a small enough outline to be detector mounted and the extensive use of low level differential signals make mounting the analog packages on printed circuit boards directly opposite the 40 MHz digital chips feasible. The readout electronics for the barrel occupies a potentially important part of the active tracker volume and an aggressive effort has been made to make it as compact as possible. Utilizing a single board for both analog and digital ASICS a 0.1 cm /sup 3/ per channel volume...

  9. A readout buffer prototype for ATLAS high-level triggers

    CERN Document Server

    Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

    2001-01-01

    Readout buffers are critical components in the dataflow chain of the ATLAS trigger/data-acquisition system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several readout buffers are grouped to form a readout buffer complex that acts as a data server for the high-level trigger selection algorithms and for the final data-collection system. This paper describes a functional prototype of a readout buffer based on a custom-made PCI mezzanine card that is designed to accept input data at up to 160 MB /s, to store up to 8 MB of data, and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and complex programmable logic devices. We present the integration of several of these cards in a readout buffer complex. We measure various performance figures and discuss to which extent these can fulfil ATLAS needs. (5 refs).

  10. Novel concept of TDI readout circuit for LWIR detector

    Science.gov (United States)

    Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

    2000-07-01

    Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

  11. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    International Nuclear Information System (INIS)

    Harion, T; Briggl, K; Chen, H; Gil, A; Kiworra, V; Schultz-Coulon, H-C; Shen, W; Stankova, V; Fischer, P; Ritzert, M

    2014-01-01

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm 3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements

  12. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  13. DRM2: the readout board for the ALICE TOF upgrade

    CERN Document Server

    Falchieri, Davide

    2018-01-01

    For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low-jitter clock. Compared to the old board, the DRM2 is able to cope with faster trigger rates and provides a larger data bandwidth towards the DAQ. The results of the measurements on the received clock jitter and data transmission performances in a full crate are given.

  14. The readout performance evaluation of PowerPC

    International Nuclear Information System (INIS)

    Chu Yuanping; Zhang Hongyu; Zhao Jingwei; Ye Mei; Tao Ning; Zhu Kejun; Tang Suqiu; Guo Yanan

    2003-01-01

    PowerPC, as a powerful low-cost embedded computer, is one of the very important research objects in recent years in the project of BESIII data acquisition system. The researches on the embedded system and embedded computer have achieved many important results in the field of High Energy Physics especially in the data acquisition system. The one of the key points to design an acquisition system using PowerPC is to evaluate the readout ability of PowerPC correctly. The paper introduce some tests for the PowerPC readout performance. (authors)

  15. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    Science.gov (United States)

    Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

    2015-06-01

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

  16. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    International Nuclear Information System (INIS)

    Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P.L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C.A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.

    2015-01-01

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented

  17. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    Energy Technology Data Exchange (ETDEWEB)

    Yang, P., E-mail: yangping0710@126.com [Central China Normal University, Wuhan (China); Aglieri, G.; Cavicchioli, C. [CERN, 1210 Geneva 23 (Switzerland); Chalmet, P.L. [MIND, Archamps (France); Chanlek, N. [Suranaree University of Technology, Nakhon Ratchasima (Thailand); Collu, A. [University of Cagliari, Cagliari (Italy); INFN (Italy); Gao, C. [Central China Normal University, Wuhan (China); Hillemanns, H.; Junique, A. [CERN, 1210 Geneva 23 (Switzerland); Kofarago, M. [CERN, 1210 Geneva 23 (Switzerland); University of Utrecht, Utrecht (Netherlands); Keil, M.; Kugathasan, T. [CERN, 1210 Geneva 23 (Switzerland); Kim, D. [Dongguk and Yonsei University, Seoul (Korea, Republic of); Kim, J. [Pusan National University, Busan (Korea, Republic of); Lattuca, A. [University of Torino, Torino (Italy); INFN (Italy); Marin Tobon, C.A. [CERN, 1210 Geneva 23 (Switzerland); Marras, D. [University of Cagliari, Cagliari (Italy); INFN (Italy); Mager, M.; Martinengo, P. [CERN, 1210 Geneva 23 (Switzerland); Mazza, G. [University of Torino, Torino (Italy); INFN (Italy); and others

    2015-06-11

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

  18. The New Readout System of the NA62 LKr Calorimeter

    CERN Document Server

    Ceccucci, A; Farthouat, P; Lamanna, G; Rouet, J; Ryjov, V; Venditti, S

    2015-01-01

    The NA62 experiment [1] at CERN SPS (Super Proton Synchrotron) accelerator aims at studying Kaon decays with high precision. The high resolution Liquid Krypton (LKr) calorimeter, built for the NA48 [2] experiment, is a crucial part of the photon-veto system; to cope with the demanding NA62 re- quirements,itsback-endelectron icshadtobecompletelyrenewed. The new readout system is based on the Calorimeter REAdout Module (CREAM) [3], a 6U VME board whose design and pro- duction was sub-contracted to CAEN [4], with CERN NA62 group continuously supervising the de velopment and production phase. The first version of the board was delivered by the manufacturer in March 2013 and, as of June 2014, the full board production is ongoing. In addition to describing the CREAM board, all aspects of the new LKr readout system, including its integration within the NA62 TDAQ scheme, will be treated.

  19. Optical pH Sensor Covering the Range from pH 0-14 Compatible with Mobile-Device Readout and Based on a Set of Rationally Designed Indicator Dyes.

    Science.gov (United States)

    Gotor, Raúl; Ashokkumar, Pichandi; Hecht, Mandy; Keil, Karin; Rurack, Knut

    2017-08-15

    In this work, a family of pH-responsive fluorescent probes has been designed in a rational manner with the aid of quantum chemistry tools, covering the entire pH range from 0-14. Relying on the boron-dipyrromethene (BODIPY) core, all the probes as well as selected reference dyes display very similar spectroscopic properties with ON-OFF fluorescence switching responses, facilitating optical readout in simple devices used for detection and analysis. Embedding of the probes and reference dyes into hydrogel spots on a plastic strip yielded a test strip that reversibly indicates pH with a considerably small uncertainty of ∼0.1 pH units. These strips are not only reusable but, combined with a 3D-printed case that can be attached to a smartphone, the USB port of which drives the integrated LED used for excitation, allows for autonomous operation in on-site or in-the-field applications; the developed Android application software ("app") further simplifies operation for unskilled users.

  20. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  1. A time projection chamber with microstrip read-out

    International Nuclear Information System (INIS)

    Bootsma, T.M.V.; Van den Brink, A.; De Haas, A.P.; Kamermans, R.; Kuijer, P.G.; De Laat, C.T.A.M.; Van Nieuwenhuizen, G.J.; Ostendorf, R.; Snellings, R.J.M.; Twenhoefel, C.J.W.; Peghaire, A.

    1994-01-01

    The design and testing of a novel detector for heavy-ion physics in the intermediate-energy regime is described. This detector consists of a large drift chamber with microstrip read-out in combination with thick plastic scintillators. With this system particle identification and energy determination with high spatial resolution and multiple hit capacity is achieved. ((orig.))

  2. Initial beam test results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Adolphsen, C.; Litke, A.; Schwarz, A.

    1986-01-01

    Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

  3. Architecture of a modular, multichannel readout system for dense electrochemical biosensor microarrays

    International Nuclear Information System (INIS)

    Ramfos, Ioannis; Birbas, Alexios; Blionas, Spyridon

    2015-01-01

    The architecture of a modular, multichannel readout system for dense electrochemical microarrays, targeting Lab-on-a-Chip applications, is presented. This approach promotes efficient component reusability through a hybrid multiplexing methodology, maintaining high levels of sampling performance and accuracy. Two readout modes are offered, which can be dynamically interchanged following signal profiling, to cater for both rapid signal transitions and weak current responses. Additionally, functional extensions to the described architecture are discussed, which provide the system with multi-biasing capabilities. A prototype integrated circuit of the proposed architecture’s analog core and a supporting board were implemented to verify the working principles. The system was evaluated using standard loads, as well as electrochemical sensor arrays. Through a range of operating conditions and loads, the prototype exhibited a highly linear response and accurately delivered the readout of input signals with fast transitions and wide dynamic ranges. (paper)

  4. A 12-bit SAR ADC integrated on a multichannel silicon drift detector readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Schembari, F., E-mail: filippo.schembari@polimi.it [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, via Golgi 40, 20133 Milano (Italy); INFN, Sezione di Milano, via Celoria 16, 20133 Milano (Italy); Bellotti, G.; Fiorini, C. [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, via Golgi 40, 20133 Milano (Italy); INFN, Sezione di Milano, via Celoria 16, 20133 Milano (Italy)

    2016-07-11

    A 12-bit analog-to-digital converter (ADC) addressed to Silicon-Drift Detectors (SDDs) multichannel readout ASICs for X- and gamma-ray applications is presented. Aiming at digitizing output multiplexed data from the upstream analog filters banks, the converter must ensure 11-bit accuracy and a sampling frequency of about 5 MS/s. The ADC architecture is the charge-redistribution (CR) successive-approximation register (SAR). A fully differential topology has also been chosen for better rejection of common-mode noise and disturbances. The internal DAC is made of binary-scaled capacitors, whose bottom plates are switched by the SAR logic to perform the binary search of the analog input value by means of the monotonic switching scheme. The A/D converter is integrated on SFERA, a multichannel ASIC fabricated in a standard CMOS 0.35 μm 3.3 V technology and it occupies an area of 0.42 mm{sup 2}. Simulated static performance shows monotonicity over the whole input–output characteristic. The description of the circuit topology and of inner blocks architectures together with the experimental characterization is here presented. - Highlights: • X- and γ-ray spectroscopy front-ends need to readout a high number of detectors. • Design efforts are increasingly oriented to compact and low-power ASICs. • A possible solution is the on-chip integration of the analog-to-digital converter. • A 12-bit CR successive-approximation-register ADC has been developed. • It is a suitable candidate as the digitizer to be integrated in multichannel ASICs.

  5. Waveshifting fiber readout of lanthanum halide scintillators

    International Nuclear Information System (INIS)

    Case, G.L.; Cherry, M.L.; Stacy, J.G.

    2006-01-01

    Newly developed high-light-yield inorganic scintillators coupled to waveshifting optical fibers provide the capability of efficient X-ray detection and millimeter scale position resolution suitable for high-energy cosmic ray instruments, hard X-ray/gamma ray astronomy telescopes and applications to national security. The CASTER design for NASA's proposed Black Hole Finder Probe mission, in particular, calls for a 6-8 m 2 hard X-ray coded aperture imaging telescope operating in the 20-600 keV energy band, putting significant constraints on cost and readout complexity. The development of new inorganic scintillator materials (e.g., cerium-doped LaBr 3 and LaCl 3 ) provides improved energy resolution and timing performance that is well suited to the requirements for national security and astrophysics applications. LaBr 3 or LaCl 3 detector arrays coupled with waveshifting fiber optic readout represent a significant advance in the performance capabilities of scintillator-based gamma cameras and provide the potential for a feasible approach to affordable, large area, extremely sensitive detectors. We describe some of the applications and present laboratory test results demonstrating the expected scintillator performance

  6. Evolution of the dual-readout calorimeter

    International Nuclear Information System (INIS)

    Penzo, Aldo

    2007-01-01

    Measuring the energy of hadronic jets with high precision is essential at present and future colliders, in particular at ILC. The 4th concept design is built upon calorimetry criteria that result in the DREAM prototype, read-out via two different types of longitudinal fibers, scintillator and quartz respectively, and therefore capable of determining for each shower the corresponding electromagnetic fraction, thus eliminating the strong effect of fluctuations in this fraction on the overall energy resolution. In this respect, 4th is orthogonal to the other three concepts, which rely on particle flow analysis (PFA). The DREAM test-beam results hold promises for excellent performances, coupled with relatively simple construction and moderate costs, making such a solution an interesting alternative to the PFA paradigm. The next foreseen steps are to extend the dual-readout principle to homogeneous calorimeters (with the potential of achieving even better performances) and to tackle another source of, fluctuation in hadronic showers, originating from binding energy losses in nuclear break-up (measuring neutrons of few MeV energy). (author)

  7. MKID digital readout tuning with deep learning

    Science.gov (United States)

    Dodkins, R.; Mahashabde, S.; O'Brien, K.; Thatte, N.; Fruitwala, N.; Walter, A. B.; Meeker, S. R.; Szypryt, P.; Mazin, B. A.

    2018-04-01

    Microwave Kinetic Inductance Detector (MKID) devices offer inherent spectral resolution, simultaneous read out of thousands of pixels, and photon-limited sensitivity at optical wavelengths. Before taking observations the readout power and frequency of each pixel must be individually tuned, and if the equilibrium state of the pixels change, then the readout must be retuned. This process has previously been performed through manual inspection, and typically takes one hour per 500 resonators (20 h for a ten-kilo-pixel array). We present an algorithm based on a deep convolution neural network (CNN) architecture to determine the optimal bias power for each resonator. The bias point classifications from this CNN model, and those from alternative automated methods, are compared to those from human decisions, and the accuracy of each method is assessed. On a test feed-line dataset, the CNN achieves an accuracy of 90% within 1 dB of the designated optimal value, which is equivalent accuracy to a randomly selected human operator, and superior to the highest scoring alternative automated method by 10%. On a full ten-kilopixel array, the CNN performs the characterization in a matter of minutes - paving the way for future mega-pixel MKID arrays.

  8. First results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

    1986-01-01

    A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

  9. The Readout Control Unit of the ALICE TPC

    CERN Document Server

    Lien, J A; Musa, L

    2004-01-01

    The ALICE Time Projection Chamber (TPC) is the main tracking detector of the central barrel of the ALICE (A Large Ion Collider) Experiment at the Large Hadron Collider (LHC), being constructed at CERN, Geneva. It is a 88 m$^{3}$ cylinder filled with gas and divided into two drift regions by the central electrode located at its axial center. The readout chambers of the TPC are multi-wire proportional chambers with cathode pad readout. About 570 000 pads are read-out by an electronics chain of amplification, digitalization and pre-processing. One of the challenges in designing the TPC for ALICE is the design of Front End Electronics (FEE) to cope with the data rates and the channel occupancy. The Readout Control Unit (RCU), which is presented in this work, is designed to control and monitor the Front End Electronics, and to collect and ship data to the High Level Trigger and the Data Acquisition System, via the Detector Data Link (DDL - optical fibre). The RCU must be capable of reading out up to 200 Mbytes/s f...

  10. Design and realization of the AMANDA software trigger for the TWA data readout system; Entwurf und Realisierung des AMANDA-Softwaretriggers fuer das TWR-Datenauslese-System

    Energy Technology Data Exchange (ETDEWEB)

    Messarius, Timo

    2006-07-15

    The thesis begins with a short introduction in the theory of astroparticle physics. Especially the processes, which lead to signal respectively background events in neutrino detectors, are discussed. Thereafter follows the descripotion of the basing detection principle and the detectors AMANDA and IceCube. The following chapter considers the two data-acquisition systems of the AMANDA detector and explains the motivation for the construction of a new data-acquisition system. The newly designed trigger system is then extensively treated. First a completely on software basing system is discussed, and then the implemented version is considered more detailedly. A procedure to detect and to mark events from atmospheric muons directly on trigger level is presented.

  11. Design and performance of SiPM-based readout of PbF 2 crystals for high-rate, precision timing applications

    International Nuclear Information System (INIS)

    Kaspar, J.; Fienberg, A.T.; Hertzog, D.W.; Huehn, M.A.; Kammel, P.; Khaw, K.S.; Peterson, D.A.; Smith, M.W.; Wechel, T.D. Van; Chapelain, A.; Gibbons, L.K.; Sweigart, D.A.; Ferrari, C.; Fioretti, A.; Gabbanini, C.; Venanzoni, G.; Iacovacci, M.; Mastroianni, S.; Giovanetti, K.; Gohn, W.

    2017-01-01

    We have developed a custom amplifier board coupled to a large-format 16-channel Hamamatsu silicon photomultiplier device for use as the light sensor for the electromagnetic calorimeters in the Muon g - 2 experiment at Fermilab. The calorimeter absorber is an array of lead-fluoride crystals, which produces short-duration Cherenkov light. The detector sits in the high magnetic field of the muon storage ring. The SiPMs selected, and their accompanying custom electronics, must preserve the short pulse shape, have high quantum efficiency, be non-magnetic, exhibit gain stability under varying rate conditions, and cover a fairly large fraction of the crystal exit surface area. We describe an optimized design that employs the new-generation of thru-silicon via devices. The performance is documented in a series of bench and beam tests.

  12. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  13. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

    2010-01-01

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  14. Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

    CERN Document Server

    Pacher, L.; Demaria, N.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Rotondo, F.; Wheadon, R.; Paternò, A.; Panati, S.; Loddo, F.; Licciulli, F.; Ciciriello, F.; Marzocca, C.; Gaioni, L.; Traversi, G.; Re, V.; De Canio, F.; Ratti, L.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.

    2018-01-01

    A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 μm × 50 μm pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irra- diation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends per- formance after irradiation. First sample chips have been also bump-bonded to 50 μm × 50 μm and sin...

  15. Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

    CERN Document Server

    Nesbo, Simon Voigt; Bonora, Matthias; Giubilato, Piero; Helstrup, Haavard; Hristozkov, Svetlomir; Aglieri Rinella, Gianluca; Röhrich, Dieter; Schambach, Joachim; Shahoyan, Ruben; Ullaland, Kjetil

    2017-01-01

    For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the up- graded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.

  16. BATS, the readout control of UA1

    Energy Technology Data Exchange (ETDEWEB)

    Botlo, M.; Dorenbosch, J.; Jimack, M.; Szoncso, F.; Taurok, A.; Walzel, G. (European Organization for Nuclear Research, Geneva (Switzerland))

    1991-04-15

    A steadily rising luminosity and different readout architectures for the various detector systems of UA1 required a new data flow control to minimize the dead time. BATS, a finite state machine conceived around two microprocessors in a single VME crate, improved flexibility and reliability. Compatibility with BATS streamlined all readout branches. BATS also proved to be a valuable asset in spotting readout problems and previously undetected data flow bottlenecks. (orig.).

  17. High-Tc dc-SQUID gradiometers in flip-chip configuration

    International Nuclear Information System (INIS)

    Peiselt, K; Schmidl, F; Linzen, S; Anton, A S; Huebner, U; Seidel, P

    2003-01-01

    We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-T c superconductor YBa 2 Cu 3 O 7-x (YBCO). For the flip-chip antenna, a 40 mm x 10 mm SrTiO 3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm x 10 mm SrTiO 3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm -1 Hz -1/2 in the white noise region and of 310 fT cm -1 Hz -1/2 at 1 Hz in the unshielded laboratory environment

  18. High-Tc dc-SQUID gradiometers in flip-chip configuration

    Science.gov (United States)

    Peiselt, K.; Schmidl, F.; Linzen, S.; Anton, A. S.; Hübner, U.; Seidel, P.

    2003-12-01

    We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-Tc superconductor YBa2Cu3O7-x (YBCO). For the flip-chip antenna, a 40 mm × 10 mm SrTiO3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm × 10 mm SrTiO3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm-1 Hz-1/2 in the white noise region and of 310 fT cm-1 Hz-1/2 at 1 Hz in the unshielded laboratory environment.

  19. Development of telescope readout system based on FELIX for testbeam experiments

    CERN Document Server

    Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

    2017-01-01

    The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

  20. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  1. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  2. Performance of a thermal imager employing a hybrid pyroelectric detector array with MOSFET readout

    International Nuclear Information System (INIS)

    Watton, R.; Mansi, M.V.

    1988-01-01

    A thermal imager employing a two-dimensional hybrid array of pyroelectric detectors with MOSFET readout has been built. The design and theoretical performance of the detector are discussed, and the results of performance measurements are presented. 8 references

  3. Data readout system for proportional chambers; Sistema schityvaniya informatsii s proportsional`nykh kamer

    Energy Technology Data Exchange (ETDEWEB)

    Zhuravlev, N I; Sidorov, V T

    1996-12-31

    Paper studies data readout system designed for data output from proportional chambers with up to 1000 channel total number. Short descriptions of the above mentioned units made according to CAMAC standard and their main characteristics are presented here. 2 figs.

  4. Embedded software design and programming of multiprocessor system-on-chip simulink and system C case studies

    CERN Document Server

    Popovici, Katalin; Jerraya, Ahmed A; Wolf, Marilyn

    2010-01-01

    Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access).Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tediou

  5. PADI ASIC for straw tube read-out

    Energy Technology Data Exchange (ETDEWEB)

    Pietraszko, Jerzy; Traeger, Michael; Fruehauf, Jochen; Schmidt, Christian [GSI, Darmstadt (Germany); Ciobanu, Mircea [ISS, Bucharest (Romania); Collaboration: CBM-Collaboration

    2016-07-01

    A prototype of the CBM MUCH straw tube detector consisting of six individual straws of 6mm inner diameter and 220 mm length filled with Ar/CO{sub 2} gas mixture has been tested at the COSY accelerator in Juelich. The straw tubes were connected to the FEET-PADI6-HDa PCB equipped with PADI-6 fast amplifier/discriminator ASIC. As a reference counter in this measurement the scCVD diamond detector has been used delivering excellent timing, time resolution below 100 ps (sigma), and very precise position information, below 50 μm. The demonstrated position resolution of about 160 μm of the straw tube read out with PADI-6 ASIC confirms the capability of the PADI chip and puts this development as a very attractive readout option for straw tubes and wire chambers.

  6. Multi-path interferometric Josephson directional amplifier for qubit readout

    Science.gov (United States)

    Abdo, Baleegh; Bronn, Nicholas T.; Jinka, Oblesh; Olivadese, Salvatore; Brink, Markus; Chow, Jerry M.

    2018-04-01

    We realize and characterize a quantum-limited, directional Josephson amplifier suitable for qubit readout. The device consists of two nondegenerate, three-wave-mixing amplifiers that are coupled together in an interferometric scheme, embedded in a printed circuit board. Nonreciprocity is generated by applying a phase gradient between the same-frequency pumps feeding the device, which plays the role of the magnetic field in a Faraday medium. Directional amplification and reflection-gain elimination are induced via wave interference between multiple paths in the system. We measure and discuss the main figures of merit of the device and show that the experimental results are in good agreement with theory. An improved version of this directional amplifier is expected to eliminate the need for bulky, off-chip isolation stages that generally separate quantum systems and preamplifiers in high-fidelity, quantum-nondemolition measurement setups.

  7. The CMS silicon strip tracker and its electronic readout

    International Nuclear Information System (INIS)

    Friedl, M.

    2001-05-01

    The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4 T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. The charge collection in silicon detectors was modeled, which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolution method of fast pulse shaping, electronic noise constraints and radiation effects. Moreover, extensive measurements on prototype components of the CMS Tracker and different versions of the APV chip in particular were performed. There was a significant contribution to the construction of several detector modules, characterized them in particle beam tests and quantified radiation induced effects on the APV chip and on silicon detectors. In addition, a prototype of the analog optical link and the analog performance of the back-end digitization unit were evaluated. The results are very encouraging, demonstrating the feasibility of the CMS Silicon Strip Tracker system and motivating progress towards the construction phase. (author)

  8. Multi-anode photon-multiplier readout electronics for the LHCb ring imaging Cherenkov detectors

    CERN Document Server

    Smale, N J

    2004-01-01

    A readout system for the Ring Imaging CHerenkov (RICH) detectors of the LHCb experiment has been developed. Two detector technologies for the measurement of Cherenkov photons are considered, the Multi-Anode Photo-Multiplier Tube (MAPMT) and the Hybrid Photon Detector (HPD), both of which meet the RICH requirements. The properties of the MAPMT are evaluated using a controlled single-photon source; a pixel-to-pixel gain variation of ~3 and a typical signal to noise of ~20 is measured. The relative tube efficiency is found to be reduced by ~26 % due to the detailed focusing structure of the MAPMT device. A radiation hard application-specific integrated circuit (ASIC) chip, the Beetle1.2MA0, has been developed to capture and store signals from a pair of MAPMTs. The Beetle1.2MA0 is built on the architecture of the Beetle family that was designed for silicon strip detectors, the difference being a modified front-end amplifier. The 128 input-channels of the Beetle1.2MA0 have a charge-sensitive pre-amplifier followed...

  9. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  10. Chip cleaning and regeneration for electrochemical sensor arrays

    Energy Technology Data Exchange (ETDEWEB)

    Bhalla, Vijayender [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Carrara, Sandro, E-mail: sandro.carrara@epfl.c [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Stagni, Claudio [Department DEIS, University of Bologna, viale Risorgimento 2, 40136 Bologna (Italy); Samori, Bruno [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy)

    2010-04-02

    Sensing systems based on electrochemical detection have generated great interest because electronic readout may replace conventional optical readout in microarray. Moreover, they offer the possibility to avoid labelling for target molecules. A typical electrochemical array consists of many sensing sites. An ideal micro-fabricated sensor-chip should have the same measured values for all the equivalent sensing sites (or spots). To achieve high reliability in electrochemical measurements, high quality in functionalization of the electrodes surface is essential. Molecular probes are often immobilized by using alkanethiols onto gold electrodes. Applying effective cleaning methods on the chip is a fundamental requirement for the formation of densely-packed and stable self-assembly monolayers. However, the available well-known techniques for chip cleaning may not be so reliable. Furthermore, it could be necessary to recycle the chip for reuse. Also in this case, an effective recycling technique is required to re-obtain well cleaned sensing surfaces on the chip. This paper presents experimental results on the efficacy and efficiency of the available techniques for initial cleaning and further recycling of micro-fabricated chips. Piranha, plasma, reductive and oxidative cleaning methods were applied and the obtained results were critically compared. Some interesting results were attained by using commonly considered cleaning methodologies. This study outlines oxidative electrochemical cleaning and recycling as the more efficient cleaning procedure for electrochemical based sensor arrays.

  11. A novel readout concept for multianode photomultiplier tubes with pad matrix anode layout

    Energy Technology Data Exchange (ETDEWEB)

    Popov, Vladimir [Thomas Jefferson National Accelerator Facility, Newport News, VA 23606 (United States)]. E-mail: Popov@jlab.org; Majewski, Stan [Thomas Jefferson National Accelerator Facility, Newport News, VA 23606 (United States); Welch, Benjamin L. [Thomas Jefferson National Accelerator Facility, Newport News, VA 23606 (United States)

    2006-11-01

    We have developed a new analog readout concept for multianode photomultiplier tubes with a pad matrix anode layout. This new readout technique is the result of a modification of a technique previously developed at the Detector Group of Jefferson Lab (V. Popov, US patent No: 6,747,263 B1) [V. Popov, S. Majewski, A.G. Weisenberger, Readout Electronics for Multianode Photomultiplier Tubes with Pad Matrix Anode Layout, Thomas Jefferson National Accelerator Facility, IEEE 2003 Medical Imaging Conference Record, November 2003]. The new analog readout circuit provides the same analog conversion of matrix 2-D output into X and Y projective output with a significant reduction of analog outputs. The old readout network consists of resistors' matrix and current collecting amplifiers, and it provides decoupling of each anode output into two directions (one to X and one to Y coordinates), but a decoupling function that is carried out independent of photomultiplier tube gains nonuniformity. A newly developed readout network (US patent pending) also consists of resistors' matrix and current collecting amplifiers, but the new matrix includes an additional dumping resistor that provides an excess current from anode pad grounding. As a result, we subtract an extra current of high-gain pads in order to move the pads gain to an absolute minimum value for a given photomultiplier tube. This gain equalization procedure reduces image distortion related to gain nonuniformity. The new readout technique was used in several new radiation imaging detectors designed in the Detector Group of Jefferson Lab. It shows a visible readout uniformity and linearity improvement. The test results of an initial evaluation of this readout that is applied for data readout of four H8500 Hamamtsu PSPMT are presented.

  12. Evolution of the dual-readout calorimeter

    Indian Academy of Sciences (India)

    ... a calorimeter system of a relatively simple construction and moderate costs, however with excellent properties, built upon experience gained with the extensively beam-tested DREAM (Dual REAdout. Module) prototype. The main idea of multiple readout calorimetry is to indepen- dently measure for each hadronic shower ...

  13. First implementation of the MEPHISTO binary readout architecture for strip detectors

    International Nuclear Information System (INIS)

    Fischer, P.

    2001-01-01

    Today's front-end readout chips for multi-channel silicon strip detectors use pipeline-like structures for temporary storage of hit information until arrival of a trigger signal. This approach leads to large-area chips when long trigger latencies are necessary. The MEPHISTO architecture uses a different concept. Hit strips are identified in real time and only the relevant binary hit information is stored in FIFOs. For the typical occupancies in LHC detectors of ∼1 hit per clock cycle this architecture requires less than half the chip area of a typical binary pipeline. This reduces the system cost considerably. At a lower data rate, operation with very long trigger latencies or even without any trigger is possible due to the real-time data sparsification. The Mephisto II architecture is presented and the expected performance is discussed

  14. Design and Implementation of 8051 Single-Chip Microcontroller for Stationary 1.0 kW PEM Fuel Cell System

    Directory of Open Access Journals (Sweden)

    Pei-Hsing Huang

    2014-01-01

    Full Text Available Proton exchange membrane fuel cells (PEMFCs have attracted significant interest as a potential green energy source. However, if the performance of such systems is to be enhanced, appropriate control strategies must be applied. Accordingly, the present study proposes a sophisticated control system for a 1.0 kW PEMFC system comprising a fuel cell stack, an auxiliary power supply, a DC-DC buck converter, and a DC-AC inverter. The control system is implemented using an 8051 single-chip microcontroller and is designed to optimize the system performance and safety in both the startup phase and the long-term operation phase. The major features of the proposed control system are described and the circuit diagrams required for its implementation introduced. In addition, the touch-sensitive, intuitive human-machine interface is introduced and typical screens are presented. Finally, the electrical characteristics of the PEMFC system are briefly examined. Overall, the results confirm that the single-chip microcontroller presented in this study has significant potential for commercialization in the near future.

  15. Common Readout System in ALICE

    CERN Document Server

    Jubin, Mitra

    2016-01-01

    The ALICE experiment at the CERN Large Hadron Collider is going for a major physics upgrade in 2018. This upgrade is necessary for getting high statistics and high precision measurement for probing into rare physics channels needed to understand the dynamics of the condensed phase of QCD. The high interaction rate and the large event size in the upgraded detectors will result in an experimental data flow traffic of about 1 TB/s from the detectors to the on-line computing system. A dedicated Common Readout Unit (CRU) is proposed for data concentration, multiplexing, and trigger distribution. CRU, as common interface unit, handles timing, data and control signals between on-detector systems and online-offline computing system. An overview of the CRU architecture is presented in this manuscript.

  16. Drift chamber data readout system

    International Nuclear Information System (INIS)

    Basiladze, S.G.; Lokhonyai, L.

    1980-01-01

    An electronic system for processing drift chamber signals is described. The system consists of 4-channel fast amplifier-discriminators of low threshold, 16-channel time-expanders transforming 0.5 μs time intervals to 10 μs and a 9-bit time-to-digital converter (TDC) recording up to 16 expanded time intervals. If the average track multiplicity is small, TDC is capable to process signals from 4 time-expanders (i.e., 64 drift gaps). In order to record multiple tracks per drift gap discriminator outputs can be connected to a number of time-expander channels. The fast clear input enables the system to be cleared within 0.5 μs. Efficient readout from TDC is facilated by reading only those channels which contain non-zero data (9 bits - drift time; 6 bits - wire number)

  17. Common Readout System in ALICE

    CERN Document Server

    Jubin, Mitra

    2017-01-01

    The ALICE experiment at the CERN Large Hadron Collider is going for a major physics upgrade in 2018. This upgrade is necessary for getting high statistics and high precision measurement for probing into rare physics channels needed to understand the dynamics of the condensed phase of QCD. The high interaction rate and the large event size in the upgraded detectors will result in an experimental data flow traffic of about 1 TB/s from the detectors to the on-line computing system. A dedicated Common Readout Unit (CRU) is proposed for data concentration, multiplexing, and trigger distribution. CRU, as common interface unit, handles timing, data and control signals between on-detector systems and online-offline computing system. An overview of the CRU architecture is presented in this manuscript.

  18. Evaluation of Fermi read-out of the Atlas Tilecal prototype

    International Nuclear Information System (INIS)

    Ajaltouni, Z.; Alifanov, A.

    1998-01-01

    Prototypes of the FERMI system have been used to read out a prototype of the ATLAS hadron calorimeter in a beam test at the CERN SPS. The FERMI read-out system, using a compressor and a sampling ADC, is compared to a standard charge integrating read-out by measuring the energy resolution of the calorimeter separately with the two systems on the same events. Signal processing techniques have been designed to optimize the treatment of FERMI data. The resulting energy resolution is better than the one obtained with the standard read-out. (orig.)

  19. LHCb : Clock and timing distribution in the LHCb upgraded detector and readout system

    CERN Multimedia

    Alessio, Federico; Barros Marin, M; Cachemiche, JP; Hachon, F; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment is upgrading part of its detector and the entire readout system towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity and increase its trigger efficiency. In this paper, the new timing, trigger and control distribution system for such an upgrade is reviewed with particular attention given to the distribution of the clock and timing information across the entire readout system, up to the FE and the on-detector electronics. Current ideas are here presented in terms of reliability, jitter, complexity and implementation.

  20. Clock and timing distribution in the LHCb upgraded detector and readout system

    CERN Document Server

    Alessio, F; Barros Marin, M; Cachemiche, JP; Hachon, F; Jacobsson, R; Wyllie, K

    2015-01-01

    The LHCb experiment is upgrading part of its detector and the entire readout system towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity and increase its trigger efficiency. In this paper, the new timing, trigger and control distribution system for such an upgrade is reviewed with particular attention given to the distribution of the clock and timing information across the entire readout system, up to the FE and the on-detector electronics. Current ideas are here presented in terms of reliability, jitter, complexity and implementation.