WorldWideScience

Sample records for readout chip designed

  1. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  2. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  3. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  4. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Science.gov (United States)

    Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

    2017-09-01

    Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  5. Event loss rates and readout chips

    CERN Document Server

    Schmelling, M

    1998-01-01

    98-57 The LHCb experiment aims at a deadtimeless readout of B­events at a primary bunch crossing rate of 40 MHz. In order to achieve this goal, information from all events must be stored in a pipeline with latency matched to the time needed for the Level 0 trigger decision. Accepted events, which constitute only a small fraction of the total sample, are stored in a fifo of a certain depth and read out with a fixed clock rate. The fifo, also referred to as multi­event or derandomizing buffer, is needed in order to even out statistical fluctuations in the trigger rate. Apart from the length of the pipeline, which determines the maximum latency of the chip, the crucial parameter characterizing a readout chip is the fraction of triggers lost due to limitations of the chip's architecture. This note describes how the different design parameters and operation conditions determine the chip's performance.

  6. Digital column readout architectures for hybrid pixel detector readout chips

    CERN Document Server

    Poikela, T; Westerlund, T; Buytaert, J; Campbell, M; De Gaspari, M; Llopart, X; Wyllie, K; Gromov, V; Kluit, R; van Beuzekom, M; Zappon, F; Zivkovic, V; Brezina, C; Desch, K; Fu, Y; Kruth, A

    2014-01-01

    In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 µm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

  7. Towards third generation pixel readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@lbl.gov; Mekkaoui, A.; Ganani, D.

    2013-12-11

    We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130 nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC design generic so that different experiments can configure it to meet significantly different requirements, without the need for everybody to develop their own ASIC from the ground up. In terms of target technology, a demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in 65 nm CMOS and irradiated with protons in December 2011 and May 2012.

  8. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  9. Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

    Science.gov (United States)

    Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

    2014-12-01

    The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

  10. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  11. LSST camera readout chip ASPIC: test tools

    Science.gov (United States)

    Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

    2012-02-01

    The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

  12. The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

    CERN Document Server

    Marconi, S; Placidi, Pisana; Christiansen, Jorgen; Hemperek, Tomasz

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

  13. Beetle A radiation hard readout chip for the LHCb experiment

    CERN Document Server

    Agari, M; Bauer, C; Baumeister, D; Van Beuzekom, M G; Feuerstack-Raible, M; Harnew, N; Hofmann, W; Jans, E; Klous, S; Knöpfle, K T; Löchner, S; Schmelling, M; Sexauer, E; Smale, N J; Trunk, U; Verkooijen, H

    2004-01-01

    A new radiation hard pipelined readout chip is being developed for the LHCb-experiment. Appropriate design measures have been taken to ensure the radiation hardness against total ionising dose effects in excess of 45 Mrad, as well as radiation effects induced by single particles.

  14. Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, Shebli; Château, Frédéric; Le Provost, Hervé; Louis, Frédéric [CEA/Irfu/SEDI Gif-sur-Yvette (France); Manolopoulos, Konstantinos [Physics Department, University of Athens (Greece); Moudden, Yassir, E-mail: yassir.moudden@cea.fr [CEA/Irfu/SEDI Gif-sur-Yvette (France); Vallage, Bertrand [CEA/Irfu/SPP Gif-sur-Yvette (France); Zonca, Eric [CEA/Irfu/SEDI Gif-sur-Yvette (France)

    2014-01-21

    A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described.

  15. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  16. Architectural modeling of pixel readout chips Velopix and Timepix3

    NARCIS (Netherlands)

    Poikela, T.; Plosila, J.; Westerlund, T.; Buytaert, J.; Campbell, M.; Llopart, X.; Plackett, R.; Wyllie, K.; van Beuzekom, M.; Gromov, V.; Kluit, R.; Zappon, F.; Zivkovic, V.; Brezina, C.; Desch, K.; Fang, X.; Kruth, A.

    2012-01-01

    We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout.

  17. Fermilab silicon strip readout chip for BTev

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Raymond; Hoff, Jim; Mekkaoui, Abderrezak; Manghisoni, Massimo; Re, Valerio; Angeleri, Valentina; Manfredi, Pier Francesco; Ratti, Lodovico; Speziali, Valeria; /Fermilab /Bergamo U. /INFN, Pavia /Pavia U.

    2005-05-01

    A chip has been developed for reading out the silicon strip detectors in the new BTeV colliding beam experiment at Fermilab. The chip has been designed in a 0.25 {micro}m CMOS technology for high radiation tolerance. Numerous programmable features have been added to the chip, such as setup for operation at different beam crossing intervals. A full size chip has been fabricated and successfully tested. The design philosophy, circuit features, and test results are presented in this paper.

  18. KLauS – A charge readout and fast discrimination chip for silicon photomultipliers

    CERN Document Server

    Dorn, M; Shen, W; Sidlauskas, G; Schultz-Coulon, H.C

    2012-01-01

    photomultipliers. The chip has been designed for the application in the analog hadronic calorimeter developed by the CALICE collaboration for the next linear collider experiment . To address the severe power constraints introduced by the highly granular design of the calorimeter, the chip has been designed for low power consumption while maintaining the high dynamic range and timing precision required by the experiment. In addition, a power gating scheme has been implemented to further decrease the average power consumption. For a duty cycle of 1% a value of 25µW per channel is achieved without affecting the readout capabilities of the chip. The chip has been designed in the 0.35µm SiGe technology and provides a low power readout channel for SiPMs with low gain for the input stage of the existing readout chip SPIROC. The analog channel of KLauS will be implemented in a future version of the SPIROC chip.

  19. FPIX2, the BTeV pixel readout chip

    CERN Document Server

    Christian, D C; Chiodini, G; Hoff, J; Kwan, S; Mekkaoui, A; Yarema, R; 10.1016/j.nima.2005.04.046

    2005-01-01

    A radiation tolerant pixel readout chip, FPIX2, has been developed at Fermilab for use by BTeV. Some of the requirements of the BTeV pixel readout chip are reviewed and contrasted with requirements for similar devices in LHC experiments. A description of the FPIX2 is given, and results of initial tests of its performance are presented, as is a summary of measurements planned for the coming year.

  20. The CMS Pixel Readout Chip for the Phase 1 Upgrade

    Science.gov (United States)

    Hits, D.; Starodumov, A.

    2015-05-01

    The present CMS pixel Read Out Chip (ROC) was designed for operation at a bunch spacing of 25 ns and to be efficient up to the nominal instantaneous luminosity of 1034 cm-2 s-1. Based on the excellent LHC performance to date and the upgrade plans for the accelerators, it is anticipated that the instantaneous luminosity could reach 2×1034 cm-2 s-1 before the Long Shutdown 2 (LS2) in 2018, and well above this by the LS3 in 2022. That is why a new ROC has been designed and why a completely new pixel detector will be built with a planned installation in CMS during an extended winter shutdown in 2016/17. The ROC for the upgraded pixel detector is an evolution of the present architecture. It will be manufactured in the same 250 nm CMOS process. The core of the architecture is maintained, with enhancement in performance in three main areas: readout protocol, reduced data loss and enhanced analog performance. The main features of the new CMS pixel ROC are presented together with measured performance of the chip.

  1. Readout of TPC Tracking Chambers with GEMs and Pixel Chip

    Energy Technology Data Exchange (ETDEWEB)

    Kadyk, John; Kim, T.; Freytsis, M.; Button-Shafer, J.; Kadyk, J.; Vahsen, S.E.; Wenzel, W.A.

    2007-12-21

    Two layers of GEMs and the ATLAS Pixel Chip, FEI3, have been combined and tested as a prototype for Time Projection Chamber (TPC) readout at the International Linear Collider (ILC). The double-layer GEM system amplifies charge with gain sufficient to detect all track ionization. The suitability of three gas mixtures for this application was investigated, and gain measurements are presented. A large sample of cosmic ray tracks was reconstructed in 3D by using the simultaneous timing and 2D spatial information from the pixel chip. The chip provides pixel charge measurement as well as timing. These results demonstrate that a double GEM and pixel combination, with a suitably modified pixel ASIC, could meet the stringent readout requirements of the ILC.

  2. Pixel readout chip for the ATLAS experiment

    CERN Document Server

    Ackers, M; Blanquart, L; Bonzom, V; Comes, G; Fischer, P; Keil, M; Kühl, T; Meuser, S; Delpierre, P A; Treis, J; Raith, B A; Wermes, N

    1999-01-01

    Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4*10/sup 8/ individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector. Consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported. (6 refs).

  3. Development and characterisation of a radiation hard readout chip for the LHCb experiment

    CERN Document Server

    Baumeister, Daniel; Stachel, Johanna

    2003-01-01

    Within this doctoral thesis parts of the radiation hard readout chip Beetle have been developed and characterised, before and after irradiation. The design work included the analogue memory with the corresponding readout amplifier as well as components of the digital control circuitry. An interface compatible with the I2C-standard and the control logic for event readout have been implemented. A scheme has been developed which ensures the robustness of the Beetle chip against Single-Event Upset (SEU). This includes the consistent use of triple-redundant memory devices together with a self-triggered correction in parts of the circuit. The Beetle ASIC is a 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier and a CR-RC pulse shaper. It features an equivalent noise charge of ENC = 497 e− +48.3 e−/pF·Cin. The analogue memory is a switched capacitor array, which provides a latency of max. 4 µs. The 128 channels are transmitted off chip in 9...

  4. Towards a new generation of pixel detector readout chips

    CERN Document Server

    Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

    2016-01-01

    The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

  5. TID-dependent current measurements of IBL readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Dette, Karola [TU Dortmund, Experimentelle Physik IV (Germany); CERN (Switzerland); Collaboration: ATLAS Pixel-Collaboration

    2016-07-01

    The ATLAS detector consists of several subsystems with a hybrid pixel detector as the innermost component of the tracking system. The pixel detector has been composed of three layers of silicon sensor assemblies during the first data taking run of the LHC and has been upgraded with a new 4th layer, the so-called Insertable B-Layer (IBL), in summer 2014. Each silicon sensor of the IBL is connected to a Front End readout chip (FE-I4) via bump bonds. During the first year of data taking an increase of the LV current produced by the readout chips was observed. This increase could be traced back to radiation damage inside the silicon. The dependence of the current on the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations and will be presented in this talk.

  6. The CMS pixel readout chip for the Phase 1 Upgrade

    CERN Document Server

    Hits, Dmitry

    2015-01-01

    The present CMS pixel Read Out Chip (ROC) was designed for operation at a bunch spacing of 25\\,ns and to be efficient up to the nominal instantaneous luminosity of 10$^{34} \\rm cm^{-2} \\rm s^{-1}$. Based on the excellent LHC performance to date and the upgrade plans for the accelerators, it is anticipated that the instantaneous luminosity could reach $2\\times10^{34} \\rm cm^{-2} \\rm s^{-1}$ before the Long Shutdown 2 (LS2) in 2018, and well above this by the LS3 in 2022. That is why a new ROC has been designed and why a completely new pixel detector will be built with a planned installation in CMS during an extended winter shutdown in 2016/17. The ROC for the upgraded pixel detector is an evolution of the present architecture. It will be manufactured in the same 250\\,nm CMOS process. The core of the architecture is maintained, with enhancement in performance in three main areas: readout protocol, reduced data loss and enhanced analog performance. The main features of the new CMS pixel ROC are presented togeth...

  7. Thin film magnetostrictive sensor with on-chip readout

    Science.gov (United States)

    Lu, Yong

    We report the first successful integration of magnetostrictive Metglas2605S2 (Fesb{78}Sisb9Bsb{13}) thin film sensor system on silicon with high resolution capacitive readout. A deposition process for Metglas thin film has been developed to allow easy control of thin film composition. An amorphous microstructure has been achieved over a wide temperature range, and in-situ magnetic domain alignment can be accomplished at room temperature as the film is deposited. The thin film has been characterized by Inductively Coupled Plasma (ICP) analysis for composition, X-Ray Diffraction (XRD) spectrum for microstructure, magnetization measurement for domain alignment and capacitive measurement for magnetostriction. The thin film is suitable for any magnetostrictive sensor applications, in particular, for IC compatible microsensors and microactuators. We have demonstrated the subsequent process integration with IC fabrication technology. Here, the Metglas thin film has been successfully incorporated to micromechanical structures using surface micromachining with appropriate choice of sacrificial layer and low stress mechanical layers. In addition, we present the development of a high resolution capacitive readout circuit co-integrated with the sensor. The readout circuit is based on a floating gate MOSFET configuration, requiring just a single transistor and operated at DC or low frequencies. Using the prototype developed in-house, we have successfully demonstrated a resolution capability of 10sp{-17} F, this translates to a few A in terms of cantilever beam deflection of the sensor. The floating gate readout technique is readily applicable to any capacitive sensors with a need for on-chip readout. It is also an ideal in-situ test structure for on IC chip process characterization and parameter extraction.

  8. Radiation tolerance of prototype BTeV pixel detector readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Gabriele Chiodini et al.

    2002-07-12

    High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pixel detectors (arrays of silicon diodes bump bonded to arrays of front-end electronic cells) is the state of the art technology able to meet these challenges. We report on irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. Prototype pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 micron CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 87 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been extensively measured.

  9. CMOS biosensor system for on-chip cell culture with read-out circuitry and microfluidic packaging.

    Science.gov (United States)

    Welch, David; Christen, Jennifer Blain

    2012-01-01

    A 1.5 mm × 3 mm CMOS chip with sensors for monitoring on-chip cell cultures has been designed. The chip is designed in a 0.5 µm CMOS process which has 3 metal layers and 2 poly layers and is a 5 volt process. The chip contains ion sensitive field effect transistors (ISFETs), as well as ISFETs with read-out circuitry, for monitoring the pH of solutions placed on top of the chip. Interdigitated electrode structures (IDESs) are made using the top metal of the process to be used for sensing cellular attachment and proliferation via impendence. IDES read-out circuits and IDES test structures are included. The chip also contains test amplifiers, bandgap reference test structures, and connections for post-processing. We designed the chip to accommodate packaging into an environment where it will be directly exposed to a cell culture environment. Specifically we designed the chip to have the incorporated sensors near the center of the chip allowing for connections made around the edge of the chip to be sealed off using an epoxy or similar material to prevent shorting. Preliminary electrical characterization results for our amplifier indicate a gain of 48 dB, a bandwidth of 1.65 kHz, and a common mode rejection ratio (CMRR) of 72 dB. We also present a packaging technique using a flexible pcb substrate.

  10. XA readout chip characteristics and CdZnTe spectral measurements

    Energy Technology Data Exchange (ETDEWEB)

    Barbier, L.M.; Birsa, F.; Odom, J. [NASA/Goddard Space Flight Center, Greenbelt, MD (United States)] [and others

    1999-02-01

    The authors report on the performance of a CdZnTe (CZT) array readout by an XA (X-ray imaging chip produced at the AMS foundry) application specific readout chip (ASIC). The array was designed and fabricated at NASA/Goddard Space Flight Center (GSFC) as a prototype for the Burst Arc-Second Imaging and Spectroscopy gamma-ray instrument. The XA ASIC was obtained from Integrated Detector and Electronics (IDE), in Norway. Performance characteristics and spectral data for {sup 241}Am are presented both at room temperature and at {minus}20 C. The measured noise ({sigma}) was 2.5 keV at 60 keV at room temperature. This paper represents a progress report on work with the XA ASIC and CZT detectors. Work is continuing and in particular, larger arrays are planned for future NASA missions.

  11. Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

    Energy Technology Data Exchange (ETDEWEB)

    Peric, I.

    2004-08-01

    Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

  12. Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

    Science.gov (United States)

    Marconi, S.; Orfanelli, S.; Karagounis, M.; Hemperek, T.; Christiansen, J.; Placidi, P.

    2017-02-01

    A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

  13. The GOTTHARD charge integrating readout detector: design and characterization

    Science.gov (United States)

    Mozzanica, A.; Bergamaschi, A.; Dinapoli, R.; Graafsma, H.; Greiffenberg, D.; Henrich, B.; Johnson, I.; Lohmann, M.; Valeria, R.; Schmitt, B.; Xintian, S.

    2012-01-01

    A charge integrating readout ASIC (Application Specific Integrated Circuit) for silicon strip sensors has been developed at PSI in collaboration with DESY. The goal of the project is to provide a charge integrating readout system able to cope with the pulsed beam of XFEL machines and at the same time to retain the high dynamic range and single photon resolution performances typical for photon counting systems. The ASIC, designed in IBM 130 nm CMOS technology, takes advantage of its three gain stages with automatic stage selection to achieve a dynamic range of 10000 12 keV photons and a noise better than 300 e.n.c.. The 4 analog outputs of the ASIC are optimized for speed, allowing frame rates higher than 1 MHz, without compromises on linearity and noise performances. This work presents the design features of the ASIC, and reports the characterization results of the chip itself.

  14. Characterizing the Noise Performance of the KPiX ASIC Readout Chip

    Energy Technology Data Exchange (ETDEWEB)

    Carman, Jerome Kyrias; /Cabrillo Coll. /SLAC

    2007-11-07

    AKPiX is a prototype front-end readout chip designed for the Silicon Detector Design Concept for the International Linear Collider (ILC). It is targeted at readout of the outer tracker and the silicon-tungsten calorimeter and is under consideration for the hadronic calorimeter and muon systems. This chip takes advantage of the ILC timing structure by implementing pulsed-power operation to reduce power and cooling requirements and buffered readout to minimize material. Successful implementation of this chip requires optimal noise performance, of which there are two measures. The first is the noise on the output signal, previously measured at 1500e{sup -}, which is much larger than the anticipated 500e{sup -}. The other is the noise on the trigger logic branch, which determines where thresholds must be set in order to eliminate noise hits, thus defining the smallest signals to which the chip can be sensitive. A test procedure has been developed to measure the noise in the trigger branch by scanning across the pedestal in trigger threshold and taking self-triggered data to measure the accept rate at each threshold. This technique measures the integral of the pedestal shape. Shifts in the pedestal mean from injection of known calibration charges are used to normalize the distribution in units of charge. The shape of the pedestal is fit well by a Gaussian, the width of which is determined to be 2480e{sup -}, far in excess of the expected noise. The variation of the noise as a function of several key parameters was studied, but no significant source has been clearly isolated. However, several problems have been identified that are being addressed or are under further investigation. Meanwhile, the techniques developed here will be critical in ultimately verifying the performance goals of the KPiX chip.

  15. Readout electronic for multichannel detectors

    CERN Document Server

    Kulibaba, V I; Naumov, S V

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

  16. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

    CERN Multimedia

    Saba, A

    2006-01-01

    2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

  17. LHCb - SALT, a dedicated readout chip for strip detectors in the LHCb Upgrade experiment

    CERN Multimedia

    Swientek, Krzysztof Piotr

    2015-01-01

    Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout 128-channel ASIC called SALT. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analogue front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. A prototype of first 8-channel version of SALT chip, comprising all important functionalities, was submitted. Its design and possibly first tests results will be presented.

  18. Design and Realisation of Integrated Circuits for the Readout of Pixel Sensors in High Energy Physics and Biomedical Imaging

    CERN Document Server

    Peric, Ivan

    2004-01-01

    Several application specific microchips (ASICs) for the readout of pixel detectors have been designed, tested and described in this thesis. The first chapter gives the detailed description of the pixel-readout chip for the ATLAS pixel detector (FEI). The chip is now in operation as the innermost electronic component of the ATLAS detector. The chip for steering of DEPFET matrix (SWITCHER) is described in the second chapter. The chip is implemented in a high-voltage CMOS technology, it generates fast high voltage signals. Finally, a novel pixel readout chip for a hybrid x-ray pixel detector based on direct conversion is introduced. The chip (CIX) has joint photon counting and integrating capability.

  19. Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

    CERN Document Server

    AUTHOR|(SzGeCERN)394193

    2016-01-01

    A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

  20. Analyses of test beam data for the ATLAS upgrade readout chip (ABC130)

    Energy Technology Data Exchange (ETDEWEB)

    Peschke, Richard [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

    2015-07-01

    As part of the ATLAS phase II upgrade it is planned to replace the current tracker with an all silicon tracker. The outer part of the new tracker will consist of silicon strip detectors. For the readout of the strip detector a new Analog to Binary Converter chip (ABC130) was designed. The chip is processed in the 130 nm technology. In laboratory measurements the preamplifier of the new ABC130 showed a significant lower gain than expected. From the measurements in the laboratory it was not possible to distinguish if the malfunction is in the preamplifier or in the test circuit. Therefore an unbiased test was mandatory. Among other measurements, one was a test beam campaign at the Stanford Linear Accelerator Collider (SLAC). The result of measurement is shown in the presentation.

  1. IRRADIATION MEASUREMENTS ON THE 0.25 micro m CMOS PIXEL READOUT TEST CHIP BY A 14 MEV NEUTRON FACILITY

    CERN Document Server

    Barbera, R; CERN. Geneva; Palmeri, A; Pappalardo, G S; Riggi, F; Di Liberto, S; Meddi, F; Sestito, S; Loi, D; Angelone, M; Badalà, A; Pillon, M

    2000-01-01

    ALICE-ITS-2000-24   Abstract   A test facility station with 14 MeV neutrons was arranged at the FNG-ENEA Laboratory in Frascati (Italy) for the characterization with respect to radiation tolerance of the prototype pixel readout chips in 0.25 m m IBM technology done in edgeless design. This facility could allow to test both the readout chips and the pilot chips for the pixel readout system. In fact, both ASICs will have to survive at the same radiation level foreseen for the innermost layer (r = 4 cm) of the Inner Tracker System (ITS) in the LHC-ALICE experiment. Two test chips were exposed to an overall flux of 1.3 x 1012 14 MeV neutrons/cm2, which is larger than the expected neutron flux in ALICE during 10 years data taking. No variation in the parameters defining the chip functionality (analog and digital currents, linearity, shapes of the signal, efficiency) was observed.

  2. SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

    Science.gov (United States)

    Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

    2016-02-01

    The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

  3. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  4. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Energy Technology Data Exchange (ETDEWEB)

    Claus, R., E-mail: claus@slac.stanford.edu

    2016-07-11

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  5. A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Irmler, C., E-mail: christian.irmler@oeaw.ac.at [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Bergauer, T.; Frankenberger, A.; Friedl, M.; Gfall, I. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Higuchi, T. [University of Tokyo, Kavli Institute for Physics and Mathematics of the Universe, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8583 (Japan); Ishikawa, A. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Joo, C. [Seoul National University, High Energy Physics Laboratory, 25-107 Shinlim-dong, Kwanak-gu, Seoul 151-742 (Korea, Republic of); Kah, D.H.; Kang, K.H. [Kyungpook National University, Department of Physics, 1370 Sankyuk Dong, Buk Gu, Daegu 702-701 (Korea, Republic of); Rao, K.K. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Kato, E. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Mohanty, G.B. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Negishi, K. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Onuki, Y.; Shimizu, N. [University of Tokyo, Department of Physics, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 (Japan); Tsuboyama, T. [KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Valentan, M. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria)

    2013-12-21

    B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure. In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor. This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO{sub 2} system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder. We present the concept and the assembly procedure of the Origami chip-on-sensor modules.

  6. Development, Optimisation and Characterisation of a Radiation Hard Mixed-Signal Readout Chip for LHCb

    CERN Document Server

    Löchner, S

    2006-01-01

    The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4 us. The 128 analogue channels are multiplexed and transmitted off chip in 900 ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU...

  7. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

  8. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    ATLAS CSC Collaboration; The ATLAS collaboration

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

  9. The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2015-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

  10. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)664042

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

  11. The FE-I4 Pixel Readout Chip and the IBL Module

    CERN Document Server

    Barbero, Marlon; Backhaus, Malte; Fang, Xiaochao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Krueger, Hans; Kruth, Andre; Wermes, Norbert; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Sasha; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; Garcia-Sciveres, Maurice; Jensen, Frank; Lu, Yunpeng; Mekkaoui, Abderrezak; Gromov, Vladimir; Kluit, Ruud; Schipper, Jan David; Zivkovic, Vladimir; Grosse-Knetter, Joern; Weingarten; Kocian, Martin

    2011-01-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the “Insertable B-Layer” project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  12. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  13. FPHX: A New Silicon Strip Readout Chip for the PHENIX Experiment at RHIC

    Energy Technology Data Exchange (ETDEWEB)

    Hoff, James R.; Zimmerman, Tom N.; Yarema, Raymond J.; /Fermilab; Kapustinsky, Jon S.; Brookes, Melynda L.; /LOS ALAMOS

    2009-01-01

    The FPHX chip is a silicon strip readout chip developed at Fermilab for use in the FVTX Detector of the PHENIX experiment at RHIC. Each front end consists of an integrator which is AC coupled to a shaper, followed by a discriminator and a 3-bit analog-to-digital converter. The backend is a novel architecture in two stages that permits dead-timeless operation and high-speed readout with very low latency. A slow controller provides an interface for all on-chip programmable functions. This chip has been fabricated in the 0.25um TSMC process. All functionality including the analog front-end, the digital back-end, and the slow controller has been verified experimentally.

  14. Studies of MaPMTs with beetle-chip read-out

    CERN Document Server

    Muheim, F

    2005-01-01

    We have evaluated the 64-channel Multianode Photo-Multiplier (MaPMT) with 8-stage dynodes for the LHCb RICH detectors. With a Beetle1.2 chip to read-out the MaPMT, we have demonstrated that the MaPMT performance is as expected using particle beams and LED light sources. We have also measured the pulse shape from 12-stage dynode MaPMTs, read out with the Beetle1.2-MA0 chip.

  15. Studies of MaPMTs with beetle-chip read-out

    CERN Document Server

    Muheim, F

    2005-01-01

    We have evaluated the 64-channel Multianode Photo-Multiplier (MaPMT) with 8-stage dynodes for the LHCb RICH detectors. With a Beetle 1.2 chip to read-out the MaPMT, we have demonstrated that the MaPMT performance is as expected using particle beams and LED light sources. We have also measured the pulse shape from 12-stage dynode MaPMTs, read out with the Beetle 1.2-MA0 chip.

  16. Preliminary Specification of a Silicon Strip Readout Chip for the LHCb Upgrade

    CERN Document Server

    Parkes, Christopher; Idzik, Marek; Van Beuzekom, Martinus; Wyllie, Kenneth; Buytaert, Jan; Collins, Paula; Artuso, Marina; Smith, Anthony Nigel; Eklund, Lars; Dijkstra, Hans; Ferro-Luzzi, Massimiliano

    2012-01-01

    This note documents discussions held between the autumn of 2011 and summer 2012 on an outline specification for the readout chip for silicon strip detectors for the LHCb upgrade. Specifications are set for the external layout, analogue front-end and digitisation performance, and initial comments are included on the digital processing stages.

  17. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  18. Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

    Energy Technology Data Exchange (ETDEWEB)

    Loechner, S.

    2006-07-26

    The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

  19. A read-out system for the Medipix2 chip capable of 500 frames per second

    Energy Technology Data Exchange (ETDEWEB)

    Maiorino, M. [IFAE Institut de Fisica d' Altes Energies, UAB Campus, 08193 Barcelona (Spain)]. E-mail: maiorino@ifae.es; Martinez, R. [Centro Nacional de Microelectronica, IMB-CNM-CSIC, UAB Campus, 08193 Barcelona (Spain); Pellegrini, G. [Centro Nacional de Microelectronica, IMB-CNM-CSIC, UAB Campus, 08193 Barcelona (Spain); Blanchot, G. [IFAE Institut de Fisica d' Altes Energies, UAB Campus, 08193 Barcelona (Spain); Chmeissani, M. [IFAE Institut de Fisica d' Altes Energies, UAB Campus, 08193 Barcelona (Spain); Garcia, J. [IFAE Institut de Fisica d' Altes Energies, UAB Campus, 08193 Barcelona (Spain); Lozano, M. [Centro Nacional de Microelectronica, IMB-CNM-CSIC, UAB Campus, 08193 Barcelona (Spain); Puigdengoles, C. [IFAE Institut de Fisica d' Altes Energies, UAB Campus, 08193 Barcelona (Spain); Ullan, M. [Centro Nacional de Microelectronica, IMB-CNM-CSIC, UAB Campus, 08193 Barcelona (Spain)

    2006-07-01

    High-speed X-ray-imaging acquisition technique is a growing field that can be used to understand microscopic mechanism of different phenomena in biology and material science. IFAE and CNM developed a very high-speed readout system, named DEMAS, for the Medipix2. The system is able to read a single Medipix2 chip through the parallel bus at a rate of 1 kHz.With a duty cycle of 50%, the real sampling speed is 500 frames per second (fps). This implies that 1 ms is allocated to the exposure time and another millisecond is devoted to the read-out of the chip. In such configuration, the raw data throughput is about 500 Mbit/s. For the first time we present examples of acquisition at 500 fps of moving samples with X-rays working in direct capture and photon counting mode.

  20. Production Testing and Quality Assurance of CMS Silicon Microstrip Tracker Readout Chips

    CERN Document Server

    Barrillon, Pierre; Hall, Geoffrey; Leaver, James; Noah, E; Raymond, M; Bisello, Dario; Candelori, Andrea; Kaminski, A; Stefanuti, L; Tessaro, Mario; French, Marcus

    2004-01-01

    The APV25 is the 128 channel CMOS chip developed for readout of the silicon microstrip tracker in the CMS experiment at the CERN Large Hadron Collider. The detector is now under construction and will be the largest silicon microstrip system ever built, with ~200m^2 of silicon sensors. Around 10^5 chips are required to instrument the system, which must operate for about 10 years in a high radiation environment with little or no possibility of microstrip system ever built, with ~200m^2 of silicon sensors. Around 10^5 chips are required to instrument the system, which must operate for about 10 years in a high radiation environment with little or no possibility of assurance of long term performance of the readout electronics, especially verification of radiation tolerance, is highly desirable. This has been achieved by means of automated probe testing of every chip on the silicon wafers from the foundry, followed by studies of sample die to evaluate in more detail properties of the chips which cannot easily be ex...

  1. Simulation of an efficiency measurement of the CMS pixel Read-Out Chip at high rates.

    CERN Document Server

    Delcourt, Martin

    2014-01-01

    My summer student project investigates the effects on the efficiency of out-of-sync events during a beam test at Fermilab on pixel detectors for the phase 1 upgrade of the CMS. While the best results of this project came from direct lab measurements, most of my work was focused on the development of a wider simulation to have a better understanding of the behaviour of the read-out chips during the beam test.

  2. HEXITEC ASIC-a pixellated readout chip for CZT detectors

    Energy Technology Data Exchange (ETDEWEB)

    Jones, Lawrence [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)], E-mail: l.l.jones@stfc.ac.uk; Seller, Paul; Wilson, Matthew; Hardie, Alec [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)

    2009-06-01

    HEXITEC is a collaborative project with the aim of developing a new range of detectors for high-energy X-ray imaging. High-energy X-ray imaging has major advantages over current lower energy imaging for the life and physical sciences, including improved phase-contrast images on larger, higher density samples and with lower accumulated doses. However, at these energies conventional silicon-based devices cannot be used, hence, the requirement for a new range of high Z-detector materials. Underpinning the HEXITEC programme are the development of a pixellated Cadmium Zinc Telluride (CZT) detectors and a pixellated readout ASIC which will be bump-bonded to the detector. The HEXITEC ASIC is required to have low noise (20 electrons rms) and tolerate detector leakage currents. A prototype 20x20 pixel ASIC has been developed and manufactured on a standard 0.35 {mu}m CMOS process.

  3. HEXITEC ASIC—a pixellated readout chip for CZT detectors

    Science.gov (United States)

    Jones, Lawrence; Seller, Paul; Wilson, Matthew; Hardie, Alec

    2009-06-01

    HEXITEC is a collaborative project with the aim of developing a new range of detectors for high-energy X-ray imaging. High-energy X-ray imaging has major advantages over current lower energy imaging for the life and physical sciences, including improved phase-contrast images on larger, higher density samples and with lower accumulated doses. However, at these energies conventional silicon-based devices cannot be used, hence, the requirement for a new range of high Z-detector materials. Underpinning the HEXITEC programme are the development of a pixellated Cadmium Zinc Telluride (CZT) detectors and a pixellated readout ASIC which will be bump-bonded to the detector. The HEXITEC ASIC is required to have low noise (20 electrons rms) and tolerate detector leakage currents. A prototype 20×20 pixel ASIC has been developed and manufactured on a standard 0.35 μm CMOS process.

  4. Performance of CMS silicon microstrip detectors with the APV6 readout chip

    CERN Document Server

    Meschini, M; Angarano, M M; Azzi, P; Babucci, E; Bacchetta, N; Bader, A J; Bagliesi, G; Basti, A; Biggeri, U; Bilei, G M; Bisello, D; Boemi, D; Bosi, F; Borrello, L; Bozzi, C; Braibant, S; Breuker, Horst; Bruzzi, Mara; Buffini, A; Busoni, S; Candelori, A; Caner, A; Castaldi, R; Castro, A; Catacchini, E; Checcucci, B; Ciampolini, P; Civinini, C; Creanza, D; D'Alessandro, R; Da Rold, M; Demaria, N; De Palma, M; Dell'Orso, R; Della Marina, R; Dutta, S; Eklund, C; Peisert, Anna; Feld, L; Fiore, L; Focardi, E; French, M; Freudenreich, Klaus; Fürtjes, A; Giassi, A; Giorgi, M A; Giraldo, A; Glessing, B; Gu, W H; Hall, G; Hammarström, R; Hebbeker, T; Hrubec, Josef; Huhtinen, M; Kaminski, A; Karimäki, V; Saint-Koenig, M; Krammer, Manfred; Lariccia, P; Lenzi, M; Loreti, M; Lübelsmeyer, K; Lustermann, W; Mättig, P; Maggi, G; Mannelli, M; Mantovani, G C; Marchioro, A; Mariotti, C; Martignon, G; McEvoy, B; Messineo, A; My, S; Paccagnella, A; Palla, Fabrizio; Pandoulas, D; Papi, A; Parrini, G; Passeri, D; Pieri, M; Piperov, S; Potenza, R; Radicci, V; Raffaelli, F; Raymond, M; Santocchia, A; Schmitt, B; Selvaggi, G; Servoli, L; Sguazzoni, G; Siedling, R; Silvestris, L; Skog, K; Starodumov, Andrei; Stavitski, I; Stefanini, G; Tempesta, P; Tonelli, G; Tricomi, A; Tuuva, T; Vannini, C; Verdini, P G; Viertel, Gert M; Xie, Z; Li Ya Hong; Watts, S; Wittmer, B

    2000-01-01

    We present results obtained with full-size wedge silicon microstrip detectors bonded to APV6 (Raymond et al., Proceedings of the 3rd Workshop on Electronics for LHC Experiments, CERN/LHCC/97-60) readout chips. We used two identical modules, each consisting of two crystals bonded together. One module was irradiated with 1.7*10/sup 14/ neutrons/cm/sup 2/. The detectors have been characterized both in the laboratory and by exposing them to a beam of minimum ionizing particles. The results obtained are a good starting point for the evaluation of the performance of the "ensemble" detector plus readout chip in a version very similar to the final production one. We detected the signal from minimum ionizing particles with a signal-to- noise ratio ranging from 9.3 for the irradiated detector up to 20.5 for the non-irradiated detector, provided the parameters of the readout chips are carefully tuned. (9 refs).

  5. Performance of CMS silicon microstrip detectors with the APV6 readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Meschini, M. E-mail: meschini@fi.infn.it; Albergo, S.; Angarano, M.; Azzi, P.; Babucci, E.; Bacchetta, N.; Bader, A.; Bagliesi, G.; Basti, A.; Biggeri, U.; Bilei, G.M.; Bisello, D.; Boemi, D.; Bosi, F.; Borrello, L.; Bozzi, C.; Braibant, S.; Breuker, H.; Bruzzi, M.; Buffini, A.; Busoni, S.; Candelori, A.; Caner, A.; Castaldi, R.; Castro, A.; Catacchini, E.; Checcucci, B.; Ciampolini, P.; Civinini, C.; Creanza, D.; D' Alessandro, R.; Da Rold, M.; Demaria, N.; De Palma, M.; Dell' Orso, R.; Marina, R. Della; Dutta, S.; Eklund, C.; Elliott-Peisert, A.; Feld, L.; Fiore, L.; Focardi, E.; French, M.; Freudenreich, K.; Fuertjes, A.; Giassi, A.; Giorgi, M.; Giraldo, A.; Glessing, B.; Gu, W.H.; Hall, G.; Hammerstrom, R.; Hebbeker, T.; Hrubec, J.; Huhtinen, M.; Kaminsky, A.; Karimaki, V.; Koenig, St.; Krammer, M.; Lariccia, P.; Lenzi, M.; Loreti, M.; Luebelsmeyer, K.; Lustermann, W.; Maettig, P.; Maggi, G.; Mannelli, M.; Mantovani, G.; Marchioro, A.; Mariotti, C.; Martignon, G.; McEvoy, B.; Messineo, A.; My, S.; Paccagnella, A.; Palla, F.; Pandoulas, D.; Papi, A.; Parrini, G.; Passeri, D.; Pieri, M.; Piperov, S.; Potenza, R.; Radicci, V.; Raffaelli, F.; Raymond, M.; Santocchia, A.; Schmitt, B.; Selvaggi, G.; Servoli, L.; Sguazzoni, G.; Siedling, R.; Silvestris, L.; Skog, K.; Starodumov, A.; Stavitski, I.; Stefanini, G.; Tempesta, P.; Tonelli, G.; Tricomi, A.; Tuuva, T.; Vannini, C.; Verdini, P.G.; Viertel, G.; Xie, Z.; Li Yahong; Watts, S.; Wittmer, B

    2000-06-01

    We present results obtained with full-size wedge silicon microstrip detectors bonded to APV6 (Raymond et al., Proceedings of the 3rd Workshop on Electronics for LHC Experiments, CERN/LHCC/97-60) readout chips. We used two identical modules, each consisting of two crystals bonded together. One module was irradiated with 1.7x10{sup 14} neutrons/cm{sup 2}. The detectors have been characterized both in the laboratory and by exposing them to a beam of minimum ionizing particles. The results obtained are a good starting point for the evaluation of the performance of the 'ensemble' detector plus readout chip in a version very similar to the final production one. We detected the signal from minimum ionizing particles with a signal-to-noise ratio ranging from 9.3 for the irradiated detector up to 20.5 for the non-irradiated detector, provided the parameters of the readout chips are carefully tuned.

  6. Emulation and Calibration of the SALT Read-out Chip for the Upstream Tracker for Modernised LHCb Detector

    CERN Document Server

    Dendek, Adam

    2015-01-01

    The LHCb is one of the four major experiments currently operating at CERN. The main reason for constructing the LHCb forward spectrometer was a precise measurement of the CP violation in heavy quarks section as well as search for a New Physics. To obtain interesting results, the LHCb is mainly focused on study of B meson decays. Unfortunately, due to the present data acquisition architecture, the LHCb experiment is statistically limited for collecting such events. This fact led the LHCb Collaboration to decide to perform far-reaching upgrade. Key part of this upgrade will be replacement of the TT detector. To perform this action, it was requited to design new tracking detector with entirely new front-end electronics. This detector will be called the Upstream Tracker (UT) and the read-out chip — SALT. This note presents an overall discussion on SALT chip. In particular, the emulation process of the SALT data preformed via the software written by the author.

  7. Design and Characterization of an Analogue Amplifier for the Readout of Micro-Pattern Gaseous Detectors

    CERN Document Server

    Trampitsch, Gerd; Pribyl, Wolfgand; Leopold, Hans

    This doctorate deals with the development of integrated analog preamplifiers for the readout of micro pattern gaseous detectors. Because of the small detector signals the noise performance of the readout electronics is of greatest significance. The design of analog preamplifiers constitutes a trade-off between bandwidth, noise, power consumption, radiation hardness and chip area. A prototype IC consisting of 12 channels was produced in a 0.13 um CMOS technology. Each channel is comprised of a single ended preamplifier followed by a fully differential shaping amplifier that produces a 4th order semi Gaussian pulse. Channels with different peaking time, conversion gain and preamplifier architectures were implemented. Among these a novel rail to rail preamplifier architecture for low voltage operation. Part of the thesis work was the design of a printed circuit test board and the characterization of the prototype ICs. The measurements show very good correlation with the simulated values and the circuit fulfills ...

  8. A monolithic charge-to-amplitude converter (QAC) chip for fast readout of photomultiplier

    CERN Document Server

    Inaba, S; Takamatsu, K; Inaba, M; Baba, T; Sugonyaev, V P; Melebeck, T; Van Bogget, U

    2000-01-01

    A fast charge-to-amplitude converter (QAC) chip has been developed for the readout electronics of the electromagnetic calorimeter (ECAL) of the COMPASS experiment at CERN SPS. It is fabricated using a new advanced complementary bipolar process from Harris Semiconductor with intrinsic radiation hardness. The new QAC chip performs the conversion of fast current pulses generated by a photomultiplier tube (PMT) into voltage signals. The output voltage of the QAC is directly proportional to the input current signal. The circuit block diagram, main features and characteristics of the chip are described. Simulation curves as well as test results of QAC prototypes are presented. They show excellent performances for the COMPASS experiment as well as for uses in high energy and nuclear physics experiments to manage fast current signals.

  9. A binary readout chip for silicon microstrip detector in proton imaging application

    Science.gov (United States)

    Sipala, V.; Bruzzi, M.; Bondì, M.; Bonanno, D.; Cadeddu, S.; Carpinelli, M.; Cirrone, G. A. P.; Civinini, C.; Cuttone, G.; Lai, A.; Leonora, E.; Lo Presti, D.; Maccioni, G.; Pallotta, S.; Randazzo, N.; Scaringella, M.; Talamonti, C.; Tesi, M.; Vanzi, E.

    2017-01-01

    The mixed-signal PRIMA-chip has been developed for sensitive-position silicon detector in proton imaging application. The chip is based upon the binary readout architecture which, providing fully parallel signal processing, is a good solution for high intensity radiation application. It includes 32-front-end channels with a charge preamplifier, a shaper and a comparator. In order to adjust the comparator thresholds, each channel contains a 8-bit DAC, programmed using an I2C like interface. The PRIMA-chip has been fabricated using the AMS 0.35 μm standard CMOS process and its performances have been tested coupling it to the detectors used in the tracker assembled for the pCT (proton Computed Tomography) apparatus.

  10. Test Beam Data Analysis for a Timepix3 Readout Chip

    CERN Document Server

    Williams, Morag

    2016-01-01

    The vertex and tracker detector R&D for a future linear collider (CLICdp) aims at developing new silicon sensor technologies. The EP-LCD group has been helping develop a novel pixel detector chip called the Timepix3 with a very thick active silicon layer (675 μm). This thick detector can be used to reconstruct the track incidence angle using the charge drift-time information. To evaluate the principle, test beam data was taken in October 2015 and June 2016 with the Timepix3 at various angles to the beam. The data was analysed to evaluate the sensors performance in calculating the track incidence angle. The device angle was determined using three methods: the first using the cluster size information, secondly using the timing information, and finally using a multivariate analysis technique. The timing method proved the principle of the Timepix3 track angle measurements but the MVA method was found to give much better results, especially for smaller angles, than the other two methods and requires fewer cal...

  11. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  12. A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  13. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature. PMID:22247656

  14. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    Science.gov (United States)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  15. Cool Timepix – Electronic noise of the Timepix readout chip down to −125 °C

    Energy Technology Data Exchange (ETDEWEB)

    Schön, R., E-mail: rolfs@nikhef.nl; Alfonsi, M.; Bakel, N. van; Beuzekom, M. van; Koffeman, E.

    2015-01-21

    The Timepix readout chip with its 65k pixels on a sensitive area of 14 mm×14 mm provides a fine spatial resolution for particle tracking or medical imaging. We explore the operation of Timepix in a dual-phase xenon environment (around −110 °C). Used in dual-phase xenon time projection chambers, e.g. for dark matter search experiments, the readout must have a sufficiently low detection limit for small energy deposits. We measured the electronic pixel noise of three bare Timepix chips. For the first time Timepix readout chips were cooled to temperatures as low as −125 °C. In this work, we present the results of analysing noise transition curves recorded while applying a well-defined charge to the pixel's input. The electronic noise reduces to an average of 99e{sup −}, a reduction of 23% compared to operation at room temperature.

  16. Super-Altro 16: a Front-End System on Chip for DSP Based Readout of Gaseous Detectors

    CERN Document Server

    Aspell, P.; Franca, H.; Garcia Garcia, E.; Musa, L.

    2013-01-01

    This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4mm2/channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40MHz before providing the digitized signal to the DSP which performs baseline subtraction, signa...

  17. First measurements on Inner Tracker silicon prototype sensors using the BEETLE v1.1 readout chip

    CERN Document Server

    Glebe, T; Pugatch, V; Schmelling, M; Lehner, F; Sievers, P; Steinkamp, O; Straumann, U; Vollahrdt, A; Ziegler, M

    2002-01-01

    Inner Tracker silicon prototype sensors were connected to the BEETLE v1.1 readout chip and evaluated in a test beam, performed at the X7 facility in October 2001. The main aim of this test was to integrate for the first time different components (BEETLE chip, ODE prototype board) of the readout chain into a running system. Noise characteristics and pulse shape were investigated in the test beam and in a laboratory test setup in Zuerich. We also present measurements of the S/N-ratio and efficiency.

  18. The Origami Chip-on-Sensor Concept for Low-Mass Readout of Double-Sided Silicon Detectors

    CERN Document Server

    Friedl, M; Pernicka, M

    2008-01-01

    Modern front-end amplifiers for silicon strip detectors offer fast shaping but consequently are susceptible to input capacitance which is the main contribution to the noise figure. Hence, the amplifier must be close to the sensor which is not an issue at LHC, but a major concern at material budget sensitive experiments such as Belle or the ILC detector. We present a design of a silicon detector module with double-sided readout where thinned front-end chips are aligned on one side of the sensor which allows efficient cooling using just a single, thin aluminum pipe. The connection to the other sensor side is established by thin kapton circuits wrapped around the edge – hence the nickname origami.

  19. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  20. Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

    Science.gov (United States)

    Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

    2010-01-01

    The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively. PMID:22294897

  1. Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Ching-Liang Dai

    2010-03-01

    Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

  2. Characterization of edgeless pixel detectors coupled to Medipix2 readout chip

    Science.gov (United States)

    Kalliopuska, Juha; Tlustos, Lukas; Eränen, Simo; Virolainen, Tuula

    2011-08-01

    VTT has developed a straightforward and fast process to fabricate four-side buttable (edgeless) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process relies on advanced ion implantation to activate the edges of the detector instead of using polysilicon. The article characterizes 150 μm thick n-on-n edgeless pixel detector prototypes with a dead layer at the edge below 1 μm. Electrical and radiation response characterization of 1.4×1.4 cm2 n-on-n edgeless detectors has been done by coupling them to the Medipix2 readout chips. The distance of the detector's physical edge from the pixels was either 20 or 50 μm. The leakage current of flip-chip bonded edgeless Medipix2 detector assembles were measured to be ˜90 nA/cm2 and no breakdown was observed below 110 V. Radiation response characterization includes X-ray tube and radiation source responses. The characterization results show that the detector's response at the pixels close to the physical edge of the detector depend dramatically on the pixel-to-edge distance.

  3. Medipix3: A 64 k pixel detector readout chip working in single photon counting mode with improved spectrometric performance

    CERN Document Server

    Ballabriga, R; Wong, W; Heijne, E; Campbell, M; Llopart, X

    2011-01-01

    Medipix3 is a 256 x 256 channel hybrid pixel detector readout chip working in a single photon counting mode with a new inter-pixel architecture, which aims to improve the energy resolution in pixelated detectors by mitigating the effects of charge sharing between channels. Charges are summed in all 2 x 2 pixel clusters on the chip and a given hit is allocated locally to the pixel summing circuit with the biggest total charge on an event-by-event basis. Each pixel contains also two 12-bit binary counters with programmable depth and overflow control. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are four times greater in area than the readout pixels. In the latter case, event-by-event summing is still possible between the larger pixels. Each pixel has around 1600 transistors and the analog static power consumption is below 15 mu W in the charge summing mode and 9 mu W in the single pixel mode. The chip has been built in an 8-m...

  4. Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

    2015-07-01

    The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

  5. Pad Plane Design and Readout for SAMURAI TPC

    Science.gov (United States)

    Barney, J.; Chajecki, Z.; Chan, C. F.; Dunn, J. W.; Estee, J.; Gilbert, J.; Lu, F.; Lynch, W. G.; Shane, R.; Tsang, M. B.; McIntosh, A. B.; Yenello, S. J.; Famiano, M.; Isobe, T.; Sakurai, H.; Taketani, A.; Murakami, T.; Samurai-Tpc Collaboration

    2011-10-01

    The SAMURAI TPC is being built at Michigan State University to be used in the SAMURAI spectrometer at RIKEN in Japan, as part of the Symmetry Energy project, which focuses on obtaining constraints on the symmetry energy at supra-saturation densities. The presentation will discuss the development of the TPC as well as design for readout plane design for the TPC. These involve enabling the use of existing and future front end electronics (FEE), making the most of limited space, designing a circuit board for the pad plane, and techniques to glue the pad plane. The pad plane has been designed to work with either STAR or AGET electronics. The pad plane is made of a circuit board designed to minimize crosstalk and capacitance. The board must be built in smaller pieces and tiled, using alignment pins and precision gluing. Prototypes for the pad plane to FEE connection, pad plane gluing and STAR card mounting will be presented. Supported by the Department of Energy under Grant DE-SC0004835.

  6. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  7. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  8. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  9. SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    Science.gov (United States)

    Bouchel, M.; Callier, S.; Dulucq, F.; Fleury, J.; Jaeger, J.-J.; de La Taille, C.; Martin-Chassard, G.; Raux, L.

    2011-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

  10. Thermal design and tests for the CMS HCAL readout box

    CERN Document Server

    Baumbaugh, B; Booke, M; Karmgard, D; Los, S; Lu, Q; Marchant, J; Reidy, J; Ronzhin, A; Ruchti, R C; Wiand, D

    2000-01-01

    A method is necessary to cool the electronics contained in the readout boxes for the CMS HCAL. The electronics to pre-amplify and digitize signals from the optical detectors will generate a large amount of heat that must be removed from the CMS HCAL system. To accomplish this a thermal management system has been designed that uses metallic extrusions, liquid coolant, and thermal foam to transfer the heat from the electronics to the exterior cooling system. Because the electronics are difficult to access throughout the life of the experiment, the temperature must be kept low to extend life expectancy. In order to test the concepts before the final design is implemented a thermal test station was built. Several methods to are under study to determine the best method of making the thermal routing from source of the heat to the liquid for heat removal. The test bed for this evaluation and methods to monitor the electronics temperature in situ will be discussed. 3 Refs.

  11. A finite state machine read-out chip for integrated surface acoustic wave sensors

    Science.gov (United States)

    Rakshit, Sambarta; Iliadis, Agis A.

    2015-01-01

    A finite state machine based integrated sensor circuit suitable for the read-out module of a monolithically integrated SAW sensor on Si is reported. The primary sensor closed loop consists of a voltage controlled oscillator (VCO), a peak detecting comparator, a finite state machine (FSM), and a monolithically integrated SAW sensor device. The output of the system oscillates within a narrow voltage range that correlates with the SAW pass-band response. The period of oscillation is of the order of the SAW phase delay. We use timing information from the FSM to convert SAW phase delay to an on-chip 10 bit digital output operating on the principle of time to digital conversion (TDC). The control inputs of this digital conversion block are generated by a second finite state machine operating under a divided system clock. The average output varies with changes in SAW center frequency, thus tracking mass sensing events in real time. Based on measured VCO gain of 16 MHz/V our system will convert a 10 kHz SAW frequency shift to a corresponding mean voltage shift of 0.7 mV. A corresponding shift in phase delay is converted to a one or two bit shift in the TDC output code. The system can handle alternate SAW center frequencies and group delays simply by adjusting the VCO control and TDC delay control inputs. Because of frequency to voltage and phase to digital conversion, this topology does not require external frequency counter setups and is uniquely suitable for full monolithic integration of autonomous sensor systems and tags.

  12. Design of a large dynamic range readout unit for the PSD detector of DAMPE

    CERN Document Server

    Zhou, Yong; Sun, Zhiyu; Zhang, Yongjie; Fang, Fang; Chen, Junling; Hu, Bitao

    2016-01-01

    A large dynamic range is required by the Plastic Scintillator Detector (PSD) of DArk Matter Paricle Explorer (DAMPE), and a double-dynode readout has been developed. To verify this design, a prototype detector module has been constructed and tested with cosmic rays and heavy ion beams. The results match with the estimation and the readout unit could easily cover the required dynamic range.

  13. Study of the VMM1 read-out chip in a neutron irradiation environment

    Science.gov (United States)

    Alexopoulos, T.; Fanourakis, G.; Geralis, T.; Kokkoris, M.; Kourkoumeli-Charalampidi, A.; Papageorgiou, K.; Tsipolitis, G.

    2016-05-01

    Within 2015, the LHC operated close to the design energy of √s = 13-14 TeV delivering instantaneous luminosities up to Script L = 5 × 1033 cm-2s-1. The ATLAS Phase-I upgrade in 2018/19 will introduce the MicroMEGAS detectors in the area of the small wheel at the end caps. Accompanying new electronics are designed and built such as the VMM front end ASIC, which provides energy, timing and triggering information and allows fast data read-out. The first VMM version (VMM1) has been widely produced and tested in various test beams, whilst the second version (VMM2) is currently being tested. This paper focuses on the VMM1 single event upset studies and more specifically on the response of the configuration registers under harsh radiation environments. Similar conditions are expected at Run III with Script L = 2 × 1034 cm-2s-1 and a mean of 55 interactions per bunch crossing. Two VMM1s were exposed in a neutron irradiation environment using the TANDEM Van Der Graaff accelerator at NSCR Demokritos, Athens, Greece. The results showed a rate of SEU occurrences at a measured cross section of (4.1±0.8)×10-14 cm2/bit for each VMM. Consequently, when extrapolating this value to the luminosity expected in Run III, the occurrence is roughly 6 SEUs/min in all the read-out system comprising 40,000 VMMs installed during the Phase-I upgrade.

  14. Design of the readout electronics for the DAMPE Silicon Tracker detector

    CERN Document Server

    Zhang, Fei; Gong, Ke; Wu, Di; Dong, Yi-Fan; Qiao, Rui; Fan, Rui-Rui; Wang, Jin-Zhou; Wang, Huan-Yu; Wu, Xin; La Marra, Daniel; Azzarello, Philipp; Gallo, Valentina; Ambrosi, Giovanni; Nardinocchi, Andrea

    2016-01-01

    The Silicon Tracker (STK) is a detector of the DAMPE satellite to measure the incidence direction of high energy cosmic ray. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73,728 readout channels. It's a great challenge to readout the channels and process the huge volume of data in the critical space environment. 1152 Application Specific Integrated Circuits (ASIC) and 384 ADCs are adopted to readout the detector channels. The 192 Tracker Front-end Hybrid (TFH) modules and 8 identical Tracker Readout Board (TRB) modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for STK and its performance will be presented in detail.

  15. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  16. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  17. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  18. A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface.

    Science.gov (United States)

    Chang, Hyejin; Kang, Homan; Jeong, Sinyoung; Ko, Eunbyeol; Lee, Yoon-Sik; Lee, Ho-Young; Jeong, Dae Hong

    2015-05-01

    Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, we analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.

  19. A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface

    Energy Technology Data Exchange (ETDEWEB)

    Chang, Hyejin; Jeong, Sinyoung; Ko, Eunbyeol; Jeong, Dae Hong, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of); Kang, Homan [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Yoon-Sik, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); School of Chemical and Biological Engineering, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Ho-Young, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Nuclear Medicine, Seoul National University Bundang Hospital, Seongnam 463-707 (Korea, Republic of)

    2015-05-15

    Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, we analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.

  20. A programmable energy efficient readout chip for a multiparameter highly integrated implantable biosensor system

    Science.gov (United States)

    Nawito, M.; Richter, H.; Stett, A.; Burghartz, J. N.

    2015-11-01

    In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtraction technique is employed to raise the resolution to 12-bits. Charge integration is utilized for oxygen and temperature measurements with the capability to cover current ranges between 30 nA and 1 μA. In order to achieve good performance over a wide range of supply and process variations, internal reference voltages are generated from a programmable band-gap regulated circuit and biasing currents are supplied from a wide-range bootstrap current reference. To accommodate the limited available electrical power, all components are designed for low power operation. Also a sequential operation approach is applied, in which essential circuit building blocks are time multiplexed between different measurement types. All measurement sequences and parameters are programmable and can be adjusted for different tissues and media. The chip communicates with external unites through a full duplex two-wire Serial Peripheral Interface (SPI), which receives operational instructions and at the same time outputs the internally stored measurement data. The circuit has been fabricated in a standard 0.5-μm CMOS process and operates on a supply as low as 2.7 V. Measurement results show good performance and agree with circuit simulation. It consumes a maximum of 500 μA DC current and is clocked between 500 kHz and 4 MHz according to the measurement parameters. Measurement results of the on-chip ADC show a

  1. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally...

  2. Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

    Science.gov (United States)

    Harb, Ali; Mussgiller, Andreas; Hauk, Johannes

    2017-02-01

    The CMS Binary Chip (CBC) is a prototype version of the front-end read-out ASIC to be used in the silicon strip modules of the CMS outer tracking detector during the high luminosity phase of the LHC. The CBC is produced in 130 nm CMOS technology and bump-bonded to the hybrid of a double layer silicon strip module, the so-called 2S-pT module. It has 254 input channels and is designed to provide on-board trigger information to the first level trigger system of CMS, with the capability of cluster-width discrimination and high-pT track identification. In November 2013 the first 2S-pT module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2 to 4 GeV. In this paper the test setup and the results are presented.

  3. Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

    Energy Technology Data Exchange (ETDEWEB)

    Harb, Ali; Hauk, Johannes; Mussgiller, Andreas [DESY-Hamburg (Germany)

    2015-07-01

    The CMS Binary Chip 2 (CBC2) is a prototype version of the front-end readout ASIC to be used in the silicon stripmodules of the CMS outer tracker during the high-luminosity phase of the LHC. The CBC2 is produced in a 130 nm CMOS technology and bump-bonded to the hybrid of the double layer silicon strip modules, the so-called 2S modules. It has 254 input channels and is designed to provide an on-board trigger with the capability of cluster-width discrimination and high-momentum track identification. In November 2013 the first 2S module prototypes equipped with CBC2 were put under test at the DESY-II test beam facility. Data was collected exploiting a beam of positrons with an energy range of 2 to 4 GeV. The test setup, the event reconstruction, and the analysis results such as beam properties, alignment, clusters properties, and per-chip efficiency are presented.

  4. Radiation and Temperature Effects on the APV25 Readout Chip for the CMS Tracker

    CERN Document Server

    Messomo, Etam Albert Noah

    2002-01-01

    The Compact Muon Solenoid (CMS) is one of four particle detectors designed for use at the Large Hadron Collider (LHC) currently under construction at CERN, the European Laboratory for Particle Physics in Geneva. The LHC will accelerate two counterrotating beams of protons to energies of 7 TeV and produce 109 proton-proton collisions per second at a bunch-crossing frequency of 40 MHz. These collisions occuring at the centre of CMS will generate a very hostile radiation environment. The CMS sub-detector system closest to the collision point is the highly segmented Tracker, consisting of a silicon pixel detector with 45 million channels and a silicon microstrip detector with 10 million channels. The microstrip detector will be read out by the APV25, a custom-made chip manufactured in a commercial 0.25 µm CMOS microelectronics process. Radiation and temperature studies are required to ensure that the APV25 can operate reliably in the CMS environment. The radiation effects to which the APV25 could be susceptible ...

  5. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  6. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  7. A 130 nm CMOS mixed mode front end readout chip for silicon strip tracking at the future linear collider

    Energy Technology Data Exchange (ETDEWEB)

    Pham, T.H., E-mail: pham@lpnhe.in2p3.f [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Charpy, A.; Ciobanu, C. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Comerma, A. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); David, J.; Dhellot, M. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Dieguez, A.; Gascon, D. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); Genat, J.F.; Savoy Navarro, A.; Sefri, R. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France)

    2010-11-01

    A 130 nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low noise charge amplifier and integration with long pulse shaping, (ii) an eight by eight positions analog sampler for both storing successive events and reconstructing the full pulse shape, and (iii) a sparsifier performing analog sum of three adjacent inputs to decide whether there is signal or not. The whole system is controlled by the digital part, which allows configuring all the reference currents and voltages, drives the control signals to the analog memories, records the timing and channel information and subsequently performs the conversion to digital values of samples. The total surface of the circuit is 10x5 mm{sup 2}, with each analog channel occupying an area of 105x3500 {mu}m{sup 2}, and the remaining space of about 9000x700 {mu}m{sup 2} being filled by the analog channels on the silicon.

  8. A large dynamic range readout design for the plastic scintillator detector of DAMPE

    Science.gov (United States)

    Zhou, Yong; Sun, Zhiyu; Yu, Yuhong; Zhang, Yongjie; Fang, Fang; Chen, Junling; Hu, Bitao

    2016-08-01

    A large dynamic range is required by the Plastic Scintillator Detector (PSD) of DArk Matter Particle Explorer (DAMPE) to detect particles from electron to heavy ions with Z ≤ 20. To expand the dynamic range, the readout design based on the double-dynodes signal extraction from the photomultiplier tube has been proposed and adopted by PSD. To verify this design, a prototype detector module has been constructed and tested with cosmic ray and relativistic ion beam. The results match with the estimation and the readout unit could easily cover the required dynamic range of about 4 orders of magnitude.

  9. Development and Characterisation of a Radiation Hard Readout Chip for the LHCb Outer Tracker Detector

    CERN Document Server

    Stange, Uwe

    2005-01-01

    The reconstruction of charged particle tracks in the Outer Tracker detector of the LHCb experiment requires to measure the drift times of the straw tubes. A Time to Digital Converter (TDC) chip has been developed for this task. The chip integrates into the LHCb data acquisition schema and ful ls the requirements of the detector. The OTIS chip is manufactured in a commercial 0.25 µm CMOS process. A 32-channel TDC core drives the drift time measurement (25 ns measurement range, 390 ps nominal resolution) without introducing dead times. The resulting drift times are bu ered until a trigger decision arrives after the xed latency of 4 µs. In case of a trigger accept signal, the digital control core processes and transmits the corresponding data to the following data acquisition stage. Drift time measurement and data processing are independent from the detector occupancy. The digital control core of the OTIS chip has been developed within this doctoral thesis. It has been integrated into the TDC chip together wit...

  10. Design of the readout electronics for the DAMPE Silicon Tracker detector

    Science.gov (United States)

    Zhang, Fei; Peng, Wen-Xi; Gong, Ke; Wu, Di; Dong, Yi-Fan; Qiao, Rui; Fan, Rui-Rui; Wang, Jin-Zhou; Wang, Huan-Yu; Wu, Xin; La Marra, Daniel; Azzarello, Philipp; Gallo, Valentina; Ambrosi, Giovanni; Nardinocchi, Andrea

    2016-11-01

    The Silicon Tracker (STK) is one of the detectors of the DAMPE satellite used to measure the incidence direction of high energy cosmic rays. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73728 readout channels. It is a great challenge to read out the channels and process the huge volume of data in the harsh environment of space. 1152 Application Specific Integrated Circuits (ASIC) and 384 ADCs are used to read out the detector channels. 192 Tracker Front-end Hybrid (TFH) modules and 8 identical Tracker Readout Board (TRB) modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for the STK and its performance are presented in detail.

  11. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

    Energy Technology Data Exchange (ETDEWEB)

    Maj, Piotr; Grybos, P.; Szczgiel, R.; Kmon, P.; Drozd, A.; Deptuch, G.

    2013-11-07

    We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 m. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

  12. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  13. Integrated Circuit Readout for the Silicon Sensor Test Station

    CERN Document Server

    Atkin, E; Silaev, A; Fedenko, A; Karmanov, D; Merkin, M; Voronin, A

    2009-01-01

    Various chips for the silicon sensors measurements are described. These chips are based on 0.35 um and 0.18um CMOS technology. Several analog chips together with self-trigger /derandomizer one allow to measure silicon sensors designed for different purposes. Tracking systems, calorimeters, particle charge measurement system and other application sensors can be investigated by the integrated circuit readout with laser or radioactive sources. Also electrical parameters of silicon sensors can be studied by such test setup.

  14. TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Gryboś, P.

    2011-01-01

    This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

  15. Tests of gases in a mini-TPC with pixel chip readout

    Energy Technology Data Exchange (ETDEWEB)

    Vahsen, S. [University of Hawaii, 2505 Correa Road, Honolulu, HI 96822 (United States); Oliver-Mallory, K.; Lopez-Thibodeaux, M. [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Kadyk, J., E-mail: jakadyk@lbl.gov [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States)

    2014-02-21

    Gases for potential use as targets for directional dark matter detection were tested in a prototype detector using two sequential Gas Electron Multipliers, or GEMs. The sensitive volume consists of a mini-TPC of 12 cm length and 7.5 cm diameter. An FEI3 pixel chip, developed for the ATLAS experiment, was used to produce spatial measurements with high resolution. An Fe55 source produced photoelectrons by X-ray conversions in the sensitive volume, and images of these were recorded by the chip. Spatial resolution plots are shown for the gases, which include the practical electron range of the photoelectrons and the effects of diffusion in the mini-TPC. Avalanche gain and gain resolution measurements were made for the four gases tested, at atmospheric and sub-atmospheric pressures: Ar(70)/CO{sub 2}(30), CF{sub 4}, He(80)/CF{sub 4}(20) and He(80)/isobutane(20)

  16. Study of Charge Diffusion in a Silicon Detector Using an Energy Sensitive Pixel Readout Chip

    CERN Document Server

    Schioppa, E. J.; van Beuzekom, M.; Visser, J.; Koffeman, E.; Heijne, E.; Engel, K. J.; Uher, J.

    2015-01-01

    A 300 μm thick thin p-on-n silicon sensor was connected to an energy sensitive pixel readout ASIC and exposed to a beam of highly energetic charged particles. By exploiting the spectral information and the fine segmentation of the detector, we were able to measure the evolution of the transverse profile of the charge carriers cloud in the sensor as a function of the drift distance from the point of generation. The result does not rely on model assumptions or electric field calculations. The data are also used to validate numerical simulations and to predict the detector spectral response to an X-ray fluorescence spectrum for applications in X-ray imaging.

  17. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  18. New smart readout technique performing edge detection designed to control vision sensors dataflow

    Science.gov (United States)

    Amhaz, Hawraa; Sicard, Gilles

    2012-03-01

    In this paper, a new readout strategy for CMOS image sensors is presented. It aims to overcome the excessive output dataflow bottleneck; this challenge is becoming more and more crucial along with the technology miniaturization. This strategy is based on the spatial redundancies suppression. It leads the sensor to perform edge detection and eventually provide binary image. One of the main advantages of this readout technique compared to other techniques, existing in the literature, is that it does not affect the in-pixel circuitry. This means that all the analogue processing circuitry is implemented outside the pixel, which keeps the pixel area and Fill Factor unchanged. The main analogue block used in this technique is an event detector developed and designed in the CMOS 0.35μm technology from Austria Micro Systems. The simulation results of this block as well as the simulation results of a test bench composed of several pixels and column amplifiers using this readout mode show the capability of this readout mode to reduce dataflow by controlling the ADCs. We must mention that this readout strategy is applicable on sensors that use a linear operating pixel element as well as for those based on logarithmic operating pixels. This readout technique is emulated by a MATLAB model which gives an idea about the expected functionalities and dataflow reduction rates (DRR). Emulation results are shown lately by giving the pre and post processed images as well as the DRR. This last cited does not have a fix value since it depends on the spatial frequency of the filmed scenes and the chosen threshold value.

  19. Offset correction system for 128-channel self-triggering readout chip with in-channel 5-bit energy measurement functionality

    Energy Technology Data Exchange (ETDEWEB)

    Otfinowski, P., E-mail: potfin@agh.edu.pl; Grybos, P.; Szczygiel, R.; Kasinski, K.

    2015-04-21

    We report on a novel, two-stage 8-bit trimming solution dedicated for multichannel systems with reduced trim DAC area occupancy. The presented design was used for comparator offset correction in a 128-channel particle tracking, self-triggering readout system and manufactured in 180 nm CMOS process. The 8-bit trim DAC has a range of ±165 mV, current consumption of 3.2 µA and occupies an area of 37 µm×17 µm in each channel, which corresponds to a 6-bit conventional current steering DAC with similar linearity.

  20. Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

    CERN Document Server

    Akerstedt, H; The ATLAS collaboration; Drake, Gary; Anderson, Kelby; Bohm, C; Oreglia, Mark; Tang, Fukun

    2015-01-01

    The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of ...

  1. Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

    Energy Technology Data Exchange (ETDEWEB)

    Akerstedt, Henrik; Muschter, Steffen; Drake, Gary; Anderson, Kelby; Bohm, Christian; Oreglia, Mark; Tang, Fukun

    2015-10-01

    The Tile Calorimeter at ATLAS [1] is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new readout system will be installed in one slice of the ATLAS Tile Calorimeter. This will allow the proposed upgrade to be thoroughly evaluated well before the planned 2023 deployment in all slices, especially with regard to long term reliability. Different firmware strategies alongside with their integration in the demonstrator are presented in the context of high reliability protection against hardware malfunction and radiation induced errors.

  2. Embedded Adaptive Optics for Ubiquitous Lab-on-a-Chip Readout on Intact Cell Phones

    Directory of Open Access Journals (Sweden)

    Pakorn Preechaburana

    2012-06-01

    Full Text Available The evaluation of disposable lab-on-a-chip (LOC devices on cell phones is an attractive alternative to migrate the analytical strength of LOC solutions to decentralized sensing applications. Imaging the micrometric detection areas of LOCs in contact with intact phone cameras is central to provide such capability. This work demonstrates a disposable and morphing liquid lens concept that can be integrated in LOC devices and refocuses micrometric features in the range necessary for LOC evaluation using diverse cell phone cameras. During natural evaporation, the lens focus varies adapting to different type of cameras. Standard software in the phone commands a time-lapse acquisition for best focal selection that is sufficient to capture and resolve, under ambient illumination, 50 μm features in regions larger than 500 × 500 μm2. In this way, the present concept introduces a generic solution compatible with the use of diverse and unmodified cell phone cameras to evaluate disposable LOC devices.

  3. Pixelized M-pi-n CdTe detector coupled to Medipix2 readout chip

    CERN Document Server

    Kalliopuska, J; Penttila, R; Andersson, H; Nenonen, S; Gadda, A; Pohjonen, H; Vanttajac, I; Laaksoc, P; Likonen, J

    2011-01-01

    We have realized a simple method for patterning an M-pi-n CdTe diode with a deeply diffused pn-junction, such as indium anode on CdTe. The method relies on removing the semiconductor material on the anode-side of the diode until the physical junction has been reached. The pixelization of the p-type CdTe diode with an indium anode has been demonstrated by patterning perpendicular trenches with a high precision diamond blade and pulsed laser. Pixelization or microstrip pattering can be done on both sides of the diode, also on the cathode-side to realize double sided detector configuration. The article compares the patterning quality of the diamond blade process, pulsed pico-second and femto-second lasers processes. Leakage currents and inter-strip resistance have been measured and are used as the basis of the comparison. Secondary ion mass spectrometry (SIMS) characterization has been done for a diode to define the pn-junction depth and to see the effect of the thermal loads of the flip-chip bonding process. Th...

  4. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized acco

  5. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  6. Design of versatile ASIC and protocol tester for CBM readout system

    Science.gov (United States)

    Zabołotny, W. M.; Byszuk, A. P.; Emschermann, D.; Gumiński, M.; Juszczyk, B.; Kasiński, K.; Kasprowicz, G.; Lehnert, J.; Müller, W. F. J.; Poźniak, K.; Romaniuk, R.; Szczygieł, R.

    2017-02-01

    Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.

  7. The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

    CERN Document Server

    Zivkovic, V; Garcia-Sciveres, M; Mekkaoui, A; Barbero, M; Darbo, G; Gnani, D; Hemperek, T; Menouni, M; Fougeron, D; Gensolen, F; Jensen, F; Caminada, L; Gromov, V; Kluit, R; Fleury, J; Krüger, H; Backhaus, M; Fang, X; Gonella, L; Rozanove, A; Arutinov, D

    2012-01-01

    The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

  8. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  9. The design of high performance, low power triple-track magnetic sensor chip.

    Science.gov (United States)

    Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

    2013-07-09

    This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  10. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  11. Video Format Conversion Chip Design

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    This paper introduces the design of an IC, which is capable of cross-converting between various DTV standards, up to the HDTV resolution. A multi-phase FIR-based filtering algorithm is developed to perform the video scaling tasks. A dedicated fast SDRAM interface is designed in the system, providing an economical high-density storage for frame buffer. Meanwhile, film material pre-processing and frame/field rate up-conversion are also implemented in the memory control block. Finally, all the programmable parameters, such as the filter properties, can be set dynamically at run-time through an I2C interface, making the IC a very flexible system.This design has been verified through an FPGA emulation system. Subjective test of the output images indicates that the IC is a suitable and high quality solution to consumer applications.

  12. Recent results of Micromegas sDHCAL with a new readout chip

    CERN Document Server

    Adloff, C; Blaising, J -J; Chefdeville, M; Dalmaz, A; Drancourt, C; Espargilière, A; Gaglione, R; Geffroy, N; Jacquemier, J; Karyotakis, Y; Peltier, F; Prast, J; Tsigaridas, S; Tsipolitis, Y; Vouters, G

    2012-01-01

    Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the active medium of a hadronic calorimeter. A chamber of 1 m2 with 9216 channels read out by a low noise front-end ASIC called MICROROC has recently been constructed and tested. Chamber design, ASIC circuitry and preliminary test beam results are reported.

  13. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    Energy Technology Data Exchange (ETDEWEB)

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  14. MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

    Science.gov (United States)

    Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2017-01-01

    MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

  15. Design of the CMS-CASTOR subdetector readout system by reusing existing designs

    CERN Document Server

    Beaumont, W

    2009-01-01

    CASTOR is a cylindrical calorimeter with a length of 1.5m and a diameter of 60cm located at 14.3 meters from the CMS interaction point and covering the range in pseudorapidity corresponding to 5.1 < | eta | < 6.6. The CASTOR project was approved in the middle of 2007. Given the limited resources and time, developing a readout system from scratch was excluded. Here the final implementations of the readout chain, the considerations for the different choices as well as the performance of the installed equipment are discussed.

  16. Design of the CMS-CASTOR sub detector readout system by reusing existing designs

    CERN Document Server

    Beaumont, Willem

    2009-01-01

    CASTOR is a cylindrical calorimeter with a length of 1.5m and a diameter of 60cm located at 14.3 meters from the CMS interaction point and covering the range in pseudo-rapidity corresponding to 5.1 ~\\textless~ \\textbar~ eta~ \\textbar ~ \\textless ~ 6.6. The CASTOR project was approved in the middle of 2007. Given the limited resources and time, developing a readout system from scratch was excluded. Here the final implementations of the readout chain, the considerations for the different choices as well as the performance of the installed equipment are discussed.

  17. Readout of the upgraded ALICE-ITS

    Science.gov (United States)

    Szczepankiewicz, A.

    2016-07-01

    The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb-Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

  18. Optimal and robust design method for two-chip out-of-plane microaccelerometers.

    Science.gov (United States)

    Lee, Sangmin; Ko, Hyoungho; Choi, Byoungdoo; Cho, Dong-il Dan

    2010-01-01

    In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g∼389 mV/g, the output nonlinearity of 0.43% FSO∼0.60% FSO, the input range of ±2 g and a bias instability of 122 μg∼229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be 74.00 dB∼75.23 dB and 180 μg/rtHz∼190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%∼1.9% and 0.3%∼0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.

  19. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers

    Directory of Open Access Journals (Sweden)

    Hyoungho Ko

    2010-11-01

    Full Text Available In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g~389 mV/g, the output nonlinearity of 0.43% FSO~0.60% FSO, the input range of ±2 g and a bias instability of 122 μg~229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be74.00 dB~75.23 dB and 180 μg/rtHz~190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%~1.9% and 0.3%~0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.

  20. Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

    CERN Document Server

    Gallin-Martel, L; Hostachy, J Y; Rarbi, F; Rossetto, O

    2009-01-01

    The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.

  1. SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Callier, S.; Fleury, J.; Dulucq, F.; De la Taille, C.; Chassard, G. Martin; Raux, L.; Seguin-Moreau, N.

    2013-01-01

    For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

  2. Design and characterization of TES bolometers and SQUID readout electronics for a balloon-borne application

    CERN Document Server

    Hubmayr, Johannes; Bissonnette, Eric; Dobbs, Matt; Hanany, Shaul; Lee, Adrian T; MacDermid, Kevin; Meng, Xiaofan; Sagiv, Ilan; Smecher, Graeme

    2009-01-01

    We present measurements of the electrical and thermal properties of new arrays of bolometeric detectors that were fabricated as part of a program to develop bolometers optimized for the low photon background of the EBEX balloon-borne experiment. An array consists of 140 spider-web transition edge sensor bolometers microfabricated on a 4" diameter silicon wafer. The designed average thermal conductance of bolometers on a proto-type array is 32 pW/K, and measurements are in good agreement with this value. The measurements are taken with newly developed, digital frequency domain multiplexer SQUID readout electronics.

  3. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  4. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  5. Study and optimization of the spatial resolution for detectors with binary readout

    CERN Document Server

    Yonamine, Ryo; De Lentdecker, Gilles

    2016-01-01

    Using simulations and analytical approaches, we have studied single hit resolutions obtained with a binary readout, which is often proposed for high granularity detectors to reduce the generated data volume. Our simulations considering several parameters (e.g. strip pitch) show that the detector geometry and an electronics parameter of the binary readout chips could be optimized for binary readout to offer an equivalent spatial resolution to the one with an analogue readout. To understand the behavior as a function of simulation parameters, we developed analytical models that reproduce simulation results with a few parameters. The models can be used to optimize detector designs and operation conditions with regard to the spatial resolution.

  6. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  7. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  8. Design and optimization of the readout system for X-ray CCDs

    Institute of Scientific and Technical Information of China (English)

    LU Bo; HAN Da-Wei; LI Mao-Shun; YANG Yan-Ji; WANG Juan; CHEN Tian-Xiang; HU Wei; LI Cheng-Kui; LIU Xiao-Yan; CUI Wei-Wei; WANG Yu-Sa; ZHU Yue; ZHANG Yi; XU Yu-Peng; CHEN Yong; HUO Jia; LI Wei

    2012-01-01

    A readout system for X-ray CCDs based on an improved architecture is presented; by optimizing several critical circuit blocks along the analog signal chain,the conflict between the readout speed and readout noise is greatly alleviated.Using CCD47-10 as its target CCD,the readout system has achieved 8.6e- readout noise and 142 eV FWHM at 5.9 keV Mn Kα under a pixel rate of 80 kHz.Also its performance of imaging has been investigated.

  9. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  10. The analog front-end section of the BaBar silicon vertex tracker readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Manfredi, P.F.; Leona, A.; Mandelli, E.; Re, V.; Svelto, F. [Pavia Univ. (Italy). Dipartimento di Elettronica]|[INFN, Sezione di Pavia, Via Bassi 6, 27100 Pavia (Italy); Kipnis, I.; Luo, L.; Momayezi, M.; Nyman, M.; Pedrali-Noy, M.; Roe, N. [E.O. Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    1998-02-01

    This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip. (orig.). 6 refs.

  11. Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

    Science.gov (United States)

    Kleczek, Rafal

    2016-12-01

    The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

  12. Radiation hardness by design for mixed signal infrared readout circuit applications

    Science.gov (United States)

    Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

    2013-09-01

    Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

  13. Approach to the design of monitoring buffer for read-out ASICs

    Science.gov (United States)

    Atkin, E. V.; Vinogradov, S. M.

    2017-01-01

    The paper describes the approach to designing built-in monitoring buffers for the purpose of checking the functionality of ASICs as parts of test printed boards. A figure of merit (FOM), based on that analysis is suggested. Features of the FOM, applied to particle physics experiments, are the speed, power consumption, load driving capability and occupied chip area. As an example, illustrating the choice of buffer according to the proposed FOM, there are presented the results of designing a buffer version as part of an ASIC for the CBM MUCH(http://www.fair-center.eu/for-users/experiments/cbm.html).

  14. Readout scheme for the Baby-MIND detector

    CERN Document Server

    Noah, Etam; Cadoux, F; Favre, Y; Martinez, B; Nicola, L; Parsa, S; Rayner, M; Antonova, M; Fedotov, S; Izmaylov, A; Kleymenova, A; Khabibullin, M; Khotyantsev, A; Kudenko, Y; Likhacheva, V; Mefodiev, A; Mineev, O; Ovsiannikova, T; Shaykhiev, A; Suvorov, S; Yershov, N; Tsenov, R

    2016-01-01

    A readout scheme has been designed for the plastic scintillator bars of the Baby-MIND detector modules. This spectrometer will measure momentum and identify the charge of 1 GeV/c muons with magnetized iron plates interleaved with detector modules. One challenge the detector aims to address is that of keeping high charge identification efficiencies for momenta below 1 GeV/c where multiple scattering in the iron plates degrades momentum resolution. A front-end board has been developed, with 3 CITIROC readout chips per board and up to 96 channels. Hamamatsu MPPCs type S12571-025C photosensors were chosen for readout of wavelength shifting fibers embedded in plastic scintillators. Procurement of the MPPCs has been carried out to instrument 3000 channels in total. Design choices and first results of this readout scheme are presented.

  15. Noiseless, kilohertz-frame-rate, imaging detector based on micro-channel plates readout with the Medipix2 CMOS pixel chip

    CERN Document Server

    McPhate, J; Tremsin, A; Siegmund, O; Mikulec, Bettina; Clark, Allan G; CERN. Geneva

    2005-01-01

    A new hybrid imaging detector is described that is being developed for the next generation adaptive optics (AO) wavefront sensors. The detector consists of proximity focused microchannel plates (MCPs) read out by pixelated CMOS application specific integrated circuit (ASIC) chips developed at CERN ("Medipix2"). Each Medipix2 pixel has an amplifier, lower and upper charge discriminators, and a 14-bit chounter. The 256x256 array can be read out noiselessly (photon counting) in 286 us. The Medipix2 is buttable on 3 sides to produce 512x(n*256) pixel devices. The readout can be electronically shuttered down to a terporal window of a few microseconds with an accuracy of 10 ns. Good quantum efficiencies can be achieved from the x-ray (open faced with opaque photocathodes) to the optical (sealed tube with multialkali or GaAs photocathode).

  16. Flow control in microfluidic chips : Material choice and smart design

    NARCIS (Netherlands)

    Debrauwer, P.; Emmelkamp, J.; Bolt, P.J.

    2009-01-01

    This paper describes a model and experiments to validate it for the design of bubble free chambers and channels in microfluidic chips. When handling liquids in a microfluidic chip problems may arise with entrapping air or liquid. These air and liquid bubbles deteriorate the efficiency of the process

  17. Development and Test of a High Performance Multi Channel Readout System on a Chip with Application in PET/MR

    OpenAIRE

    2014-01-01

    The availability of new, compact, magnetic field tolerant sensors suitable for PET has opened the opportunity to build highly integrated PET scanners that can be included in commercial MR scanners. This combination has long been expected to have big advantages over existing systems combining PET and CT. This thesis describes my work towards building a highly integrated readout ASIC for application in PET/MR within the framework of the HYPERImage and SUBLIMA projects. It also gives a brief ...

  18. The Retinal Readout System: a status report A Status Report

    CERN Document Server

    Litke, A M

    1999-01-01

    The 'Retinal Readout System' is being developed to study the language the eye uses to send information about the visual world to the brain. Its architecture is based on that of silicon microstrip detectors. An array of 512 microscopic electrodes picks up the signals generated by the output neurons of live retinal tissue in response to a dynamic image focused on the input neurons. These signals are amplified, filtered and multiplexed by a set of eight custom-designed VLSI readout chips, and digitized and recorded by a data acquisition system. This report describes the goals, design, and status of the system. (author)

  19. System design for precise digitization and readout of the CSNS-WNS BaF2 spectrometer

    Science.gov (United States)

    Zhang, De-Liang; Cao, Ping; Wang, Qi; He, Bing; Zhang, Ya-Xi; Qi, Xin-Cheng; Yu, Tao; An, Qi

    2017-02-01

    The BaF2 (barium fluoride) spectrometer is one of the experiment facilities at the CSNS-WNS (White Neutron Source at China Spallation Neutron Source), currently under construction. It is designed to precisely measure the (n, γ) cross section, with 92 crystal elements and complete 4π steradian coverage. In order to improve the precision of measurement, in this paper, a new precise digitization and readout method is proposed. Waveform digitizing with 1 GSps sampling rate and 12-bit resolution is used to precisely capture the detector signal. To solve the problem of massive data readout and processing, the readout electronics is designed as a distributed architecture with 4 PXIe crates. The digitized signal is concentrated to the PXIe crate controller through a PCIe bus on the backplane and transmitted to the data acquisition system over gigabit Ethernet in parallel. Besides, the clock and trigger can be fanned out synchronously to every electronic channel over a high-precision distribution network. Test results show that the prototype of the readout electronics can achieve good performance and meet the requirements of the CSNS-WNS BaF2 spectrometer. Supported by National Research and Development plan (2016YFA0401602) and NSAF (U1530111)

  20. On-Chip Network Design Automation with Source Routing Switches

    Institute of Scientific and Technical Information of China (English)

    MA Liwei; SUN Yihe

    2007-01-01

    Network-on-chip (NoC) is a new design paradigm for system-on-chip intraconnections in the billion-transistor era. Application specific on-chip network design is essential for NoC success in this new era.This paper presents a class of source routing switch that can be used to efficiently form arbitrary network topologies and that can be optimized for various applications. Hardware description language versions of the networks can be generated automatically for simulations and for syntheses. A series of switches and networks has been configured with their performances including latency, delay, area, and power, and analyzed theoretically and experimentally. The results show that this NoC architecture provides a large design space for application specific on-chip network designs.

  1. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  2. Implementation of the Timepix ASIC in the Scalable Readout System

    Science.gov (United States)

    Lupberger, M.; Desch, K.; Kaminski, J.

    2016-09-01

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  3. Fluoroscopic x-ray demonstrator using a CdTe polycrystalline layer coupled to a CMOS readout chip

    Science.gov (United States)

    Arques, M.; Renet, S.; Brambilla, A.; Feuillet, G.; Gasse, A.; Billon-Pierron, N.; Jolliot, M.; Mathieu, L.; Rohr, P.

    2010-04-01

    Dynamic X-ray imagers require large surface, fast and highly sensitive X-ray absorbers and dedicated readout electronics. Monocrystalline photoconductors offer the sensitivity, speed, and MTF performances. Polycristalline photoconductors offer the large surface at a moderate cost. The challenge for them is to maintain the first performances at a compatible level with the medical applications requirements. This work has been focused on polycristalline CdTe grown by Close Space Sublimation (CSS) technique. This technique offers the possibility to grow large layers with a high material evaporation yield. This paper presents the results obtained with an image demonstrator using 350μm thick CdTe_css layers coupled to a CMOS readout circuit with Indium bumping. The present demonstrator has 200 x 200 pixels, with a pixel pitch of 75μm ×75μm. A total image surface of 15mm × 15mm has then been obtained. The ASIC works in an integration mode, i.e. each pixel accumulates the charges coming from the CdTe layer on a capacitor, converting them to a voltage. Single images as well as video sequences have been obtained. X-ray performance at 16 frames per second rate is measured. In particular a readout noise of 0.5 X ray, an MTF of 50% at 4 lp/mm and a DQE of 20% at 4lp/mm and 600 nGy are obtained. Although present demonstrator surface is moderate, it demonstrates that high performance can be expected from this assembly concept and its interest for medical applications.

  4. Chip-Level Design for Digital Microfluidic Biochips

    Directory of Open Access Journals (Sweden)

    Shang Tsung Yu

    2014-11-01

    Full Text Available Recently, electrowetting-on-dielectric (EWOD chips have become the most popular actuator for droplet-based digital microfluidic biochips (DMFBs due to its high throughput, automatic control, and low cost. As the complexity of biochemical assays increases, powerful computer-aided-design (CAD tools are needed. This paper provides an overview of DMFBs and describes some important issues and problems in the chip-level design of DMFBs.

  5. Development of a novel pixel-level signal processing chain for fast readout 3D integrated CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Y.; Torheim, O.; Hu-Guo, C. [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France); Degerli, Y. [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France); Hu, Y., E-mail: yann.hu@iphc.cnrs.fr [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France)

    2013-03-11

    In order to resolve the inherent readout speed limitation of traditional 2D CMOS pixel sensors, operated in rolling shutter readout, a parallel readout architecture has been developed by taking advantage of 3D integration technologies. Since the rows of the pixel array are zero-suppressed simultaneously instead of sequentially, a frame readout time of a few microseconds is expected for coping with high hit rates foreseen in future collider experiments. In order to demonstrate the pixel readout functionality of such a pixel sensor, a 2D proof-of-concept chip including a novel pixel-level signal processing chain was designed and fabricated in a 0.13μm CMOS technology. The functionalities of this chip have been verified through experimental characterization.

  6. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  7. Study and simulation of the read-out electronics design for a high-resolution plastic scintillating fiber based hodoscope

    Energy Technology Data Exchange (ETDEWEB)

    Blasco, José María, E-mail: jose.maria.blasco@uv.es [Universitat de València, Calle Gascó Oliag n" o5, 46010, Valencia (Spain); Sanchis, E. [Universitat de València, Calle Gascó Oliag n" o5, 46010, Valencia (Spain); Granero, D. [Eresa Grupo Médico (Spain); Martín, J.D.; González, V.; Sanchis-Sánchez, E. [Universitat de València, Calle Gascó Oliag n" o5, 46010, Valencia (Spain)

    2015-06-01

    Highlights: • Plastic Scintillating Fibers for high-resolution hodoscopy. • Silicon photodiode read-out electronics design. • Plastic scintillating fibers coupled to Silicon photodiodes read-out. • Charged particle detection with plastic scintillating fibers. - Abstract: This work presents the study and simulation of a high-resolution charged particle detection device for beam positioning, monitoring and calibration, together with its read-out proposal. To provide the precise positional information of the beam, the detection system has been based on Plastic Scintillating Fibers (PSF), while the read-out on a Silicon-PhotoDiode (Si-PD) array. To carry out the study, a PSF prototype with one detection plane has been experimentally tested with a β particle source. Besides, Monte Carlo simulations of the complete system have also been conducted. Both simulations and experimental tests give consistency to the results obtained. The work presented in this article show the usefulness of this proposal for high-precision charged particle positioning, achieving resolutions up to 100 µm.

  8. Design of the Readout Electronics for the Qualification Model of DAMPE BGO Calorimeter

    CERN Document Server

    Feng, Changqing; Zhang, Junbin; Gao, Shanshan; Yang, Di; Zhang, Yunlong; Liu, Shubin; An, Qi

    2014-01-01

    The DAMPE (DArk Matter Particle Explorer) is a scientific satellite being developed in China, aimed at cosmic ray study, gamma ray astronomy, and searching for the clue of dark matter particles, with a planned mission period of more than 3 years and an orbit altitude of about 500 km. The BGO Calorimeter, which consists of 308 BGO (Bismuth Germanate Oxid) crystal bars, 616 PMTs (photomultiplier tubes) and 1848 dynode signals, has approximately 32 radiation lengths. It is a crucial sub-detector of the DAMPE payload, with the functions of precisely measuring the energy of cosmic particles from 5 GeV to 10TeV, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information for the whole DAMPE payload. The dynamic range for a single BGO crystal is about 2?105 and there are 1848 detector signals in total. To build such an instrument in space, the major design challenges for the readout electronics come from the large dynamic range, the high integrity inside the very compa...

  9. Design and characterization of the PREC (Prototype Readout Electronics for Counting particles)

    Science.gov (United States)

    Assis, P.; Brogueira, P.; Ferreira, M.; Luz, R.; Mendes, L.

    2016-08-01

    The design, tests and performance of a novel, low noise, acquisition system—the PREC (Prototype Readout Electronics for Counting particles) is presented in this article. PREC is a system developed using discrete electronics for particle counting applications using RPCs (Resistive Plate Chamber) detectors. PREC can, however, be used with other kind of detectors that present fast pulses, e.g. Silicon Photomultipliers. The PREC system consists in several Front-End boards that transmit data to a purely digital Motherboard. The amplification and discrimination of the signal is performed in the Front-End boards, making them the critical component of the system. In this paper, the Front-End was tested extensively by measuring the gain, noise level, crosstalk, trigger efficiency, propagation time and power consumption. The gain shows a decrease with the working temperature and an increase with the power supply voltage. The Front-End board shows a low noise level (Motherboard is estimated to be 5.82 ns. The maximum power consumption is 3.372 W for the Motherboard and 3.576 W and 1.443 W for each Front-End analogue circuitry and digital part, respectively.

  10. The Drift Chamber Electronics and Readout for the NA48 Experiment

    CERN Document Server

    Augustin, I; Holder, M; Kreutz, A; Otto, W; Roschangar, M; Schöfer, B; Schwarze, I; Ziolkowski, M

    1998-01-01

    A drift chamber readout system for about 8000 channels with continuous sensitivity, i.e. concurrent data recording and readout, is described. Drift times are measured in bins of 1.56 ns with respect to a continuously running 40 MHz clock. The clock interval of 25 ns is divided into 16 bins by means of a 16 element delay chain. The length of this chain is linked to the clock interval by a phase locked loop. An ASIC chip was developed to perform time measurements and data storage for 16 channels. In an asynchronous readout of this chip, data are tranferred to intermediate buffers, for use in a first level trigger and eventual final readout. The design of the electronics is described and results from data taking runs are presented.

  11. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  12. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  13. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  14. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  15. PS-Module prototypes with MPA-light readout chip for the CMS Tracker Phase 2 Upgrade

    CERN Document Server

    Grossmann, Johannes

    2016-01-01

    During the HL-LHC era an instantaneous luminosity of $5\\times10^{34}\\,\\mathrm{cm}^{-2}\\mathrm{s}^{-1}$ will be reached and possibly $3000\\mskip3mu\\mathrm{fb} ^{-1}$ integrated luminosity will be delivered. This results in the requirement for a major upgrade of the CMS Outer Tracker detector. This contribution briefly reviews the module types and the front end readout electronics foreseen in the preparation program known as phase 2 upgrade. R\\&D towards the construction of full module prototypes for the Pixel-Strip (PS) module is ongoing. The module combines a macro-pixel sensor and a strip sensor and has $p_{\\mathrm{T}}\\,$-discrimination capability at module level. The current experience from module construction with a demonstrator assembly and initial laboratory testing with an alternative module concept for the PS-module is shown. A possible calibration method is introduced.

  16. PS-module prototypes with MPA-light readout chip for the CMS Tracker Phase 2 Upgrade

    Science.gov (United States)

    Grossmann, J.

    2017-02-01

    During the HL-LHC era an instantaneous luminosity of 5×1034 cm‑2s‑1 will be reached and possibly 3000 fb‑1 integrated luminosity will be delivered. This results in the requirement for a major upgrade of the CMS Outer Tracker detector. This contribution briefly reviews the module types and the front end readout electronics foreseen in the preparation program known as phase 2 upgrade. R&D towards the construction of full module prototypes for the Pixel-Strip (PS) module is ongoing. The module combines a macro-pixel sensor and a strip sensor and has pT -discrimination capability at module level. The current experience from module construction with a demonstrator assembly and initial laboratory testing with an alternative module concept for the PS-module is shown. A possible calibration method is introduced.

  17. Analysis and Implementation of Traffic Buffering in EOS Chip Design

    Institute of Scientific and Technical Information of China (English)

    FENG Bo; LIU Hao; YIN Yan-fen

    2005-01-01

    The traffic buffering problems in the ethernet over synchronous digital hierarchy(EOS) are introduced and analyzed. Different solutionsare also presented in detail. Synchronous DRAM(SDRAM) is used as off-chip buffer to store-and-retransmission ethernet frames. A new and easy control design is introduced here. The buffer area size on chip is greatly reduced and the power dissipation is lowed at the same time.

  18. Development of an ASIC for CCD readout at the vertex detectors of the intrenational linear collider

    CERN Document Server

    Murray, P; Stefanov, K D; Woolliscroft, T

    2007-01-01

    The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit flash ADC, data sparsification logic for identification of significant data clusters, and local memory for storage of data awaiting readout. CPR2 also has hierarchical 2-level data multiplexing and intermediate data memory, enabling readout of the sparsified data via the 5-bit data output bus.

  19. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  20. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  1. Design and performance testing of the read-out boards for the CMS-DT chambers

    CERN Document Server

    Fernández, C; Marin, J; Oller, J C; Willmott, C

    2002-01-01

    Read-out boards (ROB) are one of the key elements of readout system for CMS barrel muon drift chambers. To insure proper and reliable operation under all detector environmental conditions an exhaustive set of tests have been developed and performed on the 30 pre-series ROB's before production starts. These tests include operation under CMS radiation conditions to detect and estimate SEU rates, validation with real chamber signals and trigger rates, studies of time resolution and linearity, crosstalk analysis, track pattern generation for calibration and on-line tests, and temperature cycling to uncover marginal conditions. We present the status of the ROB and tests results. (5 refs).

  2. Development and characterization of high-resolution neutron pixel detectors based on Timepix read-out chips

    Science.gov (United States)

    Krejci, F.; Zemlicka, J.; Jakubek, J.; Dudak, J.; Vavrik, D.; Köster, U.; Atkins, D.; Kaestner, A.; Soltes, J.; Viererbl, L.; Vacik, J.; Tomandl, I.

    2016-12-01

    Using a suitable isotope such as 6Li and 10B semiconductor hybrid pixel detectors can be successfully adapted for position sensitive detection of thermal and cold neutrons via conversion into energetic light ions. The adapted devices then typically provides spatial resolution at the level comparable to the pixel pitch (55 μm) and sensitive area of about few cm2. In this contribution, we describe further progress in neutron imaging performance based on the development of a large-area hybrid pixel detector providing practically continuous neutron sensitive area of 71 × 57 mm2. The measurements characterising the detector performance at the cold neutron imaging instrument ICON at PSI and high-flux imaging beam-line Neutrograph at ILL are presented. At both facilities, high-resolution high-contrast neutron radiography with the newly developed detector has been successfully applied for objects which imaging were previously difficult with hybrid pixel technology (such as various composite materials, objects of cultural heritage etc.). Further, a significant improvement in the spatial resolution of neutron radiography with hybrid semiconductor pixel detector based on the fast read-out Timepix-based detector is presented. The system is equipped with a thin planar 6LiF convertor operated effectively in the event-by-event mode enabling position sensitive detection with spatial resolution better than 10 μm.

  3. Hamiltonian design in readout from room-temperature Raman atomic memory.

    Science.gov (United States)

    Dąbrowski, Michał; Chrapkiewicz, Radosław; Wasilewski, Wojciech

    2014-10-20

    We present an experimental demonstration of the Hamiltonian manipulation in light-atom interface in Raman-type warm rubidium-87 vapor atomic memory. By adjusting the detuning of the driving beam we varied the relative contributions of the Stokes and anti-Stokes scattering to the process of four-wave mixing which reads out a spatially multimode state of atomic memory. We measured the temporal evolution of the readout fields and the spatial intensity correlations between write-in and readout as a function of detuning with the use of an intensified camera. The correlation maps enabled us to resolve between the anti-Stokes and the Stokes scattering and to quantify their contributions. Our experimental results agree quantitatively with a simple, plane-wave theoretical model we provide. They allow for a simple interpretation of the coaction of the anti-Stokes and the Stokes scattering at the readout stage. The Stokes contribution yields additional, adjustable gain at the readout stage, albeit with inevitable extra noise. Here we provide a simple and useful framework to trace it and the results can be utilized in the existing atomic memories setups. Furthermore, the shown Hamiltonian manipulation offers a broad range of atom-light interfaces readily applicable in current and future quantum protocols with atomic ensembles.

  4. PERFORMANCE ENHANCED ROUTER DESIGN FOR NETWORK ON CHIP

    Directory of Open Access Journals (Sweden)

    Anbu chozhan.P

    2013-04-01

    Full Text Available Network on chip is a new paradigm for on chip design that is able to sustain the communication provisions for the SoC with the desired performance. NOC applies networking methodology concepts to system on chip data transfer and it gives noticeable elevation over conventionalbus based communication. NOC router is the backbone of on chip communication which directs the flow of data. In NOC router the arbiter is used during number of inputs request for the similar out port. Arbiter generates the grant based on the priority and previous granted input. For NOC router we have design the efficient round robin arbiter and analyse the power and area. In this paper on chip router is designed with a buffering technique of FWFT based asynchronous FIFO which improves timing and reduce power consumption. The proposed design of router is simulated and synthesized in Xilinx ISE 13.2 and the source code is written in Verilog. Cadence soc encounter of technology ami035 is used to generate layout of router and RTL compiler is used to compute area, power and timing.

  5. Radiation hardening of low-noise readout integrated circuit for infrared focal plane arrays

    Science.gov (United States)

    Lee, Min Su; Lee, Yong Soo; Lee, Hee Chul

    2010-04-01

    A radiation-resistant readout integrated circuit for focal plane arrays was studied to improve the reliability of infrared image systems operating in a radioactive environment, such as in space or in the surroundings of a nuclear reactor. First, as radiation-hardened NMOSFET structure, which includes a layout modification technique, was proposed. The readout integrated circuit for infrared focal plane arrays was then designed on basis of the proposed NMOSFET layout. Commercial 0.35 um process technology was used to fabricate the proposed unit NMOSFET and the designed readout integrated circuit which is based on the proposed NMOSFET. The measured electrical characteristics of the fabricated unit NMOSFET and readout integrated circuit are in good agreement with the simulated results. For verification of the radiation tolerance, the fabricated chip was exposed to 1 Mrad (Si) of gamma radiation, which is high enough to guarantee reliable usage in space or in a very harsh radiation environment. While exposed to gamma radiation, the fabricated chip was connected to a power supply (3.3 V) for testing under the worst conditions. After being exposed to 1 Mrad of gamma radiation, the unit NMOSFET showed only a slight increment of a few picoamperes in the leakage current, and the designed readout integrated circuit showed little change at an output voltage of less than 10% of a proper output voltage. The changes in the characteristics of the unit NMOSFET and the designed readout infrared integrated circuit are at an allowable level in relation to process variation.

  6. Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Qin, Jia-Jun; Yang, Yun-Fan; Yu, Li; Liang, Yu; Liu, Shu-Bin; An, Qi

    2016-11-01

    High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register (SAR) architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and asynchronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA. Supported by Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), CAS Center for Excellence in Particle Physics (CCEPP)

  7. Design, construction, quality checks and test results of first resistive-Micromegas read-out boards for the ATLAS experiment

    CERN Document Server

    Iengo, Paolo; The ATLAS collaboration

    2015-01-01

    The development work carried out at CERN to push the Micromegas technology to a new frontier is now coming to an end. The construction of the first read-out boards for the upgrade of the ATLAS muon system will demonstrate in full-scale the feasibility of this ambitious project. The read-out boards, representing the heart of the detector, are manufactured in industries, making the Micromegas for ATLAS the first MPGD for a large experiment with a relevant part industrially produced. The boards are 50 cm wide and up to 220 cm long, carrying copper strips 315 μm wide with 415 μm pitch. Interconnected resistive strips, having the same pattern as the copper strips, provide spark protection. The boards are completed by the creation of cylindrical pillars 128 μm high, 280 μm in diameter and arranged in a triangular array 7 mm aside. The total number of boards to be produced for ATLAS is 2048 of 32 different types. We will review the main design parameters of the read-out boards for the ATLAS Micromegas, following...

  8. Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

    Science.gov (United States)

    Liu, Wei; Wei, Tingcun; Li, Bo; Guo, Panjie; Hu, Yongcai

    2015-06-01

    A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um2.

  9. Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Wei, E-mail: liouwei930@sina.com [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun; Li, Bo; Guo, Panjie [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

    2015-06-21

    A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um{sup 2}.

  10. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Science.gov (United States)

    Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

    2014-01-01

    This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

  11. The Design, Fabrication and Characterization of a Transparent Atom Chip

    Directory of Open Access Journals (Sweden)

    Ho-Chiao Chuang

    2014-06-01

    Full Text Available This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments.

  12. Design and Simulation of Lab-on-a-Chip Devices

    DEFF Research Database (Denmark)

    Dimaki, Maria; Okkels, Fridolin

    2015-01-01

    Microfluidic channels are an essential part of any lab-on-a-chip system. They usually perform various functions, such as transporting liquids from A to B or mixing or separating liquids. As production costs for such systems are not insignificant, it is essential that the systems are designed...

  13. Design of an Enterobacteriaceae Pan-genome Microarray Chip

    DEFF Research Database (Denmark)

    Lukjancenko, Oksana; Ussery, David

    2010-01-01

    -density microarray chip has been designed, using 116 Enterobacteriaceae genome sequences, taking into account the enteric pan-genome. Probes for the microarray were checked in silico and performance of the chip, based on experimental strains from four different genera, demonstrate a relatively high ability...... to distinguish those strains on genus, species, and pathotype/serovar levels. Additionally, the microarray performed well when investigating which genes were found in a given strain of interest. The Enterobacteriaceae pan-genome microarray, based on 116 genomes, provides a valuable tool for determination...

  14. Time resolution of a photomultiplier readout system for space application

    CERN Document Server

    Commichau, Sebastian Caspar; Capell, M; Commichau, Volker; Flügge, G; Hangarter, K; Lebedev, A; Mnich, J; Röser, U; Viertel, G M; Von Gunten, H P

    2004-01-01

    The performance of a readout system for the synchrotron radiation detector (SRD) is studied. The detector is proposed as part of the Alpha Magnetic Spectrometer experiment, an experiment to fly on the International Space Station (ISS) beginning of 2005. The SRD is designed to detect the synchrotron radiation from electrons and positrons (TeV energy range) produced in the earth's magnetic field. For the planned array of scintillators and photomultipliers a readout system is chosen, which is compact, space qualified and has a low- power consumption. The low-power chip APV, originally designed for the CMS experiment at LHC (CERN), is foreseen for the readout. To overcome the diffuse background from photons and charged particles the SRD readout must have a time resolution better than 10 ns. The intrinsic time resolution (sigma from Gauss fit) of the APV25-S0 was found to be 0.46 +or- 0.01 and 0.68 +or-0.02 ns for the APVM. whereas the time resolution of the photomultiplier-APV readout system was measured to be 2....

  15. Multiprocessor systems on chip design space exploration

    CERN Document Server

    Kempf, Torsten; Leupers, Rainer

    2011-01-01

    This comprehensive introduction to the design challenges of MPSoC platforms focuses on early space exploration and defines an iterative methodology to increase the abstraction level, enabling the evaluation of design decisions earlier in the design process.

  16. Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

    Science.gov (United States)

    Demaria, N.; Barbero, M. B.; Fougeron, D.; Gensolen, F.; Godiot, S.; Menouni, M.; Pangaud, P.; Rozanov, A.; Wang, A.; Bomben, M.; Calderini, G.; Crescioli, F.; Le Dortz, O.; Marchiori, G.; Dzahini, D.; Rarbi, F. E.; Gaglione, R.; Gonella, L.; Hemperek, T.; Huegging, F.; Karagounis, M.; Kishishita, T.; Krueger, H.; Rymaszewski, P.; Wermes, N.; Ciciriello, F.; Corsi, F.; Marzocca, C.; De Robertis, G.; Loddo, F.; Licciulli, F.; Andreazza, A.; Liberali, V.; Shojaii, S.; Stabile, A.; Bagatin, M.; Bisello, D.; Mattiazzo, S.; Ding, L.; Gerardin, S.; Giubilato, P.; Neviani, A.; Paccagnella, A.; Vogrig, D.; Wyss, J.; Bacchetta, N.; De Canio, F.; Gaioni, L.; Nodari, B.; Manghisoni, M.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Vacchi, C.; Beccherle, R.; Bellazzini, R.; Magazzu, G.; Minuti, M.; Morsani, F.; Palla, F.; Poulios, S.; Fanucci, L.; Rizzi, A.; Saponara, S.; Androsov, K.; Bilei, G. M.; Menichelli, M.; Conti, E.; Marconi, S.; Passeri, D.; Placidi, P.; Della Casa, G.; Mazza, G.; Rivetti, A.; Da Rocha Rolo, M. D.; Monteil, E.; Pacher, L.; Gajanana, D.; Gromov, V.; Hessey, N.; Kluit, R.; Zivkovic, V.; Havranek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Kafka, V.; Sicho, P.; Vrba, V.; Vila, I.; Lopez-Morillo, E.; Aguirre, M. A.; Palomo, F. R.; Muñoz, F.; Abbaneo, D.; Christiansen, J.; Dannheim, D.; Dobos, D.; Linssen, L.; Pernegger, H.; Valerio, P.; Alipour Tehrani, N.; Bell, S.; Prydderch, M. L.; Thomas, S.; Christian, D. C.; Fahim, F.; Hoff, J.; Lipton, R.; Liu, T.; Zimmerman, T.; Garcia-Sciveres, M.; Gnani, D.; Mekkaoui, A.; Gorelov, I.; Hoeferkamp, M.; Seidel, S.; Toms, K.; De Witt, J. N.; Grillo, A.; Paternò, A.

    2016-12-01

    This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5-800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

  17. On-chip High-Voltage Generator Design

    CERN Document Server

    Tanzawa, Toru

    2013-01-01

    This book describes high-voltage generator design with switched-capacitor multiplier techniques.  The author provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.   ·         Shows readers how to design charge pump circuits with lower voltage operation, higher power efficiency, and smaller circuit area; ·         Describes comprehensive circuits and systems design of on-chip high-voltage generators; ·         Covers all the component circuit blocks, including charge pumps, pump regulators, level shifters, oscillators, and references.

  18. Development of hybrid photon detectors with integrated silicon pixel readout for the RICH counters of LHCb

    CERN Document Server

    Alemi, M; Formenti, F; Gys, Thierry; Piedigrossi, D; Puertolas, D; Rosso, E; Snoeys, W; Wyllie, Ken H

    1999-01-01

    We report on the ongoing work towards a hybrid photon detector with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment at the Large Hadron Collider at CERN. The photon detector is based $9 on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a fast, binary readout chip with matching pixel electronics. The $9 performance of a half-scale prototype is presented, together with the developments and tests of a full-scale tube with large active area. Specific requirements for pixel front-end and readout electronics in LHCb are outlined, and $9 recent results obtained from pixel chips applicable to hybrid photon detector design are summarized.

  19. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  20. RD Collaboration Proposal: Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Chistiansen, J (CERN)

    2013-01-01

    This proposal describes a new RD collaboration to develop the next genrration of hybrid pixel readout chips for use in ATLAS and CMS PHase 2 upgrades. extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. Challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm2 ), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. This collaboration is specifically focused on design of hybrid pixel readout chips, and not on more general chip design or on other aspects of hybrid pixel technology. Participants include 7 institutes on ATLAS and 7 on CMS, plus 2 on both experiments.

  1. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...

  2. An Infrared Readout Circuit with On-chip Compensation%一种具有片上补偿功能的红外读出电路

    Institute of Scientific and Technical Information of China (English)

    阙隆成; 吕坚; 魏林海; 周云; 蒋亚东

    2015-01-01

    针对非制冷红外探测器系统,提出了一种恒流偏置的红外读出电路(ROIC),该电路具有衬底温度补偿功能,且可实现片上偏移非均匀性补偿。基于微测辐射热计等效电阻受目标温度、衬底温度等影响的等效模型,每个读出通道采用两个盲电阻以消除衬底温度的影响,同时使用DAC逐点调节参考电压,以完成片上偏移非均匀性补偿。该ROIC 应用到阵列大小为320×240的非制冷微测辐射热计焦平面上,已在CSMC 05MIXDDST02的0.5m CMOS标准工艺下成功流试验片。电路测试结果表明:对于常温目标,当衬底温度变化60 K时,输出电压变化小于500 mV;经偏移非均匀性补偿后,阵列的固定图像噪声为11.8 mV。该ROIC适用于应用于复杂温度环境的高均匀性非制冷红外探测器。%This paper describes a constant current-biased readout circuit with substrate temperature compensation and non-uniformity compensation for the uncooled micro-bolometer detector. The influence of temperature for the equivalent resistance of micro-bolometer is evaluated. Then an effective way for substrate temperature compensation is proposed, which utilizes two blind micro-bolometers in each readout circuit channel. On the other hand, the non-uniformity compensation is also achieved by a 5bits on-chip DAC. A 320×240 uncooled micro-bolometer focal plane array(FPA)based on the proposed circuit was implemented on silicon by 0.5m CMOS technology. The measurement data show that the maximum difference of a normal temperature object over 60K substrate of which temperature change is only 500mV and the fixed pattern noise(FPN)is less than 11.8mV. Thus it is ideally suited for high performance production applications.

  3. Comparison of Detector Intrinsic Spatial Resolution Characteristics for Sensor on the Entrance Surface and Conventional Readout Designs.

    Science.gov (United States)

    Miyaoka, Robert S; Li, Xiaoli; Lockhart, Cate; Lewellen, Tom K

    2010-01-01

    We report on a high resolution, monolithic crystal PET detector design concept that provides depth of interaction (DOI) positioning within the crystal. Our design utilizes a novel sensor on the entrance surface (SES) approach combined with a maximum likelihood positioning algorithm. We compare the intrinsic spatial resolution characteristics (i.e., X, Y and Z) using our SES design versus conventional placement of the photo-sensors on the rear surface of the crystal. The sensors can be any two-dimensional array of solid state readout devices (e.g., silicon photomultipliers (SiPM) or avalanche photodiodes (APD)). SiPMs are a new type of solid-state photodetector with Geiger mode operation that can provide signal gain similar to a photomltipiler tube (PMT). Utilizing a multi-step simulation process, we determined the intrinsic spatial resolution characteristics for a variety of detector configurations. The SES design was evaluated via simulation for three different two-dimensional array sizes: 8×8 with 5.8×5.8 mm(2) pads; 12×12 with 3.8×3.8mm(2) pads; and 16×16 with 2.8×2.8 mm(2) pads. To reduce the number of signal channels row-column summing readout was used for the 12×12 and 16×16 channel array devices. The crystal was modeled as a 15 mm monolithic slab of a lutetium-based scintillator with the large area surface varying from 48.8×48.8 mm(2) up to 49.6×49.6 mm(2) depending upon the dimensions of the two-dimensional photo-sensor array. The intrinsic spatial resolution for the 8×8 array is 0.88 mm FWHM in X and Y, and 1.83 mm FWHM in Z (i.e., DOI). Comparing the results versus using a conventional design with the photo-sensors on the backside of the crystal, an average improvement of ~24% in X and Y and 20% in Z is achieved. The X, Y intrinsic spatial resolution improved to 0.67 mm and 0.64 mm FWHM for the 12×12 and 16×16 arrays using row-column readout. Using the 12×12 and 16×16 arrays also led to a slight improvement in the DOI positioning accuracy.

  4. Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signal

    CERN Document Server

    Liu, Jian-Feng; Qin, Jia-Jun; Yang, Yun-Fan; Yu, Li; Liang, Yu; Liu, Shu-Bin; An, Qi

    2016-01-01

    High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on power-efficient Successive Approximation Register (SAR) architecture, which incorporates the key parts such as Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and asynchronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are go...

  5. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    Science.gov (United States)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  6. Fast readout of the COMPASS RICH CsI-MWPC chambers

    CERN Document Server

    Abbon, P; Deschampbs, H; Kunne, F; Gerasimov, S; Ketzer, B; Konorov, I; Kravtchuk, N; Magnon, A; Neyret, D; Panebianco, S; Paul, S; Rebourgeard, P; Tessaroto, F

    2006-01-01

    A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with “slow” signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ∼3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5–6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficien...

  7. Fast readout of the COMPASS RICH CsI-MWPC photon chambers

    Science.gov (United States)

    Abbon, P.; Delagnes, E.; Deschamps, H.; Kunne, F.; Gerasimov, S.; Ketzer, B.; Konorov, I.; Kravtchuk, N.; Magnon, A.; Neyret, D.; Panebianco, S.; Paul, S.; Rebourgeard, P.; Tessaroto, F.

    2006-11-01

    A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with "slow" signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ˜3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5-6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficient data taking at higher trigger rate.

  8. Fast readout of the COMPASS RICH CsI-MWPC photon chambers

    Energy Technology Data Exchange (ETDEWEB)

    Abbon, P. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Delagnes, E. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Deschamps, H. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Kunne, F. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Gerasimov, S. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Ketzer, B. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Konorov, I. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Kravtchuk, N. [JINR Dubna, 141980 Dubna (Russian Federation); Magnon, A. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Neyret, D. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France)]. E-mail: damien.neyret@cern.ch; Panebianco, S. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Paul, S. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Rebourgeard, P. [DSM-DAPNIA, CEA Saclay, route de Saclay, F-91191 Gif-sur-Yvette (France); Tessaroto, F. [INFN, Sezione di Trieste and University of Trieste, Trieste (Italy)

    2006-11-01

    A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with 'slow' signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from {approx}3 {mu}s for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5-6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficient data taking at higher trigger rate.

  9. Optimal design of a spectral readout type planar waveguide-mode sensor with a monolithic structure.

    Science.gov (United States)

    Wang, Xiaomin; Fujimaki, Makoto; Kato, Takafumi; Nomura, Ken-Ichi; Awazu, Koichi; Ohki, Yoshimichi

    2011-10-10

    Optical planar waveguide-mode sensor is a promising candidate for highly sensitive biosensing techniques in fields such as protein adsorption, receptor-ligand interaction and surface bacteria adhesion. To make the waveguide-mode sensor system more realistic, a spectral readout type waveguide sensor is proposed to take advantage of its high speed, compactness and low cost. Based on our previously proposed monolithic waveguide-mode sensor composed of a SiO2 waveguide layer and a single crystalline Si layer [1], the mechanism for achieving high sensitivity is revealed by numerical simulations. The optimal achievable sensitivities for a series of waveguide structures are summarized in a contour map, and they are found to be better than those of previously reported angle-scan type waveguide sensors.

  10. Readout of two-kilopixel transition-edge sensor arrays for Advanced ACTPol

    CERN Document Server

    Henderson, Shawn W; Amiri, Mandana; Austermann, Jason; Beall, James A; Chaudhuri, Saptarshi; Cho, Hsiao-Mei; Choi, Steve K; Cothard, Nicholas F; Crowley, Kevin T; Duff, Shannon M; Fitzgerald, Colin P; Gallardo, Patricio A; Halpern, Mark; Hasselfield, Matthew; Hilton, Gene; Ho, Shuay-Pwu Patty; Hubmayr, Johannes; Irwin, Kent D; Koopman, Brian J; Li, Dale; Li, Yaqiong; McMahon, Jeff; Nati, Federico; Niemack, Michael D; Reintsema, Carl D; Salatino, Maria; Schillaci, Alessandro; Schmitt, Benjamin L; Simon, Sara M; Staggs, Suzanne T; Vavagiakis, Eve M; Ward, Jonathan T

    2016-01-01

    Advanced ACTPol is an instrument upgrade for the six-meter Atacama Cosmology Telescope (ACT) designed to measure the cosmic microwave background (CMB) temperature and polarization with arcminute-scale angular resolution. To achieve its science goals, Advanced ACTPol utilizes a larger readout multiplexing factor than any previous CMB experiment to measure detector arrays with approximately two thousand transition-edge sensor (TES) bolometers in each 150 mm detector wafer. We present the implementation and testing of the Advanced ACTPol time-division multiplexing readout architecture with a 64-row multiplexing factor. This includes testing of individual multichroic detector pixels and superconducting quantum interference device (SQUID) multiplexing chips as well as testing and optimizing of the integrated readout electronics. In particular, we describe the new automated multiplexing SQUID tuning procedure developed to select and optimize the thousands of SQUID parameters required to readout each Advanced ACTPol...

  11. XAMPS Detectors Readout ASIC for LCLS

    Energy Technology Data Exchange (ETDEWEB)

    Dragone, A; /SLAC; Pratte, J.F.; Rehak, P.; /Brookhaven; Carini, G.A.; /BNL, NSLS; Herbst, R.; /SLAC; O' Connor, P.; /Brookhaven; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  12. On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips

    CERN Document Server

    Goel, Sandeep Kumar

    2011-01-01

    Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.

  13. Microarchitecture of network-on-chip routers a designer's perspective

    CERN Document Server

    Dimitrakopoulos, Giorgos; Seitanidis, Ioannis

    2014-01-01

    This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a

  14. Design of the 65 nm CLICpix demonstrator chip

    CERN Document Server

    Valerio, P.; Campbell, M.

    2012-01-01

    A hybrid pixel detector ASIC designed to be used in the vertex detector for the CLIC experiment is presented in this note. It has been designed using a commercial 65 nm CMOS technology. The main features include simultaneous 4-bit TOT and TOA measurements with 10 ns accuracy, a spatial resolution of 3 um (the pixel size is 25x25 um), an on-chip data compression scheme and power pulsing capability. A prototype with a fully featured array of 64 by 64 pixels has been designed and produced. Testing on the prototype is ongoing.

  15. Power management design for lab-on-chip biosensors.

    Science.gov (United States)

    Xiaojian Yu; Moez, Kambiz; I-Chyn Wey; Jie Chen

    2016-08-01

    Over the past decades, we have witnessed the growth demands of portable lab-on-chip biosensors. These lab-on-chip devices are mostly powered by battery, and intelligent power management systems are required to provide supply voltage for different functional units on biosensors (e.g. a microfluidic control system might require higher voltage than the rest working units of biosensors). In this paper, a fully integrated multiple-stage voltage multiplier is proposed to provide high-voltage power needs. The proposed design was implemented with the IBM's 0.13um CMOS process with a maximum power efficiency of 81.02% and maximum voltage conversion efficiency of 99.8% under a supply voltage of 1.2 V.

  16. Planar ion chip design for scalable quantum information processing

    Institute of Scientific and Technical Information of China (English)

    Wan Jin-Yin; Wang Yu-Zhu; Liu Liang

    2008-01-01

    We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing.Qubits are formed from the internal electronic states of trapped 40Ca+ ions.The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately,a combination of appropriaterf and DC potentials is applied to them for stable ion confinement.Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations.The potential distributions are calculated by using a static electric field qualitatively.This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the axrays of trapped ions.

  17. Readout electronics development for the ATLAS silicon tracker

    Energy Technology Data Exchange (ETDEWEB)

    Borer, K. [Bern Univ. (Switzerland); Beringer, J. [Bern Univ. (Switzerland); Anghinolfi, F. [CERN, CH-1211 Geneva 23 (Switzerland); Aspell, P. [CERN, CH-1211 Geneva 23 (Switzerland); Chilingarov, A. [CERN, CH-1211 Geneva 23 (Switzerland)]|[Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Jarron, P. [CERN, CH-1211 Geneva 23 (Switzerland); Heijne, E.H.M. [CERN, CH-1211 Geneva 23 (Switzerland); Santiard, J.C. [CERN, CH-1211 Geneva 23 (Switzerland); Verweij, H. [CERN, CH-1211 Geneva 23 (Switzerland); Goessling, C. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Lisowski, B. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Reichold, A. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Bonino, R. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Clark, A.G. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Kambara, H. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); La Marra, D. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Leger, A. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Wu, X. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Richeux, J.P. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Taylor, G.N. [School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia); Fedotov, M. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Kuper, E. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Velikzhanin, Yu. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Campbell, D. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Murray, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Seller, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)

    1995-06-01

    We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints. (orig.).

  18. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  19. Production Quality Control Of Microfluidic Chip Designs

    DEFF Research Database (Denmark)

    Calaon, Matteo; Hansen, Hans Nørgaard; Tosello, Guido

    2012-01-01

    -beam lithography. Subsequent nickel electroplating was employed to replicate the obtained geometries on the tool, which was used to mold on transparent polymer substrates the functional structures. To assess the critical factors affecting the replication quality throughout the different steps of the proposed...... process chain, test geometries were designed and produced on the side of the functional features. The so called “Finger Print” of the lithography and molding processes was qualitatively and quantitatively evaluated through scanning electron microscopy and atomic force microscopy respectively. The entire...

  20. Production Quality Control Of Microfluidic Chip Designs

    DEFF Research Database (Denmark)

    Calaon, Matteo; Hansen, Hans Nørgaard; Tosello, Guido

    2012-01-01

    process chain, test geometries were designed and produced on the side of the functional features. The so called “Finger Print” of the lithography and molding processes was qualitatively and quantitatively evaluated through scanning electron microscopy and atomic force microscopy respectively. The entire......The challenge of fabricating geometries with critical dimensions ranging from few microns down to 10 nanometers with high production rate is delaying the development of nanotechnology based products. Diverse research works have shown the capability of technologies such as UV lithography, nano...... imprint lithography and e-beam lithography to produce micro and nano features. However, their application for tooling purposes is relatively new and the potential to produce nanometer features with high volume low cost production is enormous. Considering possible implementation in a mass production...

  1. ASIC Design and Implementation for Digital Pulse Compression Chip

    Institute of Scientific and Technical Information of China (English)

    高俊峰; 韩月秋; 王巍

    2004-01-01

    A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

  2. Test Of The CMS Microstrip Silicon Tracker Readout And Control

    CERN Document Server

    Zghiche, A; Civinini, C; Coughlan, J; Drouhin, F; Figueiredo, P; Fiore, L; Furtjes, A; Giassi, A; Gutleber, J; Ljuslin, C; Loreti, M; Maazouzi, C; Marchioro, A; Marinelli, N; Mattig, P M; Parthipan, T; Paillard, C; Siegrist, P; Silvestris, L; Tsirou, A; Verdini, P G; Walsham, P; Wittmer, B

    2000-01-01

    The Microstrip Silicon tracker of the CMS detector is designed to provide robust particle tracking and vertex reconstruction within a strong magnetic field in the high luminosity environment of the LHC. The Tracker readout system employs Front End Driver cards to digitize and buffer the analogue data arriving via optical links from on detector pipeline chips. The control Chain of the front-end electronic is built to operate via optical fibers in order to shield the communications from the outside noise. Components close to the final design have been assembled to be tested in the X5 beam area at CERN where a dedicated 25ns temporal structrure beam has been made available by the SPS. This paper describes the hardware and the software developed for readout and control of data acquired by the front-end electronics operating at 40 MHz. Some preliminary results of the tests performed in the 25ns beam are also given.

  3. Design and research for biosensing THz microfluidic chips

    Science.gov (United States)

    Fan, Ning; Su, Bo; Zhang, Cong; Zhang, Cunlin

    2016-11-01

    Many Biomolecules vibration frequencies are in terahertz (0.1THz-10THz) frequency range, so terahertz (THz) technology is an essential tool for detecting biological molecules. However, due to terahertz strongly absorbed by water, it is difficult to detect these molecules for biological and chemical liquid samples. Therefore, we present a novel detection method by combining terahertz technology with microfluidic technology. The strong absorption of water is effectively overcome by controlling the length that terahertz passes through liquid samples. What's more, a higher signal to noise ratio is obtained through using less samples. In this paper, we designed a THz microfluidic chip that is easy to be fabricated by using the materials of Zeonor and polydimethylsiloxane (PDMS). Using terahertz time-domainspectroscopy (THz-TDS) system, we find that the chip has a high transmittance above 80% in the range from 0.2 THz to 2.6 THz. Then the THz spectra of deionized water and different kinds of solutions with different concentrations in the microfluidic chip were measured, respectively. In our research, it is found that different kinds of solutions have different transmission coefficients for THz. In addition, the THz transmission and absorption spectrum changes with the concentration of the same kind of solution.

  4. Electronic readout system for the Belle II imaging Time-Of-Propagation detector

    Science.gov (United States)

    Kotchetkov, Dmitri

    2017-07-01

    The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

  5. Compact, Low-power and Precision Timing Photodetector Readout

    Energy Technology Data Exchange (ETDEWEB)

    Varner, Gary S.; Ruckman, Larry L.; /Hawaii U.; Schwiening, Jochen; Vavra, Jaroslav; /SLAC

    2011-06-14

    Photodetector readout for next generation high event rate particle identification and single-photon detection requires a digitizer capable of integrated recording of dense arrays of sensor elements with high analog bandwidth (precision timing) and large record depth, in a cost-effective, compact and low-power way. Simply stated, one cannot do better than having a high-fidelity 'oscilloscope on a chip' for every sensor channel. A firs version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the readout basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. To address this shortcoming, a prototype intended for photodetector readout has been designed and fabricated with 64k deep sampling at multi-GSa/s operation. An evaluation system has been constructed for instrumentation of Time-Of-Propagation (TOP) and focusing DIRC prototypes and test results will be reported.

  6. Design and characterization of an image acquisition system and its optomechanical module for chip defects inspection on chip sorters

    Science.gov (United States)

    Chen, Ming-Fu; Huang, Po-Hsuan; Chen, Yung-Hsiang; Cheng, Yu-Cheng

    2011-08-01

    Chip sorter is one of packaging facilities in chip manufactory. Defects will occur for a few of chips during manufacturing processes. If the size of chip defects is larger than a criterion of impacting chip quality, these flawed chips have to be detected and removed. Defects inspection system is usually developed with frame CCD imagers. There're some drawbacks for this system, such as mechanism of pause type for image acquisition, complicated acquisition control, easy damage for moving components, etc. And acquired images per chip have to be processed in radiometry and geometry and then pieced together before inspection. These processes impact the accuracy and efficiency of defects inspection. So approaches of image acquisition system and its opto-mechanical module will be critical for inspection system. In this article, design and characterization of a new image acquisition system and its opto-mechanical module are presented. Defects with size of greater than 15μm have to be inspected. Inspection performance shall be greater than 0.6 m/sec. Thus image acquisition system shall have the characteristics of having (1) the resolution of 5μm and 10μm for optical lens and linear CCD imager respectively; (2) the lens magnification of 2; (3) the line rate of greater than 120 kHz for imager output. The design of structure and outlines for new system and module are also described in this work. Proposed system has advantages of such as transporting chips in constant speed to acquire images, using one image only per chip for inspection, no image-mosaic process, simplifying the control of image acquisition. And the inspection efficiency and accuracy will be substantially improved.

  7. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    Science.gov (United States)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  8. Design, construction and performance tests of a prototype micromegas chamber with two readout planes in a common gas volume

    Science.gov (United States)

    Brickwedde, Bernard; Düdder, Andreas; Schott, Matthias; Yildirim, Eda

    2017-08-01

    In this paper, the design and the performance of a prototype detector based on MicroMegas technology with two detection planes in a common gas volume is discussed. The detector is suited for the forward region of LHC detectors, addressing the high-rate environment and limited available space. Each detection plane has an active area of 9 × 9cm2 with a two-dimensional strip readout and is separated by a common gas region with a height of 14 mm . A micro-mesh, working as a cathode, is placed in the middle of the common gas volume separating it into two individual cells. This setup allows for an angle reconstruction of incoming particles with a precision of ∼ 2 mrad. Since this design reduces the impact of multiple scattering effects by the reduced material budget, possible applications for low energy beam experiments can be envisioned. The performance of the prototype detector has been tested with a 4 . 4 GeV electron beam, provided by the test beam facility at DESY.

  9. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

    2017-05-01

    Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  10. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  11. SPIDR, a general-purpose readout system for pixel ASICs

    Science.gov (United States)

    van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

    2017-02-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

  12. Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

    CERN Document Server

    Backhaus, M

    2013-01-01

    The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3• 10^34 cm^−2 s ^−1with an integrated luminosity over the IBL lifetime of 300 fb^−1 corresponding to a design lifetime fluence of 5 • 10^15 n_eqcm^−2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these resu...

  13. A new analogue sampling readout system for the COMPASS RICH-1 detector

    Science.gov (United States)

    Abbon, P.; Dafni, T.; Delagnes, E.; Deschamps, H.; Gerassimov, S.; Ketzer, B.; Kolosov, V.; Konorov, I.; Kravtchuk, N.; Kunne, F.; Magnon, A.; Neyret, D.; Panebianco, S.; Paul, S.; Rebourgeard, P.

    2008-05-01

    A new electronic readout for CsI-coated multiwire proportional chambers (MWPC), used as photon detectors in the COMPASS ring imaging Cherenkov (RICH) detector, is described. A prototype system comprising more than 5000 channels has been built and tested in high-intensity beam conditions. It is based on the APV25-S1 analogue sampling chip, and replaces the GASSIPLEX chip readout used previously. The APV25 chip, although originally designed for Silicon microstrip detectors, is shown to perform well even with "slow" signals from an MWPC, maintaining a signal-to-noise ratio (SNR) of 9. For every trigger the system reads out three consecutive amplitudes in time, thus allowing to extract information on both the signal amplitude and its timing. This information is used to reduce pile-up events in a high-rate environment. Prototype tests of the new readout electronics on a central RICH photocathode in nominal COMPASS beam conditions showed that the effective time window is reduced from more than 3 μs for the GASSIPLEX to less than 400 ns for the APV25 chip. This leads to a significant improvement of the signal-to-background ratio (SBR) with respect to the original readout. A gain by a factor of 5-6 was experimentally verified in the very forward region of phase space, where pile-up due to the muon beam halo is most significant. Owing to its pipelined architecture, the new readout system also considerably reduces the dead time per event, thus allowing to make use of trigger rates exceeding 50 kHz.

  14. A new analogue sampling readout system for the COMPASS RICH-1 detector

    Energy Technology Data Exchange (ETDEWEB)

    Abbon, P.; Dafni, T.; Delagnes, E.; Deschamps, H. [CEA DSM-DAPNIA, Saclay, 91191 Gif-sur-Yvette (France); Gerassimov, S. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Ketzer, B. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany)], E-mail: Bernhard.Ketzer@cern.ch; Kolosov, V. [European Laboratory for Particle Physics CERN, 1211 Geneva 23 (Switzerland); Konorov, I. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Kravtchuk, N. [JINR Dubna, 141980 Dubna (Russian Federation); Kunne, F.; Magnon, A.; Neyret, D.; Panebianco, S. [CEA DSM-DAPNIA, Saclay, 91191 Gif-sur-Yvette (France); Paul, S. [Physik Department, Technische Universitaet Muenchen, D-85748 Garching (Germany); Rebourgeard, P. [CEA DSM-DAPNIA, Saclay, 91191 Gif-sur-Yvette (France)

    2008-05-15

    A new electronic readout for CsI-coated multiwire proportional chambers (MWPC), used as photon detectors in the COMPASS ring imaging Cherenkov (RICH) detector, is described. A prototype system comprising more than 5000 channels has been built and tested in high-intensity beam conditions. It is based on the APV25-S1 analogue sampling chip, and replaces the GASSIPLEX chip readout used previously. The APV25 chip, although originally designed for Silicon microstrip detectors, is shown to perform well even with 'slow' signals from an MWPC, maintaining a signal-to-noise ratio (SNR) of 9. For every trigger the system reads out three consecutive amplitudes in time, thus allowing to extract information on both the signal amplitude and its timing. This information is used to reduce pile-up events in a high-rate environment. Prototype tests of the new readout electronics on a central RICH photocathode in nominal COMPASS beam conditions showed that the effective time window is reduced from more than 3{mu}s for the GASSIPLEX to less than 400ns for the APV25 chip. This leads to a significant improvement of the signal-to-background ratio (SBR) with respect to the original readout. A gain by a factor of 5-6 was experimentally verified in the very forward region of phase space, where pile-up due to the muon beam halo is most significant. Owing to its pipelined architecture, the new readout system also considerably reduces the dead time per event, thus allowing to make use of trigger rates exceeding 50kHz.

  15. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Science.gov (United States)

    Fischer, P.; Comes, G.; Krüger, H.

    1999-07-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized.

  16. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Energy Technology Data Exchange (ETDEWEB)

    Fischer, P. E-mail: fischerp@physik.uni-bonn.de; Comes, G.; Krueger, H

    1999-07-11

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  17. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    CERN Document Server

    Fischer, P; Krüger, H

    1999-01-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  18. Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

    CERN Document Server

    Lee, MyeongJae; Chang, Jessica K; Ding, Dawei; Gnani, Dario; Grace, Carl R; Jones, John A; Kolomensky, Yury G; von der Lippe, Henrik; Mcvittie, Patrick J; Stettler, Matthew W; Walder, Jean-Pierre

    2015-01-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Po...

  19. Data encoding efficiency in pixel detector readout with charge information

    CERN Document Server

    Garcia-Sciveres, Maurice

    2016-01-01

    The minimum number of bits needed for lossless readout of a pixel detector is calculated, in the regime of interest for particle physics where only a small fraction of pixels have a non-zero value per frame. This permits a systematic comparison of the readout efficiency of different encoding implementations. The calculation is compared to the bits used for by the FE-I4 pixel readout chip of the ATLAS experiment.

  20. Data encoding efficiency in pixel detector readout with charge information

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, Maurice, E-mail: mgs@lbl.gov [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Wang, Xinkang [University of Chicago, Chicago, IL (United States)

    2016-04-11

    The average minimum number of bits needed for lossless readout of a pixel detector is calculated, in the regime of interest for particle physics where only a small fraction of pixels have a non-zero value per frame. This permits a systematic comparison of the readout efficiency of different encoding implementations. The calculation is compared to the number of bits used by the FE-I4 pixel readout chip of the ATLAS experiment.

  1. Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

    CERN Document Server

    INSPIRE-00218480

    2016-01-01

    The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

  2. Design of a GaAs X-ray imaging sensor with integrated HEMT readout circuitry

    CERN Document Server

    Boardman, D

    2002-01-01

    A new monolithic semi-insulating (SI) GaAs sensor design for X-ray imaging applications between 10-100keV has been proposed. Monolithic pixel detectors offer a number of advantages over hybrid bump-bonded detectors, such as high device yield, low costs and are easier to produce large scale arrays. In this thesis, an investigation is made of the use of a SI GaAs wafer as both a detector element and substrate for the epitaxially grown High Electron Mobility Transistors (HEMTs). The design of the HEMT transistors, optimised for this application, were produced with the aid of the Silvaco 'Virtual Wafer Fab' simulation package. It was determined that the device characteristics would consist of a small positive threshold voltage, a low off-state drain current and high transconductance. The final HEMT transistor design, that would be integrated to a pixel detector, had a threshold voltage of 0.17V, an off-state leakage current of approx 1nA and a transconductance of 7.4mS. A number of test detectors were characteris...

  3. NetList(+): A simple interface language for chip design

    Science.gov (United States)

    Wuu, Tzyh-Yung

    1991-04-01

    NetList (+) is a design specification language developed at MOSIS for rapid turn-around cell-based ASIC prototyping. By using NetList (+), a uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an interfacing methodology between design specification and independent computer aided design tools. Designers need only to specify a system by writing a corresponding netlist. This netlist is used for both functional simulation and timing simulation. The same netlist is also used to derive the low level physical tools to generate layout. Another goal of using NetList (+) is to generate parts of a design by running it through different kinds of placement and routing (P and R) tools. For example some parts of a design will be generated by standard cell P and R tools. Other parts may be generated by a layout tiler; i.e., datapath compiler, RAM/ROM generator, or PLA generator. Finally all different parts of a design can be integrated by general block P and R tools as a single chip. The NetList (+) language can actually act as an interface among tools. Section 2 shows a flowchart to illustrate the NetList (+) system and its relation with other related design tools. Section 3 shows how to write a NetList (+) description from the block diagram of a circuit. In section 4 discusses how to prepare a cell library or several cell libraries for a design system. Section 5 gives a few designs by NetList (+) and shows their simulation and layout results.

  4. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  5. Readout scheme of the upgraded ALICE TPC

    CERN Document Server

    Appelshaeuser, Harald; Ivanov, Marian; Lippmann, Christian; Wiechula, Jens

    2016-01-01

    In this document, we present the updated readout scheme for the ALICE TPC Upgrade. Two major design changes are implemented with respect to the concept that was presented in the TPC Upgrade Technical Design Report: – The SAMPA front-end ASIC will be used in direct readout mode. – The ADC sampling frequency will be reduced from 10 to 5 MHz. The main results from simulations and a description of the new readout scheme is outlined.

  6. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  7. Characterization of Silicon Photomultiplier Readout Designs for Use in Positron Emission Tomography Systems

    Science.gov (United States)

    Liu, Chen-Yi

    Geiger-mode avalanche photodiodes, or silicon photomultipliers, are promising light sensors for the next generation Positron Emission Tomography (PET) scanners. The sensor is being used in the scanner's gamma ray detector to measure scintillation light. This thesis describes the test results of three gamma ray detectors that utilize silicon photomultipliers. The first one is a commercial detector, and the other two are custom made. The detectors are tested for their 511 keV photon energy and timing resolution, as well as their ability to measure light from small scintillator crystals. The two custom made detectors had smaller active area, but outperformed the commercial detector in energy resolution. The introduction of buffer amplifiers improved the timing resolution of one detector. All three detectors had their crystal decoding ability limited by signal multiplexing and the sensor's dark noise. Finally, a detector design was proposed for the PET system being developed in our group.

  8. Readout electronics and test bench for the CMS Phase I pixel detector

    CERN Document Server

    Del Burgo, Riccardo

    2016-01-01

    The present CMS pixel detector will be replaced with an upgraded pixel system during the LHC extended technical stop in winter 2016/2017. The CMS Phase 1 pixel upgrade combines a new pixel readout chip, which minimizes detection inefficiencies, with several other design improvements to maintain the excellent tracking performance of CMS at the higher luminosity conditions foreseen for the coming years. The upgraded detector features new readout electronics which require detailed evaluation. For this purpose a test stand has been setup, including a slice of the CMS pixel DAQ system, all components of the upgraded readout chain together with a number of detector modules. The test stand allows for detailed evaluation and verification of all detector components, and is also crucial to develop tests and procedures to be used during the detector assembly and the commissioning and calibration of the detector. In this talk the system test and its functionalities will be described with a focus on the tests performed fo...

  9. Chip Design Process Optimization Based on Design Quality Assessment

    Science.gov (United States)

    Häusler, Stefan; Blaschke, Jana; Sebeke, Christian; Rosenstiel, Wolfgang; Hahn, Axel

    2010-06-01

    Nowadays, the managing of product development projects is increasingly challenging. Especially the IC design of ASICs with both analog and digital components (mixed-signal design) is becoming more and more complex, while the time-to-market window narrows at the same time. Still, high quality standards must be fulfilled. Projects and their status are becoming less transparent due to this complexity. This makes the planning and execution of projects rather difficult. Therefore, there is a need for efficient project control. A main challenge is the objective evaluation of the current development status. Are all requirements successfully verified? Are all intermediate goals achieved? Companies often develop special solutions that are not reusable in other projects. This makes the quality measurement process itself less efficient and produces too much overhead. The method proposed in this paper is a contribution to solve these issues. It is applied at a German design house for analog mixed-signal IC design. This paper presents the results of a case study and introduces an optimized project scheduling on the basis of quality assessment results.

  10. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  11. Optical microscope for nuclear emulsion readout: system design and results in application

    Science.gov (United States)

    Winkler, Kerstin; Koerner, Lienhard; Gussek, Peter; Balogh, Istvan; Breitfelder, Stefan; Schlichting, Johannes; Dupraz, Jean-Pierre; Fabre, Jean-Paul; Panman, Jaap; Papadopoulos, Ioannis M.; Zucchelli, Piero; van de Vyver, Bart

    1999-10-01

    Experiments such as CHORUS at CERN require the inspection of a large amount of nuclear emulsion plates exposed to particle beams. Rare events need to be found, measured and analyzed. Their features are stored as grains in microscopic dimensions in a 3D stack of plates. A new, fully automatic immersion microscope system was developed for this purpose. It features high resolution, small depth of focus, large working distance, large field of view and synchronization of illumination and detector. An additional requirement is given by variations in the refraction index and in the relative thickness of immersion oil and emulsion. The approach used here is an imaging system based on a various objective lens with extreme numerical aperture, large working distance and wide field, combined with a matched high-aperture Koehler illuminator. The light source is a mercury arc lamp, combined with a filter package for the g- line. It includes liquid crystal elements for synchronized shuttering and variable attenuation. The theoretical resolution is less than 1 micron in x, y, z within a volume of 0.5mm diameter times 1 mm scanning depth in all situations within a predefined index range. Three identical pieces of the system have been built. The identical pieces of the system have been built. The experimentally measured resolution confirms the expectations and is better than 1 micron in all three dimensions. This is the result of a complex process of system design and manufacturing, unifying optical, opto-mechanical and opto-electronical contributions. This process spans from the early stages of feasibility and manufacturing up to the test and adjustment procedures. The three prototypes are operational since the fall of 1998 in the frame of the CHORUS project. Practical experience and application results are presented.

  12. The read-out ASIC for the Space NUCLEON project

    Science.gov (United States)

    Atkin, E.; Voronin, A.; Karmanov, D.; Kudryashov, I.; Podorozhniy, D.; Shumikhin, V.

    2015-04-01

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1-40 000 mip) at low power consumption ( 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T&H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN.

  13. Design of a trigger layout and the corresponding implementation of a 200 GB/s readout network for the ALICE transition radiation detector; Entwicklung des Triggerkonzepts und die entsprechende Implementierung eines 200-GB/s-Auslesenetzwerks fuer den ALICE-Uebergangsstrahlungsdetektor

    Energy Technology Data Exchange (ETDEWEB)

    Schneider, Rolf

    2008-05-19

    Through the use of modern information technology, intelligent trigger systems are gaining more and more importance in high-energy physics. Particularly in heavy ion experiments, the large number of generated particles results in an enormous amount of data. By filtering the data at an early stage and discarding irrelevant events, the efficiency of the entire system can be raised significantly. The ALICE experiment at CERN breaks new ground in this respect. With the Transition Radiation Detector, the acquired signals are processed parallel right on the detector using more than 65 000 multi-chip modules. Via a readout network, the preprocessed data arrives at a global track reconstruction unit, which contributes to the decision whether an event is discarded or further processed. In this thesis, a trigger concept for the Transition Radiation Detector is developed and the readout network is implemented. A special challenge is to achieve an efficient interaction of the above processing stages. By means of simulations and analyses, the entire system is optimized in this regard. It turns out that the read-out process plays a decisive role. In this context, a design flow for the used ASIC is developed. The analyses show that through optimizations the extremely high demands made on this complex system can be met. During a beam time, first prototypes have successfully been tested. The entire system is currently being assembled and will be brought on line in 2008. (orig.)

  14. \\title{Test beam results of the first CMS\\\\double-sided strip module prototypes\\\\using the CBC2 read-out chip}

    CERN Document Server

    Harb, Ali; Hauk, Johannes

    2016-01-01

    In November 2013 the first 2S-$p_{T}$ module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2~to 4 GeV. In this paper the test setup and the results are presented.

  15. Multimedia Terminal System-on-Chip Design and Simulation

    Directory of Open Access Journals (Sweden)

    Barbieri Ivano

    2005-01-01

    Full Text Available This paper proposes a design approach based on integrated architectural and system-on-chip (SoC simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW digital signal processors (DSPs, the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

  16. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  17. The fast readout system for the MAPMTs of COMPASS RICH-1

    CERN Document Server

    Abbon, P; Angerer, H; Birsa, R; Bordalo, P; Bradamante, Franco; Bressan, A; Chiosso, M; Ciliberti, P; Colantoni, M L; Dafni, T; Dalla Torre, S; Delagnes, E; Denisov, O; Deschamps, H; Díaz, V; Dibiase, N; Duic, V; Eyrich, W; Ferrero, A; Finger, M; Finger, M Jr; Fischer, H; Gerassimov, S; Giorgi, M; Gobbo, B; Hagemann, R; Von Harrach, D; Heinsius, F H; Joosten, R; Ketzer, B; Kolosov, V N; Königsmann, K C; Konorov, I; Kramer, Daniel; Kunne, F; Lehmann, A; Levorato, S; Maggiora, A; Magnon, A; Mann, A; Martin, A; Menon, G; Mutter, A; Nähle, O; Nerling, F; Neyret, D; Panzieri, D; Paul, S; Pesaro, G; Pizzolotto, C; Polak, J; Rebourgeard, P; Robinet, F; Rocco, E; Schiavon, P; Schill, C; Schoenmeier, P; Schröder, W; Silva, L; Slunecka, M; Sozzi, F; Steiger, L; Sulc, M; Svec, M; Takekawa, S; Tessarotto, F; Teufel, A; Wollny, H

    2008-01-01

    A fast readout system for the upgrade of the COMPASS RICH detector has been developed and successfully used for data taking in 2006 and 2007. The new readout system for the multi-anode PMTs in the central part of the photon detector of the RICH is based on the high-sensitivity MAD4 preamplifier-discriminator and the dead-time free F1-TDC chip characterized by high-resolution. The readout electronics has been designed taking into account the high photon flux in the central part of the detector and the requirement to run at high trigger rates up to 100 kHz with negligible dead-time. The system is designed in a very compact setup and mounted directly in front of the multi-anode photomultipliers. The data are digitized on the frontend boards and transferred via optical links to the readout system. The read-out electronics system is described in detail together with its measured performances.

  18. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    Science.gov (United States)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  19. Alibava : A portable readout system for silicon microstrip sensors

    CERN Document Server

    Marco-Hernández, Ricardo; Casse, G; García, C; Greenall, A; Lacasta, C; Lozano, M; Martí i García, S; Martínez, R; Miñano, M; Pellegrini, G; Smith, N A; Ullán, M

    2007-01-01

    A portable readout system for silicon microstrip sensors is currently being developed. This system uses a front-end readout chip, which was developed for the LHC experiments. The system will be used to investigate the main properties of this type of sensors and their future applications. The system is divided in two parts: a daughter board and a mother board. The first one is a small board which contains two readout chips and has fan-ins and sensor support to interface the sensors. The last one is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. The core of this board is a FPGA that controls the readout chips, a 10 bit ADC, an integrated TDC and an USB controller. This board also contains the analogue electronics to process the data that comes from the readout chips. There is also provision for an external trigger input (e.g. scintillator trigger) and a 'synchronised' trigger output for ...

  20. Optimised cantilever biosensor with piezoresistive read-out

    DEFF Research Database (Denmark)

    Rasmussen, Peter; Thaysen, J.; Hansen, Ole

    2003-01-01

    We present a cantilever-based biochemical sensor with piezoresistive read-out which has been optimised for measuring surface stress. The resistors and the electrical wiring on the chip are encapsulated in low-pressure chemical vapor deposition (LPCVD) silicon nitride, so that the chip is well sui...

  1. A Self Triggered Amplifier/Digitizer Chip for CBM

    CERN Document Server

    Armbruster, A; Perić, I

    2009-01-01

    The development of front-end electronics for the planned CBM experiment at FAIR/GSI is in full progress. For charge readout of the various sub-detectors a new self-triggered amplification and digitization chip is being designed and tested. The mixed signal readout chip will have 32-64 channels each containing a low-power/low-noise preamplifier/shaper front-end, an 8-9 bit ADC and a digital post-processing based on a FIR/IIR-filter. The ADC has a pipeline architecture that uses a novel current-mode storage cell as a basic building block. The current prototype provides 26 different parametrized preamplifier/shaper/discriminator channels, 8 pipeline ADCs, a readout shift register matrix and a synthesized redundant signed binary (RSD) decoder.

  2. Cost effective flip chip assembly and interconnection technologies for large area pixel sensor applications

    Energy Technology Data Exchange (ETDEWEB)

    Fritzsch, T., E-mail: thomas.fritzsch@izm.fraunhofer.de [Fraunhofer IZM, Gustav-Meyer-Allee 25, Berlin 13355 (Germany); Jordan, R.; Oppermann, H. [Fraunhofer IZM, Gustav-Meyer-Allee 25, Berlin 13355 (Germany); Ehrmann, O. [Berlin Institute of Technology (TUB), Berlin 10623 (Germany); Toepper, M.; Baumgartner, T.; Lang, K.-D. [Fraunhofer IZM, Gustav-Meyer-Allee 25, Berlin 13355 (Germany)

    2011-09-11

    Much of the cost of manufacturing pixel detectors is due to bumping and flip chip assembly of the readout chips onto sensor tiles, even if it is done on wafer level. To address this issue, Fraunhofer IZM investigated two new technological approaches, namely screen printing using dry film resist and chip-to-wafer assembly. In the first approach, solder bumps with diameters of 80 and 25 {mu}m in pitches of 110 and 60 {mu}m, respectively, were produced by screen-printing solder paste using a photo-structured dry film resist. Results indicated that the technology is a viable high yield and low cost bumping process. The second approach was developed to decrease the number of manual handling steps in pixel module manufacturing, which is critical for reducing processing time and cost. Here, chip designs on 200 mm readout chip (ROC) wafers and 150 mm sensor wafers were especially adapted for chip-to-wafer assembly and to ensure that the interconnection yield and reliability could be tested. After bumping and dicing of the readout chip wafer and UBM plating on the sensor wafer, individual dice were flip chip mounted on the pre-diced sensor wafer. This paper describes the technological steps, key processing parameters and first results for both technologies.

  3. A new analogue sampling readout system for the COMPASS RICH-1 detector

    CERN Document Server

    Abbon, P; Dafni, T; Delagnes, E; Deschamps, H; Gerassimov, S; Ketzer, B; Konorov, I; Kravtchuk, N; Kunne, Fabienne; Magnon, A; Neyret, D; Panebianco, S; Paul, S; Rebourgeard, P

    2008-01-01

    A new electronic readout for CsI-coated multiwire proportional chambers (MWPC), used as photon detectors in the COMPASS ring imaging Cherenkov (RICH) detector, is described. A prototype system comprising more than 5000 channels has been built and tested in high-intensity beam conditions. It is based on the APV25-S1 analogue sampling chip, and replaces the GASSIPLEX chip readout used previously. The APV25 chip, although originally designed for Silicon microstrip detectors, is shown to perform well even with “slow” signals from an MWPC, maintaining a signal-to-noise ratio (SNR) of 9. For every trigger the system reads out three consecutive amplitudes in time, thus allowing to extract information on both the signal amplitude and its timing. This information is used to reduce pile-up events in a high-rate environment. Prototype tests of the new readout electronics on a central RICH photocathode in nominal COMPASS beam conditions showed that the effective time window is reduced from more than for the GASSIPLEX...

  4. Research on and design of key circuits in RFID tag chip for container management

    Directory of Open Access Journals (Sweden)

    Wang Wenjie

    2016-01-01

    Full Text Available This paper introduces the design of semi-passive RFID tag chip capable of monitoring container safety. A system framework complying with requirements by ISO/IEC 18000-6C is firstly presented, and then differences from the key units of common passive chip, such as switch-state monitoring circuit, power management unit and anti-shake design in baseband processor, are elaborated. The main function of such a chip is to record the container opening frequency during transportation. Finally, the realizations of each unit’s function are simulated.

  5. Design of a high voltage stimulator chip for a stroke rehabilitation system.

    Science.gov (United States)

    Zeng, Lei; Yi, Xin; Lu, Sheng; Lou, Yuan; Jiang, Jianfei; Qu, Hongen; Lan, Ning; Wang, Guoxing

    2013-01-01

    This paper describes the design of an 8-channel high voltage stimulator chip for rehabilitation of stroke patients through surface stimulation, which requires high stimulation currents and high compliance voltage. The chip gets stimulation control data through its Serial Peripheral Interface (SPI), and can accordingly generate biphasic stimulation currents with different amplitudes, duration, frequencies and polarities independently for each channel. The current driver is implemented with thick oxide devices with a supply voltage up to 90V. The chip is designed in a 0.35εm X-FAB high voltage process.

  6. The high performance readout chain for the DSSC 1Megapixel detector, designed for high throughput during pulsed operation mode

    Science.gov (United States)

    Kirchgessner, M.; Soldat, J.; Kugel, A.; Donato, M.; Porro, M.; Fischer, P.

    2015-01-01

    The readout chain of the DSSC 1M pixel detector currently built at DESY, Hamburg for the European X-Ray Free Electron Laser is described. The system operates in pulsed operation mode comparable to the new ILC. Each 0.1 seconds 800 images of 1M pixels are produced and readout by the DSSC DAQ electronics. The total data production rate of the system is about 134 Gbit/s. In order to deal with the high data rates, latest technology components like the Xilinx Kintex 7 FPGA are used to implement fast DDR3-1600 image buffers, high speed serial FPGA to FPGA communication and 10 GB Ethernet links concentrated in one 40 Gbit/s QSFP+ transceiver.

  7. Study and simulation of the read-out electronics design for a high-resolution plastic scintillating fiber based hodoscope

    Science.gov (United States)

    Blasco, José María; Sanchis, E.; Granero, D.; Martín, J. D.; González, V.; Sanchis-Sánchez, E.

    2015-06-01

    This work presents the study and simulation of a high-resolution charged particle detection device for beam positioning, monitoring and calibration, together with its read-out proposal. To provide the precise positional information of the beam, the detection system has been based on Plastic Scintillating Fibers (PSF), while the read-out on a Silicon-PhotoDiode (Si-PD) array. To carry out the study, a PSF prototype with one detection plane has been experimentally tested with a β particle source. Besides, Monte Carlo simulations of the complete system have also been conducted. Both simulations and experimental tests give consistency to the results obtained. The work presented in this article show the usefulness of this proposal for high-precision charged particle positioning, achieving resolutions up to 100 μm.

  8. ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; O CONNOR,P.; KANDASAMY,A.; GROSHOLZ,J.

    2002-07-08

    A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 {micro}m CMOS and tested. Design concepts and experimental results are discussed.

  9. High frame rate measurements of semiconductor pixel detector readout IC

    Science.gov (United States)

    Szczygiel, R.; Grybos, P.; Maj, P.

    2012-07-01

    We report on high count rate and high frame rate measurements of a prototype IC named FPDR90, designed for readouts of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 is constructed in 90 nm CMOS technology and has dimensions of 4 mm×4 mm. Its main part is a matrix of 40×32 pixels with 100 μm×100 μm pixel size. The chip works in the single photon counting mode with two discriminators and two 16-bit ripple counters per pixel. The count rate per pixel depends on the effective CSA feedback resistance and can be set up to 6 Mcps. The FPDR90 can operate in the continuous readout mode, with zero dead time. Due to the architecture of digital blocks in pixel, one can select the number of bits read out from each counter from 1 to 16. Because in the FPDR90 prototype only one data output is available, the frame rate is 9 kfps and 72 kfps for 16 bits and 1 bit readout, respectively (with nominal clock frequency of 200 MHz).

  10. High frame rate measurements of semiconductor pixel detector readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Szczygiel, R., E-mail: robert.szczygiel@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Instrumentation, Al. Mickiewicza 30, 30-059 Cracow (Poland); Grybos, P.; Maj, P. [AGH University of Science and Technology, Department of Measurement and Instrumentation, Al. Mickiewicza 30, 30-059 Cracow (Poland)

    2012-07-11

    We report on high count rate and high frame rate measurements of a prototype IC named FPDR90, designed for readouts of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 is constructed in 90 nm CMOS technology and has dimensions of 4 mm Multiplication-Sign 4 mm. Its main part is a matrix of 40 Multiplication-Sign 32 pixels with 100 {mu}m Multiplication-Sign 100 {mu}m pixel size. The chip works in the single photon counting mode with two discriminators and two 16-bit ripple counters per pixel. The count rate per pixel depends on the effective CSA feedback resistance and can be set up to 6 Mcps. The FPDR90 can operate in the continuous readout mode, with zero dead time. Due to the architecture of digital blocks in pixel, one can select the number of bits read out from each counter from 1 to 16. Because in the FPDR90 prototype only one data output is available, the frame rate is 9 kfps and 72 kfps for 16 bits and 1 bit readout, respectively (with nominal clock frequency of 200 MHz).

  11. chipD: a web tool to design oligonucleotide probes for high-density tiling arrays

    Science.gov (United States)

    Dufour, Yann S.; Wesenberg, Gary E.; Tritt, Andrew J.; Glasner, Jeremy D.; Perna, Nicole T.; Mitchell, Julie C.; Donohue, Timothy J.

    2010-01-01

    chipD is a web server that facilitates design of DNA oligonucleotide probes for high-density tiling arrays, which can be used in a number of genomic applications such as ChIP-chip or gene-expression profiling. The server implements a probe selection algorithm that takes as an input, in addition to the target sequences, a set of parameters that allow probe design to be tailored to specific applications, protocols or the array manufacturer’s requirements. The algorithm optimizes probes to meet three objectives: (i) probes should be specific; (ii) probes should have similar thermodynamic properties; and (iii) the target sequence coverage should be homogeneous and avoid significant gaps. The output provides in a text format, the list of probe sequences with their genomic locations, targeted strands and hybridization characteristics. chipD has been used successfully to design tiling arrays for bacteria and yeast. chipD is available at http://chipd.uwbacter.org/. PMID:20529880

  12. A data readout approach for physics experiments

    Institute of Scientific and Technical Information of China (English)

    HUANG Xi-Ru; CAO Ping; GAO Li-Wei; ZHENG Jia-Jun

    2015-01-01

    With increasing physical event rates and the number of electronic channels,traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane.In this paper,a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ.Features of exPlicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments.Furthermore,to guarantee the readout performance and flexibility,a standalone embedded CPU system is utilized for network protocol stack processing.To receive the customized data format and protocol from front-end electronics,a field programmable gate array (FPGA) is used for logic reconfiguration.To optimize the interface and to improve the data throughput between CPU and FPGA,a sophisticated method based on SRAM is presented in this paper.For the purpose of evaluating this high-speed readout method,a simplified readout module is designed and implemented.Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.

  13. Miniature Bose-Einstein condensate system design based on a transparent atom chip

    Science.gov (United States)

    Cheng, Jun; Li, Xiaolin; Zhang, Jingfang; Xu, Xinping; Jiang, Xiaojun; Zhang, Haichao; Wang, Yuzhu

    2016-08-01

    We propose a new miniature Bose-Einstein condensate (BEC) system based on a transparent atom chip with a compact external coil structure. A standard six-beam macroscopic magneto-optical trap (MOT) is able to be created near the chip surface due to the chip’s transparency. A novel wire pattern consisting of a double-z wire and a z-shaped wire is designed on the transparent atom chip. With a vertical bias magnetic field, the double-z wire can create the quadrupole magnetic field of an intermediate chip MOT, which is suitable for transporting atoms from the macroscopic MOT to the chip z-wire trap efficiently. The compact external coil structure is designed with a rectangular frameless geometry consisting of only four coil pairs and its volume is less than 0.3 liters. The maximum system power consumption during the BEC generation procedure is about 45 W. The miniature system is evaluated, and about 3 × 106 atoms can be loaded into the chip z-wire trap. The miniature chip BEC system has the advantages of small volume and low power consumption, and it has great potential for practical applications of BEC.

  14. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  15. Thermopile detector radiation hard readout

    Science.gov (United States)

    Gaalema, Stephen; Van Duyne, Stephen; Gates, James L.; Foote, Marc C.

    2010-08-01

    The NASA Jupiter Europa Orbiter (JEO) conceptual payload contains a thermal instrument with six different spectral bands ranging from 8μm to 100μm. The thermal instrument is based on multiple linear arrays of thermopile detectors that are intrinsically radiation hard; however, the thermopile CMOS readout needs to be hardened to tolerate the radiation sources of the JEO mission. Black Forest Engineering is developing a thermopile readout to tolerate the JEO mission radiation sources. The thermal instrument and ROIC process/design techniques are described to meet the JEO mission requirements.

  16. Design of a Low-Noise Readout Circuit for CZT Detector%CZT探测器低噪声读出电路设计

    Institute of Scientific and Technical Information of China (English)

    曾蕙明; 魏廷存; 高武

    2013-01-01

    采用TSMC 0.35 μm CMOS工艺,设计了CZT探测器低噪声读出电路链和一款多通道能量读出ASIC,该电路将应用于8×8 CZT像素探测器的能量读出.给出了系统框图及低噪声能量读出电路链,分析了低噪声技术策略.实验结果表明,能量分辨范围为20 keV~4 MeV,等效噪声电荷(ENC)小于150个电子,电荷转电压增益为9.2 V/pC,非线性度小于3%,多通道串扰小于10个电子,满足设计需求.%A low-noise front-end readout circuit chain and a multi-channel energy readout ASIC for CZT detector in PET imaging system were designed based on TSMC's 0.35 μm mixed-signal CMOS process.Architecture of the PET imaging system and the low-noise energy readout circuit chain were presented,and low-noise technology strategy was analyzed.Simulation results showed that the energy resolution was from 20 keV to 4 MeV,the equivalent noise charge (ENC) was less than 150 electrons (rms),the charge-to-voltage gain was 9.2 V/pC,the non-linearity was below 3%,and crosstalk of multi channels was less than 10 electrons,satisfying requirements of the design.

  17. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  18. A custom readout electronics for the BESIII CGEM detector

    Science.gov (United States)

    Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

    2017-07-01

    For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

  19. Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

    Science.gov (United States)

    Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

    2007-01-01

    A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

  20. Low noise CMOS readout for CdZnTe detector arrays

    Energy Technology Data Exchange (ETDEWEB)

    Jakobson, C.G.; Asa, G.; Lev, S. Bar; Nemirovsky, Y. E-mail: nemirov@ee.technion.ac.il

    1999-06-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 {mu}m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing function incorporated in the shaper provides low power and reduces chip area. The system is partitioned into a chip containing the charge amplifiers and a chip containing the semi-Gaussian pulse shaper and multiplexer. This architecture minimizes coupling from multiplexer switches as well as shaper output to the input of the charge sensitive preamplifiers.

  1. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    Science.gov (United States)

    Aliaga, R. J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-11-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

  2. A Prototype Scalable Readout System for Micro-pattern Gas Detectors

    CERN Document Server

    Zheng, Qi-Bin; Tian, Jing; Li, Cheng; Feng, Chang-Qing; An, Qi

    2016-01-01

    A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The Adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the Adapter, has a FPGA-based reconfigurable logic and I/O interfaces, allowing users to choose various ASIC cards and Adapters for different types of detectors. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor (SiTCP) IP core in field-programmable gate arrays (FPGA). The readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chips, VA140 and AGET, are applied to verify the concept of this SRS architecture. Based on this VA140 or AGET SR...

  3. A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz; Christian, David; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2008-12-01

    3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 x 20 {micro}m{sup 2} pixels, laid out in an array of 64 x 64 elements and was fabricated in a 3-tier 0.18 {micro}m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 {micro}m CMOS process to overcome some of the disadvantages of an FDSOI process.

  4. A prototype scalable readout system for micro-pattern gas detectors

    Science.gov (United States)

    Zheng, Qi-Bin; Liu, Shu-Bin; Tian, Jing; Li, Cheng; Feng, Chang-Qing; An, Qi

    2016-08-01

    A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules: the ASIC card, the adapter card and the front-end card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array (FPGA)-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor (SiTCP) IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC (VA140) cards handling 512 detector channels, or 4 ASIC (AGET) cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels. Supported by National Natural Science Foundation of China (11222552)

  5. Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

    Energy Technology Data Exchange (ETDEWEB)

    Shen, Wei

    2012-07-24

    Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

  6. A ten thousand frames per second readout MAPS for the EUDET beam telescope

    CERN Document Server

    Hu-Guo, C; Bertolone, G; Besson, A; Brogna, A S; Colledani, C; Claus, G; De Masi, R; Degerli, Y; Dorokhov, A; Doziere, G; Dulinski, W; Fang, X; Gelin, M; Goffea, M; Guillouxb, F; Himmi, A; Jaaskelainen, K; Koziel, M; Morel, F; Orsini, F; Santos, G; Specht, M; Sun, Q; Torheim, O; Valin, I; Voutsinas, Y; Wintera, M

    2009-01-01

    Designed and manufactured in a commercial CMOS 0.35 μm OPTO process for equipping the EUDET beam telescope, MIMOSA26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels with 576 rows and 1152 columns, covering an active area of ~224 mm2. A single point resolution of about 4 μm was obtained with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The paper describes the chip design, test and major characterisation outcome.

  7. PANDA straw tube detectors and readout

    Science.gov (United States)

    Strzempek, P.; Panda Collaboration

    2016-07-01

    PANDA is a detector under construction dedicated to studies of production and interaction of particles in the charmonium mass range using antiproton beams in the momentum range of 1.5 - 15 GeV/c at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt. PANDA consists of two spectrometers: a Target Spectrometer with a superconducting solenoid and a Forward Spectrometer using a large dipole magnet and covering the most forward angles (Θ < 10 °). In both spectrometers, the particle's trajectories in the magnetic field are measured using self-supporting straw tube detectors. The expected high count rates, reaching up to 1 MHz/straw, are one of the main challenges for the detectors and associated readout electronics. The paper presents the readout chain of the tracking system and the results of tests performed with realistic prototype setups. The readout chain consists of a newly developed ASIC chip (PASTTREC 〈 PANDASTTReadoutChip 〉) with amplification, signal shaping, tail cancellation, discriminator stages and Time Readout Boards as digitizer boards.

  8. A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

    CERN Document Server

    Fiergolski, Adrian

    2017-01-01

    The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

  9. A high dynamic range readout unit for a calorimeter

    Institute of Scientific and Technical Information of China (English)

    ZHANG Yun-Long; WU Jian; CHANG Jin; LI Bing; FENG Chang-Qing; LI Xian-Li; WANG Xiao-Lian; XU Zi-Zong; GUO Jian-Hua; CAI Ming-Sheng; HU Yi-Ming

    2012-01-01

    A high dynamic range readout system,consisting of a multi-dynode readout PMT and a VA32 chip,is presented.An LED system is set up to calibrate the relative gains between the dynodes,and the ADC counts per MIPs from dynode 7 are determined under cosmic-ray calibration.A dynamic range from 0.5 MIPs to 1 × 105 MIPs is achieved.

  10. Developing organ-on-a-chip concepts using bio-mechatronic design methodology.

    Science.gov (United States)

    Christoffersson, Jonas; van Noort, Danny; Mandenius, Carl-Fredrik

    2017-05-26

    Mechatronic design is an engineering methodology for conceiving, configuring and optimising the design of a technical device or product to the needs and requirements of the final user. In this article, we show how the basic principles of this methodology can be exploited for in vitro cell cultures-often referred to as organ-on-a-chip devices. Due to the key role of the biological cells, we have introduced the term bio-mechatronic design, to highlight the complexity of designing a system that should integrate biology, mechanics and electronics in the same device structure. The strength of the mechatronic design is to match the needs of the potential users to a systematic evaluation of overall functional design alternative. It may be especially attractive for organs-on-chips where biological constituents such as cells and tissues in 3D settings and in a fluidic environment should be compared, screened and selected. Through this approach, design solutions ranked to customer needs are generated according to specified criteria, thereby defining the key constraints of the fabrication. As an example, the bio-mechatronic methodology is applied to a liver-on-a-chip based on information extrapolated from previous theoretical and experimental knowledge. It is concluded that the methodology can generate new fabrication solutions for devices, as well as efficient guidelines for refining the design and fabrication of many of today's organ-on-a-chip devices.

  11. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    Wojciech Wierba; on behalf of the FCAL Collaboration

    2007-12-01

    The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed.

  12. Correlated Color Temperature Tunable Multi-chip Light Emitting Diodes Light Source Design

    Institute of Scientific and Technical Information of China (English)

    SHEN Hai-ping; PAN Jian-gen; FENG Hua-jun

    2008-01-01

    One of the methods to derive white light from light emitting diodes(LEDs) is the multi-chip white LED technology, which mixes the light from red, green and blue LEDs. Introduced is an optimal algorithm for the spectrum design of the multi-chip white LEDs in this paper. It optimizes the selection of single color LEDs and drive current controlling, so that the multi-chip white LED achieves the target correlated color temperature(CCT), as well as high luminous efficacy and good color rendering. A CCT tunable LED light source with four high-power LEDs is realized based on the above optimal design. Test results show that it maintains satisfactory color rendering and stable luminous efficacy across the whole CCT tuning range. Finally, discussed are the design improvement and the prospect of the future applications of the CCT tunable LED light source.

  13. AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

    Directory of Open Access Journals (Sweden)

    Rehan Maroofi

    2011-10-01

    Full Text Available Traditional System-on-Chip (SoC design employed shared buses for data transfer among varioussubsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbasedarchitecture is giving way to a new paradigm for on-chip communication. This paradigm is calledNetwork-on-Chip (NoC. A communication network of point-to-point links and routing switches is used tofacilitate communication between subsystems. The routing switch proposed in this paper consists of fourcomponents, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design isdescribed in this paper. The function of the scheduler is to arbitrate between requests by data packets foruse of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Dueto the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduleronto itself, thereby reducing its area roughly by 50%.

  14. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    of wireless integrated sensor networks which are an emerging class of networked embedded computer systems. The work described here demonstrates how to model multiprocessor systems-on-chip at the system level by abstracting away most of the lower-level details albeit retaining the parameters most relevant......The first part of the thesis presents an overview of the existing theories and practices of modeling and simulation of multiprocessor systems-on-chip. The systematic categorization of the plethora of existing programming models at various levels of abstraction is the main contribution here which...... is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...

  15. Human-on-a-chip design strategies and principles for physiologically based pharmacokinetics/pharmacodynamics modeling.

    Science.gov (United States)

    Abaci, Hasan Erbil; Shuler, Michael L

    2015-04-01

    Advances in maintaining multiple human tissues on microfluidic platforms has led to a growing interest in the development of microphysiological systems for drug development studies. Determination of the proper design principles and scaling rules for body-on-a-chip systems is critical for their strategic incorporation into physiologically based pharmacokinetic (PBPK)/pharmacodynamic (PD) model-aided drug development. While the need for a functional design considering organ-organ interactions has been considered, robust design criteria and steps to build such systems have not yet been defined mathematically. In this paper, we first discuss strategies for incorporating body-on-a-chip technology into the current PBPK modeling-based drug discovery to provide a conceptual model. We propose two types of platforms that can be involved in the different stages of PBPK modeling and drug development; these are μOrgans-on-a-chip and μHuman-on-a-chip. Then we establish the design principles for both types of systems and develop parametric design equations that can be used to determine dimensions and operating conditions. In addition, we discuss the availability of the critical parameters required to satisfy the design criteria, consider possible limitations for estimating such parameter values and propose strategies to address such limitations. This paper is intended to be a useful guide to the researchers focused on the design of microphysiological platforms for PBPK/PD based drug discovery.

  16. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Multimedia

    Tomasek, L; Loddo, F; Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Pacher, L; Kluit, R; Hinchliffe, I; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Prydderch, M L; Bilei, G M; Da rocha rolo, M D; Fanucci, L; Grillo, A A; Bellazzini, R; Manghisoni, M; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Key-charriere, M; Andreazza, A; Traversi, G; De canio, F; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Gromov, V; Morsani, F; Bisello, D; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

    The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

  17. Electronics and readout of a large area silicon detector for LHC

    Energy Technology Data Exchange (ETDEWEB)

    Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J. (Univ. of Bern (Switzerland) Cavendish Lab., Univ. of Cambridge (United Kingdom) CERN, Geneva (Switzerland) Inst. fuer Physik, Univ. Dortmund (Germany) DPNC, Geneva Univ. (Switzerland) 1. Inst. fur Experimentalphysik, Hamburg (Germany) School of Physics, Univ. of Melbourne, Parkville, VIC (Australia) Dept. of Nuclear Physics, Oxford Univ. (United Kingdom) Rutherford Appleton Lab., Chilton, Didcot (United Kingdom) Centre d' Etudes Nucleaires de Saclay, 91 Gif

    1994-04-21

    The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)

  18. Electronics and readout of a large area silicon detector for LHC

    Science.gov (United States)

    Borer, K.; Munday, D. J.; Parker, M. A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E. H. M.; Santiard, J. C.; Scampoli, P.; Verweij, H.; Gössling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A. G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R. A.; Gorfine, G. W.; Moorhead, G. F.; Taylor, G. N.; Tovey, S. N.; Bibby, J. H.; Hawkings, R. J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.

    1994-04-01

    The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquistion systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10°C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture.

  19. Design Centering and Yield Optimisation of MMIC’s with Off-Chip Digital Controllers

    OpenAIRE

    Centurelli, F.; Luzzi, R; Scotti, G.; Tommasino, P.; Trifiletti, A.

    2002-01-01

    In this paper, a new methodology to perform yield-oriented design of MMIC’s in III-V technologies is proposed. A digital control of MMIC bias, based on process parameters estimation by on-chip auxiliary circuits, allows yield enhancement. The design centering approach and a distance-dependent correlated statistical model of HEMT devices are used to design the external controller. The design of a MMIC for optical digital systems has highlighted significant yield improvement with respect to pre...

  20. Design of a CMOS-based multichannel integrated biosensor chip for bioelectronic interface with neurons.

    Science.gov (United States)

    Zhang, Xin; Wong, Wai Man; Zhang, Yulong; Zhang, Yandong; Gao, Fei; Nelson, Richard D; Larue, John C

    2009-01-01

    In this paper we present the design and prototyping of a 24-channel mixed signal full-customized CMOS integrated biosensor chip for in vitro extracellular recording of neural signals. Design and implementation of hierarchical modules including microelectrode electrophysiological sensors, analog signal buffers, high gain amplifier and control/interface units are presented in detail. The prototype chip was fabricated by MOSIS with AMI C5 0.5 microm, double poly, triple metal layer CMOS technology. The electroless gold plating process is used to replace the aluminum material obtained from the standard CMOS process with biocompatible metal gold in the planner microelectrode array sensors to prevent cell poisoning and undesirable electrochemical corrosion. The biosensor chip provides a satisfactory signal-to-noise ratio for neural signals with amplitudes and frequencies within the range of 600microV - 2mV and 100 Hz to 10KHz, respectively.

  1. Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2015-01-01

    Full Text Available The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS-microelectro -mechanical system (MEMS technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

  2. A universal probe design for colorimetric detection of single-nucleotide variation with visible readout and high specificity

    Science.gov (United States)

    Chen, Xueping; Zhou, Dandan; Shen, Huawei; Chen, Hui; Feng, Wenli; Xie, Guoming

    2016-01-01

    Single-nucleotide variation (SNV) is a crucial biomarker for drug resistance-related detection in cancer and bacterial infection. However, the unintended binding of DNA probes limits the specificity of SNV detection, and the need for redesigned sequences compromise the universality of SNV assay. Herein, we demonstrated a universal and low-cost assay for the colorimetric discrimination of drug-resistance related point mutation. By the use of a universal DNA probe and a split G-quadruplex, the signal could be recognized by naked eye at room temperature. The DNA probe was used as a signal reporter which not only improved the universality, but also enabled high specificity of probe hybridization. This assay was successfully applied in the detection of cancer-related SNV in the epidermal growth factor receptor (EGFR) gene, kirsten rat sarcoma viral oncogene homologue (KRAS), and tuberculosis drug-resistance related point mutation in RNA polymerase beta subunit gene (rpoB) with high specificity and visible readout. This method was simple, rapid, high-throughput and effective, which was suitable for point-of-care applications. PMID:26830326

  3. A 97 dB dynamic range CSA-based readout circuit with analog temperature compensation for MEMS capacitive sensors

    Science.gov (United States)

    Tao, Yin; Chong, Zhang; Huanming, Wu; Qisong, Wu; Haigang, Yang

    2013-11-01

    This paper presents a charge-sensitive-amplifier (CSA) based readout circuit for capacitive microelectro-mechanical-system (MEMS) sensors. A continuous-time (CT) readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits. An operational trans-conductance amplifier (OTA) structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal. An analog temperature compensation method is proposed, which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity. The chip is designed and implemented in a 0.35 μm CMOS process and is 2.1 × 2.1 mm2 in area. The measurement shows that the readout circuit achieves 0.9 aF / √Hz capacitive resolution, 97 dB dynamic range in 100 Hz signal bandwidth, and 0.8 mV/fF sensitivity with a temperature drift of 35 ppm/°C after optimized compensation.

  4. ASIC DESIGN OF ADAPTIVE THRESHOLD DENOISE DWT CHIP

    Institute of Scientific and Technical Information of China (English)

    Luo Feng; Wu Shunjun; Jiao Licheng; ZhangLinrang

    2002-01-01

    According to the relationship of wavelet transform and perfect reconstructive FIR filter banks, this paper presents a real-time chip with adaptive Donoho's non-linear soft-threshold for denoising in different levels of multi-scale space through rearranging the input data during convolving, filtering and sub-sampling. And more important, it gives a simple iterative algorithm to calculate the variance of the noise in interregna with no signal. It works well whether the signal or noise is stationary or not.

  5. Experiences in flip chip production of radiation detectors

    Science.gov (United States)

    Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

    2006-09-01

    Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

  6. Experiences in flip chip production of radiation detectors

    Energy Technology Data Exchange (ETDEWEB)

    Savolainen-Pulli, Satu [VTT, MEMS- and Micropackaging, P.O. Box 1000, Tietotie 3, Espoo, FI-02044 VTT (Finland)]. E-mail: satu.savolainen-pulli@vtt.fi; Salonen, Jaakko [VTT, MEMS- and Micropackaging, P.O. Box 1000, Tietotie 3, Espoo, FI-02044 VTT (Finland); Salmi, Jorma [VTT, MEMS- and Micropackaging, P.O. Box 1000, Tietotie 3, Espoo, FI-02044 VTT (Finland); Vaehaenen, Sami [VTT, MEMS- and Micropackaging, P.O. Box 1000, Tietotie 3, Espoo, FI-02044 VTT (Finland)

    2006-09-01

    Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-{mu}m diameter tin-lead solder bumps at a 50-{mu}m pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

  7. OLA, A low-noise bipolar amplifier for the readout of Silicon Drift Detectors

    Science.gov (United States)

    Dabrowski, W.; Białas, W.; Bonazzola, G.; Bonvicini, V.; Ceretto, F.; Giubellino, P.; Idzik, M.; Prest, M.; Riccati, L.; Zampa, N.

    1995-11-01

    A very low noise, 32-channel preamplifier/shaper chip has been designed for the analogue readout of silicon detectors. The circuit has been optimised in view of the operation of Silicon Drift Detectors, which have very low capacitance and produce gaussian signals of σ up to ˜ 100 ns. The chip (OLA) has been designed and manufactured using the SHPi full-custom bipolar process by Tektronix. Each channel is composed by a preamplifier, a shaper and a symmetrical line driver, which allows to drive either a positive and a negative single ended output separately on 50 Ω impedance or a differential twisted pair. The intrinsic peaking time of the circuit is ˜ 60 ns, and the noise is below 250 electrons at zero input load capacitance. The power consumption is 2 mW/channel, mostly due to the output driver.

  8. 14-bit pipeline-SAR ADC for image sensor readout circuits

    Science.gov (United States)

    Wang, Gengyun; Peng, Can; Liu, Tianzhao; Ma, Cheng; Ding, Ning; Chang, Yuchun

    2015-03-01

    A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.

  9. Frequency and sensitivity tunable microresonator array for high-speed quantum processor readout

    Science.gov (United States)

    Hoskinson, Emile; Whittaker, J. D.; Swenson, L. J.; Volkmann, M. H.; Spear, P.; Altomare, F.; Berkley, A. J.; Bumble, B.; Bunyk, P.; Day, P. K.; Eom, B. H.; Harris, R.; Hilton, J. P.; Johnson, M. W.; Kleinsasser, A.; Ladizinsky, E.; Lanting, T.; Oh, T.; Perminov, I.; Tolkacheva, E.; Yao, J.

    Frequency multiplexed arrays of superconducting microresonators have been used as detectors in a variety of applications. The degree of multiplexing achievable is limited by fabrication variation causing non-uniform shifts in resonator frequencies. We have designed, implemented and characterized a superconducting microresonator readout that incorporates two tunable inductances per detector, allowing independent control of each detector frequency and sensitivity. The tunable inductances are adjusted using on-chip programmable digital-to-analog flux converters, which are programmed with a scalable addressing scheme that requires few external lines.

  10. An optimal parametric design to improve chip cooling

    Energy Technology Data Exchange (ETDEWEB)

    Tseng, Y.-S. [Department of Engineering and System Science, National Tsing Hua University, Taiwan (China); Fu, H.-H. [Department of Business Administration, Shu-Te University, Taiwan (China); Hung, T.-C. [Department of Mechanical and Automation Engineering, I-Shou University, Kaohsiung County 840, Taiwan (China)]. E-mail: tchung@isu.edu.tw; Pei, B.-S. [Department of Engineering and System Science, National Tsing Hua University, Taiwan (China)

    2007-08-15

    The thermal problems of most electronic components have been solved in recent years by installing various cooling equipments. The passive cooling, which has no need of the fluid-driving devices, can be more reliable and achieved with less cost. In this paper, the Taguchi's method is applied on the optimization of the passive cooling for electronic systems, and a representative CFD (computational fluid dynamic) model is selectively implemented for statistical analysis. The selected parameters in this study are the power density, mother board orientation, chip geometry, opening between chips and the flow pattern. The optimal combination for thermal cooling is obtained by using a two-level statistical approach. Analysis results indicate that about 50% of the effort in performing experiments and simulations can be saved. Further, the results confirmed that the most important parameters affecting the thermal behaviors are the openings in the mother board, power density, and the flow pattern in sequence. Finally, the concept of opening increases the reliability, reduces the manufacturing cost, and simplifies the assembly procedures.

  11. Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

    Science.gov (United States)

    Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

    2011-01-01

    The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

  12. A fast integrated readout system for a cathode pad photon detector

    Science.gov (United States)

    French, M.; Lovell, M.; Chesi, E.; Racz, A.; Seguinot, J.; Ypsilantis, T.; Arnold, R.; Guyonnet, J. L.; Egger, J.; Gabathuler, K.

    1994-04-01

    A fast integrated electronic chain is presented to read out the cathode pad array of a multiwire photon detector for a fast RICH counter. Two VLSI circuits have been designed and produced. An analog eight channel, low noise, fast, bipolar, current preamplifier and discriminator chip serves as front-end electronics. It has an rms equivalent noise current of 10 nA (2000 e -), 50 MHz bandwidth with 10 mW of power consumption per channel. Two analogue chips are coupled to a digital 16 channels CMOS readout chip, operating at 20 MHz, that provides a pipelined delay of 1.3 μs and zero suppression with a power consumption of about 6 mW per channel. Readout of a 4000 pad sector requires 3-4 μs depending on the number of hit pads. The full RICH counter is made up of many of such sectors (the prototype has three fully equipped sectors), read out in parallel [1,2]. The minimum time to separate successive hits on the same pad is about 70 ns. The time skew of the full chain is about 15 ns.

  13. Front-end readout ASIC for charged particle counting with the RADEM instrument on the ESA JUICE mission

    Science.gov (United States)

    Stein, Timo A.; Pâhlsson, Philip; Meier, Dirk; Hasanbegovic, Amir; Otnes Berge, Hans Kristian; Altan, Mehmet Akif; Ackermann, Jörg; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Gheorghe, Codin; Steenari, David; Øya, Petter; Johansen, Tor Magnus; Maehlum, Gunnar

    2016-07-01

    The detector readout for the Radiation-hard Electron Monitor (RADEM) aboard the JUpiter ICy moons Explorer (JUICE) uses a custom-made application-specific integrated circuit (ASIC, model: IDE3466) for the charge signal readout from silicon radiation sensors. RADEM measures the total ionizing dose and dose rate for protons (5 MeV to 250 MeV), electrons (0.3 MeV to 40 MeV) and ions. RADEM has in total three chips of the same design: one chip for the proton and ion detector, one for the electron detector, and one for the directional detector. The ASIC has 36 chargesensitive pre-amplifiers (CSA), 36 counters of 22-bits each, and one analogue output for multiplexing the pulse heights from all channels. The counters count pulses from charged particles in the silicon sensors depending on the charge magnitude and the coincidence trigger pattern from the 36 channels. We have designed the ASIC in 0.35-μm CMOS process and an ASIC wafer lot has been manufactured at AMS. This article presents the ASIC design specifications and design validation results. The preliminary results from tests with bare chips indicate that the design meets the technical requirements.

  14. Development of a chip-based ingroove microplasma source: Design, characterization, and diagnostics

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuemei; Meng, Fanying; Yuan, Xin; Yan, Yanyue; Zhao, Zhongjun; Duan, Yixiang, E-mail: yduan@scu.edu.cn [Research Center of Analytical Instrumentation, College of Chemistry and College of Life Science Sichuan University, Chengdu (China); Tang, Jie [State Key Laboratory of Transient Optics and Photonics, Xi' an Institute of Optics and Precision Mechanics of CAS, Xi' an (China)

    2014-03-10

    A chip-based ingroove microplasma source was designed for molecular emission spectrometry by using a space-confined direct current duct in air. The voltage-current characteristics of different size generators, emission spectroscopy of argon were discussed, respectively. It is found that the emission intensity of excited Ar and N{sub 2} approaches its maximum near the cathode, while OH and O peaks most likely appear close to the anode. The electron density, electronic excitation temperature, rotational temperature, and vibrational temperature of the argon plasma were also calculated. More importantly, the chip-based ingroove microplasma shows much better stability compared with its counterparts.

  15. Design of On—Chip Clock Generation with 50/50 Duty Cycle Correction

    Institute of Scientific and Technical Information of China (English)

    HANYueqiu; CUIWei; CHENHe

    2003-01-01

    A circuit design of on-chip clock generation which improves the duty cycle performance and prevents latch-up effect is described.The circuity provides onchip clock with automatic duty cycle correction so as to overcome the shortcoming of clock duty cycle dependence on technology parameters of the traditional on-chip clock generation circuit.It is extremely important that the dynamic power consumption equals approximately the one of its predecessor.The effective performance of the proposed circuit is confirmed by SPICE simulation.

  16. Blood cleaner on-chip design for artificial human kidney manipulation.

    Science.gov (United States)

    Suwanpayak, N; Jalil, M A; Aziz, M S; Ismail, F D; Ali, J; Yupapin, P P

    2011-01-01

    A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells) can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney), and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.

  17. Design and Implementation of Single Chip WCDMA High Speed Channel Decoder

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX' XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30.72MHz) driving can concurrently process a data rate up to 2.5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0.2~0.3dB or less lost comparing to float simulation.

  18. The design, modeling and optimization of on-chip inductor and transformer circuits

    Science.gov (United States)

    Mohan, Sunderarajan Sunderesan

    2000-08-01

    On-chip inductors and transformers play a crucial role in radio frequency integrated circuits (RFICs). For gigahertz circuitry, these components are usually realized using bond-wires or planar on-chip spirals. Although bond wires exhibit higher quality factors (Q) than on-chip spirals, their use is constrained by the limited range of realizable inductances, large production fluctuations and large parasitic (bondpad) capacitances. On the other hand, spiral inductors exhibit good matching and are therefore attractive for commonly used differential architectures. Furthermore, they permit a large range of inductances to be realized. However, they possess smaller Q values and are more difficult to model. In this dissertation, we develop a current sheet theory based on fundamental electromagnetic principles that yields simple, accurate inductance expressions for a variety of geometries, including planar spirals that are square, hexagonal, octagonal or circular. When compared to field solver simulations and measurements over a wide design space, these expressions exhibit typical errors of 2-3%, making them ideal for use in circuit synthesis and optimization. When combined with a commonly used lumped π model, these expressions allow the engineer to explore trade-offs quickly and easily. These current sheet based expressions eliminate the need for using segmented summation methods (such as the Greenhouse approach) to evaluate the inductance of spirals. Thus, the design and optimization of on-chip spiral inductors and transformers can now be performed in a standard circuit design environment (such as SPICE). Field solvers (which are difficult to integrate into a circuit design environment) are now only needed to verify the final design. Using these newly developed inductance expressions, this thesis explores how on-chip inductors should be optimized for various circuit applications. In particular, a new design methodology is presented for enhancing the bandwidth of

  19. LHCb: Fast Readout Control for the upgraded readout architecture of the LHCb experiment at CERN

    CERN Multimedia

    Alessio, F

    2013-01-01

    The LHCb experiment at CERN has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity with an upgraded LHCb detector. As a consequence, the various LHCb sub-systems in the readout architecture will be upgraded to cope with higher sub-detector occupancies, higher rate, and higher readout load. The new architecture, new functionalities, and the first hardware implementation of a new LHCb Readout Control system (commonly referred to as S-TFC) for the upgraded LHCb experiment is here presented. Our attention is focused in describing solutions for the distribution of clock and timing information to control the entire upgraded readout architecture by profiting of a bidirectional optical network and powerful FPGAs, including a real-time mechanism to synchronize the entire system. Solutions and implementations are presented, together with first results on the simulation and the validation of the system.

  20. Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

    Science.gov (United States)

    Feller, A.; Lombardi, T.

    1978-01-01

    Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

  1. Intensity-based readout of resonant-waveguide grating biosensors: Systems and nanostructures

    Science.gov (United States)

    Paulsen, Moritz; Jahns, Sabrina; Gerken, Martina

    2017-09-01

    Resonant waveguide gratings (RWG) - also called photonic crystal slabs (PCS) - have been established as reliable optical transducers for label-free biochemical assays as well as for cell-based assays. Current readout systems are based on mechanical scanning and spectrometric measurements with system sizes suitable for laboratory equipment. Here, we review recent progress in compact intensity-based readout systems for point-of-care (POC) applications. We briefly introduce PCSs as sensitive optical transducers and introduce different approaches for intensity-based readout systems. Photometric measurements have been realized with a simple combination of a light source and a photodetector. Recently a 96-channel, intensity-based readout system for both biochemical interaction analyses as well as cellular assays was presented employing the intensity change of a near cut-off mode. As an alternative for multiparametric detection, a camera system for imaging detection has been implemented. A portable, camera-based system of size 13 cm × 4.9 cm × 3.5 cm with six detection areas on an RWG surface area of 11 mm × 7 mm has been demonstrated for the parallel detection of six protein binding kinetics. The signal-to-noise ratio of this system corresponds to a limit of detection of 168 M (24 ng/ml). To further improve the signal-to-noise ratio advanced nanostructure designs are investigated for RWGs. Here, results on multiperiodic and deterministic aperiodic nanostructures are presented. These advanced nanostructures allow for the design of the number and wavelengths of the RWG resonances. In the context of intensity-based readout systems they are particularly interesting for the realization of multi-LED systems. These recent trends suggest that compact point-of-care systems employing disposable test chips with RWG functional areas may reach market in the near future.

  2. Development of a CMOS-compatible PCR chip: comparison of design and system strategies

    Science.gov (United States)

    Erill, Ivan; Campoy, Susana; Rus, José; Fonseca, Luis; Ivorra, Antoni; Navarro, Zenón; Plaza, José A.; Aguiló, Jordi; Barbé, Jordi

    2004-11-01

    In the last decade research in chips for DNA amplification through the polymerase chain reaction (PCR) has been relatively abundant, but has taken very diverse approaches, leaving little common ground for a straightforward comparison of results. Here we report the development of a line of PCR chips that is fully compatible with complementary-metal-oxide-semiconductor (CMOS) technology and its revealing use as a general platform to test and compare a wide range of experimental parameters involved in PCR-chip design and operation. Peltier-heated and polysilicon thin-film driven PCR chips have been produced and directly compared in terms of efficiency, speed and power consumption, showing that thin-film systems run faster and more efficiently than Peltier-based ones, but yield inferior PCR products. Serpentine-like chamber designs have also been compared with standard rectangular designs and with the here reported rhomboidal chamber shape, showing that serpentine-like chambers do not have detrimental effects in PCR efficiency when using non-flow-through schemes, and that chamber design has a strong impact on sample insertion/extraction yields. With an accurate temperature control (±0.2 °C) we have optimized reaction kinetics to yield sound PCR amplifications of 25 µl mixtures in 20 min and with 24.4 s cycle times, confirming that a titrated amount of bovine albumin serum (BSA, 2.5 µg µl-1) is essential to counteract polymerase adsorption at chip walls. The reported use of a CMOS-compatible technological process paves the way for an easy adaption to foundry requirements and for a scalable integration of electro-optic detection and control circuitry.

  3. BESIII ETOF upgrade readout electronics commissioning

    Science.gov (United States)

    Wang, Xiao-Zhuang; Dai, Hong-Liang; Wu, Zhi; Heng, Yue-Kun; Zhang, Jie; Cao, Ping; Ji, Xiao-Lu; Li, Cheng; Sun, Wei-Jia; Wang, Si-Yu; Wang, Yun

    2017-01-01

    It is proposed to upgrade the endcap time-of-flight (ETOF) of the Beijing Spectrometer III (BESIII) with a multi-gap resistive plate chamber (MRPC), aiming at an overall time resolution of about 80 ps. After completing the entire readout electronics system, some experiments, such as heat radiation, radiation hardness and large-current beam tests, have been carried out to confirm the reliability and stability of the readout electronics. An on-detector test of the readout electronics has also been performed with the beam at the BEPCII E3 line. The test results indicate that the readout electronics system fulfills its design requirements. Supported by Chinese Academy of Sciences (1G201331231172010)

  4. Back-Side Readout Silicon Photomultiplier

    Science.gov (United States)

    Choong, Woon-Seng; Holland, Stephen E.

    2012-01-01

    We present a novel structure for the back-side readout silicon photomultipler (SiPM). Current SiPMs are front-illuminated structures with front-side readout, which have relatively small geometric fill factor leading to degradation in their photon detection efficiency (PDE). Back-side readout devices will provide an advantageous solution to achieve high PDE. We designed and investigated a novel structure that would allow back-side readout while creating a region of high electric field optimized for avalanche breakdown. In addition, this structure has relatively high fill factor and also allow direct coupling of individual micro-cell of the SiPM to application-specific integrated circuits. We will discuss the performance that can be attained with this structure through device simulation and the process flow that can be used to fabricate this structure through process simulation. PMID:23564969

  5. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  6. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  7. A 4k-Pixel CTIA Readout for Far IR Photodetector Arrays Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to design a low noise, two-side buttable, 64x64 readout multiplexer with the following key design features: 1- By far the largest readout array developed...

  8. ALIBAVA A portable readout system for silicon microstrip sensors

    CERN Document Server

    Marco-Hernández, R; Casse, G; García, C; Greenall, A; Lacasta, C; Lozano, M; Martí i García, S; Martínez, R; Miñano, M; Pellegrini, G; Smith, N A; Ullán, M

    2007-01-01

    A portable readout system for micro-strip silicon sensors has been developed. The system uses an analogue pipelined readout chip, which was developed for the LHC experiments. The system will be used to characterise the properties of both non-irradiated and irradiated micro-strip sensors. Heavily irradiated sensors will be operated at the Super LHC (SLHC). The system hardware has two main parts: a daughter board and a mother board. The daughter board contains two readout chips, analogue data buffering, power supply regulation and chip-to-sensor fan-in structures. The mother board is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. There is provision for an external trigger input (e.g. scintillator trigger) and a synchronised trigger output for pulsing an external excitation source (e.g. laser system). A prototype of the system will be presented.

  9. A micromachined surface stress sensor with electronic readout

    NARCIS (Netherlands)

    Carlen, E.T.; Weinberg, M.S.; Zapata, A.M.; Borenstein, J.T.

    2008-01-01

    A micromachined surface stress sensor has been fabricated and integrated off chip with a low-noise, differential capacitance, electronic readout circuit. The differential capacitance signal is modulated with a high frequency carrier signal, and the output signal is synchronously demodulated and filt

  10. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  11. Asynchronous Pipeline Micro—Control—Unit (MCU) Chip Design

    Institute of Scientific and Technical Information of China (English)

    ZHOUQian; XUKe; MINHao

    2003-01-01

    The work of this paper includes a researchon asynch ronous design methodology, and a design and implementation of an asynchronous 8-Bit micro-control-unit (MCU). This paper introduces a new application of New-Instruction-Fetching method to detect new instruc-tion which makes this chip fit for demand changeable sys-tem. The instruction set of this asynchronous MCU is compatible with PIC16C6X (Sicrochip Technology Inc).This paper also introduces a new architecture of pipeline,which increases the average speed of chip operation. The asynchronous low power MCU has been fabricated with CSMC (central semiconductor manufacturing corporation)0.6μm CMOS process in Aug 2001. The chip size is about 1.60mm*2.00mm (without taking account of PAD size).Now the test work has been accomplished and the test-ing result of this chip is also presented. The testing result shows that the asynchronous architecture could fulfill all the expected functions, additionally with higher processs peed and lower power consumption than its synchronous counterpart under the same supply voltage.

  12. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    Energy Technology Data Exchange (ETDEWEB)

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  13. Design and synthesis of target-responsive hydrogel for portable visual quantitative detection of uranium with a microfluidic distance-based readout device.

    Science.gov (United States)

    Huang, Yishun; Fang, Luting; Zhu, Zhi; Ma, Yanli; Zhou, Leiji; Chen, Xi; Xu, Dunming; Yang, Chaoyong

    2016-11-15

    Due to uranium's increasing exploitation in nuclear energy and its toxicity to human health, it is of great significance to detect uranium contamination. In particular, development of a rapid, sensitive and portable method is important for personal health care for those who frequently come into contact with uranium ore mining or who investigate leaks at nuclear power plants. The most stable form of uranium in water is uranyl ion (UO2(2+)). In this work, a UO2(2+) responsive smart hydrogel was designed and synthesized for rapid, portable, sensitive detection of UO2(2+). A UO2(2+) dependent DNAzyme complex composed of substrate strand and enzyme strand was utilized to crosslink DNA-grafted polyacrylamide chains to form a DNA hydrogel. Colorimetric analysis was achieved by encapsulating gold nanoparticles (AuNPs) in the DNAzyme-crosslinked hydrogel to indicate the concentration of UO2(2+). Without UO2(2+), the enzyme strand is not active. The presence of UO2(2+) in the sample activates the enzyme strand and triggers the cleavage of the substrate strand from the enzyme strand, thereby decreasing the density of crosslinkers and destabilizing the hydrogel, which then releases the encapsulated AuNPs. As low as 100nM UO2(2+) was visually detected by the naked eye. The target-responsive hydrogel was also demonstrated to be applicable in natural water spiked with UO2(2+). Furthermore, to avoid the visual errors caused by naked eye observation, a previously developed volumetric bar-chart chip (V-Chip) was used to quantitatively detect UO2(2+) concentrations in water by encapsulating Au-Pt nanoparticles in the hydrogel. The UO2(2+) concentrations were visually quantified from the travelling distance of ink-bar on the V-Chip. The method can be used for portable and quantitative detection of uranium in field applications without skilled operators and sophisticated instruments.

  14. Computationally Informed Design of a Multi-Axial Actuated Microfluidic Chip Device.

    Science.gov (United States)

    Gizzi, Alessio; Giannitelli, Sara Maria; Trombetta, Marcella; Cherubini, Christian; Filippi, Simonetta; De Ninno, Adele; Businaro, Luca; Gerardino, Annamaria; Rainer, Alberto

    2017-07-14

    This paper describes the computationally informed design and experimental validation of a microfluidic chip device with multi-axial stretching capabilities. The device, based on PDMS soft-lithography, consisted of a thin porous membrane, mounted between two fluidic compartments, and tensioned via a set of vacuum-driven actuators. A finite element analysis solver implementing a set of different nonlinear elastic and hyperelastic material models was used to drive the design and optimization of chip geometry and to investigate the resulting deformation patterns under multi-axial loading. Computational results were cross-validated by experimental testing of prototypal devices featuring the in silico optimized geometry. The proposed methodology represents a suite of computationally handy simulation tools that might find application in the design and in silico mechanical characterization of a wide range of stretchable microfluidic devices.

  15. Design, Construction and Performance Tests of a Prototype MicroMegas Chamber with Two Readout Planes in a Common Gas Volume

    CERN Document Server

    Brickwedde, Bernard; Schott, Matthias; Yildirim, Eda

    2016-01-01

    In this paper, the design and the performance of a prototype detector based on MicroMegas technology with two detection planes in a common gas volume is discussed. The detector is suited for the forward region of LHC detectors, addressing the high-rate environment and limited available space. Each detection plane has an active area of 9x9 cm^2 with a two-dimensional strip readout and is separated by a common gas region with a height of 14 mm. A micro-mesh, working as a cathode, is placed in the middle of the common gas volume separating it into two individual cells. This setup allows for an angle reconstruction of incoming particles with a precision of 2 mrad. Since this design reduces the impact of multiple scattering effects by the reduced material budget, possible applications for low energy beam experiments can be envisioned. The performance of the prototype detector has been tested with a 4.4 GeV electron beam, provided by the test beam facility at DESY.

  16. Characterization of Silicon Detector Readout Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Jones, M. [Purdue U.

    2015-07-22

    Configuration and calibration of the front-end electronics typical of many silicon detector configurations were investigated in a lab activity based on a pair of strip sensors interfaced with FSSR2 read-out chips and an FPGA. This simple hardware configuration, originally developed for a telescope at the Fermilab Test Beam Facility, was used to measure thresholds and noise on individual readout channels and to study the influence that different configurations of the front-end electronics had on the observed levels of noise in the system. An understanding of the calibration and operation of this small detector system provided an opportunity to explore the architecture of larger systems such as those currently in use at LHC experiments.

  17. Design of an MR image processing module on an FPGA chip.

    Science.gov (United States)

    Li, Limin; Wyrwicz, Alice M

    2015-06-01

    We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

  18. Design verification and performance analysis of Serial AXI Links in Broadcom System-on-Chip

    OpenAIRE

    Sarai, Simran Kaur

    2014-01-01

    Design verification is an essential step in the development of any product. Also referred to as qualification testing, design verification ensures that the product as designed is the same as the product as intended. In this project, design verification and performance analysis of Thin Advanced Extensible Interface Links (T-AXI) is conducted on a Broadcom’s SoC (System on Chip). T-AXI is a Broadcom’s proprietary bus that interfaces all the subsystems on the System-onchip (SoC) to the system me...

  19. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    Kremastiotis, Iraklis; Campbell, Michael; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Kulis, Szymon; Peric, Ivan

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  20. Design and implementation of a microfluidic half adder chip based on double-stranded DNA.

    Science.gov (United States)

    Wang, Jing; Huang, Yourui

    2014-06-01

    In recent years, DNA computing has gained significant research interest. The design of a biochip with DNA computing as a carrier has become a key area in the development of a DNA molecular computer. The half adder, as the basic unit of various arithmetic units, has a complex structure that directly affects the overall complexity of a computer's structure. In this study, a half adder on a microfluidic chip is developed by means of bio-reaction. This technology is combined with a biochip and adopts glass and polydimethylsiloxane to fabricate a microscale hybrid chip. Using a DNA strand as an operand, realization of the half adder on a microfluidic chip is achieved by controlling the annealing and denaturation of double-stranded DNA. The computing results are rapidly and accurately obtained by detecting the presence of double-stranded DNA in a solution by agarose gel electrophoresis. The microfluidic half-adder chip accurately realizes half-adder computations and overcomes the shortcomings of traditional integrated circuit half adders, optical half adders, and chemical molecule half adders, such as complex structure, limited component size, and low accuracy.

  1. A 4096-pixel MAPS device with on-chip data sparsification

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, A. [Universita di Bologna and INFN-Bologna Viale Berti Pichat 6/2, 40127 Bologna (Italy)], E-mail: alessandro.gabrielli@bo.infn.it; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Cenci, R.; Dell' Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M.A.; Lusiani, A.; Marchiori, G.; Morsani, F.; Neri, N.; Paoloni, E.; Rizzo, G.; Walsh, J. [Universita degli Studi di Pisa, INFN-Pisa and Scuola Normale Superiore (Italy); Andreoli, C.; Gaioni, L.; Pozzati, E. [Universita degli Studi di Pavia and INFN-Pavia (Italy)] (and others)

    2009-06-01

    A prototype of a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensor (MAPS) was fabricated via STM 130 nm CMOS technology. Groups of 4x4 pixels form a macro-pixel (MP). The readout architecture is parallel and could overcome the readout speed limit of big matrices. As the output port can only accept one-hit information at a time, an internal queuing system has been provided to face high hit-rate conditions. The ASIC can work in two different manners as it can be connected to an actual full-custom matrix of MAPS or to a digital matrix emulator composed of standard cells, for testing facilities. For both operating modes a slow-control phase is required to load the chip configuration. Previous versions of similar ASICs were designed and tested. The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven extending the flexibility of the system to be also used in first level triggers on tracks in vertex detectors. Preliminary simulations and tests indicate that the readout system can cope with an average hit-rate up to 100 MHz/cm{sup 2} if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

  2. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  3. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  4. Buffer planning for application-specific networks-on-chip design

    Institute of Scientific and Technical Information of China (English)

    YIN ShouYi; LIU LeiBo; WEI ShaoJun

    2009-01-01

    Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used In on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each muter buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements.

  5. Technology Aware Network-on-Chip Connectivity and Synchronization Design

    NARCIS (Netherlands)

    Ludovici, D.

    2011-01-01

    NoCs have been considered as the new design paradigm for large MPSoC systems in the past ten years. In the beginning NoCs were radically different compared to the current state of the art mainly due to the unexpected unique challenges that system designers had to solve with the evolving CMOS technol

  6. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement

  7. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-09-02

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  8. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  9. Design and fabrication of diffractive atom chips for laser cooling and trapping

    CERN Document Server

    Cotter, J P; Griffin, P F; Rabey, I M; Docherty, K; Riis, E; Arnold, A S; Hinds, E A

    2016-01-01

    It has recently been shown that optical reflection gratings fabricated directly into an atom chip provide a simple and effective way to trap and cool substantial clouds of atoms [1,2]. In this article we describe how the gratings are designed and micro-fabricated and we characterise their optical properties, which determine their effectiveness as a cold atom source. We use simple scalar diffraction theory to understand how the morphology of the gratings determines the power in the diffracted beams.

  10. Design of a Virtual Component Neutral Network-on-Chip Transaction Layer

    CERN Document Server

    Martin, Philippe

    2011-01-01

    Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communication standards. This paper describes a number of issues faced when designing a VC-neutral NoC, i.e. compatible with standards such as AHB 2.0, AXI, VCI, OCP, and various other proprietary protocols, and how a layered approach to communication helps solve these issues.

  11. Design and simulation of on-chip lossy transmission line pairs

    OpenAIRE

    Demeester, Thomas; De Zutter, Daniël

    2008-01-01

    A quasi-TM reciprocity based multi-conductor transmission line model is used to investigate the influence of the geometry on the performance of on-chip transmission line pairs for high-frequency differential signal transmission. It is shown that both the knowledge of the fundamental transmission line modes and of the internal impedance of both connected circuits, are essential for a good design.

  12. AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

    Directory of Open Access Journals (Sweden)

    Rehan Maroof

    2011-09-01

    Full Text Available Traditional System-on-Chip (SoC design employed shared buses for data transfer among various subsystems. As So Cs become more complex involving a larger number of subsystems, traditional bus based architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC. A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

  13. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  14. Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

    Science.gov (United States)

    Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

    2013-06-21

    We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

  15. Prototype readout electronics for the upgraded ALICE Inner Tracking System

    Science.gov (United States)

    Sielewicz, K. M.; Aglieri Rinella, G.; Bonora, M.; Ferencei, J.; Giubilato, P.; Rossewij, M. J.; Schambach, J.; Vanat, T.

    2017-01-01

    The ALICE Collaboration is preparing a major upgrade to the experimental apparatus. A key element of the upgrade is the construction of a new silicon-based Inner Tracking System containing 12 Gpixels in an area of 10 m2. Its readout system consists of 192 readout units that control the pixel sensors and the power units, and deliver the sensor data to the counting room. A prototype readout board has been designed to test: the interface between the sensor modules and the readout electronics, the signal integrity and reliability of data transfer, the interface to the ALICE DAQ and trigger, and the susceptibility of the system to the expected radiation level.

  16. LHCb: A new Readout Control system for the LHCb Upgrade

    CERN Multimedia

    Alessio, F

    2012-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation of a new Readout Control system for the LHCb upgrade. The system is based on FPGAs and bi-directional links for the control of the entire readout architecture. First results on the validation of the system are also given.

  17. A new DOI detector design using discrete crystal array with depth-dependent reflector patterns and single-ended readout

    Science.gov (United States)

    Lee, Seung-Jae; Lee, Chaeyeong; Kang, Jihoon; Chung, Yong Hyun

    2017-01-01

    We developed a depth of interaction (DOI) positron emission tomography (PET) detector using depth-dependent reflector patterns in a discrete crystal array. Due to the different reflector patterns at depth, light distribution was changed relative to depth. As a preliminary experiment, we measured DOI detector module crystal identification performance. The crystal consisted of a 9×9 array of 2 mmx2 mmx20 mm lutetium-yttrium oxyorthosilicate (LYSO) crystals. The crystal array was optically coupled to a 64-channel position-sensitive photomultiplier tube with a 2 mmx2 mm anode size and an 18.1 mmx18.1 mm effective area. We obtained the flood image with an Anger-type calculation. DOI layers and 9×9 pixels were well distinguished in the obtained images. Preclinical PET scanners based on this detector design offer the prospect of high and uniform spatial resolution.

  18. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  19. Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

    Directory of Open Access Journals (Sweden)

    Fernando Gutierrez

    2017-03-01

    Full Text Available To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC. With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

  20. Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

    CERN Document Server

    Soliman, Ahmed H M; El-Bably, M; Keshk, Hesham M A M

    2012-01-01

    The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementing a NoC on an FPGA does not only reduce the cost but also decreases programming and verification cycles. In this paper, an Asynchronous NoC has been implemented on a SPARTAN-3E\\textregistered device. The NoC supports basic transactions of both widely used on-chip interconnection standards, the Open Core Protocol (OCP) and the WISHBONE Protocol. Although, FPGA devices are synchronous in nature, it has been shown that they can be used to prototype a Global Asynchronous Local Synchronous (GALS) systems, comprising an Asynchr...

  1. Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

    CERN Document Server

    Teuscher, Christof

    2007-01-01

    Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long- versus short-range connections, and measure the net...

  2. Circuit Design of On-Chip BP Learning Neural Network with Programmable Neuron Characteristics

    Institute of Scientific and Technical Information of China (English)

    卢纯; 石秉学; 陈卢

    2000-01-01

    A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning.

  3. USB 3.0 readout and time-walk correction method for Timepix3 detector

    Science.gov (United States)

    Turecek, D.; Jakubek, J.; Soukup, P.

    2016-12-01

    The hybrid particle counting pixel detectors of Medipix family are well known. In this contribution we present new USB 3.0 based interface AdvaDAQ for Timepix3 detector. The AdvaDAQ interface is designed with a maximal emphasis to the flexibility. It is successor of FitPIX interface developed in IEAP CTU in Prague. Its modular architecture supports all Medipix/Timepix chips and all their different readout modes: Medipix2, Timepix (serial and parallel), Medipix3 and Timepix3. The high bandwidth of USB 3.0 permits readout of 1700 full frames per second with Timepix or 8 channel data acquisition from Timepix3 at frequency of 320 MHz. The control and data acquisition is integrated in a multiplatform PiXet software (MS Windows, Mac OS, Linux). In the second part of the publication a new method for correction of the time-walk effect in Timepix3 is described. Moreover, a fully spectroscopic X-ray imaging with Timepix3 detector operated in the ToT mode (Time-over-Threshold) is presented. It is shown that the AdvaDAQ's readout speed is sufficient to perform spectroscopic measurement at full intensity of radiographic setups equipped with nano- or micro-focus X-ray tubes.

  4. A Design of ABC95 Array Computer Multi-function Interconnection Chips

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have enough I/O band and flexible communications between Pes. The authors designed the interconnecting network chips of ABC95 and realized a form of multi-function interconnection. The multi-function interconnecting network supports conflict-free access from processors to memory matrix and the MESH network of enhanced processors to processor communications. The design scheme has been proved feasible by experiment.

  5. Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

    CERN Document Server

    Martina, Maurizio

    2009-01-01

    This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.

  6. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  7. A Readout System for the LHCb Outer Tracker

    CERN Document Server

    Wiedner, D; Apeldorn , G; Bachmann, S; Bagaturi , I; Bauer, T; Berkien, A; Blouw, J; Bos, E; Deisenroth, M; Dubitzki, R; Eisele, F; Guz , Y; Haas, T; Hommels, B; Ketel, T; Knopf , J; Merk , M; Nardulli , J; Nedos, M; Pellegrino, A; Rausch, A; Rusnyak, R; Schwemmer, R; Simoni, E; Sluijk , T; Spaan, B; Spelt , J; Stange, U; van Tilburg, J; Trunk , U; Tuning , N; Uwer, U; Vankow , P; Warda, K

    2006-01-01

    The LHCb Outer Tracker is composed of 55 000 straw drift tubes. The requirements for the OT electronics are the precise (1 ns) drift time measurement at 6 % occupancy and 1 MHz readout. Charge signals from the straw detector are amplified, shaped and discriminated by ATLAS ASDBLR chips. Drift-times are determined and stored in the OTIS TDC and put out to a GOL serializer at L0 accept. Optical fibres carry the data 90 m to the TELL1 acquisition board. The full readout chain performed well in an e- test beam.

  8. Designing 2D and 3D network-on-chip architectures

    CERN Document Server

    Tatas, Konstantinos; Soudris, Dimitrios; Jantsch, Axel

    2014-01-01

    This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

  9. Design, fabrication and characterization of drug delivery systems based on lab-on-a-chip technology.

    Science.gov (United States)

    Nguyen, Nam-Trung; Shaegh, Seyed Ali Mousavi; Kashaninejad, Navid; Phan, Dinh-Tuan

    2013-11-01

    Lab-on-a-chip technology is an emerging field evolving from the recent advances of micro- and nanotechnologies. The technology allows the integration of various components into a single microdevice. Microfluidics, the science and engineering of fluid flow in microscale, is the enabling underlying concept for lab-on-a-chip technology. The present paper reviews the design, fabrication and characterization of drug delivery systems based on this amazing technology. The systems are categorized and discussed according to the scales at which the drug is administered. Starting with the fundamentals on scaling laws of mass transfer and basic fabrication techniques, the paper reviews and discusses drug delivery devices for cellular, tissue and organism levels. At the cellular level, a concentration gradient generator integrated with a cell culture platform is the main drug delivery scheme of interest. At the tissue level, the synthesis of smart particles as drug carriers using lab-on-a-chip technology is the main focus of recent developments. At the organism level, microneedles and implantable devices with fluid-handling components are the main drug delivery systems. For drug delivery to a small organism that can fit into a microchip, devices similar to those of cellular level can be used.

  10. Blood cleaner on-chip design for artificial human kidney manipulation

    Directory of Open Access Journals (Sweden)

    Suwanpayak N

    2011-05-01

    Full Text Available N Suwanpayak1, MA Jalil2, MS Aziz3, FD Ismail3, J Ali3, PP Yupapin11Nanoscale Science and Engineering Research Alliance (N'SERA, Advanced Research Center for Photonics, Faculty of Science, King Mongkut's Institute of Technology, Ladkrabang, Bangkok, Thailand; 2Ibnu Sina Institute of Fundamental Science Studies (IIS, 3Institute of Advanced Photonics Science, Nanotechnology Research Alliance, Universiti Teknologi Malaysia, Johor Bahru, MalaysiaAbstract: A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney, and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.Keywords: optical trapping, blood dialysis, blood cleaner, human kidney manipulation

  11. CMOS current-mode neural associative memory design with on-chip learning.

    Science.gov (United States)

    Wu, C Y; Lan, J F

    1996-01-01

    Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.

  12. Description of the TRT Readout Scheme

    CERN Document Server

    Luehring, F C

    2002-01-01

    This paper documents the TRT detector readout scheme. A description is provided of the data buffers used in the TRT readout chain: the single TRT channel output data format, the DTMROC output data buffer format, the TRT-ROD input FIFO data format, the TRT-ROD output buffer format, and the ROB output buffer data format. Also documented are the current designs for the TRT-ROD zero suppression and data compression schemes. A proposal is presented for ordering the data generated by individual TRT channels suitably for Level-2 triggering, Level-3 triggering and offline data processing.

  13. Imaging achievements with the Vernier readout

    CERN Document Server

    Lapington, J S; Worth, L B C; Tandy, J A

    2002-01-01

    We describe the Vernier anode, a high resolution and charge division image readout for microchannel plate detectors. It comprises a planar structure of insulated electrodes deposited on an insulating substrate. The charge cloud from an event is divided amongst all nine electrodes and the charge ratio uniquely determines the two-dimensional position coordinate of the charge centroid. We discuss the design of the anode pattern and describe the advantages offered by this readout. The cyclic variation of the electrode structure allows the image resolution to exceed the charge measurement resolution and enables the entire active area of the readout to be utilized. In addition, fixed pattern noise is greatly reduced. We present results demonstrating the position resolution and image linearity. A position resolution of 10 mu m FWHM is demonstrated and the overall imaging performance is shown to be limited by the microchannel plate pore spacing. We present measurements of the image distortions and describe techniques...

  14. The NA60 experiment readout architecture

    CERN Document Server

    Floris, M; Usai, G L; David, A; Rosinsky, P; Ohnishi, H

    2004-01-01

    The NA60 experiment was designed to identify signatures of a new state of matter, the Quark Gluon Plasma, in heavy-ion collisions at the CERN Super Proton Synchroton. The apparatus is composed of four main detectors: a muon spectrometer (MS), a zero degree calorimeter (ZDC), a silicon vertex telescope (VT), and a silicon microstrip beam tracker (BT). The readout of the whole experiment is based on a PCI architecture. The basic unit is a general purpose PCI card, interfaced to the different subdetectors via custom mezzanine cards. This allowed us to successfully implement several completely different readout protocols (from the VME like protocol of the MS to the custom protocol of the pixel telescope). The system was fully tested with proton and ion beams, and several million events were collected in 2002 and 2003. This paper presents the readout architecture of NA60, with particular emphasis on the PCI layer common to all the subdetectors. (16 refs).

  15. TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

    2011-08-11

    The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

  16. Dual-readout Calorimetry

    CERN Document Server

    Akchurin, N; Cardini, A.; Cascella, M.; Cei, F.; De Pedis, D.; Fracchia, S.; Franchino, S.; Fraternali, M.; Gaudio, G.; Genova, P.; Hauptman, J.; La Rotonda, L.; Lee, S.; Livan, M.; Meoni, E.; Moggi, A.; Pinci, D.; Policicchio, A.; Saraiva, J.G.; Sill, A.; Venturelli, T.; Wigmans, R.

    2013-01-01

    The RD52 Project at CERN is a pure instrumentation experiment whose goal is to un- derstand the fundamental limitations to hadronic energy resolution, and other aspects of energy measurement, in high energy calorimeters. We have found that dual-readout calorimetry provides heretofore unprecedented information event-by-event for energy resolution, linearity of response, ease and robustness of calibration, fidelity of data, and particle identification, including energy lost to binding energy in nuclear break-up. We believe that hadronic energy resolutions of {\\sigma}/E $\\approx$ 1 - 2% are within reach for dual-readout calorimeters, enabling for the first time comparable measurement preci- sions on electrons, photons, muons, and quarks (jets). We briefly describe our current progress and near-term future plans. Complete information on all aspects of our work is available at the RD52 website http://highenergy.phys.ttu.edu/dream/.

  17. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    KAUST Repository

    Gooneratne, Chinthaka P.

    2016-08-26

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device

  18. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Chinthaka P. Gooneratne

    2016-08-01

    Full Text Available The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA for the manipulation of superparamagnetic beads (SPBs, and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads® demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead® SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads® travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

  19. On-Chip Magnetic Bead Manipulation and Detection Using a Magnetoresistive Sensor-Based Micro-Chip: Design Considerations and Experimental Characterization.

    Science.gov (United States)

    Gooneratne, Chinthaka P; Kodzius, Rimantas; Li, Fuquan; Foulds, Ian G; Kosel, Jürgen

    2016-08-26

    The remarkable advantages micro-chip platforms offer over cumbersome, time-consuming equipment currently in use for bio-analysis are well documented. In this research, a micro-chip that includes a unique magnetic actuator (MA) for the manipulation of superparamagnetic beads (SPBs), and a magnetoresistive sensor for the detection of SPBs is presented. A design methodology, which takes into account the magnetic volume of SPBs, diffusion and heat transfer phenomena, is presented with the aid of numerical analysis to optimize the parameters of the MA. The MA was employed as a magnetic flux generator and experimental analysis with commercially available COMPEL™ and Dynabeads(®) demonstrated the ability of the MA to precisely transport a small number of SPBs over long distances and concentrate SPBs to a sensing site for detection. Moreover, the velocities of COMPEL™ and Dynabead(®) SPBs were correlated to their magnetic volumes and were in good agreement with numerical model predictions. We found that 2.8 μm Dynabeads(®) travel faster, and can be attracted to a magnetic source from a longer distance, than 6.2 μm COMPEL™ beads at magnetic flux magnitudes of less than 10 mT. The micro-chip system could easily be integrated with electronic circuitry and microfluidic functions, paving the way for an on-chip biomolecule quantification device.

  20. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either...... synchronous or mesochronous, but both approaches have their limitations: a globally synchronous NOC is no longer feasible in today's sub micron technologies and a mesochronous NOC requires special FIFO-based synchronizers in all input ports of all routers in order to accommodate for clock phase differences....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...

  1. Design and implementation of a high-speed reconfigurable cipher chip

    Institute of Scientific and Technical Information of China (English)

    Gao Nana; Li Zhancai; Wang Qin

    2006-01-01

    A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.

  2. Dual-readout Calorimetry

    OpenAIRE

    Akchurin, N.; Bedeschi, F.; Cardini, A.; Cascella, M.; Cei, F.; Pedis, D.; Fracchia, S.; Franchino, S.; Fraternali, M.; Gaudio, G.; P. Genova; Hauptman, J.; La Rotonda, L.; Lee, S.; Livan, M.(INFN Sezione di Pavia, Pavia, Italy)

    2013-01-01

    The RD52 Project at CERN is a pure instrumentation experiment whose goal is to understand the fundamental limitations to hadronic energy resolution, and other aspects of energy measurement, in high energy calorimeters. We have found that dual-readout calorimetry provides heretofore unprecedented information event-by-event for energy resolution, linearity of response, ease and robustness of calibration, fidelity of data, and particle identification, including energy lost to binding energy in n...

  3. The FE-I4 pixel readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@bl.gov [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Arutinov, D.; Barbero, M. [University of Bonn, Bonn (Germany); Beccherle, R. [Istituto Nazionale di Fisica Nucleare Sezione di Genova, Genova (Italy); Dube, S.; Elledge, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Fleury, J. [Laboratoire de l' Accelerateur Lineaire, Orsay (France); Fougeron, D.; Gensolen, F. [Centre de Physique des Particules de Marseille, Marseille (France); Gnani, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Gromov, V. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Hemperek, T.; Karagounis, M. [University of Bonn, Bonn (Germany); Kluit, R. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Kruth, A. [University of Bonn, Bonn (Germany); Mekkaoui, A. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Menouni, M. [Centre de Physique des Particules de Marseille, Marseille (France); Schipper, J.-D. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands)

    2011-04-21

    A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

  4. A reconfigurable image tube using an external electronic image readout

    Science.gov (United States)

    Lapington, J. S.; Howorth, J. R.; Milnes, J. S.

    2005-08-01

    We have designed and built a sealed tube microchannel plate (MCP) intensifier for optical/NUV photon counting applications suitable for 18, 25 and 40 mm diameter formats. The intensifier uses an electronic image readout to provide direct conversion of event position into electronic signals, without the drawbacks associated with phosphor screens and subsequent optical detection. The Image Charge technique is used to remove the readout from the intensifier vacuum enclosure, obviating the requirement for additional electrical vacuum feedthroughs and for the readout pattern to be UHV compatible. The charge signal from an MCP intensifier is capacitively coupled via a thin dielectric vacuum window to the electronic image readout, which is external to the sealed intensifier tube. The readout pattern is a separate item held in proximity to the dielectric window and can be easily detached, making the system easily reconfigurable. Since the readout pattern detects induced charge and is external to the tube, it can be constructed as a multilayer, eliminating the requirement for narrow insulator gaps and allowing it to be constructed using standard PCB manufacturing tolerances. We describe two readout patterns, the tetra wedge anode (TWA), an optimized 4 electrode device similar to the wedge and strip anode (WSA) but with a factor 2 improvement in resolution, and an 8 channel high speed 50 ohm device, both manufactured as multilayer PCBs. We present results of the detector imaging performance, image resolution, linearity and stability, and discuss the development of an integrated readout and electronics device based on these designs.

  5. Analysis and design of networks-on-chip under high process variation

    CERN Document Server

    Ezz-Eldin, Rabab; Hamed, Hesham F A

    2015-01-01

    This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies;  Includes an overview of the sy...

  6. Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

    Science.gov (United States)

    Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

    2017-03-01

    CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

  7. Noise and mismatch optimization for capacitive MEMS readout

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Chong; Wu Qisong; Yin Tao; Yang Haigang, E-mail: yanghg@mail.ie.ac.c [Institute of Electronics, Chinese Academy of Sciences, Beijing 100190 (China)

    2009-11-15

    This paper presents a high precision CMOS readout circuit for a capacitive MEMS gyroscope. A continuous time topology is employed as well as the chopper noise cancelling technique. A detailed analysis of the noise and mismatch of the capacitive readout circuit is given. The analysis and measurement results have shown that thermal noise dominates in the proposed circuit, and several approaches should be used for both noise and mismatch optimization. The circuit chip operates under a single 5 V supply, and has a measured capacitance resolution of 0.2 aF/sq rootHz. With such a readout circuit, the gyroscope can accurately measure the angular rate with a sensitivity of 15.3 mV/{sup 0}/s. (semiconductor integrated circuits)

  8. Noise and mismatch optimization for capacitive MEMS readout

    Institute of Scientific and Technical Information of China (English)

    Zhang Chong; Wu Qisong; Yin Tao; Yang Haigang

    2009-01-01

    This paper presents a high precision CMOS readout circuit for a capacitive MEMS gyroscope. A continuous time topology is employed as well as the chopper noise cancelling technique. A detailed analysis of the noise and mismatch of the capacitive readout circuit is given. The analysis and measurement results have shown that thermal noise dominates in the proposed circuit, and several approaches should be used for both noise and mismatch optimization. The circuit chip operates under a single 5 V supply, and has a measured capacitance resolution of 0.2 aF/√Hz. With such a readout circuit, the gyroscope can accurately measure the angular rate with a sensitivity of 15.3 mV/°/s.

  9. Improvement of Event Synchronization in the ATLAS Pixel Readout Development

    Science.gov (United States)

    Adams, Logan; Atlas Collaboration

    2017-01-01

    As the LHC continues in Run2, the B-Layer still uses the Atlas-SiROD Pixel readout system initially developed for Run 1. The higher luminosity occurring during Run 2 results in higher occupancy causing increased desynchronization errors in the Pixel Readout. In order to ensure lasting operation of the B-Layer until it is replaced after Run 3, changes were made to the firmware and software to add debug capabilities to identify when the errors are crossing certain thresholds and change the internal control logic accordingly. These features also allow for better debugging of the Event Counter Reset addition to the firmware. This talk will focus on the features implemented and measurements to demonstrate the positive impact on the Pixel DAQ system. A Pixel front-end chip emulator which can be used for readout system development beyond Run 3 will also be discussed. Presenter is Logan Adams, University of Washington.

  10. A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

    Energy Technology Data Exchange (ETDEWEB)

    Heuvelmans, S; Boerrigter, M, E-mail: sander.heuvelmans@bruco.nl [Bruco integrated circuits BV, Oostermaat 2, 7623 CS (Netherlands)

    2011-01-15

    Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

  11. Optimizing design of triplexer chip with low insert loss and high isolation based on planar lightwave circuit

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    Design optimization of a novel integrated triplexer based on planar lightwave circuit (PLC) for fiber-to-the-home applications is described. The two-mode interference coupler and Mach-Zehnder interference are used to construct the filter chip.Simulation results of high isolation and low insertion loss are gotten for proposed design. Technique tolerance is improved for fabricating device.

  12. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  13. A 4-Channel Waveform Sampling ASIC in 0.13 μm CMOS for front-end Readout of Large-Area Micro-Channel Plate Detectors

    Science.gov (United States)

    Oberla, E.; Grabas, H.; Bogdan, M.; Frisch, H.; Genat, J. F.; Nishimura, K.; Varner, G.; Wong, A.

    We describe here the development of PSEC-3, a custom integrated circuit designed in the IBM-8RF 0.13 μm CMOS process and intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this chip has been designed as a prototype application-specific integrated circuit (ASIC) for the front-end transmission line readout of large-area micro-channel plate photomultiplier tubes (MCP-PMTs). With 4 channels, PSEC-3 has a buffer depth of 256 samples on each channel, a chip-parallel ramp-compare ADC, and a serial data readout that includes the capability for region-of-interest windowing to reduce dead time. Chip calibrations and performance results, including achieved sampling rates of 2.5-17 GSa/s, are reported. Some design issues are identified, in particular the dependence of analog bandwidth on location in the sampling array. The causes have been found and addressed in a subsequent PSEC-4 submission.

  14. SLIM5 beam test results for thin striplet detector and fast readout beam telescope

    Energy Technology Data Exchange (ETDEWEB)

    Vitale, Lorenzo, E-mail: lorenzo.vitale@ts.infn.i [Universita degli Studi di Trieste and INFN-Trieste (Italy); Bruschi, M.; Di Sipio, R.; Fabbri, L.; Giacobbe, B.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini, N.; Spighi, R.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Universita degli Studi di Bologna and INFN-Bologna (Italy); Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Ceccanti, M. [Universita degli Studi di Pisa and INFN-Pisa (Italy)

    2010-05-21

    In September 2008 the SLIM5 collaboration submitted a low material budget silicon demonstrator to test with 12 GeV/c protons, at the PS-T9 test-beam at CERN. Two different detectors were placed as DUTs inside a high-resolution and fast-readout beam telescope. The first DUT was a high resistivity double sided silicon detector, with short strips ('striplets') and with reduced thickness, at 45{sup 0} angle to the detector's edge, readout by the data-driven FSSR2 chip. The other one was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, providing digital sparsified readout. In the following, I present the striplets and also the beam telescope characteristics, with some details about the frontend readout (based on the FSSR2 chip) and some preliminary results of the data-analysis.

  15. Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

    CERN Document Server

    Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

    2014-01-01

    In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

  16. A novel readout system for wireless passive pressure sensors

    Science.gov (United States)

    Zhang, Huixin; Hong, Yingping; Ge, Binger; Liang, Ting; Xiong, Jijun

    2014-03-01

    This paper presents a novel readout system for wireless passive pressure sensors based on the inductively coupled inductor and cavity (LC) resonant circuits. The proposed system consists of a reader antenna inductively coupled to the sensor circuit, a readout circuit, and a personal computer (PC) post processing unit. The readout circuit generates a voltage signal representing the sensor's capacitance. The frequency of the reader antenna driving signal is a constant, which is equal to the sensor's resonant frequency at zero pressure. Based on mechanical and electrical modeling, the pressure sensor design based on the high temperature co-fired ceramic (HTCC) technology is conducted and discussed. The functionality and accuracy of the readout system are tested with a voltage-capacitance measurement system and demonstrated in a realistic pressure measurement environment, so that the overall performance and the feasibility of the readout system are proved.

  17. Recent developments in neurodynamics and their impact on the design of neuro-chips.

    Science.gov (United States)

    Ramacher, U; Schildberg, P

    1993-12-01

    Neurons can be modeled either by equations or differential equations. For the latter, a low-pass filter must be added to the analog function blocks associated with the McCullogh and Pitts type of static neuron in order to provide the time-dependent neuron solution. The low-pass filter enhances stability and enables a time-continuous analog implementation much more compact than that attained with time-discrete analog or pure digital design. A few examples of equations as well as differential equations are known for that part of learning. However, much less than for the recall mode, it is clear how to design learning neuro-chips for temporal pattern processing. It is shown here that a partial differential equation can be used to provide a unified description of both the recall and learning dynamics of a neural network as well as to investigate systematically the VLSI potential for analog time-continuous neuro-chips. It turns out that the recall and learning dynamics can be divided into causal as well as noncausal solutions. The first type of solution includes oscillating or spiking neurons. The second type of solution allows for a much simpler signal representation but leads to the problem of storing the temporal signal of each neuron for as long a time as a single pattern lasts. As this is prohibitive for larger networks and time-varying patterns, the analog VLSI implementation of causal neuron models is suggested.

  18. Design of automatic curtain controlled by wireless based on single chip 51 microcomputer

    Science.gov (United States)

    Han, Dafeng; Chen, Xiaoning

    2017-08-01

    In order to realize the wireless control of the domestic intelligent curtains, a set of wireless intelligent curtain control system based on 51 single chip microcomputer have been designed in this paper. The intelligent curtain can work in the manual mode, automatic mode and sleep mode and can be carried out by the button and mobile phone APP mode loop switch. Through the photosensitive resistance module and human pyroelectric infrared sensor to collect the indoor light value and the data whether there is the person in the room, and then after single chip processing, the motor drive module is controlled to realize the positive inversion of the asynchronous motor, the intelligent opening and closing of the curtain have been realized. The operation of the motor can be stopped under the action of the switch and the curtain opening and closing and timing switch can be controlled through the keys and mobile phone APP. The optical fiber intensity, working mode, curtain state and system time are displayed by LCD1602. The system has a high reliability and security under practical testing and with the popularity and development of smart home, the design has broad market prospects.

  19. R&D on a novel spectro-imaging polarimeter with Micromegas detectors and a Caliste readout system

    Energy Technology Data Exchange (ETDEWEB)

    Attié, D., E-mail: david.attie@cea.fr [DSM-IRFU, CEA Saclay, Centre de Saclay, F-91191 Gif-sur-Yvette (France); Blondel, C. [AIM, CEA/DSM-CNRS-Université Paris Diderot, IRFU/Service d’Astrophysique (France); Boilevin-Kayl, L.; Desforges, D.; Ferrer-Ribas, E.; Giomataris, I.; Gevin, O.; Jeanneau, F. [DSM-IRFU, CEA Saclay, Centre de Saclay, F-91191 Gif-sur-Yvette (France); Limousin, O.; Meuris, A. [AIM, CEA/DSM-CNRS-Université Paris Diderot, IRFU/Service d’Astrophysique (France); Papaevangelou, T.; Peyaud, A. [DSM-IRFU, CEA Saclay, Centre de Saclay, F-91191 Gif-sur-Yvette (France)

    2015-07-01

    Micromegas detectors, part of the Micro-Pattern Gaseous Detectors (MPGD) family, are used in a very wide range of applications in the High Energy Physics community but also in astroparticle and neutrino physics. In most of the Micromegas applications the design of the detector vessel and the readout plane is extremely coupled. A way of dissociating these two components would be by separating the amplification structure and the detector volume from the readout plane and electronics. This is achieved with the so called piggyback Micromegas detectors. They open up new possibilities of applications in terms of adaptability to new electronics. In particular piggyback resistive Micromegas can be easily coupled to modern pixel array electronic ASICs. First tests have been carried out with a Medipix chip where the protection of the resistive layer has been proved. The results of very recent tests coupling piggyback Micromegas with the readout module of Caliste are presented. Caliste is a high performance spectro-imager with event time-tagging capability, able to detect photons between 2 keV and 250 keV in the context of a spatial micro spectro-imaging polarimetrer. In the current application, with the Piggyback Micromegas, we use the readout module only as the sensitive detector. We benefit of the good spatial resolution thanks to the high density readout pixels (~600 μm pixel pitch), to the low noise, to the low power and to the radiation hard integrated front-end IDEF-X electronics. The advantage of such a device is to have a high gain, low noise, low threshold, and robust detector operating at room temperature. This would be very attractive for spatial applications, for instance X-ray polarisation.

  20. The UK ROB-in,A prototype ATLAS readout buffer input module

    CERN Document Server

    Boorman, G; Cranfield, R; Crone, G J; Green, B; Strong, J

    2000-01-01

    This paper describes the specification, design, operation, performanceand status of the UK ROB-in. The UK ROB-in is a prototype ATLAS ReadOut Buffer (ROB) input module intended both as a prototype componentfor the final system and for use in prototyping other parts of theATLAS trigger/DAQ system. Its function is to buffer event fragments atthe rate expected on a single detector Read Out Link and output orrelease selected fragments on request. The module is available in PCIor PMC formats and is designed around a MACH5 CPLD and an Intel i960microprocessor, together with appropriate SRAM and FIFO chips. Ittakes input via an S-LINK daughter-board connector at a continuousrate of up to 132 MB/s. Its functionality is based on the requirementsdescribed in the ROB-in User Requirements Document, itself based onrequirements defined for a complete ATLAS ROB.

  1. Development of analog-digital readout integrated circuits for infrared focal plane arrays

    Science.gov (United States)

    Dem'yanenko, M. A.; Kozlov, A. I.; Marchishin, I. V.; Ovsyuk, V. N.

    2016-11-01

    This paper describes the design of readout integrated circuits (ROICs) for hybrid infrared focal plane arrays (IR FPAs). This work contains the estimation of the noise equivalent temperature difference (NETD) of IR FPAs based on frame and row integration of pixel signals in the spectral ranges of 8 to 14 and 3 to 5 μm. This paper also describes the development of ROICs for IR FPAs created with the use of mercury—cadmium—telluride (MCT) photodiodes and quantum well infrared photodetectors (QWIPs). The designed ROICs ensure the use of matrix and linear photodetector chips, including those with increased dark currents, in order to produce IR FPAs with temperature resolution corresponding to the world level of array analogs.

  2. DIRAC v2 a DIgital Readout Asic for hadronic Calorimeter

    CERN Document Server

    Gaglione, R; Chefdeville, M; Drancourt, C; Vouters, G

    2009-01-01

    DIRAC is a 64 channel mixed-signal readout integrated circuit designed for Micro-Pattern Gaseous Detectors (MICROMEGAS, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physic requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). The DIRAC ASIC has been especially designed for these constraints. Each channel of the DIRAC chip is made of a 4 gains charge preamplifier, a DC-servo loop, 3 switched comparators and a digital memory, thus providing additional energy information for a hit. A bulk MICROMEGAS detector with embedded DIRAC v1 ASIC has been built. The tests of this assembly, both in laboratory with X-Rays and in a beam at CERN are presented, demonstrating the feasibility of a bulk MICROMEGAS detector with embedded electronics. The second version of...

  3. Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

    CERN Document Server

    Liberali, Valentino; The ATLAS collaboration

    2016-01-01

    We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

  4. Development and simulation results of a sparsification and readout circuit for wide pixel matrices

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, A.; Giorgi, F. [University and INFN of Bologna (Italy); Morsani, F. [University and INFN of Pisa (Italy); Villa, M. [University and INFN of Bologna (Italy)

    2011-06-15

    In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: (http://www.pi.infn.it/SuperB)]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, (doi:10.1016/j.nima.2010.05.039)]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm{sup 2} with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack . s{sup -1} . cm{sup -2} with a temporal resolution below 1 {mu}s. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.

  5. Development and simulation results of a sparsification and readout circuit for wide pixel matrices

    Science.gov (United States)

    Gabrielli, A.; Giorgi, F.; Morsani, F.; Villa, M.

    2011-06-01

    In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: http://www.pi.infn.it/SuperB]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, doi:10.1016/j.nima.2010.05.039]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm 2 with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack ṡ s -1 ṡ cm -2 with a temporal resolution below 1 μs. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.

  6. Design of Antenna-on-Chip, Antenna-on-Package and Detectors from RF, Microwave to THz Frequency Range in SiGe-C Technology

    NARCIS (Netherlands)

    Wane, S; Bardy, S.; Heijster, R.M.E.M. van; Goulet, F.; Gamand, P.

    2011-01-01

    Design solutions for on-chip signal detectors, Antenna-on- Chip and Antenna-on-Package (with Bond Wire elements), from RF, Microwave to THz frequency range, using state-of-theart SiGe BiCMOS technology are presented. Both CML and CMOS detectors are designed, fabricated and compared in terms of their

  7. Design of flat-band superprism structures for on-chip spectroscopy.

    Science.gov (United States)

    Gao, Boshen; Shi, Zhimin; Boyd, Robert W

    2015-03-01

    We present a systematic design procedure of photonic crystal (PhC) superprism structures for on-chip spectroscopic applications. In specific, we propose a new figure of merit, namely the angular-group-dispersion-bandwidth-product (AGDBP) to quantitatively describe the spectroscopic performance of PhC superprism structures, and an optimum PhC structure for spectroscopic applications should have large angular group dispersion over a large bandwidth, i.e., a flat-top dispersion profile. We demonstrate the advantage of such a new design consideration by optimizing the geometry of a two-dimensional parallelogram-lattice PhC superprism structure. The performance of such a superprism spectrometer is further analyzed numerically using finite-difference time-domain simulations, which out-performs current implementations in terms of the number of achievable output spectral channels.

  8. Design of On-chip Power Transport and Coupling Components for a Silicon Woodpile Accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Ziran; Ng, C.; McGuinness, C.; Colby, E.; /SLAC

    2011-05-23

    Three-dimensional woodpile photonic bandgap (PBG) waveguide enables high-gradient and efficient laser driven acceleration, while various accelerator components, including laser couplers, power transmission lines, woodpile accelerating and focusing waveguides, and energy recycling resonators, can be potentially integrated on a single monolithic structure via lithographic fabrications. This paper will present designs of this on-chip accelerator based on silicon-on-insulator (SOI) waveguide. Laser power is coupled from free-space or fiber into SOI waveguide by grating structures on the silicon surface, split into multiple channels to excite individual accelerator cells, and eventually gets merged into the power recycle pathway. Design and simulation results will be presented regarding various coupling components involved in this network.

  9. A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed For Evolvability

    DEFF Research Database (Denmark)

    Patou, François; Dimaki, Maria; Svendsen, Winnie Edith

    2015-01-01

    Unprecedented knowledge levels in life sciences along with technological advances in micro- and nanotechnologies and microfluidics have recently conditioned the advent of Lab-on-Chip (LoC) devices for In-Vitro Medical Testing (IVMT). Combined with smart-mobile technologies, LoCs are pervasively...... giving rise to opportunities to better diagnose disease, predict and monitor personalised treatment efficacy, or provide healthcare decision-making support at the Point-of-Care (PoC). Although made increasingly available to the consumer market, the adoption of LoC-based PoC In-Vitro Medical Testing (IVMT......) systems is still in its infancy. This attrition partly pertains to the intricacy of designing and developing complex systems, destined to be used sporadically, in a fast-pace evolving technological paradigm. System evolvability is therefore key in the design process and constitutes the main motivation...

  10. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  11. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  12. An Implanted Closed-loop Chip System for Heart Rate Control: System Design and Effects in Conscious Rats.

    Science.gov (United States)

    Zhou, Yuxuan; Yuan, Yuan; Gao, Juan; Yang, Ling; Zhang, Feng; Zhu, Guoqing; Gao, Xingya

    2010-03-01

    To evaluate the efficiency of an implanted chip system for the control of heart rate (HR). The HR was recorded in six conscious Sprague-Dawley (SD) rats. An implanted chip system was designed to regulate the HR by stimulating the right cervical vagus nerve according to the feedback of real time HR. Each rat was subjected to 30-min regulation and 30-min recovery. The change of HR during the regulation period was compared with the control. The ECG was recorded during the experiment for 24 h. The ECG signals were successfully recorded during the experiment. The HR was significantly decreased during the period of regulation compared with control (-79.3 ±34.5, P chip system can regulate the HR to a designated set point.

  13. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    AUTHOR|(CDS)2069646; Abbas, M.; Abbrescia, M.; Abdelalim, A.A.; Abi Akl, M.; Aboamer, O.; Acosta, D.; Ahmad, A.; Ahmed, W.; Ahmed, W.; Aleksandrov, A.; Aly, R.; Altieri, P.; Asawatangtrakuldee, C.; Aspell, P.; Assran, Y.; Awan, I.; Bally, S.; Ban, Y.; Banerjee, S.; Barashko, V.; Barria, P.; Bencze, G.; Beni, N.; Benussi, L.; Bhopatkar, V.; Bianco, S.; Bos, J.; Bouhali, O.; Braghieri, A.; Braibant, S.; Buontempo, S.; Calabria, C.; Caponero, M.; Caputo, C.; Cassese, F.; Castaneda, A.; Cauwenbergh, S.; Cavallo, F.R.; Celik, A.; Choi, M.; Choi, S.; Christiansen, J.; Cimmino, A.; Colafranceschi, S.; Colaleo, A.; Conde Garcia, A.; Czellar, S.; Dabrowski, M.M.; De Lentdecker, G.; De Oliveira, R.; de Robertis, G.; Dildick, S.; Dorney, B.; Elmetenawee, W.; Endroczi, G.; Errico, F.; Fenyvesi, A.; Ferry, S.; Furic, I.; Giacomelli, P.; Gilmore, J.; Golovtsov, V.; Guiducci, L.; Guilloux, F.; Gutierrez, A.; Hadjiiska, R.M.; Hassan, A.; Hauser, J.; Hoepfner, K.; Hohlmann, M.; Hoorani, H.; Iaydjiev, P.; Jeng, Y.G.; Kamon, T.; Karchin, P.; Korytov, A.; Krutelyov, S.; Kumar, A.; Kim, H.; Lee, J.; Lenzi, T.; Litov, L.; Madorsky, A.; Maerschalk, T.; Maggi, M.; Magnani, A.; Mal, P.K.; Mandal, K.; Marchioro, A.; Marinov, A.; Masod, R.; Majumdar, N.; Merlin, J.A.; Mitselmakher, G.; Mohanty, A.K.; Mohamed, S.; Mohapatra, A.; Molnar, J.; Muhammad, S.; Mukhopadhyay, S.; Naimuddin, M.; Nuzzo, S.; Oliveri, E.; Pant, L.M.; Paolucci, P.; Park, I.; Passeggio,G.; Pavlov, B.; Philipps, B.; Piccolo, D.; Postema, H.; Puig Baranac, A.; Radi, A.; Radogna, R.; Raffone, G.; Ranieri, A.; Rashevski, G.; Riccardi, C.; Rodozov, M.; Rodrigues, A.; Ropelewski, L.; RoyChowdhury, S.; Ryu, G.; Ryu, M.S.; Safonov, A.; Salva, S.; Saviano, G.; Sharma, A.; Sharma, A.; Sharma, R.; Shah, A.H.; Shopova, M.; Sturdy, J.; Sultanov, G.; Swain, S.K.; Szillasi, Z.; Talvitie, J.; Tamma, C.; Tatarinov, A.; Tuuva, T.; Tytgat, M.; Vai, I.; Van Stenis, M.; Venditti, R.; Verhagen, E.; Verwilligen, P.; Vitulo, P.; Volkov, S.; Vorobyev, A.; Wang, D.; Wang, M.; Yang, U.; Yang, Y.; Yonamine, R.; Zaganidis, N.; Zenoni, F.; Zhang, A.

    2016-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  14. Design and simulation of a Torus topology for network on chip

    Institute of Scientific and Technical Information of China (English)

    Wu Chang; Li Yubai; Chai Song

    2008-01-01

    Aiming at the applications of NOC(network on chip)technology in rising scale and complexity on chip systems,a Torus structure and corresponding route algorithm for NOC is proposed.This Torus structure improves traditional Torus topology and redefines the denotations of the routers.Through redefining the router denotations and changing the origihal router locations,the Torns structure for NOC application is reconstructed.On the basis of this structure.a dead-lock and live-lock free route algorithm is designed according to dimension increase.System C is used to implement this structure and the route algorithm is simulated.In the four different traffic patterns.average,hotspot 13%,hotspot 67% and transpose,the average delay and normalization throughput of this Torus structure are evaluated.Then,the performance of delay and throughput between this Torns and Mesh structure is compared.The results indicate that this Torns structure is more suitable for NOC applications.

  15. Microwave multiplex readout for superconducting sensors

    Science.gov (United States)

    Ferri, E.; Becker, D.; Bennett, D.; Faverzani, M.; Fowler, J.; Gard, J.; Giachero, A.; Hays-Wehle, J.; Hilton, G.; Maino, M.; Mates, J.; Puiu, A.; Nucciotti, A.; Reintsema, C.; Schmidt, D.; Swetz, D.; Ullom, J.; Vale, L.

    2016-07-01

    The absolute neutrino mass scale is still an outstanding challenge in both particle physics and cosmology. The calorimetric measurement of the energy released in a nuclear beta decay is a powerful tool to determine the effective electron-neutrino mass. In the last years, the progress on low temperature detector technologies has allowed to design large scale experiments aiming at pushing down the sensitivity on the neutrino mass below 1 eV. Even with outstanding performances in both energy (~ eV on keV) and time resolution (~ 1 μs) on the single channel, a large number of detectors working in parallel is required to reach a sub-eV sensitivity. Microwave frequency domain readout is the best available technique to readout large array of low temperature detectors, such as Transition Edge Sensors (TESs) or Microwave Kinetic Inductance Detectors (MKIDs). In this way a multiplex factor of the order of thousands can be reached, limited only by the bandwidth of the available commercial fast digitizers. This microwave multiplexing system will be used to readout the HOLMES detectors, an array of 1000 microcalorimeters based on TES sensors in which the 163Ho will be implanted. HOLMES is a new experiment for measuring the electron neutrino mass by means of the electron capture (EC) decay of 163Ho. We present here the microwave frequency multiplex which will be used in the HOLMES experiment and the microwave frequency multiplex used to readout the MKID detectors developed in Milan as well.

  16. Development of a low noise readout ASIC for CZT detectors for gamma-ray spectroscopy applications

    Science.gov (United States)

    Luo, J.; Deng, Z.; Wang, G.; Li, H.; Liu, Y.

    2012-08-01

    A multi-channel readout ASIC for pixelated CZT detectors has been developed for gamma-ray spectroscopy applications. Each channel consists of a low noise dual-stage charge sensitive amplifier (CSA), a CR-(RC)4 semi-Gaussian shaper and a class-AB output buffer. The equivalent noise charge (ENC) of input PMOS transistor is optimized for 5 pF input capacitance and 1 μs peaking time using gm/ID design methodology. The gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. A 16-channel chip has been designed and fabricated in 0.35 μm 2P4M CMOS technology. The test results show that the chip works well and fully satisfies the design specifications. The ENC was measured to be 72 e + 26 e/pF at 1 μs peaking time and 86 e + 20 e/pF at 4 μs peaking time. The non-uniformity of the channel gain and ENC was less than ±12% and ±11% respectively for 16 channels in one chip. The chip was also tested with a pixelated CZT detector at room temperature. The measured energy resolution at 59.5 keV photopeak of 241Am and 122 keV photopeak of 57Co were 4.5% FWHM and 2.8% FWHM for the central area pixels, respectively.

  17. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    Science.gov (United States)

    Li, H. S.; Jiang, X. S.; Liu, G.; Wang, N.; Sheng, H. Y.; Zhuang, B. A.; Zhao, J. W.

    2012-03-01

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  18. Introduction to Open Core Protocol Fastpath to System-on-Chip Design

    CERN Document Server

    Schwaderer, W David

    2012-01-01

    This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

  19. KPIX a pixel detector imaging chip

    CERN Document Server

    Cadeddu, S; Caria, M

    2002-01-01

    We present a VLSI custom device, named KPIX, developed in a 0.6 mu m CMOS technology. The circuit is dedicated to readout solid-state detectors covering large areas (on the order of square centimetre) and featuring very small currents. KPIX integrates 1024 channels (current amplifiers) and 8 ADCs on a 15.5x4 mm sup 2 area. Both an analogue and digital readout are allowed, with a 10 bit amplitude resolution. Amplifiers are organized in 8 columns of 128 rows. When choosing the digital or the analogue readout, the complete set of channels can be read out in about 30 ms. The specific design of the amplification cells allows to measure very small input current levels, on the order of fractions of pico-ampere. Power consumption has also been kept at the level of 80 mu W per cell and 150 mW (peak value) in total. The specific chip architecture and geometry allow use of many KPIX circuits together in order to serve a large detector sensitive area. The KPIX structure is presented along with some measurements character...

  20. Design and characterization of a 52K SNP chip for goats.

    Directory of Open Access Journals (Sweden)

    Gwenola Tosser-Klopp

    Full Text Available The success of Genome Wide Association Studies in the discovery of sequence variation linked to complex traits in humans has increased interest in high throughput SNP genotyping assays in livestock species. Primary goals are QTL detection and genomic selection. The purpose here was design of a 50-60,000 SNP chip for goats. The success of a moderate density SNP assay depends on reliable bioinformatic SNP detection procedures, the technological success rate of the SNP design, even spacing of SNPs on the genome and selection of Minor Allele Frequencies (MAF suitable to use in diverse breeds. Through the federation of three SNP discovery projects consolidated as the International Goat Genome Consortium, we have identified approximately twelve million high quality SNP variants in the goat genome stored in a database together with their biological and technical characteristics. These SNPs were identified within and between six breeds (meat, milk and mixed: Alpine, Boer, Creole, Katjang, Saanen and Savanna, comprising a total of 97 animals. Whole genome and Reduced Representation Library sequences were aligned on >10 kb scaffolds of the de novo goat genome assembly. The 60,000 selected SNPs, evenly spaced on the goat genome, were submitted for oligo manufacturing (Illumina, Inc and published in dbSNP along with flanking sequences and map position on goat assemblies (i.e. scaffolds and pseudo-chromosomes, sheep genome V2 and cattle UMD3.1 assembly. Ten breeds were then used to validate the SNP content and 52,295 loci could be successfully genotyped and used to generate a final cluster file. The combined strategy of using mainly whole genome Next Generation Sequencing and mapping on a contig genome assembly, complemented with Illumina design tools proved to be efficient in producing this GoatSNP50 chip. Advances in use of molecular markers are expected to accelerate goat genomic studies in coming years.

  1. Chip, Chip, Hooray!

    Science.gov (United States)

    Kelly, Susan

    2001-01-01

    Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

  2. Readout electronics for LGAD sensors

    Science.gov (United States)

    Alonso, O.; Franch, N.; Canals, J.; Palacio, F.; López, M.; Vilà, A.; Diéguez, A.; Carulla, M.; Flores, D.; Hidalgo, S.; Merlos, A.; Pellegrini, G.; Quirion, D.

    2017-02-01

    In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

  3. Characterization of Medipix3 with the MARS readout and software

    CERN Document Server

    Ronaldson, J P; van Leeuwen, D; Doesburg, R M N; Ballabriga, R; Butler, A P H; Donaldson, J; Walsh, M; Nik, S J; Clyne, M N

    2011-01-01

    The Medipix3 x-ray imaging detector has been characterized using the MARS camera. This x-ray camera comprises custom built readout electronics and software libraries designed for the Medipix family of detectors. The performance of the Medipix3 and MARS camera system is being studied prior to use in real-world applications such as the recently developed MARS-CT3 spectroscopic micro-CT scanner. We present the results of characterization measurements, describe methods for optimizing performance and give examples of spectroscopic images acquired with Medipix3 and the MARS camera system. A limited number of operating modes of the Medipix3 chip have been characterized and single-pixel mode has been found to give acceptable performance in terms of energy response, image quality and stability over time. Spectroscopic performance is significantly better in charge-summing mode than single-pixel mode however image quality and stability over time are compromised. There are more modes of operation to be tested and further...

  4. Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

    Science.gov (United States)

    Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

    2008-01-01

    A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

  5. Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

    Science.gov (United States)

    Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

    2008-01-01

    A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

  6. 100 Gbps PCI-Express Readout for the LHCb Upgrade

    CERN Document Server

    Durante, Paolo; Schwemmer, Rainer; Marconi, Umberto; Balbi, Gabriele; Lax, Ignazio

    2015-01-01

    We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new common readout board, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We describe a new high-performance DMA controller for data acquisition, implemented on an FPGA, coupled with a custom software module for the Linux kernel. Lastly, we describe how these components can be leveraged to achieve a throughput of 100 Gbit/s per readout board.

  7. A system-level bandwidth design method for wormhole network-on-chip

    Science.gov (United States)

    Wang, Jian; Li, Yubai; Liao, Changjun

    2016-11-01

    To improve the Network-on-Chip (NoC) performance, we propose a system-level bandwidth design method customising the bandwidths of the NoC links. In details, we first built a mathematical model to catch the relationship between the NoC commutation latency and the NoC link bandwidth, and then develop a bandwidth allocation algorithm to automatically optimise the bandwidth for each NoC link. The experimental results show that our bandwidth-customising method improves the NoC performance compared to the traditional uniform bandwidth allocation method. Besides, it can also make our NoC to achieve the same communication performance level as the uniform bandwidth NoC but using fewer bandwidth resources, which is beneficial to save the NoC area and power.

  8. Design of a DNA chip for detection of unknown genetically modified organisms (GMOs).

    Science.gov (United States)

    Nesvold, Håvard; Kristoffersen, Anja Bråthen; Holst-Jensen, Arne; Berdal, Knut G

    2005-05-01

    Unknown genetically modified organisms (GMOs) have not undergone a risk evaluation, and hence might pose a danger to health and environment. There are, today, no methods for detecting unknown GMOs. In this paper we propose a novel method intended as a first step in an approach for detecting unknown genetically modified (GM) material in a single plant. A model is designed where biological and combinatorial reduction rules are applied to a set of DNA chip probes containing all possible sequences of uniform length n, creating probes capable of detecting unknown GMOs. The model is theoretically tested for Arabidopsis thaliana Columbia, and the probabilities for detecting inserts and receiving false positives are assessed for various parameters for this organism. From a theoretical standpoint, the model looks very promising but should be tested further in the laboratory. The model and algorithms will be available upon request to the corresponding author.

  9. The Investigation on the TOT Readout Electronics Which is Based on the NINO Chip%基于NINO芯片的TOT读出电子学系统的研究

    Institute of Scientific and Technical Information of China (English)

    秦熙; 刘树彬; 安琪

    2012-01-01

    介绍了CERN设计的一款基于过阈时间法(Time - Over - Threshold)的ASIC芯片-NINO,并列出了一些基于NINO芯片设计的测试板的测试结果,用于评估该芯片在BES Ⅲ端盖TOF升级及在中子管位置灵敏探测器中的位置测量中应用的可能性.NINO芯片8通道高度集成,对实验电路板的设计和测试表明,其噪声抖动低(前沿噪声抖动约5.1 ps),可以满足TOT方法中高精度时间测量的要求.%The test result of the NINO chip which is based on the time over threshold (TOT) technique is described. The test is carried out to evaluate the possibility of applying the chip in the upgrade of BES III TOF and in the position measurement of Neutrino Position Sensitive Proportional Detector. The NINO chip is 8 channel integrated and of low noise ( 5.1 ps front edge jitter) which can serve high precision time measurement satisfactorily.

  10. Read-out electronics for fast photon detection with COMPASS RICH-1

    CERN Document Server

    Abbon, P

    2008-01-01

    A new read-out electronics system has been developed for the fast photon detection of the central region of the COMPASS RICH-1. The project is based on multi-anode photomultipliers read out by the high-sensitivity MAD4 preamplifier-discriminator and the dead-time free F1 TDC chip characterised by high time resolution. The system has been designed taking into account the high photon flux in the central region of the detector and the high rate requirement of the COMPASS experiment. The system is described in detail together with the measured performances. The new electronics system has been installed and used for the 2006 data taking; it entirely fulfils the expected performances.

  11. Deep silicon etch for biology MEMS fabrication: review of process parameters influence versus chip design

    Science.gov (United States)

    Magis, T.; Ballerand, S.; Bellemin Comte, A.; Pollet, Olivier

    2013-03-01

    Micro-system for biology is a growing market, especially for micro-fluidic applications (environment and health). Key part for the manufacturing of biology MEMS is the deep silicon etching by plasma to create microstructures. Usual etching process as an alternation of etching and passivation steps is a well-known method for MEMS fabrication, nowadays used in high volume production for devices like sensors and actuators. MEMS for biology applications are very different in design compared to more common micro-systems like accelerometers for instance. Indeed, their design includes on the same chip structures of very diverse size like narrow pillars, large trenches and wide cavities. This makes biology MEMS fabrication very challenging for DRIE, since each type of feature considered individually would require a specific etch process. Furthermore process parameters suited to match specifications on small size features (vertical profile, low sidewall roughness) induce issues and defects on bigger structures (undercut, micro-masking) and vice versa. Thus the process window is constrained leading to trade-offs in process development. In this paper process parameters such as source and platen powers, pressure, etching and passivation gas flows and steps duration were investigated to achieve all requirements. As well interactions between those different factors were characterized at different levels, from individual critical feature up to chip scale and to wafer scale. We will show the plasma process development and tuning to reach all these specifications. We also compared different chambers configurations of our ICP tool (source wafer distance, plasma diffusion) in order to obtain a good combination of hardware and process. With optimized etching we successfully fabricate micro-fluidic devices like micro-pumps.

  12. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Science.gov (United States)

    Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

    2016-01-01

    An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

  13. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Directory of Open Access Journals (Sweden)

    Cheng-Chun Wu

    2016-10-01

    Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  14. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

    Science.gov (United States)

    Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

    2016-10-25

    An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  15. Membrane Transport Processes Analyzed by a Highly Parallel Nanopore Chip System at Single Protein Resolution.

    Science.gov (United States)

    Urban, Michael; Vor der Brüggen, Marc; Tampé, Robert

    2016-08-16

    Membrane protein transport on the single protein level still evades detailed analysis, if the substrate translocated is non-electrogenic. Considerable efforts have been made in this field, but techniques enabling automated high-throughput transport analysis in combination with solvent-free lipid bilayer techniques required for the analysis of membrane transporters are rare. This class of transporters however is crucial in cell homeostasis and therefore a key target in drug development and methodologies to gain new insights desperately needed. The here presented manuscript describes the establishment and handling of a novel biochip for the analysis of membrane protein mediated transport processes at single transporter resolution. The biochip is composed of microcavities enclosed by nanopores that is highly parallel in its design and can be produced in industrial grade and quantity. Protein-harboring liposomes can directly be applied to the chip surface forming self-assembled pore-spanning lipid bilayers using SSM-techniques (solid supported lipid membranes). Pore-spanning parts of the membrane are freestanding, providing the interface for substrate translocation into or out of the cavity space, which can be followed by multi-spectral fluorescent readout in real-time. The establishment of standard operating procedures (SOPs) allows the straightforward establishment of protein-harboring lipid bilayers on the chip surface of virtually every membrane protein that can be reconstituted functionally. The sole prerequisite is the establishment of a fluorescent read-out system for non-electrogenic transport substrates. High-content screening applications are accomplishable by the use of automated inverted fluorescent microscopes recording multiple chips in parallel. Large data sets can be analyzed using the freely available custom-designed analysis software. Three-color multi spectral fluorescent read-out furthermore allows for unbiased data discrimination into different

  16. A VME MXI-II Based Setup for Testing ALICE Pixel Readout Prototypes

    CERN Document Server

    Chochula, P; CERN. Geneva

    2000-01-01

    Abstract One of the possible readout scenarios for ALICE ITS pixel layers counts on in- situ zero suppression, performed by Pilot control chip. Preprocessed event will be then serialized and sent out via about 50 m long copper cable for further processing. The VME prototypes of Pilot chip and link (called "SHORTLINK") were developed in the frames of Alice collaboration. Here we describe the VME test system, developed to test the modules.

  17. Timing and Readout Contorl in the LHCb Upgraded Readout System

    CERN Document Server

    Alessio, Federico

    2016-01-01

    In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

  18. High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

    Directory of Open Access Journals (Sweden)

    Chih-Cheng Lu

    2014-07-01

    Full Text Available This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

  19. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  20. Rational design of on-chip refractive index sensors based on lattice plasmon resonances (Presentation Recording)

    Science.gov (United States)

    Lin, Linhan; Zheng, Yuebing

    2015-08-01

    Lattice plasmon resonances (LPRs), which originate from the plasmonic-photonic coupling in gold or silver nanoparticle arrays, possess ultra-narrow linewidth by suppressing the radiative damping and provide the possibility to develop the plasmonic sensors with high figure of merit (FOM). However, the plasmonic-photonic coupling is greatly suppressed when the nanoparticles are immobilized on substrates because the diffraction orders are cut off at the nanoparticle-substrate interfaces. Here, we develop the rational design of LPR structures for the high-performance, on-chip plasmonic sensors based on both orthogonal and parallel coupling. Our finite-difference time-domain simulations in the core/shell SiO2/Au nanocylinder arrays (NCAs) reveal that new modes of localized surface plasmon resonances (LSPRs) show up when the aspect ratio of the NCAs is increased. The height-induced LSPRs couple with the superstrate diffraction orders to generate the robust LPRs in asymmetric environment. The high wavelength sensitivity and narrow linewidth in these LPRs lead to the plasmonic sensors with high FOM and high signal-to-noise ratio (SNR). Wide working wavelengths from visible to near-infrared are also achieved by tuning the parameters of the NCAs. Moreover, the wide detection range of refractive index is obtained in the parallel LPR structure. The electromagnetic field distributions in the NCAs demonstrate the height-enabled tunability of the plasmonic "hot spots" at the sub-nanoparticles resolution and the coupling between these "hot spots" with the superstrate diffraction waves, which are responsible for the high performance LPRs-based on-chip refractive index sensors.

  1. Design and Fabrication of a Chip-based Continuous-wave Atom Laser

    CERN Document Server

    Power, E P; Vanderelzen, B; Herrera-Fierro, P; Murphy, R; Yalisove, S M; Raithel, G

    2012-01-01

    We present a design for a continuous-wave (CW) atom laser on a chip and describe the process used to fabricate the device. Our design aims to integrate quadrupole magnetic guiding of ground state Rb atoms with continuous surface adsorption evaporative cooling to create a continuous Bose-Einstein condensate; out-coupled atoms from the condensate should realize a CW atom laser. We choose a geometry with three wires embedded in a spiral pattern in a silicon subtrate. The guide features an integrated solenoid to mitigate spin-flip losses and provide a tailored longitudinal magnetic field. Our design also includes multiple options for atom interferometry: accomodations are in place for laser-generated atom Fabry-Perot and Mach-Zehnder interferometers, and a pair of atomic beam X-splitters is incorporated for an all-magnetic atom Mach-Zehnder setup. We demonstrate the techniques necessary to fabricate our device using existing micro- and nano-scale fabrication equipment, and discuss future options for modified desi...

  2. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  3. A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2017-01-01

    Full Text Available This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs, a differential polysilicon cross-shaped Hall plate (CSHP, and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit—composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier—was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND. Both ‘no grounding’ and ‘grounding to power supply’ conditions were unsuitable for measuring the induced Hall voltage.

  4. A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit

    Science.gov (United States)

    Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

    2017-01-01

    This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit—composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier—was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both ‘no grounding’ and ‘grounding to power supply’ conditions were unsuitable for measuring the induced Hall voltage. PMID:28075392

  5. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  6. Low noise CMOS readout for CdZnTe detector arrays

    CERN Document Server

    Jakobson, C G; Lev, S B; Nemirovsky, Y

    1999-01-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 mu m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing functi...

  7. The NA62 Gigatracker: Detector properties and pixel read-out architectures

    Energy Technology Data Exchange (ETDEWEB)

    Fiorini, M., E-mail: Massimiliano.Fiorini@cern.c [CERN, CH-1211 Geneva 23 (Switzerland); Carassiti, V. [INFN Sezione di Ferrara, 44100 Ferrara (Italy); Ceccucci, A. [CERN, CH-1211 Geneva 23 (Switzerland); Cortina, E. [Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium); Cotta Ramusino, A. [INFN Sezione di Ferrara, 44100 Ferrara (Italy); Dellacasa, G. [INFN Sezione di Torino, 10125 Torino (Italy); Jarron, P.; Kaplon, J.; Kluge, A. [CERN, CH-1211 Geneva 23 (Switzerland); Marchetto, F. [INFN Sezione di Torino, 10125 Torino (Italy); Martin, E. [Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium); Martoiu, S.; Mazza, G. [INFN Sezione di Torino, 10125 Torino (Italy); Noy, M. [CERN, CH-1211 Geneva 23 (Switzerland); Petrucci, F. [INFN Sezione di Ferrara, 44100 Ferrara (Italy); Riedler, P. [CERN, CH-1211 Geneva 23 (Switzerland); Rivetti, A. [INFN Sezione di Torino, 10125 Torino (Italy); Tiuraniemi, S. [CERN, CH-1211 Geneva 23 (Switzerland)

    2010-12-11

    The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconstruction with unprecedented time resolution (150 ps rms) in a harsh radiation environment. To meet these requirements, and in order to reduce material budget to a minimum, three hybrid silicon pixel detector stations will be installed in vacuum. An adequate strategy to compensate for the discriminator time-walk must be implemented and R and D investigating two different options is ongoing. Two read-out chip prototypes have been designed in order to compare their performance: one approach is based on the use of a constant-fraction discriminator followed by an on-pixel TDC, while the other one is based on the use of a time-over-threshold circuit followed by a TDC shared by a group of pixels. This paper describes the Gigatracker system, presents the global architectures of both read-out ASICs and reviews the current status of the R and D project.

  8. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    Science.gov (United States)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  9. Thermopile Area Array Readout Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA/JPL thermopile detector linear arrays, wire bonded to Black Forest Engineering (BFE) CMOS readout integrated circuits (ROICs), have been utilized in NASA...

  10. Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

    Energy Technology Data Exchange (ETDEWEB)

    Villa, M., E-mail: villa@bo.infn.i [Universita degli Studi di Bologna and INFN-Bologna (Italy); Bruschi, M.; Di Sipio, R.; Fabbri, L.; Giacobbe, B.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini, N.; Spighi, R.; Valentinetti, S.; Zoccoli, A. [Universita degli Studi di Bologna and INFN-Bologna (Italy); Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Ceccanti, M.; Cenci, R. [Universita degli Studi di Pisa and INFN-Pisa (Italy)

    2010-05-21

    The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12 GeV/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, square pixels 50{mu}m wide, thinned down to 100{mu}m and equipped with a digital sparsified readout running up to 50 MHz. The other was a high resistivity double sided silicon detector, 200{mu}m thick, with short strips with 50{mu}m pitch at 45{sup 0} angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed. The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.

  11. Study for the LHCb upgrade read-out board

    CERN Document Server

    Cachemiche, J P; Hachon, F; Le Gac, R; Marin, F

    2010-01-01

    The LHCb experiment envisages to upgrade its readout electronics in order to increase the readout rate from 1 MHz to 40 MHz. This electronics upgrade is very challenging, since readout boards will have to handle a higher number of serial links with an increased bandwidth. In addition, the new communication protocol (GBT) developed by the CERN micro-electronics group mixes data acquisition, slow control and clock distribution on the same link. To explore the feasibility of such a readout system, elementary building blocks have been studied. Their goals are multiple: understand signal integrity when using highly integrated high speed serial links running at 8 - 10 Gbits/s; test the implementation of the GBT protocol within FPGAs; understand advantages and limitations of commercial standard with a predefined interconnection topology; validate ideas on how to control easily such a system. We designed two boards compliant with the xTCA standard which meets an increasing interest in the physics community. The first...

  12. Test of High Time Resolution MRPC with Different Readout Modes

    CERN Document Server

    Yang, S; Li, C; Heng, Y K; Qian, S; Chen, H F; Chen, T X; Dai, H L; Fan, H H; Liu, S B; Liu, S D; Jiang, X S; Shao, M; Tang, Z B; Zhang, H; Zhao, Z G

    2014-01-01

    In order to further enhance the particle identification capability of the Beijing Spectrometer (BESIII), it is proposed to upgrade the current end-cap time-of-flight (eTOF) detector with multi-gap resistive plate chamber (MRPC). The prototypes, together with the front end electronics (FEE) and time digitizer (TDIG) module have been tested at the E3 line of Beijing Electron Positron Collider (BEPCII) to study the difference between the single and double-end readout MRPC designs. The time resolutions (sigma) of the single-end readout MRPC are 47/53 ps obtained by 600 MeV/c proton/pion beam, while that of the double-end readout MRPC is 40 ps (proton beam). The efficiencies of three MRPC modules tested by both proton and pion beam are better than 98%. For the double-end readout MRPC, no incident position dependence is observed.

  13. Balanced homodyne readout for quantum limited gravitational wave detectors.

    Science.gov (United States)

    Fritschel, Peter; Evans, Matthew; Frolov, Valery

    2014-02-24

    Balanced homodyne detection is typically used to measure quantum-noise-limited optical beams, including squeezed states of light, at audio-band frequencies. Current designs of advanced gravitational wave interferometers use some type of homodyne readout for signal detection, in part because of its compatibility with the use of squeezed light. The readout scheme used in Advanced LIGO, called DC readout, is however not a balanced detection scheme. Instead, the local oscillator field, generated from a dark fringe offset, co-propagates with the signal field at the anti-symmetric output of the beam splitter. This article examines the alternative of a true balanced homodyne detection for the readout of gravitational wave detectors such as Advanced LIGO. Several practical advantages of the balanced detection scheme are described.

  14. Design and Fabrication of Complementary Metal-Oxide-Semiconductor Sensor Chip for Electrochemical Measurement

    Science.gov (United States)

    Yamazaki, Tomoyuki; Ikeda, Takaaki; Kano, Yoshiko; Takao, Hidekuni; Ishida, Makoto; Sawada, Kazuaki

    2010-04-01

    An electrochemical sensor has been developed on a single chip in which potentiostat and sensor electrodes are integrated. Sensor chips were fabricated using 5.0 µm complementary metal-oxide-semiconductor (CMOS) technology. All processes including the CMOS process, postprocessing for fabricating sensor electrodes and passivation layers, and packaging were performed at Toyohashi University of Technology. The integration makes it possible to measure electrochemical signals without having to use a bulky external electrochemical system. The potential between the working electrode and the reference electrode was controlled using an on-chip potentiostat composed of CMOS transistors. The chip characteristics were verified by electrochemical measurement, namely, by cyclic voltammetry. Potassium ferricyanide solution was measured to obtain results that fit well to the theoretical formula. A clear proportional relationship between peak height and the concentration of the sample solution was obtained using the proposed sensor chip, and the dynamic range obtained was 0.10 to 8.0 mM.

  15. Challenges in the Design and Fabrication of a Lab-on-a-Chip Photoacoustic Gas Sensor

    Directory of Open Access Journals (Sweden)

    Alain Glière

    2014-01-01

    Full Text Available The favorable downscaling behavior of photoacoustic spectroscopy has provoked in recent years a growing interest in the miniaturization of photoacoustic sensors. The individual components of the sensor, namely widely tunable quantum cascade lasers, low loss mid infrared (mid-IR waveguides, and efficient microelectromechanical systems (MEMS microphones are becoming available in complementary metal–oxide–semiconductor (CMOS compatible technologies. This paves the way for the joint processes of miniaturization and full integration. Recently, a prototype microsensor has been designed by the means of a specifically designed coupled optical-acoustic model. This paper discusses the new, or more intense, challenges faced if downscaling is continued. The first limitation in miniaturization is physical: the light source modulation, which matches the increasing cell acoustic resonance frequency, must be kept much slower than the collisional relaxation process. Secondly, from the acoustic modeling point of view, one faces the limit of validity of the continuum hypothesis. Namely, at some point, velocity slip and temperature jump boundary conditions must be used, instead of the continuous boundary conditions, which are valid at the macro-scale. Finally, on the technological side, solutions exist to realize a complete lab-on-a-chip, even if it remains a demanding integration problem.

  16. Single Core Hardware Modeling of Built-in-Self-Test for System on Chip Design

    Directory of Open Access Journals (Sweden)

    M.D. Mamun

    2012-04-01

    Full Text Available This study describes a hardware modeling environment of built-in-self-test (BIST for System on Chip (SOC testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. The design is modularized and each module is modeled individually using hardware description language VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit, which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications with a maximum clock frequency of 31.4 MHz.

  17. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  18. Design, Construction and Testing of the Digital Hadron Calorimeter (DHCAL) Electronics

    CERN Document Server

    Adams, C; Bilki, B; Butler, J; Corriveau, F; Cundiff, T; Drake, G; Francis, K; Guarino, V; Haberichter, B; Hazen, E; Hoff, J; Holm, S; Kreps, A; DeLurgio, P; Monte, L Dal; Mucia, N; Norbeck, E; Northacker, D; Onel, Y; Pollack, B; Repond, J; Schlereth, J; Smith, J R; Trojand, D; Underwood, D; Velasco, M; Walendziak, J; Wood, K; Wu, S; Xia, L; Zhang, Q; Zhao, A

    2016-01-01

    A novel hadron calorimeter is being developed for future lepton colliding beam detectors. The calorimeter is optimized for the application of Particle Flow Algorithms (PFAs) to the measurement of hadronic jets and features a very finely segmented readout with 1 x 1 cm2 cells. The active media of the calorimeter are Resistive Plate Chambers (RPCs) with a digital, i.e. one-bit, readout. To first order the energy of incident particles in this calorimeter is reconstructed as being proportional to the number of pads with a signal over a given threshold. A large-scale prototype calorimeter with approximately 500,000 readout channels has been built and underwent extensive testing in the Fermilab and CERN test beams. This paper reports on the design, construction, and commissioning of the electronic readout system of this prototype calorimeter. The system is based on the DCAL front-end chip and a VME-based back-end.

  19. Design and Implementation of Embedded Transmission Control Protocol/Internet Protocol Network Based on System-on-programmable Chip

    Institute of Scientific and Technical Information of China (English)

    LUO Yong; HAN Xiao-jun

    2008-01-01

    A scheme of transmission control protocol/Internet protocol(TCP/IP) network system based on system-on-programmable chip(SOPC) is proposed for the embedded network communication. In this system, Nios processor, Ethernet controller and other peripheral logic circuits are all integrated on a Stratix Ⅱ field programmable gate array(FPGA) chip by using SOPC builder design software. And the network communication is realized by transplanting MicroC/OS Ⅱ(μC/OS Ⅱ) operation system and light weight Internet protocol(LwIP). The design idea, key points and the structures of both software and hardware of the system are presented and ran with a telecommunication example. The experiment shows that the embedded TCP/IP network system has high reliability and real-time performance.

  20. Cryogenic readout techniques for germanium detectors

    Energy Technology Data Exchange (ETDEWEB)

    Benato, G. [University of Zurich, (Switzerland); Cattadori, C. [INFN - Milano Bicocca, (Italy); Di Vacri, A. [INFN LNGS, (Italy); Ferri, E. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy); D' Andrea, V.; Macolino, C. [GSSI/INFN LNGS, (Italy); Riboldi, S. [Universita degli Studi di Milano/INFN Milano, (Italy); Salamida, F. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy)

    2015-07-01

    High Purity Germanium detectors are used in many applications, from nuclear and astro-particle physics, to homeland security or environment protection. Although quite standard configurations are often used, with cryostats, charge sensitive amplifiers and analog or digital acquisition systems all commercially available, it might be the case that a few specific applications, e.g. satellites, portable devices, cryogenic physics experiments, etc. also require the development of a few additional or complementary techniques. An interesting case is for sure GERDA, the Germanium Detector Array experiment, searching for neutrino-less double beta decay of {sup 76}Ge at the Gran Sasso National Laboratory of INFN - Italy. In GERDA the entire detector array, composed of semi-coaxial and BEGe naked crystals, is operated suspended inside a cryostat filled with liquid argon, that acts not only as cooling medium and but also as an active shield, thanks to its scintillation properties. These peculiar circumstances, together with the additional requirement of a very low radioactive background from all the materials adjacent to the detectors, clearly introduce significant constraints on the design of the Ge front-end readout electronics. All the Ge readout solutions developed within the framework of the GERDA collaboration, for both Phase I and Phase II, will be briefly reviewed, with their relative strength and weakness compared together and with respect to ideal Ge readout. Finally, the digital processing techniques developed by the GERDA collaboration for energy estimation of Ge detector signals will be recalled. (authors)

  1. Embedded controller for GEM detector readout system

    Science.gov (United States)

    Zabołotny, Wojciech M.; Byszuk, Adrian; Chernyshova, Maryna; Cieszewski, Radosław; Czarski, Tomasz; Dominik, Wojciech; Jakubowska, Katarzyna L.; Kasprowicz, Grzegorz; Poźniak, Krzysztof; Rzadkiewicz, Jacek; Scholz, Marek

    2013-10-01

    This paper describes the embedded controller used for the multichannel readout system for the GEM detector. The controller is based on the embedded Mini ITX mainboard, running the GNU/Linux operating system. The controller offers two interfaces to communicate with the FPGA based readout system. FPGA configuration and diagnostics is controlled via low speed USB based interface, while high-speed setup of the readout parameters and reception of the measured data is handled by the PCI Express (PCIe) interface. Hardware access is synchronized by the dedicated server written in C. Multiple clients may connect to this server via TCP/IP network, and different priority is assigned to individual clients. Specialized protocols have been implemented both for low level access on register level and for high level access with transfer of structured data with "msgpack" protocol. High level functionalities have been split between multiple TCP/IP servers for parallel operation. Status of the system may be checked, and basic maintenance may be performed via web interface, while the expert access is possible via SSH server. System was designed with reliability and flexibility in mind.

  2. RCU2-The ALICE TPC readout electronics consolidation for Run2

    CERN Document Server

    Alme, J; Christiansen, P; Yang, S; Lien, J; Velure, A; Rehman, A Ur; Torgersen, C; David, E; Gunji, T; Osterman, L; Ullaland, K; Roed, K; Tarantola, A; Langoy, R; Appelshaeuser, H; Oskarsson, A; Alt, T; Costa, F; Bratrud, L; Zhao, C; Lippmann, C; Torsvik, I Nikolai; Kiss, T

    2013-01-01

    This paper presents the solution for optimization of the ALICE TPC readout for running at full energy in the Run2 period after 2014. For the data taking with heavy ion beams an event readout rate of 400 Hz with a low dead time is envisaged for the ALICE central barrel detectors during these three years. A new component, the Readout Control Unit 2 (RCU2), is being designed to increase the present readout rate by a factor of up to 2.6. The immunity to radiation induced errors will also be significantly improved by the new design.

  3. Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

    Science.gov (United States)

    Hsieh, I.-Wei

    In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic

  4. Heterogeneous System-on-a-Chip Design for Self-Powered Wireless Sensor Networks in Non-Benign Environments

    Science.gov (United States)

    2008-03-01

    due to the academic non-disclosure agreement in force. The novel photocell design utilizes NPN SiGe large area transistors , which are thin and close... transistor test structures and are discussed in section 4.4. Test chip results reveal that the NPN CB junction is not activated as expected. Upon closer...broadened over the past decade with the introduction of processes optimized for radio frequency (RF), optical sensors, integrated bipolar transistors

  5. A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

    Science.gov (United States)

    Paternò, A.; Pacher, L.; Monteil, E.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.

    2017-02-01

    This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

  6. An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar; Olsen, Rasmus Grøndahl

    2005-01-01

    decouples communication and computation, providing memory-mapped OCP transactions based on primitive message-passing services of the network. Also, it facilitates GALS-type systems, by adapting to the clockless network. This helps leverage a modular SoC design flow. We evaluate performance and cost of 0......The demand for IP reuse and system level scalability in System-on-Chip (SoC) designs is growing. Network-onchip (NoC) constitutes a viable solution space to emerging SoC design challenges. In this paper we describe an OCP compliant network adapter (NA) architecture for the MANGO NoC. The NA...

  7. RCP: a novel probe design bias correction method for Illumina Methylation BeadChip.

    Science.gov (United States)

    Niu, Liang; Xu, Zongli; Taylor, Jack A

    2016-09-01

    The Illumina HumanMethylation450 BeadChip has been extensively utilized in epigenome-wide association studies. This array and its successor, the MethylationEPIC array, use two types of probes-Infinium I (type I) and Infinium II (type II)-in order to increase genome coverage but differences in probe chemistries result in different type I and II distributions of methylation values. Ignoring the difference in distributions between the two probe types may bias downstream analysis. Here, we developed a novel method, called Regression on Correlated Probes (RCP), which uses the existing correlation between pairs of nearby type I and II probes to adjust the beta values of all type II probes. We evaluate the effect of this adjustment on reducing probe design type bias, reducing technical variation in duplicate samples, improving accuracy of measurements against known standards, and retention of biological signal. We find that RCP is statistically significantly better than unadjusted data or adjustment with alternative methods including SWAN and BMIQ. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website (https://www.bioconductor.org/packages/release/bioc/html/ENmix.html). niulg@ucmail.uc.edu Supplementary data are available at Bioinformatics online. Published by Oxford University Press 2016. This work is written by US Government employees and is in the public domain in the US.

  8. Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

    Directory of Open Access Journals (Sweden)

    ASHUTOSH KUMAR SINGH,

    2011-03-01

    Full Text Available Resolution is a big issue in SOC( system On Chip while dealing with number of master trying to sense a single data bus . The ffectiveness of a system to resolve this priority resides in its ability to logical assignment of the chance to transmit data width of the data, response to the interrupts etc. The purpose of this paper is to propose the scheme to implement such a system using the specification of AMBA bus protocol .The scheme involves the typical AMBA features of ‘single clock edge transition ‘, Split transaction ‘,’several bus masters ‘, ‘burst transfer ’.The bus arbiter ensures that only one bus master at a time is allowed to initiate data ransfers. Even though the arbitration protocol is fixed, any arbitration algorithm, such as highest priority or fair access can be implemented depending on the application requirements .The design architecture is written using VHDL(Very High Speed Integrated CircuitsHardware Description Language code using Xilinx ISE Tools .The architecture is modeled and synthesized using RTL(Register Transfer Level abstraction and Implemented on Virtex2 series.

  9. On the Design of Laser Structured Ka Band Multi-Chip Module

    Directory of Open Access Journals (Sweden)

    Ghulam Mehdi

    2013-09-01

    Full Text Available The rapid prototyping of millimeter wave (MMW multi-chip module (MCM on low-cost ceramic-polymer composite substrate using laser ablation process is presented. A Ka band MCM front-end receiver is designed, fabricated and tested. The complete front-end receiver module except the IF and power distribution sections is realized on the single prescribed substrate. The measured receiver gain, noise figure and image rejection is 37 dB, 4.25 dB and 40 dB respectively. However, it deduced from the experimental results of the two front-end modules that the complex permittivity characteristics of the substrate are altered after the laser ablation process. The effective permittivity alteration phenomenon is further validated through the characterization and comparison of various laser ablated and chemically etched Ka band parallel-coupled band-pass filters. A simple and experimentally verified method is worked out to utilize the laser ablation structuring process on the prescribed substrate. It is anticipated that the proposed method can be applied to other laminated substrates as well with the prescribed manufacturing process.

  10. Design and Analysis of Delayed Chip Slope Modulation in Optical Wireless Communication

    KAUST Repository

    Park, Kihong

    2015-08-23

    In this letter, we propose a novel slope-based binary modulation called delayed chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. Shorter duration of chips than bit duration are used to represent the change of state in an amplitude level according to consecutive bit information and to exploit the trade-off between bandwidth and power efficiency. We analyze the power spectral density and error rate performance of the proposed DCSM. We show from numerical results that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to conventional modulation schemes.

  11. The front-end chip of the SuperB SVT detector

    Energy Technology Data Exchange (ETDEWEB)

    Giorgi, F., E-mail: giorgi@bo.infn.it [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università degli Studi di Bergamo (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pavia (Italy); Fabbri, L.; Gabrielli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Pellegrini, G.; Sbarra, C. [Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Berra, A.; Lietti, D.; Prest, M. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Wilson, F. [STFC Rutherford Appleton Laboratory, Harwell Oxford, Didcot OX11 0QX (United Kingdom); Beck, G.; Morris, J. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); and others

    2013-08-01

    The asymmetric e{sup +}e{sup −} collider SuperB is designed to deliver a high luminosity, greater than 10{sup 36}cm{sup −2}s{sup −1}, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  12. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  13. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  14. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  15. TOFFEE: a full custom amplifier-comparator chip for timing applications with silicon detectors

    Science.gov (United States)

    Cenna, F.; Cartiglia, N.; Di Francesco, A.; Olave, J.; Da Rocha Rolo, M.; Rivetti, A.; Silva, J. C.; Silva, R.; Varela, J.

    2017-03-01

    We report on the design of a full custom amplifier-comparator readout chip for silicon detectors with internal gain designed for precise timing applications. The ASIC has been developed in UMC 110 nm CMOS technology and is aimed to fulfill the CMS-TOTEM Precision Proton Spectrometer (CT-PPS) time resolution requirements (~ 30 ps per detector plane). It features LVDS outputs and the signal dynamic range matches the requirements of the High Precision TDC (HPTDC) system. The preliminary measurements results with a test board are included.

  16. Study on a Real-Time BEAM System for Diagnosis Assistance Based on a System on Chips Design

    Directory of Open Access Journals (Sweden)

    Kung-Wei Chang

    2013-05-01

    Full Text Available As an innovative as well as an interdisciplinary research project, this study performed an analysis of brain signals so as to establish BrainIC as an auxiliary tool for physician diagnosis. Cognition behavior sciences, embedded technology, system on chips (SOC design and physiological signal processing are integrated in this work. Moreover, a chip is built for real-time electroencephalography (EEG processing purposes and a Brain Electrical Activity Mapping (BEAM system, and a knowledge database is constructed to diagnose psychosis and body challenges in learning various behaviors and signals antithesis by a fuzzy inference engine. This work is completed with a medical support system developed for the mentally disabled or the elderly abled.

  17. The Design of the ADC Sampling System Based on the Readout Electronics for GEM Detector%GEM 探测器读出电子学 ADC 采样系统设计

    Institute of Scientific and Technical Information of China (English)

    杜秋宇; 江晓山; 李绍富; 胡俊; 张杰; 陈少佳; 宁哲

    2015-01-01

    本文简要介绍了GEM探测器读出电子学ADC采样系统设计与测试。该系统包括模数变换模块、数据汇总模块和后端数据接收模块三部分。本文详细介绍了模数变换模块硬件电路设计、FPGA逻辑设计、光纤数据传输设计以及ADC采样芯片的测试方法。经过测试,该系统实现了8通道数据实时采集、传输、存储及显示功能。%This article introduces the design and the test of ADC sampling system based on the readout electron-ics for GEM detector.The system consists of an analog to digital converter module, a data collection module and a back-end data receiving module.The analog to digital converter module is presented in detail, including hardware circuit design, FPGA firmware design, optical fiber data transmission design and ADC performance test.After testing, the system implements 8-channel real-time data sampling, transfer, storage and display, and the system works well.

  18. Wideband pulse amplifiers for the NECTAr chip

    Science.gov (United States)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

    2012-12-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  19. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  20. Design and experimental verification of CMOS magnetic-based microbead detection using an asynchronous intra-chip inductive-coupling transceiver

    Science.gov (United States)

    Niitsu, Kiichi; Kobayashi, Atsuki; Yoshida, Kohei; Nakazato, Kazuo

    2017-01-01

    In this study, an asynchronous intra-chip inductive-coupling transceiver was used to design and experimentally verify a CMOS magnetic-based microbeads detection system. Magnetic microbeads were employed for the surrounding living cells. These microbeads increased the magnetic flux and enabled the operation of an intra-chip inductive-coupling transceiver with a low transmitter supply voltage. Thus, by sensing the change in transmitter supply voltage, the system detected the living cells surrounded by microbeads. To verify the effectiveness of the proposed approach, a test chip was fabricated using 0.25 µm CMOS technology. The measured results successfully demonstrated the detection of microbeads.

  1. Analysis techniques and performance of the Domino Ring Sampler version 4 based readout for the MAGIC telescopes

    CERN Document Server

    Sitarek, Julian; Mazin, Daniel; Paoletti, Riccardo; Tescaro, Diego

    2013-01-01

    Recently the readout of the MAGIC telescopes has been upgraded to a new system based on the Domino Ring Sampler version 4 chip. We present the analysis techniques and the signal extraction performance studies of this system. We study the behaviour of the baseline, the noise, the cross-talk, the linearity and the time resolution. We investigate also the optimal signal extraction. In addition we show some of the analysis techniques specific to the readout based on the Domino Ring Sampler version 2 chip, previously used in the MAGIC II telescope.

  2. 18k Channels single photon counting readout circuit for hybrid pixel detector

    Science.gov (United States)

    Maj, P.; Grybos, P.; Szczygiel, R.; Zoladz, M.; Sakumura, T.; Tsuji, Y.

    2013-01-01

    We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm×20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96×192 pixels with 100 μm×100 μm pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 μW/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 μV/e- and the equivalent noise charge is 168 e- rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

  3. 18k Channels single photon counting readout circuit for hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Maj, P., E-mail: piotr.maj@agh.edu.pl [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Grybos, P.; Szczygiel, R.; Zoladz, M. [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Sakumura, T.; Tsuji, Y. [X-ray Analysis Division, Rigaku Corporation, Matsubara, Akishima, Tokyo 196-8666 (Japan)

    2013-01-01

    We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm Multiplication-Sign 20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96 Multiplication-Sign 192 pixels with 100 {mu}m Multiplication-Sign 100 {mu}m pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 {mu}W/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 {mu}V/e{sup -} and the equivalent noise charge is 168 e{sup -} rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

  4. Design, realization and test of a digital chip for ALICE ITS experiment

    CERN Document Server

    Antinori, S; Gabrielli, A; Gandolfi, E

    2004-01-01

    CARLOS v3 (Compression And Run Length encOding subSystem) is the name of the third version of a digital radiation hardened chip that plays a significant role in the data acquisition chain of the ALICE experiment (A Large Ion Collider Experiment) for what concerns the Inner Tracking System (ITS). In particular CARLOS has the purpose of performing an on-line compression on data coming from two half detectors SDDs (Silicon Drift Detectors). In fact data volume of SDD events and trigger rate require the use of an on-line compression device with high performances for what concerns compression coefficient and total throughput. The chip has been tested using a specific PCB (Printed Circuit Board) containing the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chips have been inserted on the PCB using a ZIF socket, that allowed us to test the 35 packaged samples out of the total amount of bare chips received from the foundry. The test phase has shown that 32 out of 35 chips und...

  5. Multi-Anode Photomultplier (MAPMT) readout for High Granularity Calorimeters

    CERN Document Server

    Mkrtchyan, Tigran; The ATLAS collaboration

    2017-01-01

    Hadron calorimeter high performance in jet sub-structure measurements can be achieved for objects with $p_{T}$ greater than 1 TeV if the readout geometry is finely segmented in $\\Delta\\eta \\times \\Delta\\phi$. A feasibility study to increase the readout granularity of TileCal, the central hadron calorimeter of the ATLAS detector, is presented. We show a preliminary study exploring the possibility to increase by a factor 4 the present readout granularity of the inner layer cells of TileCal (0.1->0.025 in $\\Delta\\eta$) and to split into two layers the intermediate section of TileCal. The proposed solution is designed to cope with mechanical and readout bandwidth and power constraints. Assuming that the mechanics of the Tile modules cannot be changed, Multi-Anode PMTs with same boundary geometry of the present single-anode PMTs are considered to readout WLS bers, ideally one per pixel, carrying the signals from the individual scintillating tiles of each detector cells. The discussed challenges of the design are: ...

  6. Design and testing of micro fluidic chemical analysis chip integrated with micro valveless pump

    Institute of Scientific and Technical Information of China (English)

    FU; Xin; XIE; Haibo; YANG; Huayong; JIA; Zhijian; FANG; Qun

    2005-01-01

    A new structure and working principle of the chip integrated with micro valveless pump for capillary electrophoresis was proposed in this paper. The micro valveless pump with plane structure has advantages of simple structure, and the process technology is compatible with existing micro chips for capillary electrophoresis. Based upon the mathematical model, simulation study of micro pump was carried out to investigate the influence of structural parameters on flow characteristics, and the performance of the integrated micro pump was also tested with different control parameters. The simulation results agree with the experimental results. Three samples, which are amino acid, fluorescein and buffer solution, have been examined with this chip. The results of the primary experiments showed that the micro valveless pump was promising in the integration and automatization of miniature integrated fluidic systems.

  7. Simulation and design of a self-heating continuous-flow PCR chip

    Institute of Scientific and Technical Information of China (English)

    CHEN Wei-ping; TIAN Li; LI Ming-jiang; LIU Xiao-wei

    2007-01-01

    A novel continuous-flow PCR chip adopting self-heating, passive-cooling mode to realize the DNA fragments amplification was presented. Using the ANSYS finite element analysis, the temperature distribution of the chip is simulated and analyzed. The optimal size of the chip is 30 × 22 mm2, the roundabout micro-channel is the 90 μm width, 40 μm depth. Two micro-heater with the nickel-chrome alloy material film are formed on the side of silicon belonging to denaturation and renaturation zones needed for PCR reaction, and two adiabatic structures with groove on side of silicon by anisotropy etching. By the mede of heating local zones at single side,three wider constant temperature zones could be formed, which are 60 ℃ ,72 ℃ ,95 ℃ and suitable for PCR,and the temperature-difference could be restricted in less than 5 ℃.

  8. Inductorless Ultra-Wide Band Front-End Chip Design with Noise Cancellation Technology for Wireless Communication Applications 10

    Institute of Scientific and Technical Information of China (English)

    Jhin-fang HUANG; Ming-chun HSU; Ron-yi LIU

    2010-01-01

    An inductorless Ultra-Wide Band (UWB) receiver front-end chip design used in wireless communications for the frequency band of 3.1~4.8 GHz is presented. This homodyne receiver mainly consists of a differential Low Noise Amplifier (LNA) circuit followed by a down-converting mixer. The proposed LNA circuit with a noise canceling resistor is connected to the CMOS device's body to reduce the substrate thermal noise. Simulation and measurement results show that the chip can reduce the front-end Noise Figure (NF) about 0.5dB and achieve the Conversion Gain (CG) of 19.44~21.57 dB and double-sideband NF less than 7.8 dB. Also, the input third-order intercept point (IIP3) is -11 dBm, and the input second-order intercept point (IIP2) is 49 dBm. Fabricated in TSMC 0.18 μm CMOS technology, this chip occupies only 0.167 mm2 and dissipates power 59.2 mW.

  9. A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

    Science.gov (United States)

    Kaimin, Zhou; Ziqiang, Wang; Chun, Zhang; Zhihua, Wang

    2012-06-01

    A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

  10. A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    Zhou Kaimin; Wang Ziqiang; Zhang Chun; Wang Zhihua

    2012-01-01

    A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented.By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased,and the systematic offsets of two input op-amps are cancelled.The common-mode noise and even-order distortion are also rejected.A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps,and a Verilog-A-based varaetor is used to model the real variable sensing capacitor.Simulation results show that the output voltage of this proposed readout circuit responds correctly,while the under-test capacitance changes with a frequency of 1 kHz.A metal-insulator-metal capacitor array is designed on chip for measurement,and the measurement results show that this circuit achieves sensitivity of 370 mV/pF,linearity error below 1% and power consumption as low as 2.5 mW.This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

  11. VLSI design of turbo decoder for integrated communication system on a chip applications

    Science.gov (United States)

    Fang, Wai-Chi; Sethuram, Ashwin; Belevi, Kemal

    2003-01-01

    A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as satellite communications, wireless LAN, digital TV, cable modem, Digital Video Broadcast (DVB), and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watts.

  12. The Belle II SVD data readout system

    Science.gov (United States)

    Thalmeier, R.; Adamczyk, K.; Aihara, H.; Angelini, C.; Aziz, T.; Babu, V.; Bacher, S.; Bahinipati, S.; Barberio, E.; Baroncelli, Ti.; Baroncelli, To.; Basith, A. K.; Batignani, G.; Bauer, A.; Behera, P. K.; Bergauer, T.; Bettarini, S.; Bhuyan, B.; Bilka, T.; Bosi, F.; Bosisio, L.; Bozek, A.; Buchsteiner, F.; Bulla, L.; Casarosa, G.; Ceccanti, M.; Cervenkov, D.; Chendvankar, S. R.; Dash, N.; Divekar, S. T.; Doleźal, Z.; Dutta, D.; Forti, F.; Friedl, M.; Hara, K.; Higuchi, T.; Horiguchi, T.; Irmler, C.; Ishikawa, A.; Jeon, H. B.; Joo, C.; Kandra, J.; Kang, K. H.; Kato, E.; Kawasaki, T.; Kodyś, P.; Kohriki, T.; Koike, S.; Kolwalkar, M. M.; Kvasnićka, P.; Lanceri, L.; Lettenbicher, J.; Lueck, T.; Maki, M.; Mammini, P.; Mayekar, S. N.; Mohanty, G. B.; Mohanty, S.; Morii, T.; Nakamura, K. R.; Natkaniec, Z.; Negishi, K.; Nisar, N. K.; Onuki, Y.; Ostrowicz, W.; Paladino, A.; Paoloni, E.; Park, H.; Pilo, F.; Profeti, A.; Rao, K. K.; Rashevskaya, I.; Rizzo, G.; Rozanska, M.; Sasaki, J.; Sato, N.; Schultschik, S.; Schwanda, C.; Seino, Y.; Shimizu, N.; Stypula, J.; Suzuki, J.; Tanaka, S.; Tanida, K.; Taylor, G. N.; Thomas, R.; Tsuboyama, T.; Uozumi, S.; Urquijo, P.; Vitale, L.; Watanuki, S.; Watson, I. J.; Webb, J.; Wiechczynski, J.; Williams, S.; Würkner, B.; Yamamoto, H.; Yin, H.; Yoshinobu, T.

    2017-02-01

    The Belle II Experiment at the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, will explore the asymmetry between matter and antimatter and search for new physics beyond the standard model. 172 double-sided silicon strip detectors are arranged cylindrically in four layers around the collision point to be part of a system which measures the tracks of the collision products of electrons and positrons. A total of 1748 radiation-hard APV25 chips read out 128 silicon strips each and send the analog signals by time-division multiplexing out of the radiation zone to 48 Flash Analog Digital Converter Modules (FADC). Each of them applies processing to the data; for example, it uses a digital finite impulse response filter to compensate line signal distortions, and it extracts the peak timing and amplitude from a set of several data points for each hit, using a neural network. We present an overview of the SVD data readout system, along with front-end electronics, cabling, power supplies and data processing.

  13. Design and prototyping of a chip-based multi-micro-organoid culture system for substance testing, predictive to human (substance) exposure.

    Science.gov (United States)

    Sonntag, Frank; Schilling, Niels; Mader, Katja; Gruchow, Mathias; Klotzbach, Udo; Lindner, Gerd; Horland, Reyk; Wagner, Ilka; Lauster, Roland; Howitz, Steffen; Hoffmann, Silke; Marx, Uwe

    2010-07-01

    Dynamic miniaturized human multi-micro-organ bioreactor systems are envisaged as a possible solution for the embarrassing gap of predictive substance testing prior to human exposure. A rational approach was applied to simulate and design dynamic long-term cultures of the smallest possible functional human organ units, human "micro-organoids", on a chip the shape of a microscope slide. Each chip contains six identical dynamic micro-bioreactors with three different micro-organoid culture segments each, a feed supply and waste reservoirs. A liver, a brain cortex and a bone marrow micro-organoid segment were designed into each bioreactor. This design was translated into a multi-layer chip prototype and a routine manufacturing procedure was established. The first series of microscopable, chemically resistant and sterilizable chip prototypes was tested for matrix compatibility and primary cell culture suitability. Sterility and long-term human cell survival could be shown. Optimizing the applied design approach and prototyping tools resulted in a time period of only 3 months for a single design and prototyping cycle. This rapid prototyping scheme now allows for fast adjustment or redesign of inaccurate architectures. The designed chip platform is thus ready to be evaluated for the establishment and maintenance of the human liver, brain cortex and bone marrow micro-organoids in a systemic microenvironment.

  14. Two-dimensional electronic readout system for multi-step-avalanche chambers

    NARCIS (Netherlands)

    Carlén, L.; Garpmann, S.; Gustafsson, H.-A.; Löhner, H.; Nystrand, J.; Oskarsson, A.; Otterlund, I.; Svensson, T.; Stenlund, E.; Söderström, K.; Whitlow, H.J.

    1997-01-01

    We present prototype studies of a new technical solution of detector readout for measurements of charged particles at very high particle densities. In particular, this paper describes a readout system for Multi-Step Avalanche Chambers designed for the WA98 experiment at the CERN SPS. Results from th

  15. IEEE 1451.0-2007 Compatible Smart Sensor Readout with Error Compensation Using FPGA

    Directory of Open Access Journals (Sweden)

    J. Kamala

    2009-03-01

    Full Text Available This paper deals with effective usage of user TEDS for developing smart sensor readout which is suitable to estimate and compensate the disturbances occurring in the system. The system parameters are incorporated along with other transducer data. Appropriate processing capabilities are built in Transducer Interface Module TIM for disturbance estimation and compensation. A Verilog based single chip module of IEEE 1451.0 smart sensor is proposed incorporating the above mentioned features. The architecture enables reliable and smart readout for sensors at low cost for a given application. The programmable nature of the proposed architecture enables wide usage of the smart sensor for various applications.

  16. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  17. The ALICE Time of Flight Readout System AFRO

    CERN Document Server

    Kluge, A

    1999-01-01

    The ALICE Time of Flight Detector system comprises more than 100.000 channels and covers an area of more than 100 m2. The timing resolution should be better than 150 ps. This combination of requirements poses a major challenge to the readout system. All detector timing measurements are referenced to a unique start signal t0. This signal is generated at the time an event occurs. Timing measurements are performed using a multichannel TDC chip which requires a 40 MHz reference clock signal. The general concept of the readout system is based on a modular architecture. Detector cells are combined to modules of 1024 channels. Each of these modules can be read out and calibrated independently from each other. By distributing a reference signal, a timing relationship between the modules is established. This reference signal can either be the start signal t0 or the TDC-reference clock. The readout architecture is divided into three steps; the TDC controller, the module controller, and the time of flight controller. Th...

  18. Demonstration of a scalable frequency-domain readout of metallic magnetic calorimeters by means of a microwave SQUID multiplexer

    Directory of Open Access Journals (Sweden)

    Sebastian Kempf

    2017-01-01

    Full Text Available We report on the first demonstration of a scalable GHz frequency-domain readout of metallic magnetic calorimeters (MMCs using a 64 pixel detector array that is read out by an integrated, on-chip microwave SQUID multiplexer. The detector array is optimized for detecting soft X-ray photons and the multiplexer is designed to provide a signal rise time τrise<400ns and an intrinsic energy sensitivity ϵ<30h. This results in an expected energy resolution ΔEFWHM<10eV. We measured a signal rise time τrise as low as 90ns and an energy resolution ΔEFWHM as low as 50eV for 5.9keV photons. The rise time is about an order of magnitude faster compared to other multiplexed low-temperature microcalorimeters and close to the intrinsic value set by the coupling between electron and spins. The energy resolution is degraded with respect to our design value due to a rather low intrinsic quality factor of the microwave resonators that is caused by the quality of the Josephson junction of the associated rf-SQUID as well as an elevated chip temperature as compared to the heat bath. Though the achieved energy resolution is not yet compatible with state-of-the-art single-channel MMCs, this demonstration of a scalable readout approach for MMCs in combination with the full understanding of the device performance showing ways how to improve represents an important milestone for the development of future large-scale MMC detector arrays.

  19. Development of radiation hard readout electronics for LHCb

    CERN Document Server

    Sexauer, Edgar; Lindenstruth, Volker

    2001-01-01

    The experiment LHCb is under development at CERN and aims to measure CP-violation in the B-Meson system at very high precision. The experiment makes use of a vertex detector that is equipped with silicon microstrip detectors. A chip suitable for the readout of this detector has been developed in a working group at the ASIC-laboratory Heidelberg. This readout chip 'Beetle-1.0' contains 128 analog input stages of a charge sensitive preamplifier, a pulse shaper and a buffer. The analog signal is fed into a comparator, from which a fast trigger signal can be derived. The following pipeline, realized as an array of gate capacitances, can be used to either store the analog output of the input amplifiers or to store the digital comparator output. External trigger signals mark events that have to be read out and the according pipeline location is stored in a derandomizing buffer. Pending events are read out from the pipeline via a charge-sensitive, resetable amplifier and an analog multiplexer, which serializes the s...

  20. Analysis and design of an on-chip retargeting engine for IEEE 1687 networks

    NARCIS (Netherlands)

    Ibrahim, Ahmed; Kerkhoff, Hans G.

    2016-01-01

    IEEE 1687 (iJTAG) standard introduces a methodology for accessing the increasing number of embedded instruments found in modern System-on-Chips. Retargeting is defined by iJTAG as the procedure of translating instrument-level patterns to system-level scan vectors for a certain network organization.