WorldWideScience

Sample records for radiation-hardened cmos devices

  1. Radiation Hardening and Heavy-ion to Laser Correlation in SiGe Devices and Circuits

    Science.gov (United States)

    2017-03-01

    Radiation Hardening and Heavy-ion to Laser Correlation in SiGe Devices and Circuits Zachary E. Fleetwood and John D. Cressler School of...platforms intended for radiation - intense applications and spaceflight hardware considerations. A number of new radio frequency (RF) studies have...extended the knowledge base of applying radiation -hardening-by- design (RHBD) to SiGe Heterojunction Bipolar Transistor (HBT) circuits. Other research

  2. Characterization of Radiation Hardened Bipolar Linear Devices for High Total Dose Missions

    Science.gov (United States)

    McClure, Steven S.; Harris, Richard D.; Rax, Bernard G.; Thorbourn, Dennis O.

    2012-01-01

    Radiation hardened linear devices are characterized for performance in combined total dose and displacement damage environments for a mission scenario with a high radiation level. Performance at low and high dose rate for both biased and unbiased conditions is compared and the impact to hardness assurance methodology is discussed.

  3. Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

    Science.gov (United States)

    Danchenko, V. (Inventor)

    1974-01-01

    A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

  4. Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

    Science.gov (United States)

    Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

    1989-01-01

    Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

  5. Implantable CMOS Biomedical Devices

    Directory of Open Access Journals (Sweden)

    Toshihiko Noda

    2009-11-01

    Full Text Available The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

  6. Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

    Science.gov (United States)

    Gerber, Scott S.; Hammond, Ahmad; Elbuluk, Malik E.; Patterson, Richard L.; Overton, Eric; Ghaffarian, Reza; Ramesham, Rajeshuni; Agarwal, Shri G.

    2001-01-01

    Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

  7. Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

    Science.gov (United States)

    Danchenko, V.

    1974-01-01

    Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

  8. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  9. Radiation Hardening of Computers

    Science.gov (United States)

    Nichols, D. K.; Smith, L. S.; Zoutendyk, J. A.; Giddings, A. E.; Hewlett, F. W.; Treece, R. K.

    1986-01-01

    Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips.

  10. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  11. Irradiate-anneal screening of total dose effects in semiconductor devices. [radiation hardening of spacecraft components of Mariner spacecraft

    Science.gov (United States)

    Stanley, A. G.; Price, W. E.

    1976-01-01

    An extensive investigation of irradiate-anneal (IRAN) screening against total dose radiation effects was carried out as part of a program to harden the Mariner Jupiter/Saturn 1977 (MJS'77) spacecraft to survive the Jupiter radiation belts. The method consists of irradiating semiconductor devices with Cobalt-60 to a suitable total dose under representative bias conditions and of separating the parts in the undesired tail of the distribution from the bulk of the parts by means of a predetermined acceptance limit. The acceptable devices are then restored close to their preirradiation condition by annealing them at an elevated temperature. IRAN was used when lot screen methods were impracticable due to lack of time, and when members of a lot showed a diversity of radiation response. The feasibility of the technique was determined by testing of a number of types of linear bipolar integrated circuits, analog switches, n-channel JFETS and bipolar transistors. Based on the results of these experiments a number of device types were selected for IRAN of flight parts in the MJS'77 spacecraft systems. The part types, screening doses, acceptance criteria, number of parts tested and rejected as well as the program steps are detailed.

  12. Radiation hardened COTS-based 32-bit microprocessor; Microprocesseur 32 bits durci aux radiations base sur un produit commercial

    Energy Technology Data Exchange (ETDEWEB)

    Haddad, N.; Brown, R.; Cronauer, T.; Phan, H. [Lockheed Martin Space Electronics and Communications, Manassas, VA (United States)

    1999-07-01

    A high performance radiation hardened 32-bit RISC microprocessor based upon a commercial single chip CPU has been developed. This paper presents the features of radiation hardened microprocessor, the methods used to radiation harden this device, the results of radiation testing, and shows that the RAD6000 is well-suited for the vast majority of space applications. (authors)

  13. Multi-MGy Radiation Hardened Camera for Nuclear Facilities

    Energy Technology Data Exchange (ETDEWEB)

    Girard, Sylvain; Boukenter, Aziz; Ouerdane, Youcef [Universite de Saint-Etienne, Lab. Hubert Curien, UMR-CNRS 5516, F-42000 Saint-Etienne (France); Goiffon, Vincent; Corbiere, Franck; Rolando, Sebastien; Molina, Romain; Estribeau, Magali; Avon, Barbara; Magnan, Pierre [ISAE, Universite de Toulouse, F-31055 Toulouse (France); Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Raine, Melanie [CEA, DAM, DIF, F-91297 Arpajon (France)

    2015-07-01

    There is an increasing interest in developing cameras for surveillance systems to monitor nuclear facilities or nuclear waste storages. Particularly, for today's and the next generation of nuclear facilities increasing safety requirements consecutive to Fukushima Daiichi's disaster have to be considered. For some applications, radiation tolerance needs to overcome doses in the MGy(SiO{sub 2}) range whereas the most tolerant commercial or prototypes products based on solid state image sensors withstand doses up to few kGy. The objective of this work is to present the radiation hardening strategy developed by our research groups to enhance the tolerance to ionizing radiations of the various subparts of these imaging systems by working simultaneously at the component and system design levels. Developing radiation-hardened camera implies to combine several radiation-hardening strategies. In our case, we decided not to use the simplest one, the shielding approach. This approach is efficient but limits the camera miniaturization and is not compatible with its future integration in remote-handling or robotic systems. Then, the hardening-by-component strategy appears mandatory to avoid the failure of one of the camera subparts at doses lower than the MGy. Concerning the image sensor itself, the used technology is a CMOS Image Sensor (CIS) designed by ISAE team with custom pixel designs used to mitigate the total ionizing dose (TID) effects that occur well below the MGy range in classical image sensors (e.g. Charge Coupled Devices (CCD), Charge Injection Devices (CID) and classical Active Pixel Sensors (APS)), such as the complete loss of functionality, the dark current increase and the gain drop. We'll present at the conference a comparative study between these radiation-hardened pixel radiation responses with respect to conventional ones, demonstrating the efficiency of the choices made. The targeted strategy to develop the complete radiation hard camera

  14. System-Level Radiation Hardening

    Science.gov (United States)

    Ladbury, Ray

    2014-01-01

    Although system-level radiation hardening can enable the use of high-performance components and enhance the capabilities of a spacecraft, hardening techniques can be costly and can compromise the very performance designers sought from the high-performance components. Moreover, such techniques often result in a complicated design, especially if several complex commercial microcircuits are used, each posing its own hardening challenges. The latter risk is particularly acute for Commercial-Off-The-Shelf components since high-performance parts (e.g. double-data-rate synchronous dynamic random access memories - DDR SDRAMs) may require other high-performance commercial parts (e.g. processors) to support their operation. For these reasons, it is essential that system-level radiation hardening be a coordinated effort, from setting requirements through testing up to and including validation.

  15. Radiation hardening of diagnostics

    Science.gov (United States)

    Siemon, R. E.

    The world fusion program has advanced to the stage where it is appropriate to construct a number of devices for the purpose of burning DT fuel. In these next-generation experiments, the expected flux and fluence of 14 MeV neutrons and associated gamma rays will pose a significant challenge to the operation and diagnostics of the fusion device. Radiation effects include structural damage to materials such as vacuum windows and seals, modifications to electrical properties such as electrical conductivity and dielectric strength and impaired optical properties such as reduced transparency and luminescence of windows and fiber optics during irradiation. In preparation for construction and operation of these new facilities, the fusion diagnostics community needs to work with materials scientists to develop a better understanding of radiation effects, and to undertake a testing program aimed at developing workable solutions for this multi-faceted problem. A unique facility to help in this regard is the Los Alamos Spallation Radiation Effects Facility, a neutron source located at the beam stop of the world's most powerful accelerator, the Los Alamos Meson Physics Facility (LAMPF). The LAMPF proton beam generates 10(exp 16) neutrons per second because of spallation'reactions when the protons collide with the copper nuclei in the beam stop.

  16. Radiation Hardened Electronics for Extreme Environments

    Science.gov (United States)

    Keys, Andrew S.; Watson, Michael D.

    2007-01-01

    The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

  17. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  18. Decline in Radiation Hardened Microcircuit Infrastructure

    Science.gov (United States)

    LaBel, Kenneth A.

    2015-01-01

    Two areas of radiation hardened microcircuit infrastructure will be discussed: 1) The availability and performance of radiation hardened microcircuits, and, and 2) The access to radiation test facilities primarily for proton single event effects (SEE) testing. Other areas not discussed, but are a concern include: The challenge for maintaining radiation effects tool access for assurance purposes, and, the access to radiation test facilities primarily for heavy ion single event effects (SEE) testing. Status and implications will be discussed for each area.

  19. A Review of NASA's Radiation-Hardened Electronics for Space Environments Project

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Patrick, Marshall C.; Johnson, Michael A.; Cressler, John D.

    2008-01-01

    NASA's Radiation Hardened Electronics for Space Exploration (RHESE) project develops the advanced technologies required to produce radiation hardened electronics, processors, and devices in support of the requirements of NASA's Constellation program. Over the past year, multiple advancements have been made within each of the RHESE technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of these advancements, discusses their application to Constellation projects, and addresses the plans for the coming year.

  20. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  1. Radiation Hardening of Silicon Detectors

    CERN Multimedia

    Leroy, C; Glaser, M

    2002-01-01

    %RD48 %title\\\\ \\\\Silicon detectors will be widely used in experiments at the CERN Large Hadron Collider where high radiation levels will cause significant bulk damage. In addition to increased leakage current and charge collection losses worsening the signal to noise, the induced radiation damage changes the effective doping concentration and represents the limiting factor to long term operation of silicon detectors. The objectives are to develop radiation hard silicon detectors that can operate beyond the limits of the present devices and that ensure guaranteed operation for the whole lifetime of the LHC experimental programme. Radiation induced defect modelling and experimental results show that the silicon radiation hardness depends on the atomic impurities present in the initial monocrystalline material.\\\\ \\\\ Float zone (FZ) silicon materials with addition of oxygen, carbon, nitrogen, germanium and tin were produced as well as epitaxial silicon materials with epilayers up to 200 $\\mu$m thickness. Their im...

  2. CMOS and BiCMOS process integration and device characterization

    CERN Document Server

    El-Kareh, Badih

    2009-01-01

    Covers both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. This book also covers silicon devices and integrated process technologies. It discusses modern silicon devices, their characteristics, and interactions with process parameters.

  3. Developments in Radiation-Hardened Electronics Applicable to the Vision for Space Exploration

    Science.gov (United States)

    Keys, Andrew S.; Frazier, Donald O.; Patrick , Marshall C.; Watson, Michael D.; Johnson, Michael A.; Cressler, John D.; Kolawa, Elizabeth A.

    2007-01-01

    The Radiation Hardened Electronics for Space Exploration (RHESE) project develops the advanced technologies required to produce radiation hardened electronics, processors, and devices in support of the anticipated requirements of NASA's Constellation program. Methods of protecting and hardening electronics against the encountered space environment are discussed. Critical stages of a spaceflight mission that are vulnerable to radiation-induced interruptions or failures are identified. Solutions to mitigating the risk of radiation events are proposed through the infusion of RHESE technology products and deliverables into the Constellation program's spacecraft designs.

  4. Configurable Radiation Hardened High Speed Isolated Interface ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  5. Technology Developments in Radiation-Hardened Electronics for Space Environments

    Science.gov (United States)

    Keys, Andrew S.; Howell, Joe T.

    2008-01-01

    The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.

  6. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  7. Open Source Radiation Hardened by Design Technology

    Science.gov (United States)

    Shuler, Robert

    2016-01-01

    The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.

  8. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    Science.gov (United States)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  9. Radiation Hardened Ethernet PHY and Switch Fabric Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Innoflight will develop a new family of radiation hardened (up to 3 Mrad(Si)), fault-tolerant, high data-rate (up to 8 Gbps), low power Gigabit Ethernet PHY and...

  10. Technologies Enabling Custom Radiation-Hardened Component Development Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Two primary paths are available for the creation of a Rad-Hard ASIC. The first approach is to use a radiation hardened process such as existing Rad-Hard foundries....

  11. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Space Micro proposes to build a radiation hardened by design (RHBD) flash memory, using a modified version of our RH-eDRAM Memory Controller to solve all the single...

  12. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation hardened nonvolatile memories for space is still primarily confined to EEPROM. There is high density effective or cost effective NVM solution available to...

  13. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  14. TID Simulation of Advanced CMOS Devices for Space Applications

    Science.gov (United States)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  15. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  16. Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

    Science.gov (United States)

    Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

    2017-01-01

    Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

  17. Radiation Hardened Turbo Coded OFDM Modulator Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Space Micro Inc. proposes to develop an innovative Turbo-Coded Orthogonal Frequency Division Modulation (TC-OFDM) ASIC device. The proposed device provides data...

  18. Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

    Energy Technology Data Exchange (ETDEWEB)

    Holbert, Keith E. [Arizona State Univ., Tempe, AZ (United States); Clark, Lawrence T. [Arizona State Univ., Tempe, AZ (United States)

    2016-02-19

    Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance to megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration

  19. High-Performance, Radiation-Hardened Electronics for Space Environments

    Science.gov (United States)

    Keys, Andrew S.; Watson, Michael D.; Frazier, Donald O.; Adams, James H.; Johnson, Michael A.; Kolawa, Elizabeth A.

    2007-01-01

    The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog

  20. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  1. The power conversion efficiency of visible light emitting devices in standard BiCMOS processes

    NARCIS (Netherlands)

    Kuindersma, P.; Hoang, T.; Schmitz, Jurriaan; Vijayaraghavan, M.N.; Dijkstra, Mindert; Dijkstra, M.; van Noort, W.A.; Vanhoucke, T.; Peters, W.C.M.; Kramer, M.C.J.C.M.

    2008-01-01

    We present experimental and theoretical proof for a single and unique relationship between the breakdown voltage and power efficiency of visible light emitting devices fabricated in standard BiCMOS processes.

  2. The development of radiation hardened robot for nuclear facility

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Seung Ho; Jung, Seung Ho; Kim, Byung Soo and others

    2000-04-01

    The work conducted in this stage covers development of core technology of tele-robot system including monitoring technique in high-level radioactive area, tele-sensing technology and radiation-hardened technology for the non-destructive tele-inspection system which monitors the primary coolant system during the normal operations of PHWR(Pressurized Heavy Water Reactor) NPPs and measures the decrease of bending part of feeder pipe during overall. Based on the developed core technology, the monitoring mobile robot system of the primary coolant system and the feeder pipe inspecting robot system are developed.

  3. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Directory of Open Access Journals (Sweden)

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  4. Radiation-Hardened Memristor-based Memory for Extreme Environments Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA space exploration missions require radiation-hardened memory technologies that can survive and operate over a wide temperature range. Memristors...

  5. Some new results on irradiation characteristics of synthetic quartz crystals and their application to radiation hardening

    Science.gov (United States)

    Bahadur, H.; Parshad, R.

    1983-01-01

    The paper reports some new results on irradiation characteristics of synthetic quartz crystals and their application to radiation hardening. The present results show how the frequency shift in quartz crystals can be influenced by heat processing prior to irradiation and how this procedure can lead to radiation hardening for obtaining precise frequencies and time intervals from quartz oscillators in space.

  6. Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

    Directory of Open Access Journals (Sweden)

    Liang Zhou

    2015-10-01

    Full Text Available This paper proposes a radiation hardened NULL Convention Logic (NCL architecture that can recover from a single event latchup (SEL or single event upset (SEU fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.

  7. Radiation Hardening by Software Techniques on FPGAs: Flight Experiment Evaluation and Results

    Science.gov (United States)

    Schmidt, Andrew G.; Flatley, Thomas

    2017-01-01

    We present our work on implementing Radiation Hardening by Software (RHBSW) techniques on the Xilinx Virtex5 FPGAs PowerPC 440 processors on the SpaceCube 2.0 platform. The techniques have been matured and tested through simulation modeling, fault emulation, laser fault injection and now in a flight experiment, as part of the Space Test Program- Houston 4-ISS SpaceCube Experiment 2.0 (STP-H4-ISE 2.0). This work leverages concepts such as heartbeat monitoring, control flow assertions, and checkpointing, commonly used in the High Performance Computing industry, and adapts them for use in remote sensing embedded systems. These techniques are extremely low overhead (typically radiation hardened processor. The recently concluded STP-H4 flight experiment was an opportunity to upgrade the RHBSW techniques for the Virtex5 FPGA and demonstrate them on-board the ISS to achieve TRL 7. This work details the implementation of the RHBSW techniques, that were previously developed for the Virtex4-based SpaceCube 1.0 platform, on the Virtex5-based SpaceCube 2.0 flight platform. The evaluation spans the development and integration with flight software, remotely uploading the new experiment to the ISS SpaceCube 2.0 platform, and conducting the experiment continuously for 16 days before the platform was decommissioned. The experiment was conducted on two PowerPCs embedded within the Virtex5 FPGA devices and the experiment collected 19,400 checkpoints, processed 253,482 status messages, and incurred 0 faults. These results are highly encouraging and future work is looking into longer duration testing as part of the STP-H5 flight experiment.

  8. Optimized radiation-hardened erbium doped fiber amplifiers for long space missions

    Science.gov (United States)

    Ladaci, A.; Girard, S.; Mescia, L.; Robin, T.; Laurent, A.; Cadier, B.; Boutillier, M.; Ouerdane, Y.; Boukenter, A.

    2017-04-01

    In this work, we developed and exploited simulation tools to optimize the performances of rare earth doped fiber amplifiers (REDFAs) for space missions. To describe these systems, a state-of-the-art model based on the rate equations and the particle swarm optimization technique is developed in which we also consider the main radiation effect on REDFA: the radiation induced attenuation (RIA). After the validation of this tool set by confrontation between theoretical and experimental results, we investigate how the deleterious radiation effects on the amplifier performance can be mitigated following adequate strategies to conceive the REDFA architecture. The tool set was validated by comparing the calculated Erbium-doped fiber amplifier (EDFA) gain degradation under X-rays at ˜300 krad(SiO2) with the corresponding experimental results. Two versions of the same fibers were used in this work, a standard optical fiber and a radiation hardened fiber, obtained by loading the previous fiber with hydrogen gas. Based on these fibers, standard and radiation hardened EDFAs were manufactured and tested in different operating configurations, and the obtained data were compared with simulation data done considering the same EDFA structure and fiber properties. This comparison reveals a good agreement between simulated gain and experimental data (architecture evolutions in the amplifier performance during the space mission. Optimization of both the fiber length and the EDFA pumping scheme allows us to strongly reduce its radiation vulnerability in terms of gain. The presented approach is a complementary and effective tool for hardening by device techniques and opens new perspectives for the applications of REDFAs and lasers in harsh environments.

  9. Non Radiation Hardened Microprocessors in Spaced Based Remote Sensing Systems

    Science.gov (United States)

    Decoursey, Robert J.; Estes, Robert F.; Melton, Ryan

    2006-01-01

    The CALIPSO (Cloud-Aerosol Lidar and Infrared Pathfinder Satellite Observations) mission is a comprehensive suite of active and passive sensors including a 20Hz 230mj Nd:YAG lidar, a visible wavelength Earth-looking camera and an imaging infrared radiometer. CALIPSO flies in formation with the Earth Observing System Post-Meridian (EOS PM) train, provides continuous, near-simultaneous measurements and is a planned 3 year mission. CALIPSO was launched into a 98 degree sun synchronous Earth orbit in April of 2006 to study clouds and aerosols and acquires over 5 gigabytes of data every 24 hours. The ground track of one CALIPSO orbit as well as high and low intensity South Atlantic Anomaly outlines is shown. CALIPSO passes through the SAA several times each day. Spaced based remote sensing systems that include multiple instruments and/or instruments such as lidar generate large volumes of data and require robust real-time hardware and software mechanisms and high throughput processors. Due to onboard storage restrictions and telemetry downlink limitations these systems must pre-process and reduce the data before sending it to the ground. This onboard processing and realtime requirement load may mean that newer more powerful processors are needed even though acceptable radiation-hardened versions have not yet been released. CALIPSO's single board computer payload controller processor is actually a set of four (4) voting non-radiation hardened COTS Power PC 603r's built on a single width VME card by General Dynamics Advanced Information Systems (GDAIS). Significant radiation concerns for CALIPSO and other Low Earth Orbit (LEO) satellites include the South Atlantic Anomaly (SAA), the north and south poles and strong solar events. Over much of South America and extending into the South Atlantic Ocean the Van Allen radiation belts dip to just 200-800km and spacecraft entering this area are subjected to high energy protons and experience higher than normal Single Event Upset

  10. Evolution of radiation defect and radiation hardening in heat treated SA508 Gr3 steel

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Hyung-Ha; Kwon, Junhyun [Nuclear Materials Division, Korea Atomic Energy Research Institute, 989-111 Daeduck-daero, Yuseong-gu, Daejeon 305-353 (Korea, Republic of); Shin, Chansun, E-mail: c.shin@mju.ac.kr [Department of Materials Science and Engineering, Myongji University, 116 Myongji-ro, Cheoin-gu, Youngin-shi, Gyeonggi-do 449-728 (Korea, Republic of)

    2014-01-15

    The formation of radiation defects and corresponding radiation hardening in heat-treated SA508 Gr3 steel after Fe ion irradiation were investigated by means of transmission electron microscopy and a nano-indentation technique. As the residual dislocation density is increased in the matrix, the formation of radiation defects is considerably weakened. Comparison between the characteristics of the radiation defect and an evaluation of radiation hardening indicates that a large dislocation loop contributes little to the radiation hardening in the heat-treated SA508 Gr3 steel.

  11. Evolution of radiation defect and radiation hardening in heat treated SA508 Gr3 steel

    Science.gov (United States)

    Jin, Hyung-Ha; Kwon, Junhyun; Shin, Chansun

    2014-01-01

    The formation of radiation defects and corresponding radiation hardening in heat-treated SA508 Gr3 steel after Fe ion irradiation were investigated by means of transmission electron microscopy and a nano-indentation technique. As the residual dislocation density is increased in the matrix, the formation of radiation defects is considerably weakened. Comparison between the characteristics of the radiation defect and an evaluation of radiation hardening indicates that a large dislocation loop contributes little to the radiation hardening in the heat-treated SA508 Gr3 steel.

  12. Radiation Hardened Nanobridge based Non-volatile Memory for Space Applications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This NASA Phase I SBIR program would develop and demonstrate radiation hardened nanobridge based non-volatile memory (NVM) for space applications. Specifically, we...

  13. Radiation-Hardened, Substrate-Removed, Metamorphic InGaAs Detector Arrays Project

    Data.gov (United States)

    National Aeronautics and Space Administration — High-performance radiation-hardened metamorphic InGaAs imaging arrays sensitive from the ultraviolet (UV) through the short-wavelength infrared (SWIR) will be...

  14. A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low...

  15. Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

    Science.gov (United States)

    Deleonibus, S.

    2006-12-01

    Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, ...), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS.

  16. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  17. First principle leakage current reduction technique for CMOS devices

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-12-01

    Full Text Available that the device is suitable for low power applications. Physical models used for simulation included SI(sub3)N(sub4) and HfO(sub2) as gate dielectric with TiSix as metal gate. From the simulation result, it was shown that HfO2 was the best dielectric material when...

  18. CMOS Compatible SOI MESFETs for Radiation Hardened DC-to-DC Converters Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We have developed a novel metal-semiconductor field-effect-transistor (MESFET) technology suitable for extreme environment electronics. The MESFET technology is...

  19. Estimation of radiation hardening in ferritic steels using the cluster dynamics models

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Jun Hyun; Kim, Whung Whoe; Hong, Jun Hwa [Korea Atomic Energy Research Institute, Taejon (Korea, Republic of)

    2005-07-01

    Evolution of microstructure under irradiation brings about the mechanical property changes of materials, of which the major concern is radiation hardening in this work. Radiation hardening is generally expressed in terms of an increase in yield strength as a function of radiation dose and temperature. Cluster dynamics model for radiation hardening has been developed to describe the evolution of point defects clusters (PDCs) and copperrich precipitates (CRPs). While the mathematical models developed by Stoller focus on the evolution of PDCs in ferritic steels under neutron irradiation, we slightly modify the model by including the CRP growth and estimate the magnitude of hardening induced by PDC and CRP. The model is then used to calculate the changes in yield strength of RPV steels. The calculation results are compared to measured yield strength values, obtained from surveillance testing of PWR vessel steels in France.

  20. Dual-PLL based on Temporal Redundancy for Radiation-Hardening

    OpenAIRE

    Kim, SinNyoung; Tsuchiya, Akira; Onodera, Hidetoshi

    2013-01-01

    This paper proposes a dual-PLL based on temporal redundancy for radiation-hardening. A common practice technique for radiation-hardening is the triple modular redundancy (TMR). However, it is inefficient to apply for PLLs because PLLs include huge size of capacitance and static current consumers, means analog circuits. Thus, we propose a dual-PLL and a detective circuit that detects a perturbed PLL by radiation-strike. Although our proposal is based on DMR, it allows both detecting and correc...

  1. Radiation hardening of components and systems for nuclear rocket vehicle applications

    Science.gov (United States)

    Greenhow, W. A.; Cheever, P. R.

    1972-01-01

    The results of the analysis of the S-2 and S-4B components, although incomplete, indicate that many Saturn 5 components and subsystems, e.g., pumps, valves, etc., can be radiation hardened to meet NRV requirements by material substitution and minor design modifications. Results of these analyses include (1) recommended radiation tolerance limits for over 100 material applications; (2) design data which describes the components of each system; (3) presentation of radiation hardening examples of systems; and (4) designing radiation effects tests to supply data for selecting materials.

  2. Development of radiation hardened pixel sensors for charged particle detection

    CERN Document Server

    Koziel, Michal

    2014-01-01

    CMOS Pixel Sensors are being developed since a few years to equip vertex detectors for future high-energy physics experiments with the crucial advantages of a low material budget and low production costs. The features simultaneously required are a short readout time, high granularity and high tolerance to radiation. This thesis mainly focuses on the radiation tolerance studies. To achieve the targeted readout time (tens of microseconds), the sensor pixel readout was organized in parallel columns restricting in addition the readout to pixels that had collected the signal charge. The pixels became then more complex, and consequently more sensitive to radiation. Different in-pixel architectures were studied and it was concluded that the tolerance to ionizing radiation was limited to 300 krad with the 0.35- m fabrication process currently used, while the targeted value was several Mrad. Improving this situation calls for implementation of the sensors in processes with a smaller feature size which naturally imp...

  3. Parylene to silicon nitride bonding for post-integration of high pressure microfluidics to CMOS devices.

    Science.gov (United States)

    Ciftlik, Ata Tuna; Gijs, Martin A M

    2012-01-21

    High pressure-rated channels allow microfluidic assays to be performed on a smaller footprint while keeping the throughput, thanks to the higher enabled flow rates, opening up perspectives for cost-effective integration of CMOS chips to microfluidic circuits. Accordingly, this study introduces an easy, low-cost and efficient method for realizing high pressure microfluidics-to-CMOS integration. First, we report a new low temperature (280 °C) Parylene-C wafer bonding technique, where O(2) plasma-treated Parylene-C bonds directly to Si(3)N(4) with an average bonding strength of 23 MPa. The technique works for silicon wafers with a nitride surface and uses a single layer of Parylene-C deposited only on one wafer, and allows microfluidic structures to be easily formed by directly bonding to the nitride passivation layer of the CMOS devices. Exploiting this technology, we demonstrated a microfluidic chip burst pressure as high as 16 MPa, while metal electrode structures on the silicon wafer remained functional after bonding.

  4. Radiation Hardening and Verification Procedure for Compact Flip-Flop Design

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Inyong; Sung, Seung Hwan [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    For radiation-related applications applying electronic devices in nuclear, space, medicine, and scientific experiment, single event transients (SETs) and single event upsets (SEUs) are become primary concern since they can cause malfunctions in a system by affecting the signal transition and flipping digital bits. The D flip-flop as a register is generally used in digital circuits that require data stability and high speed. For many years, radiation-hardened-by-design (RHBD) circuits have been gradually developed from traditional circuit architectures. One of common methods is to exploit redundancy in an important circuit block to preserve the correct signal. This technique uses a voting process to have a correct output when other duplicated systems fail due to a single event effect (SEE) including SET and SEU. For instance, B. Olson applied the redundancy technique, formally referred the triple modular redundancy (TMR). Other researchers use various error detection and correction (EDAC) algorithms including redundant bits in the storage circuits to detect and correct errors at the system level. practical experiments at radiation exposure facilities. Korea Atomic Energy Research Institute (KAERI) operates a laboratory with high energy radioactive isotope, {sup 60}Co in Jeongeup, Korea. The facility can provide various experiments requiring experimental environment changes by controlling radiation activity and radiated energy. The future direction on RHBD circuits would be integration with the digital DFF presented in this paper and analog front-end units such as OP-amp for charge sensitive or shaping amplifier. Analog-to-digital converters (ADCs) are also major components necessarily imbedded in the most of sensor related electronics. Thus RHBD techniques are inevitably required to protect these circuits from SEE; specifically, SEUs for digital logics and SETs for analog signals. Since most ADCs consist of both analog and digital circuits in their architectures

  5. The design of radiation-hardened ICs for space - A compendium of approaches

    Science.gov (United States)

    Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

    1988-01-01

    Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

  6. Electro-optical modulating multistack device based on the CMOS-compatible technology of amorphous silicon

    Science.gov (United States)

    Rao, S.; Della Corte, F. G.

    2010-09-01

    In this paper we report results on a field-effect induced light modulation at λ = 1.55 um in a high-index-contrast waveguide based on a multisilicon-on-insulator (MSOI) platform. The device is realized with the hydrogenated amorphous silicon (α-Si:H) technology and it is suitable for monolithic integration in a CMOS Integrated Circuit. The device exploits the free carrier optical absorption electrically induced in the semiconductor core waveguide. The dynamic behaviour of the device was experimentally and theoretically analyzed in presence of a visible illumination showing a link between the photogeneration and the free carriers provided by doped α-Si:H layers. The core waveguide contains several thin dielectric films of amorphous silicon carbonitride (α-SiCN) embedded along its thickness highly enhancing the absorbing action of the modulator held in the on-state.

  7. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  8. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  9. Analysis of the performance of CMOS APS imagers after proton damage

    Science.gov (United States)

    Meroli, S.; Passeri, D.; Servoli, L.; Angelucci, A.

    2013-02-01

    In this work we have irradiated a standard commercial CMOS imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, Catania (Italy) up to a nominal fluence of 1014 [protons/cm-2]. The device under test was a standard VGA detector, fabricated with a 130 nm technology without radiation hardening. During the irradiation the detector was operated to monitor the progressive damaging of the sensor and the associated on-pixel electronics. After 18 months from the irradiation damage session, with the detector stored at room temperature, a study on the detection efficiency and charge collection capability has been carried out using fluorescent X-ray photons, emitted from copper target. We found that the detector is still working at 1013 protons/cm2, with a moderate increase of the noise and a slightly decrease of the detection capabilities.

  10. New technologies for radiation-hardening analog to digital converters

    Science.gov (United States)

    Gauthier, M. K.

    1982-01-01

    Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

  11. Final report on LDRD project 52722 : radiation hardened optoelectronic components for space-based applications.

    Energy Technology Data Exchange (ETDEWEB)

    Hargett, Terry W. (L& M Technologies, Inc.); Serkland, Darwin Keith; Blansett, Ethan L.; Geib, Kent Martin; Sullivan, Charles Thomas; Hawkins, Samuel D.; Wrobel, Theodore Frank; Keeler, Gordon Arthur; Klem, John Frederick; Medrano, Melissa R.; Peake, Gregory Merwin; Karpen, Gary D.; Montano, Victoria A. (L& M Technologies, Inc.)

    2003-12-01

    This report describes the research accomplishments achieved under the LDRD Project 'Radiation Hardened Optoelectronic Components for Space-Based Applications.' The aim of this LDRD has been to investigate the radiation hardness of vertical-cavity surface-emitting lasers (VCSELs) and photodiodes by looking at both the effects of total dose and of single-event upsets on the electrical and optical characteristics of VCSELs and photodiodes. These investigations were intended to provide guidance for the eventual integration of radiation hardened VCSELs and photodiodes with rad-hard driver and receiver electronics from an external vendor for space applications. During this one-year project, we have fabricated GaAs-based VCSELs and photodiodes, investigated ionization-induced transient effects due to high-energy protons, and measured the degradation of performance from both high-energy protons and neutrons.

  12. Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

    Science.gov (United States)

    Zand, Ramtin; DeMara, Ronald F.

    2017-12-01

    In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

  13. A Compact, Radiation Hardened, Stable, Low Power, Programmable Crystal Oscillator for Extreme Temperature and High Reliability Space Application Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose a feasibility study of a fully intgrated radiation hardened (>1Mrad/si), programmable crystal oscilator (RPXO) in a miniature package that will deliver...

  14. Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Report 3

    Energy Technology Data Exchange (ETDEWEB)

    Britton, Jr, Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Shelton, Jacob H. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

    2015-03-01

    As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios when human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments because of the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is a report of the activities involving Task 3 of the Nuclear Energy Enabling Technologies (NEET) 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays [1]. Evaluation of the performance of the system for both pre- and post-irradiation as well as operation at elevated temperature will be performed. Detailed performance of the system will be documented to ensure the design meets requirements prior to any extended evaluation. A suite of tests will be developed which will allow evaluation before and after irradiation and during temperature. Selection of the radiation exposure facilities will be determined in the early phase of the project. Radiation exposure will consist of total integrated dose (TID) up to 200 kRad or above with several intermediate doses during test. Dose rates will be in various ranges determined by the facility that will be used with a target of 30 kRad/hr. Many samples of the pre-commercial devices to be used will have been tested in previous projects to doses of at least 300 kRad and temperatures up to 125C. The complete systems will therefore be tested for performance at intermediate doses. Extended temperature testing will be performed up to the limit of the commercial sensors. The test suite performed at each test point will consist of operational testing of the three basic

  15. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  16. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  17. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  18. Fabrication and Characterization of a CMOS-Based Quantum Dot Device

    Science.gov (United States)

    Xiao, Ming; Yablonovitch, E.; Jiang, H. W.

    2008-03-01

    Silicon-based single electron devices are particularly attractive for implementing quantum information processing due to the extremely long electron spin lifetimes. We report here the demonstration of a stack-gated CMOS structure that can define a quantum dot in the few-electron regime and can be integrated with a sensitive, high bandwidth field effect transistor. Multiple lower layer side gates, as small as 50nm, on an ion-implanted Si/SiO2 wafer electrostatically define the quantum dot. A top gate that controls the electron population in the quantum dot is then fabricated on top of an isolating Al2O3 layer made by atomic layer deposition (ALD). The low-temperature ALD process provides excellent device stability while preserving the integrity of the side gates. We found that the devices can be operated effectively both in the accumulation mode and in the depletion mode. Transport through the quantum dots in the few-electron regime for currents less than 100fA can be reliably studied with a good reproducibility. We will detail our fabrication and characterization processes in this presentation.

  19. Radiation Hardened Telerobotic Dismantling System Development Final Report CRADA No. TC-1340-96

    Energy Technology Data Exchange (ETDEWEB)

    Smith, C. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Lightman, A. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2017-09-27

    This project was a collaborative effort between the University of California, LLNL and RedZone Robotics, Inc. for the development of radiation-hardened telerobotic dismantling systems for use in applications such as nuclear facility remediation, nuclear accident response, and Chemobyltype remediation. The project supported the design, development, fabrication and testing of a Ukrainian robotic systems. The project was completed on time and within budget. All deliverables were completed. The final project deliverables were consistent with the plans developed in the original project with the exception that the fabricated systems remained in Ukraine.

  20. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  1. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  2. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  3. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices

    Science.gov (United States)

    Staple, Bevan D.; Watts, Herman A.; Dyck, Christopher W.; Griego, A. P.; Hewlett, F. W.; Smith, James H.

    1998-09-01

    Thy monolithic integration of MicroElectroMechanical Systems (MEMS) with the driving, controlling, and signal processing electronics promises to improve the performance of micromechanical devices as well as lower their manufacturing, packaging, and instrumentation costs. Key to this integration is the proper interleaving, combining, and customizing of the manufacturing processes to produce functional integrated micromechanical devices with electronics. We have developed a MEMS-first monolithic integrated process that first seals the micromechanical devices in a planarized trench and then builds the electronics in a conventional CMOS process. To date, most of the research published on this technology has focused on the performance characteristics of the mechanical portion of the devices, with little information on the attributes of the accompanying electronics. This work attempts to reduce this information void by presenting the results of SPICE Level 3 and BSIM3v3.1 model parameters extracted for the CMOS portion of the MEMS-first process. Transistor-level simulations of MOSFET current, capacitance, output resistance, and transconductance versus voltage using the extracted model parameters closely match the measured data. Moreover, in model validation efforts, circuit-level simulation values for the average gate propagation delay in a 101-stage ring oscillator are within 13 - 18% of the measured data. These results establish the following: (1) the MEMS-first approach produces functional CMOS devices integrated on a single chip with MEMS devices and (2) the devices manufactured in the approach have excellent transistor characteristics. Thus, the MEMS-first approach renders a solid technology foundation for customers designing in the technology.

  4. Fabrication and total dose testing of a 256K x 1 radiation-hardened SRAM

    Science.gov (United States)

    Kushner, R. A.; Kohler, R. A.; Steenwyk, S. D.; Desko, J. C.; Alchesky, L. C.

    1988-12-01

    A 256K x 1 radiation-hard SRAM and the process enhancements that resulted in its successful fabrication are described, and total-dose-exposure results are presented. Typical performance values include an address-activated access time of 36 nsec and a write time of 34 nsec. Soft-error studies predict the memory cell to be SEU-insensitive, and rail-span collapse simulations estimate transient dose immunity to greater than 4 Grad(Si)/sec. The technology used was a standard 1.0-micron two-level metal, non-SORT CMOS, radiation-hard process. SORT (selective oxidation to reduce topography) is a process that uses silicon nitride masking of active device areas during field oxide growth to reduce vertical dimensions. To improve reliability and cosmetic quality, the process has been modified to provide about 50-percent metal step coverage at both metal levels.

  5. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Science.gov (United States)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  6. Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Final Report

    Energy Technology Data Exchange (ETDEWEB)

    Britton, Jr., Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Bobrek, Miljko [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

    2015-12-01

    As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios where human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments due the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is the final report of the activities involving the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. We present a detailed functional block diagram of the proposed data acquisition system, the thought process leading to technical decisions, the implemented system, and the tested results from the systems. This system will be capable of monitoring at least three parameters of importance to nuclear reactor monitoring: temperature, radiation level, and pressure.

  7. Effects of initial microstructure and helium production on radiation hardening in F82H Steels

    Energy Technology Data Exchange (ETDEWEB)

    Okubo, N.; Wakai, E.; Takada, F.; Jitsukawa, S. [Japan Atomic Energy Agency, Naga-gun, Ibaraki-ken (Japan); Katoh, Y. [Oak Ridge Noational Laboratory, TN (United States)

    2007-07-01

    Full text of publication follows: Fission neutron irradiation to steels doped with isotope boron-10 is frequently conducted to study effects of the helium production on mechanical properties. The intrinsic mechanical properties of F82H steels could have been changed due to the boron doping. Recently, we reported that co-doping with boron and nitrogen to F82H (F82H+B+N) improved the mechanical properties of F82H doped only with boron. The mechanical properties of F82H+B+N are successfully comparable with the non-doped F82H before irradiation. In order to evaluate the effects of initial microstructure and helium production on radiation hardening, F82H and F82H+B+N were irradiate d Specimens used in this study were standard F82H martensitic steels, F82H steels doped with 60 mass ppm {sup 10}B and 200 ppm N (F82H+10B+N) and F82H steels doped with 60 mass ppm {sup 11}B and 200 ppm N (F82H+11B+N). Initial microstructures were changed by tempering conditions, and the tempering temperatures were at 700, 750 and 780 deg. C. Irradiation was performed at nominally 250 deg. C to 2 dpa in JMTR. Tensile properties were measured for the specimens before and after irradiation. Change of yield stress due to the irradiation in the F82H+11B+N steels depended strongly on the initial microstructure and hardness before irradiation. The radiation hardening due to helium production in the F82H+10B+N steels was less than 60 MPa in these experiments. Size of dimple in the fracture surface of specimen with helium production was larger than that with non-helium production. (authors)

  8. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  9. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  10. Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

    Science.gov (United States)

    Guichard, Alex Richard

    Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores

  11. The measuring station for research of effects of increased radiation on CCD and CMOS sensors (Radiation effects on photonics devices)

    Energy Technology Data Exchange (ETDEWEB)

    Kalicki, A.

    2005-09-01

    This work comes into being as a part of projects, realized by PERG group in cooperation with DESY (Deutsches Elektronen - Synchrotron) in Hamburg, Germany. There are two new projects being developed. X-FEL - X-ray Free Electron Laser and VUV-FEL - Vacuum Ultraviolet Free Electron Laser. The new idea is to place some electronic control systems in collider tunnel, where during operation a dose of neutron and gamma parasitic radiation is produced. Exposure to increased radiation may cause many problems in regular work of electronic devices. The goal of this diploma work was to perform irradiation sensitivity experiments of electronic components, especially CCD and CMOS sensors. As well development of low cost and real time measurement methods of radiation level using those sensors and neutron bubble detectors. Study of radiation influence on electronics components was done, physics aspects of possible effects and methods of recognition and counting. There were developed proper algorithms used for CCD and CMOS cameras and image recognition algorithm for reading neutron bubble detectors - Optical Bubble Counting Algorithm (OBCA) with user friendly graphical interface written in JAVA. This paper presents developed algorithms, scheme of measurement and results. (orig.)

  12. Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

    Science.gov (United States)

    Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

    2009-05-01

    This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

  13. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  14. A New Approach of Electronics and Photonics Convergence on Si CMOS Platform: How to Reduce Device Diversity of Photonics for Integration

    Directory of Open Access Journals (Sweden)

    Kazumi Wada

    2008-01-01

    Full Text Available Integrated photonics via Si CMOS technology has been a strategic area since electronics and photonics convergence should be the next platform for information technology. The platform is recently referred to as “Si photonics” that attracts much interest of researchers in industries as well as academia in the world. The main goal of Si Photonics is currently to reduce material diversity of photonic devices to pursuing CMOS-compatibility. In contrast, the present paper proposes another route of Si Photonics, reducing diversity of photonic devices. The proposed device unifying functionality of photonics is a microresonator with a pin diode structure that enables the Purcell effect and Franz-Keldysh effect to emit and to modulate light from SiGe alloys.

  15. A 130 nm radiation hardened flip—flop with an annular gate and a C-element

    Science.gov (United States)

    Lei, Wang; Jianhua, Jiang; Yiming, Xiang; Yumei, Zhou

    2014-01-01

    This paper presents a radiation hardened flip—flop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 μm process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell's saturation cross section by approximately two orders of magnitude with little penalty on performance.

  16. Low Temperature (30 K) TID Test Results of a Radiation Hardened 128 Channel Serial-to-Parallel Converter

    Science.gov (United States)

    Meyer, Stephen; Buchner, Stephen; Moseley, Harvey; Ray, Knute; Tuttle, Jim; Quinn, Ed; Buchanan, Ernie; Bloom, Dave; Hait, Tom; Pearce, Mike; hide

    2006-01-01

    This viewgraph presentation reviews the low temperature, Total Ionizing Dose (TID) tests of radiation hardened serial to parallel converter to be used on the James Webb Space Telescope. The test results show that the original HV583 level shifter - a COTS part -was not suitable for JWST because the supply currents exceeded specs after 20 krad( Si) .The HV584 - functionally similar to the HV583 -was designed using RHBD approach that reduced the leakage currents to within acceptable levels and had only a small effect on the level-shifted output voltage.

  17. A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

    Science.gov (United States)

    Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

    2017-04-01

    The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

  18. A MGy radiation-hardened sensor instrumentation link for nuclear reactor monitoring and remote handling

    Energy Technology Data Exchange (ETDEWEB)

    Verbeeck, Jens; Cao, Ying [KU Leuven - KUL, Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Mont Casellas, Laura; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy - F4E, c/Josep,n deg. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. OTL, 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); De Cock, Wouter; Vermeeren, Ludo [SCK-CEN, Boeretang 200, 2400 Mol (Belgium); Steyaert, Michiel [KU Leuven, ESAT-MICAS, KasteelparkArenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, KasteelparkArenberg 10, 3001 Heverlee (Belgium)

    2015-07-01

    Decommissioning, dismantling and remote handling applications in nuclear facilities all require robotic solutions that are able to survive in radiation environments. Recently raised safety, radiation hardness and cost efficiency demands from both the nuclear regulatory and the society impose severe challenges in traditional methods. For example, in case of the dismantling of the Fukushima sites, solutions that survive accumulated doses higher than 1 MGy are mandatory. To allow remote operation of these tools in nuclear environments, electronics were used to be shielded with several centimeters of lead or even completely banned in these solutions. However, shielding electronics always leads to bulky and heavy solutions, which reduces the flexibility of robotic tools. It also requires longer repair time and produces extra waste further in a dismantling or decommissioning cycle. In addition, often in current reactor designs, due to size restrictions and the need to inspect very tight areas there are limitations to the use of shielding. A MGy radiation-hardened sensor instrumentation link developed by MAGyICS provides a solution to build a flexible, easy removable and small I and C module with MGy radiation tolerance without any shielding. Hereby it removes all these pains to implement electronics in robotic tools. The demonstrated solution in this poster is developed for ITER Remote Handling equipments operating in high radiation environments (>1 MGy) in and around the Tokamak. In order to obtain adequately accurate instrumentation and control information, as well as to ease the umbilical management, there is a need of front-end electronics that will have to be located close to those actuators and sensors on the remote handling tool. In particular, for diverter remote handling, it is estimated that these components will face gamma radiation up to 300 Gy/h (in-vessel) and a total dose of 1 MGy. The radiation-hardened sensor instrumentation link presented here, consists

  19. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  20. Performance evaluation of a digital intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate

    Energy Technology Data Exchange (ETDEWEB)

    Cho, Hyosung [Department of Radiological Science, Yonsei University, 234 Maeji Heungup, Wonju 220 710 (Korea, Republic of)], E-mail: hscho1@yonsei.ac.kr; Choi, Sungil [Department of Radiological Science, Yonsei University, 234 Maeji Heungup, Wonju 220 710 (Korea, Republic of); Kim, Jongguk [Department of Physics, Myongji University, 38-2 Namdong Cheuingu, Yongin 449 728 (Korea, Republic of); Koo, Yangseo; Kim, Taewoo; Ro, Changjoon [Radiation Technology Laboratory, Vatech Co., Ltd., 75-11 Seogu Dongtan, Hwaseong 445 811 (Korea, Republic of); Lee, Bongsoo [School of Biomedical Engineering, Konkuk University, 322 Danweul, Chungju 380 701 (Korea, Republic of); Kim, Sin [Department of Nuclear and Energy Engineering, Cheju National University, 66 Chejudaehakro, Cheju 690 756 (Korea, Republic of); Kim, Hokyung [School of Mechanical Engineering, Pusan National University, 30 Jangjeun Geumjung, Pusan 609 735 (Korea, Republic of)

    2007-08-21

    As a continuation of our digital X-ray imaging sensor R and D, we have developed a cost-effective, intraoral imaging device based on the complementary-metal-oxide semiconductor (CMOS) photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35x35 {mu}m{sup 2} pixel size and a 688x910 pixel array dimension, and a high-efficiency columnar CsI(Tl) scintillator of a 90 {mu}m thickness directly deposited on a fiber-optic faceplate of a 6 {mu}m core size and an 1.46 mm thickness with 85/15 core-cladding ratio (NA{approx}1.0 in air). The fiber-optic faceplate is a highly X-ray attenuating material that minimizes X-ray absorption on the end CMOS photosensor array, thus, minimizing X-ray induced noise at the photosensor array. It uses a high light-output columnar CsI(Tl) scintillator with a peak spectral emission at 545 nm, giving better spatial resolution, but attenuates some of this light due to interfacial and optical attenuation factors. In this paper, we presented the performance analysis of the intraoral imaging device with experimental measurements and acquired X-ray images in terms of modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE)

  1. Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

    Energy Technology Data Exchange (ETDEWEB)

    Learn, Mark Walter

    2012-01-01

    The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

  2. Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

    Science.gov (United States)

    Li, Haisong; Wu, Longsheng; Yang, Bo; Jiang, Yihu

    2017-08-01

    With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n+ guard ring and p+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET’s pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 {MeV}\\cdot {{cm}}2/{mg}, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETeff from 12.5 {MeV}\\cdot {{cm}}2/{mg} to 79.5 {MeV}\\cdot {{cm}}2/{mg} and the pulse-width presents saturation tendency when the effective linear energy transfer (LETeff) value is larger than 40 {MeV}\\cdot {{cm}}2/{mg}. The test results also show that the hardened commercial standard cell’s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

  3. A Radiation-Hardened Design Flow for Advanced SoC

    Science.gov (United States)

    Liran, Tuvia; Ginosar, Ran; Alon, Dov

    2010-08-01

    The technology and design flow used for developing two advanced Systems On Chip is described. The chips are JPIC, an image compression ASIC using JPEG2000 standard, and GR712RC, a dual core LEON3FT processor. Both chips employ the Rad-Hard-By-Design RadSafe™ technology, and are implemented on a standard 0.18μm CMOS technology. Each chip size is 12x12mm, integrating more than 40 million transistors. RadSafe™ technology provides very high immunity to all radiation effects. The library was designed for high immunity to radiation and high reliability. It includes standard cells, SRAMs, all-digital DLL and I/O cells. It was proven on several test chips, demonstrating TID immunity in excess of 300Krad, proven SEL above 80MeV and SEU at 20μ2 cross section (10-12 errors/bit/day). Logic design includes EDAC, memory BIST, and techniques to minimize soft errors. Logic synthesis was performed with large timing margins and scan insertion. Physical synthesis includes a robust power grid, careful placement of I/O cells, immunity to process sensitivities, robustness to thermomechanical stress and packaging reliability. A custom 240 pins CQFP ceramic package for GR712RC was optimized for mechanical stress, hermeticity, improved supply connection for reduced impedance, and robustness to handling. A custom 208 pins PQFP plastic package was designed for JPIC.

  4. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    Directory of Open Access Journals (Sweden)

    Chia-Hua Ho

    2012-03-01

    Full Text Available This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs in the conventional Complementary Metal-Oxide Semiconductor (CMOS-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH and sensitive deoxyribonucleic acid (DNA detection ability (100 pM at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window. The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  5. Operating characteristics of radiation-hardened silicon pixel detectors for the CMS experiment

    CERN Document Server

    Hyosung, Cho

    2002-01-01

    The Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider (LHC) will have forward silicon pixel detectors as its innermost tracking device. The pixel devices will be exposed to the harsh radiation environment of the LHC. Prototype silicon pixel detectors have been designed to meet the specification of the CMS experiment. No guard ring is required on the n/sup +/ side, and guard rings on the p/sup +/ side are always kept active before and after type inversion. The whole n/sup +/ side is grounded and connected to readout chips, which greatly simplifies detector assembling and improves the stability of bump-bonded readout chips on the n/sup +/ side. Operating characteristics such as the leakage current, the full depletion voltage, and the potential distributions over guard rings were tested using standard techniques. The tests are discussed in this paper. (9 refs).

  6. Radiation-Hardened Fiber Bragg Grating Based Sensors for Harsh Environments

    Science.gov (United States)

    Morana, A.; Girard, S.; Marin, E.; Périsse, J.; Genot, J. S.; Kuhnhenn, J.; Grelin, J.; Hutter, L.; Mélin, G.; Lablonde, L.; Robin, T.; Cadier, B.; Macé, J.-R.; Boukenter, A.; Ouerdane, Y.

    2017-01-01

    Fiber Bragg Grating (FBG) based sensors are nowadays used for several applications, but, even if they present advantages for their incorporation into radiation environments, commercial-off-the-shelf devices cannot still be used in harsh conditions. We recently reported a procedure for fabricating FBGs resistant to severe constraints combining both high radiation doses up to MGy levels and operation temperatures exceeding 200°C (RadHard FBGs). Following these results, the European project HOBAN was granted by Kic InnoEnergy with the aim of developing and marketing FBG-based temperature and strain monitoring systems suitable for harsh nuclear environments (350°C temperature and MGy dose levels), with their associated instrumentation devices. In this framework, we present an accurate study about the robustness of the radiation-response of these RadHard FBGs against the main grating inscription parameters. Up to the accumulated X-ray dose of 1 MGy(SiO2), no significant radiation induced Bragg wavelength shift is observed meaning that radiations induce errors below ± 0.4°C in the temperature estimation. Moreover, a study about the dose-rate dependence (1 to 50 Gy/s) of the gratings response is also reported and confirms the high radiation hardness of our RadHard FBGs at all dose rates.

  7. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  8. CMOS Image Sensors for High Speed Applications

    OpenAIRE

    Jamal Deen, M.; Qiyin Fang; Louis Liu; Frances Tse; David Armstrong; Munir El-Desouki

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm) due to ...

  9. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  10. Analysis of Single-Event Effects in a Radiation-Hardened Low-Jitter PLL Under Heavy Ion and Pulsed Laser Irradiation

    Science.gov (United States)

    Chen, Zhuojun; Lin, Min; Ding, Ding; Zheng, Yunlong; Sang, Zehua; Zou, Shichang

    2017-01-01

    A radiation-hardened low-jitter phase-locked loop (PLL) with a low-mismatch charge pump and a robust voltage-controlled oscillator is designed in a 130 nm PD-SOI process. In order to evaluate the overall response to single-event effects, the accumulated phase jitter has been put forward, which can exclude the inherent noise floor and accumulate all the radiation-induced noise. Then the single-event sensitivity of the proposed PLL is comprehensively analyzed by heavy ion and pulsed laser tests.

  11. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  12. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  13. Evaluation on the Effect of Composition on Radiation Hardening and Embrittlement in Model FeCrAl Alloys

    Energy Technology Data Exchange (ETDEWEB)

    Field, Kevin G. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Briggs, Samuel A. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Edmondson, Philip [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Hu, Xunxiang [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Littrell, Kenneth C. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Howard, Richard [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Parish, Chad M. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Yamamoto, Yukinori [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2015-09-18

    This report details the findings of post-radiation mechanical testing and microstructural characterization performed on a series of model and commercial FeCrAl alloys to assist with the development of a cladding technology with enhanced accident tolerance. The samples investigated include model alloys with simple ferritic grain structure and two commercial alloys with minor solute additions. These samples were irradiated in the High Flux Isotope Reactor (HFIR) at Oak Ridge National Laboratory (ORNL) up to nominal doses of 7.0 dpa near or at Light Water Reactor (LWR) relevant temperatures (300-400 C). Characterization included a suite of techniques including small angle neutron scattering (SANS), atom probe tomography (APT), and transmission based electron microscopy techniques. Mechanical testing included tensile tests at room temperature on sub-sized tensile specimens. The goal of this work was to conduct detailed characterization and mechanical testing to begin establishing empirical and/or theoretical structure-property relationships for radiation-induced hardening and embrittlement in the FeCrAl alloy class. Development of such relationships will provide insight on the performance of FeCrAl alloys in an irradiation environment and will enable further development of the alloy class for applications within a LWR environment. A particular focus was made on establishing trends, including composition and radiation dose. The report highlights in detail the pertinent findings based on this work. This report shows that radiation hardening in the alloys is primarily composition dependent due to the phase separation in the high-Cr FeCrAl alloys. Other radiation induced/enhanced microstructural features were less dependent on composition and when observed at low number densities, were not a significant contributor to the observed mechanical responses. Pre-existing microstructure in the alloys was found to be important, with grain boundaries and pre-existing dislocation

  14. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  15. Behavior of faulty double BJT BiCMOS logic gates

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  16. Single event upset rate estimates for a 16-K CMOS SRAM

    Science.gov (United States)

    Browning, J. S.; Koga, R.; Kolasinski, W. A.

    1985-12-01

    A radiation-hardened 16-K CMOS SRAM has been developed for satellite and deep space applications. The RAM memory cell was modeled to predict the critical charge, necessary for single-particle upset, as a function of temperature, total dose, and hardening feedback resistance. Laboratory measurements of the single event cross section and effective funnel length were made using the Lawrence Berkeley Laboratory's 88-inch cyclotron to generate high energy krypton ions. The combination of modeled and measured parameters permitted estimation of the upset rate for the ramcell, and the mean-time-to-failure for a 512-K word, 22-bit memory system employing error detection and correction circuits while functioning in the Adam's '90 percent worst case' cosmic ray environment. This paper is presented in the form of a tutorial review, summarizing the results of substantial research efforts within the single event community.

  17. A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments

    CERN Document Server

    Cervelli, Giovanni; Moreira, Paulo

    2004-01-01

    A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-mum CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-Omega line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds. 13 Refs.

  18. Post-CMOS FinFET integration of bismuth telluride and antimony telluride thin-film-based thermoelectric devices on SoI substrate

    KAUST Repository

    Aktakka, Ethem Erkan

    2013-10-01

    This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb 2Te3) thin-film-based thermoelectric ffect transistors) via a characterized TE-film coevaporationand shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μ W from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers. © 2013 IEEE.

  19. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  20. SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

    Science.gov (United States)

    Yui, C.; Swift, G.; Fabula, J.; Carmichael, C.

    2002-01-01

    The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

  1. Dense Heterogeneous Integration for InP Bi-CMOS Technology

    Science.gov (United States)

    2009-05-01

    many mixed signal applications, having circuits composed of both Si CMOS, which possesses low power dissipation and high transistor count, and...compound semiconductor transistors with high-speed high-voltage swing performance would be advantageous. In general, heterogeneous integration (HI) of...Fastest CMOS and HBTs  / >109LowHighCoSMOS Lags latest CMOS᝺ 6ModModSiGe HBT No precision fast device, low drive >109LowModCMOS BJT only

  2. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  3. Reliability engineering in RF CMOS

    NARCIS (Netherlands)

    Sasse, G.T.

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is

  4. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  5. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  6. A 0.13 mum CMOS serializer for data and trigger optical links in particle physics experiments

    CERN Document Server

    Cervelli, Giovanni; Moreira, Paulo

    2003-01-01

    A 3.2 Gbit/s serializer prototype has been fabricated in a 0.13 mum CMOS technology to demonstrate its applicability within future LHC data readout and trigger systems. The IC includes a clock-multiplying Phase-Locked-Loop (PLL), a 50 Omega line driver, internal self- testing features and data pattern generation. The serial output stream is 8B/10B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 years. This work describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and Bit-Error-Rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test-beds.

  7. Radiation hardening of silicon detectors

    CERN Document Server

    Lemeilleur, F

    1999-01-01

    The radiation hardness of high grade silicon detectors is summarized in terms of an increase of the diode reverse current and evolution of the full depletion voltage and charge collection efficiency. With the aim of improving their radiation tolerance, detectors have been produced from non-standard, float-zone silicon containing various atomic impurities and from epitaxial silicon materials. Some recent results concerning their radiation hardness are presented. (15 refs).

  8. Stackable Radiation Hardened FRAM Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Purpose of this effort was to offer a novel solution to the pressing need for radiation tolerant memory for the demanding satellite and space probe worldwide...

  9. Stackable Radiation Hardened FRAM Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Satellite and space systems designers of long duration lunar and planetary missions continue to find it difficult to provide the ever increasing amount of memory...

  10. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  11. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  12. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  13. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  14. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  15. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  16. Integrated tunable CMOS laser.

    Science.gov (United States)

    Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

    2013-11-18

    An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications.

  17. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  18. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  19. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  20. Monolithic integration of a plasmonic sensor with CMOS technology

    Science.gov (United States)

    Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

    2017-02-01

    Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

  1. System and Circuit Design Aspects for CMOS Wireless Handset Receivers

    DEFF Research Database (Denmark)

    Mikkelsen, Jan H.

    The presented work deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. First, an overview, from a historic perspective, on the use of CMOS in cellular applications is provided. Based on this the tremendous...... developments in CMOS technology are considered and the short-comings from an analog design perspective are evaluated. The lack of high quality passive devices, inductors in particular, is found to be one of the major obstacles in achieving a fully integrated RF design based on CMOS. Following this, an overview...... practice to employ a full separation of different distortion mechanisms. While this approach is very useful when an implementation performance surplus is available it is not an option when a low-cost silicon technology is the target. To manage this, a simple approach that allows all interfering components...

  2. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  3. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  4. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  5. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  6. Current-mode CMOS hybrid image sensor

    Science.gov (United States)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  7. A CMOS-Compatible Hybrid Plasmonic Slot Waveguide With Enhanced Field Confinement

    NARCIS (Netherlands)

    Xiao, Jing; Wei, Qi-Qin; Yang, Daoguo; Zhang, Ping; He, Ning; Zhang, G.Q.; Ren, Tian-Ling; Chen, XP

    2016-01-01

    The emerging field of nanophotonics requires plasmonic devices to be fully compatible with semiconductor fabrication techniques. However, very few feasible practical structures exist at present. Here, we propose a CMOS-compatible hybrid plasmonic slot waveguide (HPSW) with enhanced field

  8. High-speed lateral polysilicon photodiode in standard CMOS

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    2003-01-01

    A high-performance lateral polysilicon photodiode was designed in standard 0.18 /spl mu/m CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which figure was limited by the measurement equipment. The high intrinsic

  9. High-speed lateral polysilicon photodiode in standard CMOS

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    A high-performance lateral polysilicon photodiode was designed in standard 0.18 μm CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which figure was limited by the measurement equipment. The high intrinsic (physical)

  10. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  11. Two- and multi-terminal CMOS/BiCMOS Si LED’s

    Science.gov (United States)

    du Plessis, Monuko; Aharoni, Herzl; Snyman, Lukas W.

    2005-02-01

    Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented. The differences observed between avalanche and low-voltage field emission LED performance are presented. It is shown that the low-voltage devices exhibit a square-law light intensity vs. reverse current non-linearity at low-current levels, but a linear dependency at higher currents, compared to the linear behaviour of avalanche devices at all current levels. The detail spectral characteristics of the field emission devices are investigated, showing that in the non-linear region of operation, the shape of the emitted spectrum changes, with reduced short wavelength generation at lower current levels. Bipolar junction transistor (BJT) multi-terminal devices are also discussed, and the square-law behaviour of these devices is presented.

  12. On the degradation of OTA-C--based CMOS low-power filter circuits for biomedical instrumentation

    OpenAIRE

    ÖZCELEP, Yasin; KUNTMAN, Ayten; Kuntman, Hulusi Hakan

    2011-01-01

    In this work, we propose a degraded transistor-based circuit degradation simulation method to investigate the degradation effect in complementary metal-oxide semiconductor (CMOS) biomedical devices. The method is demonstrated on an operational transconductance amplifier and capacitor (OTA-C)-based CMOS filter structure. First, we simulate the degradation of the symmetrical CMOS OTA by determining the degraded transistors in the structure. The simulation results are compared with the exper...

  13. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  14. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  15. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  16. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications.

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-31

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  17. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  18. Efficient algorithms for mixed aleatory-epistemic uncertainty quantification with application to radiation-hardened electronics. Part I, algorithms and benchmark results.

    Energy Technology Data Exchange (ETDEWEB)

    Swiler, Laura Painton; Eldred, Michael Scott

    2009-09-01

    This report documents the results of an FY09 ASC V&V Methods level 2 milestone demonstrating new algorithmic capabilities for mixed aleatory-epistemic uncertainty quantification. Through the combination of stochastic expansions for computing aleatory statistics and interval optimization for computing epistemic bounds, mixed uncertainty analysis studies are shown to be more accurate and efficient than previously achievable. Part I of the report describes the algorithms and presents benchmark performance results. Part II applies these new algorithms to UQ analysis of radiation effects in electronic devices and circuits for the QASPR program.

  19. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  20. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  1. Evaluation of circuit performance of ultra-thin-body SOI CMOS

    Science.gov (United States)

    Pacha, Christian; Schmal, Artur; Schulz, Thomas; Göttsche, Ralf; Steinhögl, Werner

    2003-07-01

    Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm [1]. In this paper we analyze the impact of this emerging CMOS device concept on the performance of a representative selection of various digital CMOS circuits under different load conditions for typical ASIC/SOC applications. For compact modeling a physics-based fully depleted SOI model is used [2] and combined with a technology scenario assuming an undoped Si-body, elevated source-drain regions, and midgap gate workfunction.

  2. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    Science.gov (United States)

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  3. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    Science.gov (United States)

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  4. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    Directory of Open Access Journals (Sweden)

    Mohd Haris Md Khir

    2011-08-01

    Full Text Available This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  5. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  6. Hardening of commercial CMOS PROMs with polysilicon fusible links

    Science.gov (United States)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  7. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  8. Development of CMOS integrated circuits

    Science.gov (United States)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  9. Designing analog circuits in CMOS

    NARCIS (Netherlands)

    Annema, Anne J.; Nauta, Bram; van Langevelde, Ronald; Tuinhout, Hans

    2004-01-01

    The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression. This article

  10. Radiation-Hardened HDTV Sensors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — High-performance HDTV cameras are commercially widespread, but are not presently available in radiation-hard versions. The objective of the proposed SBIR effort is...

  11. Thermopile Detector Radiation Hardened Readout Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The NASA Jupiter Europa Orbiter (JEO) conceptual payload contains a thermal instrument with six different spectral bands ranging from 85m to 100lm. The thermal...

  12. Radiation hardening revisited: Role of intracascade clustering

    DEFF Research Database (Denmark)

    Singh, B.N.; Foreman, A.J.E.; Trinkaus, H.

    1997-01-01

    be explained in terms of conventional dispersed-barrier hardening because (a) the grown-in dislocations are not free, and (b) irradiation-induced defect clusters are not rigid indestructible Orowan obstacles. A new model called 'cascade-induced source hardening' is presented where glissile loops produced...... directly in cascades are envisaged to decorate the grown-in dislocations so that they cannot act as dislocation sources. The upper yield stress is related to the breakaway stress which is necessary to pull the dislocation away from the clusters/loops decorating it. The magnitude of the breakaway stress has...

  13. Thermopile Detector Radiation Hardened Readout Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The Europa Jupiter System Mission (EJSM) will provide a better understanding as to how gas giant planets and their satellites form and evolve. The Jupiter Europa...

  14. Radiation hardening design of nuclear powered spacecraft

    Science.gov (United States)

    Schmidt, R. E.

    1987-01-01

    The design and operation of space systems utilizing nuclear fueled power systems must consider the radiation environment from the earliest stages of their design. A range of nuclear systems are being considered for present and future satellite systems capable of supplying tens of kilowatts to multimegawatt and generating a corresponding range of radiation environments. The effects of these radiations on electronics and materials can be minimized by implementing early design considerations which maximize the design efficiency and minimize the impact on system mass. Space systems design considerations for the radiation environment must include all sources in addition to the self induced gamma ray and neutron radiation. These include the orbital dependent environment from the high energy electron and protons encountered in natural space. The system trades which the designer must consider in the development of space platforms which utilize nuclear reactor power supplies are discussed.

  15. Chemistry of MOS-LSI radiation hardening

    Science.gov (United States)

    Grunthaner, P.

    1985-01-01

    The objective of this task was to obtain chemical information on MOS test samples. Toward this end, high resolution X-ray photoemission spectroscopy (XPS) has been the primary techniques used to characterize the chemistry and structure of the SiO2/Si interface for a variety of MOS structures with differing degrees of susceptibility to damage by ionizing radiation. The major accomplishments of this program are: (1) the identification of a structurally distinct region of SiO2 in the near-interfacial region of thermal SiO2 on Si; (2) the identification in the near-interfacial region of SiO2 structural differences between radiation hard and soft gate oxides; (3) the direct observation of radiation-induced damage sites in thermal SiO2 with XPS using in situ electron stress; (4) the correlation of suboxide state distributions at the SiO2/Si interface with processing parameters and radiation susceptibility; (5) the development of a chemical mechanism for radiation-induced interface state generation in SiO2/Si structures; and (6) the development benign chemical profiling techniques which permit the investigation of oxide/semiconductor structures using surface sensitive electron spectroscopic techniques.

  16. Radiation Hardened Bolometer Linear Array Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA has developed space-based thermal instrument spectrometers based on thermopile detectors linear arrays that are intrinsically radiation hard. Micro-bolometers...

  17. Fabrication of integrated metallic MEMS devices

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

    2002-01-01

    A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

  18. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  19. CMOS in-pixel optical pulse frequency modulator

    Science.gov (United States)

    Nel, Nicolaas E.; du Plessis, M.; Joubert, T.-H.

    2016-02-01

    This paper covers the design of a complementary metal oxide semiconductor (CMOS) pixel readout circuit with a built-in frequency conversion feature. The pixel contains a CMOS photo sensor along with all signal-to-frequency conversion circuitry. An 8×8 array of these pixels is also designed. Current imaging arrays often use analog-to-digital conversion (ADC) and digital signal processing (DSP) techniques that are off-chip1. The frequency modulation technique investigated in this paper is preferred over other ADC techniques due to its smaller size, and the possibility of a higher dynamic range. Careful considerations are made regarding the size of the components of the pixel, as various characteristics of CMOS devices are limited by decreasing the scale of the components2. The methodology used was the CMOS design cycle for integrated circuit design. All components of the pixel were designed from first principles to meet necessary requirements of a small pixel size (30×30 μm2) and an output resolution greater than that of an 8-bit ADC. For the photodetector, an n+-p+/p-substrate diode was designed with a parasitic capacitance of 3 fF. The analog front-end stage was designed around a Schmitt trigger circuit. The photo current is integrated on an integration capacitor of 200 fF, which is reset when the Schmitt trigger output voltage exceeds a preset threshold. The circuit schematic and layout were designed using Cadence Virtuoso and the process used was the AMS CMOS 350 nm process using a power supply of 5V. The simulation results were confirmed to comply with specifications, and the layout passed all verification checks. The dynamic range achieved is 58.828 dB per pixel, with the output frequencies ranging from 12.341kHz to 10.783 MHz. It is also confirmed that the output frequency has a linear relationship to the photocurrent generated by the photodiode.

  20. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  1. Nanoelectronic device applications handbook

    CERN Document Server

    Morris, James E

    2013-01-01

    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that range from nano-scaled complementary metal-oxide-semiconductor (CMOS) devices through recent developments in nano capacitors and AlGaAs/GaAs devices. The contributors are world-renowned experts from academia and industry from around the globe. The handbook explores current research into potentially disruptive technologies for a post-CMOS world.These include: Nanoscale advance

  2. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  3. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  4. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    Science.gov (United States)

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-08-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400 times 400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 mum times 30 mum. The devices exhibited sensitivity of 6.2 muC/Rcm2 with corresponding dark current of 2.7 nA/cm2, and a 80 mum FWHM planar image response to a 50 mum slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 mum spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 mum), fast readout speeds (8 fps for a 3200 times 3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes.

  5. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  6. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors.

    Science.gov (United States)

    Qu, Chen; Bi, Du-Yan; Sui, Ping; Chao, Ai-Nong; Wang, Yun-Fei

    2017-09-22

    The CMOS (Complementary Metal-Oxide-Semiconductor) is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze), causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF) framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  7. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  8. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  9. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  10. Nanophotonic integration in state-of-the-art CMOS foundries.

    Science.gov (United States)

    Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popović, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanović, Vladimir; Ram, Rajeev J

    2011-01-31

    We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming.

  11. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  12. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  13. A Surface Micromachined CMOS MEMS Humidity Sensor

    OpenAIRE

    Jian-Qiu Huang; Fei Li; Min Zhao; Kai Wang

    2015-01-01

    This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. A...

  14. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  15. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  16. Fabrication and Measurement of a Suspended Nanochannel Microbridge Resonator Monolithically Integrated with CMOS Readout Circuitry

    Directory of Open Access Journals (Sweden)

    Gabriel Vidal-Álvarez

    2016-03-01

    Full Text Available We present the fabrication and characterization of a suspended microbridge resonator with an embedded nanochannel. The suspended microbridge resonator is electrostatically actuated, capacitively sensed, and monolithically integrated with complementary metal-oxide-semiconductor (CMOS readout circuitry. The device is fabricated using the back end of line (BEOL layers of the AMS 0.35 μm commercial CMOS technology, interconnecting two metal layers with a contact layer. The fabricated device has a 6 fL capacity and has one of the smallest embedded channels so far. It is able to attain a mass sensitivity of 25 ag/Hz using a fully integrable electrical transduction.

  17. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  18. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  19. Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments

    Science.gov (United States)

    Terzo, S.; Cavallaro, E.; Casanova, R.; Di Bello, F.; Förster, F.; Grinstein, S.; Períc, I.; Puigdengoles, C.; Ristić, B.; Barrero Pinto, M. Vicente; Vilella, E.

    2017-06-01

    An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.

  20. Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

    Directory of Open Access Journals (Sweden)

    Edwin Becerra‐Álvarez

    2009-04-01

    Full Text Available This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA for the next generation of wireless hand‐held devicesby using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing thefulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such thatthe mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit underanalysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topologyincluding inductive‐source degeneration, MOS‐varactor based tuning networks, and programmable bias currents. This proposal,with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications;the LNA is designed to cope with the requirements of GSM (PCS1900, WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g. In orderto evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA featuresNF16dB, S11‐3.3 dBm over the 1.85‐2.48 GHz band. For all the standards understudy the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of thereconfigurable LNA occupies an area of 1.8mm2.

  1. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  2. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    Science.gov (United States)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  3. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  4. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  5. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    Science.gov (United States)

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  6. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  7. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic.

    Science.gov (United States)

    Lee, Myeongwon; Jeon, Youngin; Moon, Taeho; Kim, Sangsig

    2011-04-26

    A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ∼9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality.

  8. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  9. Single donor electronics and quantum functionalities with advanced CMOS technology.

    Science.gov (United States)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-16

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  10. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  11. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  12. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  13. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...... the technology facilitates integration of discrete components directly on the surface of the chip, the need for an additional substrate is eliminated. For a single chip solution employing the presented via technology and on-chip integration of components, the total height of the package constituting a complete...

  14. Stochastic process variation in deep-submicron CMOS circuits and algorithms

    CERN Document Server

    Zjajo, Amir

    2014-01-01

    One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

  15. Opportunities of CMOS-MEMS integration through LSI foundry and open facility

    Science.gov (United States)

    Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

    2017-06-01

    Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

  16. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  17. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Directory of Open Access Journals (Sweden)

    John-Ojur Dennis

    2015-07-01

    Full Text Available This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2 nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that

  18. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  19. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  20. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  1. The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

    Science.gov (United States)

    Chen, Kuan-Neng; Krusin-Elbaum, Lia

    2010-04-02

    We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

  2. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  3. CMOS Application of Schottky Source/Drain SOI MOSFET with Shallow Doped Extension

    Science.gov (United States)

    Matsumoto, Sumie; Nishisaka, Mika; Asano, Tanemasa

    2004-04-01

    The silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) whose source/drain is composed of Schottky contacts and a shallow-doped extension is investigated. It is demonstrated that the incorporation of the shallow-doped extension into the Schottky source/drain can increase the current drive and reduce the leakage current under reverse bias for both n-channel and p-channel devices. The shallow doping is performed by implanting Sb for n-channel devices, and BF2 or Ga for p-channel devices. The effect of Schottky contacts on the floating body effect (FBE) is investigated by analyzing the lateral bipolar characteristics of these devices. By employing the shallow-doped extension, a complementary MOS (CMOS) of the Schottky source/drain can be fabricated using single metal (cobalt, in this work) silicide. The stability of CMOS operation with the proposed devices under a high supply voltage is demonstrated by comparing it with a conventional pn-junction SOI MOSFET. It is also demonstrated from the characteristics of the CMOS-inverter ring oscillator that the proposed device operates at speeds as high as or even higher than that of the conventional SOI MOSFET.

  4. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  5. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  6. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  7. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  8. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  9. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  10. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  11. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  12. Experiments with synchronized sCMOS cameras

    Science.gov (United States)

    Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

    2016-07-01

    Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

  13. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Science.gov (United States)

    Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

    2017-01-01

    A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µVrms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter. PMID:28394289

  14. A Review on Energy Efficient CMOS Digital Logic

    Directory of Open Access Journals (Sweden)

    B. L. Dokic

    2013-12-01

    Full Text Available Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt and power supply voltage (Vdd on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL, complementary pass logic (CPL, push-pull pass logic (PPL and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

  15. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  16. CMOS tunable-wavelength multi-color photogate sensor.

    Science.gov (United States)

    Ho, Derek; Noor, M Omair; Krull, Ulrich J; Gulak, Glenn; Genov, Roman

    2013-12-01

    A CMOS tunable-wavelength multi-color photogate (CPG) sensor is presented. Sensing of a small set of well-separated wavelengths (e.g., > 50 nm apart) is achieved by tuning the spectral response of the device with a bias voltage. The CPG employs the polysilicon gate as an optical filter, which eliminates the need for an external color filter. A prototype has been fabricated in a standard 0.35 μm digital CMOS technology and demonstrates intensity measurements of blue (450 nm), green (520 nm), and red (620 nm) illumination with peak signal-to-noise ratios (SNRs) of 34.7 dB , 29.2 dB, and 34.8 dB, respectively. The prototype is applied to fluorescence detection of green-emitting quantum dots (gQDs) and red-emitting quantum dots (rQDs). It spectrally differentiates among multiple emission bands, effectively implementing on-chip emission filtering. The prototype demonstrates single-color measurements of gQD and rQD concentrations to a detection limit of 24 nM, and multi-color measurements of solutions containing both colors of QDs to a detection limit of 90 nM and 120 nM of gQD and rQD, respectively.

  17. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Directory of Open Access Journals (Sweden)

    Elnaz Ghodsevali

    2017-04-01

    Full Text Available A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  18. Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

    Science.gov (United States)

    Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

    2017-09-09

    We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

  19. Modeling Single-Event Transient Propagation in a SiGe BiCMOS Direct-Conversion Receiver

    Science.gov (United States)

    Ildefonso, Adrian; Song, Ickhyun; Tzintzarov, George N.; Fleetwood, Zachary E.; Lourenco, Nelson E.; Wachter, Mason T.; Cressler, John D.

    2017-08-01

    The propagation of single-event transient (SET) signals in a silicon-germanium direct-conversion receiver carrying modulated data is explored. A theoretical analysis of transient propagation, verified by simulation, is presented. A new methodology to characterize and quantify the impact of SETs in communication systems carrying modulated data is proposed. The proposed methodology uses a pulsed radiation source to induce distortions in the signal constellation. The error vector magnitude due to SETs can then be calculated to quantify errors. Two different modulation schemes were simulated: QPSK and 16-QAM. The distortions in the constellation diagram agree with the presented circuit theory. Furthermore, the proposed methodology was applied to evaluate the improvements in the SET response due to a known radiation-hardening-by-design (RHBD) technique, where the common-base device of the low-noise amplifier was operated in inverse mode. The proposed methodology can be a valid technique to determine the most sensitive parts of a system carrying modulated data.

  20. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Oleg Nizhnik; Kazusuke Maenaka; Kohei Higuchi

    2011-01-01

    A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  1. Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid.

    Science.gov (United States)

    Walker, James Alfred; Sinnott, Richard; Stewart, Gordon; Hilder, James A; Tyrrell, Andy M

    2010-08-28

    The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.

  2. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  3. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  4. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...

  5. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  6. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  7. Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

    Directory of Open Access Journals (Sweden)

    Sylvain Barraud

    2016-03-01

    Full Text Available The definition of the ampere will change in the next few years. This electrical base unit of the S.I. will be redefined by fixing the value of the charge quantum, i.e., the electron charge e. As a result electron pumps will become the natural device for the mise en pratique of this new ampere. In the last years semiconductor electron pumps have emerged as the most advanced systems, both in terms of speed and precision. Another figure of merit for a metrological device would be its ability to be predictible and shared. For that reason a mature fabrication process would certainly be an advantage. In this article we present electron pumps made within a CMOS (Complementary Metal Oxide Semiconductor research facility on 300 mm silicon-on-insulator wafers, using advanced microelectronics tools and processes. We give an overview of the whole integration scheme and emphasize the fabrication steps which differ from the normal CMOS route.

  8. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Barnaby, Hugh J. [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States)]. E-mail: hbarnaby@asu.edu; Mclain, Michael [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States); Esqueda, Ivan Sanchez [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States)

    2007-08-15

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits.

  9. Design and fabrication of a CMOS-compatible MHP gas sensor

    Directory of Open Access Journals (Sweden)

    Ying Li

    2014-03-01

    Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  10. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  11. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  12. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Venkatesh, Srinivasan; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel

  13. Smart temperature sensors in standard CMOS

    NARCIS (Netherlands)

    Makinwa, K.A.A.

    2010-01-01

    A smart temperature sensor is an integrated system consisting of a temperature sensor, its bias circuitry and an analog-to-digital converter (ADC). When manufactured in CMOS technology, such sensors have found widespread use due to their low cost, small size and ease of use. In this paper the basic

  14. A fail-safe CMOS logic gate

    Science.gov (United States)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  15. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important

  16. On Dynamic Range Limitations of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1999-01-01

    This paper is concerned with the dynamic range of continuous time CMOS current mode circuits. As a representative current mode device a class AB current conveyor is examined. First, the voltage input range of the high impedance Y input is investigated. Next, the current input range of the low...... impedance X input is investigated. It is compared to the thermal noise in the X to Z signal path in order to evaluate the dynamic range, and the dependencies of the dynamic range on the supply voltage and the transistor lay-out is derived, both for the situation where the conveyor is used over a narrow...... frequency band and for the situation where the conveyor is used over the full bandwidth achievable. Finally, the optimisation of the current input range is related to the distortion characteristics and it is pointed out that to a first order approximation the distortion is independent of the current range....

  17. Low-Power SOI CMOS Transceiver

    Science.gov (United States)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  18. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

    Science.gov (United States)

    Li, Shu; Zhang, Tong

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  19. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.

    2016-05-18

    We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

  20. Voltage-tolerant circuit design for fully CMOS-compatible differential multiple-time programmable nonvolatile memories

    Science.gov (United States)

    Wu, Chia-You; Lin, Hongchin; Chiu, Hou-Jen

    2017-04-01

    In this paper, a fully CMOS-compatible differential multiple-time programmable (DFMTP) nonvolatile memory (NVM) circuit, fabricated by the standard TSMC 0.18 µm CMOS process without violating the design and electrical rules, is proposed. Novel voltage-tolerant circuits were designed using the standard 3.3 and 1.8 V devices for the bit line (BL) and control gate (CG) drivers for -3 and 6 V program/erase operations, as well as the negative voltage isolation circuits for sense amplifiers. The DFMTP array with these voltage-tolerant control circuits was used and measured to confirm the correct program/erase/read operations.

  1. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  2. Tin (Sn) - An Unlikely Ally to Extend Moore's Law for Silicon CMOS?

    KAUST Repository

    Hussain, Aftab M.

    2012-12-01

    There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

  3. Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories

    Energy Technology Data Exchange (ETDEWEB)

    Fujiwara, K.; Miyakawa, H.; Yoshikawa, N.; Feng, Y.; Whiteley, S.R.; Van Duzer, T

    2003-10-15

    We have been developing Josephson-CMOS hybrid memories where high-density CMOS devices are used as storage cells. One of the key components in the system is the interface circuit, which amplifies the signal from the SFQ circuits into voltage level processible in the CMOS circuits at high-speed. In this paper, we have implemented the ultra-fast interface circuit, which is composed of a Josephson driver and a Josephson-CMOS hybrid amplifier. The propagation delay of the ultra-fast interface circuit is estimated to be about 60 ps assuming a 2.5 kA/cm{sup 2} Nb process and a 0.6 {mu}m CMOS process. A low speed test results of the interface circuit shows that it amplifies the input voltage of 80 {mu}V to 0.9 V. We have also investigated their propagation delay and output voltage swing assuming the spread of the critical current in the Josephson stack.

  4. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    Science.gov (United States)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  5. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  6. Spectrum acquisition of detonation based on CMOS

    Science.gov (United States)

    Li, Yan; Bai, Yonglin; Wang, Bo; Liu, Baiyu; Xue, Yingdong; Zhang, Wei; Gou, Yongsheng; Bai, Xiaohong; Qin, Junjun; Xian, Ouyang

    2010-10-01

    The detection of high-speed dynamic spectrum is the main method to acquire transient information. In order to obtain the large amount spectral data in real-time during the process of detonation, a CMOS-based system with high-speed spectrum data acquisition is designed. The hardware platform of the system is based on FPGA, and the unique characteristic of CMOS image sensors in the rolling shutter model is used simultaneously. Using FPGA as the master control chip of the system, not only provides the time sequence for CIS, but also controls the storage and transmission of the spectral data. In the experiment of spectral data acquisition, the acquired information is transmitted to the host computer through the CameraLink bus. The dynamic spectral curve is obtained after the subsequent processing. The experimental results demonstrate that this system is feasible in the acquisition and storage of high-speed dynamic spectrum information during the process of detonation.

  7. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  8. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications

    KAUST Repository

    Hussain, Aftab M.

    2015-11-26

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today\\'s digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. An investigation of medical radiation detection using CMOS image sensors in smartphones

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Han Gyu [Department of Senior Healthcare, Graduate School of Eulji University, Daejeon 301-746 (Korea, Republic of); Song, Jae-Jun [Department of Otorhinolaryngology-Head & Neck Surgery, Korea University, Guro Hospital,148, Gurodong-ro, Guro-gu, Seoul 152-703 (Korea, Republic of); Lee, Kwonhee [Graduate Program in Bio-medical Science, Korea University, 2511 Sejong-ro, Sejong City 339-770 (Korea, Republic of); Nam, Ki Chang [Department of Medical Engineering, College of Medicine, Dongguk University, 32 Dongguk-ro, Goyang-si, Gyeonggi-do 410-820 (Korea, Republic of); Hong, Seong Jong; Kim, Ho Chul [Department of Radiological Science, Eulji University, 553 Yangji-dong, Sujeong-gu, Seongnam-si, Gyeonggi-do 431-713 (Korea, Republic of)

    2016-07-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  10. Supply Voltage Glitches Effects on CMOS Circuits

    OpenAIRE

    Djellid-Ouar, Anissa; Cathébras, Guy; Bancel, Frédéric

    2006-01-01

    International audience; Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers. . . ) ...

  11. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  12. 10 Gb/s CMOS photonics technology

    Science.gov (United States)

    Gunn, Cary

    2006-02-01

    Freescale's production 0.13μm SOI process is used to fabricate all required electrical and optical components for 10Gb interconnect up to 2000m using only 1.7W. The optical transceiver cores are monolithically fabricated with CMOS circuitry required for bias and control as well as the electrical PHY interface. Optical multiplexing of 4 to 10 channels allows scaling to 40/100Gb.

  13. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  14. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  15. High-gain monolithic 3D CMOS inverter using layered semiconductors

    Science.gov (United States)

    Sachid, Angada B.; Desai, Sujay B.; Javey, Ali; Hu, Chenming

    2017-11-01

    We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.

  16. Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

    CERN Document Server

    Huffman, B T; Arndt, K; Bates, R; Benoit, M; Di Bello, F; Blue, A; Bortoletto, D; Buckland, M; Buttar, C; Caragiulo, P; Das, D; Dopke, J; Dragone, A; Ehrler, F; Fadeyev, V; Galloway, Z; Grabas, H; Gregor, I M; Grenier, P; Grillo, A; Hoeferkamp, M; Hommels, L B A; John, J; Kanisauskas, K; Kenney, C; Kramberger, J; Liang, Z; Mandic, I; Maneuski, D; Martinez-McKinney, F; McMahon, S; Meng, L; Mikuž, M; Muenstermann, D; Nickerson, R; Peric, I; Phillips, P; Plackett, R; Rubbo, F; Segal, J; Seidel, S; Seiden, A; Shipsey, I; Song, W; Stanitzki, M; Su, D; Tamma, C; Turchetta, R; Vigani, L; olk, J; Wang, R; Warren, M; Wilson, F; Worm, S; Xiu, Q; Zhang, J; Zhu, H

    2016-01-01

    The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with theAMSH35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

  17. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  18. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    A 205GHz Amplifier in 90nm CMOS Technology Shahab Ardalan, Senior Member, IEEE Electrical Department, Charles W. Davidson College of Engineering...greater CMOS technologies . Keywords: Amplifier, neutralization, parasitic, Psat, P1dB.   Introduction Millimeter-wave and sub-mm-wave (THz band...amplifier has been implemented and fabricated in 90nm CMOS technology . The proposed amplifier attained a gain of 10.5 dB whilst consuming a dc power

  19. A standard CMOS humidity sensor without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 μW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  20. Interferometric comparison of the performance of a CMOS and sCMOS detector

    Science.gov (United States)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  1. Fundamental performance differences of CMOS and CCD imagers: part V

    Science.gov (United States)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  2. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    Science.gov (United States)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  3. Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

    Science.gov (United States)

    Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

    2017-11-01

    The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

  4. High resolution, high bandwidth global shutter CMOS area scan sensors

    Science.gov (United States)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  5. Integration of complex optical functionality in a production CMOS process

    Science.gov (United States)

    Gunn, Lawrence C., III

    Optical functionality has been developed within the confines of an existing CMOS process. As of this writing, 10Gigabit modulators, electrically tunable optical filters, waveguides, and grating coupler technology have been successfully implemented alongside the existing transistors in the Freescale Hip7SOI process. This technology will be used to manufacture high bandwidth optical interconnections directly on silicon chips, allowing a new type of network and computing infrastructure to be developed. This work is covered in two distinct phases. First, the exploratory work done to gain experience with high index contrast silicon waveguides primarily served to uncover challenges related with simulation of these devices, and with the practical limitations of efficiently coupling the resulting waveguide devices with the outside world. The second phase began as the grating coupler emerged to address the coupling challenge. It became feasible to conceive of a commercially viable technology based on silicon photonics. The coupler has been evolved to a high level, currently achieving coupling loss of less than 1dB. Once the light is on chip, filtering and modulation technology are implemented. The reverse-biased plasma dispersion modulator has a 3dB roll-off of 10GHz, and an insertion loss less than 5dB. Optical filters based on ring resonators, arrayed waveguide gratings, and interleavers have all been implemented, often with world record performance, and many of the devices have been made electronically tunable to compensate for manufacturing variations and environmental excursions. Finally, circuitry has been designed and constructed on the same die with the optical functionality, fully demonstrating the ability to achieve monolithic integration of these devices.

  6. LGSD/NGSD: high speed visible CMOS imagers for E-ELT adaptive optics

    Science.gov (United States)

    Downing, Mark; Kolb, Johann; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Fryer, Martin; Gach, Jean-Luc; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Pike, Andrew; Reyes, Javier; Stadler, Eric; Swift, Nick

    2016-08-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the European Extremely Large Telescope (E-ELT) has been identified as the Large Visible Laser/Natural Guide Star AO Wavefront Sensing (WFS) detector. The combination of large format, 1600x1600 pixels to finely sample the wavefront and the spot elongation of laser guide stars (LGS), fast frame rate of 700 frames per second (fps), low read noise ( 90%) makes the development of this device extremely challenging. Results of design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most suitable technology. Two generations of the CMOS Imager are planned: a) a smaller `pioneering' device of > 800x800 pixels capable of meeting first light needs of the E-ELT. The NGSD, the topic of this paper, is the first iteration of this device; b) the larger full sized device called LGSD. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). Results of comprehensive tests performed both at e2v and ESO are presented that validate the choice of CMOS Imager as the correct technology for the E-ELT Large Visible WFS Detector. These results along with plans for a second iteration to improve two issues of hot pixels and cross-talk are presented.

  7. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  8. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  9. CMOS current controlled fully balanced current conveyor

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Zhang Qiujing; Liu Haiguang, E-mail: wch1227164@sina.co [School of Computer and Communication, Hunan University, Changsha 410082 (China)

    2009-07-15

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-{mu}m CMOS technology; with {+-}1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  10. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  11. Method and circuitry for CMOS transconductor linearization

    OpenAIRE

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a sec...

  12. Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

    2017-08-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

  13. Gamma-ray irradiation tests of CMOS sensors used in imaging techniques

    Directory of Open Access Journals (Sweden)

    Cappello Salvatore G.

    2014-01-01

    Full Text Available Technologically-enhanced electronic image sensors are used in various fields as diagnostic techniques in medicine or space applications. In the latter case the devices can be exposed to intense radiation fluxes over time which may impair the functioning of the same equipment. In this paper we report the results of gamma-ray irradiation tests on CMOS image sensors simulating the space radiation over a long time period. Gamma-ray irradiation tests were carried out by means of IGS-3 gamma irradiation facility of Palermo University, based on 60Co sources with different activities. To reduce the dose rate and realize a narrow gamma-ray beam, a lead-collimation system was purposely built. It permits to have dose rate values less than 10 mGy/s and to irradiate CMOS Image Sensors during operation. The total ionizing dose to CMOS image sensors was monitored in-situ, during irradiation, up to 1000 Gy and images were acquired every 25 Gy. At the end of the tests, the sensors continued to operate despite a background noise and some pixels were completely saturated. These effects, however, involve isolated pixels and therefore, should not affect the image quality.

  14. AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    N. B. ROMLI

    2015-03-01

    Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

  15. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    Directory of Open Access Journals (Sweden)

    Liping Wei

    2014-09-01

    Full Text Available Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

  16. The intersection of CMOS microsystems and upconversion nanoparticles for luminescence bioimaging and bioassays.

    Science.gov (United States)

    Wei, Liping; Doughan, Samer; Han, Yi; DaCosta, Matthew V; Krull, Ulrich J; Ho, Derek

    2014-09-10

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

  17. Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

    Directory of Open Access Journals (Sweden)

    Nobuyuki Sugii

    2014-04-01

    Full Text Available Ultralow-voltage (ULV CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB CMOS is a strong candidate for the ultralow-power (ULP electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT era.

  18. Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

    Directory of Open Access Journals (Sweden)

    Ignacio Bravo

    2011-02-01

    Full Text Available This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS sensor and a Field Programmable Gate Array (FPGA. The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely.

  19. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  20. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  1. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  2. Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

    2017-07-15

    A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  3. Recent X-ray hybrid CMOS detector developments and measurements

    Science.gov (United States)

    Hull, Samuel V.; Falcone, Abraham D.; Burrows, David N.; Wages, Mitchell; Chattopadhyay, Tanmoy; McQuaide, Maria; Bray, Evan; Kern, Matthew

    2017-08-01

    The Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors (TIS), have progressed their efforts to improve soft X-ray Hybrid CMOS detector (HCD) technology on multiple fronts. Having newly acquired a Teledyne cryogenic SIDECARTM ASIC for use with HxRG devices, measurements were performed with an H2RG HCD and the cooled SIDECARTM. We report new energy resolution and read noise measurements, which show a significant improvement over room temperature SIDECARTM operation. Further, in order to meet the demands of future high-throughput and high spatial resolution X-ray observatories, detectors with fast readout and small pixel sizes are being developed. We report on characteristics of new X-ray HCDs with 12.5 micron pitch that include in-pixel CDS circuitry and crosstalk-eliminating CTIA amplifiers. In addition, PSU and TIS are developing a new large-scale array Speedster-EXD device. The original 64 × 64 pixel Speedster-EXD prototype used comparators in each pixel to enable event driven readout with order of magnitude higher effective readout rates, which will now be implemented in a 550 × 550 pixel device. Finally, the detector lab is involved in a sounding rocket mission that is slated to fly in 2018 with an off-plane reflection grating array and an H2RG X-ray HCD. We report on the planned detector configuration for this mission, which will increase the NASA technology readiness level of X-ray HCDs to TRL 9.

  4. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  5. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.......5 mum CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/rootHz. The amplifier power consumption is 275 muW, drawn...

  6. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  7. Manufacturing Methods for Radiation-Hardened Multiple IC Chip Package

    Science.gov (United States)

    1975-10-01

    anodization. Although the resistor material to be used on this program is MoSi^, the effects of anodization on CrSi resistors was also studied because CrSi ...is a thin-film resistor material which is also used in low-power radiacion-hardened integrated circuits. However, since the results for CrSi were

  8. Radiation-Hardened Electronics for Advanced Communications Systems

    Science.gov (United States)

    Whitaker, Sterling

    2015-01-01

    Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

  9. 1 Gb Radiation Hardened Nonvolatile Memory Development Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of this effort is to identify, characterize and develop advanced semiconductor materials and fabrication process techniques, and design and produce a...

  10. The Development of a Radiation Hardened Robot for Nuclear Facilities

    Energy Technology Data Exchange (ETDEWEB)

    Jung, Seung Ho; Kim, Chang Hoi; Seo, Yong Chil (and others)

    2007-04-15

    We has been developed two remotely controlled robotic systems. One is a underwater vehicle for inspection of the internal structures of PWRs and retrieving foreign stubs in the reactor pressure vessels and reactor coolant pipes. The other robotic system consists of a articulated-type mobile robot capable of recovering the failure of the fuel exchange machine and a mini modular mobile robot for inspection of feeder pipes with ultrasonic array sensors in PHWRs. The underwater robot has been designed by considering radiation effect, underwater condition, and accessibility to the working area. The size of underwater robot is designed to enter the cold legs. A extendable manipulator is mounted on the mobile robot, which can restore nuclear fuel exchange machine. The mini modular mobile robot is composed of dual inch worm mechanisms, which are constructed by two gripper bodies that can fix the robot body on to the pipe and move along the longitudinal and to rotate in a circumferential direction to access all of the outer surfaces of the pipe.

  11. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    Science.gov (United States)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz

  12. CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

    CERN Document Server

    Hehn, Thorsten

    2014-01-01

    This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

  13. A fully integrated preamplifier for cardiac sensing in a HV-CMOS technology.

    Science.gov (United States)

    Lasa, J; Arnaud, A; Miguez, M

    2010-01-01

    A novel fully integrated preamplifier stage for cardiac activity sensing is presented. The proposed design takes advantage of the High Voltage CMOS (HV) technology properties to comply with the safety requirements of implantable devices without the addition of external decoupling capacitors. The power consumption is minimum; while the input referred noise is kept well below the minimum signal to be sensed. This first stage is a high pass filter with a cut off frequency at 75Hz, and 25db gain. Simulation results are presented, the circuit is being fabricated in a 0.6 microm technology.

  14. Nano-scale CMOS analog circuits models and CAD techniques for high-level design

    CERN Document Server

    Pandit, Soumya; Patra, Amit

    2014-01-01

    Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database.Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physic

  15. 30-Gb/s 90-nm CMOS-driven equalized multimode optical link.

    Science.gov (United States)

    Hamel-Bissell, Brendan H; Proesel, Jonathan E; Lee, Benjamin G; Kuchta, Daniel M; Rylyakov, Alexander V; Schow, Clint L

    2013-05-06

    We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s.

  16. Uncooled CMOS terahertz imager using a metamaterial absorber and pn diode.

    Science.gov (United States)

    Escorcia, Ivonne; Grant, James; Gough, John; Cumming, David R S

    2016-07-15

    We demonstrate a low-cost uncooled terahertz (THz) imager fabricated in a standard 180 nm CMOS process. The imager is composed of a broadband THz metamaterial absorber coupled with a diode microbolometer sensor where the pn junction is used as a temperature sensitive device. The metamaterial absorber array is integrated in the top metallic layers of a six metal layer process allowing for complete monolithic integration of the metamaterial absorber and sensor. We demonstrate the capability of the detector for stand-off imaging applications by using it to form transmission and reflection images of a metallic object hidden in a manila envelope.

  17. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

    Science.gov (United States)

    Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

    2009-01-01

    We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

  18. Monolithic optical link in silicon-on-insulator CMOS technology.

    Science.gov (United States)

    Dutta, Satadal; Agarwal, Vishal; Hueting, Raymond J E; Schmitz, Jurriaan; Annema, Anne-Johan

    2017-03-06

    This work presents a monolithic laterally-coupled wide-spectrum (350 nm link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n+p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.

  19. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  20. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  1. Optimizing a manufacturing submicron CMOS process for low-voltage applications

    Science.gov (United States)

    Ma, Jun; Cheng, Sunny; Pryor, Bob; Klein, Kevin

    1996-09-01

    A low threshold voltage (Vt) is desired to improve a CMOS circuit performance when operating at reduced supply voltages to save power. In this paper, a practical approach to reduce Vt for a conventional, manufacturing submicron CMOS process is presented. This `evolutionary' approach to reduce Vt is taken so as the ensure manufacturability and to reduce process cost. This is found to be useful especially before a deep-submicron or a sophisticated process targeted for low voltage application becomes available and manufacturable. Vt reduction is achieved by the integration of a thinner, in the case presented here a 105 angstroms, gate oxide into a 0.65 micrometers process. The process is then optimized to provide the device with highest current-drive while obtaining lowest Vt with acceptable subthreshold leakage with conventional front-end and back-end process. It is shown that, with the minimal changes to the 0.65 micrometers conventional manufacturing process, the Vt's for nominal n- and p-channel devices can be reduced by 20% - 30%, with more than 1.5X improvement in current drive at 3.3 V compared to devices with 150 angstroms gate oxide. The enhancement of circuit performance is demonstrated with measurements of benchmark circuits including CPU, ROM, and FSRAM, where successful operation has been obtained near IV and operating frequencies are nearly doubled at supply voltage near 1.6 V compared to conventional 0.65 micrometers process.

  2. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  3. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  4. Advanced source/drain and contact design for nanoscale CMOS

    Science.gov (United States)

    Vega, Reinaldo

    The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide. The small source/drain extension (SDE) regions extending from the metallic contact regions are an important design parameter in DSS MOSFETs, since their size and concentration affect contact resistance, series resistance, band-to-band tunneling (BTBT), SDE tunneling, and direct source-to-drain tunneling (DSDT) leakage. This work investigates key design issues surrounding DSS MOSFETs from both a modeling and experimental perspective, including the effect of SDE design on ambipolar leakage, the effect of random dopant fluctuation (RDF) on specific contact resistivity, 3D FinFET source/drain and contact design optimization, and experimental methods to achieve tuning of the SDE region. It is found that DSS MOSFETs are appropriate for thin body high performance (HP) and low operating power (LOP) MOSFETs, but not low standby power (LSTP) MOSFETs, due to a trade-off between ambipolar leakage and contact resistance. It is also found that DSDT will not limit DSS MOSFET scalability, nor will RDF limit contact resistance scaling, at the end of the CMOS roadmap. Furthermore, it is found that SDE tunability in DSS MOSFETs is achievable in the real-world, for an implant-to-silicide (ITS) process, by employing fluorine implant prior to metal deposition and silicidation. This is found to open up the DSS process design space for the trade-off between SDE junction depth and contact resistance. Si1-xGex process technology is also explored, and Ge melt processing is found to be a promising low-cost alternative to epitaxial Si1-xGex growth for forming crystalline Si1-xGe x films. Finally, a new device

  5. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  6. Additive electroplating technology as a post-CMOS process for the production of MEMS acceleration-threshold switches for transportation applications

    Science.gov (United States)

    Michaelis, Sven; Timme, Hans-Jörg; Wycisk, Michael; Binder, Josef

    2000-06-01

    This paper presents an acceleration-threshold sensor fabricated with an electroplating technology which can be integrated on top of a pre-processed CMOS signal processing circuit. The device can be manufactured using a standard low-cost CMOS production line and then adding the mechanical sensor elements via a specialized back-end process. This makes the system especially interesting for automotive applications, such as airbag safety systems or transportation shock monitoring systems, where smaller size, improved functionality, high reliability and low costs are important.

  7. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise...... model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...

  8. The CMOS integration of a power inverter

    Science.gov (United States)

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  9. High-speed analog CMOS pipeline system

    Science.gov (United States)

    Möschen, J.; Caldwell, A.; Hervas, L.; Hosticka, B.; Kötz, U.; Sippach, B.

    1990-03-01

    We present a switched-capacitor readout system for high speed analog signals. It consists of a 10 MHz four-channel delay-line chip with 58 samples per channel and a 12 channel buffer chip with a sampling rate of 1 MHz and a depth of nine samples. In addition the buffer chip includes an analog multiplexer with 25 inputs for the buffer channels and for 13 additional unbuffered signals. Both chips have been fabricated in CMOS-technology and will be used for the readout of the ZEUS high resolution calorimeter. The circuit and chip concept will be presented and some design optimizations will be discussed. Measurements from integrated prototypes will be given including some experimental data from irradiated chips.

  10. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with mic......Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible...... with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...... platform and its integration in future electronic chips....

  11. Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

    Science.gov (United States)

    Sherwood, Nicholas Ramsey

    While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

  12. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. © 2015 Wiley Periodicals, Inc.

  13. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  14. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  15. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  16. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  17. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    Science.gov (United States)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

  18. Selenium coated CMOS passive pixel array for medical imaging

    Science.gov (United States)

    Majid, Shaikh Hasibul; Goldan, Amir H.; Hadji, Bahman; Belev, George; Kasap, Safa; Karim, Karim S.

    2011-03-01

    Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how an 8×8 PPS array is integrated with the 75 micron thick stabilized amorphous selenium detector. A non-linear increase in the dark current of 200 pA, 500 pA and 2 nA is observed with 0.27, 0.67 and 1.33 V/micron electric field respectively, which shows a successful integration of selenium layer with the CMOS array. Results also show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research, which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

  19. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  20. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    OpenAIRE

    Fangming Deng; Yigang He; Chaolong Zhang; Wei Feng

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate ...

  1. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  2. Modeling and simulation of TDI CMOS image sensors

    Science.gov (United States)

    Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

    2013-09-01

    In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

  3. Radiation-Tolerant High-Speed Camera

    Science.gov (United States)

    2017-03-01

    Radiation -Tolerant High-Speed Camera Esko Mikkola, Andrew Levy, Matt Engelman Alphacore, Inc. Tempe, AZ 85281 Abstract: As part of an... radiation -hardened CMOS image sensor and camera system. Radiation -hardened cameras with frame rates as high as 10 kfps and resolution of 1Mpixel are not...camera solution that is under development with a similar architecture. It also includes a brief description of the radiation -hardened camera that

  4. Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

    Science.gov (United States)

    Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2014-02-01

    This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

  5. 28 nm CMOS process ESD protection based on diode-triggered silicon controlled rectifier

    Science.gov (United States)

    Li, Xiang; Dong, Shurong; Jin, Hao; Miao, Meng; Hu, Tao; Guo, Wei; Wong, Hei

    2017-11-01

    The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28 nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7 mA/μm which was about 65% larger than that of a simple SCR with the same width of 30 μm and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.

  6. Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

    Science.gov (United States)

    Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

    2018-01-01

    Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

  7. Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

    Directory of Open Access Journals (Sweden)

    David Bol

    2011-01-01

    Full Text Available Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

  8. CMOS pixel sensor for a space radiation monitor with very low cost, power and mass

    Science.gov (United States)

    Zhou, Y.; Baudot, J.; Duverger, C.; Hu-Guo, Ch; Hu, Y.; Winter, M.

    2012-12-01

    With the purpose of measuring simultaneously the proton and electron environment using a single sensitive device, we propose a CMOS pixel sensor featuring a 10 mm2 sensitive area, counting capability up to 107/cm2/s and with a minimal error due to pileup of two close particle impacts on the matrix. The proposed architecture includes a 64 × 64 square pixel matrix with 50 μm pitch size, 64 column level 3-bit ADCs to provide an appropriate energy resolution, and an embedded digital logic that directly calculates the particle properties from the hit information provided by the pixels. To validate experimentally the expected performance within the year 2012, a first prototype has been designed and fabricated in a 0.35 μm process without the integrated digital processing part. The device simulation and design architecture are presented.

  9. Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

    CERN Document Server

    Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

    2010-01-01

    We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

  10. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  11. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  12. Fixed Pattern Noise pixel-wise linear correction for crime scene imaging CMOS sensor

    Science.gov (United States)

    Yang, Jie; Messinger, David W.; Dube, Roger R.; Ientilucci, Emmett J.

    2017-05-01

    Filtered multispectral imaging technique might be a potential method for crime scene documentation and evidence detection due to its abundant spectral information as well as non-contact and non-destructive nature. Low-cost and portable multispectral crime scene imaging device would be highly useful and efficient. The second generation crime scene imaging system uses CMOS imaging sensor to capture spatial scene and bandpass Interference Filters (IFs) to capture spectral information. Unfortunately CMOS sensors suffer from severe spatial non-uniformity compared to CCD sensors and the major cause is Fixed Pattern Noise (FPN). IFs suffer from "blue shift" effect and introduce spatial-spectral correlated errors. Therefore, Fixed Pattern Noise (FPN) correction is critical to enhance crime scene image quality and is also helpful for spatial-spectral noise de-correlation. In this paper, a pixel-wise linear radiance to Digital Count (DC) conversion model is constructed for crime scene imaging CMOS sensor. Pixel-wise conversion gain Gi,j and Dark Signal Non-Uniformity (DSNU) Zi,j are calculated. Also, conversion gain is divided into four components: FPN row component, FPN column component, defects component and effective photo response signal component. Conversion gain is then corrected to average FPN column and row components and defects component so that the sensor conversion gain is uniform. Based on corrected conversion gain and estimated image incident radiance from the reverse of pixel-wise linear radiance to DC model, corrected image spatial uniformity can be enhanced to 7 times as raw image, and the bigger the image DC value within its dynamic range, the better the enhancement.

  13. Characterization of active CMOS pixel sensors on high resistive substrate

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

    2016-07-01

    Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  14. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  15. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Science.gov (United States)

    2012-12-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors and...

  16. Non-logic devices in logic processes

    CERN Document Server

    Ma, Yanjun

    2017-01-01

    This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes.  Readers will benefit from the author’s extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.

  17. Bioelectronic Sensors and Devices

    Science.gov (United States)

    Reed, Mark

    Nanoscale electronic devices have recently enabled the ability to controllably probe biological systems, from the molecular to the cellular level, opening up new applications and understanding of biological function and response. This talk reviews some of the advances in the field, ranging from diagnostic and therapeutic applications, to cellular manipulation and response, to the emulation of biological response. In diagnostics, integrated nanodevice biosensors compatible with CMOS technology have achieved unprecedented sensitivity, enabling a wide range of label-free biochemical and macromolecule sensing applications down to femtomolar concentrations. These systems have demonstrated integrated assays of biomarkers at clinically important concentrations for both diagnostics and as a quantitative tool for drug design and discovery. Cellular level response can also be observed, including immune response function and dynamics. Finally, the field is beginning to create devices that emulate function, and the demonstration of a solid state artificial ion channel will be discussed.

  18. A CMOS humidity sensor for passive RFID sensing applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  19. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2014-05-01

    Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  20. Analytic models of CMOS logic in various regimes

    Directory of Open Access Journals (Sweden)

    Dokić Branko

    2014-01-01

    Full Text Available In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

  1. Design of CMOS logic gates for TID radiation

    Science.gov (United States)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  2. Equalizing Si photodetectors fabricated in standard CMOS processes

    Science.gov (United States)

    Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

    2017-05-01

    This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

  3. Piezoresistive Sensors Development Using Monolithic CMOS MEMS Technology

    Directory of Open Access Journals (Sweden)

    A. Chaehoi

    2011-04-01

    Full Text Available This paper presents the development of a monolithic CMOS-MEMS platform under the iDesign and SemeMEMS projects with the aim of jointly providing an open access “one-stop-shop” design and prototyping facility for integrated CMOS-MEMS. This work addresses the implementation of a 3-axis accelerometer and a pressure sensor using Semefab’s in-house 2-poly 1-metal CMOS process on a 380/4/15 μm SOI wafer; the membrane and the proof mass being micromachined using double-sided Deep Reactive Ion Etching (DRIE. This monolithic approach promises, in high volume production and using low complexity processes, a dramatic cost reduction over hybrid sensors. Furthermore, the embedded signal conditioning and the low-noise level in polysilicon gauges enables high performance to be achieved by implementing dedicated on-chip amplification and filtering circuitry.

  4. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  5. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...... of the electrical parameters of n-channel and p-channel transistors. The magnetron sputtering technique is shown to be compatible with standard CMOS electronics without any restriction of the metal types and annealing requirements.......This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation...

  6. Using a large area CMOS APS for direct chemiluminescence detection in Western blotting electrophoresis

    Science.gov (United States)

    Esposito, Michela; Newcombe, Jane; Anaxagoras, Thalis; Allinson, Nigel M.; Wells, Kevin

    2012-03-01

    Western blotting electrophoretic sequencing is an analytical technique widely used in Functional Proteomics to detect, recognize and quantify specific labelled proteins in biological samples. A commonly used label for western blotting is Enhanced ChemiLuminescence (ECL) reagents based on fluorescent light emission of Luminol at 425nm. Film emulsion is the conventional detection medium, but is characterized by non-linear response and limited dynamic range. Several western blotting digital imaging systems have being developed, mainly based on the use of cooled Charge Coupled Devices (CCDs) and single avalanche diodes that address these issues. Even so these systems present key drawbacks, such as a low frame rate and require operation at low temperature. Direct optical detection using Complementary Metal Oxide Semiconductor (CMOS) Active Pixel Sensors (APS)could represent a suitable digital alternative for this application. In this paper the authors demonstrate the viability of direct chemiluminescent light detection in western blotting electrophoresis using a CMOS APS at room temperature. Furthermore, in recent years, improvements in fabrication techniques have made available reliable processes for very large imagers, which can be now scaled up to wafer size, allowing direct contact imaging of full size western blotting samples. We propose using a novel wafer scale APS (12.8 cm×13.2 cm), with an array architecture using two different pixel geometries that can deliver an inherently low noise and high dynamic range image at the same time representing a dramatic improvement with respect to the current western blotting imaging systems.

  7. Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

    CERN Document Server

    Gonella, L; Silvestri, M; Gerardin, S; Pantano, D; Re, V; Manghisoni, M; Ratti, L; Ranieri, A

    2007-01-01

    The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of th...

  8. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  9. Metal-insulator-silicon-insulator-metal waveguides compatible with standard CMOS technology.

    Science.gov (United States)

    Kwon, Min-Suk

    2011-04-25

    Metal-insulator-silicon-insulator-metal (MISIM) waveguides are proposed and investigated theoretically. They are hybrid plasmonic waveguides, and light is highly confined to the insulator between the metal and silicon. As compared to previous ones, they are advantageous since they may be realized in a simple way by using current standard CMOS technology and their insulator is easily replaceable without affecting the metal and silicon. First, their structure and fabrication process are explained, both of which are compatible with standard CMOS technology. Then, the characteristics of the single MISIM waveguide whose insulator has its original or an adjusted refractive index are analyzed. The analysis demonstrates that its characteristics are comparable to those of previous hybrid plasmonic waveguides and that they are very effectively tuned by changing the refractive index of the insulator. Finally, the characteristics of the two coupled MISIM waveguides are analyzed. Through the analysis, it is obtained how close or far apart they are for efficient power transfer or low crosstalk. MISIM-waveguide-based devices may play an important role in connecting Si-based photonic and electronic circuits.

  10. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

    2017-05-01

    Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  11. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  12. LGSD/NGSD: high speed optical CMOS imagers for E-ELT adaptive optics

    Science.gov (United States)

    Downing, Mark; Kolb, Johann; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Payne, Andrew; Pike, Andrew; Reyes, Javier; Simpson, Robert; Stadler, Eric; Stent, Jeremy; Swift, Nick

    2014-07-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the optical Laser/Natural Guide Star WFS detector. The combination of large format, 1760×1680 pixels to finely sample the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 frames per second (fps), low read noise ( 90%) makes the development of this device extremely challenging. Design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most likely technology to succeed. Two generations of the CMOS Imager are being developed: a) the already designed and manufactured NGSD (Natural Guide Star Detector), a quarter-sized pioneering device of 880×840 pixels capable of meeting first light needs of the E-ELT; b) the LGSD (Laser Guide Star Detector), the larger full size device. The detailed design is presented including the approach of using massive parallelism (70,400 ADCs) to achieve the low read noise at high pixel rates of ~3 Gpixel/s and the 88 channel LVDS 220Mbps serial interface to get the data off-chip. To enable read noise closer to the goal of 1e- to be achieved, a split wafer run has allowed the NGSD to be manufactured in the more speculative, but much lower read noise, Ultra Low Threshold Transistors in the unit cell. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). First results of tests performed both at e2v and ESO are presented.

  13. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  14. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as respondents...

  15. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  16. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  17. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  18. A 0.5-GHz CMOS digital RF memory chip

    Science.gov (United States)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  19. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  20. CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

    KAUST Repository

    Ghoneim, Mohamed T.

    2014-08-01

    Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

  1. Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

    Science.gov (United States)

    Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

    2018-01-01

    We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1–200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

  2. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  3. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  4. Backside-illuminated, high-QE, 3e- RoN, fast 700fps, 1760x1680 pixels CMOS imager for AO with highly parallel readout

    Science.gov (United States)

    Downing, Mark; Kolb, Johann; Baade, Dietrich; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Dupont, Benoit; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Iwert, Olaf; Jerram, Paul; Jorden, Paul; Pike, Andrew; Pratlong, Jerome; Reyes, Javier; Stadler, Eric; Walker, Andrew

    2012-07-01

    The success of the next generation of instruments for 8 to 40-m class telescopes will depend upon improving the image quality (correcting the distortion caused by atmospheric turbulence) by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the Laser/Natural Guide Star (LGS/NGS) WaveFront Sensing (WFS) detector. The combination of large format, 1760x1680 pixels to finely sample (84x84 sub-apertures) the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 (up to 1000) frames per second, low read noise ( 90%) makes the development of such a device extremely challenging. Design studies by industry concluded that a thinned and backside-illuminated CMOS Imager as the most promising technology. This paper describes the multi-phased development plan that will ensure devices are available on-time for E-ELT first-light AO systems; the different CMOS pixel architectures studied; measured results of technology demonstrators that have validated the CMOS Imager approach; the design explaining the approach of massive parallelism (70,000 ADCs) needed to achieve low noise at high pixel rates of ~3 Gpixel/s ; the 88 channel LVDS data interface; the restriction that stitching (required due to the 5x6cm size) posed on the design and the solutions found to overcome these limitations. Two generations of the CMOS Imager will be built: a pioneering quarter sized device of 880x840 pixels capable of meeting first light needs of the E-ELT called NGSD (Natural Guide Star Detector); followed by the full size device, the LGSD (Laser Guide Star Detector). Funding sources: OPTICON FP6 and FP7 from European Commission and ESO.

  5. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments practical design aspects

    CERN Document Server

    Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    1999-01-01

    We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).

  6. A Wide-Band CMOS Injection Locked Frequency Divider

    NARCIS (Netherlands)

    Acar, M.; Leenaerts, Domine; Nauta, Bram

    In this paper we propose a novel inductorless injection-locked frequency divider (ILFD) that can make divisions with ratios 2,4,6 and 8 with wide locking ranges. Fabricated in a digital 0.18 μm CMOS process the divider can operate up to 15 GHz. The measured locking ranges of the divider for division

  7. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  8. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  9. Temperature Sensors Integrated into a CMOS Image Sensor

    NARCIS (Netherlands)

    Abarca Prouza, A.N.; Xie, S.; Markenhof, Jules; Theuwissen, A.J.P.

    2017-01-01

    In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of

  10. A CMOS four-quadrant analog current multiplier

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1991-01-01

    A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

  11. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...

  12. High-speed photodiodes in standard CMOS technology

    NARCIS (Netherlands)

    Radovanovic, S.

    2004-01-01

    This thesis describes high-speed photodiodes in standard CMOS technology which allow monolithic integration of optical receivers for short-haul communication. The electronics for (multiple users) long-haul communication is very expensive (InP, GaAs), but the usage is justified by the large number of

  13. Monolithic optical link in silicon-on-insulator CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal; Agarwal, Vishal Vishal; Hueting, Raymond Josephus Engelbart; Schmitz, Jurriaan; Annema, Anne J.

    2017-01-01

    This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical

  14. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    Abstract. This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS ...

  15. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  16. Fundamental Characteristics of a Pinned Photodiode CMOS Pixels

    NARCIS (Netherlands)

    Xu, Y.

    2015-01-01

    This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier.

  17. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  18. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    Directory of Open Access Journals (Sweden)

    Mao-Chen Liu

    2010-02-01

    Full Text Available This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  19. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  20. Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

    Directory of Open Access Journals (Sweden)

    Kwang-Jow Gan

    2016-06-01

    Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

  1. A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT

    Science.gov (United States)

    Zucca, S.; Ratti, L.; Traversi, G.; Morsani, F.; Gabrielli, A.; Giorgi, F.

    2013-08-01

    The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.

  2. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Guo-Neng Lu

    2009-01-01

    Full Text Available We present a single-transistor pixel for CMOS image sensors (CIS. It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

  3. Optimisation of CMOS pixel sensors for high performance vertexing and tracking

    CERN Document Server

    Baudot, Jérôme; Claus, Gilles; Dulinski, Wojciech; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Molnar, Levente; Sanchez-Castro, Xitzel; Senyukov, Serhiy; Winter, Marc

    2013-01-01

    CMOS Pixel Sensors tend to become relevant for a growing spectrum of charged particle detection instruments. This comes mainly from their high granularity and low material budget. However, several potential applications require a higher read-out speed and radiation tolerance than those achieved with available devices based on a 0.35 micrometers feature size technology. This paper shows preliminary test results of new prototype sensors manufactured in a 0.18 micrometers process based on a high resistivity epitaxial layer of sizeable thickness. Grounded on these observed performances, we discuss a development strategy over the coming years to reach a full scale sensor matching the specifications of the upgraded version of the Inner Tracking System (ITS) of the ALICE experiment at CERN, for which a sensitive area of up to about 10 square meters may be equipped with pixel sensors.

  4. A High Performance CMOS Current Mirror Circuit with Neuron MOSFETs and a Transimpedance Amplifier

    Science.gov (United States)

    Shimizu, Akio; Ishikawa, Yohei; Fukai, Sumio; Aikawa, Masayoshi

    In this paper, we propose a high accuracy current mirror circuit suitable for a low-voltage operation. The proposed circuit has a novel negative feedback that is composed of neuron MOSFETs and a transimpedance amplifier. As a result, the proposed circuit achieves a high accuracy current mirror circuit. At the same time, the proposed circuit monitors an error current by a low voltage because the negative feedback operates in a current-mode. The performance of the proposed circuit is evaluated using HSPICE simulation with On-Semiconductor 1.48μm CMOS device parameters. Simulation results show that the output resistance of the proposed circuit is 5.79[GΩ] and minimum operating range is 0.3[V].

  5. A comprehensive model on field-effect pnpn devices (Z2-FET)

    Science.gov (United States)

    Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

    2017-08-01

    A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

  6. AC signal characterization for optimization of a CMOS single-electron pump

    Science.gov (United States)

    Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

    2018-02-01

    Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

  7. Microfabrication and Characterization of an Integrated 3-Axis CMOS-MEMS Accelerometer

    Directory of Open Access Journals (Sweden)

    Hongwei QU

    2007-10-01

    Full Text Available This paper reports the fabrication and characterization of a monolithically integrated 3-axis CMOS-MEMS accelerometer with a single proof mass. An improved microfabrication process has been developed to solve the structure overheating and particle contamination problems in the plasma etching processes of device fabrication. The whole device is made of bulk silicon except for some short thin films for electrical isolation, allowing large sensing capacitance and flat device structure. A low-noise, low-power amplifier is designed for each axis, which provides 40 dB on-chip amplification and consumes only 1 mW power. Quasi-static and dynamic characterization of the fabricated device has been performed. The measured sensitivities of the lateral- and z-axis accelerometers are 560 mV/g and 320 mV/g, respectively, which can be tuned by simply varying the amplitude of the modulation signal. The over-all noise floors of the lateral- and z-axis are 12 μg/ÖHz and 110 μg/ÖHz, respectively when tested at 200 Hz.

  8. Single InAs/GaSb nanowire low-power CMOS inverter.

    Science.gov (United States)

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  9. Germanium CMOS potential from material and process perspectives: Be more positive about germanium

    Science.gov (United States)

    Toriumi, Akira; Nishimura, Tomonori

    2018-01-01

    CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III–V compounds. There is a debate that Ge should be used for p-MOSFETs and III–V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices

  10. CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks

    Science.gov (United States)

    Hopf, Toby; Ercken, Monique; Mannaert, Geert; Kunnen, Eddy; Tao, Zheng; Vandenbroeck, Nadia; Sebaai, Farid; Kikuchi, Yoshiaki; Mertens, Hans; Kubicek, Stefan; Demuynck, Steven; Horiguchi, Naoto

    2017-03-01

    In this paper proof-of-principle demonstrations of spin-on carbon (SOC)/spin-on glass (SOG)-based lithography processes which could replace standard patterning stacks within the FEOL for upcoming advanced nodes like N10/N7 are presented. At these dimensions the standard lithography approaches that have been utilized within the previous nodes will begin to run into fundamental limitations as a result of the extremely high aspect ratios of the device topography, requiring both new materials as well as new patterning flows in order to allow for continued device scaling. Here, novel SOC/SOG-based patterning flows have been demonstrated which could be applied to implement Source Drain Extension implantations and epitaxial growth processes for CMOS FinFET device architectures even down at N10/N7 dimensions.

  11. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    Science.gov (United States)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  12. Fault-tolerant architectures for nanoelectronic and quantum devices

    NARCIS (Netherlands)

    Han, J.

    2004-01-01

    The progress in CMOS technology has entered the sub-micron realm, and the technology will approach its limits within about 15 years. Already various novel information processing devices, based on quantum mechanical effects at the nanometer scale, have been widely investigated and some have been

  13. Registration of Large Motion Blurred CMOS Images

    Science.gov (United States)

    2017-08-28

    any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information   if it does not display a...Comprehensive comparisons with state-of-the art methods reveal that their approach not only exhibits significant computational gains and unconstrained...functionality but also leads to improved performance. 15. SUBJECT TERMS Image Processing, Motion Blur, charge-coupled device, complementary metal-oxide

  14. Development of a low-cost 2.5-Gbps SFP optical transceiver using 0.18μm CMOS ICs

    Science.gov (United States)

    Chai, Yi Yoon; Zhang, Jing; Ramana, Pamidighantma V.; Yap, Guan Jie; Lau, John Hon-Shing

    2008-02-01

    The high cost of optoelectronics components typically used for long-haul communication is prohibitive in the Fiber to the Home (FTTH) and Passive Optical Networks (PONs). One method of cost reduction is through the reducing the cost of the electronics in the transceiver and reducing the packaging cost. We report the development of low-cost 2.5-Gbps optical transceiver for Gigabit Passive Optical Network (GPON) using CMOS driver ICs and chip-on-board assembly method. We developed the Laser Diode Driver (LDD), Trans-impedance Amplifier (TIA), Limiting Amplifier (LA) and the Clock and Data Recovery (CDR) using CMOS technology for short reach application and developed the burst mode version of the ICs for PON applications. The ICs are designed in house and fabricated on a standard CMOS 8" wafer with 0.18μm technology. The devices operate at 1.8V and are low power in nature, thus reducing the demand on power dissipation. The transceiver consists of an un-cooled and direct modulated laser diode driven with a LDD, a high speed PIN photo-diode with amplifier and CMOS ICs. The bare CMOS ICs are attached on a transceiver substrate that is compliant with the small form-factor pluggable (SFP) package multisource agreement (MSA) and coupled to a 1310nm FP laser TOSA and a PIN ROSA with LC connector. The integrated transceiver is characterized up to 2.5-Gbps. In this publication, we present the detail of the module development, assembly methods and performance characterization at 1310nm.

  15. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  16. Characterisation of a novel reverse-biased PPD CMOS image sensor

    Science.gov (United States)

    Stefanov, K. D.; Clarke, A. S.; Ivory, J.; Holland, A. D.

    2017-11-01

    A new pinned photodiode (PPD) CMOS image sensor (CIS) has been developed and characterised. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the pixel p-wells, called Deep Depletion Extension (DDE), have been added in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The first prototype has been manufactured on a 18 μm thick, 1000 Ω .cm epitaxial silicon wafers using 180 nm PPD image sensor process at TowerJazz Semiconductor. The chip contains arrays of 10 μm and 5.4 μm pixels, with variations of the shape, size and the depth of the DDE implant. Back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v, and characterised together with the front-side illuminated (FSI) variants. The presented results show that the devices could be reverse-biased without parasitic leakage currents, in good agreement with simulations. The new 10 μm pixels in both BSI and FSI variants exhibit nearly identical photo response to the reference non-modified pixels, as characterised with the photon transfer curve. Different techniques were used to measure the depletion depth in FSI and BSI chips, and the results are consistent with the expected full depletion.

  17. Monolithic integration of a novel microfluidic device with silicon light emitting diode-antifuse and photodetector

    NARCIS (Netherlands)

    Le Minh, P.; Holleman, J.; Berenschot, Johan W.; Tas, Niels Roelof; van den Berg, Albert

    2002-01-01

    Light emitting diode antifuse has been integrated into a microfluidic device that is realized with extended standard CMOS technological steps. The device comprises of a microchannel sandwiched between a photodiode detector and a nanometer-scale diode antifuse light emitter. Within this contribution,

  18. Integration of a novel microfluidic device with silicon light emitting diode-antifuse and photodetector

    NARCIS (Netherlands)

    Le Minh, P.; Holleman, J.; Berenschot, Johan W.; Tas, Niels Roelof; van den Berg, Albert

    2002-01-01

    Light emitting diode antifuse has been integrated into a microfluidic device that is realized with extended standard CMOS technological steps. The device comprises of a microchannel sandwiched between a photodiode detector and a nanometer-scale diode antifuse light emitter. Within this contribution,

  19. Gate current for p+-poly PMOS devices under gate injection conditions

    NARCIS (Netherlands)

    Hof, A.J.; Holleman, J.; Woerlee, P.H.

    2001-01-01

    In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the

  20. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    Science.gov (United States)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  1. A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications

    Directory of Open Access Journals (Sweden)

    Taeho Oh

    2017-12-01

    Full Text Available Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS and two p-channel MOSFETs (PMOS devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process.

  2. Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

    Science.gov (United States)

    Lu, Chih-Cheng; Liao, Kuan-Hsun; Udrea, F.; Covington, J. A.; Gardner, J. W.

    2008-07-01

    This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms.

  3. Smart CMOS image sensor for lightning detection and imaging.

    Science.gov (United States)

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  4. CMOS nanoelectrode array for all-electrical intracellular electrophysiological imaging

    Science.gov (United States)

    Abbott, Jeffrey; Ye, Tianyang; Qin, Ling; Jorgolli, Marsela; Gertner, Rona S.; Ham, Donhee; Park, Hongkun

    2017-05-01

    Developing a new tool capable of high-precision electrophysiological recording of a large network of electrogenic cells has long been an outstanding challenge in neurobiology and cardiology. Here, we combine nanoscale intracellular electrodes with complementary metal-oxide-semiconductor (CMOS) integrated circuits to realize a high-fidelity all-electrical electrophysiological imager for parallel intracellular recording at the network level. Our CMOS nanoelectrode array has 1,024 recording/stimulation 'pixels' equipped with vertical nanoelectrodes, and can simultaneously record intracellular membrane potentials from hundreds of connected in vitro neonatal rat ventricular cardiomyocytes. We demonstrate that this network-level intracellular recording capability can be used to examine the effect of pharmaceuticals on the delicate dynamics of a cardiomyocyte network, thus opening up new opportunities in tissue-based pharmacological screening for cardiac and neuronal diseases as well as fundamental studies of electrogenic cells and their networks.

  5. Micromachined high-performance RF passives in CMOS substrate

    Science.gov (United States)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  6. A passive CMOS pixel sensor for the high luminosity LHC

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    The high luminosity upgrade for the Large Hadron Collider at CERN requires a new inner tracking detector for the ATLAS experiment. About 200 m{sup 2} of silicon detectors are needed demanding new, low cost hybridization- and sensor technologies. One promising approach is to use commercial CMOS technologies to produce the passive sensor for a hybrid pixel detector design. In this talk a fully functional prototype of a 300 μm thick, backside biased CMOS pixel sensor in 150 nm LFoundry technology is presented. The sensor is bump bonded to the ATLAS FE-I4 with AC and DC coupled pixels. Results like leakage current, noise performance, and charge collection efficiency are presented and compared to the actual ATLAS pixel sensor design.

  7. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  8. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  9. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  10. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  11. Radiation-induced edge effects in deep submicron CMOS transistors

    CERN Document Server

    Faccio, F

    2005-01-01

    The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

  12. A CMOS biosensor array for measuring cellular exocytosis.

    OpenAIRE

    Ayers, S.

    2009-01-01

    Release of neurotransmitters and hormones from secretory vesicles plays a fundamental role in the function of the nervous system including neuronal communication. High-throughput testing of drugs modulating transmitter release is becoming an increasingly important area in the fields of cell biology, neurobiology, and neurology. In this thesis, I will describe the design and operation of a novel CMOS potentiostat circuit that is capable of measuring transient amperometric oxidation currents at...

  13. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    Science.gov (United States)

    Do, Trong-Hop; Yoo, Myungsik

    2016-02-29

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

  14. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers.

    Science.gov (United States)

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d(33f), d(31) and d(33) of up to 2.9, -1.9 and 6.5 pm V(-1), respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  15. CMOS IC design for wireless medical and health care

    CERN Document Server

    Wang, Zhihua; Chen, Hong

    2014-01-01

    This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to tu...

  16. CMOS integration of inkjet-printed graphene for humidity sensing

    Science.gov (United States)

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  17. Self-calibrated humidity sensor in CMOS without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  18. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Kazusuke Maenaka; Kohei Higuchi; Oleg Nizhnik

    2011-01-01

    A 1.1 µW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  19. Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

  20. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

    CERN Document Server

    Cerjan, C J

    2000-01-01

    The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

  1. The design, simulation, and fabrication of a BiCMOS VLSI digitally programmable GIC filter

    OpenAIRE

    Milne, Paul R.

    2001-01-01

    This thesis used a previously-designed programmable GIC filter as a basis in which to incorporate a BiCMOS operational amplifier. An NPN bipolar transistor layout was designed and incorporated into an opamp layout, which was a modified version of a CMOS-only design. The BiCMOS opamp was simulated using Silvaco SmartSpice and showed considerable improvement over its CMOS equivalent. Additional improvements were made to the GIC filter to include a passgate with reduced resistance, and a correct...

  2. Metrology solutions using optical scatterometry for advanced CMOS: III-V and Germanium multi-gate field-effect transistors

    Science.gov (United States)

    Chin, Hock-Chun; Liu, Bin; Zhang, Xingui; Ling, Moh-Lung; Yip, Chan-Hoe; Liu, Yongdong; Hu, Jiangtao; Yeo, Yee-Chia

    2013-04-01

    In this work, we report metrology solutions using scatterometry Optical Critical Dimension (OCD) characterization on two advanced CMOS devices: novel n-channel gate-last In0.53Ga0.47As FinFET with self-aligned Molybdenum (Mo) contacts and p-channel Ge FinFET formed on Germanium-on-Insulator (GOI) substrate. Key critical process steps during the fabrication of these advanced transistors were identified for process monitor using scatterometry OCD measurement to improve final yield. Excellent correlation with reference metrology and high measurement precision were achieved by using OCD characterization, confirming scatterometry OCD as a promising metrology technique for next generation device applications. In addition, we also further explore OCD characterization using normal incidence spectroscopic reflectometry (SR), oblique incidence spectroscopic ellipsometry (SE), and combined SR+SE technologies. The combined SR+SE approach was found to provide better precision.

  3. Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

    Science.gov (United States)

    Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

    The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

  4. Contact engineering for nano-scale CMOS

    KAUST Repository

    Hussain, Muhammad Mustafa

    2012-09-10

    High performance computation with longer battery lifetime is an essential component in our today\\'s digital electronics oriented life. To achieve these goals, field effect transistors based complementary metal oxide semiconductor play the key role. One of the critical requirements of transistor structure and fabrication is efficient contact engineering. To catch up with high performance information processing, transistors are going through continuous scaling process. However, it also imposes new challenges to integrate good contact materials in a small area. This can be counterproductive as smaller area results in higher contact resistance thus reduced performance for the transistor itself. At the same time, discovery of new one or two-dimensional materials like nanowire, nanotube, or atomic crystal structure materials, introduces new set of challenges and opportunities. In this paper, we are reviewing them in a synchronized fashion: fundamentals of contact engineering, evolution into non-planar field effect transistors, opportunities and challenges with one and two-dimensional materials and a new opportunity of contact engineering from device architecture perspective. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. A CMOS IC–based multisite measuring system for stimulation and recording in neural preparations in vitro

    Directory of Open Access Journals (Sweden)

    Takashi eTateno

    2014-10-01

    Full Text Available In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS integrated circuit (IC chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 mm × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA, and a PC. To test the system, microelectrode arrays (MEAs were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μV root mean square (10 Hz to 100 kHz, which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μVpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  6. Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

    Science.gov (United States)

    Tseng, Sheng-Hsiang; S-C Lu, Michael; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

    2012-05-01

    This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm2, and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G-1with a standard deviation of 2.5 mV G-1. The measured output noise floor is 354 µG Hz-1/2, corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C-1 below 85 °C.

  7. Point Defects in Al2O3 and their impact on novel CMOS performance

    Science.gov (United States)

    Weber, Justin; Janotti, Anderson; van de Walle, Chris

    2010-03-01

    The desire for III-V CMOS devices has stimulated interest in novel dielectrics, which form high-quality interfaces III-V semiconductors. Recent significant progress has been reported using Al2O3. However, there is concern about defects that could degrade device quality. Therefore, we have performed a first-principles study of point defects in Al2O3. We analyze native point defects such as vacancies, self-interstitials, antisites, and dangling bonds, as well as hydrogen-related defects. Our first-principles calculations utilize state-of-the-art hybrid-functional methods within the HSE formalism. We also use calculated band offsets to make predictions about the location of defect levels with respect to the band edges of relevant III-V semiconductors. We find that the oxygen vacancy defect introduces defect levels near the conduction-band edge of relevant channel materials. Also, we find that vacancies can be responsible for accumulation of fixed charge in the crystal. Finally, hydrogen is considered as a passivation agent for defect states and fixed charge introduced by vacancy-related defects. Work supported by the Semiconductor Research Corporation and by NSF.

  8. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  9. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  10. An ebCMOS camera system for marine bioluminescence observation: The LuSEApher prototype

    Energy Technology Data Exchange (ETDEWEB)

    Dominjon, A., E-mail: a.dominjon@ipnl.in2p3.fr [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Ageron, M. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Billault, M.; Brunner, J. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Calabria, P. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Chabanat, E. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Chaize, D.; Doan, Q.T.; Guerin, C.; Houles, J.; Vagneron, L. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France)

    2012-12-11

    The ebCMOS camera, called LuSEApher, is a marine bioluminescence recorder device adapted to extreme low light level. This prototype is based on the skeleton of the LUSIPHER camera system originally developed for fluorescence imaging. It has been installed at 2500 m depth off the Mediterranean shore on the site of the ANTARES neutrino telescope. The LuSEApher camera is mounted on the Instrumented Interface Module connected to the ANTARES network for environmental science purposes (European Seas Observatory Network). The LuSEApher is a self-triggered photo detection system with photon counting ability. The presentation of the device is given and its performances such as the single photon reconstruction, noise performances and trigger strategy are presented. The first recorded movies of bioluminescence are analyzed. To our knowledge, those types of events have never been obtained with such a sensitivity and such a frame rate. We believe that this camera concept could open a new window on bioluminescence studies in the deep sea.

  11. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    Energy Technology Data Exchange (ETDEWEB)

    Saripalli, Ganesh [Iowa State Univ., Ames, IA (United States)

    2002-01-01

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35μ CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  12. Demonstrating the γ-transparency of a CMOS pixel detector for a future neutron dosimeter

    Science.gov (United States)

    Vanstalle, M.; Husson, D.; Higueret, S.; Trocmé, M.; Lê, T. D.; Nourreddine, A. M.

    2012-01-01

    The RaMsEs group (Radioprotection et Mesures Environnementales) is working on a new compact device for operational neutron dosimetry. The electronic part of the detector is made of an integrated active pixel sensor, originally designed for tracking in particle physics. This device has useful features, including a high detection efficiency for charged particles, a good radiation resistance, a high readout speed and a low power consumption. Moreover, because of the thinness of the active layer, these CMOS sensors have low sensitivity to γ-rays, which is an attractive feature for neutron issues. In order to determine the γ response of the sensor, measurements have been carried out with a γ source of 60Co (1.17 MeV and 1.33 MeV). Other experiments have been performed with a fast neutron source of AmBe. We demonstrate the good discrimination between recoil protons from fast neutrons and from γ-background. Our results show that with an appropriate threshold, most γ-rays that generate photoelectrons can be removed from detection.

  13. Micro- and nanoelectronics emerging device challenges and solutions

    CERN Document Server

    Brozek, Tomasz

    2014-01-01

    Micro- and Nanoelectronics: Emerging Device Challenges and Solutions presents a comprehensive overview of the current state of the art of micro- and nanoelectronics, covering the field from fundamental science and material properties to novel ways of making nanodevices. Containing contributions from experts in both industry and academia, this cutting-edge text:Discusses emerging silicon devices for CMOS technologies, fully depleted device architectures, characteristics, and scalingExplains the specifics of silicon compound devices (SiGe, SiC) and their unique propertiesExplores various options

  14. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  15. Analysis and Design of Monolithic Inductors in Sub-micron CMOS

    DEFF Research Database (Denmark)

    Fallesen, Carsten; Jørgensen, Allan

    1997-01-01

    In the last few years the CMOS processes have gone into deep sub-micron channel lengths. This means that it is now possible to make GHz applications in CMOS. In analog GHz applications it is often necessary to have access to inductors. This report describes the development of a physical model of ...

  16. Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

    Science.gov (United States)

    Lee, C.; Johnston, A.

    1998-01-01

    This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

  17. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  18. An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.

    2013-01-01

    This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

  19. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the `126...

  20. An integrated CMOS quantitative-polymerase-chain-reaction lab-on-chip for point-of-care diagnostics.

    Science.gov (United States)

    Norian, Haig; Field, Ryan M; Kymissis, Ioannis; Shepard, Kenneth L

    2014-10-21

    Considerable effort has recently been directed toward the miniaturization of quantitative-polymerase-chain-reaction (qPCR) instrumentation in an effort to reduce both cost and form factor for point-of-care applications. Considerable gains have been made in shrinking the required volumes of PCR reagents, but resultant prototypes retain their bench-top form factor either due to heavy heating plates or cumbersome optical sensing instrumentation. In this paper, we describe the use of complementary-metal-oxide semiconductor (CMOS) integrated circuit (IC) technology to produce a fully integrated qPCR lab-on-chip. Exploiting a 0.35 μm high-voltage CMOS process, the IC contains all of the key components for performing qPCR. Integrated resistive heaters and temperature sensors regulate the surface temperature of the chip to an accuracy of 0.45 °C. Electrowetting-on-dielectric microfluidics are actively driven from the chip surface, allowing for droplet generation and transport down to volumes less than 1.2 nanoliter. Integrated single-photon avalanche diodes (SPADs) are used for fluorescent monitoring of the reaction, allowing for the quantification of target DNA with more than four-orders-of-magnitude of dynamic range and sensitivities down to a single copy per droplet. Using this device, reliable and sensitive real-time proof-of-concept detection of Staphylococcus aureus (S. aureus) is demonstrated.

  1. Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

    Science.gov (United States)

    Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

    2014-06-01

    A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10μs latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

  2. A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission.

    Science.gov (United States)

    Lee, Hyung-Min; Ghovanloo, Maysam

    2013-06-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.

  3. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

    Directory of Open Access Journals (Sweden)

    Pooja Batra

    2014-05-01

    Full Text Available For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs, wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS embedded DRAM (EDRAM having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

  4. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... to solve the problem, namely freeze-drying and resist-assisted release. The fabrication results of cantilevers defined by laser and E-beam lithography are shown. Finally, an AFM based characterization setup is presented and the electrical characterization of a laser-defined cantilever fully integrated...

  5. A CMOS readout system for very large detector capacitances

    Science.gov (United States)

    Schoeneberg, U.; Hosticka, B. J.; Fent, J.; Oberlack, H.; Zimmer, G.

    1990-03-01

    In this contribution we present readout electronics for a liquid-argon calorimeter. It has been designed and optimized for operation at cryogenic temperatures and it is integrated in an n-well 2 μm CMOS technology. The chip contains 16 analog channels with switched-capacitor circuits for charge collection, storage, and amplification, and averaging and correlated double sampling circuits for noise reduction. Further components include a trigger generator, an analog multiplexer, digital control circuits for analog switching, and 50 ω cable drivers.

  6. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  7. Solar Battery Charger in CMOS 0.25 um Technology

    OpenAIRE

    Tao Wang; Chang-Ching Huang; Tian-Jen Wang

    2014-01-01

    A solar cell powered Li-ion battery charger in CMOS 0.25um is proposed. The solar battery charger consists of a DC/DC boost converter and a battery charger. The voltage generated by a solar cell is up converted from 0.65V to 1.8V, which is used as the VDD of the battery charger.  In this way, the solar battery charger automatically converts solar energy to electricity and stores it directly to a Li-ion rechargeable battery. In this system, a super capacitor is needed as a charge buffer betwee...

  8. Displacement Damage Effects in Pinned Photodiode CMOS Image Sensors

    OpenAIRE

    Virmontois, Cédric; Goiffon, Vincent; Corbière, Franck; Magnan, Pierre; Girard, Sylvain; Bardoux, Alain

    2012-01-01

    This paper investigates the effects of displacement damage in Pinned Photodiode (PPD) CMOS Image Sensors (CIS) using proton and neutron irradiations. The DDD ranges from 12 TeV/g to ${1.2 times 10^{6}}$ TeV/g. Particle fluence up to $5 times 10^{14}$ n.cm $^{-2}$ is investigated to observe electro-optic degradation in harsh environments. The dark current is also investigated and it would appear that it is possible to use the dark current spectroscopy in PPD CIS. The dark current random telegr...

  9. On drift fields in CMOS monolithic active pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Deveaux, Michael [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2016-07-01

    CMOS Monolithic Active Pixel Sensors (MAPS) combine an excellent spatial resolution of few μm with a very low material budget of 0.05% X{sub 0}. To extend their radiation tolerance to the level needed for future experiments like e.g. CBM, it is regularly considered to deplete their active volume. We discuss the limits of this strategy accounting for the specific features of the sensing elements of MAPS. Moreover, we introduce an alternative approach to generate the drift fields needed to provoke a faster charge collection by means of doping gradients.

  10. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Science.gov (United States)

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  11. Modulation Techniques for Biomedical Implanted Devices and Their Challenges

    Directory of Open Access Journals (Sweden)

    Salina A. Samad

    2011-12-01

    Full Text Available Implanted medical devices are very important electronic devices because of their usefulness in monitoring and diagnosis, safety and comfort for patients. Since 1950s, remarkable efforts have been undertaken for the development of bio-medical implanted and wireless telemetry bio-devices. Issues such as design of suitable modulation methods, use of power and monitoring devices, transfer energy from external to internal parts with high efficiency and high data rates and low power consumption all play an important role in the development of implantable devices. This paper provides a comprehensive survey on various modulation and demodulation techniques such as amplitude shift keying (ASK, frequency shift keying (FSK and phase shift keying (PSK of the existing wireless implanted devices. The details of specifications, including carrier frequency, CMOS size, data rate, power consumption and supply, chip area and application of the various modulation schemes of the implanted devices are investigated and summarized in the tables along with the corresponding key references. Current challenges and problems of the typical modulation applications of these technologies are illustrated with a brief suggestions and discussion for the progress of implanted device research in the future. It is observed that the prime requisites for the good quality of the implanted devices and their reliability are the energy transformation, data rate, CMOS size, power consumption and operation frequency. This review will hopefully lead to increasing efforts towards the development of low powered, high efficient, high data rate and reliable implanted devices.

  12. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  13. CMOS digital intra-oral sensor for x-ray radiography

    Science.gov (United States)

    Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

    2011-03-01

    In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

  14. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  15. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  16. Using high frame rate CMOS sensors for three-dimensional eye tracking.

    Science.gov (United States)

    Clarke, A H; Ditterich, J; Drüen, K; Schönfeld, U; Steineke, C

    2002-11-01

    A novel three-dimensional eye tracker is described and its performance evaluated. In contrast to previous devices based on conventional video standards, the present eye tracker is based on programmable CMOS image sensors, interfaced directly to digital processing circuitry to permit real-time image acquisition and processing. This architecture provides a number of important advantages, including image sampling rates of up to 400/sec measurement, direct pixel addressing for preprocessing and acquisition,and hard-disk storage of relevant image data. The reconfigurable digital processing circuitry also facilitates inline optmization of the front-end, time-critical processes. The primary acquisition algorithm for tracking the pupil and other eye features is designed around the generalized Hough transform. The tracker permits comprehensive measurement of eye movement (three degrees of freedom) and head movement (six degrees of freedom), and thus provides the basis for many types of vestibulo-oculomotor and visual research. The device has been qualified by the German Space Agency (DLR) and NASA for deployment on the International Space Station. It is foreseen that the device will be used together with appropriate stimulus generators as a general purpose facility for visual and vestibular experiments. Initial verification studies with an artificial eye demonstrate a measurement resolution of better than 0.1 degrees in all three components (i.e.,system noise for each of the components measured as 0.006 degrees H, 0.005 degrees V, and 0.016 degrees T. Over a range of +/-20 degrees eye rotation, linearity was found to be <0.5% (H), <0.5% (V), and <2.0% (T). A comparison with the scleral search coil technique yielded near equivalent values for the system noise and the thickness of Listing's plane.

  17. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  18. Development of a multi-sensor CMOS ASIC

    Science.gov (United States)

    van der Merwe, D. G.

    2016-02-01

    A multi-sensor application specific integrated circuit has been developed with a number of sensors: capacitive, inductive, magnetic, ambient light, infrared and acceleration. The capacitive sensing is implemented using a unique, patented, charge transfer technique allowing the measurement of very small capacitances while at the same time eliminating the effects of unwanted parasitic capacitances in the measurement circuit. For cost effective implementation the charge transfer measurement circuit has been has been modified, augmented and expanded to not only measure capacitance but also to act as the measurement circuit for all the sensors. Enabling the multi-sensor chip to measure acceleration on a range of MEMs accelerometer chips including a single axis accelerometer, a dual axis xy accelerometer and a z-axis accelerometer, innovative and patent pending techniques have been developed and implemented on standard CMOS. The CMOS ASIC and a MEMs chip will be double bonded in a plastic package offering multi-sensor capability in a small low cost package.

  19. Macromolecular crystallography with a large format CMOS detector

    Energy Technology Data Exchange (ETDEWEB)

    Nix, Jay C., E-mail: jcnix@lbl.gov [Molecular Biology Consortium 12003 S. Pulaski Rd. #166 Alsip, IL 60803 U.S.A (United States)

    2016-07-27

    Recent advances in CMOS technology have allowed the production of large surface area detectors suitable for macromolecular crystallography experiments [1]. The Molecular Biology Consortium (MBC) Beamline 4.2.2 at the Advanced Light Source in Berkeley, CA, has installed a 2952 x 2820 mm RDI CMOS-8M detector with funds from NIH grant S10OD012073. The detector has a 20nsec dead pixel time and performs well with shutterless data collection strategies. The sensor obtains sharp point response and minimal optical distortion by use of a thin fiber-optic plate between the phosphor and sensor module. Shutterless data collections produce high-quality redundant datasets that can be obtained in minutes. The fine-sliced data are suitable for processing in standard crystallographic software packages (XDS, HKL2000, D*TREK, MOSFLM). Faster collection times relative to the previous CCD detector have resulted in a record number of datasets collected in a calendar year and de novo phasing experiments have resulted in publications in both Science and Nature [2,3]. The faster collections are due to a combination of the decreased overhead requirements of shutterless collections combined with exposure times that have decreased by over a factor of 2 for images with comparable signal to noise of the NOIR-1 detector. The overall increased productivity has allowed the development of new beamline capabilities and data collection strategies.

  20. Backside illuminated CMOS-TDI line scanner for space applications

    Science.gov (United States)

    Cohen, O.; Ben-Ari, N.; Nevo, I.; Shiloah, N.; Zohar, G.; Kahanov, E.; Brumer, M.; Gershon, G.; Ofer, O.

    2017-09-01

    A new multi-spectral line scanner CMOS image sensor is reported. The backside illuminated (BSI) image sensor was designed for continuous scanning Low Earth Orbit (LEO) space applications including A custom high quality CMOS Active Pixels, Time Delayed Integration (TDI) mechanism that increases the SNR, 2-phase exposure mechanism that increases the dynamic Modulation Transfer Function (MTF), very low power internal Analog to Digital Converters (ADC) with resolution of 12 bit per pixel and on chip controller. The sensor has 4 independent arrays of pixels where each array is arranged in 2600 TDI columns with controllable TDI depth from 8 up to 64 TDI levels. A multispectral optical filter with specific spectral response per array is assembled at the package level. In this paper we briefly describe the sensor design and present some electrical and electro-optical recent measurements of the first prototypes including high Quantum Efficiency (QE), high MTF, wide range selectable Full Well Capacity (FWC), excellent linearity of approximately 1.3% in a signal range of 5-85% and approximately 1.75% in a signal range of 2-95% out of the signal span, readout noise of approximately 95 electrons with 64 TDI levels, negligible dark current and power consumption of less than 1.5W total for 4 bands sensor at all operation conditions .

  1. A CMOS variable gain LNA for UWB receivers

    Science.gov (United States)

    Feihua, Chen; Lingyun, Li; Xinzhong, Duo; Tong, Tian; Xiaowei, Sun

    2011-02-01

    A CMOS variable gain low noise amplifier (LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13-μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1,1) less than -9 dB and S(2,2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.

  2. Performance of Very Small Robotic Fish Equipped with CMOS Camera

    Directory of Open Access Journals (Sweden)

    Yang Zhao

    2015-10-01

    Full Text Available Underwater robots are often used to investigate marine animals. Ideally, such robots should be in the shape of fish so that they can easily go unnoticed by aquatic animals. In addition, lacking a screw propeller, a robotic fish would be less likely to become entangled in algae and other plants. However, although such robots have been developed, their swimming speed is significantly lower than that of real fish. Since to carry out a survey of actual fish a robotic fish would be required to follow them, it is necessary to improve the performance of the propulsion system. In the present study, a small robotic fish (SAPPA was manufactured and its propulsive performance was evaluated. SAPPA was developed to swim in bodies of freshwater such as rivers, and was equipped with a small CMOS camera with a wide-angle lens in order to photograph live fish. The maximum swimming speed of the robot was determined to be 111 mm/s, and its turning radius was 125 mm. Its power consumption was as low as 1.82 W. During trials, SAPPA succeeded in recognizing a goldfish and capturing an image of it using its CMOS camera.

  3. A Low-Cost CMOS Programmable Temperature Switch

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2008-05-01

    Full Text Available A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  4. A Baseband Ultra-Low Noise SiGe:C BiCMOS 0.25 µm Amplifier And Its Application For An On-Chip Phase-Noise Measurement Circuit

    OpenAIRE

    Godet, Sylvain; Tournier, Éric; Llopis, Olivier; Cathelin, Andreia; Juyon, Julien

    2009-01-01

    4 pages; International audience; The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on-chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This ...

  5. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  6. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair

    Science.gov (United States)

    Chlis, Ilias

    2014-01-01

    This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity. PMID:24683340

  7. Comparative analyses of phase noise in 28 nm CMOS LC oscillator circuit topologies: Hartley, Colpitts, and common-source cross-coupled differential pair.

    Science.gov (United States)

    Chlis, Ilias; Pepe, Domenico; Zito, Domenico

    2014-01-01

    This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  8. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair

    Directory of Open Access Journals (Sweden)

    Ilias Chlis

    2014-01-01

    Full Text Available This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  9. Installation of a TCT set-up for characterization of novel HV-CMOS planar silicon sensors

    CERN Document Server

    Marx, Lisa

    2013-01-01

    For future upgrades of the LHC it is necessary to develop new tracking detectors: more radiation hard and cost efficient pixel detectors with high spacial resolution are required for the planned high luminosity version of the LHC (HL-LHC). For future tracking devices HV-CMOS active pixel sensors are great candidates since they fulfill all the demands mentioned above. First prototypes of these sensors are assembled on custom test boards and together with FE-I4 readout chips they make up the first test pixel detectors. One approach for testing these chips is through using lasers to induce electron-hole-pairs into the depletion zone of the sensor chip diodes to simulate an ionizing particle crossing through the bulk. Comparison measurements of irradiated/non-irradiated sensors are used to explore the radiation hardness of the sensors.

  10. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  11. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Havranek, Miroslav [University of Bonn, Bonn (Germany); Institute of Physics of the Academy of Sciences, Prague (Czech Republic)

    2015-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges coming from the higher hit rate will have to be solved by designing faster and more complex circuits, while at the same time keeping in mind very high radiation hardness requirements. Therefore matching the specification set by the high luminosity upgrade requires a large R and D effort. Our group is participating in such a joint development * namely the RD53 collaboration * which goal is to design a new pixel chip using an advanced 65 nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology will be shown together with a comparison with older technologies (130 nm, 250 nm). Most of the talk is allocated to presenting some of the circuits designed by our group, along with their performance measurement results.

  12. Noise characteristics of stacked CMOS active pixel sensor for charged particles

    Energy Technology Data Exchange (ETDEWEB)

    Kunihiro, Takuya E-mail: kunihiro@geo.titech.ac.jp; Nagashima, Kazuhide; Takayanagi, Isao; Nakamura, Junichi; Kosaka, Koji; Yurimoto, Hisayoshi

    2001-09-11

    The noise characteristics of a stacked CMOS active pixel sensor (SCAPS) for incident charged particles have been analyzed under 4.5 keV Si{sup +} ion irradiation. The source of SCAPS dark current was found to change from thermal to electron leakage with decreasing device temperature. Leakage current at charge integration part in a pixel has been reduced to 0.1 electrons s{sup -1} at 77 K. The incident ion signals are computed by subtracting reset frame values from each frame using a non-destructive readout operation. With increase of irradiated ions, the dominant noise source changed from read noise, and shot noise from the incident ions, to signal frame fixed-pattern noise from variations in sensitivity between pixels. Pixel read noise is equivalent to ten incident ions. The charge of an incident ion is converted to 1.5 electrons in the pixel capacitor. Shot noise corresponds to the statistical fluctuation of incident ions. Signal frame fixed-pattern noise is 0.7% of the signal. By comparing full well conditions to noise floor, a dynamic range of 80 dB is achieved. SCPAS is useful as a two-dimensional detector for microanalyses such as stigmatic secondary ion mass spectrometry.

  13. The research on binocular stereo video imaging and display system based on low-light CMOS

    Science.gov (United States)

    Xie, Ruobing; Li, Li; Jin, Weiqi; Guo, Hong

    2015-10-01

    It is prevalent for the low-light night-vision helmet to equip the binocular viewer with image intensifiers. Such equipment can not only acquire night vision ability, but also obtain the sense of stereo vision to achieve better perception and understanding of the visual field. However, since the image intensifier is for direct-observation, it is difficult to apply the modern image processing technology. As a result, developing digital video technology in night vision is of great significance. In this paper, we design a low-light night-vision helmet with digital imaging device. It consists of three parts: a set of two low-illumination CMOS cameras, a binocular OLED micro display and an image processing PCB. Stereopsis is achieved through the binocular OLED micro display. We choose Speed-Up Robust Feature (SURF) algorithm for image registration. Based on the image matching information and the cameras' calibration parameters, disparity can be calculated in real-time. We then elaborately derive the constraints of binocular stereo display. The sense of stereo vision can be obtained by dynamically adjusting the content of the binocular OLED micro display. There is sufficient space for function extensions in our system. The performance of this low-light night-vision helmet can be further enhanced in combination with The HDR technology and image fusion technology, etc.

  14. High-ratio voltage conversion in CMOS for efficient mains-connected standby

    CERN Document Server

    Meyvaert, Hans

    2016-01-01

    This book describes synergetic innovation opportunities offered by combining the field of power conversion with the field of integrated circuit (IC) design. The authors demonstrate how integrating circuits enables increased operation frequency, which can be exploited in power converters to reduce drastically the size of the discrete passive components. The authors introduce multiple power converter circuits, which are very compact as result of their high level of integration. First, the limits of high-power-density low-voltage monolithic switched-capacitor DC-DC conversion are investigated to enable on-chip power granularization. AC-DC conversion from the mains to a low voltage DC is discussed, enabling an efficient and compact, lower-power auxiliary power supply to take over the power delivery during the standby mode of mains-connected appliances, allowing the main power converter of these devices to be shut down fully. Discusses high-power-density monolithic switched-capacitor DC-DC conversion in bulk CMOS,...

  15. Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

    Directory of Open Access Journals (Sweden)

    M. Schleyer

    2017-09-01

    Full Text Available This paper reports on an effective root-cause analysis method of memory effects in power amplifiers, as well as introduces compensation techniques on a circuit design level. Despite conventional memory-effect approaches, the discussed method uses a two-tone scan over a wide operation and modulation range. This enables an in-depth study of physical causes and helps to implement compensation techniques at design stage. On the one hand, this circuit investigation is optimized using an automated SystemC model parametrized with real device and measurement values. Hence, computation time is widely reduced which shortens design cycles. On the other hand, the implementation of the derived circuit compensation means will reduce the complexity of digital pre-distortion due to a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach is demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a PAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be reduced by more than 8 %.

  16. Estimation of leakage power and delay in CMOS circuits using parametric variation

    Directory of Open Access Journals (Sweden)

    Preeti Verma

    2016-09-01

    Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

  17. An All-Solution-Based Hybrid CMOS-Like Quantum Dot/Carbon Nanotube Inverter.

    Science.gov (United States)

    Shulga, Artem G; Derenskyi, Vladimir; Salazar-Rios, Jorge Mario; Dirin, Dmitry N; Fritsch, Martin; Kovalenko, Maksym V; Scherf, Ullrich; Loi, Maria A

    2017-09-01

    The development of low-cost, flexible electronic devices is subordinated to the advancement in solution-based and low-temperature-processable semiconducting materials, such as colloidal quantum dots (QDs) and single-walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high-performance complementary metal-oxide-semiconductor (CMOS)-like inverters is demonstrated. The n-type field effect transistors (FETs) based on I(-) capped PbS QDs (Vth = 0.2 V, on/off = 10(5) , SS-th = 114 mV dec(-1) , µe = 0.22 cm(2) V(-1) s(-1) ) and the p-type FETs with tailored parameters based on low-density random network of SWCNTs (Vth = -0.2 V, on/off > 10(5) , SS-th = 63 mV dec(-1) , µh = 0.04 cm(2) V(-1) s(-1) ) are integrated on the same substrate in order to obtain high-performance hybrid inverters. The inverters operate in the sub-1 V range (0.9 V) and have high gain (76 V/V), large maximum-equal-criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV). © 2017 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. High aspect ratio sharp nanotip for nanocantilever integration at CMOS compatible temperature

    Science.gov (United States)

    Wang, P.; Michael, A.; Kwok, CY

    2017-08-01

    In this paper, we demonstrate a novel low temperature nanofabrication approach that enables the formation of ultra-sharp high aspect ratio (HAR) and high density nanotip structures and their integration onto nanoscale cantilever beams. The nanotip structure consists of a nanoscale thermally evaporated Cr Spindt tip on top of an amorphous silicon rod. An apex radius of the tip, as small as 2.5 nm, has been achieved, and is significantly smaller than any other Spindt tips reported so far. 100 nm wide tips with aspect ratio of more than 50 and tip density of more than 5 × 109 tips cm-2 have been fabricated. The HAR tips have been integrated onto an array of 460 nm wide cantilever beams with high precision and yield. In comparison with other approaches, this approach allows the integration of HAR sharp nanotips with nano-mechanical structures in a parallel and CMOS compatible fashion for the first time to our knowledge. Potential applications include on-chip high-speed atomic force microscopy and field emission devices.

  19. Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

    Science.gov (United States)

    Schleyer, Martin; Maurath, Dominic; Klar, Heinrich; Gerfers, Friedel

    2017-09-01

    This paper reports on an effective root-cause analysis method of memory effects in power amplifiers, as well as introduces compensation techniques on a circuit design level. Despite conventional memory-effect approaches, the discussed method uses a two-tone scan over a wide operation and modulation range. This enables an in-depth study of physical causes and helps to implement compensation techniques at design stage. On the one hand, this circuit investigation is optimized using an automated SystemC model parametrized with real device and measurement values. Hence, computation time is widely reduced which shortens design cycles. On the other hand, the implementation of the derived circuit compensation means will reduce the complexity of digital pre-distortion due to a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach is demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a PAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be reduced by more than 8 %.

  20. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.