WorldWideScience

Sample records for radiation-hardened cmos devices

  1. Radiation-hardened bulk CMOS technology

    International Nuclear Information System (INIS)

    Dawes, W.R. Jr.; Habing, D.H.

    1979-01-01

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  2. Radiation-hardened bulk Si-gate CMOS microprocessor family

    International Nuclear Information System (INIS)

    Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

    1979-01-01

    RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

  3. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  4. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  5. Process controls for radiation hardened aluminum gate bulk silicon CMOS

    International Nuclear Information System (INIS)

    Gregory, B.L.

    1975-01-01

    Optimized dry oxides have recently yielded notable improvements in CMOS radiation-hardness. By following the proper procedures and recipes, it is now possible to produce devices which will function satisfactorily after exposure to a total ionizing dose in excess of 10 6 RADS (Si). This paper is concerned with the controls required on processing parameters once the optimized process is defined. In this process, the pre-irradiation electrical parameters must be closely controlled to insure that devices will function after irradiation. In particular, the specifications on n- and p-channel threshold voltages require tight control of fixed oxide charge, surface-state density, oxide thickness, and substrate and p-well surface concentrations. In order to achieve the above level of radiation hardness, certain processing procedures and parameters must also be closely controlled. Higher levels of cleanliness are required in the hardened process than are commonly required for commercial CMOS since, for hardened dry oxides, no impurity gettering can be employed during or after oxidation. Without such gettering, an unclean oxide is unacceptable due to bias-temperature instability. Correct pre-oxidation cleaning, residual surface damage removal, proper oxidation and annealing temperatures and times, and the correct metal sintering cycle are all important in determining device hardness. In a reproducible, hardened process, each of these processing steps must be closely controlled. (U.S.)

  6. Radiation-hardened CMOS/SOS LSI circuits

    International Nuclear Information System (INIS)

    Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.

    1976-01-01

    The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology

  7. Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs

    International Nuclear Information System (INIS)

    Abare, W.E.; Huffman, D.D.; Moffett, G.E.

    1982-01-01

    This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented

  8. Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

    International Nuclear Information System (INIS)

    Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

    1984-01-01

    The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

  9. Using a novel spectroscopic reflectometer to optimize a radiation-hardened submicron silicon-on-sapphire CMOS process

    International Nuclear Information System (INIS)

    Do, N.T.; Zawaideh, E.; Vu, T.Q.; Warren, G.; Mead, D.; Do, N.T.; Li, G.P.; Tsai, C.S.

    1999-01-01

    A radiation-hardened sub-micron silicon-on-sapphire CMOS process is monitored and optimized using a novel optical technique based on spectroscopic reflectometry. Quantitative measurements of the crystal quality, surface roughness, and device radiation hardness show excellent correlation between this technique and the Atomic Force Microscopy. (authors)

  10. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  11. Using a novel spectroscopic reflectometer to optimize a radiation-hardened submicron silicon-on-sapphire CMOS process; Utilisation d'une nouvelle reflectometrie spectroscopique pour optimiser un procede de fabrication CMOS/SOS durci aux radiations

    Energy Technology Data Exchange (ETDEWEB)

    Do, N.T.; Zawaideh, E.; Vu, T.Q.; Warren, G.; Mead, D. [Raytheon Systems company, Microelectronics Div., Newport Beach, California (United States); Li, G.P.; Tsai, C.S. [California Univ., School of Engineering, Newport Beach, CA (United States)

    1999-07-01

    A radiation-hardened sub-micron silicon-on-sapphire CMOS process is monitored and optimized using a novel optical technique based on spectroscopic reflectometry. Quantitative measurements of the crystal quality, surface roughness, and device radiation hardness show excellent correlation between this technique and the Atomic Force Microscopy. (authors)

  12. Radiation hardening of CMOS-based circuitry in SMART transmitters

    International Nuclear Information System (INIS)

    Loescher, D.H.

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term ''SMART'' denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection

  13. CMOS/SOS 4k Rams hardened to 100 Krads (s:)

    International Nuclear Information System (INIS)

    Napoli, L.S.; Heagerty, W.F.; Smeltzer, R.K.; Yeh, J.L.

    1982-01-01

    Two CMOS/SOS 4K memories were fabricated with a recently developed, hardened SOS process. Memory functionality after radiation doses well in excess of 100 Krads(Si) was demonstrated. The critical device processing steps were identified. The radiationinduced failure mode of the memories is understood in terms of the circuit organization and the radiation behavior of the individual transistors in the memories

  14. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  15. Radiation-hardened nonvolatile MNOS RAM

    International Nuclear Information System (INIS)

    Wrobel, T.F.; Dodson, W.H.; Hash, G.L.; Jones, R.V.; Nasby, R.D.; Olson, R.J.

    1983-01-01

    A radiation hardened nonvolatile MNOS RAM is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s

  16. Radiation hardening of integrated circuits technologies

    International Nuclear Information System (INIS)

    Auberton-Herve, A.J.; Leray, J.L.

    1991-01-01

    The radiation hardening studies started in the mid decade -1960-1970. To survive the different military or space radiative environment, a new engineering science borned, to understand the degradation of electronics components. The different solutions to improve the electronic behavior in such environment, have been named radiation hardening of the technologies. Improvement of existing technologies, and qualification method have been widely studied. However, at the other hand, specific technologies was developped : The Silicon On Insulator technologies for CMOS or Bipolar. The HSOI3HD technology (supported by DGA-CEA DAM and LETI with THOMSON TMS) offers today the highest hardening level for the integration density of hundreds of thousand transistors on the same silicon. Full complex systems would be realized on a single die with a technological radiation hardening and no more system hardening

  17. Custom high-reliability radiation-hard CMOS-LSI circuit design

    International Nuclear Information System (INIS)

    Barnard, W.J.

    1981-01-01

    Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

  18. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

    International Nuclear Information System (INIS)

    Bonacini, S.

    2007-11-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

  19. Radiation hardening of MOS devices by boron

    International Nuclear Information System (INIS)

    Danchenko, V.

    1975-01-01

    A novel technique is disclosed for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device of the type having a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. In the preferred embodiment, the novel inventive technique contemplates the introduction of boron into the insulating oxide, the boron being introduced within a layer of the oxide of about 100A to 300A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 atoms/ cm 3 . The novel technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations, which accumulations, if not eliminated, would cause shifting of the gate threshold potential of a radiation subjected MOS device, and thus render the device unstable and/or inoperative. (auth)

  20. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  1. Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

    International Nuclear Information System (INIS)

    Lee, Min Su; Lee, Hee Chul

    2012-01-01

    To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

  2. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Hughes, R.C.

    1977-01-01

    Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

  3. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    Energy Technology Data Exchange (ETDEWEB)

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  4. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

    International Nuclear Information System (INIS)

    Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

  5. Radiation hardened COTS-based 32-bit microprocessor

    International Nuclear Information System (INIS)

    Haddad, N.; Brown, R.; Cronauer, T.; Phan, H.

    1999-01-01

    A high performance radiation hardened 32-bit RISC microprocessor based upon a commercial single chip CPU has been developed. This paper presents the features of radiation hardened microprocessor, the methods used to radiation harden this device, the results of radiation testing, and shows that the RAD6000 is well-suited for the vast majority of space applications. (authors)

  6. Characterization of Radiation Hardened Bipolar Linear Devices for High Total Dose Missions

    Science.gov (United States)

    McClure, Steven S.; Harris, Richard D.; Rax, Bernard G.; Thorbourn, Dennis O.

    2012-01-01

    Radiation hardened linear devices are characterized for performance in combined total dose and displacement damage environments for a mission scenario with a high radiation level. Performance at low and high dose rate for both biased and unbiased conditions is compared and the impact to hardness assurance methodology is discussed.

  7. Novel circuits for radiation hardened memories

    International Nuclear Information System (INIS)

    Haraszti, T.P.; Mento, R.P.; Moyer, N.E.; Grant, W.M.

    1992-01-01

    This paper reports on implementation of large storage semiconductor memories which combine radiation hardness with high packing density, operational speed, and low power dissipation and require both hardened circuit and hardened process technologies. Novel circuits, including orthogonal shuffle type of write-read arrays, error correction by weighted bidirectional codes and associative iterative repair circuits, are proposed for significant improvements of SRAMs' immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mbit and 10-Mbit monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrad and a projected SEU rate of 1 x 10 - 12 error/bit/day. Using radiation hardened processing improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate

  8. Multi-MGy Radiation Hardened Camera for Nuclear Facilities

    International Nuclear Information System (INIS)

    Girard, Sylvain; Boukenter, Aziz; Ouerdane, Youcef; Goiffon, Vincent; Corbiere, Franck; Rolando, Sebastien; Molina, Romain; Estribeau, Magali; Avon, Barbara; Magnan, Pierre; Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Raine, Melanie

    2015-01-01

    There is an increasing interest in developing cameras for surveillance systems to monitor nuclear facilities or nuclear waste storages. Particularly, for today's and the next generation of nuclear facilities increasing safety requirements consecutive to Fukushima Daiichi's disaster have to be considered. For some applications, radiation tolerance needs to overcome doses in the MGy(SiO 2 ) range whereas the most tolerant commercial or prototypes products based on solid state image sensors withstand doses up to few kGy. The objective of this work is to present the radiation hardening strategy developed by our research groups to enhance the tolerance to ionizing radiations of the various subparts of these imaging systems by working simultaneously at the component and system design levels. Developing radiation-hardened camera implies to combine several radiation-hardening strategies. In our case, we decided not to use the simplest one, the shielding approach. This approach is efficient but limits the camera miniaturization and is not compatible with its future integration in remote-handling or robotic systems. Then, the hardening-by-component strategy appears mandatory to avoid the failure of one of the camera subparts at doses lower than the MGy. Concerning the image sensor itself, the used technology is a CMOS Image Sensor (CIS) designed by ISAE team with custom pixel designs used to mitigate the total ionizing dose (TID) effects that occur well below the MGy range in classical image sensors (e.g. Charge Coupled Devices (CCD), Charge Injection Devices (CID) and classical Active Pixel Sensors (APS)), such as the complete loss of functionality, the dark current increase and the gain drop. We'll present at the conference a comparative study between these radiation-hardened pixel radiation responses with respect to conventional ones, demonstrating the efficiency of the choices made. The targeted strategy to develop the complete radiation hard camera

  9. Multi-MGy Radiation Hardened Camera for Nuclear Facilities

    Energy Technology Data Exchange (ETDEWEB)

    Girard, Sylvain; Boukenter, Aziz; Ouerdane, Youcef [Universite de Saint-Etienne, Lab. Hubert Curien, UMR-CNRS 5516, F-42000 Saint-Etienne (France); Goiffon, Vincent; Corbiere, Franck; Rolando, Sebastien; Molina, Romain; Estribeau, Magali; Avon, Barbara; Magnan, Pierre [ISAE, Universite de Toulouse, F-31055 Toulouse (France); Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Raine, Melanie [CEA, DAM, DIF, F-91297 Arpajon (France)

    2015-07-01

    There is an increasing interest in developing cameras for surveillance systems to monitor nuclear facilities or nuclear waste storages. Particularly, for today's and the next generation of nuclear facilities increasing safety requirements consecutive to Fukushima Daiichi's disaster have to be considered. For some applications, radiation tolerance needs to overcome doses in the MGy(SiO{sub 2}) range whereas the most tolerant commercial or prototypes products based on solid state image sensors withstand doses up to few kGy. The objective of this work is to present the radiation hardening strategy developed by our research groups to enhance the tolerance to ionizing radiations of the various subparts of these imaging systems by working simultaneously at the component and system design levels. Developing radiation-hardened camera implies to combine several radiation-hardening strategies. In our case, we decided not to use the simplest one, the shielding approach. This approach is efficient but limits the camera miniaturization and is not compatible with its future integration in remote-handling or robotic systems. Then, the hardening-by-component strategy appears mandatory to avoid the failure of one of the camera subparts at doses lower than the MGy. Concerning the image sensor itself, the used technology is a CMOS Image Sensor (CIS) designed by ISAE team with custom pixel designs used to mitigate the total ionizing dose (TID) effects that occur well below the MGy range in classical image sensors (e.g. Charge Coupled Devices (CCD), Charge Injection Devices (CID) and classical Active Pixel Sensors (APS)), such as the complete loss of functionality, the dark current increase and the gain drop. We'll present at the conference a comparative study between these radiation-hardened pixel radiation responses with respect to conventional ones, demonstrating the efficiency of the choices made. The targeted strategy to develop the complete radiation hard camera

  10. A Novel Radiation Hardened CAM

    CERN Document Server

    Shojaii, Seyed Ruhollah; The ATLAS collaboration

    2018-01-01

    This poster describes an innovative Content Addressable Memory cell with radiation hardened (RH-CAM) architecture. The RH-CAM is designed in a commercial 28 nm CMOS technology. The circuit has been simulated in worst-case conditions, and the effects due to single particles are analyzed injecting a fault current into a circuit node. The proposed architecture can perform on-time pattern recognition tasks in harsh environments, such as very front-end electronics in hadron colliders and in space applications.

  11. Hardening device, by inserts, of electronic component against radiation

    International Nuclear Information System (INIS)

    Val, C.

    1987-01-01

    The hardening device includes at least two materials, one with high atomic number with respect to the other. One of these materials is set as inserts in a layer of the other material. The hardening device is then made by stacking of such layers, the insert density varying from one layer to the other, making thus vary the atomic number resulting from the hardening device along its thickness, following a predefined law [fr

  12. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  13. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  14. Radiation hardening of smart electronics

    International Nuclear Information System (INIS)

    Mayo, C.W.; Cain, V.R.; Marks, K.A.; Millward, D.G.

    1991-02-01

    Microprocessor based ''smart'' pressure, level, and flow transmitters were tested to determine the radiation hardness of this class of electronic instrumentation for use in reactor building applications. Commercial grade Complementary Metal Oxide Semiconductor (CMOS) integrated circuits used in these transmitters were found to fail at total gamma dose levels between 2500 and 10,000 rad. This results in an unacceptably short lifetime in many reactor building radiation environments. Radiation hardened integrated circuits can, in general, provide satisfactory service life for normal reactor operations when not restricted to the extremely low power budget imposed by standard 4--20 mA two-wire instrument loops. The design of these circuits will require attention to vendor radiation hardness specifications, dose rates, process control with respect to radiation hardness factors, and non-volatile programmable memory technology. 3 refs., 2 figs

  15. An Innovative Radiation Hardened CAM Architecture

    CERN Document Server

    Shojaii, Seyed Ruhollah; The ATLAS collaboration

    2018-01-01

    This article describes an innovative Content Addressable Memory (CAM) cell with radiation hardened (RH) architecture. The RH-CAM is designed in a commercial 28 nm CMOS technology. The circuit has been simulated in worst-case conditions, and the effects due to single particles have been analyzed by injecting a current pulse into a circuit node. The proposed architecture is suitable for on-time pattern recognition tasks in harsh environments, such as front-end electronics in hadron colliders and in space applications.

  16. An improved standard total dose test for CMOS space electronics

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Winokur, P.S.; Riewe, L.C.; Pease, R.L.

    1989-01-01

    The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at ≅ 200 rad(SiO 2 )/s followed by a 1-week 100 degrees C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space surviability of CMOS circuits: a Co-60 irradiation and test to screen against oxide-trapped charge related failures, and an additional rebound test to screen against interface-trap related failures. Testing implications for bipolar technologies are also discussed

  17. E-Beam Effects on CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

    2011-01-01

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  18. Radiation sensitivity of integrated circuits Pt. 1

    International Nuclear Information System (INIS)

    Bereczkine Kerenyi, Ilona

    1986-01-01

    The cosmic ray sensitivity of CMOS integrated circuits are overviewed in three parts. The aim is to analyze the effects of ionizing radiation on the degradation of electronic parameters, the effects of the electric state during irradiation, and the radiation hardening of ICs. In this Part 1 a general introduction of the response of semiconductors to cosmic radiation is given, and the radiation tolerance and hardening of small-scale integrated CMOS ICs is analyzed in detail. The devices include various basic inverters and simple gate ICs. (R.P.)

  19. Challenges in hardening technologies using shallow-trench isolation

    International Nuclear Information System (INIS)

    Shaneyfelt, M.R.; Dodd, P.E.; Draper, B.L.; Flores, R.S.

    1998-02-01

    Challenges related to radiation hardening CMOS technologies with shallow-trench isolation are explored. Results show that trench hardening can be more difficult than simply replacing the trench isolation oxide with a hardened field oxide

  20. A comparison of ionizing radiation damage in CMOS devices from 60Co gamma rays, electrons and protons

    International Nuclear Information System (INIS)

    He Baoping; Yao Zhibin; Zhang Fengqi

    2009-01-01

    Radiation hardened CC4007RH and non-radiation hardened CC4011 devices were irradiated using 60 Co gamma rays, 1 MeV electrons and 1-9 MeV protons to compare the ionizing radiation damage of the gamma rays with the charged particles. For all devices examined, with experimental uncertainty, the radiation induced threshold voltage shifts (ΔV th ) generated by 60 Co gamma rays are equal to that of 1 MeV electron and 1-7 MeV proton radiation under 0 gate bias condition. Under 5 V gate bias condition, the distinction of threshold voltage shifts (ΔV th ) generated by 60 Co gamma rays and 1 MeV electrons irradiation are not large, and the radiation damage for protons below 9 MeV is always less than that of 60 Co gamma rays. The lower energy the proton has, the less serious the radiation damage becomes. (authors)

  1. Exploration of a radiation hardening stabilized voltage power supply

    International Nuclear Information System (INIS)

    Xie Zeyuan; Xu Xianguo

    2014-01-01

    This paper mainly introduces the design method of radiation hardening stabilized voltage power supply that makes use of commercial radiation resistant electronic devices and the test results of radiation performance of the power supply and devices are presented in detail. The experiment results show that the hardened power supply can normally work until 1000 Gy (Si) total dose and 1 × 10 14 n/cm 2 neutron radiation, and it doesn't latchup at about 1 × l0 9 Gy (Si)/s gamma transient dose rate. (authors)

  2. Two transistor cluster DICE Cells with the minimum area for a hardened 28-nm CMOS and 65-nm SRAM layout design

    International Nuclear Information System (INIS)

    Stenin, V.Ya.; Stepanov, P.V.

    2015-01-01

    A hardened DICE cell layout design is based on the two spaced transistor clusters of the DICE cell each consisting of four transistors. The larger the distance between these two CMOS transistor clusters, the more robust the hardened DICE SRAM to Single Event Upsets. Some versions of the 28-nm and 65-nm DICE CMOS SRAM block composition have been suggested with minimum cluster distances of 2.27-2.32 mkm. The area of hardened 28-nm DICE CMOS cells is larger than the area of 28-nm 6T CMOS cells by a factor of 2.1 [ru

  3. Non-destructive screening method for radiation hardened performance of large scale integration

    International Nuclear Information System (INIS)

    Zhou Dong; Xi Shanbin; Guo Qi; Ren Diyuan; Li Yudong; Sun Jing; Wen Lin

    2013-01-01

    The space radiation environment could induce radiation damage on the electronic devices. As the performance of commercial devices is generally superior to that of radiation hardened devices, it is necessary to screen out the devices with good radiation hardened performance from the commercial devices and applying these devices to space systems could improve the reliability of the systems. Combining the mathematical regression analysis with the different physical stressing experiments, we investigated the non-destructive screening method for radiation hardened performance of the integrated circuit. The relationship between the change of typical parameters and the radiation performance of the circuit was discussed. The irradiation-sensitive parameters were confirmed. The pluralistic linear regression equation toward the prediction of the radiation performance was established. Finally, the regression equations under stress conditions were verified by practical irradiation. The results show that the reliability and accuracy of the non-destructive screening method can be elevated by combining the mathematical regression analysis with the practical stressing experiment. (authors)

  4. Radiation-hardened control system

    International Nuclear Information System (INIS)

    Vandermolen, R.I.; Smith, S.F.; Emery, M.S.

    1993-01-01

    A radiation-hardened bit-slice control system with associated input/output circuits was developed to prove that programmable circuits could be constructed to successfully implement intelligent functions in a highly radioactive environment. The goal for this effort was to design and test a programmable control system that could withstand a minimum total dose of 10 7 rads (gamma). The Radiation Hardened Control System (RHCS) was tested in operation at a dose rate that ranged up to 135 krad/h, with an average total dose of 10.75 Mrads. Further testing beyond the required 10 7 rads was also conducted. RHCS performed properly through the target dose of 10 7 rads, and sporadic intermittent failures in some programmable logic devices were noted after ∼ 13 Mrads

  5. Radiation-hardenable diluents for radiation-hardenable compositions

    International Nuclear Information System (INIS)

    Schuster, K.E.; Rosenkranz, H.J.; Furh, K.; Ruedolph, H.

    1979-01-01

    Radiation-crosslinkable diluents for radiation-hardenable compositions (binders) consisting of a mixture of triacrylates of a reaction product of trimethylol propane and ethylene oxide with an average degree of ethoxylation of from 2.5 to 4 are described. The ethoxylated trimethylol propane is substantially free from trimethylol propane and has the following distribution: 4 to 5% by weight of monoethoxylation product, 14 to 16% by weight of diethoxylation product, 20 to 30% by weight of triethoxylation product, 20 to 30% by weight of tetraethoxylation product, 16 to 18% by weight of pentaethoxylation product, and 6 to 8% by weight of hexaethoxylation product. The diluents effectively reduce the viscosity of radiation-hardenable compositions and do not have any adverse effect upon their reactivity or upon the properties of the resulting hardened products

  6. Future challenges in single event effects for advanced CMOS technologies

    International Nuclear Information System (INIS)

    Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

    2010-01-01

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  7. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  8. Radiation-hard silicon gate bulk CMOS cell family

    International Nuclear Information System (INIS)

    Gibbon, C.F.; Habing, D.H.; Flores, R.S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved

  9. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  10. Superconducting (radiation hardened) magnets for mirror fusion devices

    International Nuclear Information System (INIS)

    Henning, C.D.; Dalder, E.N.C.; Miller, J.R.; Perkins, J.R.

    1983-01-01

    Superconducting magnets for mirror fusion have evolved considerably since the Baseball II magnet in 1970. Recently, the Mirror Fusion Test Facility (MFTF-B) yin-yang has been tested to a full field of 7.7 T with radial dimensions representative of a full scale reactor. Now the emphasis has turned to the manufacture of very high field solenoids (choke coils) that are placed between the tandem mirror central cell and the yin-yang anchor-plug set. For MFTF-B the choke coil field reaches 12 T, while in future devices like the MFTF-Upgrade, Fusion Power Demonstration and Mirror Advanced Reactor Study (MARS) reactor the fields are doubled. Besides developing high fields, the magnets must be radiation hardened. Otherwise, thick neutron shields increase the magnet size to an unacceptable weight and cost. Neutron fluences in superconducting magnets must be increased by an order of magnitude or more. Insulators must withstand 10 10 to 10 11 rads, while magnet stability must be retained after the copper has been exposed to fluence above 10 19 neutrons/cm 2

  11. Principles and techniques of radiation hardening. Volume 2. Transient radiation effects in electronics (TREE)

    International Nuclear Information System (INIS)

    Rudie, N.J.

    1976-01-01

    The three-volume book is intended to serve as a review of the effects of thermonuclear explosion induced radiation (x-rays, gamma rays, and beta particles) and the resulting electromagnetic pulse (EMP). Volume 2 deals with the following topics: radiation effects on quartz crystals, tantalum capacitors, bipolar semiconductor devices and integrated circuits, field effect transistors, and miscellaneous electronic devices; hardening electronic systems to photon and neutron radiation; nuclear radiation source and/or effects simulation techniques; and radiation dosimetry

  12. Radiation-hardened micro-electronics for nuclear instrumentation

    International Nuclear Information System (INIS)

    Van Uffelen, M.

    2007-01-01

    The successful development and deployment of future fission and thermonuclear fusion reactors depends to a large extent on the advances of different enabling technologies. Not only the materials need to be custom engineered but also the instrumentation, the electronics and the communication equipment need to support operation in this harsh environment, with expected radiation levels during maintenance up to several MGy. Indeed, there are yet no commercially available electronic devices available off-the-shelf which demonstrated a satisfying operation at these extremely high radiation levels. The main goal of this task is to identify commercially available radiation tolerant technologies, and to design dedicated and integrated electronic circuits, using radiation hardening techniques, both at the topological and architectural level. Within a stepwise approach, we first design circuits with discrete components and look for an equivalent integrated technology. This will enable us to develop innovative instrumentation and communication tools for the next generation of nuclear reactors, where both radiation hardening and miniaturization play a dominant role

  13. SEU testing of a novel hardened register implemented using standard CMOS technology

    International Nuclear Information System (INIS)

    Monnier, T.; Roche, F.M.; Cosculluela, J.; Velazco, R.

    1999-01-01

    A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron nonradiation hardened CMOS technology. This paper presents the results of heavy ions tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact to die real estate, write time, or power consumption

  14. Radiation effects in optoelectronic devices

    International Nuclear Information System (INIS)

    Barnes, C.E.

    1977-03-01

    A summary is given of studies on radiation effects in light-emitting diodes, laser diodes, detectors, optical isolators and optical fibers. It is shown that the study of radiation damage in these devices can provide valuable information concerning the nature of the devices themselves, as well as methods of hardening these devices for applications in radiation environments

  15. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    Science.gov (United States)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  16. First result on biased CMOS MAPs-on-diamond devices

    Energy Technology Data Exchange (ETDEWEB)

    Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  17. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  18. Radiation response of high speed CMOS integrated circuits

    International Nuclear Information System (INIS)

    Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

  19. Radiation effects on radiation-hardened KU and KS-4V optical fibres

    International Nuclear Information System (INIS)

    Ivanov, A.A.; Tugarinov, S.N.; Kaschuck, Y.A.; Krasilnikov, A.V.; Bender, S.E.

    1999-01-01

    The aim of this work was to test the un-pretreated and the hardened (H 2 -loaded and pre-irradiated) KS-4V and KU optical fibres in reactor environment by in-situ measurements of both the radiation-induced loss and the luminescence in the visible spectral region. Both the radio-luminescent and the transmission spectra were in-situ detected during irradiation by charge-coupled-device (CCD) linear detector in the visible spectral region of 400 to 700 nm. The radiation induced loss spectra at the fast neutron fluence of 2*10 6 n/cm 2 shows the hardened, H 2 -loading and pre-irradiating effects in the both KU and KS-4V fibres. KU un-pretreated fibre shows a big radiation absorption band of non-bridging oxygen centered at the wavelength of 630 nm. It appears that the KS-4V hardened fibre has a specific point in the loss spectrum in the vicinity of 460 nm. Other measurements were performed, particularly after reactor shutdown and at 3 different neutron fluences with constant neutron flux after restarting

  20. An investigation of medical radiation detection using CMOS image sensors in smartphones

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Han Gyu [Department of Senior Healthcare, Graduate School of Eulji University, Daejeon 301-746 (Korea, Republic of); Song, Jae-Jun [Department of Otorhinolaryngology-Head & Neck Surgery, Korea University, Guro Hospital,148, Gurodong-ro, Guro-gu, Seoul 152-703 (Korea, Republic of); Lee, Kwonhee [Graduate Program in Bio-medical Science, Korea University, 2511 Sejong-ro, Sejong City 339-770 (Korea, Republic of); Nam, Ki Chang [Department of Medical Engineering, College of Medicine, Dongguk University, 32 Dongguk-ro, Goyang-si, Gyeonggi-do 410-820 (Korea, Republic of); Hong, Seong Jong; Kim, Ho Chul [Department of Radiological Science, Eulji University, 553 Yangji-dong, Sujeong-gu, Seongnam-si, Gyeonggi-do 431-713 (Korea, Republic of)

    2016-07-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  1. An investigation of medical radiation detection using CMOS image sensors in smartphones

    International Nuclear Information System (INIS)

    Kang, Han Gyu; Song, Jae-Jun; Lee, Kwonhee; Nam, Ki Chang; Hong, Seong Jong; Kim, Ho Chul

    2016-01-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  2. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

    Institute of Scientific and Technical Information of China (English)

    Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

    2012-01-01

    Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

  3. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  4. Characterisation of a CMOS charge transfer device for TDI imaging

    International Nuclear Information System (INIS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-01-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques

  5. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1983-09-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

  6. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1984-01-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

  7. Radiation effects in LDD MOS devices

    International Nuclear Information System (INIS)

    Woodruff, R.L.; Adams, J.R.

    1987-01-01

    The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined that the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10 6 rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10 6 rads(Si), and shows promise for achieving 1.0 x 10 7 rad(Si) total-dose capability

  8. Design and implementation of a programming circuit in radiation-hardened FPGA

    International Nuclear Information System (INIS)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

  9. Design and implementation of a programming circuit in radiation-hardened FPGA

    Science.gov (United States)

    Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

    2011-08-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  10. Study of hard X-ray dose enhancement effects for some kinds of semiconductor devices

    CERN Document Server

    Guo Hong Xia; Chen Yu Sheng; Zhou Hui; He Chao Hui; Xie Ya Ning; Huang Yu Ying; He Wei; Hu Tian Dou

    2002-01-01

    Experimental results of X-ray dose enhancement effects are given for CMOS4069 and floating gate ROMs irradiated in Beijing Synchrotron Radiation Facility and in cobalt source. Shift of threshold voltage vs. total dose for CMOS4069 and the errors vs. total dose for 28f256 and 29c256 have been tested on line and the equivalent relation of total dose damage under the same accumulated dose is provided comparing the response of devices irradiated by X-ray and gamma-ray source. These results can be provided for X-ray radiation hardening technology as an effective evaluation data

  11. Radiation hardenable coating mixture

    International Nuclear Information System (INIS)

    Howard, D.D.

    1977-01-01

    This invention relates to coatings that harden under radiation and to their compositions. Specifically, this invention concerns unsaturated urethane resins polymerisable by addition and to compositions, hardening under the effect of radiation, containing these resins. These resins feature the presence of at least one unsaturated ethylenic terminal group of structure CH 2 =C and containing the product of the reaction of an organic isocyanate compound with at least two isocyanate groups and one polyester polyol with at least two hydroxyl groups, and one unsaturated monomer compound polymerisable by addition having a single active hydrogen group reacting with the isocyanate [fr

  12. Radiation-chemical hardening of phenol-formaldehyde oligomers

    International Nuclear Information System (INIS)

    Shlapatskaya, V.V.; Omel'chenko, S.I.

    1978-01-01

    Radiation-chemical hardening of phenol formaldehyde oligomers of the resol type has been studied in the presence of furfural and diallylphthalate diluents. The samples have been hardened on an electron accelerator at an electron energy of 1.0-1.1 MeV and a dose rate of 2-3 Mrad/s. The kinetics of hardening has been studied on the yield of gel fraction within the range of absorbed doses from 7 to 400 Mrad. Radiation-chemical hardening of the studied compositions is activated with sensitizers, namely, amines, metal chlorides, and heterocyclic derivatives of metals. Furfural and diallylphthalate compositions are suitable for forming glass-fibre plastic items by the wet method and coatings under the action of ionizing radiations

  13. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  14. Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

    Science.gov (United States)

    Zand, Ramtin; DeMara, Ronald F.

    2017-12-01

    In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

  15. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    Venuto, D. de; Corsi, F.; Ohletz, M.J.

    1999-01-01

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  16. Radiation effects in advanced microelectronics technologies

    Science.gov (United States)

    Johnston, A. H.

    1998-06-01

    The pace of device scaling has increased rapidly in recent years. Experimental CMOS devices have been produced with feature sizes below 0.1 /spl mu/m, demonstrating that devices with feature sizes between 0.1 and 0.25 /spl mu/m will likely be available in mainstream technologies after the year 2000. This paper discusses how the anticipated changes in device dimensions and design are likely to affect their radiation response in space environments. Traditional problems, such as total dose effects, SEU and latchup are discussed, along with new phenomena. The latter include hard errors from heavy ions (microdose and gate-rupture errors), and complex failure modes related to advanced circuit architecture. The main focus of the paper is on commercial devices, which are displacing hardened device technologies in many space applications. However, the impact of device scaling on hardened devices is also discussed.

  17. Effects of radiation on MOS structures and silicon devices

    International Nuclear Information System (INIS)

    Braeunig, D.; Fahrner, W.

    1983-02-01

    A comprehensive view of radiation effects on MOS structures and silicon devices is given. In the introduction, the interaction of radiation with semiconductor material is presented. In the next section, the electrical degradation of semiconductor devices due to this interaction is discussed. The commonly used hardening techniques are shown. The last section deals with testing of radiation hardness of devices. (orig.) [de

  18. Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

    International Nuclear Information System (INIS)

    Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

    2010-01-01

    The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

  19. Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

    International Nuclear Information System (INIS)

    Holland, S.

    1991-11-01

    A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

  20. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  1. Thermomechanical properties of radiation hardened oligoesteracrylates

    International Nuclear Information System (INIS)

    Lomonosova, N.V.; Chikin, Yu.A.

    1984-01-01

    Thermomechanical properties of radiation hardened oligoesteracrylates are studied by the methods of isothermal heating and thermal mechanics. Films of dimethacrylate of ethylene glycol, triethylene glycol (TGM-3), tetraethylene glycol, tridecaethylene glycol and TGM-3 mixture with methyl methacrylate hardened by different doses (5-150 kGy) using Co 60 installation with a dose rate of 2x10 -3 kGy/s served as a subject of the research. During oligoesteracrylate hargening a space network is formed, chain sections between lattice points of which are in a stressed state. Maximum of deformation is observed at 210-220 deg C on thermomechanical curves of samples hardened by doses > 5 kGy, which form and intensity is dependent on an absorbed dose. Presence of a high-temperature maximum on diaqrams of isometric heating of spatially cross-linked oligoesteracrylates is discovered. High thermal stability of three-dimensional network of radiation hardened oligoesteracrylates provides satisfactory tensile properties (40% of initial strength) in sample testing an elevated temperatures (200-250 deg C)

  2. Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

    CERN Document Server

    Huffman, B T; Arndt, K; Bates, R; Benoit, M; Di Bello, F; Blue, A; Bortoletto, D; Buckland, M; Buttar, C; Caragiulo, P; Das, D; Dopke, J; Dragone, A; Ehrler, F; Fadeyev, V; Galloway, Z; Grabas, H; Gregor, I M; Grenier, P; Grillo, A; Hoeferkamp, M; Hommels, L B A; John, J; Kanisauskas, K; Kenney, C; Kramberger, J; Liang, Z; Mandic, I; Maneuski, D; Martinez-McKinney, F; McMahon, S; Meng, L; Mikuž, M; Muenstermann, D; Nickerson, R; Peric, I; Phillips, P; Plackett, R; Rubbo, F; Segal, J; Seidel, S; Seiden, A; Shipsey, I; Song, W; Stanitzki, M; Su, D; Tamma, C; Turchetta, R; Vigani, L; olk, J; Wang, R; Warren, M; Wilson, F; Worm, S; Xiu, Q; Zhang, J; Zhu, H

    2016-01-01

    The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with theAMSH35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

  3. SEU-hardened design for shift register in CMOS APS

    International Nuclear Information System (INIS)

    Meng Liya; Liu Zedong; Hu Dajiang; Wang Qingxiang

    2012-01-01

    The inverter-based quasi-static shift register in CMOS APS, which is used in ionizing radiation environment, is susceptible to single event upset (SEU), thus affecting the CMOS active pixel sensor (APS) working. The analysis of the SEU for inverter-based quasi-static shift register concludes that the most sensitive node to single event transient (SET) exists in the input of inverter, and the threshold voltage and capacitance of input node of inverter determine the capability of anti-SEU. A new method was proposed, which replaced the inverter with Schmitt trigger in shift register. Because there is a hysteresis on voltage transfer characteristic of Schmitt trigger, there is high flip threshold, thus better capability of anti-SEU can be achieved. Simulation results show that the anti-SEU capability of Schmitt trigger is 10 times more than that of inverter. (authors)

  4. First principle leakage current reduction technique for CMOS devices

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-12-01

    Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

  5. Radiation hardening coating material

    International Nuclear Information System (INIS)

    McDonald, W.H.; Prucnal, P.J.; DeMajistre, Robert.

    1977-01-01

    This invention concerns a radiation hardening coating material. First a resin is prepared by reaction of bisphenol diglycidylic ether with acrylic or methacrylic acids. Then the reactive solvent is prepared by reaction of acrylic or methacrylic acids with epichlorhydrine or epibromhydrine. Then a solution consisting of the resin dissolved in the reactive solvent is prepared. A substrate (wood, paper, polyesters, polyamines etc.) is coated with this composition and exposed to ionizing radiations (electron beams) or ultraviolet radiations [fr

  6. Radiation hardening of semiconductor parts

    International Nuclear Information System (INIS)

    Anon.

    1993-01-01

    This chapter is an overview of total-ionizing-dose and single-event hardening techniques and should be used as a guide to a range of research publications. It should be stressed that there is no clear and simple route to a radiation-tolerant silicon integrated circuit. What works for one fabrication process may not work for another, and there are many complex interactions within individual processes and designs. The authors have attempted to highlight the most important factors and those process changes which should bring improved hardness. The main point is that radiation-hardening as a procedure must be approached in a methodical fashion and with a good understanding of the response mechanisms involved

  7. RHOBOT: Radiation hardened robotics

    Energy Technology Data Exchange (ETDEWEB)

    Bennett, P.C.; Posey, L.D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-10-01

    A survey of robotic applications in radioactive environments has been conducted, and analysis of robotic system components and their response to the varying types and strengths of radiation has been completed. Two specific robotic systems for accident recovery and nuclear fuel movement have been analyzed in detail for radiation hardness. Finally, a general design approach for radiation-hardened robotics systems has been developed and is presented. This report completes this project which was funded under the Laboratory Directed Research and Development program.

  8. RHOBOT: Radiation hardened robotics

    International Nuclear Information System (INIS)

    Bennett, P.C.; Posey, L.D.

    1997-10-01

    A survey of robotic applications in radioactive environments has been conducted, and analysis of robotic system components and their response to the varying types and strengths of radiation has been completed. Two specific robotic systems for accident recovery and nuclear fuel movement have been analyzed in detail for radiation hardness. Finally, a general design approach for radiation-hardened robotics systems has been developed and is presented. This report completes this project which was funded under the Laboratory Directed Research and Development program

  9. Space and military radiation effects in silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Schwank, J.R.

    1996-09-01

    Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

  10. Optimized radiation-hardened erbium doped fiber amplifiers for long space missions

    Science.gov (United States)

    Ladaci, A.; Girard, S.; Mescia, L.; Robin, T.; Laurent, A.; Cadier, B.; Boutillier, M.; Ouerdane, Y.; Boukenter, A.

    2017-04-01

    In this work, we developed and exploited simulation tools to optimize the performances of rare earth doped fiber amplifiers (REDFAs) for space missions. To describe these systems, a state-of-the-art model based on the rate equations and the particle swarm optimization technique is developed in which we also consider the main radiation effect on REDFA: the radiation induced attenuation (RIA). After the validation of this tool set by confrontation between theoretical and experimental results, we investigate how the deleterious radiation effects on the amplifier performance can be mitigated following adequate strategies to conceive the REDFA architecture. The tool set was validated by comparing the calculated Erbium-doped fiber amplifier (EDFA) gain degradation under X-rays at ˜300 krad(SiO2) with the corresponding experimental results. Two versions of the same fibers were used in this work, a standard optical fiber and a radiation hardened fiber, obtained by loading the previous fiber with hydrogen gas. Based on these fibers, standard and radiation hardened EDFAs were manufactured and tested in different operating configurations, and the obtained data were compared with simulation data done considering the same EDFA structure and fiber properties. This comparison reveals a good agreement between simulated gain and experimental data (vulnerability in terms of gain. The presented approach is a complementary and effective tool for hardening by device techniques and opens new perspectives for the applications of REDFAs and lasers in harsh environments.

  11. Applications of Si/SiGe heterostructures to CMOS devices

    International Nuclear Information System (INIS)

    Sidek, R.M.

    1999-03-01

    For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

  12. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  13. Radiation hardening and irradiation testing of in-cell electronics for MA23/APM

    International Nuclear Information System (INIS)

    Friant, A.

    1988-09-01

    We relate briefly the radiation hardening method used to guarantee a gamma resistance of 10 Mrad for the whole electronic equipment associated with the slave arm of MA23 M servomanipulator which will be set up in cell 404 in Marcoule (APM). We describe the radiation testing of electronic devices and of the various subsystems designed by the D. LETI groups involved in the MA23/APM project

  14. Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

    International Nuclear Information System (INIS)

    Neamen, D.; Shedd, W.; Buchanan, B.

    1975-01-01

    The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

  15. Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

    Science.gov (United States)

    McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

    2017-03-28

    Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

  16. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  17. Radiation-hardened optoelectronic components: detectors

    International Nuclear Information System (INIS)

    Wiczer, J.J.

    1986-01-01

    In this talk, we will survey recent research in the area of radiation hardened optical detectors. We have studied conventional silicon photodiode structures, special radiation hardened silicon photodiodes, and special double heterojunction AlGaAs/GaAs photodiodes in neutron, gamma, pulsed x-ray and charged particle environments. We will present results of our work and summarize other research in this area. Our studies have shown that detectors can be made to function acceptably after exposures to neutron fluences of 10 15 n/cm 2 , total dose gamma exposures of 10 8 rad (Si), and flash x-ray environments of 10 8 rad/sec (Si). We will describe detector structures that can operate through these conditions, pre-rad and post-rad operational characteristics, and experimental conditions that produced these results. 23 refs., 10 figs., 1 tab

  18. Radiation hardening of metals irradiated by heavy ions

    International Nuclear Information System (INIS)

    Didyk, A.Yu.; Skuratov, V.A.; Mikhajlova, N.Yu.; Regel', V.R.

    1988-01-01

    The damage dose dependence in the 10 -4 -10 -2 dpa region of radiation hardening of Al, V, Ni, Cu irradiated by xenon ions with 124 MeV energy is investigated using the microhardness technique and transmission electron microscope. It is shown that the pure metals radiation hardening is stimulated for defects clusters with the typical size less than 5 nm, as in the case of neutron and the light charge ion irradiation

  19. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  20. Skin hardening effect in patients with polymorphic light eruption: comparison of UVB hardening in hospital with a novel home UV-hardening device.

    Science.gov (United States)

    Franken, S M; Genders, R E; de Gruijl, F R; Rustemeyer, T; Pavel, S

    2013-01-01

    An effective prophylactic treatment of patients with polymorphic light eruption (PLE) consists of repeated low, gradually increasing exposures to UVB radiation. This so-called UV(B) hardening induces better tolerance of the skin to sunlight. SunshowerMedical company (Amsterdam) has developed an UV (B) source that can be used during taking shower. The low UV fluence of this apparatus makes it an interesting device for UV hardening. In a group of PLE patients, we compared the effectiveness of the irradiation with SunshowerMedical at home with that of the UVB treatment in the hospital. The PLE patients were randomized for one of the treatments. The hospital treatment consisted of irradiations with broad-band UVB (Waldmann 85/UV21 lamps) twice a week during 6 weeks. The home UV-device was used each day with the maximal irradiation time of 6 min. The outcome assessment was based on the information obtained from patients' dermatological quality of life (DLQI) questionnaires, the ability of both phototherapies to reduce the provocation reaction and from the patients' evaluation of the long-term benefits of their phototherapies. Sixteen patients completed treatment with SunshowerMedical and thirteen completed treatment in hospital. Both types of phototherapy were effective. There was a highly significant improvement in DLQI with either treatment. In most cases, the hardening reduced or even completely suppressed clinical UV provocation of PLE. The patients using SunshowerMedical at home were, however, much more content with the treatment procedure than the patients visiting the dermatological units. Both treatments were equally effective in the induction of skin tolerance to sunlight in PLE patients. However, the home treatment was much better accepted than the treatment in the hospital. © 2011 The Authors. Journal of the European Academy of Dermatology and Venereology © 2011 European Academy of Dermatology and Venereology.

  1. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  2. A new method of preventing bulk-Si CMOS devices from latchup

    International Nuclear Information System (INIS)

    Xu Xianguo; Xu Xi

    2004-01-01

    A new method, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After we study the design of pseudo-latchup path method in detail, a practice and the corresponding simulation result by computer are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but it cannot be used to eliminate the dose rate upset of bulk-Si CMOS devices. (authors)

  3. 0.25μm radiation tolerant technology for space applications

    International Nuclear Information System (INIS)

    Haddad, N.; Brady, F.; Scott, T.; Yoder, J.

    1999-01-01

    Lockheed Martin federal systems has developed a state-of-the-art radiation tolerant 0,25 μm CMOS capability that is compatible with commercial foundries as well as radiation hardened fabrication. A technology test chip was designed, fabricated and evaluated for performance, power and radiation hardness in order to validate the methodology and evaluate the technology. Testing results show that -) the active transistor threshold shift is negligible for 0.25 μm CMOS, -) the hardened STI (shallow trench isolation) can support Mega-rad applications, and -) the holding voltage is well beyond the operating voltage of 2.5 V. This technology is intended to support high density, high performance and low power space applications

  4. BUSFET -- A radiation-hardened SOI transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

  5. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  6. Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

    International Nuclear Information System (INIS)

    Walther, S.; Lenoble, D.; Lallement, F.; Grouillet, A.; Erokhin, Y.; Singh, V.; Testoni, A.

    2005-01-01

    For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5x higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p + /n ultra-shallow junctions formed with BF 3 plasma doping have superior X j /R s characteristics to beamline implants and yield up to 30% lower R s for 20 nm X j while using standard spike anneal with ramp-up rate of 75 deg. C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior V t roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving V t roll-off and I on -I off performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity

  7. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  8. Update on radiation-hardened microcomputers for robotics and teleoperated systems

    International Nuclear Information System (INIS)

    Sias, F.R. Jr.; Tulenko, J.S.

    1993-01-01

    Since many programs sponsored by the Department of Defense are being canceled, it is important to select carefully radiation-hardened microprocessors for projects that will mature (or will require continued support) several years in the future. At the present time there are seven candidate 32-bit processors that should be considered for long-range planning for high-performance radiation-hardened computer systems. For Department of Energy applications it is also important to consider efforts at standardization that require the use of the VxWorks operating system and hardware based on the VMEbus. Of the seven processors, one has been delivered and is operating and other systems are scheduled to be delivered late in 1993 or early in 1994. At the present time the Honeywell-developed RH32, the Harris RH-3000 and the Harris RHC-3000 are leading contenders for meeting DOE requirements for a radiation-hardened advanced 32-bit microprocessor. These are all either compatible with or are derivatives of the MIPS R3000 Reduced Instruction Set Computer. It is anticipated that as few as two of the seven radiation-hardened processors will be supported by the space program in the long run

  9. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  10. The review of radiation effects of γ total dose in CMOS circuits

    International Nuclear Information System (INIS)

    Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

    1992-01-01

    Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

  11. Radiation hardening and embrittlement of some refractory metals and alloys

    International Nuclear Information System (INIS)

    Fabritsiev, S.; Pokrovskyb

    2007-01-01

    Tungsten is proposed for application in the ITER divertor and limiter as plasma facing material. The tungsten operation temperature in the ITER divertor is relatively high. Hence, the ductile properties of tungsten will be controlled by the low temperature radiation embrittlement. The mechanism of radiation hardening and embrittlement under neutron irradiation at low temperature is well studied for FCC metals, in particular for copper. At the same time, low-temperature radiation hardening of BCC materials, in particular for refractory metals, is less studied. This study presents the results of investigation into radiation hardening and embrittlement of pure metals: W, Mo and Nb, and W-Re and Ta-4W alloys. The materials were in the annealed conditions. The specimens were irradiated in the SM-2 reactor to doses of 10 -4 -10 -1 dpa at 80 C and then tested for tension at 80 C. The study of the stress-strain curves of unirradiated specimens revealed a yield drop for W, Mo, Nb, Ta-4W, W-Re. After the yield drop some metals (Mo,Nb) retain their capability for strain hardening and demonstrate a high elongation (20-50%). Radiation hardening is maximum in Mo (∝400MPa) and minimum in Nb (∝100 MPa). In this case the dependence slope for Nb is similar to that for pure copper irradiated in SM-2 under the same conditions. Ii and Ta-4W have a higher slope. Measurement of electrical resistivity of irradiated specimens showed that for all materials it is increased monotonously with an increase in the irradiation dose. A minimum gain in electrical resistivity with a dose was observed for Nb (∝3% at 0.1 dpa). As for Mo it was essentially higher, i.e. ∝ 30%. The gain was maximum for W-Re alloy. Comparison of radiation hardening dose dependencies obtained in this study with the data for FCC metals (Cu) showed that in spite of the quantitative difference the qualitative behavior of these two classes of metals is similar. (orig.)

  12. Estimation of radiation hardening in ferritic steels using the cluster dynamics models

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Jun Hyun; Kim, Whung Whoe; Hong, Jun Hwa [Korea Atomic Energy Research Institute, Taejon (Korea, Republic of)

    2005-07-01

    Evolution of microstructure under irradiation brings about the mechanical property changes of materials, of which the major concern is radiation hardening in this work. Radiation hardening is generally expressed in terms of an increase in yield strength as a function of radiation dose and temperature. Cluster dynamics model for radiation hardening has been developed to describe the evolution of point defects clusters (PDCs) and copperrich precipitates (CRPs). While the mathematical models developed by Stoller focus on the evolution of PDCs in ferritic steels under neutron irradiation, we slightly modify the model by including the CRP growth and estimate the magnitude of hardening induced by PDC and CRP. The model is then used to calculate the changes in yield strength of RPV steels. The calculation results are compared to measured yield strength values, obtained from surveillance testing of PWR vessel steels in France.

  13. Overview of CMOS process and design options for image sensor dedicated to space applications

    Science.gov (United States)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  14. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  15. Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

    Science.gov (United States)

    Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

    2017-01-01

    Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

  16. Large Format CMOS-based Detectors for Diffraction Studies

    Science.gov (United States)

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  17. Large Format CMOS-based Detectors for Diffraction Studies

    International Nuclear Information System (INIS)

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  18. Architecture and performance of radiation-hardened 64-bit SOS/MNOS memory

    International Nuclear Information System (INIS)

    Kliment, D.C.; Ronen, R.S.; Nielsen, R.L.; Seymour, R.N.; Splinter, M.R.

    1976-01-01

    This paper discusses the circuit architecture and performance of a nonvolatile 64-bit MNOS memory fabricated on silicon on sapphire (SOS). The circuit is a test vehicle designed to demonstrate the feasibility of a high-performance, high-density, radiation-hardened MNOS/SOS memory. The array is organized as 16 words by 4 bits and is fully decoded. It utilizes a two-(MNOS) transistor-per-bit cell and differential sensing scheme and is realized in PMOS static resistor load logic. The circuit was fabricated and tested as both a fast write random access memory (RAM) and an electrically alterable read only memory (EAROM) to demonstrate design and process flexibility. Discrete device parameters such as retention, circuit electrical characteristics, and tolerance to total dose and transient radiation are presented

  19. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    International Nuclear Information System (INIS)

    Barnaby, Hugh J.; Mclain, Michael; Esqueda, Ivan Sanchez

    2007-01-01

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits

  20. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    International Nuclear Information System (INIS)

    Hu Rongbin; Wang Yuxin; Lu Wu

    2014-01-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  1. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

  2. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    International Nuclear Information System (INIS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

    2016-01-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  3. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  4. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  5. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  6. Designing Security-Hardened Microkernels For Field Devices

    Science.gov (United States)

    Hieb, Jeffrey; Graham, James

    Distributed control systems (DCSs) play an essential role in the operation of critical infrastructures. Perimeter field devices are important DCS components that measure physical process parameters and perform control actions. Modern field devices are vulnerable to cyber attacks due to their increased adoption of commodity technologies and that fact that control networks are no longer isolated. This paper describes an approach for creating security-hardened field devices using operating system microkernels that isolate vital field device operations from untrusted network-accessible applications. The approach, which is influenced by the MILS and Nizza architectures, is implemented in a prototype field device. Whereas, previous microkernel-based implementations have been plagued by poor inter-process communication (IPC) performance, the prototype exhibits an average IPC overhead for protected device calls of 64.59 μs. The overall performance of field devices is influenced by several factors; nevertheless, the observed IPC overhead is low enough to encourage the continued development of the prototype.

  7. Coatings hardenable by ionizing radiation and their applications

    International Nuclear Information System (INIS)

    Aronoff, E.J.; Labana, S.S.

    1976-01-01

    The invention deals with the production of a coating medium which can be hardened by ionizing radiation. The composition includes tetravinyl compounds containing no free hydroxyl groups which were obtained by the conversion of di-epoxides with acryl or methacryl acid via the intermediary step of a divinyl ester condensation product. The intermediary product is converted with acryloyl or methacryloyl halides. The mass still contains non-polymerisable solvent (such as tolual, xylol), pigments and fillers. It is of advantage if the di-epoxide has a molecular weight of 140 to 500. Furthermore, coatings are to be made of this coating medium which are hardened by ionizing radiation at temperatures between 20 0 C and 70 0 C. 19 examples. (HK) [de

  8. Comparison of analytical models and experimental results for single-event upset in CMOS SRAMs

    International Nuclear Information System (INIS)

    Mnich, T.M.; Diehl, S.E.; Shafer, B.D.

    1983-01-01

    In an effort to design fully radiation-hardened memories for satellite and deep-space applications, a 16K and a 2K CMOS static RAM were modeled for single-particle upset during the design stage. The modeling resulted in the addition of a hardening feedback resistor in the 16K remained tentatively unaltered. Subsequent experiments, using the Lawrence Berkeley Laboratories' 88-inch cyclotron to accelerate krypton and oxygen ions, established an upset threshold for the 2K and the 16K without resistance added, as well as a hardening threshold for the 16K with feedback resistance added. Results for the 16K showed it to be hardenable to the higher level than previously published data for other unhardened 16K RAMs. The data agreed fairly well with the modeling results; however, a close look suggests that modification of the simulation methodology is required to accurately predict the resistance necessary to harden the RAM cell

  9. Sensitivity Enhancement of a Vertical-Type CMOS Hall Device for a Magnetic Sensor

    Directory of Open Access Journals (Sweden)

    Sein Oh

    2018-01-01

    Full Text Available This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of 16 μm and a height of 2 μm is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

  10. CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

    Science.gov (United States)

    Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

  11. Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

    Energy Technology Data Exchange (ETDEWEB)

    Holbert, Keith E. [Arizona State Univ., Tempe, AZ (United States); Clark, Lawrence T. [Arizona State Univ., Tempe, AZ (United States)

    2016-02-19

    Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance to megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration

  12. Radiation hardening of optical fibers and fiber sensors for space applications: recent advances

    Science.gov (United States)

    Girard, S.; Ouerdane, Y.; Pinsard, E.; Laurent, A.; Ladaci, A.; Robin, T.; Cadier, B.; Mescia, L.; Boukenter, A.

    2017-11-01

    In these ICSO proceedings, we review recent advances from our group concerning the radiation hardening of optical fiber and fiber-based sensors for space applications and compare their benefits to state-of-the-art results. We focus on the various approaches we developed to enhance the radiation tolerance of two classes of optical fibers doped with rare-earths: the erbium (Er)-doped ones and the ytterbium/erbium (Er/Yb)-doped ones. As a first approach, we work at the component level, optimizing the fiber structure and composition to reduce their intrinsically high radiation sensitivities. For the Erbium-doped fibers, this has been achieved using a new structure for the fiber that is called Hole-Assisted Carbon Coated (HACC) optical fibers whereas for the Er/Ybdoped optical fibers, their hardening was successfully achieved adding to the fiber, the Cerium element, that prevents the formation of the radiation-induced point defects responsible for the radiation induced attenuation in the infrared part of the spectrum. These fibers are used as part of more complex systems like amplifiers (Erbium-doped Fiber Amplifier, EDFA or Yb-EDFA) or source (Erbium-doped Fiber Source, EDFS or Yb- EDFS), we discuss the impact of using radiation-hardened fibers on the system radiation vulnerability and demonstrate the resistance of these systems to radiation constraints associated with today and future space missions. Finally, we will discuss another radiation hardening approach build in our group and based on a hardening-by-system strategy in which the amplifier is optimized during its elaboration for its future mission considering the radiation effects and not in-lab.

  13. 3D integration of planar crossbar memristive devices with CMOS substrate

    International Nuclear Information System (INIS)

    Lin, Peng; Pi, Shuang; Xia, Qiangfei

    2014-01-01

    Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. (paper)

  14. SEU-hardened silicon bipolar and GaAs MESFET SRAM cells using local redundancy techniques

    International Nuclear Information System (INIS)

    Hauser, J.R.

    1992-01-01

    Silicon bipolar and GaAs FET SRAM's have proven to be more difficult to harden with respect to single-event upset mechanisms than have silicon CMOS SRAM's. This is a fundamental property of bipolar and JFET or MESFET device technologies which do not have a high-impedance, nonactive isolation between the control electrode and the current or voltage being controlled. All SEU circuit level hardening techniques applied at the local level must use some type of information storage redundancy so that information loss on one node due to an SEU event can be recovered from information stored elsewhere in the cell. In CMOS technologies, this can be achieved by the use of simple cross-coupling resistors, whereas in bipolar and FET technologies, no such simple approach is possible. Several approaches to the use of local redundancy in bipolar and FET technologies are discussed in this paper. At the expense of increased cell complexity and increased power consumption and write time, several approaches are capable of providing complete SEU hardness at the local cell level

  15. Formulating the strength factor α for improved predictability of radiation hardening

    Energy Technology Data Exchange (ETDEWEB)

    Tan, L., E-mail: tanl@ornl.gov; Busby, J.T.

    2015-10-15

    Analytical equations were developed to calculate the strength factors of precipitates, Frank loops, and cavities in austenitic alloys, which strongly depend on barrier type, size, geometry and density, as well as temperature. Calculated strength factors were successfully used to estimate radiation hardening using the broadly employed dispersed barrier-hardening model, leading to good agreement with experimentally measured hardening in neutron-irradiated type 304 and 316 stainless steel variants. The formulated strength factor provides a route for more reliable hardening predictions and can be easily incorporated into component simulations and design.

  16. Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications

    OpenAIRE

    Pan, Chenyun; Naeemi, Azad

    2017-01-01

    The latest results of benchmarking research are presented for a variety of beyond-CMOS charge- and spin-based devices. In addition to improving the device-level models, several new device proposals and a few majorly modified devices are investigated. Deep pipelining circuits are employed to boost the throughput of low-power devices. Furthermore, the benchmarking methodology is extended to interconnect-centric analyses and non-Boolean logic applications. In contrast to Boolean circuits, non-Bo...

  17. Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

    Science.gov (United States)

    Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

    2008-08-01

    The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

  18. Radiation-hardened I2L 8*8 multiplier circuit

    International Nuclear Information System (INIS)

    Doyle, B.R.; Kreps, S.A.; Van Vonno, N.W.; Lake, G.W.

    1979-01-01

    Development of improved Substrate Fed I 2 L (SFL) processing has been combined with geometry and fanout constraints to design a radiation hardened LSI 8.8 Multiplier. This study describes details of the process and circuit design and gives resultant electrical and radiation test performance

  19. Radiation Hardened Structured ASIC Platform with Compensation of Delay for Temperature and Voltage Variations for Multiple Redundant Temporal Voting Latch Technology

    Science.gov (United States)

    Ardalan, Sasan (Inventor)

    2018-01-01

    The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.

  20. Measuring ionizing radiation with a mobile device

    Science.gov (United States)

    Michelsburg, Matthias; Fehrenbach, Thomas; Puente León, Fernando

    2012-02-01

    In cases of nuclear disasters it is desirable to know one's personal exposure to radioactivity and the related health risk. Usually, Geiger-Mueller tubes are used to assess the situation. Equipping everyone with such a device in a short period of time is very expensive. We propose a method to detect ionizing radiation using the integrated camera of a mobile consumer device, e.g., a cell phone. In emergency cases, millions of existing mobile devices could then be used to monitor the exposure of its owners. In combination with internet access and GPS, measured data can be collected by a central server to get an overview of the situation. During a measurement, the CMOS sensor of a mobile device is shielded from surrounding light by an attachment in front of the lens or an internal shutter. The high-energy radiation produces free electrons on the sensor chip resulting in an image signal. By image analysis by means of the mobile device, signal components due to incident ionizing radiation are separated from the sensor noise. With radioactive sources present significant increases in detected pixels can be seen. Furthermore, the cell phone application can make a preliminary estimate on the collected dose of an individual and the associated health risks.

  1. Radiation effects in semiconductors

    CERN Document Server

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  2. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    International Nuclear Information System (INIS)

    Sawadsaringkarn, Y; Kimura, H; Maezawa, Y; Nakajima, A; Kobayashi, T; Sasagawa, K; Noda, T; Tokuda, T; Ohta, J

    2012-01-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  3. Nuclear EMP: key suppression device parameters for EMP hardening

    International Nuclear Information System (INIS)

    Durgin, D.L.; Brown, R.M.

    1975-03-01

    The electrical transients induced by EMP exhibit unique characteristics which differ considerably from transients associated with other phenomena such as lightning, switching, and circuit malfunctions. The suppression techniques developed to handle more common transients, though not necessarily the same devices, can be used for EMP damage protection. The suppression devices used for circuit level EMP protection are referred to as Terminal Protection Devices (TPD). Little detailed data describing the response of TPD's to EMP-related transients have been published. While most vendors publish specifications for TPD performance, there is little standardization of parameters and TPD response models are not available. This lack of parameter standardization has resulted in a proliferation of test data that is sometimes conflicting and often not directly comparable. This paper derives and/or defines a consistent set of parameters based on EMP circuit hardening requirements and on measurable component parameters and is concerned only with use of TPD's to prevent permanent damage. Three sets of parameters pertaining to pertinent TPD functional characteristics were defined as follows: standby parameters, protection parameters, and failure parameters. These parameters are used to evaluate a representative sample of TPD's and the results are presented in matrix form to facilitate the selection of devices for specific hardening problems

  4. Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

    Science.gov (United States)

    Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

    2016-09-01

    The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

  5. Radiation effects of protons and 60Co γ rays on CMOS operational amplifier

    International Nuclear Information System (INIS)

    Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Yan Rongliang

    1997-01-01

    Radiation effects of 60 Co γ ray and 4,7 and 30 MeV protons on LF 7650 CMOS operational amplifier were investigated. The damage mechanism of LF7650 was discussed. It is indicated that the mobility reduction of major carrier caused by ionizing and displacement damage is the chief mechanism causing the failure of CMOS operational amplifier irradiated by protons, and that is why the degradation of LF 7650 caused by protons is much more serious than that caused by 60 Co γ ray. In addition, a comparison of proton radiation effects on CMOS operational amplifier and MOSFET showed a significant difference in mechanism

  6. Design considerations for a radiation hardened nonvolatile memory

    International Nuclear Information System (INIS)

    Murray, J.R.

    1993-01-01

    Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques

  7. Radiation dose effects, hardening of electronic components

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.

    1991-01-01

    This course reviews the mechanism of interaction between ionizing radiation and a silicon oxide type dielectric, in particular the effect of electron-hole pairs creation in the material. Then effects of cumulated dose on electronic components and especially in MOS technology are examined. Finally methods hardening of these components are exposed. 93 refs

  8. Development of radiation hard CMOS active pixel sensors for HL-LHC

    International Nuclear Information System (INIS)

    Pernegger, Heinz

    2016-01-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  9. Minimalist fault-tolerance techniques for mitigating single-event effects in non-radiation-hardened microcontrollers

    Science.gov (United States)

    Caldwell, Douglas Wyche

    Commercial microcontrollers--monolithic integrated circuits containing microprocessor, memory and various peripheral functions--such as are used in industrial, automotive and military applications, present spacecraft avionics system designers an appealing mix of higher performance and lower power together with faster system-development time and lower unit costs. However, these parts are not radiation-hardened for application in the space environment and Single-Event Effects (SEE) caused by high-energy, ionizing radiation present a significant challenge. Mitigating these effects with techniques which require minimal additional support logic, and thereby preserve the high functional density of these devices, can allow their benefits to be realized. This dissertation uses fault-tolerance to mitigate the transient errors and occasional latchups that non-hardened microcontrollers can experience in the space radiation environment. Space systems requirements and the historical use of fault-tolerant computers in spacecraft provide context. Space radiation and its effects in semiconductors define the fault environment. A reference architecture is presented which uses two or three microcontrollers with a combination of hardware and software voting techniques to mitigate SEE. A prototypical spacecraft function (an inertial measurement unit) is used to illustrate the techniques and to explore how real application requirements impact the fault-tolerance approach. Low-cost approaches which leverage features of existing commercial microcontrollers are analyzed. A high-speed serial bus is used for voting among redundant devices and a novel wire-OR output voting scheme exploits the bidirectional controls of I/O pins. A hardware testbed and prototype software were constructed to evaluate two- and three-processor configurations. Simulated Single-Event Upsets (SEUs) were injected at high rates and the response of the system monitored. The resulting statistics were used to evaluate

  10. A Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC

    Data.gov (United States)

    National Aeronautics and Space Administration — This projects seeks to continue the development of the Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC. The effort has taken parallel paths by implementing...

  11. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  12. Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

  13. Radiation effects on custom MOS devices

    International Nuclear Information System (INIS)

    Harris, R.

    1999-05-01

    This Thesis consists of four chapters: The first is primarily for background information on the effects of radiation on MOS devices and the theory of wafer bonding; the second gives a full discussion of all practical work carried out for manufacture of Field Effect test Capacitors, the third discusses manufacture of vacuum insulator Field Effect Transistors (FET's) and the fourth discusses the testing of these devices. Using a thermally bonded field effect capacitor structure, a vacuum dielectric was studied for use in high radiation environments with a view to manufacturing a CMOS compatible, micro machined transistor. Results are given in the form of high frequency C-V curves before and after a 120 kGy(Si), 12 MRad(Si), dose from a Co 60 source showing a 1 Volt shift. The work is then extended to the design and manufacture of a micro machined, under-etch technique, Field Effect Transistor for use in high radiation areas. Results are shown for Threshold, Subthreshold and Transfer characteristics before and after irradiation up to a total dose of 100kGy or 10MRad. The conclusion from this work is that it should be possible to commercially manufacture practical vacuum dielectric field effect transistors which are radiation hard to at least 120 kGy(Si). (author)

  14. Technologies Enabling Custom Radiation-Hardened Component Development, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Two primary paths are available for the creation of a Rad-Hard ASIC. The first approach is to use a radiation hardened process such as existing Rad-Hard foundries....

  15. Radiation Hardened Ethernet PHY and Switch Fabric, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Innoflight will develop a new family of radiation hardened (up to 3 Mrad(Si)), fault-tolerant, high data-rate (up to 8 Gbps), low power Gigabit Ethernet PHY and...

  16. Radiation-Hardened Memristor-based Memory for Extreme Environments, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA space exploration missions require radiation-hardened memory technologies that can survive and operate over a wide temperature range. Memristors...

  17. Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

    Science.gov (United States)

    León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

    2018-05-01

    We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

  18. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  19. Configurable Radiation Hardened High Speed Isolated Interface ASIC, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  20. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, J.

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

  1. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  2. Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

    Science.gov (United States)

    Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

    2003-05-01

    Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

  3. Experimental research on transient ionizing radiation effects of CMOS microcontroller

    International Nuclear Information System (INIS)

    Jin Xiaoming; Fan Ruyu; Chen Wei; Wang Guizhen; Lin Dongsheng; Yang Shanchao; Bai Xiaoyan

    2010-01-01

    This paper presents an experimental test system of CMOS microcontroller EE80C196KC20. Based on this system, the transient ionizing radiation effects on microcontroller were investigated using 'Qiangguang-I' accelerator. The gamma pulse width was 20 ns and the dose rate (for the Si atom) was in the range of 6.7 x 10 6 to 2.0 x 10 8 Gy/s in the experimental study. The disturbance and latchup effects were observed at different dose rate levels. Latchup threshold of the microcontroller was obtained. Disturbance interval and the system power supply current have a relationship with the dose rate level. The transient ionizing radiation induces photocurrent in the PN junctions that are inherent in CMOS circuits. The photocurrent is responsible for the electrical and functional degradation. (authors)

  4. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation hardened nonvolatile memories for space is still primarily confined to EEPROM. There is high density effective or cost effective NVM solution available to...

  5. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; hide

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  6. Identification of radiation induced dark current sources in pinned photodiode CMOS image sensors

    International Nuclear Information System (INIS)

    Goiffon, V.; Virmontois, C.; Magnan, P.; Cervantes, P.; Place, S.; Estribeau, M.; Martin-Gonthier, P.; Gaillardin, M.; Girard, S.; Paillet, P.

    2012-01-01

    This paper presents an investigation of Total Ionizing Dose (TID) induced dark current sources in Pinned Photodiodes (PPD) CMOS Image Sensors based on pixel design variations. The influence of several layout parameters is studied. Only one parameter is changed at a time enabling the direct evaluation of its contribution to the observed device degradation. By this approach, the origin of radiation induced dark current in PPD is localized on the pixel layout. The PPD peripheral shallow trench isolation does not seem to play a role in the degradation. The PPD area and a transfer gate contribution independent of the pixel dimensions appear to be the main sources of the TID induced dark current increase. This study also demonstrates that applying a negative voltage on the transfer gate during integration strongly reduces the radiation induced dark current. (authors)

  7. A monolithic 180 nm CMOS dosimeter for In Vivo Dosimetry medical application

    International Nuclear Information System (INIS)

    Villani, E.G.; Crepaldi, M.; DeMarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Rosenfeld, A.; Zhang, Z.

    2014-01-01

    The design and development of a monolithic system-on-chip dosimeter fabricated in a standard 180 nm CMOS technology is described. The device is intended for real time In Vivo measurement of dose of radiation during radiotherapy sessions. Owing to its proposed small size, of approximately 1 mm 3 , such solution could be made in-body implantable and, as such, provide a much-enhanced high-resolution, real-time dose measurement for quality assurance in radiation therapy. The device transmits the related information on dose of radiation wirelessly to an external receiver operating in the MICS band. The various phases of this two years project, started in 2011, including the design and development of radiation sensors and integrated RF to perform the readout, will be described. - Highlights: • A novel monolithic CMOS dosimeter of size of 1 mm 3 has been proposed. • Three different fabrications using a CMOS 180 nm technology have been carried out. • Radiation tests results showed a sensitivity of 1 cGy with accuracy better than 3%. • Preliminary RF tests showed that an RF signal is detectable in free air

  8. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Directory of Open Access Journals (Sweden)

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  9. Taking SiC Power Devices to the Final Frontier: Addressing Challenges of the Space Radiation Environment

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan

    2017-01-01

    Silicon carbide power device technology has the potential to enable a new generation of aerospace power systems that demand high efficiency, rapid switching, and reduced mass and volume in order to expand space-based capabilities. For this potential to be realized, SiC devices must be capable of withstanding the harsh space radiation environment. Commercial SiC components exhibit high tolerance to total ionizing dose but to date, have not performed well under exposure to heavy ion radiation representative of the on-orbit galactic cosmic rays. Insertion of SiC power device technology into space applications to achieve breakthrough performance gains will require intentional development of components hardened to the effects of these highly-energetic heavy ions. This work presents heavy-ion test data obtained by the authors over the past several years for discrete SiC power MOSFETs, JFETs, and diodes in order to increase the body of knowledge and understanding that will facilitate hardening of this technology to space radiation effects. Specifically, heavy-ion irradiation data taken under different bias, temperature, and ion beam conditions is presented for devices from different manufacturers, and the emerging patterns discussed.

  10. Process for hardening synthetic resins by ionizing radiation

    International Nuclear Information System (INIS)

    Hesse, W.; Ritz, J.

    1975-01-01

    Synthetic resins containing hydroxy groups and polymerizable carbon-carbon bonds are reacted with diketenes to yield aceto ester derivatives, which when reacted with metal compounds to form chelates, and mixed with copolymerizable monomers, are capable of being hardened by unusually low radiation doses to form coatings and articles with superior properties. (E.C.B.)

  11. The capability of pulsed laser radiation for cutting band saws hardening

    Directory of Open Access Journals (Sweden)

    Marinin Evgeny

    2017-01-01

    Full Text Available The article deals with the possibilities of pulsed laser radiation for hardening the band saws. The regimes of pulsed laser hardening the band saws of 1 mm thick made of tool steel 9CrV are grounded theoretically and experimentally tested. Selected and justified modes of treatment harden in the autohardening mode without additional heat removal. The results of the experimental research of microhardness are presented and formed as a result of processing of the microstructure. Selected modes increase the microhardness of the surface to 8500 MPa and form ultra highly dispersed structure in the surface layer characterized by high resistance to abrasion.

  12. Effects of plasma-deposited silicon nitride passivation on the radiation hardness of CMOS integrated circuits

    International Nuclear Information System (INIS)

    Clement, J.J.

    1980-01-01

    The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point

  13. An analysis of radiation effects on electronics and soi-mos devices as an alternative

    International Nuclear Information System (INIS)

    Ikraiam, F. A.

    2013-01-01

    The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

  14. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — Space Micro proposes to build a radiation hardened by design (RHBD) flash memory, using a modified version of our RH-eDRAM Memory Controller to solve all the single...

  15. Simulation of pulsed-ionizing-radiation-induced errors in CMOS memory circuits

    International Nuclear Information System (INIS)

    Massengill, L.W.

    1987-01-01

    Effects of transient ionizing radiation on complementary metal-oxide-semiconductor (CMOS) memory circuits was studied by computer simulation. Simulation results have uncovered the dominant mechanism leading to information loss (upset) in dense (CMOS) circuits: rail span collapse. This effect is the catastrophic reduction in the local power supply at a RAM cell location due to the conglomerate radiation-induced photocurrents from all other RAM cells flowing through the power-supply-interconnect distribution. Rail-span collapse leads to reduced RAM cell-noise margins and can predicate upset. Results show that rail-span collapse in the dominant pulsed radiation effect in many memory circuits, preempting local circuit responses to the radiation. Several techniques to model power-supply noise, such as that arising from rail span collapse, are presented in this work. These include an analytical model for design optimization against these effects, a hierarchical computer-analysis technique for efficient power bus noise simulation in arrayed circuits, such as memories, and a complete circuit-simulation tool for noise margin analysis of circuits with arbitrary topologies

  16. Radiation hardening techniques for rare-earth based optical fibers and amplifiers

    International Nuclear Information System (INIS)

    Girard, Sylvain; Marcandella, Claude; Vivona, Marilena; Prudenzano, Luciano Mescia F.; Laurent, Arnaud; Robin, Thierry; Cadier, Benoit; Pinsard, Emmanuel; Ouerdane, Youcef; Boukenter, Aziz; Cannas, Marco; Boscaino, Roberto

    2012-01-01

    Er/Yb doped fibers and amplifiers have been shown to be very radiation sensitive, limiting their integration in space. We present an approach including successive hardening techniques to enhance their radiation tolerance. The efficiency of our approach is demonstrated by comparing the radiation responses of optical amplifiers made with same lengths of different rare-earth doped fibers and exposed to gamma-rays. Previous studies indicated that such amplifiers suffered significant degradation for doses exceeding 10 krad. Applying our techniques significantly enhances the amplifier radiation resistance, resulting in a very limited degradation up to 50 krad. Our optimization techniques concern the fiber composition, some possible pre-treatments and the interest of simulation tools used to harden by design the amplifiers. We showed that adding cerium inside the fiber phospho-silicate-based core strongly decreases the fiber radiation sensitivity compared to the standard fiber. For both fibers, a pre-treatment with hydrogen permits to enhance again the fiber resistance. Furthermore, simulations tools can also be used to improve the tolerance of the fiber amplifier by helping identifying the best amplifier configuration for operation in the radiative environment. (authors)

  17. A novel CMOS SRAM feedback element for SEU environments

    International Nuclear Information System (INIS)

    Verghese, S.; Wortman, J.J.; Kerns, S.E.

    1987-01-01

    A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

  18. Radiation Effects and Hardening Techniques for Spacecraft Microelectronics

    Science.gov (United States)

    Gambles, J. W.; Maki, G. K.

    2002-01-01

    The natural radiation from the Van Allen belts, solar flares, and cosmic rays found outside of the protection of the earth's atmosphere can produce deleterious effects on microelectronics used in space systems. Historically civil space agencies and the commercial satellite industry have been able to utilize components produced in special radiation hardened fabrication process foundries that were developed during the 1970s and 1980s under sponsorship of the Departments of Defense (DoD) and Energy (DoE). In the post--cold war world the DoD and DoE push to advance the rad--hard processes has waned. Today the available rad--hard components lag two-plus technology node generations behind state- of-the-art commercial technologies. As a result space craft designers face a large performance gap when trying to utilize available rad--hard components. Compounding the performance gap problems, rad--hard components are becoming increasingly harder to get. Faced with the economic pitfalls associated with low demand versus the ever increasing investment required for integrated circuit manufacturing equipment most sources of rad--hard parts have simply exited this market in recent years, leaving only two domestic US suppliers of digital rad--hard components. This paper summarizes the radiation induced mechanisms that can cause digital microelectronics to fail in space, techniques that can be applied to mitigate these failure mechanisms, and ground based testing used to validate radiation hardness/tolerance. The radiation hardening techniques can be broken down into two classes, Hardness By Process (HBP) and Hardness By Design (HBD). Fortunately many HBD techniques can be applied to commercial fabrication processes providing space craft designer with radiation tolerant Application Specific Integrated Circuits (ASICs) that can bridge the performance gap between the special HBP foundries and the commercial state-of-the-art performance.

  19. Theoretic simulation for CMOS device on total dose radiation response

    International Nuclear Information System (INIS)

    He Baoping; Zhou Heqin; Guo Hongxia; He Chaohui; Zhou Hui; Luo Yinhong; Zhang Fengqi

    2006-01-01

    Total dose effect is simulated for C4007B, CC4007RH and CC4011 devices at different absorbed dose rate by using linear system theory. When irradiation response and dose are linear, total dose radiation and post-irradiation annealing at room temperature are determined for one random by choosing absorbed dose rate, and total dose effect at other absorbed dose rate can be predicted by using linear system theory. The simulating results agree with the experimental results at different absorbed dose rate. (authors)

  20. Investigation of single event latchup

    International Nuclear Information System (INIS)

    Xue Yuxiong; Yang Shengsheng; Cao Zhou; Ba Dedong; An Heng; Chen Luojing; Guo Gang

    2012-01-01

    Radiation effects on avionics microelectronics are important reliability issues for many space applications. In particular, single-event latchup (SEL) phenomenon is a major threat to CMOS integrated circuits in space systems. To effectively circumvent the failure, it is important to know the behavior of such devices during latchup. In this paper, the mechanisms for SEL in CMOS devices are investigated. Several microelectronic devices used in avionics are tested using heavy ion beams, pulsed laser and 252 Cf source. Based on the SEL test results, SEL-hardening and monitoring methods for preventing SEL from the systems design level are proposed. (authors)

  1. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  2. A research on radiation calibration of high dynamic range based on the dual channel CMOS

    Science.gov (United States)

    Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

    2017-10-01

    The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

  3. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  4. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  5. Microhardness technique for determination of radiation hardening in austenitic stainless steel using

    International Nuclear Information System (INIS)

    Hofman, A.

    1995-01-01

    The use of microhardness technique to determine the radiation hardening has been studied. Microhardness measurements have been conducted on austenitic stainless steel 0H18N10T irradiated up to 2·10 23 nm -2 . It was determined that the increase in microhardness varies directly with the measured increase in the 0,2% offret yield strength and has been found that microhardness technique may be an effective tool to measurements of radiation induced hardening. Based on the results and Cahoon's relation that σ 0,2 (MPa)=3,27HV(0,1) n method for evaluating the yield stress σ 0,2 by microhardness technique is analyzed. 14 refs., 3 figs., 3 tabs

  6. Radiation evaluation of commercial ferroelectric nonvolatile memories

    International Nuclear Information System (INIS)

    Benedetto, J.M.; DeLancey, W.M.; Oldham, T.R.; McGarrity, J.M.; Tipton, C.W.; Brassington, M.; Fisch, D.E.

    1991-01-01

    This paper reports on ferroelectric (FE) on complementary metal-oxide semiconductor (CMOS) 4-kbit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips that were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-kbit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field- oxide effects in the underlying CMOS. No significant difference was observed between the radiation responses of devices with and without the FE film in this commercial process

  7. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  8. The RD50 activity in the context of future pixel detector systems

    International Nuclear Information System (INIS)

    Casse, G.

    2015-01-01

    The CERN/RD50 collaboration is dedicated to the radiation hardening of semiconductor sensors for future super-collider needs. The findings of this collaboration are therefore especially relevant to the pixel devices for the LHC experiment upgrades. A considerable amount of results on the enhancement of the radiation tolerance of silicon sensors has been found within RD50. The research towards radiation hardening has highlighted, and increased the knowledge on properties of sensors that are relevant to other applications. For example radiation hardening relies on the speed of signal collection in irradiated devices. As a consequence, the methods envisaged for increasing this collection speed turn out to be promising for significantly improving the performance of time resolved, high spatial resolution systems. A new type of device processing strongly emerging for production of future pixel sensor systems is the HV-CMOS technology. The RD50 research methodology provides the tools for characterising the behaviour of the deep collecting electrode (deep n-well) for this type of device after irradiation and the optimal framework for comparing the performance of the new devices with the current state of the art

  9. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    International Nuclear Information System (INIS)

    Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

  10. Characterization and radiation studies of diode test structures in LFoundry CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    In order to prepare for the High Luminosity upgrade of the LHC, all subdetector systems of the ATLAS experiment will be upgraded. In preparation for this process, different possibilities for new radiation-hard and cost-efficient silicon sensor technologies to be used as part of hybrid pixel detectors in the ATLAS inner tracker are being investigated. One promising way to optimize the cost-efficiency of silicon-based pixel detectors is to use commercially available CMOS technologies such as the 150 nm process by LFoundry. In this talk, several CMOS pixel test structures, such as simple diodes and small pixel arrays, that were manufactured in this technology are characterized regarding general performance and radiation hardness and compared to each other as well as to the current ATLAS pixel detector.

  11. Nuclear Radiation Degradation Study on HD Camera Based on CMOS Image Sensor at Different Dose Rates.

    Science.gov (United States)

    Wang, Congzheng; Hu, Song; Gao, Chunming; Feng, Chang

    2018-02-08

    In this work, we irradiated a high-definition (HD) industrial camera based on a commercial-off-the-shelf (COTS) CMOS image sensor (CIS) with Cobalt-60 gamma-rays. All components of the camera under test were fabricated without radiation hardening, except for the lens. The irradiation experiments of the HD camera under biased conditions were carried out at 1.0, 10.0, 20.0, 50.0 and 100.0 Gy/h. During the experiment, we found that the tested camera showed a remarkable degradation after irradiation and differed in the dose rates. With the increase of dose rate, the same target images become brighter. Under the same dose rate, the radiation effect in bright area is lower than that in dark area. Under different dose rates, the higher the dose rate is, the worse the radiation effect will be in both bright and dark areas. And the standard deviations of bright and dark areas become greater. Furthermore, through the progressive degradation analysis of the captured image, experimental results demonstrate that the attenuation of signal to noise ratio (SNR) versus radiation time is not obvious at the same dose rate, and the degradation is more and more serious with increasing dose rate. Additionally, the decrease rate of SNR at 20.0, 50.0 and 100.0 Gy/h is far greater than that at 1.0 and 10.0 Gy/h. Even so, we confirm that the HD industrial camera is still working at 10.0 Gy/h during the 8 h of measurements, with a moderate decrease of the SNR (5 dB). The work is valuable and can provide suggestion for camera users in the radiation field.

  12. A COTS-based single board radiation-hardened computer for space applications

    International Nuclear Information System (INIS)

    Stewart, S.; Hillman, R.; Layton, P.; Krawzsenek, D.

    1999-01-01

    There is great community interest in the ability to use COTS (Commercial-Off-The-Shelf) technology in radiation environments. Space Electronics, Inc. has developed a high performance COTS-based radiation hardened computer. COTS approaches were selected for both hardware and software. Through parts testing, selection and packaging, all requirements have been met without parts or process development. Reliability, total ionizing dose and single event performance are attractive. The characteristics, performance and radiation resistance of the single board computer will be presented. (authors)

  13. Radiation Hardening and Verification Procedure for Compact Flip-Flop Design

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Inyong; Sung, Seung Hwan [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    For radiation-related applications applying electronic devices in nuclear, space, medicine, and scientific experiment, single event transients (SETs) and single event upsets (SEUs) are become primary concern since they can cause malfunctions in a system by affecting the signal transition and flipping digital bits. The D flip-flop as a register is generally used in digital circuits that require data stability and high speed. For many years, radiation-hardened-by-design (RHBD) circuits have been gradually developed from traditional circuit architectures. One of common methods is to exploit redundancy in an important circuit block to preserve the correct signal. This technique uses a voting process to have a correct output when other duplicated systems fail due to a single event effect (SEE) including SET and SEU. For instance, B. Olson applied the redundancy technique, formally referred the triple modular redundancy (TMR). Other researchers use various error detection and correction (EDAC) algorithms including redundant bits in the storage circuits to detect and correct errors at the system level. practical experiments at radiation exposure facilities. Korea Atomic Energy Research Institute (KAERI) operates a laboratory with high energy radioactive isotope, {sup 60}Co in Jeongeup, Korea. The facility can provide various experiments requiring experimental environment changes by controlling radiation activity and radiated energy. The future direction on RHBD circuits would be integration with the digital DFF presented in this paper and analog front-end units such as OP-amp for charge sensitive or shaping amplifier. Analog-to-digital converters (ADCs) are also major components necessarily imbedded in the most of sensor related electronics. Thus RHBD techniques are inevitably required to protect these circuits from SEE; specifically, SEUs for digital logics and SETs for analog signals. Since most ADCs consist of both analog and digital circuits in their architectures

  14. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  15. Simulation of Hamming Coding and Decoding for Microcontroller Radiation Hardening

    OpenAIRE

    Rehab I. Abdul Rahman; Mazhar B. Tayel

    2015-01-01

    This paper presents a method of hardening the 8051 micro-controller, able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 micro-controller, Hamming code protection was used in its SRAM memory and registers. A VHDL code has been used for this hamming code protection.

  16. Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

    International Nuclear Information System (INIS)

    Jiang Yuxi; Li Jiao; Ran Feng; Cao Jialin; Yang Dianxiong

    2009-01-01

    Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented. (semiconductor devices)

  17. Nuclear Radiation Degradation Study on HD Camera Based on CMOS Image Sensor at Different Dose Rates

    Directory of Open Access Journals (Sweden)

    Congzheng Wang

    2018-02-01

    Full Text Available In this work, we irradiated a high-definition (HD industrial camera based on a commercial-off-the-shelf (COTS CMOS image sensor (CIS with Cobalt-60 gamma-rays. All components of the camera under test were fabricated without radiation hardening, except for the lens. The irradiation experiments of the HD camera under biased conditions were carried out at 1.0, 10.0, 20.0, 50.0 and 100.0 Gy/h. During the experiment, we found that the tested camera showed a remarkable degradation after irradiation and differed in the dose rates. With the increase of dose rate, the same target images become brighter. Under the same dose rate, the radiation effect in bright area is lower than that in dark area. Under different dose rates, the higher the dose rate is, the worse the radiation effect will be in both bright and dark areas. And the standard deviations of bright and dark areas become greater. Furthermore, through the progressive degradation analysis of the captured image, experimental results demonstrate that the attenuation of signal to noise ratio (SNR versus radiation time is not obvious at the same dose rate, and the degradation is more and more serious with increasing dose rate. Additionally, the decrease rate of SNR at 20.0, 50.0 and 100.0 Gy/h is far greater than that at 1.0 and 10.0 Gy/h. Even so, we confirm that the HD industrial camera is still working at 10.0 Gy/h during the 8 h of measurements, with a moderate decrease of the SNR (5 dB. The work is valuable and can provide suggestion for camera users in the radiation field.

  18. Radiation damage studies on STAR250 CMOS sensor at 300 keV for electron microscopy

    International Nuclear Information System (INIS)

    Faruqi, A.R.; Henderson, R.; Holmes, J.

    2006-01-01

    There is a pressing need for better electronic detectors to replace film for recording high-resolution images using electron cryomicroscopy. Our previous work has shown that direct electron detection in CMOS sensors is promising in terms of resolution and efficiency at 120 keV [A.R. Faruqi, R. Henderson, M. Prydderch, R. Turchetta, P. Allport, A. Evans, Nucl. Instr. and Meth. 546 (2005) 170], but in addition, the detectors must not be damaged by the electron irradiation. We now present new measurements on the radiation tolerance of a 25 μm pitch CMOS active-pixel sensor, the STAR250, which was designed by FillFactory using radiation-hard technology for space applications. Our tests on the STAR250 aimed to establish the imaging performance at 300 keV following irradiation. The residual contrast, measured on shadow images of a 300 mesh grid, was >80% after corrections for increased dark current, following irradiation with up to 5x10 7 electrons/pixel (equivalent to 80,000 electron/μm 2 ). A CMOS sensor with this degree of radiation tolerance would survive a year of normal usage for low-dose electron cryomicroscopy, which is a very useful advance

  19. Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit.

    Science.gov (United States)

    Kwon, Min-Woo; Baek, Myung-Hyun; Hwang, Sungmin; Kim, Sungjun; Park, Byung-Gook

    2018-09-01

    We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

  20. Simulation of design dependent failure exposure levels for CMOS ICs

    International Nuclear Information System (INIS)

    Kaul, N.; Bhuva, B.L.; Rangavajjhala, V.; van der Molen, H.; Kerns, S.E.

    1990-01-01

    The total dose exposure of CMOS ICs introduces bias-dependent parameter shifts in individual devices. The bias dependency of individual parameter shifts of devices cause different designs to behave differently under identical testing conditions. This paper studies the effect of design and bias on the radiation tolerance of ICs and presents an automated design tool that produces different designs for a logic function, and presents important parameters of each design to circuit designer for trade off analysis

  1. Radiation hardness assurances categories for COTS technologies

    International Nuclear Information System (INIS)

    Hash, G.L.; Shaneyfelt, M.R.; Sexton, F.W.; Winokur, P.S.

    1997-01-01

    A comparison of the radiation tolerance of three commercial, and one radiation hardened SRAM is presented for four radiation environments. This work has shown the difficulty associated with strictly categorizing a device based solely on its radiation response, since its category depends on the specific radiation environment considered. For example, the 3.3-V Paradigm SRAM could be considered a radiation-tolerant device except for its SEU response. A more useful classification depends on the methods the manufacturer uses to ensure radiation hardness, i.e. whether specific design and process techniques have been used to harden the device. Finally, this work has shown that burned-in devices may fail functionally as much as 50% lower in total dose environments than non-burned-in devices. No burn-in effect was seen in dose-rate upset, latchup, or SEE environments. The user must ensure that total dose lot acceptance testing was performed on burned-in devices

  2. Low-temperature mobility measurements on CMOS devices

    International Nuclear Information System (INIS)

    Hairpetian, A.; Gitlin, D.; Viswanathan, C.R.

    1989-01-01

    The surface channel mobility of carriers in eta- and rho-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 Κ. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP), which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appears to have different temperature dependence for eta- and rho-channel devices. The electron mobility increases with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibits a different temperature behavior depending upon whether the gate voltage corresponds to strong inversion or is near threshold

  3. Radiation hardening of diagnostics

    International Nuclear Information System (INIS)

    Siemon, R.E.

    1991-01-01

    The world fusion program has advanced to the stage where it is appropriate to construct a number of devices for the purpose of burning DT fuel. In these next-generation experiments, the expected flux and fluence of 14 MeV neutrons and associated gamma rays will pose a significant challenge to the operation and diagnostics of the fusion device. Radiation effects include structural damage to materials such as vacuum windows and seals, modifications to electrical properties such as electrical conductivity and dielectric strength and impaired optical properties such as reduced transparency and luminescence of windows and fiber optics during irradiation. In preparation for construction and operation of these new facilities, the fusion diagnostics community needs to work with materials scientists to develop a better understanding of radiation effects, and to undertake a testing program aimed at developing workable solutions for this multi-faceted problem. A unique facility to help in this regard is the Los Alamos Spallation Radiation Effects Facility, a neutron source located at the beam stop of the world's most powerful accelerator, the Los Alamos Meson Physics Facility (LAMPF). The LAMPF proton beam generates 10 16 neutrons per second because of ''spallation'' reactions when the protons collide with the copper nuclei in the beam stop

  4. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  5. High temperature, radiation hardened electronics for application to nuclear power plants

    International Nuclear Information System (INIS)

    Gover, J.E.

    1980-01-01

    Electronic circuits were developed and built at Sandia for many aerospace and energy systems applications. Among recent developments were high temperature electronics for geothermal well logging and radiation hardened electronics for a variety of aerospace applications. Sandia has also been active in technology transfer to commercial industry in both of these areas

  6. Mechanism and modelling of source/drain asymmetry variation in 65 nm CMOS devices for SRAM and logic applications

    International Nuclear Information System (INIS)

    Lee, T H; Fang, Y K; Chiang, Y T; Lin, C T; Chen, M S; Cheng, O

    2008-01-01

    The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM

  7. Evaluation method of radiation stability of hardened cement paste with chemical additives

    Energy Technology Data Exchange (ETDEWEB)

    Medvedev, Vyacheslav; Pustovgar, Andrey [National Research Univ. ' Moscow State Univ. of Civil Engineering' (MSUCE), Moscow (Russian Federation); National Research Univ. ' Moscow State Univ. of Civil Engineering' (MSUCE), Moscow (Russian Federation). Scientific Research Inst. of Constructional Materials and Technologies; Denisov, Alexander; Soloviev, Vitaly [National Research Univ. ' Moscow State Univ. of Civil Engineering' (MSUCE), Moscow (Russian Federation)

    2013-07-01

    The influence of additives on the radiation resistance of the concrete will occur through the influence of radiation changes of hardened cement paste on radiation changes of concrete and can be quite significant. The test sequence was produced according to the modified method. The samples were prepared in the form of prisms with the following dimensions: 10 mm x 10 mm, 30 mm long. Measurement series were produced after each heating and cooling sequence. Then the difference between the values before and after heating was calculated. (orig.)

  8. A 0.18μm CMOS low-power radiation sensor for UWB wireless transmission

    International Nuclear Information System (INIS)

    Crepaldi, M; Demarchi, D; Gabrielli, A; Khan, A; Pikhay, E; Roizin, Y; Villani, G; Zhang, Z

    2012-01-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm 2 , the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  9. Proton irradiation effects in silicon devices

    Energy Technology Data Exchange (ETDEWEB)

    Simoen, E; Vanhellemont, J; Alaerts, A [IMEC, Leuven (Belgium); and others

    1997-03-01

    Proton irradiation effects in silicon devices are studied for components fabricated in various substrates in order to reveal possible hardening effects. The degradation of p-n junction diodes increases in first order proportionally with the fluence, when submitted to 10 MeV proton irradiations in the range 5x10{sup 9} cm{sup -2} to 5x10{sup 11} cm{sup -2}. The damage coefficients for both p- and n-type Czochralski, Float-Zone and epitaxial wafers are reported. Charge-Coupled Devices fabricated in a 1.2 {mu}m CCD-CMOS technology are shown to be quite resistant to 59 MeV H{sup +} irradiations, irrespective of the substrate type. (author)

  10. Radiation Tolerant Design with 0.18-micron CMOS Technology

    CERN Document Server

    Chen, Li; Durdle , Nelson G.

    This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and afte...

  11. Open Source Radiation Hardened by Design Technology

    Science.gov (United States)

    Shuler, Robert

    2016-01-01

    The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.

  12. Radiation hardenable impregnating agents for the consolidating conservation of wooden objects

    International Nuclear Information System (INIS)

    Schaudy, R.

    1985-01-01

    Radiation hardenable impregnating agents offer some advantages over the conventional agents. At the author's institution objects up to 110 cm length can be impregnated for conservation. More than 200 monomers and resins have been investigated. The procedure of impregnation is outlined and some kinds of wooden objects conserved in this way listed. (G.W.)

  13. Influence of oxygen impurity atoms on defect clusters and radiation hardening in neutron-irradiated vanadium

    International Nuclear Information System (INIS)

    Bajaj, R.; Wechsler, M.S.

    1975-01-01

    Single crystal TEM samples and polycrystalline tensile samples of vanadium containing 60-640 wt ppm oxygen were irradiated at about 100 0 C to about 1.3 x 10 19 neutrons/cm 2 (E greater than 1 MeV) and post-irradiation annealed up to 800 0 C. The defect cluster density increased and the average size decreased with increasing oxygen concentration. Higher oxygen concentrations caused the radiation hardening and radiation-anneal hardening to increase. The observations are consistent with the nucleation of defect clusters by small oxygen or oxygen-point defect complexes and the trapping of oxygen at defect clusters upon post-irradiation annealing

  14. Hardening CISCO Devices based on Cryptography and Security Protocols - Part One: Background Theory

    Directory of Open Access Journals (Sweden)

    Faisal Waheed

    2018-07-01

    Full Text Available Network Security is a vital part of any corporate and enterprise network. Network attacks greatly compromise not only the sensitive data of the consumers but also cause outages to these networks. Thus inadequately protected networks need to be “hardened”. The hardening of network devices refers to the hardware and software components, device operating system’s features, management controls, access-list restrictions, operational configurations and above all making sure that the data and credentials are not stored or transferred in ‘plaintext’ over the network. This article investigates the use of cryptography and network protocols based on encryption, to meet the need for essential security requirements. Use of non-secure protocols, underrating and misconfigurations of management protection are reasons behind network devices not properly being hardened; hence leaving vulnerabilities for the intruders. The gap identified after conducting intense search and review of past work is used as the foundation to present solutions. When performing cryptography techniques by encrypting packets using tunnelling and security protocols, management level credentials are encrypted. These include password encryption and exceptional analysis of the emulated IOS (Internetwork Operating System. Necessary testing is carried out to evaluate an acceptable level of protection of these devices. In a virtual testing environment, security flaws are found mainly in the emulated IOS. The discoveries does not depend on the hardware or chassis of a networking device. Since routers primarily rely on its Operating System (OS, attackers focus on manipulating the command line configuration before initiating an attack. Substantial work is devoted to implementation and testing of a router based on Cryptography and Security Protocols in the border router. This is deployed at the core layer and acts as the first point of entry of any trusted and untrusted traffic. A step

  15. Development of radiation hardened pixel sensors for charged particle detection

    CERN Document Server

    Koziel, Michal

    2014-01-01

    CMOS Pixel Sensors are being developed since a few years to equip vertex detectors for future high-energy physics experiments with the crucial advantages of a low material budget and low production costs. The features simultaneously required are a short readout time, high granularity and high tolerance to radiation. This thesis mainly focuses on the radiation tolerance studies. To achieve the targeted readout time (tens of microseconds), the sensor pixel readout was organized in parallel columns restricting in addition the readout to pixels that had collected the signal charge. The pixels became then more complex, and consequently more sensitive to radiation. Different in-pixel architectures were studied and it was concluded that the tolerance to ionizing radiation was limited to 300 krad with the 0.35- m fabrication process currently used, while the targeted value was several Mrad. Improving this situation calls for implementation of the sensors in processes with a smaller feature size which naturally imp...

  16. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

    CERN Document Server

    Cerjan, C J

    2000-01-01

    The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

  17. Passive radiation detection using optically active CMOS sensors

    Science.gov (United States)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  18. Principles and techniques of radiation hardening. Volume 3. Electromagnetic pulse (EMP) and system generated EMP

    International Nuclear Information System (INIS)

    Rudie, N.J.

    1976-01-01

    The three-volume book is intended to serve as a review of the effects of thermonuclear explosion induced radiation (x-rays, gamma rays, and beta particles) and the resulting electromagnetic pulse (EMP). Volume 3 deals with the following topics: selected fundamentals of electromagnetic theory; EMP induced currents on antennas and cables; the EMP response of electronics; EMP hardening; EMP testing; injection currents; internal electromagnetic pulse (IEMP); replacement currents; and system generated electromagnetic pulse (SGEMP) hardening

  19. Study on radiation damage of electron and γ-rays and mechanism of nuclear hardening

    International Nuclear Information System (INIS)

    Jing Tao

    2001-01-01

    Radiation damage effects of electrons and γ-rays are presented. The damage defects are studied by experimental methods. On the basis of these studies the damage mechanism and nuclear hardening techniques are studied

  20. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  1. Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Report 3

    Energy Technology Data Exchange (ETDEWEB)

    Britton, Jr, Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Shelton, Jacob H. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

    2015-03-01

    As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios when human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments because of the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is a report of the activities involving Task 3 of the Nuclear Energy Enabling Technologies (NEET) 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays [1]. Evaluation of the performance of the system for both pre- and post-irradiation as well as operation at elevated temperature will be performed. Detailed performance of the system will be documented to ensure the design meets requirements prior to any extended evaluation. A suite of tests will be developed which will allow evaluation before and after irradiation and during temperature. Selection of the radiation exposure facilities will be determined in the early phase of the project. Radiation exposure will consist of total integrated dose (TID) up to 200 kRad or above with several intermediate doses during test. Dose rates will be in various ranges determined by the facility that will be used with a target of 30 kRad/hr. Many samples of the pre-commercial devices to be used will have been tested in previous projects to doses of at least 300 kRad and temperatures up to 125C. The complete systems will therefore be tested for performance at intermediate doses. Extended temperature testing will be performed up to the limit of the commercial sensors. The test suite performed at each test point will consist of operational testing of the three basic

  2. Development of a radiation hardened ANDROS robot for environmental restoration and waste management operations

    International Nuclear Information System (INIS)

    Tulenko, J.S.; Youk, G.; Ekdahl, D.; Liu, H.; Zhou, H.; Phillips, K.; Sias, F.; Jones, S.; Cable, T.; Harvey, H.

    1995-01-01

    A radiation hardened and tolerant version of the ANDROS V-A and VI-A system has been developed by a team composed of engineers and scientists from REMOTEC, Inc. and the University of Florida. The final upgrade of the major control components to a hardness level greater than one megarad is detailed. Over twelve hundred parts were reviewed. The project has completed its Phase 1 and Phase 2 SBIR redesign with the upgrade of all control components. The facilities at the University of Florida which include a linear accelerator and multiple cobalt irradiators have provided the capability to perform the extensive testing required. The commercial production of this radiation hardened ANDROS makes available a mobile platform that can serve as a main work and inspection system for hazardous tasks facing the world nuclear industry

  3. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  4. Radiation Effects and Component Hardening testing program at the Oak Ridge National Laboratory

    International Nuclear Information System (INIS)

    Draper, J.V.; Weil, B.S.; Chesser, J.B.

    1993-01-01

    This paper describes Phase II of the Radiation Effects and Component Hardening (REACH) testing program, performed as part of the joint collaborative agreement between the United States Department of Energy (USDOE) and the Power Reactor and Nuclear Fuel Development Corporation (PNC) of Japan, Components and materials were submitted to 10 5 R/hr gamma radiation fields for 10,000 hr, producing accumulated doses of 10 9 R; most performed as expected

  5. Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

    Science.gov (United States)

    Seto, Daisaku; Watanabe, Minoru

    2015-09-01

    In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

  6. The development of radiation hardened robot for nuclear facility

    International Nuclear Information System (INIS)

    Kim, Seung Ho; Jung, Seung Ho; Kim, Byung Soo and others

    2000-04-01

    The work conducted in this stage covers development of core technology of tele-robot system including monitoring technique in high-level radioactive area, tele-sensing technology and radiation-hardened technology for the non-destructive tele-inspection system which monitors the primary coolant system during the normal operations of PHWR(Pressurized Heavy Water Reactor) NPPs and measures the decrease of bending part of feeder pipe during overall. Based on the developed core technology, the monitoring mobile robot system of the primary coolant system and the feeder pipe inspecting robot system are developed

  7. The development of radiation hardened robot for nuclear facility

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Seung Ho; Jung, Seung Ho; Kim, Byung Soo and others

    2000-04-01

    The work conducted in this stage covers development of core technology of tele-robot system including monitoring technique in high-level radioactive area, tele-sensing technology and radiation-hardened technology for the non-destructive tele-inspection system which monitors the primary coolant system during the normal operations of PHWR(Pressurized Heavy Water Reactor) NPPs and measures the decrease of bending part of feeder pipe during overall. Based on the developed core technology, the monitoring mobile robot system of the primary coolant system and the feeder pipe inspecting robot system are developed.

  8. Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

    CERN Document Server

    Bonacini, Sandro; Kloukinas, Kostas

    2007-01-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

  9. Radiation Hardening of Silicon Detectors

    CERN Multimedia

    Leroy, C; Glaser, M

    2002-01-01

    %RD48 %title\\\\ \\\\Silicon detectors will be widely used in experiments at the CERN Large Hadron Collider where high radiation levels will cause significant bulk damage. In addition to increased leakage current and charge collection losses worsening the signal to noise, the induced radiation damage changes the effective doping concentration and represents the limiting factor to long term operation of silicon detectors. The objectives are to develop radiation hard silicon detectors that can operate beyond the limits of the present devices and that ensure guaranteed operation for the whole lifetime of the LHC experimental programme. Radiation induced defect modelling and experimental results show that the silicon radiation hardness depends on the atomic impurities present in the initial monocrystalline material.\\\\ \\\\ Float zone (FZ) silicon materials with addition of oxygen, carbon, nitrogen, germanium and tin were produced as well as epitaxial silicon materials with epilayers up to 200 $\\mu$m thickness. Their im...

  10. Device Innovation and Material Challenges at the Limits of CMOS Technology

    Science.gov (United States)

    Solomon, P. M.

    2000-08-01

    Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

  11. A radiation-hardened SOI-based FPGA

    International Nuclear Information System (INIS)

    Han Xiaowei; Wu Lihua; Zhao Yan; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Chen, Stanley L.; Liu Zhongli; Yu Fang; Zhao Kai

    2011-01-01

    A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 x 10 11 rad(Si)/s and a neutron fluence immunity of 1 x 10 14 n/cm 2 . (semiconductor integrated circuits)

  12. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  13. Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Final Report

    Energy Technology Data Exchange (ETDEWEB)

    Britton, Jr., Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Bobrek, Miljko [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

    2015-12-01

    As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios where human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments due the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is the final report of the activities involving the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. We present a detailed functional block diagram of the proposed data acquisition system, the thought process leading to technical decisions, the implemented system, and the tested results from the systems. This system will be capable of monitoring at least three parameters of importance to nuclear reactor monitoring: temperature, radiation level, and pressure.

  14. Study of interaction among silicon, lithium, oxygen and radiation-induced defects for radiation-hardened solar cells

    Science.gov (United States)

    Berman, P. A.

    1973-01-01

    In order to improve reliability and the useful lifetime of solar cell arrays for space use, a program was undertaken to develop radiation-hardened lithium-doped silicon solar cells. These cells were shown to be significantly more resistant to degradation by ionized particles than the presently used n-p nonlithium-doped silicon solar cells. The results of various analyses performed to develop a more complete understanding of the physics of the interaction among lithium, silicon, oxygen, and radiation-induced defects are presented. A discussion is given of those portions of the previous model of radiation damage annealing which were found to be in error and those portions which were upheld by these extensive investigations.

  15. Radiation effects on and dose enhancement of electronic materials

    International Nuclear Information System (INIS)

    Srour, J.R.; Long, D.M.

    1984-01-01

    This book describes radiation effects on and dose enhancement factors for electronic materials. Alteration of the electrical properties of solid-state devices and integrated circuits by impinging radiation is well-known. Such changes may cause an electronic subsystem to fail, thus there is currently great interest in devising methods for avoiding radiation-induced degradation. The development of radiation-hardened devices and circuits is an exciting approach to solving this problem for many applications, since it could minimize the need for shielding or other system hardening techniques. Part 1 describes the basic mechanisms of radiation effects on electronic materials, devices, and integrated circuits. Radiation effects in bulk silicon and in silicon devices are treated. Ionizing radiation effects in silicon dioxide films and silicon MOS devices are discussed. Single event phenomena are considered. Key literature references and a bibliography are provided. Part II provides tabulations of dose enhancement factors for electronic devices in x-ray and gamma-ray environments. The data are applicable to a wide range of semiconductor devices and selected types of capacitors. Radiation environments discussed find application in system design and in radiation test facilities

  16. A radiation-hardened 1K-bit dielectrically isolated random access memory

    International Nuclear Information System (INIS)

    Sandors, T.J.; Boarman, J.W.; Kasten, A.J.; Wood, G.M.

    1982-01-01

    Dielectric Isolation has been used for many years as the bipolar technology for latch-up free, radiation hardened integrated circuits in strategic systems. The state-of-the-art up to this point has been the manufacture of MSI functions containing a maximum of several hundred isolated components. This paper discusses a 1024 Bit Random Access Memory chip containing over 4000 dielectrically isolated components which has been designed for strategic radiation environments. The process utilized and the circuit design of the 1024 Bit RAM have been previously discussed. The techniques used are similar to those employed for the MX digital integrated circuits except for specific items required to make this a true LSI technology. These techniques, along with electrical and radiation data for the RAM, are presented

  17. Radiation effects on microelectronics in space

    International Nuclear Information System (INIS)

    Srour, J.R.; McGarrity, J.M.

    1988-01-01

    The basic mechanisms of space radiation effects on microelectronics are reviewed in this paper. Topics discussed include the effects of displacement damage and ionizing radiation on devices and circuits, single event phenomena, dose enhancement, radiation effects on optoelectronic devices and passive components, hardening approaches, and simulation of the space radiation environment. A summary is presented of damage mechanisms that can cause temporary or permanent failure of devices and circuits operating in space

  18. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  19. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  20. Process for hardening an alkyd resin composition using ionizing radiation. [electron beams, gamma radiation

    Energy Technology Data Exchange (ETDEWEB)

    Watanabe, T; Murata, K; Maruyama, T

    1969-11-27

    In an alkyd resin composition having free hydroxide radicals and containing a conjugated unsaturated fatty acid and/or oil as a component thereof, a process for hardening an alkyd resin composition comprises the steps of dissolving into a vinyl monomer, the product obtained by the semi-esterification reaction of said hydroxide radicals with acid anhydrides having polymerizable radicals and hardening by ionizing radiation to provide a coating with a high degree of cross-linking, with favorable properties such as toughness, hardness, chemical resistance and resistance to weather and with the feasibility of being applied as the ground and finish coat on metals, wood, paper, outdoor construction or the like. Any kind of ionization radiation, particularly accelerated electron beams, ..gamma.. radiation can be used at 50/sup 0/C to -5/sup 0/C for a few seconds or minutes, permitting continuous operation. In one example, 384 parts of phthalic anhydride, 115 parts of pentaerythritol, 233 parts of trimethylol ethane, 288 parts of tung fatty acid and 49 parts of para-tertiary-butyl benzoic acid are mixed and heated with 60 parts of xylene to an acid value of 12. In addition, 271 parts of maleic anhydride and 0.6 parts of hydroquinone are admixed with the content and heated to terminate the reaction. 100 parts of a 50% stylene solution of this alkyd resin are mixed with 1 part of a 60% toluene solution of cobalt naphthenate, and then coated on a glass plate and irradiated with high energy electron beams of 300 kV with a dose of 5 Mrad for 1 sec.

  1. Technological parameter and experimental set-up influences on latch-up triggering level in bulk CMOS device

    International Nuclear Information System (INIS)

    Dubuc, J.P.; Azais, B.; Murcia, M. de

    1994-01-01

    This paper deals with experimental and simulation results on latch-up triggered by an electrical or X-rays pulse in CMOS/bulk devices. Test condition influences as well as the great importance of process parameters on latch-up immunity are emphasized. (author). 10 refs., 19 figs., 1 tab

  2. Micro-scale characterization of a CMOS-based neutron detector for in-phantom measurements in radiation therapy

    Science.gov (United States)

    Arbor, Nicolas; Higueret, Stephane; Husson, Daniel

    2018-04-01

    The CMOS sensor AlphaRad has been designed at the IPHC Strasbourg for real-time monitoring of fast and thermal neutrons over a full energy spectrum. Completely integrated, highly transparent to photons and optimized for low power consumption, this sensor offers very interesting characteristics for the study of internal neutrons in radiation therapy with anthropomorphic phantoms. However, specific effects related to the CMOS metal substructure and to the charge collection process of low energy particles must be carefully estimated before being used for medical applications. We present a detailed characterization of the AlphaRad chip in the MeV energy range using proton and alpha micro-beam experiments performed at the AIFIRA facility (CENBG, Bordeaux). Two-dimensional maps of the charge collection were carried out on a micro-metric scale to be integrated into a Geant4 Monte Carlo simulation of the system. The gamma rejection, as well as the fast and thermal neutrons separation, were studied using both simulation and experimental data. The results highlight the potential of a future system based on CMOS sensor for in-phantom neutron detection in radiation therapies.

  3. Effect of Pigment Colouring on Physico-mechanical Properties of Hardened Cement Paste and Response of Colour Intensity to UV Radiation

    International Nuclear Information System (INIS)

    Khattab, M.M.; Abdel-Rahman, H.A.; Hassan, M.S.

    2010-01-01

    In this work, different ratios of pigment colour was mixed with cement paste during mixing. The pigment colour used was Phthalocyanine Green. The effect of pigment colouring on hardened cement paste (HCP) was characterized in terms of compressive strength, IR spectroscopic analysis and X-ray diffraction. In addition, the effect of UV radiation on the colour strength of hardened cement paste/pigment colour composites was investigated. The results indicated that the increase in the ratio of pigment colour was accompanied with a slight decrease in the values of compressive strength. The exposure of the coloured hardened cement paste to UV radiation for long lengths of time causes a little effect on the colour intensity

  4. Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

    International Nuclear Information System (INIS)

    Brucker, G.J.; Heagerty, W.

    1976-01-01

    This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

  5. Linear devices in combined high-level radiation environments

    International Nuclear Information System (INIS)

    van Vonno, N.W.

    1987-01-01

    The design of precision analog integrated circuits for use in combined high-level radiation environments has traditionally been on a full-custom basis. The use of semicustom design methods has become prevalent in digital devices, with standard cell libraries and gate arrays readily available from multiple vendors. This paper addresses the application of semicustom design techniques to analog parts. In all cases the emphasis is on bipolar technology, since this provides an optimal combination of precision and radiation hardness. A mixed mode analog/digital (A/D) cell family for implementing semicustom designs is described, together with the fabrication process used. Specific processing and design methods are used to provide circuit hardness against neutron, total gamma dose, and transient gamma environments. Semicustom mixed analog/digital design is seen as an appropriate methodology for implementation of medium-performance mixed mode functions for radiation-hardened applications. This leads to trade-offs in process complexity and performance. Full custom design remains necessary for demanding applications such as high-speed A/D conversion and associated sample/hold functions. An A/D cell family optimized for hardness is described, together with the bipolar process used to implement it

  6. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  7. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  8. Absorbed dose by a CMOS in radiotherapy

    International Nuclear Information System (INIS)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  9. Proposed radiation hardened mobile vehicle for Chernobyl dismantlement and nuclear accident response

    International Nuclear Information System (INIS)

    Rowland, M.S.; Holliday, M.A.; Karpachov, J.A.

    1995-01-01

    Researchers are developing a radiation hardened, Telerobotic Dismantling System (TDS) to remediate the Chernobyl facility. To withstand the severe radiation fields, the robotic system, will rely on electrical motors, actuators, and relays proven in the Chernobyl power station. Due to its dust suppression characteristics and ability to cut arbitrary materials the authors propose using a water knife as the principle tool to slice up the large fuel containing masses. The front end of the robot will use a minimum number of moving parts by locating most of the susceptible and bulky components outside the work area. Hardened and shielded video cameras will be designed for remote control and viewing of the robotic functions. Operators will supervise and control robot movements based on feedback from a suite of sensory systems that would include vision systems, radiation detection and measurement systems and force reflection systems. A gripper will be instrumented with a variety of sensors (e.g. force, torque, or tactile), allowing varying debris surface properties to be grasped. The gripper will allow the operator to manipulate and segregate debris items without entering the radiologically and physically dangerous dismantlement operations area. The robots will initially size reduce the FCM's to reduce the primary sources of the airborne radionuclides. The robot will then remove the high level waste for packaging or decontamination, and storage nearby

  10. Radiation-hardened microwave communications system

    International Nuclear Information System (INIS)

    Smith, S.F.; Crutcher, R.I.; Vandermolen, R.I.

    1990-01-01

    The consolidated fuel reprocessing program (CFRP) at the Oak Ridge National Laboratory (ORNL) has been developing signal transmission techniques and equipment to improve the efficiency of remote handling operations for nuclear applications. These efforts have been largely directed toward the goals of (a) remotely controlling bilateral force-reflecting servomanipulators for dexterous manipulation-based operations in remote maintenance tasks and (b) providing television viewing of the work site. In September 1987, developmental microwave transceiving hardware operating with dish antennas was demonstrated in the advanced integrated maintenance system (AIMS) facility at ORNL, successfully implementing both high-quality one-way television transmissions and simultaneous bidirectional digital control data transmissions with very low error rates. Initial test results based on digital transmission at a 1.0-Mbaud data rate indicated that the error rates of the microwave system were comparable to those of a hardwired system. During these test intervals, complex manipulator operations were performed, and the AIMS transporter was moved repeatedly without adverse effects on data integrity. Results of these tests have been factored into subsequent phases of the development program, with an ultimate goal of designing a fully radiation-hardened microwave signal transmission system for use in nuclear facilities

  11. Radiation hardening at 77 K in Zn and Cu single crystals at low doses

    International Nuclear Information System (INIS)

    Gonzalez, H.C.; Bisogni, E.A.

    1980-01-01

    There is controversy about radiation hardening phenomenon and its additivity with other hardening mechanisms. The purpose of this work is to contribute to the understanding of this subject, through measurements made in Zn and Cu single crystals. Post-irradiation measurements of yield stress of Zn, made on different single crystals, show a direct proportionality to the 0.5 power of the dose. It is determined that for a dose greater than 3.7 x 10 16 neutrons cm -2 s -1 there is always cleavage. The maximum critical resolved shear stress measured is about 8.82 MPa. In order to study additivity it is necessary to lower experimental errors. A micro tensile machine is designed to operate in the CNEA facility RA1 in a bath of liquid N 2 . Experimental measurements of yield stress with dose are carried out in-situ on the same single crystals. Experimental results on Cu and Zn show that radiation induced yield stress increases with a 0.5 power law. It must be taken into account that the definition of radiation induced yield stress stands for radiation created obstacles operating alone. The radiation induced yield stress adds algebraically to the athermal component of the initial yield stress but is not exactly additive to the other thermally activated mechanisms. A gradual transition from one to the other type of obstacles is observed. (author)

  12. Simulations of depleted CMOS sensors for high-radiation environments

    CERN Document Server

    Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

    2017-01-01

    After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

  13. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  14. Depleted CMOS pixels for LHC proton–proton experiments

    International Nuclear Information System (INIS)

    Wermes, N.

    2016-01-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  15. Effects of total dose of ionizing radiation on integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Silveira, Marcilei A.G.; Cirne, K.H.; Gimenez, S.; Santos, R.B.B. [Centro Universitario da FEI, Sao Bernardo do Campo, SP (Brazil); Added, N.; Barbosa, M.D.L.; Medina, N.H.; Tabacniks, M.H. [Universidade de Sao Paulo (IF/USP), SP (Brazil). Inst. de Fisica; Lima, J.A. de; Seixas Junior, L.E.; Melo, W. [Centro de Tecnologia da Informacao Paulo Archer, Sao Paulo, SP (Brazil)

    2011-07-01

    Full text: The study of ionizing radiation effects on materials used in electronic devices is of great relevance for the progress of global technological development and, particularly, it is a necessity in some strategic areas in Brazil. Electronic circuits are strongly influenced by radiation and the need for IC's featuring radiation hardness is largely growing to meet the stringent environment in space electronics. On the other hand, aerospace agencies are encouraging both scientific community and semiconductors industry to develop hardened-by-design components using standard manufacturing processes to achieve maximum performance, while significantly reducing costs. To understand the physical phenomena responsible for changes in devices exposed to ionizing radiation several kinds of radiation should then be considered, among them alpha particles, protons, gamma and X-rays. Radiation effects on the integrated circuits are usually divided into two categories: total ionizing dose (TID), a cumulative dose that shifts the threshold voltage and increases transistor's off-state current; single events effects (SEE), a transient effect which can deposit charge directly into the device and disturb the properties of electronic circuits. TID is one of the most common effects and may generate degradation in some parameters of the CMOS electronic devices, such as the threshold voltage oscillation, increase of the sub-threshold slope and increase of the off-state current. The effects of ionizing radiation are the creation of electron-hole pairs in the oxide layer changing operation mode parameters of the electronic device. Indirectly, there will be also changes in the device due to the formation of secondary electrons from the interaction of electromagnetic radiation with the material, since the charge carriers can be trapped both in the oxide layer and in the interface with the oxide. In this work we have investigated the behavior of MOSFET devices fabricated with

  16. A Radiation-Hard Analog Memory In The AVLSI-RA Process

    International Nuclear Information System (INIS)

    Britton, C.L. Jr.; Wintenberg, A.L.; Read, K.F.; Simpson, M.L.; Young, G.R.; Clonts, L.G.; Kennedy, E.J.; Smith, R.S.; Swann, B.K.; Musser, J.A.

    1995-01-01

    A radiation hardened analog memory for an Interpolating Pad Camber has been designed at Oak Ridge National Laboratory and fabricated by Harris Semiconductor in the AVLSI-RA CMOS process. The goal was to develop a rad-hard analog pipeline that would deliver approximately 9-bit performance, a readout settling time of 500ns following read enable, an input and output dynamic range of +/-2.25V, a corrected rms pedestal of approximately 5mV or less, and a power dissipation of less than 10mW/channel. The pre- and post-radiation measurements to 5MRad are presented

  17. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    International Nuclear Information System (INIS)

    Kim, Y; Pham, C; Chang, J P

    2015-01-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  18. Nano-electromechanical switch-CMOS hybrid technology and its applications.

    Science.gov (United States)

    Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

    2011-01-01

    Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

  19. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    CERN Document Server

    Miucci, A; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; Rosa, A.La; Muenstermann, D.; George, M.; Grosse-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J.C.; Liu, J; Barbero, M.; Rozanov, A

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. 1Corresponding author. c CERN 2014, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/9/05/C050642014 JINST 9 C05064 A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation a...

  20. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  1. JPL CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  2. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  3. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  4. Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

    Directory of Open Access Journals (Sweden)

    Liang Zhou

    2015-10-01

    Full Text Available This paper proposes a radiation hardened NULL Convention Logic (NCL architecture that can recover from a single event latchup (SEL or single event upset (SEU fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.

  5. A mixed analog-digital radiation hard technology for high energy physics electronics DMILL (Durci Mixte sur Isolant Logico-Linéaire)

    CERN Document Server

    Beuville, E; Borgeaud, P; Fourches, N T; Rouger, M; Blanc, J P; Bruel, M; Delevoye-Orsier, E; Gautier, J; Du Port de Pontcharra, J; Truche, R; Dupont-Nivet, E; Flament, O; Leray, J L; Martin, J L; Montaron, J; Borel, G; Brice, J M; Chatagnon, P; Terrier, C; Aubert, Jean-Jacques; Delpierre, P A; Habrard, M C; Potheau, R; CERN. Geneva. Detector Research and Development Committee

    1992-01-01

    The high radiation level expected in the inner regions of the high luminosity LHC detectors (gamma and neutron) will require radiation hardened electronics. A consortium between the CEA (Commissariat a l'Energie Atomique) and Thomson TMS (Thomson Composants Militaires et Spatiaux) has been created to push for the development and the industrialization of a nascent technology which looks particularly adapted to the needs of HEP electronics. This technology, currently under development at the LETI(CEA), uses a SIMOX substrate with an epitaxial silicon film. It includes CMOS, JFETs and vertical bipolar transistors with a potential multi-megarad hardness. The CMOS and bipolar transistors constitute a rad-hard BiCMOS which will be useful to design analog and digital high-speed architectures. JFETs, which have intrinsically high hardness behaviour and low noise performances even at low temperature will enable very rad-hard, low noise front end electronics to be designed. Present results, together with the improvemen...

  6. Environmental hardening of a mobile-manipulator system for nuclear environments

    International Nuclear Information System (INIS)

    Jones, S.L.; Cable, T.; Tulenko, J.S.; Toshkov, S.; Sias, F.R. Jr.

    1993-01-01

    This research report discusses the radiation hardening of a commercially available mobile robot, the REMOTEC ANDROS. This hardening effort is culminating in the availability of a megarad hardened mobile platform to access areas in nuclear facilities with extremely high levels of radiation (0.1 to 1 Mrad). These radiation levels may be encountered both during routine repair and monitoring activities and accident situations. The project has completed a phase-I U.S. Department of Energy Small Business Innovative Research contract and is now in a phase-II effort with completion scheduled in early 1995. The research involves the evaluation of the material and electrical components of an ANDROS robot to determine the anticipated radiation hardness of the current production version and evaluation of the components that must be replaced or modified to harden the system to higher radiation levels. The work being reported is based on an evaluation of the complete list of all electronic, electrical, and mechanical parts used in the robot and includes initial experimental radiation evaluations performed at the University of Florida

  7. Digital characteristics of CMOS devices at cryogenic temperatures

    International Nuclear Information System (INIS)

    Deen, M.J.

    1989-01-01

    This paper presents the results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and a supply voltage between 3 and 20 V. Using a fixed supply of 5 V, the low noise margin (NM L decreased from 2.54 to 2.11 V, but the high noise margin NM H ) increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V 1L and V 1H increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity, V H - V L , and V 1H - V 1L all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained as due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β N /β rho ratio as the temperature is lowered

  8. Radiation emitting devices regulations

    International Nuclear Information System (INIS)

    1970-01-01

    The Radiation Emitting Devices Regulations are the regulations referred to in the Radiation Emitting Devices Act and relate to the operation of devices. They include standards of design and construction, standards of functioning, warning symbol specifications in addition to information relating to the seizure and detention of machines failing to comply with the regulations. The radiation emitting devices consist of the following: television receivers, extra-oral dental x-ray equipment, microwave ovens, baggage inspection x-ray devices, demonstration--type gas discharge devices, photofluorographic x-ray equipment, laser scanners, demonstration lasers, low energy electron microscopes, high intensity mercury vapour discharge lamps, sunlamps, diagnostic x-ray equipment, ultrasound therapy devices, x-ray diffraction equipment, cabinet x-ray equipment and therapeutic x-ray equipment

  9. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  10. Thermal annealing response following irradiation of a CMOS imager for the JUICE JANUS instrument

    Science.gov (United States)

    Lofthouse-Smith, D.-D.; Soman, M. R.; Allanwood, E. A. H.; Stefanov, K. D.; Holland, A. D.; Leese, M.; Turne, P.

    2018-03-01

    ESA's JUICE (JUpiter ICy moon Explorer) spacecraft is an L-class mission destined for the Jovian system in 2030. Its primary goals are to investigate the conditions for planetary formation and the emergence of life, and how does the solar system work. The JANUS camera, an instrument on JUICE, uses a 4T back illuminated CMOS image sensor, the CIS115 designed by Teledyne e2v. JANUS imager test campaigns are studying the CIS115 following exposure to gammas, protons, electrons and heavy ions, simulating the harsh radiation environment present in the Jovian system. The degradation of 4T CMOS device performance following proton fluences is being studied, as well as the effectiveness of thermal annealing to reverse radiation damage. One key parameter for the JANUS mission is the Dark current of the CIS115, which has been shown to degrade in previous radiation campaigns. A thermal anneal of the CIS115 has been used to accelerate any annealing following the irradiation as well as to study the evolution of any performance characteristics. CIS115s have been irradiated to double the expected End of Life (EOL) levels for displacement damage radiation (2×1010 protons, 10 MeV equivalent). Following this, devices have undergone a thermal anneal cycle at 100oC for 168 hours to reveal the extent to which CIS115 recovers pre-irradiation performance. Dark current activation energy analysis following proton fluence gives information on trap species present in the device and how effective anneal is at removing these trap species. Thermal anneal shows no quantifiable change in the activation energy of the dark current following irradiation.

  11. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  12. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Ristic, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

  13. Radiation hardening revisited: Role of intracascade clustering

    DEFF Research Database (Denmark)

    Singh, B.N.; Foreman, A.J.E.; Trinkaus, H.

    1997-01-01

    be explained in terms of conventional dispersed-barrier hardening because (a) the grown-in dislocations are not free, and (b) irradiation-induced defect clusters are not rigid indestructible Orowan obstacles. A new model called 'cascade-induced source hardening' is presented where glissile loops produced...... directly in cascades are envisaged to decorate the grown-in dislocations so that they cannot act as dislocation sources. The upper yield stress is related to the breakaway stress which is necessary to pull the dislocation away from the clusters/loops decorating it. The magnitude of the breakaway stress has...

  14. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  15. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  16. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  17. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  18. Radiation emitting devices act

    International Nuclear Information System (INIS)

    1970-01-01

    This Act, entitled the Radiation Emitting Devices Act, is concerned with the sale and importation of radiation emitting devices. Laws relating to the sale, lease or import, labelling, advertising, packaging, safety standards and inspection of these devices are listed as well as penalties for any person who is convicted of breaking these laws

  19. Neutron absorbed dose in a pacemaker CMOS

    International Nuclear Information System (INIS)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  20. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  1. Total ionizing dose radiation hardness of the ATLAS MDT-ASD and the HP-Agilent 0.5 um CMOS process

    CERN Document Server

    Posch, C

    2002-01-01

    A total ionizing dose (TID) test of the MDT-ASD, the ATLAS MDT front-end chip has been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5 um CMOS process (AMOS14TB). The accumulated TID at the end of the test was 300 krad, delivered by 160 MeV protons at a rate of approximately 70 rad/sec. All 10 irradiated chips retained their full functionality and performance and showed only irrelevantly small changes in device parameters. As the total accumulated dose is substantially higher than the relevant ATLAS Radiation Tolerance Criteria (RTCtid), the results of this test indicate that MDT-ASD meets the ATLAS TID radiation hardness requirements. In addition, the results of this test correspond well with results of a 30 keV gamma TID irradiation test performed by us on an earlier prototype at the CERN x-ray facility as well as with results of other irradiation test on this process found in literature.

  2. A simple method to identify radiation and annealing biases that lead to worst-case CMOS static RAM postirradiation response

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Dressendorfer, P.V.

    1987-01-01

    The authors illustrate a simple method to identify bias conditions that lead to worst-case postirradiation speed and timing response for SRAMs. Switching cell states between radiation and anneal should lead to maximum speed and timing degradation for many hardened designs and technologies. The greatest SRAM cell imbalance is also established by these radiation and annealing conditions for the hardened and commercial parts that we have examined. These results should provide insight into the behavior of SRAMs during and after irradiation. The results should also be useful to establishing guidelines for integrated-circuit functionality testing, and SEU and dose-rate upset testing, after total-dose irradiation

  3. Why semiconductors must be hardened when used in space

    International Nuclear Information System (INIS)

    Winokur, P.S.

    2000-01-01

    The natural space radiation environment presents a great challenge to present and future satellite systems with significant assets in space. Defining requirements for such systems demands knowledge about the space radiation environment and its effects on electronics and optoelectronics technologies, as well as suitable risk assessment of the uncertainties involved. For mission of high radiation levels, radiation-hardened integrated circuits will be required to preform critical mission functions. The most successful systems in space will be those that are best able to blend standard commercial electronics with custom radiation-hardened electronics in a mix that is suitable for the system of interest

  4. Design Features of Hardening Turners with Outstripping Plastic Deformation

    Directory of Open Access Journals (Sweden)

    V. M. Yaroslavtsev

    2014-01-01

    Full Text Available An efficiency of the cutting method with outstripping plastic deformation (OPD in lathe works is defined in many respects by design features of the add-on devices for mechanical hardening of a cut-off layer material in the course of cutting. Applied on lathes, deforming OPD devices can have differing dimensions, placement on the lathe, drive type (manual, electric, hydraulic, pneumatic, pneumohydraulic, electromagnetic, and autonomy degree towards the metalcutting equipment and industrial equipment.At the same time there are a number of inherent design features of work-hardening devices the modernized lathes with OPD use for machining. Now the OPD standard devices implement two principle construction options: loading device is placed on the machine or on the OPD slide support separate of the tool, or it is structurally aligned with the cutting tool. In the latter case the OPD device for turning is called a tool mandrel, which is mounted in a tool post of the machine or, at large dimensions, such a mandrel is mounted on the machine instead of the tool mandrel.When designing the OPD devices, is important to take into consideration production requirements and recommendations for the technological equipment, developed in the course of creation, working off and introduction of such installations for mechanical hardening of material. In compliance with it, OPD devices, their placement on the machine, and working displacements shouldn't limit technological capabilities of the applied metal-cutting equipment. OPD stresses have to be smoothly regulated, with maximum loads being limited to admissible values for the machine model to be modernized. It is necessary to ensure synchronized longitudinal and cross displacements of the cutting tool and OPD hardener with respect to the axis of billet rotation to enable regulation and readjustment of the hardener and tool placement. It ought to foresee the increased mobile components rigidity and manufacturing

  5. Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

    OpenAIRE

    Tanaka, Masahiro; Omura, Ichiro

    2012-01-01

    Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables t...

  6. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Science.gov (United States)

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  7. Radiation hardened high efficiency silicon space solar cell

    International Nuclear Information System (INIS)

    Garboushian, V.; Yoon, S.; Turner, J.

    1993-01-01

    A silicon solar cell with AMO 19% Beginning of Life (BOL) efficiency is reported. The cell has demonstrated equal or better radiation resistance when compared to conventional silicon space solar cells. Conventional silicon space solar cell performance is generally ∼ 14% at BOL. The Radiation Hardened High Efficiency Silicon (RHHES) cell is thinned for high specific power (watts/kilogram). The RHHES space cell provides compatibility with automatic surface mounting technology. The cells can be easily combined to provide desired power levels and voltages. The RHHES space cell is more resistant to mechanical damage due to micrometeorites. Micro-meteorites which impinge upon conventional cells can crack the cell which, in turn, may cause string failure. The RHHES, operating in the same environment, can continue to function with a similar crack. The RHHES cell allows for very efficient thermal management which is essential for space cells generating higher specific power levels. The cell eliminates the need for electrical insulation layers which would otherwise increase the thermal resistance for conventional space panels. The RHHES cell can be applied to a space concentrator panel system without abandoning any of the attributes discussed. The power handling capability of the RHHES cell is approximately five times more than conventional space concentrator solar cells

  8. A monolithic 180 nm CMOS dosimeter for wireless In Vivo Dosimetry

    International Nuclear Information System (INIS)

    Villani, E.G.; Crepaldi, M.; DeMarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Rosenfeld, A.; Zhang, Z.

    2016-01-01

    The design, fabrication and testing of a novel monolithic system-on-chip dosimeter fabricated in a standard 180 nm CMOS technology is described. The device, implementing a radiation sensor and an RF transmitter, is proposed to address the need for real-time In Vivo Dosimetry (IVD) of radiation during Linac radiotherapy sessions. Owing to its small size, of approximately 1 mm"3, such solution could be made in-body implantable and, as such, provide a much-enhanced high-resolution, real-time dose measurement to improve Quality Assurance (QA) in radiation therapy. The device transmits the related information on dose of radiation wirelessly to a remote receiver operating in the Medical Implant Communication Service (MICS) band. Comprehensive description of the various phases of this project, including the development of the radiation sensors and integrated RF transmitter to perform the readout, along with the final test results using a radiation beam, will be given. - Highlights: • A Monolithic Dosimeter for real time dosimetry during radiotherapy is proposed. • The proposed device is 1 mm3 in size and could potentially be body implantable. • The device includes a radiation sensor and RF readout, operating in the MICS band. • Detailed tests have been performed under radiation beam in a clinical environment. • Reported sensitivity is 1 cGy over 50 Gy, with an accuracy of better than 3%.

  9. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  10. Recent developments with CMOS SSPM photodetectors

    Energy Technology Data Exchange (ETDEWEB)

    Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

    2009-10-21

    Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

  11. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  12. Single-Event Effects in Silicon Carbide Power Devices

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

    2015-01-01

    This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

  13. Characterization of active CMOS pixel sensors on high resistive substrate

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

    2016-07-01

    Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  14. Ionizing Radiation Effects on the Noise of 65 nm CMOS Transistors for Pixel Sensor Readout at Extreme Total Dose Levels

    CERN Document Server

    Re, V.; Manghisoni, M.; Riceputi, E.; Traversi, G.; Ratti, L.

    2018-01-01

    This paper is focused on the study of the noise performance of 65 nm CMOS transistors at extremely high total ionizing dose (TID) levels of the order of several hundreds of Mrad(SiO2). Noise measurements are reported and discussed, analyzing radiation effects on 1/ f noise and channel thermal noise. In nMOSFETs, up to 10 Mrad(SiO2), the experimental behavior is consistent with a damage mechanism mainly associ- ated with lateral isolation oxides, and can be modeled by parasitic transistors turning on after irradiation and contributing to the total noise of the device. At very high dose, these parasitic transistors tend to be turned off by negative charge accumulating in interface states and compensating radiation-induced positive charge building up inside thick isolation oxides. Effects associated with ionization and hydrogen transport in spacer oxides may become dominant at 600 Mrad(SiO2) and may explain the observed noise behavior at extremely high TID. The results of this analysis provide an understanding o...

  15. Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

    2017-08-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

  16. Proton Radiation Effects on Dark Signal Distribution of PPD CMOS Image Sensors: Both TID and DDD Effects.

    Science.gov (United States)

    Xue, Yuanyuan; Wang, Zujun; Chen, Wei; Liu, Minbo; He, Baoping; Yao, Zhibin; Sheng, Jiangkun; Ma, Wuying; Dong, Guantao; Jin, Junshan

    2017-11-30

    Four-transistor (T) pinned photodiode (PPD) CMOS image sensors (CISs) with four-megapixel resolution using 11µm pitch high dynamic range pixel were radiated with 3 MeV and 10MeV protons. The dark signal was measured pre- and post-radiation, with the dark signal post irradiation showing a remarkable increase. A theoretical method of dark signal distribution pre- and post-radiation is used to analyze the degradation mechanisms of the dark signal distribution. The theoretical results are in good agreement with experimental results. This research would provide a good understanding of the proton radiation effects on the CIS and make it possible to predict the dark signal distribution of the CIS under the complex proton radiation environments.

  17. CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko, E-mail: thirono@uni-bonn.de [Physikalisches Institute der Universität Bonn, Bonn (Germany); Barbero, Marlon; Breugnon, Patrick; Godiot, Stephanie [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Gonella, Laura; Hemperek, Tomasz; Hügging, Fabian; Krüger, Hans [Physikalisches Institute der Universität Bonn, Bonn (Germany); Liu, Jian; Pangaud, Patrick [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Peric, Ivan [IPE, Karlsruher Institut für Technologie, Karlsruhe (Germany); Pohl, David-Leon [Physikalisches Institute der Universität Bonn, Bonn (Germany); Rozanov, Alexandre [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Rymaszewski, Piotr [Physikalisches Institute der Universität Bonn, Bonn (Germany); Wang, Anqing [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Wermes, Norbert [Physikalisches Institute der Universität Bonn, Bonn (Germany)

    2016-09-21

    A depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150 nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166 μm and 80 μm. We report the results obtained with the prototype fabricated in this technology.

  18. Radiation hardening: study of production velocity and post-irradiation recovery of defect clusters produced by neutron irradiation at 77 K

    International Nuclear Information System (INIS)

    Gonzalez, Hector C.; Miralles, Monica T.

    1999-01-01

    This work includes three basic studies using radiation hardening of Cu single crystals irradiated at 77 K in the RA-1-reactor of CNEA: 1) The initial of a production curve of defect clusters originated during radiation until 5.2 x 10 20 n m 2 . The shape of the curve is compared with those obtained from measurement of resistivity increased (Δρ) with neutronic doses (φt) and the acceptance of the linear dependency of Δρ with Frenkel Pairs concentration (PFs); 2) The isochronal hardening recovery in the temperature interval of stage V (T > 450 K). The existence of the sub-stages Vb (∼ 550 K) and Vc (∼ 587 K), determined for the first time from hardening measurements, are shown and compared with results obtained by other techniques; 3) Isothermal recoveries performed in the temperature interval of the sub-stage Vc to determine phenomenologically the apparent activation energy of the sub-stage. The value obtained was in agreement with the energy for Cu vacancies auto diffusion. (author)

  19. CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

    CERN Document Server

    Manazza, A; Manghisoni, M; Re, V; Traversi, G; Bettarini, S; Forti, F; Morsani, F; Rizzo, G; 10.1109/TNS.2014.2299341

    2014-01-01

    This work presents the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous, vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for application of the experiments at the future high luminosity colliders, is provided through the characterization of the prototypes, including tests with infrared (IR) laser, 55Fe and 90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance.

  20. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  1. Paint and binding material to be hardened by ionizing radiations

    International Nuclear Information System (INIS)

    Johnson, O.B.; Labana, S.S.

    1976-01-01

    The invention concerns a paint binding material which can be hardened due to the effect of ionising radiation, consisting of a dispersion of a) an ethylene unsaturated material in b) at least one vinyl monomer. Component (a) is a reaction product of graded rubber particles (0.1 - 4 μm) and an ethylene unsaturated component with a reactive epoxy-, hydroxy- or carbonyl-group, which is connected to the rubber by ester or urethane links. The rubber particles have a core of cross linked elastomer acrylic polymers, an outer shell of reactive groups and an intermediate layer made from the core monomer and the shell. 157 examples explain the manufacturing process. The paint is suitable for covering articles which will later be subject to distortion. (UWI) [de

  2. Efficient, radiation-hardened, 800-keV neutral beam injection system

    International Nuclear Information System (INIS)

    Anderson, O.A.; Cooper, W.S.; Goldberg, D.A.; Ruby, L.; Soroka, L.; Fink, J.H.

    1982-10-01

    Recent advances and new concepts in negative ion generation, transport, acceleration, and neutrailzation make it appear likely that an efficient, radiation-hardened neutral beam injection system could be developed in time for the proposed FED-A tokamak. These new developments include the operation of steady-state H - ion sources at over 5 A per meter of source length, the concept of using strong-focussing electrostatic structures for low-gradient dc acceleration of high-current sheet beams of negative ions and the transport of these beams around corners, and the development of powerful oxygen-iodine chemical lasers which will make possible the efficient conversion of the negative ions to neutrals using a photodetachment scheme in which the ion beam passes through the laser cavity

  3. Pattern imprinting in CMOS static RAMs from Co-60 irradiation

    International Nuclear Information System (INIS)

    Schott, J.T.; Zugich, M.H.

    1987-01-01

    Total dose irradiation of various CMOS SRAMs is shown to imprint the pattern stored in the memory during irradiation. This imprinted pattern is the preferred state of the memory at subsequent power-up. Imprinting can occur at dose levels significantly below the failure level of the devices and is consistent with the bias dependent radiation induced threshold shifts of the individual transistors of the memory cells. However, before total imprinting occurs, other unusual imprinting phenomena can occur, such as a reverse imprinting effect seen in SOS memories, which is probably related to the bias dependence of back-channel leakage

  4. Backside illuminated CMOS-TDI line scan sensor for space applications

    Science.gov (United States)

    Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

    2018-05-01

    A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

  5. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  6. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  7. Radiation Effects in Carbon Nanoelectronics

    Directory of Open Access Journals (Sweden)

    Cory D. Cress

    2012-07-01

    Full Text Available We experimentally investigate the effects of Co-60 irradiation on the electrical properties of single-walled carbon nanotube and graphene field-effect transistors. We observe significant differences in the radiation response of devices depending on their irradiation environment, and confirm that, under controlled conditions, standard dielectric hardening approaches are applicable to carbon nanoelectronics devices.

  8. Radiation analysis devices, radiation analysis methods, and articles of manufacture

    Science.gov (United States)

    Roybal, Lyle Gene

    2010-06-08

    Radiation analysis devices include circuitry configured to determine respective radiation count data for a plurality of sections of an area of interest and combine the radiation count data of individual of sections to determine whether a selected radioactive material is present in the area of interest. An amount of the radiation count data for an individual section is insufficient to determine whether the selected radioactive material is present in the individual section. An article of manufacture includes media comprising programming configured to cause processing circuitry to perform processing comprising determining one or more correction factors based on a calibration of a radiation analysis device, measuring radiation received by the radiation analysis device using the one or more correction factors, and presenting information relating to an amount of radiation measured by the radiation analysis device having one of a plurality of specified radiation energy levels of a range of interest.

  9. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

    2016-01-01

    . The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

  10. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Science.gov (United States)

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  11. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  12. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  13. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    International Nuclear Information System (INIS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-01-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10 14 cm −2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation

  14. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  15. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  16. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    Science.gov (United States)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  17. High-temperature complementary metal oxide semiconductors (CMOS)

    International Nuclear Information System (INIS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  18. 4T CMOS Active Pixel Sensors under Ionizing Radiation

    NARCIS (Netherlands)

    Tan, J.

    2013-01-01

    This thesis investigates the ionizing radiation effects on 4T pixels and the elementary in-pixel test devices with regard to the electrical performance and the optical performance. In addition to an analysis of the macroscopic pixel parameter degradation, the radiation-induced degradation mechanisms

  19. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  20. Radiation Hardened Telerobotic Dismantling System Development Final Report CRADA No. TC-1340-96

    Energy Technology Data Exchange (ETDEWEB)

    Smith, C. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Lightman, A. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2017-09-27

    This project was a collaborative effort between the University of California, LLNL and RedZone Robotics, Inc. for the development of radiation-hardened telerobotic dismantling systems for use in applications such as nuclear facility remediation, nuclear accident response, and Chemobyltype remediation. The project supported the design, development, fabrication and testing of a Ukrainian robotic systems. The project was completed on time and within budget. All deliverables were completed. The final project deliverables were consistent with the plans developed in the original project with the exception that the fabricated systems remained in Ukraine.

  1. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    Science.gov (United States)

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. The use of microhardness tests to determine the radiation hardening of austenitic stainless steel; Zastosowanie pomiarow mikrotwardosci dla okreslenia umocnienia radiacyjnego stali austenitycznej napromienionej neutronami

    Energy Technology Data Exchange (ETDEWEB)

    Hofman, A.; Kochanski, T.; Malczyk, A.

    1994-12-31

    The use of microhardness technique to determine the radiation hardening has been studied. Microhardness measurements have been conducted on austenitic stainless steel OH18N1OT irradiated up to 2x10{sup 19} ncm{sup -2}. It was determined that the increase in microhardness varies directly with the measured increase in the 0.2% offset yield strength and has been found that microhardness technique may be an effective tool to measurements of radiation induced hardening. (author). 18 refs, 3 figs, 3 tabs.

  3. COTS – Harsh Condition Effects Considerations from Technology to User Level

    Directory of Open Access Journals (Sweden)

    Kirsten Weide-Zaage

    2017-08-01

    Full Text Available Radiation hardened devices are mostly extremely expensive. The continuously downscaling of microelectronic structures and the unavoidable presence of particle radiation on ground and in space leads to unwanted failures in electronic devices. Furthermore it is expected that in the next few years around 8000 new satellites will be launched around the world. Due to the enormous increasing need for Rad-Hard devices, there will be more focus on Commercial Of The Shelf (COTS devices, which costs are lower. Also nowadays microelectronics for automotive systems are tested to withstand radiation especially SEU-single event upsets. It is clear that SEU cannot be ignored anymore especially in the application of unmanned autonomous vehicles and systems. Reliability testing is expensive and extremely time consuming. The use of COTS-Commercials of the shelf is the ultimate goal to reach. In this paper, an overview of radiation effects on different CMOS technologies used in COTS devices is given. These effects can be considered while selecting different functional equivalent COTS devices implemented with different technologies. Moreover, an overview of software techniques used in programmable commercial devices to reduce the radiation effects is also described.

  4. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-01-01

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

  5. A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2001-01-01

    An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 1...

  6. A large dynamic range radiation tolerant analog memory in a quarter micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2000-01-01

    A 8*128 cell analog memory prototype has been designed in a commercial 0.25 jam CMOS process. The aim of this work was to investigate the possibility of designing large dynamic range mixed- mode switched capacitor circuits for High-Energy Physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant left bracket 1 right bracket . The memory cells employ gate-oxide capacitors for storage, allowing for a very high density. A voltage write - voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (V//D//D = 2.5 V), with a linearity of at least 7.5 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is plus or minus 0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after lOMrd (...

  7. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  8. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  9. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  10. Investigation of epitaxial silicon layers as a material for radiation hardened silicon detectors

    International Nuclear Information System (INIS)

    Li, Z.; Eremin, V.; Ilyashenko, I.; Ivanov, A.; Verbitskaya, E.

    1997-12-01

    Epitaxial grown thick layers (≥ 100 micrometers) of high resistivity silicon (Epi-Si) have been investigated as a possible candidate of radiation hardened material for detectors for high-energy physics. As grown Epi-Si layers contain high concentration (up to 2 x 10 12 cm -3 ) of deep levels compared with that in standard high resistivity bulk Si. After irradiation of test diodes by protons (E p = 24 GeV) with a fluence of 1.5 x 10 11 cm -2 , no additional radiation induced deep traps have been detected. A reasonable explanation is that there is a sink of primary radiation induced defects (interstitial and vacancies), possibly by as-grown defects, in epitaxial layers. The ''sinking'' process, however, becomes non-effective at high radiation fluences (10 14 cm -2 ) due to saturation of epitaxial defects by high concentration of radiation induced ones. As a result, at neutron fluence of 1 x 10 14 cm -2 the deep level spectrum corresponds to well-known spectrum of radiation induced defects in high resistivity bulk Si. The net effective concentration in the space charge region equals to 3 x 10 12 cm -3 after 3 months of room temperature storage and reveals similar annealing behavior for epitaxial as compared to bulk silicon

  11. Development of a hardened X-ray imager for the Megajoule Laser radiative environment

    International Nuclear Information System (INIS)

    Rousseau, A.

    2014-01-01

    Thermonuclear fusion experiments are led on Megajoule class laser facility by imploding a capsule filled with Deuterium and Tritium. In this context, it is necessary to diagnose the core size and the shape of the compressed target in order to provide valuable information and identify reasons for failure. State of the art X-ray imaging diagnostics cannot realize measurements without being perturbed by the nuclear background. The diagnostic that has been designed in this thesis combine high spatial resolution X-ray imaging at high energy and radiation tolerance to nuclear background. We have first guaranteed, theoretically and experimentally, survivability of X ray multilayer coating to energetic neutrons irradiation. Consequently, we have design the X-ray imaging system in order to achieve 5 μm resolution in a spectral range up to 95 keV. The X-ray image has then been converted into visible light in order to be easily transferred through a hardened optical relay to a protected area where the optical analyser is set. This analyser, combining light amplifier and pixelised detector, has also been studied and a novel method has been developed to reduce nuclear related transient perturbations on the device. This by parts design associated with Monte-Carlo Simulation (GEANT4) and experimental campaign on FCI facility (OMEGA) led to a coherent diagnostic architecture which will sustain high level of nuclear perturbation. (author) [fr

  12. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  13. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  14. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  15. Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source

    International Nuclear Information System (INIS)

    Carna, M; Havranek, M; Hejtmanek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Vrba, V

    2014-01-01

    We present a study of radiation effects on MOSFET transistors irradiated with a 60 Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation

  16. CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

    International Nuclear Information System (INIS)

    Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

    2009-01-01

    CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

  17. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  18. Predictions of integrated circuit serviceability in space radiation fields

    Energy Technology Data Exchange (ETDEWEB)

    Khamidullina, N.M.; Kuznetsov, N.V.; Pichkhadze, K.M.; Popov, V.D

    1999-10-01

    The present paper suggests an approach to estimating and predicting the serviceability of on-board electronic equipment. It is based on the postulates of the reliability theory and accounts for total-dose and single-event radiation effects as well as other exterior destabilizing factors. The methods of determination of failure and upset rates for CMOS devices are considered. The probability of non-failure operation of a two CMOS RAM is calculated along the whole trajectory of the 'Solar Probe' spacecraft.

  19. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

  20. Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

    International Nuclear Information System (INIS)

    Anelli, Giovanni Maria

    2000-01-01

    The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

  1. Nanosecond-laser induced crosstalk of CMOS image sensor

    Science.gov (United States)

    Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

    2018-02-01

    The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

  2. DEVELOPMENT AND RESEARCH OF ULTRASONIC OSCILLATORY SYSTEM FOR HARDENING OF SPRING PLATE BILLETS

    Directory of Open Access Journals (Sweden)

    V. A. Tomilo

    2015-01-01

    Full Text Available Various schemes of ultrasonic oscillatory system are developed: with a «force nonsensitive» support, with a «force sensitive» support, with the deforming steel balls in bulk. Results of the ultrasonic treatment showed that hardening of a surface of the samples took place when the vibration amplitude of a radiator exceeds a certain level. The level of hardening increases with increase in amplitude of fluctuations of a radiator. Higher level of hardening is registered when the surface is treated by steel balls.

  3. Radiation effects in optoelectronic devices

    International Nuclear Information System (INIS)

    Barnes, C.E.; Wiczer, J.J.

    1984-05-01

    Purpose of this report is to provide not only a summary of radiation damage studies at Sandia National Laboratories, but also of those in the literature on the components of optoelectronic systems: light emitting diodes (LEDs), laser diodes, photodetectors, optical fibers, and optical isolators. This review of radiation damage in optoelectronic components is structured according to device type. In each section, a brief discussion of those device properties relevant to radiation effects is given

  4. Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology

    CERN Document Server

    Kuczynska, Marika; Bugiel, Szymon; Firlej, Miroslaw; Fiutowski, Tomasz; Idzik, Marek; Michelis, Stefano; Moron, Jakub; Przyborowski, Dominik; Swientek, Krzysztof

    2015-01-01

    A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, w...

  5. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  6. Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

    Science.gov (United States)

    Seco, Joao; Depauw, Nicolas

    2011-02-01

    Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

  7. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  8. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    Science.gov (United States)

    Rimoldi, M.

    2017-12-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

  9. Extracting material response from simple mechanical tests on hardening-softening-hardening viscoplastic solids

    Science.gov (United States)

    Mohan, Nisha

    Compliant foams are usually characterized by a wide range of desirable mechanical properties. These properties include viscoelasticity at different temperatures, energy absorption, recoverability under cyclic loading, impact resistance, and thermal, electrical, acoustic and radiation-resistance. Some foams contain nano-sized features and are used in small-scale devices. This implies that the characteristic dimensions of foams span multiple length scales, rendering modeling their mechanical properties difficult. Continuum mechanics-based models capture some salient experimental features like the linear elastic regime, followed by non-linear plateau stress regime. However, they lack mesostructural physical details. This makes them incapable of accurately predicting local peaks in stress and strain distributions, which significantly affect the deformation paths. Atomistic methods are capable of capturing the physical origins of deformation at smaller scales, but suffer from impractical computational intensity. Capturing deformation at the so-called meso-scale, which is capable of describing the phenomenon at a continuum level, but with some physical insights, requires developing new theoretical approaches. A fundamental question that motivates the modeling of foams is `how to extract the intrinsic material response from simple mechanical test data, such as stress vs. strain response?' A 3D model was developed to simulate the mechanical response of foam-type materials. The novelty of this model includes unique features such as the hardening-softening-hardening material response, strain rate-dependence, and plastically compressible solids with plastic non-normality. Suggestive links from atomistic simulations of foams were borrowed to formulate a physically informed hardening material input function. Motivated by a model that qualitatively captured the response of foam-type vertically aligned carbon nanotube (VACNT) pillars under uniaxial compression [2011,"Analysis of

  10. Stochastic process variation in deep-submicron CMOS circuits and algorithms

    CERN Document Server

    Zjajo, Amir

    2014-01-01

    One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

  11. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. High-energy heavy ion testing of VLSI devices for single event ...

    Indian Academy of Sciences (India)

    Unknown

    per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

  13. Hardening by means of ionising radiation

    International Nuclear Information System (INIS)

    Spoor, H.; Demmler, K.

    1979-01-01

    The polymerisable ethylic unsaturated mixture can be hardened by means of electron irradiation and used as a corrosion preventive layer. The mixture mainly consists of at least a di-olefinic unsaturated polyester, partial esters of polycarbonic acids, in particular the monoester of dicarbonic acids, with a copolymerizable C-C double bond, and mono-olefine unsaturated hydrocarbons, for example vinyl aromatics. The coatings exhibit good adhesion to the substrate, in particular to metal, and good flexibility. (DG) [de

  14. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  15. Radiation area monitor device and method

    Science.gov (United States)

    Vencelj, Matjaz; Stowe, Ashley C.; Petrovic, Toni; Morrell, Jonathan S.; Kosicek, Andrej

    2018-01-30

    A radiation area monitor device/method, utilizing: a radiation sensor; a rotating radiation shield disposed about the radiation sensor, wherein the rotating radiation shield defines one or more ports that are transparent to radiation; and a processor operable for analyzing and storing a radiation fingerprint acquired by the radiation sensor as the rotating radiation shield is rotated about the radiation sensor. Optionally, the radiation sensor includes a gamma and/or neutron radiation sensor. The device/method selectively operates in: a first supervised mode during which a baseline radiation fingerprint is acquired by the radiation sensor as the rotating radiation shield is rotated about the radiation sensor; and a second unsupervised mode during which a subsequent radiation fingerprint is acquired by the radiation sensor as the rotating radiation shield is rotated about the radiation sensor, wherein the subsequent radiation fingerprint is compared to the baseline radiation fingerprint and, if a predetermined difference threshold is exceeded, an alert is issued.

  16. Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, M.

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

  17. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  18. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  19. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  20. Simulation and measurement of total ionizing dose radiation induced image lag increase in pinned photodiode CMOS image sensors

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Jing [School of Materials Science and Engineering, Xiangtan University, Hunan (China); State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O.Box 69-10, Xi’an (China); Chen, Wei, E-mail: chenwei@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O.Box 69-10, Xi’an (China); Wang, Zujun, E-mail: wangzujun@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O.Box 69-10, Xi’an (China); Xue, Yuanyuan; Yao, Zhibin; He, Baoping; Ma, Wuying; Jin, Junshan; Sheng, Jiangkun; Dong, Guantao [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O.Box 69-10, Xi’an (China)

    2017-06-01

    This paper presents an investigation of total ionizing dose (TID) induced image lag sources in pinned photodiodes (PPD) CMOS image sensors based on radiation experiments and TCAD simulation. The radiation experiments have been carried out at the Cobalt −60 gamma-ray source. The experimental results show the image lag degradation is more and more serious with increasing TID. Combining with the TCAD simulation results, we can confirm that the junction of PPD and transfer gate (TG) is an important region forming image lag during irradiation. These simulations demonstrate that TID can generate a potential pocket leading to incomplete transfer.

  1. Study of a design criterion for 316L irradiated represented by a strain hardened material

    International Nuclear Information System (INIS)

    Gouin, H.

    1999-01-01

    The aim of this study is to analyse the consequence of radiation on different structure submitted to imposed displacement loading and for damages due to plastic instability or rupture. The main consequence of radiation is a material hardening with a ductility decrease. This effect is similar to initial mechanical hardening: the mechanical properties (determined on smooth tensile specimen) evolve in the same way while irradiation or mechanical hardening increase. So in this study, radiation hardening is simulated by mechanical hardening (swaging). Tests were carried out for which two damages were considered: plastic instability and rupture. These two damages were studied with initial mechanical hardening (5 tested hammering rate 0, 15, 25, 35 and 45% on 316L stainless steel). Likewise two types of loading were studied: tensile or bending loading on specimens with or without geometrical singularities (notches). From tensile tests, two deformation criteria are proposed for prevention against the two quoted damages. Numerical study is carried out allowing to confirm hypothesis made at the time of the tensile test result interpretation and to validate the rupture criterion by applying on bending test. (author)

  2. Study of radiation hardening in reactor pressure vessel steels

    International Nuclear Information System (INIS)

    Nogiwa, Kimihiro; Nishimura, Akihiko

    2008-01-01

    In order to investigate the dependence of hardening on copper precipitate diameter and density, in-situ transmission electron microscopy (TEM) observations during tensile tests of dislocation gliding through copper rich-precipitates in thermally aged and neutron irradiated Fe-Cu alloys were performed. The obstacle strength has been estimated from the critical bow-out angle, φ, of dislocations. The obstacle distance on the dislocation line measured from in-situ TEM observations were compared with number density and diameter measured by 3D-AP (three dimensional atom probe) and TEM observation. A comparison is made between hardening estimation based on the critical bowing angles and those obtained from conventional tensile tests. (author)

  3. Radiation flux measuring device

    International Nuclear Information System (INIS)

    Corte, E.; Maitra, P.

    1977-01-01

    A radiation flux measuring device is described which employs a differential pair of transistors, the output of which is maintained constant, connected to a radiation detector. Means connected to the differential pair produce a signal representing the log of the a-c component of the radiation detector, thereby providing a signal representing the true root mean square logarithmic output. 3 claims, 2 figures

  4. Optimization of hardening/softening behavior of plane frame structures using nonlinear normal modes

    DEFF Research Database (Denmark)

    Dou, Suguang; Jensen, Jakob Søndergaard

    2016-01-01

    Devices that exploit essential nonlinear behavior such as hardening/softening and inter-modal coupling effects are increasingly used in engineering and fundamental studies. Based on nonlinear normal modes, we present a gradient-based structural optimization method for tailoring the hardening...... involving plane frame structures where the hardening/softening behavior is qualitatively and quantitatively tuned by simple changes in the geometry of the structures....

  5. Optimization of ultra-low-power CMOS transistors

    International Nuclear Information System (INIS)

    Stockinger, M.

    2000-01-01

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  6. Pixel front-end development in 65 nm CMOS technology

    International Nuclear Information System (INIS)

    Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

  7. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  8. Radiation hardening of oxygen-doped niobium by 14-MeV neutrons

    International Nuclear Information System (INIS)

    Bradley, E.R.; Jones, R.H.

    1983-09-01

    The flow properties of niobium containing 185 and 480 wt ppM oxygen have been studied following irradiation at 300K with T(d,n) neutrons to fluence levels ranging from 6 x 10 20 to 2 x 10 22 m -2 . Two hardening stages connected by a plateau region were observed in the niobium containing 185 wt ppM oxygen. Increasing the oxygen content by 300 wt ppM oxygen shifted the beginning of the high-fluence hardening stage from 6 x 10 21 to 1 x 10 21 m -2 , thereby eliminating the plateau region. This shift resulted in 1.5 times more hardening in the oxygen-doped niobium irradiated to fluence levels above 5 x 10 21 m -2

  9. Evaluation on the Effect of Composition on Radiation Hardening and Embrittlement in Model FeCrAl Alloys

    Energy Technology Data Exchange (ETDEWEB)

    Field, Kevin G. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Briggs, Samuel A. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Edmondson, Philip [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Hu, Xunxiang [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Littrell, Kenneth C. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Howard, Richard [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Parish, Chad M. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Yamamoto, Yukinori [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2015-09-18

    This report details the findings of post-radiation mechanical testing and microstructural characterization performed on a series of model and commercial FeCrAl alloys to assist with the development of a cladding technology with enhanced accident tolerance. The samples investigated include model alloys with simple ferritic grain structure and two commercial alloys with minor solute additions. These samples were irradiated in the High Flux Isotope Reactor (HFIR) at Oak Ridge National Laboratory (ORNL) up to nominal doses of 7.0 dpa near or at Light Water Reactor (LWR) relevant temperatures (300-400 C). Characterization included a suite of techniques including small angle neutron scattering (SANS), atom probe tomography (APT), and transmission based electron microscopy techniques. Mechanical testing included tensile tests at room temperature on sub-sized tensile specimens. The goal of this work was to conduct detailed characterization and mechanical testing to begin establishing empirical and/or theoretical structure-property relationships for radiation-induced hardening and embrittlement in the FeCrAl alloy class. Development of such relationships will provide insight on the performance of FeCrAl alloys in an irradiation environment and will enable further development of the alloy class for applications within a LWR environment. A particular focus was made on establishing trends, including composition and radiation dose. The report highlights in detail the pertinent findings based on this work. This report shows that radiation hardening in the alloys is primarily composition dependent due to the phase separation in the high-Cr FeCrAl alloys. Other radiation induced/enhanced microstructural features were less dependent on composition and when observed at low number densities, were not a significant contributor to the observed mechanical responses. Pre-existing microstructure in the alloys was found to be important, with grain boundaries and pre-existing dislocation

  10. Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

    Science.gov (United States)

    Guichard, Alex Richard

    Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores

  11. SOR/72-43 Radiation Emitting Devices Regulations

    International Nuclear Information System (INIS)

    1972-01-01

    These Regulations of 10 February 1972, supplemented by SOR/77-895, lay down the classes of radiation emitting devices for the purposes of the Radiation Emitting Devices Act. They lay down their standards of design and construction and warning sign specifications and provide for the procedure to be followed by inspectors of such devices. The devices include inter alia extra-oral dental x-ray equipment, baggage inspection x-ray devices, laser scanners, television receivers. (NEA)

  12. Fabrication of integrated metallic MEMS devices

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

    2002-01-01

    A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators are characteri......A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

  13. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  14. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  15. Characterization of a fully resonant, 1-MHz, 25-watt, DC/DC converter fabricated in a rad-hard BiCMOS/high-voltage process

    International Nuclear Information System (INIS)

    Titus, J.L.; Gehlhausen, M.A.; Desko, J.C. Jr.; Nguyen, T.T.; Roberts, D.J.; Shibib, M.A.; Hollenbach, K.E.

    1995-01-01

    This paper presents the characterization of a DC/DC converter prototype when its power integrated circuit (PIC) chip is exposed to total dose, dose rate, neutron, and heavy ion environments. This fully resonant, 1-MHZ, 25-Watt, DC/DC converter is composed of a brassboard, populated with input/output filters, isolation transformers, output rectifier, capacitors, resistors, and PIC chip, integrating the primary-side control circuitry, secondary-side control circuitry, power switch, gate-drive circuitry, and voltage references. The brassboard is built using commercial off-the-shelf components; and the PIC chip is fabricated using AT and T's rad-hard, bipolar complementary metal-oxide semiconductor (BiCMOS)/high-voltage process. The intent of this paper is to demonstrate that the PIC chip is fabricated with a radiation-hardened process and to demonstrate that various analog, digital, and power functions can be effectively integrated

  16. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  17. High-voltage CMOS detectors

    International Nuclear Information System (INIS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-01-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  18. High-voltage CMOS detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

    2016-07-11

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  19. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  20. CMOS and BiCMOS process integration and device characterization

    CERN Document Server

    El-Kareh, Badih

    2009-01-01

    Covers both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. This book also covers silicon devices and integrated process technologies. It discusses modern silicon devices, their characteristics, and interactions with process parameters.

  1. Silicon solid state devices and radiation detection

    CERN Document Server

    Leroy, Claude

    2012-01-01

    This book addresses the fundamental principles of interaction between radiation and matter, the principles of working and the operation of particle detectors based on silicon solid state devices. It covers a broad scope with respect to the fields of application of radiation detectors based on silicon solid state devices from low to high energy physics experiments including in outer space and in the medical environment. This book covers stateof- the-art detection techniques in the use of radiation detectors based on silicon solid state devices and their readout electronics, including the latest developments on pixelated silicon radiation detector and their application.

  2. CMOS image sensor-based immunodetection by refractive-index change.

    Science.gov (United States)

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

  3. DMILL circuits. The hardened electronics decuples its performances

    International Nuclear Information System (INIS)

    Anon.

    1998-01-01

    Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)

  4. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  5. Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

    Energy Technology Data Exchange (ETDEWEB)

    Learn, Mark Walter

    2012-01-01

    The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

  6. Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

    International Nuclear Information System (INIS)

    Moreau, Y.; Gasiot, J.; Duzellier, S.

    1995-01-01

    Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined

  7. Radiation ray measuring device

    International Nuclear Information System (INIS)

    Maekawa, Tatsuyuki; Ida, Masaki.

    1997-01-01

    The present invention provides a chained-radiation ray monitoring system which can be applied to an actual monitoring system of a nuclear power plant or the like. Namely, this device comprises a plurality of scintillation detectors. Each of the detectors has two light take-out ports for emitting light corresponding to radiation rays irradiated from the object of the measurement to optical fibers. In addition, incident light from the optical fiber by way of one of the light take-out optical ports is transmitted to the other of the ports and sent from the other optical port to the fibers. Plurality sets of measuring systems are provided in which each of the detectors are disposed corresponding to a plurality of objects to be measured. A signal processing device is (1) connected with optical fibers of plurality sets of measuring systems in conjunction, (2) detects the optical pulses inputted from the optical fibers to identify the detector from which the optical pulses are sent and (3) measures the amount of radiation rays detected by the identified detector. As a result, the device of the present invention can form a measuring system with redundancy. (I.S.)

  8. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.

    2016-05-18

    We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

  9. Radiation-Tolerance Assessment of a Redundant Wireless Device

    Science.gov (United States)

    Huang, Q.; Jiang, J.

    2018-01-01

    This paper presents a method to evaluate radiation-tolerance without physical tests for a commercial off-the-shelf (COTS)-based monitoring device for high level radiation fields, such as those found in post-accident conditions in a nuclear power plant (NPP). This paper specifically describes the analysis of radiation environment in a severe accident, radiation damages in electronics, and the redundant solution used to prolong the life of the system, as well as the evaluation method for radiation protection and the analysis method of system reliability. As a case study, a wireless monitoring device with redundant and diversified channels is evaluated by using the developed method. The study results and system assessment data show that, under the given radiation condition, performance of the redundant device is more reliable and more robust than those non-redundant devices. The developed redundant wireless monitoring device is therefore able to apply in those conditions (up to 10 M Rad (Si)) during a severe accident in a NPP.

  10. Radiation sterilization of medical devices

    International Nuclear Information System (INIS)

    Kaluska, I.; Stuglik, Z.

    1996-01-01

    Overview of sterilization methods of medical devices has been given, with the special stress put on radiation sterilization. A typical validation program for radiation sterilization has been shown and also a comparison of European and ISO standards concerning radiation sterilization has been discussed. (author). 13 refs, 1 fig., 2 tabs

  11. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

  12. Significance of rate of work hardening in tempered martensite embrittlement

    International Nuclear Information System (INIS)

    Pietikainen, J.

    1995-01-01

    The main explanations for tempered martensite embrittlement are based on the effects of impurities and cementite precipitation on the prior austenite grain boundaries. There are some studies where the rate of work hardening is proposed as a potential reason for the brittleness. One steel was studied by means of a specially developed precision torsional testing device. The test steel had a high Si and Ni content so ε carbide and Fe 3 C appear in quite different tempering temperature ranges. The M S temperature is low enough so that self tempering does not occur. With the testing device it was possible to obtain the true stress - true strain curves to very high deformations. The minimum toughness was always associated with the minimum of rate of work hardening. The change of deformed steel volume before the loss of mechanical stability is proposed as at least one reason for tempered martensite embrittlement. The reasons for the minimum of the rate of work hardening are considered. (orig.)

  13. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    Science.gov (United States)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  14. Nanoelectronic device applications handbook

    CERN Document Server

    Morris, James E

    2013-01-01

    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that range from nano-scaled complementary metal-oxide-semiconductor (CMOS) devices through recent developments in nano capacitors and AlGaAs/GaAs devices. The contributors are world-renowned experts from academia and industry from around the globe. The handbook explores current research into potentially disruptive technologies for a post-CMOS world.These include: Nanoscale advance

  15. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  16. Radiation monitoring device

    International Nuclear Information System (INIS)

    Sato, Toshifumi.

    1993-01-01

    The device of the present invention concerns a reactor start-up region monitor of a nuclear power plant. In an existent start-up region monitor, bias voltage is limited, if the reactor moves to a power region, in order to prevent degradation of radiation detectors. Accordingly, since the power is lower than an actual reactor power, the reactor power can not be monitored. The device of the present invention comprises a memory means for previously storing a Plateau's characteristic of the radiation detectors and a correction processing means for obtaining a correction coefficient in accordance with the Plateau's characteristic to correct and calculate the reactor power when the bias voltage is limited. With such a constitution, when the reactor power exceeds a predetermined value and the bias voltage is limited, the correction coefficient can be obtained by the memory means and the correction processing means. Corrected reactor power can also be obtained from the start-up region monitor by the correction coefficient. As a result, monitoring of the reactor power can be continued while preventing degradation of the radiation detector even if the bias voltage is limited. (I.S.)

  17. CMOS SPDT switch for WLAN applications

    International Nuclear Information System (INIS)

    Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

    2015-01-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

  18. Cmos spdt switch for wlan applications

    Science.gov (United States)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  19. Radiation effects in charge coupled devices

    International Nuclear Information System (INIS)

    Williams, R.A.; Nelson, R.D.

    1975-01-01

    Charge coupled devices (CCD s) exhibit a number of advantages (low cost, low power, high bit density) in their several applications (serial memories, imagers, digital filters); however, fairly elementary theoretical considerations indicate that they will be very vulnerable to permanent radiation damage, by both neutrons and ionizing radiation, and to transient upset by pulsed ionizing radiation. Although studies of permanent ionizing-radiation damage in CCD's have been reported, little information has been published concerning their overall nuclear radiation vulnerability. This paper presents a fairly comprehensive experimental study of radiation effects in a 256-cell surface-channel, CCD shift-register. A limited amount of similar work is also presented for a 128-cell surface-channel device and a 130 cell peristaltic CCD shift register. The radiation effects phenomena discussed herein, include transient-ionizing-radiation responses, permanent ionizing- radiation damage to transfer efficiency, charge-carrying capacity and input transfer gate bias, and neutron damage to storage time--determined from dark current and charge-up time measurements

  20. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  1. Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

    Science.gov (United States)

    Fossum, Eric R.

    The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

  2. Gamma and Proton-Induced Dark Current Degradation of 5T CMOS Pinned Photodiode 0.18 mu{m} CMOS Image Sensors

    Science.gov (United States)

    Martin, E.; Nuns, T.; David, J.-P.; Gilard, O.; Vaillant, J.; Fereyre, P.; Prevost, V.; Boutillier, M.

    2014-02-01

    The radiation tolerance of a 0.18 μm technology CMOS commercial image sensor has been evaluated with Co60 and proton irradiations. The effects of protons on the hot pixels and dynamic bias and duty cycle conditions during gamma irradiations are studied.

  3. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  4. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  5. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  6. Counterbalanced radiation detection device

    International Nuclear Information System (INIS)

    Platz, W.

    1986-01-01

    A counterbalanced radiation detection device is described which consists of: (a) a base; (b) a radiation detector having a known weight; (c) means connected with the radiation detector and the base for positioning the radiation detector in different heights with respect to the base; (d) electronic component means movably mounted on the base for counterbalancing the weight of the radiation detector; (e) means connected with the electronic component means and the radiation detector positioning means for positioning the electronic component means in different heights with respect to the base opposite to the heights of the radiation detector; (f) means connected with the radiation detector and the base for shifting the radiation detector horizontally with respect to the base; and (g) means connected with the electronic component means and the radiation detector shifting means for shifting the electronic component means horizontally with respect to the base in opposite direction to shifting of the radiation detector

  7. Geant4-based simulations of charge collection in CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Esposito, M.; Allinson, N.M.; Price, T.; Anaxagoras, T.

    2017-01-01

    Geant4 is an object-oriented toolkit for the simulation of the interaction of particles and radiation with matter. It provides a snapshot of the state of a simulated particle in time, as it travels through a specified geometry. One important area of application is the modelling of radiation detector systems. Here, we extend the abilities of such modelling to include charge transport and sharing in pixelated CMOS Active Pixel Sensors (APSs); though similar effects occur in other pixel detectors. The CMOS APSs discussed were developed in the framework of the PRaVDA consortium to assist the design of custom sensors to be used in an energy-range detector for proton Computed Tomography (pCT). The development of ad-hoc classes, providing a charge transport model for a CMOS APS and its integration into the standard Geant4 toolkit, is described. The proposed charge transport model includes, charge generation, diffusion, collection, and sharing across adjacent pixels, as well as the full electronic chain for a CMOS APS. The proposed model is validated against experimental data acquired with protons in an energy range relevant for pCT.

  8. First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

    Science.gov (United States)

    Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

    2017-06-01

    The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

  9. First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

    International Nuclear Information System (INIS)

    Pernegger, H.; Hoorne, J.W. van; Kugathasan, T.; Musa, L.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E.J.; Snoeys, W.; Bates, R.; Buttar, C.; Maneuski, D.; Dalla, M.; Sbarra, C.

    2017-01-01

    The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 10"1"5 n _e_q/cm"2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

  10. The effects of emitter-tied field plates on lateral PNP ionizing radiation response

    International Nuclear Information System (INIS)

    Barnaby, H.J.; Schrimpf, R.D.; Cirba, C.R.; Pease, R.L.; Fleetwood, D.M.; Kosier, S.L.

    1998-03-01

    Radiation response comparisons of lateral PNP bipolar technologies reveal that device hardening may be achieved by extending the emitter contact over the active base. The emitter-tied field plate suppresses recombination of carriers with interface traps

  11. Radiation tolerance study of a commercial 65 nm CMOS technology for high energy physics applications

    Energy Technology Data Exchange (ETDEWEB)

    Ding, Lili, E-mail: lili03.ding@gmail.com [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); State Key Laboratory of Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, Xi' an (China); Gerardin, Simone [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Bagatin, Marta [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); Bisello, Dario [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Mattiazzo, Serena [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); Paccagnella, Alessandro [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy)

    2016-09-21

    This paper reports the radiation tolerance study of a commercial 65 nm technology, which is a strong candidate for the Large Hadron Collider applications. After exposure to 3 MeV protons till 1 Grad dose, the 65 nm CMOS transistors, especially the pMOSFETs, showed severe long-term degradation mainly in the saturation drain currents. There were some differences between the degradation levels in the nMOSFETs and the pMOSFETs, which were likely attributed to the positive charges trapped in the gate spacers. After exposure to heavy ions till multiple strikes, the pMOSFETs did not show any sudden loss of drain currents, the degradations in the characteristics were negligible.

  12. Thermosonic wire bonding of IC devices using palladium wire

    International Nuclear Information System (INIS)

    Shze, J.H.; Poh, M.T.; Tan, R.M.

    1996-01-01

    The feasibility of replacing gold wire by palladium wire in thermosonic wire bonding of CMOS and bipolar devices are studied in terms of the manufacturability, physical, electrical and assembly performance. The results that palladium wire is a viable option for bonding the bipolar devices but not the CMOS devices

  13. Prospects of radiation sterilization of medical devices

    International Nuclear Information System (INIS)

    Hosobuchi, Kazunari

    1992-01-01

    Since radiation sterilization was first introduced in the United States in 1956 in the field of disposable medical devices, it has become an indispensable technique for sterilization because of the following reasons: (1) introduction into dialyzers, (2) introduction in medical device makers, (3) development of disposable medical devices associated with developing both high molecular chemistry and cool sterilization, (4) rationality of sterilization process, and (5) problems of sterilization with ethylene oxide gas. To promote the further development of radiation sterilization, the following items are considered necessary: (1) an increase in the number of facilities for radiation sterilization, (2) recommendation of the international standardization of sterilization method, (3) decrease in radiation doses associated with sterilization, (4) development of electron accelerators and bremsstrahlung equipments for radiation sources, and (5) simplification of sterilization process management. Factors precluding the development of radiation sterilization are: (1) development of other methods than radiation sterilization, (2) development of technique for sterile products, (3) high facility cost, (4) high irradiation cost, (5) benefits and limits of sterilization markets, and (6) influences of materials. (N.K.)

  14. Contribution to the study of ionizing radiation effects on bipolar technologies: application to the hardening of integrated circuits

    International Nuclear Information System (INIS)

    Briand, R.

    2001-01-01

    The use of analog integrated circuits in radiation environments raises the problem of their behaviour with respect to the different effects induced by particles and radiations. The first chapter of this thesis presents the origins of radiations and the different topologies of bipolar transistors. The effects of ionizing radiations on bipolar components, like cumulative dose, dose rates, and single events, are detailed in three distinct chapters with the same scientifical approach. The simulation of the physical degradation phenomena of the components allows to establish original electrical models coming from the understanding of the induced mechanisms. These models are used to evaluate the degradations occurring in linear analogic circuits. Common and original hardening methods are presented, some of which are applied to bipolar integrated circuit technologies. Finally, experimental laser beam test techniques are presented, which are used to reproduce the dose rate and the single events. (J.S.)

  15. Advances in CMOS solid-state photomultipliers for scintillation detector applications

    Energy Technology Data Exchange (ETDEWEB)

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric [Radiation Monitoring Devices, 44 Hunt Street, Watertownm, MA 02472 (United States); Augustine, Frank L., E-mail: JChristian@RMDInc.co [Augustine Engineering, 2115 Park Dale Ln, Encinitas, CA 92024 (United States)

    2010-12-11

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

  16. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  17. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  18. CMOS latch-up analysis and prevention

    International Nuclear Information System (INIS)

    Shafer, B.D.

    1975-06-01

    An analytical model is presented which develops relationships between ionization rates, minority carrier lifetimes, and latch-up in bulk CMOS integrated circuits. The basic mechanism for latch-up is the SCR action reported by Gregory and Shafer. The SCR is composed of a vertical NPN transistor formed by the N-channel source diffusion, the P-Well, and the N-substrate. The second part of the SCR is the lateral PNP transistor made up of the P-channel source diffusion, the N-substrate, and P-Well. It is shown that the NPN transistor turns on due to photocurrent-induced lateral voltage drops in the base of the transistor. The gain of this double diffused transistor has been shown to be as high as 100. Therefore, the transistor action of this device produces a much larger current flow in the substrate. This transistor current adds to that produced by the P-Well diode photocurrent in the substrate. It is found that the combined flow of current in the substrate forward biases the base emitter junction of the PNP device long before this could occur due to the P-Well photocurrent alone. The analysis indicated that a CD4007A CMOS device biased in the normal mode of operation should latch at about 2 . 10 8 rads/sec. Experimental results produced latch-up at 1 to 3 . 10 8 rads/sec. (U.S.)

  19. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  20. Radiation detection device and a radiation detection method

    International Nuclear Information System (INIS)

    Blum, A.

    1975-01-01

    A radiation detection device is described including at least one scintillator in the path of radiation emissions from a distributed radiation source; a plurality of photodetectors for viewing each scintillator; a signal processing means, a storage means, and a data processing means that are interconnected with one another and connected to said photodetectors; and display means connected to the data processing means to locate a plurality of radiation sources in said distributed radiation source and to provide an image of the distributed radiation sources. The storage means includes radiation emission response data and location data from a plurality of known locations for use by the data processing means to derive a more accurate image by comparison of radiation responses from known locations with radiation responses from unknown locations. (auth)

  1. Prospects for charge sensitive amplifiers in scaled CMOS

    Science.gov (United States)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-03-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

  2. Prospects for charge sensitive amplifiers in scaled CMOS

    International Nuclear Information System (INIS)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-01-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

  3. The effects of cosmic radiation on implantable medical devices

    International Nuclear Information System (INIS)

    Bradley, P.

    1996-01-01

    Metal oxide semiconductor (MOS) integrated circuits, with the benefits of low power consumption, represent the state of the art technology for implantable medical devices. Three significant sources of radiation are classified as having the ability to damage or alter the behavior of implantable electronics; Secondary neutron cosmic radiation, alpha particle radiation from the device packaging and therapeutic doses(up to 70 Gγ) of high energy radiation used in radiation oncology. The effects of alpha particle radiation from the packaging may be eliminated by the use of polyimide or silicone rubber die coatings. The relatively low incidence of therapeutic radiation incident on an implantable device and the use of die coating leaves cosmic radiation induced secondary neutron single event upset (SEU) as the main pervasive ionising radiation threat to the reliability of implantable devices. A theoretical model which predicts the susceptibility of a RAM cell to secondary neutron cosmic radiation induced SEU is presented. The model correlates well within the statistical uncertainty associated with both the theoretical and field estimate. The predicted Soft Error Rate (SER) is 4.8 x l0 -12 upsets/(bit hr) compared to an observed upset rate of 8.5 x 10 -12 upsets/(bit hr) from 20 upsets collected over a total of 284672 device days. The predicted upset rate may increase by up to 20% when consideration is given to patients flying in aircraft The upset rate is also consistent with the expected geographical variations of the secondary cosmic ray neutron flux, although insufficient upsets precluded a statistically significant test. This is the first clinical data set obtained indicating the effects of cosmic radiation on implantable devices. Importantly, it may be used to predict the susceptibility of future to the implantable device designs to the effects of cosmic radiation

  4. A brief review of cavity swelling and hardening in irradiated copper and copper alloys

    International Nuclear Information System (INIS)

    Zinkle, S.J.

    1990-01-01

    The literature on radiation-induced swelling and hardening in copper and its alloy is reviewed. Void formation does not occur during irradiation of copper unless suitable impurity atoms such as oxygen or helium are present. Void formation occurs for neutron irradiation temperatures of 180 to 550 degree C, with peak swelling occurring at ∼320 degree C for irradiation at a damage rate of 2 x 10 -7 dpa/s. The post-transient swelling rate has been measured to be ∼0.5%/dpa at temperatures near 400 degree C. Dispersion-strengthened copper has been found to be very resistant to void swelling due to the high sink density associated with the dispersion-stabilized dislocation structure. Irradiation of copper at temperatures below 400 degree C generally causes an increase in strength due to the formation of defect clusters which inhibit dislocation motion. The radiation hardening can be adequately described by Seeger's dispersed barrier model, with a barrier strength for small defect clusters of α ∼ 0.2. The radiation hardening apparently saturates for fluences greater than ∼10 24 n/m 2 during irradiation at room temperature due to a saturation of the defect cluster density. Grain boundaries can modify the hardening behavior by blocking the transmission of dislocation slip bands, leading to a radiation- modified Hall-Petch relation between yield strength and grain size. Radiation-enhanced recrystallization can lead to softening of cold-worked copper alloys at temperatures above 300 degree C

  5. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  6. Medical Devices; General Hospital and Personal Use Devices; Classification of the Ultraviolet Radiation Chamber Disinfection Device. Final order.

    Science.gov (United States)

    2015-11-20

    The Food and Drug Administration (FDA or the Agency) is classifying the ultraviolet (UV) radiation chamber disinfection device into class II (special controls). The special controls that will apply to the device are identified in this order and will be part of the codified language for the UV radiation chamber disinfection device classification. The Agency is classifying the device into class II (special controls) in order to provide a reasonable assurance of safety and effectiveness of the device.

  7. Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.

    Science.gov (United States)

    Yongsu Lee; Hyeonwoo Lee; Seunghyup Yoo; Hoi-Jun Yoo

    2016-08-01

    The sticker-type sensor system is proposed targeting ECG/PPG concurrent monitoring for cardiovascular diseases. The stickers are composed of two types: Hub and Sensor-node (SN) sticker. Low-power CMOS SoC for measuring ECG and PPG signal is hybrid integrated with organic light emitting diodes (OLEDs) and organic photo detector (OPD). The sticker has only 2g weight and only consumes 141μW. The optical calibration loop is adopted for maintaining SNR of PPG signal higher than 30dB. The pulse arrival time (PAT) and SpO2 value can be extracted from various body parts and verified comparing with the reference device from 20 people in-vivo experiments.

  8. Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

    2017-07-15

    A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  9. New technologies for radiation-hardening analog to digital converters

    International Nuclear Information System (INIS)

    Gauthier, M.K.

    1982-12-01

    Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

  10. New technologies for radiation-hardening analog to digital converters

    Science.gov (United States)

    Gauthier, M. K.

    1982-01-01

    Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

  11. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  12. Radiometric assessment of quality of concrete mix with respect to hardened concrete strength

    International Nuclear Information System (INIS)

    Czechowski, J.

    1983-01-01

    The experiments have confirmed the relationship between the intensity of backscattered gamma radiation and the density of fresh concrete, and also between the flow of backscattered fast neutrons and the water content. From the said two parameters it is possible to derive the compression strength of concrete over the determined period of mix hardening, e.g., after 28 days. For a certain composition of concrete it is possible to derive empirical relations between the intensity of backscattered gamma radiation and neutrons and concrete strength after hardening and to construct suitable nomograms. (Ha)

  13. Electron bombardment cross-linking of coating materials. Pt.2. Analysis of patent literature on formulating radiation-hardenable binders

    International Nuclear Information System (INIS)

    Mileo, J.-C.

    1976-01-01

    The process of drying paints and varnishes by electron irradiation is analyzed from the chemical standpoint. A review is made of the different methods of producing radiation hardenable resins that have resulted in abundant patent literature. These resins are classified according to the nature of the reactive unsaturations they contain: unsaturations of the maleic ester type; simple (meth)acrylic esters and amides; β-hydroxyl (meth)acrylic esters, their (un)saturated esters and other derivatives; siloxanes; maleimides; allylic unsaturations; saturated resins [fr

  14. Changed of the working capacity of CMOS integrated circuits under ionizing radiations effect of low and high dose rate; Izmeneniya rabotosposobnosti KMOP integral`nykh mikroskhem pri vozdejstvii ioniziruyushchikh izluchenij s nizkoj i vysokoj intensivnost`yu

    Energy Technology Data Exchange (ETDEWEB)

    Bogatyrev, Yu V; Korshunov, F P

    1994-12-31

    Results of experimental investigations into the working capacity of different types of integrated CMOS circuits under effect of electron and gamma radiation are presented. Methods for evaluating IC CMOS under low irradiation intensity using the microcircuit testing under hugh intensity or at increased temperature with regard to the processes of parameter reconstruction after irradiation are proposed.

  15. Evaluating a radiation monitor for mixed-field environments based on SRAM technology

    CERN Document Server

    Tsiligiannis, G; Bosio, A; Girard, P; Pravossoudovitch, S; Todri, A; Virazel, A; Mekki, J; Brugger, M; Wrobel, F; Saigne, F

    2014-01-01

    Instruments operating in particle accelerators and colliders are exposed to radiations that are composed of particles of different types and energies. Several of these instruments often embed devices that are not hardened against radiation effects. Thus, there is a strong need for mon- itoring the levels of radiation inside the mixed-field radiation areas, throughout different positions. Different metrics exist for measuring the radiation damage induced to electronic devices, such as the Total Ionizing Dose (TID), the Displacement Damage (DD) and of course the fluence of parti- cles for estimating the error rates of the electronic devices among other applications. In this paper, we propose an SRAM based monitor, that is used to define the fluence of High Energy Hadrons (HEH) by detecting Single Event Upsets in the memory array. We evaluated the device by testing it inside the H4IRRAD area of CERN, a test area that reproduces the radiation conditions inside the Large Hadron Collider (LHC) tunnel and its shield...

  16. Advanced Small Animal Conformal Radiation Therapy Device.

    Science.gov (United States)

    Sharma, Sunil; Narayanasamy, Ganesh; Przybyla, Beata; Webber, Jessica; Boerma, Marjan; Clarkson, Richard; Moros, Eduardo G; Corry, Peter M; Griffin, Robert J

    2017-02-01

    We have developed a small animal conformal radiation therapy device that provides a degree of geometrical/anatomical targeting comparable to what is achievable in a commercial animal irradiator. small animal conformal radiation therapy device is capable of producing precise and accurate conformal delivery of radiation to target as well as for imaging small animals. The small animal conformal radiation therapy device uses an X-ray tube, a robotic animal position system, and a digital imager. The system is in a steel enclosure with adequate lead shielding following National Council on Radiation Protection and Measurements 49 guidelines and verified with Geiger-Mueller survey meter. The X-ray source is calibrated following AAPM TG-61 specifications and mounted at 101.6 cm from the floor, which is a primary barrier. The X-ray tube is mounted on a custom-made "gantry" and has a special collimating assembly system that allows field size between 0.5 mm and 20 cm at isocenter. Three-dimensional imaging can be performed to aid target localization using the same X-ray source at custom settings and an in-house reconstruction software. The small animal conformal radiation therapy device thus provides an excellent integrated system to promote translational research in radiation oncology in an academic laboratory. The purpose of this article is to review shielding and dosimetric measurement and highlight a few successful studies that have been performed to date with our system. In addition, an example of new data from an in vivo rat model of breast cancer is presented in which spatially fractionated radiation alone and in combination with thermal ablation was applied and the therapeutic benefit examined.

  17. The secondary hardening phenomenon in strain-hardened MP35N alloy

    International Nuclear Information System (INIS)

    Asgari, S.; El-Danaf, E.; Shaji, E.; Kalidindi, S.R.; Doherty, R.D.

    1998-01-01

    Mechanical testing and microscopy techniques were used to investigate the influence of aging on the structure and strengthening of MP35N alloy. It was confirmed that aging the deformed material at 600 C for 4 h provided additional strengthening, here referred to as secondary hardening, in addition to the primary strain hardening. The secondary hardening phenomenon was shown to be distinctly different from typical age hardening processes in that it only occurred in material deformed beyond a certain cold work level. At moderate strains, aging caused a shift in the entire stress-strain curve of the annealed material to higher stresses while at high strains, it produced shear localization and limited work softening. The secondary hardening increment was also found to be grain size dependent. The magnitude of the secondary hardening appeared to be controlled by the flow stress in the strain hardened material. A model is proposed to explain the observations and is supported by direct experimental evidence. The model is based on formation of h.c.p. nuclei through the Suzuki mechanism, that is segregation of solute atoms to stacking faults, on aging the strain hardened material. The h.c.p. precipitates appear to thicken only in the presence of high dislocation density produced by prior cold work

  18. Effects of initial microstructure and helium production on radiation hardening in F82H Steels

    Energy Technology Data Exchange (ETDEWEB)

    Okubo, N.; Wakai, E.; Takada, F.; Jitsukawa, S. [Japan Atomic Energy Agency, Naga-gun, Ibaraki-ken (Japan); Katoh, Y. [Oak Ridge Noational Laboratory, TN (United States)

    2007-07-01

    Full text of publication follows: Fission neutron irradiation to steels doped with isotope boron-10 is frequently conducted to study effects of the helium production on mechanical properties. The intrinsic mechanical properties of F82H steels could have been changed due to the boron doping. Recently, we reported that co-doping with boron and nitrogen to F82H (F82H+B+N) improved the mechanical properties of F82H doped only with boron. The mechanical properties of F82H+B+N are successfully comparable with the non-doped F82H before irradiation. In order to evaluate the effects of initial microstructure and helium production on radiation hardening, F82H and F82H+B+N were irradiate d Specimens used in this study were standard F82H martensitic steels, F82H steels doped with 60 mass ppm {sup 10}B and 200 ppm N (F82H+10B+N) and F82H steels doped with 60 mass ppm {sup 11}B and 200 ppm N (F82H+11B+N). Initial microstructures were changed by tempering conditions, and the tempering temperatures were at 700, 750 and 780 deg. C. Irradiation was performed at nominally 250 deg. C to 2 dpa in JMTR. Tensile properties were measured for the specimens before and after irradiation. Change of yield stress due to the irradiation in the F82H+11B+N steels depended strongly on the initial microstructure and hardness before irradiation. The radiation hardening due to helium production in the F82H+10B+N steels was less than 60 MPa in these experiments. Size of dimple in the fracture surface of specimen with helium production was larger than that with non-helium production. (authors)

  19. Installation of a TCT set-up for characterization of novel HV-CMOS planar silicon sensors

    CERN Document Server

    Marx, Lisa

    2013-01-01

    For future upgrades of the LHC it is necessary to develop new tracking detectors: more radiation hard and cost efficient pixel detectors with high spacial resolution are required for the planned high luminosity version of the LHC (HL-LHC). For future tracking devices HV-CMOS active pixel sensors are great candidates since they fulfill all the demands mentioned above. First prototypes of these sensors are assembled on custom test boards and together with FE-I4 readout chips they make up the first test pixel detectors. One approach for testing these chips is through using lasers to induce electron-hole-pairs into the depletion zone of the sensor chip diodes to simulate an ionizing particle crossing through the bulk. Comparison measurements of irradiated/non-irradiated sensors are used to explore the radiation hardness of the sensors.

  20. Simultaneous surface engineering and bulk hardening of precipitation hardening stainless steel

    DEFF Research Database (Denmark)

    Frandsen, Rasmus Berg; Christiansen, Thomas; Somers, Marcel A. J.

    2006-01-01

    This article addresses simultaneous bulk precipitation hardening and low temperature surface engineering of two commercial precipitation hardening stainless steels: Sandvik Nanoflex® and Uddeholm Corrax®. Surface engineering comprised gaseous nitriding or gaseous carburising. Microstructural....... The duration and temperature of the nitriding/carburising surface hardening treatment can be chosen in agreement with the thermal treatment for obtaining optimal bulk hardness in the precipitation hardening stainless steel....... characterisation of the cases developed included X-ray diffraction analysis, reflected light microscopy and micro-hardness testing. It was found that the incorporation of nitrogen or carbon resulted in a hardened case consisting of a combination of (tetragonal) martensite and expanded (cubic) austenite...

  1. CMOS-MEMS prestress vertical cantilever resonator with electrostatic driving and piezoresistive sensing

    Energy Technology Data Exchange (ETDEWEB)

    Chiou, J-C; Shieh, L-J; Lin, Y-J [Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan (China)], E-mail: chiou@mail.nctu.edu.tw, E-mail: ljs.ece93g@nctu.edu.tw, E-mail: yjlin@mail.nctu.edu.tw

    2008-10-21

    This paper presents a CMOS-MEMS prestress vertical comb-drive resonator with a piezoresistive sensor to detect its static and dynamic response. The proposed resonator consists of a set of comb fingers fabricated along with a composite beam. One end of the composite beam is clamped to the anchor, while the other is elevated by residual stress. Actuation occurs when the electrostatic force, induced by the fringe effect, pulls the composite beam downwards to the substrate. The initial tip height at the free end of the resonator due to residual stress is approximately 60 {mu}m. A piezoresistor is designed to sense the vertical deflection and vibration of the resonator. The relative change in the resistance of the piezoresistor ({delta}R/R) is about 0.52% when a voltage of 100 V is applied in static mode. The first resonant frequency of the device is 14.5 kHz, and the quality factor is around 36 in air. The device is fabricated through TSMC 0.35 {mu}m 2p4m CMOS process and post-CMOS process.

  2. CMOS-MEMS prestress vertical cantilever resonator with electrostatic driving and piezoresistive sensing

    International Nuclear Information System (INIS)

    Chiou, J-C; Shieh, L-J; Lin, Y-J

    2008-01-01

    This paper presents a CMOS-MEMS prestress vertical comb-drive resonator with a piezoresistive sensor to detect its static and dynamic response. The proposed resonator consists of a set of comb fingers fabricated along with a composite beam. One end of the composite beam is clamped to the anchor, while the other is elevated by residual stress. Actuation occurs when the electrostatic force, induced by the fringe effect, pulls the composite beam downwards to the substrate. The initial tip height at the free end of the resonator due to residual stress is approximately 60 μm. A piezoresistor is designed to sense the vertical deflection and vibration of the resonator. The relative change in the resistance of the piezoresistor (ΔR/R) is about 0.52% when a voltage of 100 V is applied in static mode. The first resonant frequency of the device is 14.5 kHz, and the quality factor is around 36 in air. The device is fabricated through TSMC 0.35 μm 2p4m CMOS process and post-CMOS process.

  3. Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

    Science.gov (United States)

    Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

    2014-12-01

    We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

  4. Hardening and microstructural evolution of A533b steels irradiated with Fe ions and electrons

    Energy Technology Data Exchange (ETDEWEB)

    Watanabe, H., E-mail: watanabe@riam.kyushu-u.ac.jp [Research Institute for Applied Mechanics, Kyushu University, 6-1, Kasuga-kouenn, Kasugashi, Fukuoka, 816-8580 (Japan); Arase, S. [Interdisciplinary Graduate School of Kyushu University, 6-1, Kasuga-kouenn, Kasugashi, Fukuoka, 816-8580 (Japan); Yamamoto, T.; Wells, P. [Dept. Chemical Engineering, UCSB Engineering II, RM3357, Santa Barbara, CA, 93106-5080 (United States); Onishi, T. [Interdisciplinary Graduate School of Kyushu University, 6-1, Kasuga-kouenn, Kasugashi, Fukuoka, 816-8580 (Japan); Odette, G.R. [Dept. Chemical Engineering, UCSB Engineering II, RM3357, Santa Barbara, CA, 93106-5080 (United States)

    2016-04-01

    Radiation hardening and embrittlement of A533B steels is heavily dependent on the Cu content. In this study, to investigate the effect of copper on the microstructural evolution of these materials, A533B steels with different Cu levels were irradiated with 2.4 MeV Fe ions and 1.0 MeV electrons. Ion irradiation was performed from room temperature (RT) to 350 °C with doses up to 1 dpa. At RT and 290 °C, low dose (<0.1 dpa) hardening trend corresponded with ΔH ∝ (dpa){sup n}, with n initially approximately 0.5 and consistent with a barrier hardening mechanism, but saturating at ≈0.1 dpa. At higher dose levels, the radiation-induced hardening exhibited a strong Cu content dependence at 290 °C, but not at 350 °C. Electron irradiation using high-voltage electron microscopy revealed the growth of interstitial-type dislocation loops and enrichment of Ni, Mn, and Si in the vicinities of pre-existing dislocations at doses for which the radiation-induced hardness due to ion irradiation was prominent.

  5. A vertex detector for the International Linear Collider based on CMOS sensors

    Energy Technology Data Exchange (ETDEWEB)

    Besson, Auguste [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: abesson@in2p3.fr; Claus, Gilles [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Colledani, Claude [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Degerli, Yavuz [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Deptuch, Grzegorz [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Deveaux, Michael [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France) and GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Dulinski, Wojciech [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Fourches, Nicolas [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Goffe, Mathieu [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Grandjean, Damien [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Guilloux, Fabrice [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Heini, Sebastien [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]|[GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Himmi, Abdelkader; Hu, Christine; Jaaskelainen, Kimmo [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Li, Yan; Lutz, Pierre; Orsini, Fabienne [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Pellicioli, Michel; Scopelliti, Emanuele; Shabetai, Alexandre; Szelezniak, Michal; Valin, Isabelle [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Winter, Marc [Institut de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: marc.winter@ires.in2p3.f

    2006-11-30

    The physics programme at the International Linear Collider (ILC) calls for a vertex detector (VD) providing unprecedented flavour tagging performances, especially for c-quarks and {tau} leptons. This requirement makes a very granular, thin and multi-layer VD installed very close to the interaction region mandatory. Additional constraints, mainly on read-out speed and radiation tolerance, originate from the beam background, which governs the occupancy and the radiation level the detector should be able to cope with. CMOS sensors are being developed to fulfil these requirements. This report addresses the ILC requirements (highly related to beamstrahlung), the main advantages and features of CMOS sensors, the demonstrated performances and the specific aspects of a VD based on this technology. The status of the main R and D directions (radiation tolerance, thinning procedure and read-out speed) are also presented.

  6. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    Science.gov (United States)

    Benoit, M.; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Perić, I.; Rimoldi, M.; Ristić, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2018-02-01

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the 4th generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between 1× 1014 and 5× 1015 1-MeV- neq. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of 85 V. The sample irradiated to a fluence of 1× 1015 neq—a relevant value for a large volume of the upgraded tracker—exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.

  7. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...... for integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  8. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

    International Nuclear Information System (INIS)

    Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

    2014-01-01

    In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

  9. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

    CERN Document Server

    Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

    2000-01-01

    A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

  10. CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

    Directory of Open Access Journals (Sweden)

    Ekavut Kritchanchai

    2015-08-01

    Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

  11. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  12. A hardenability test proposal

    Energy Technology Data Exchange (ETDEWEB)

    Murthy, N.V.S.N. [Ingersoll-Rand (I) Ltd., Bangalore (India)

    1996-12-31

    A new approach for hardenability evaluation and its application to heat treatable steels will be discussed. This will include an overview and deficiencies of the current methods and discussion on the necessity for a new approach. Hardenability terminology will be expanded to avoid ambiguity and over-simplification as encountered with the current system. A new hardenability definition is proposed. Hardenability specification methods are simplified and rationalized. The new hardenability evaluation system proposed here utilizes a test specimen with varying diameter as an alternative to the cylindrical Jominy hardenability test specimen and is readily applicable to the evaluation of a wide variety of steels with different cross-section sizes.

  13. Detection device of dangerous radiation for the living beings

    International Nuclear Information System (INIS)

    Lacoste, F.

    1991-01-01

    This invention is about a portable device able to measure dose rates or doses of gamma, ultraviolet and X radiation or charged particles. This device is composed of a radiation detector, a calculator of the accumulate dose and a memory to store the data. This device has a credit card format

  14. Radiation sensitive devices and systems for detection of radioactive materials and related methods

    Science.gov (United States)

    Kotter, Dale K

    2014-12-02

    Radiation sensitive devices include a substrate comprising a radiation sensitive material and a plurality of resonance elements coupled to the substrate. Each resonance element is configured to resonate responsive to non-ionizing incident radiation. Systems for detecting radiation from a special nuclear material include a radiation sensitive device and a sensor located remotely from the radiation sensitive device and configured to measure an output signal from the radiation sensitive device. In such systems, the radiation sensitive device includes a radiation sensitive material and a plurality of resonance elements positioned on the radiation sensitive material. Methods for detecting a presence of a special nuclear material include positioning a radiation sensitive device in a location where special nuclear materials are to be detected and remotely interrogating the radiation sensitive device with a sensor.

  15. Total integrated dose testing of solid-state scientific CD4011, CD4013, and CD4060 devices by irradiation with CO-60 gamma rays

    Science.gov (United States)

    Dantas, A. R. V.; Gauthier, M. K.; Coss, J. R.

    1985-01-01

    The total integrated dose response of three CMOS devices manufactured by Solid State Scientific has been measured using CO-60 gamma rays. Key parameter measurements were made and compared for each device type. The data show that the CD4011, CD4013, and CD4060 produced by this manufacturers should not be used in any environments where radiation levels might exceed 1,000 rad(Si).

  16. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  17. Comparison of Thermal Creep Strain Calculation Results Using Time Hardening and Strain Hardening Rules

    International Nuclear Information System (INIS)

    Kim, Junehyung; Cheon, Jinsik; Lee, Byoungoon; Lee, Chanbock

    2014-01-01

    One of the design criteria for the fuel rod in PGSFR is the thermal creep strain of the cladding, because the cladding is exposed to a high temperature for a long time during reactor operation period. In general, there are two kind of calculation scheme for thermal creep strain: time hardening and strain hardening rules. In this work, thermal creep strain calculation results for HT9 cladding by using time hardening and strain hardening rules are compared by employing KAERI's current metallic fuel performance analysis code, MACSIS. Also, thermal creep strain calculation results by using ANL's metallic fuel performance analysis code, LIFE-METAL which adopts strain hardening rule are compared with those by using MACSIS. Thermal creep strain calculation results for HT9 cladding by using time hardening and strain hardening rules were compared by employing KAERI's current metallic fuel performance analysis code, MACSIS. Also, thermal creep strain calculation results by using ANL's metallic fuel performance analysis code, LIFE-METAL which adopts strain hardening rule were compared with those by using MACSIS. Tertiary creep started earlier in time hardening rule than in strain hardening rule. Also, calculation results by MACSIS with strain hardening and those obtained by using LIFE-METAL were almost identical to each other

  18. Effect of hardening on the crack growth rate of austenitic stainless steels in primary PWR conditions

    International Nuclear Information System (INIS)

    Castano, M.L.; Garcia, M.S.; Diego, G. de; Gomez-Briceno, D.; Francia, L.

    2002-01-01

    Intergranular cracking of non-sensitized materials, found in light water reactor (LWR) components exposed to neutron radiation, has been attributed to Irradiation Assisted Stress Corrosion Cracking (IASCC). Cracking of baffle former bolts, fabricated of AISI-316L and AISI-347, have been reported in some Europeans and US PWR plants. Examinations of removed bolts indicate the intergranular cracking characteristics can be associated with IASCC phenomena. Neutron radiation produce critical modifications of the microstructure and microchemical of stainless steels such hardening due to irradiation and Radiation Induce Segregation (RIS) at grain boundaries, among others. Chromium depletion at grain boundary due to RIS seems to justify the intergranular cracking of irradiated materials, both in plant and in lab tests, at high electrochemical corrosion potential (BWR-NWC environments), but it is not enough to explain cracking at low corrosion potential (BWR-HWC and PWR environments). In these latter conditions, hardening is considered a possible additional mechanism to explain the behavior of irradiated material. Radiation Hardening can be simulated in non irradiated material by mechanical deformation. Although some differences exists in the types of defects produced by radiation and mechanical deformation, it is accepted that the study of the stress corrosion behavior of unirradiated austenitic steels with different hardening levels would contribute to the understanding of IASCC mechanism. In order to evaluate the influence of hardening on the stress corrosion susceptibility of austenitic steels, crack growth rate tests with 316L and 347 stainless steels with nominal yield strengths from 500 to 900 MPa, produced by cold work are being carried out at 340 deg C in PWR conditions. Preliminary results indicate that crack propagation was obtained in the 316Lss and 347ss cold worked, even with a yield strength of 550 MPa. (authors)

  19. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  20. Design and fabrication of a CMOS-compatible MHP gas sensor

    Directory of Open Access Journals (Sweden)

    Ying Li

    2014-03-01

    Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  1. Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

    International Nuclear Information System (INIS)

    Casas, L.M. Jara; Ceresa, D.; Kulis, S.; Christiansen, J.; Francisco, R.; Miryala, S.; Gnani, D.

    2017-01-01

    A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, V t flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

  2. Effect of yield strength on stress corrosion crack propagation under PWR and BWR environments of hardened stainless steels

    Energy Technology Data Exchange (ETDEWEB)

    Castano, M.L.; Garcia, M.S.; Diego, G. de; Gomez-Briceno, D. [CIEMAT, Nuclear Fission Department, Structural Materials Program, Avda. Complutense 22, 28040 Madrid (Spain)

    2004-07-01

    Core components of light water reactor (LWR), mainly made of austenitic stainless steels (SS), subjected to stress and exposed to relatively high fast neutron flux may suffer a cracking process termed as Irradiation Assisted Stress Corrosion Cracking (IASCC). Neutron radiation leads to critical modifications in material characteristics, which can modify their stress corrosion cracking (SCC) response. Current knowledge highlights three fundamental factors, induced by radiation, as primary contributors to IASCC of core materials: Radiation Induced Segregation (RIS) at grain boundaries, Radiation Hardening and Radiolysis. Most of the existing literature on IASCC is focussed on the influence of RIS, mainly chromium depletion, which can promote IASCC in oxidizing environments, such a Boiling Water Reactor (BWR) under normal water chemistry. However, in non-oxidizing environments, such as primary water of Pressurized Water Reactor (PWR) or BWR hydrogen water chemistry, the role played by chromium depletion at grain boundary on IASCC behaviour of highly irradiated material is irrelevant. One important issue with limited study is the effect of radiation induced hardening. The role of hardening on IASCC is became stronger considered, especially for environments where other factors, like micro-chemistry, have no significant influence. To formulate the mechanism of IASCC, a well-established method is to isolate and quantify the effect of individual parameters. The use of unirradiated material and the simulation of the irradiation effects is a procedure used with success for evaluating the influence of irradiation effects. Radiation hardening can be simulated by mechanical deformation and, although some differences exist in the types of defects produced, it is believed that the study of the SCC behaviour of unirradiated materials with different hardening levels would contribute to the understanding of IASCC mechanism. In order to evaluate the influence of hardening on the

  3. Influence of Cooling Condition on the Performance of Grinding Hardened Layer in Grind-hardening

    Science.gov (United States)

    Wang, G. C.; Chen, J.; Xu, G. Y.; Li, X.

    2018-02-01

    45# steel was grinded and hardened on a surface grinding machine to study the effect of three different cooling media, including emulsion, dry air and liquid nitrogen, on the microstructure and properties of the hardened layer. The results show that the microstructure of material surface hardened with emulsion is pearlite and no hardened layer. The surface roughness is small and the residual stress is compressive stress. With cooling condition of liquid nitrogen and dry air, the specimen surface are hardened, the organization is martensite, the surface roughness is also not changed, but high hardness of hardened layer and surface compressive stress were obtained when grinding using liquid nitrogen. The deeper hardened layer grinded with dry air was obtained and surface residual stress is tensile stress. This study provides an experimental basis for choosing the appropriate cooling mode to effectively control the performance of grinding hardened layer.

  4. A novel multi-actuation CMOS RF MEMS switch

    Science.gov (United States)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  5. A MGy radiation-hardened sensor instrumentation link for nuclear reactor monitoring and remote handling

    Energy Technology Data Exchange (ETDEWEB)

    Verbeeck, Jens; Cao, Ying [KU Leuven - KUL, Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Mont Casellas, Laura; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy - F4E, c/Josep,n deg. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. OTL, 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); De Cock, Wouter; Vermeeren, Ludo [SCK-CEN, Boeretang 200, 2400 Mol (Belgium); Steyaert, Michiel [KU Leuven, ESAT-MICAS, KasteelparkArenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, KasteelparkArenberg 10, 3001 Heverlee (Belgium)

    2015-07-01

    Decommissioning, dismantling and remote handling applications in nuclear facilities all require robotic solutions that are able to survive in radiation environments. Recently raised safety, radiation hardness and cost efficiency demands from both the nuclear regulatory and the society impose severe challenges in traditional methods. For example, in case of the dismantling of the Fukushima sites, solutions that survive accumulated doses higher than 1 MGy are mandatory. To allow remote operation of these tools in nuclear environments, electronics were used to be shielded with several centimeters of lead or even completely banned in these solutions. However, shielding electronics always leads to bulky and heavy solutions, which reduces the flexibility of robotic tools. It also requires longer repair time and produces extra waste further in a dismantling or decommissioning cycle. In addition, often in current reactor designs, due to size restrictions and the need to inspect very tight areas there are limitations to the use of shielding. A MGy radiation-hardened sensor instrumentation link developed by MAGyICS provides a solution to build a flexible, easy removable and small I and C module with MGy radiation tolerance without any shielding. Hereby it removes all these pains to implement electronics in robotic tools. The demonstrated solution in this poster is developed for ITER Remote Handling equipments operating in high radiation environments (>1 MGy) in and around the Tokamak. In order to obtain adequately accurate instrumentation and control information, as well as to ease the umbilical management, there is a need of front-end electronics that will have to be located close to those actuators and sensors on the remote handling tool. In particular, for diverter remote handling, it is estimated that these components will face gamma radiation up to 300 Gy/h (in-vessel) and a total dose of 1 MGy. The radiation-hardened sensor instrumentation link presented here, consists

  6. Development of a 750x750 pixels CMOS imager sensor for tracking applications

    Science.gov (United States)

    Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

    2017-11-01

    Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on

  7. SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

    Science.gov (United States)

    Tang, Zhaohuan; Fu, Xinghua; Yang, Fashun; Tan, Kaizhou; Ma, Kui; Wu, Xue; Lin, Jiexing

    2017-12-01

    Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture (SEGR) and single event burnout (SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers. Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs. Project supported by the National Natural Science Foundation of China (No. 61464002), the Grand Science and Technology Special Project in Guizhou Province of China (No. [2015]6006), and the Ministry of Education Open Foundation for Semiconductor Power Device Reliability (No. 010201).

  8. Devices for obtaining information about radiation sources

    International Nuclear Information System (INIS)

    Tosswill, C.H.

    1981-01-01

    The invention provides a sensitive, fast high-resolution device for obtaining information about the distribution of gamma and X-radiation sources and provides a radiation detector useful in such a device. It comprises a slit collimator with a multiplicity of slits each with slit-defining walls of material and thickness to absorb beam components impinging on them. The slits extend further in one direction than the other. The detector for separately detecting beam components passing through the slits also provides data output signals. It comprises a plurality of radiation transducing portions which are not photoconductor elements each at the end of a slit. A positioner operates to change the transverse position of the slits and radiation transducing portions relative to the source, wherein each radiation transducing element is positioned within its respective slit between the slit defining walls. Full details and preferred embodiments are given. (U.K.)

  9. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  10. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  11. Radiation hardening commercial off-the-shelf erbium doped fibers by optimal photo-annealing source

    Science.gov (United States)

    Peng, Tz-Shiuan; Liu, Ren-Young; Lin, Yen-Chih; Mao, Ming-Hua; Wang, Lon A.

    2017-09-01

    Erbium doped fibers (EDFs) based devices are widely employed in space for optical communication [1], remote sensing [2], and navigation applications, e.g. interferometric fiber optic gyroscope (IFOG). However, the EDF suffers severely radiation induced attenuation (RIA) in radiation environments, e.g. space applications and nuclear reactors [3].

  12. Flexible-CMOS and biocompatible piezoelectric AlN material for MEMS applications

    International Nuclear Information System (INIS)

    Jackson, Nathan; Keeney, Lynette; Mathewson, Alan

    2013-01-01

    The development of a CMOS compatible flexible piezoelectric material is desired for numerous applications and in particular for biomedical MEMS devices. Aluminum nitride (AlN) is the most commonly used CMOS compatible piezoelectric material, which is typically deposited on Si in order to enhance the c-axis (002) crystal orientation which gives AlN its high piezoelectric properties. This paper reports on the successful deposition of AlN on polyimide (PI-2611) material. The AlN deposited has a FWHM (002) value of 5.1° and a piezoelectric d 33 value of 1.12 pm V −1 , and SEM images show high quality columnar grains. The highly crystalline AlN material is due to the semi-crystalline properties of the polyimide film used. Cytotoxicity testing showed the AlN/polyimide material to be non-toxic to 3T3 cells and primary neurons. Surface properties of the AlN/polyimide film were evaluated as they have a significant effect on the adhesion of cells to the film. The results show neurons adhering to the AlN surface. The results of this paper show the characterization of a new flexible-CMOS and biocompatible AlN/polyimide material for MEMS devices with improved crystallinity and piezoelectric properties. (paper)

  13. Devices for obtaining information about radiation sources

    International Nuclear Information System (INIS)

    Tosswill, C.H.

    1981-01-01

    The invention provides a sensitive, fast, high-resolution device for obtaining information about the distribution of gamma and X-radiation sources and provides a radiation detector useful in such a device. It comprises a slit collimator with a multiplicity of slits each with slit-defining walls of material and thickness to absorb beam components impinging on them. The slits extend further in one transverse direction than the other. The detector for separately detecting beam components passing through the slits also provides data output signals. It comprises a plurality of radiation transducing portions, each at the end of a slit. A positioner changes the transverse position of the slits and radiation transducer (a photoconductor) relative to the source. Applications are in nuclear medicine and industry. Full details and preferred embodiments are given. (U.K.)

  14. Radiation sensitive area detection device and method

    Science.gov (United States)

    Carter, Daniel C. (Inventor); Hecht, Diana L. (Inventor); Witherow, William K. (Inventor)

    1991-01-01

    A radiation sensitive area detection device for use in conjunction with an X ray, ultraviolet or other radiation source is provided which comprises a phosphor containing film which releases a stored diffraction pattern image in response to incoming light or other electromagnetic wave. A light source such as a helium-neon laser, an optical fiber capable of directing light from the laser source onto the phosphor film and also capable of channelling the fluoresced light from the phosphor film to an integrating sphere which directs the light to a signal processing means including a light receiving means such as a photomultiplier tube. The signal processing means allows translation of the fluoresced light in order to detect the original pattern caused by the diffraction of the radiation by the original sample. The optical fiber is retained directly in front of the phosphor screen by a thin metal holder which moves up and down across the phosphor screen and which features a replaceable pinhole which allows easy adjustment of the resolution of the light projected onto the phosphor film. The device produces near real time images with high spatial resolution and without the distortion that accompanies prior art devices employing photomultiplier tubes. A method is also provided for carrying out radiation area detection using the device of the invention.

  15. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    Science.gov (United States)

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

  16. Influence of transfer gate design and bias on the radiation hardness of pinned photodiode CMOS image sensors

    International Nuclear Information System (INIS)

    Goiffon, V.; Estribeau, M.; Cervantes, P.; Molina, R.; Magnan, P.; Gaillardin, M.

    2014-01-01

    The effects of Cobalt 60 gamma-ray irradiation on pinned photodiode (PPD) CMOS image sensors (CIS) are investigated by comparing the total ionizing dose (TID) response of several transfer gate (TG) and PPD designs manufactured using a 180 nm CIS process. The TID induced variations of charge transfer efficiency (CTE), pinning voltage, equilibrium full well capacity (EFWC), full well capacity (FWC) and dark current measured on the different pixel designs lead to the conclusion that only three degradation sources are responsible for all the observed radiation effects: the pre-metal dielectric (PMD) positive trapped charge, the TG sidewall spacer positive trapped charge and, with less influence, the TG channel shallow trench isolation (STI) trapped charge. The different FWC evolutions with TID presented here are in very good agreement with a recently proposed analytical model. This work also demonstrates that the peripheral STI is not responsible for the observed degradations and thus that the enclosed layout TG design does not improve the radiation hardness of PPD CIS. The results of this study also lead to the conclusion that the TG OFF voltage bias during irradiation has no influence on the radiation effects. Alternative design and process solutions to improve the radiation hardness of PPD CIS are discussed. (authors)

  17. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  18. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    International Nuclear Information System (INIS)

    Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

    2011-01-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  19. Method and device for controlling radiation

    International Nuclear Information System (INIS)

    Wilhelm, G.M.

    1979-01-01

    A device which will control radiation emanating from colour television sets is described. It consists of two transparent plates the same size as a television screen, with a thin layer of transparent mineral oil sealed between them. The device may be installed by the manufacturer or bought separately and installed by the user. (LL)

  20. CMOS/SOS RAM transient radiation upset and ''inversion'' effect investigation

    International Nuclear Information System (INIS)

    Nikiforov, A.Y.; Poljakov, I.V.

    1996-01-01

    The Complementary Metal-Oxide-Semiconductor/Silicon-on-Sapphire Random Access Memory (CMOS/SOS RAM) transient upset and inversion effect were investigated with pulsed laser, pulsed voltage generator and low-intensity light simulators. It was found that the inversion of information occurs due to memory cell photocurrents simultaneously with the power supply voltage drop transfer to memory cells outputs

  1. On-Line High Dose-Rate Gamma Ray Irradiation Test of the CCD/CMOS Cameras

    Energy Technology Data Exchange (ETDEWEB)

    Cho, Jai Wan; Jeong, Kyung Min [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-05-15

    In this paper, test results of gamma ray irradiation to CCD/CMOS cameras are described. From the CAMS (containment atmospheric monitoring system) data of Fukushima Dai-ichi nuclear power plant station, we found out that the gamma ray dose-rate when the hydrogen explosion occurred in nuclear reactors 1{approx}3 is about 160 Gy/h. If assumed that the emergency response robot for the management of severe accident of the nuclear power plant has been sent into the reactor area to grasp the inside situation of reactor building and to take precautionary measures against releasing radioactive materials, the CCD/CMOS cameras, which are loaded with the robot, serve as eye of the emergency response robot. In the case of the Japanese Quince robot system, which was sent to carry out investigating the unit 2 reactor building refueling floor situation, 7 CCD/CMOS cameras are used. 2 CCD cameras of Quince robot are used for the forward and backward monitoring of the surroundings during navigation. And 2 CCD (or CMOS) cameras are used for monitoring the status of front-end and back-end motion mechanics such as flippers and crawlers. A CCD camera with wide field of view optics is used for monitoring the status of the communication (VDSL) cable reel. And another 2 CCD cameras are assigned for reading the indication value of the radiation dosimeter and the instrument. In the preceding assumptions, a major problem which arises when dealing with CCD/CMOS cameras in the severe accident situations of the nuclear power plant is the presence of high dose-rate gamma irradiation fields. In the case of the DBA (design basis accident) situations of the nuclear power plant, in order to use a CCD/CMOS camera as an ad-hoc monitoring unit in the vicinity of high radioactivity structures and components of the nuclear reactor area, a robust survivability of this camera in such intense gamma-radiation fields therefore should be verified. The CCD/CMOS cameras of various types were gamma irradiated at a

  2. Radiation dose rate measuring device

    International Nuclear Information System (INIS)

    Sorber, R.

    1987-01-01

    A portable device is described for in-field usage for measuring the dose rate of an ambient beta radiation field, comprising: a housing, substantially impervious to beta radiation, defining an ionization chamber and having an opening into the ionization chamber; beta radiation pervious electrically-conductive window means covering the opening and entrapping, within the ionization chamber, a quantity of gaseous molecules adapted to ionize upon impact with beta radiation particles; electrode means disposed within the ionization chamber and having a generally shallow concave surface terminating in a generally annular rim disposed at a substantially close spacing to the window means. It is configured to substantially conform to the window means to define a known beta radiation sensitive volume generally between the window means and the concave surface of the electrode means. The concave surface is effective to substantially fully expose the beta radiation sensitive volume to the radiation field over substantially the full ambient area faced by the window means

  3. Terrestrial radiation effects in ULSI devices and electronic systems

    CERN Document Server

    Ibe, Eishi H

    2014-01-01

    A practical guide on how mathematical approaches can be used to analyze and control radiation effects in semiconductor devices within various environments Covers faults in ULSI devices to failures in electronic systems caused by a wide variety of radiation fields, including electrons, alpha -rays, muons, gamma rays, neutrons and heavy ions. Readers will learn the environmental radiation features at the ground or avionics altitude. Readers will also learn how to make numerical models from physical insight and what kind of mathematical approaches should be implemented to analyze the radiation effects. A wide variety of mitigation techniques against soft-errors are reviewed and discussed. The author shows how to model sophisticated radiation effects in condensed matter in order to quantify and control them. The book provides the reader with the knowledge on a wide variety of radiation fields and their effects on the electronic devices and systems. It explains how electronic systems including servers and rout...

  4. An innovation for prevention of radiation induced latchup

    International Nuclear Information System (INIS)

    Xu Xianguo; Hu Jiandong; Xu Xi

    2006-01-01

    An innovation for prevention latchup, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After the design of pseudo-latchup path method is studied in detail, a practice and the corresponding simulation and experiment validation result are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but not to eliminate the dose rate upset in bulk-Si CMOS devices. An innovation for prevention latchup, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After the design of pseudo-latchup path method is studied in detail, a practice and the corresponding simulation and experiment validation result are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but not to eliminate the dose rate upset in bulk-Si CMOS devices. (authors)

  5. Radiation detection device

    International Nuclear Information System (INIS)

    Peschmann, Kristian.

    1982-01-01

    A radiation detector suitable for use in computer tomography device has an ionization chamber which comprises a high voltage electrode, a collector electrode, a high voltage source having two terminals, one connected to the high voltage electrode, current measuring means having two terminals, one connected to the high voltage source and the other to the collector electrode, and an auxilliary electrode near and parallel to the entrance window of the device, having one adjacent to the high voltage electrode and the other adjacent but not connected to the collector electrode. The auxilliary electrode is connected to the high voltage source. In this way the electric field between the high voltage and collector electrodes is made homogeneous in the vicinity of the auxilliary electrode, improving the measuring speed of the detector

  6. Radiation Testing on State-of-the-Art CMOS: Challenges, Plans, and Preliminary Results

    Science.gov (United States)

    LaBel, Kenneth A.; Cohn, Lewis M.

    2009-01-01

    At GOMAC 2007 and 2008, we discussed a variety of challenges for radiation testing of modern semiconductor devices and technologies [1, 2]. In this presentation, we provide more specific details in this on-going investigation focusing on out-of-the-box lessons observed for providing radiation effects assurances as well as preliminary test results.

  7. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  8. High efficiency grating couplers based on shared process with CMOS MOSFETs

    International Nuclear Information System (INIS)

    Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  9. Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

    Science.gov (United States)

    Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

    2017-06-01

    Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

  10. Pitch dependence of the tolerance of CMOS monolithic active pixel sensors to non-ionizing radiation

    International Nuclear Information System (INIS)

    Doering, D.; Deveaux, M.; Domachowski, M.; Fröhlich, I.; Koziel, M.; Müntz, C.; Scharrer, P.; Stroth, J.

    2013-01-01

    CMOS monolithic active pixel sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few μm), a detection efficiency of ≳99.9%, very low material budget (0.05%X 0 ) and good radiation tolerance (≳1Mrad, ≳10 13 n eq /cm 2 ) (Deveaux et al. [1]). This makes them an interesting technology for various applications in heavy ion and particle physics. Their tolerance to bulk damage was recently improved by using high-resistivity (∼1kΩcm) epitaxial layers as sensitive volume (Deveaux et al. [1], Dorokhov et al. [2]). The radiation tolerance of conventional MAPS is known to depend on the pixel pitch. This is as a higher pitch extends the distance, which signal electrons have to travel by thermal diffusion before being collected. Increased diffusion paths turn into a higher probability of loosing signal charge due to recombination. Provided that a similar effect exists in MAPS with high-resistivity epitaxial layer, it could be used to extend their radiation tolerance further. We addressed this question with MIMOSA-18AHR prototypes, which were provided by the IPHC Strasbourg and irradiated with reactor neutrons. We report about the results of this study and provide evidences that MAPS with 10μm pixel pitch tolerate doses of ≳3×10 14 n eq /cm 2

  11. CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

    Science.gov (United States)

    Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

    2011-09-01

    Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

  12. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  13. Tunable radiation emitting semiconductor device

    NARCIS (Netherlands)

    2009-01-01

    A tunable radiation emitting semiconductor device includes at least one elongated structure at least partially fabricated from one or more semiconductor materials exhibiting a bandgap characteristic including one or more energy transitions whose energies correspond to photon energies of light

  14. Radiation sensitive solid state devices

    International Nuclear Information System (INIS)

    Shannon, J.M.; Ralph, J.E.

    1975-01-01

    A solid state radiation sensitive device is described employing JFETs as the sensitive elements. Two terminal construction is achieved by using a common conductor to capacitively couple to the JFET gate and to one of the source and drain connections. (auth)

  15. International Standards for Radiation Sterilization of Medical Devices

    International Nuclear Information System (INIS)

    Miller, A.

    2007-01-01

    For a terminally sterilized medical device to be designated '' STERILE '', probability of finding the viable micro-organisms in the device shall be equal to or less than 1 x 10 -6 (EN 556-1:2001: Sterilization of medical devices - Requirements for medical devices to be designated '' STERILE '' - Part 1: Requirements for terminally sterilized medical devices). Author presents the main legal aspects of the international standards for radiation sterilization of medical devices

  16. DICE based flip-flop with SET pulse discriminator on a 90 nm bulk CMOS process

    International Nuclear Information System (INIS)

    Maru, A.; Kuboyama, S.; Shindou, H.; Ebihara, T.; Tamura, T.; Makihara, A.; Hirao, Toshio

    2010-01-01

    In recent years, due to the demand for increased integration and device scaling, integrated circuits have been designed with the design rule less than 100 nm. In such integrated circuits, SEUs and SETs are serious problems because their supply voltage and the threshold voltage of the transistors are decreased. A DICE-based flip-flop with a SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated. Its improved performance was demonstrated through radiation testing and discussion. SEU sensitivity for the angled irradiation was measured and discussed in this study. The test of edge-on irradiation was performed for the first time. The importance of the angled irradiation for the memory cells that have redundant memory nodes was demonstrated. (author)

  17. Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

    Science.gov (United States)

    Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

    2008-09-01

    In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

  18. A comprehensive model on field-effect pnpn devices (Z2-FET)

    Science.gov (United States)

    Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

    2017-08-01

    A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

  19. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  20. Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

    Science.gov (United States)

    Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

    2018-05-01

    Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.