Flexible programmable logic module

Science.gov (United States)

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

International Nuclear Information System (INIS)

Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve

2014-01-01

Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

Energy Technology Data Exchange (ETDEWEB)

Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve [Doosan HF Controls Corp, Carrollton (United States)

2014-08-15

Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Implementation of BES-III TOF trigger system in programmable logic devices

International Nuclear Information System (INIS)

Zheng Wei; Liu Shubin; Liu Xuzong; An Qi

2009-01-01

The TOF trigger sub-system on the upgrading Beijing Spectrometer is designed to receive 368 bits fast hit signals from the front end electronics module to yield 7 bits trigger information according to the physical requirement. It sends the processed real time trigger information to the Global-Trigger-Logic to generate the primal trigger signal L1, and sends processed 136 bits real time position information to the Track-Match-Logic to calculate the particle flight tracks. The sub-system also packages the valid events for the DAQ system to read out. Following the reconfigurable concept, a large number of programmable logic devices are employed to increase the flexibility and reliability of the system, and decrease the complexity and the space requirement of PCB layout. This paper describes the implementation of the kernel trigger logic in a programmable logic device. (authors)

A Fault-tolerant RISC Microprocessor for Spacecraft Applications

Science.gov (United States)

Timoc, Constantin; Benz, Harry

1990-01-01

Viewgraphs on a fault-tolerant RISC microprocessor for spacecraft applications are presented. Topics covered include: reduced instruction set computer; fault tolerant registers; fault tolerant ALU; and double rail CMOS logic.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

Science.gov (United States)

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

International Nuclear Information System (INIS)

Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

2010-01-01

Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

Small Microprocessor for ASIC or FPGA Implementation

Science.gov (United States)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

Microprocessor multi-task monitor

International Nuclear Information System (INIS)

Ludemann, C.A.

1983-01-01

This paper describes a multi-task monitor program for microprocessors. Although written for the Intel 8085, it incorporates features that would be beneficial for implementation in other microprocessors used in controlling and monitoring experiments and accelerators. The monitor places permanent programs (tasks) arbitrarily located throughout ROM in a priority ordered queue. The programmer is provided with the flexibility to add new tasks or modified versions of existing tasks, without having to comply with previously defined task boundaries or having to reprogram all of ROM. Scheduling of tasks is triggered by timers, outside stimuli (interrupts), or inter-task communications. Context switching time is of the order of tenths of a milllisecond

An INTEL 8080 microprocessor development system

International Nuclear Information System (INIS)

Horne, P.J.

1977-01-01

The INTEL 8080 has become one of the two most widely used microprocessors at CERN, the other being the MOTOROLA 6800. Even thouth this is the case, there have been, to date, only rudimentary facilities available for aiding the development of application programs for this microprocessor. An ideal development system is one which has a sophisticated editing and filing system, an assembler/compiler, and access to the microprocessor application. In many instances access to a PROM programmer is also required, as the application may utilize only PROMs for program storage. With these thoughts in mind, an INTEL 8080 microprocessor development system was implemented in the Proton Synchrotron (PS) Division. This system utilizes a PDP 11/45 as the editing and file-handling machine, and an MSC 8/MOD 80 microcomputer for assembling, PROM programming and debugging user programs at run time. The two machines are linked by an existing CAMAC crate system which will also provide the means of access to microprocessor applications in CAMAC and the interface of the development system to any other application. (Auth.)

Programmable logic control applied to a coal preparation plant complex

Energy Technology Data Exchange (ETDEWEB)

Krahenbil, L W

1979-02-01

The programmable Logic Controller (PLC), at its present stage of evolution, is now considered as a mature control system. The PLC combines the solid-state reliability of hard-wired logic and computer control systems with the simplicity of a relay ladder logic. Relay symbolic programming through a function-oriented keyboard provides a means which plant personnel can easily become accoustomed to work with. In a large coal facility, it is shown that the control engineer can provide improved control flexibility with the advanced capabilities of the PLC.

Programming Programmable Logic Controller. High-Technology Training Module.

Science.gov (United States)

Lipsky, Kevin

This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

International Nuclear Information System (INIS)

Yamanashi, Y; Akimoto, A; Yoshikawa, N; Tanaka, M; Kawamoto, T; Kamiya, Y; Fujimaki, A; Terai, H; Yorozu, S

2006-01-01

A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm -2 Nb standard process and confirmed its correct operation experimentally

Dependable Design Flow for Protection Systems using Programmable Logic Devices

CERN Document Server

Kwiatkowski, M

2011-01-01

Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. The final synthesis result, used to generate the bit-stream to program the device, must be shown to meet the design’s requirements. This paper describes how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example is given for one of the critical functions of the Safe Machine Parameters (SMP) system, used in the protection of the Large Hadron Collider (LHC) at CERN. CERN is also working towards an adaptation of the IEC- 61508 lifecycle designed for Machine Protection Systems (MPS), and the High Energy Physics environment, implementation of a protection function in FPGA code is only one small step of this lifecycle. The ultimate aim of this project is to cre...

Microprocessor-controlled, programmable ramp voltage generator

International Nuclear Information System (INIS)

Hopwood, J.

1978-11-01

A special-purpose voltage generator has been developed for driving the quadrupole mass filter of a residual gas analyzer. The generator is microprocessor-controlled with desired ramping parameters programmed by setting front-panel digital thumb switches. The start voltage, stop voltage, and time of each excursion are selectable. A maximum of five start-stop levels may be pre-selected for each program. The ramp voltage is 0 to 10 volts with sweep times from 0.1 to 999.99 seconds

Programmable logic controllers in Heavy Water Project, Manuguru (Paper No. 3.4)

International Nuclear Information System (INIS)

Gupta, S.C.; Bhaskar, R.; Maiti, A.; Venkatesu, G.; Satish, P.; Goel, R.K.

1992-01-01

Enhancement to plant operational flexibility has been achieved in Heavy Water Project, Manuguru by installing programmable logic controllers for its control equipment. The earlier sulfide based Heavy Water Plant, Kota is using relay logic and diode based program-matrix for binary controls. Performance improvement and advantages of PLC and experience in its operation are described. (author). 3 refs

A microarchitecture for resource-limited superscalar microprocessors

Science.gov (United States)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined

Microprocessors

CERN Document Server

Cornillie, O A R

1985-01-01

Microprocessors presents an overview of the state of the art in the field of microprocessors and illustrates, with the aid of patents, its utilization and application. Organized into six parts, the book begins with an introduction to the microprocessor, microcomputer, and software. Parts I-III focus on program control, digital control, and electrical motor control. Subsequent parts show the medical applications, measuring instruments, and treatment of data in microprocessors.

Integrated plant automation using programmable logic controllers

International Nuclear Information System (INIS)

Qureshi, S.A.

2002-01-01

In the world of automation the Programmable Logic Controller (PLC) has became for control. It now not only replaces the earlier relay logic controls but also has taken over many additional control functions. Initially the PLC was used to replace relay logic, but is ever-increasing range of functions means that it is found in many and more complex applications. As the structure of the PLC is based on the same principles as those employed in computer architecture, it is capable of performance not only relay switching tasks, but also other applications such as counting, calculating, comparing and the processing of analogue signals. Due to the simplicity of entering and modifying the programmed instructions to suit the requirements of the process under control, the PLC is truly a versatile and flexible device that can be employed easily and efficiently to repeatedly control tasks that vary in nature and complexes. A photograph of the Siemens S-5 95U. To illustrate the advantage of using a PLC over a traditional relay logic system, consider a control system with 20 input/output points. This assembly could comprise 60-80 relays, some counter/timers and a great deal of wiring. This assembly would be cumbersome with a power consumption of 30-40VA. A considerable time would be required to design, test and commission the assembly and once it is in full working order any desired modification, even of minor nature, could require major hardware changes. (author)

The use of microprocessors at TRIUMF in the control of radiation safety interlock systems

International Nuclear Information System (INIS)

King, L.

1988-01-01

At TRIUMF the cyclotron vault, all primary beam lines, and each experimental area has a dedicated control unit to manage the safety interlock control of the area lockup sequence, beam blocker drive and area access. Typically each area has 24 devices which are monitored to control 16 outputs. These control units (Area Safety Units) were first implemented through the use of relay logic. The relay logic was reliable but difficult to modify to incorporate changes to the areas. In 1979 it was decided to use microprocessors in the form of single board computers to control the Area Safety Units. The details of the hardware and software is discussed as well as the advantages of microprocessor control

Universal Programmable Logic Controller Software

International Nuclear Information System (INIS)

Mohd Arif Hamzah; Azhar Shamsudin; Fadil Ismail; Muhammad Nor Atan; Anwar Abdul Rahman

2013-01-01

Programmable Logic Controller (PLC) is an electronic hardware which is widely used in manufacturing or processing industries. It is also serve as the main control system hardware to run the production and manufacturing process. There are more than ten (10) well known company producing PLC hardware, with their own specialties, including the method of programming and language used. Malaysia Nuclear Agency have various plant and equipment, runs and control by PLC, such as Mintex Sinagama Plant, Alurtron Plant, and few laboratory equipment. Since all the equipment and plant are equipped with various brand or different manufacture of PLC, it creates difficulties to the supporting staff to master the control program. The same problems occur for new application of this hardware, since there no policies to purchase only one specific brand of PLC. (author)

Application of programmable logic controller in nuclear experiments

International Nuclear Information System (INIS)

Ponikvar, D.

1991-09-01

The applicability of programmable logic controller (PLC) in nuclear experiments was studied on an example that simulated the monitoring and control of an ion beam in an accelerator. Using infrared and laser light, a comparison was made between the complexity and suitability of PLC compared to a setup using a personal computer. The experiments are described in detail. The routines for registration of signals from appropriate sensors and for control of the stepper monitor were written in quick BASIC. (author). 5 figs

Microprocessor controller for stepping motors

International Nuclear Information System (INIS)

Strait, B.G.; Thuot, M.E.

1977-01-01

A new concept for digital computer control of multiple stepping motors which operate in a severe electromagnetic pulse environment is presented. The motors position mirrors in the beam-alignment system of a 100-kJ CO 2 laser. An asynchronous communications channel of a computer is used to send coded messages, containing the motor address and stepping-command information, to the stepping-motor controller in a bit serial format over a fiber-optics communications link. The addressed controller responds by transmitting to the computer its address and other motor information, thus confirming the received message. Each controller is capable of controlling three stepping motors. The controller contains the fiber-optics interface, a microprocessor, and the stepping-motor driven circuits. The microprocessor program, which resides in an EPROM, decodes the received messages, transmits responses, performs the stepping-motor sequence logic, maintains motor-position information, and monitors the motor's reference switch. For multiple stepping-motor application, the controllers are connected in a daisy chain providing control of many motors from one asynchronous communications channel of the computer

The Programmable Logic Controller and its application in nuclear reactor systems

International Nuclear Information System (INIS)

Palomar, J.; Wyman, R.

1993-09-01

This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out

The Programmable Logic Controller and its application in nuclear reactor systems

Energy Technology Data Exchange (ETDEWEB)

Palomar, J.; Wyman, R. [Lawrence Livermore National Lab., CA (United States)

1993-09-01

This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

Roles of programmable logic controllers in fuel reprocessing plants

International Nuclear Information System (INIS)

Mishra, Hrishikesh; Balakrishnan, V.P.; Pandya, G.J.

1999-01-01

Fuel charging facility is another application of Programmable Logic Controllers (PLC) in fuel reprocessing plants, that involves automatic operation of fuel cask dolly, charging motor, pneumatic doors, clutches, clamps, stepper motors and rod pushers in a pre-determined sequence. Block diagram of ACF system is given for underlining the scope of control and interlocks requirements involved for automation of the fuel charging system has been provided for the purpose at KARP Plant, Kalpakkam

Cardiac output measurement instruments controlled by microprocessors

International Nuclear Information System (INIS)

Spector, M.; Barritault, L.; Boeri, C.; Fauchet, M.; Gambini, D.; Vernejoul, P. de

The nuclear medicine and biophysics laboratory of the Necker-Enfants malades University Hospital Centre has built a microprocessor controlled Cardiac flowmetre. The principle of the cardiac output measurement from a radiocardiogram is well established. After injection of a radioactive indicator upstream from the heart cavities the dilution curve is obtained by the use of a gamma-ray precordial detector. This curve normally displays two peaks due to passage of the indicator into the right and left sides of the heart respectively. The output is then obtained from the stewart Hamilton principle once recirculation is eliminated. The graphic method used for the calculation however is long and tedious. The decreasing fraction of the dilution curve is projected in logarithmic space in order to eliminate recirculation by determining the mean straight line from which the decreasing exponential is obtained. The principle of the use of microprocessors is explained (electronics, logics) [fr

Concept report: Microprocessor control of electrical power system

Science.gov (United States)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

Final Report and Documentation for the PLD11 Multipurpose Programmable Logic VME Board Design

International Nuclear Information System (INIS)

Hutchinson, Robert L.; Pierson, Lyndon G.; Robertson, Perry J.; Tarman, Thomas D.; Witzke, Edward L.

1999-01-01

The PLD11 board is a 9U VME board containing 11 Altera 10K100 Programmable Logic Devices, controlled impedance clock tree, VME interface, programming inteface, 0C3 (155 Mbps) interface and serial port. The 11 Altera 10K100 Programmable Logic Devices arranged to provide four 96 bit wide buses for a total of 384 parallel digital data lines in and out of the board that can operate up to 100 Mhz for a aggrigate throughput of 38.4 Gpbs. The 14.44'' X 15.75'' board has over 1.1 million programmable gates that can be programmed through a serial interace. The board contains a clock reference and 50 ohm clock distribution tree that can drive each of the eleven 10K100 devices with two critically timed clock references. Five external clock references can be used to drive five additional PLD 11 boards for a total of six boards operating all from the same synchronous clock reference. A system of six boards provides just under 7 million programmable gates

Microprocessor interfacing

CERN Document Server

Vears, R E

2014-01-01

Microprocessor Interfacing provides the coverage of the Business and Technician Education Council level NIII unit in Microprocessor Interfacing (syllabus U86/335). Composed of seven chapters, the book explains the foundation in microprocessor interfacing techniques in hardware and software that can be used for problem identification and solving. The book focuses on the 6502, Z80, and 6800/02 microprocessor families. The technique starts with signal conditioning, filtering, and cleaning before the signal can be processed. The signal conversion, from analog to digital or vice versa, is expl

Microprocessorized message multiplexer

International Nuclear Information System (INIS)

Ejzman, S.; Guglielmi, L.; Jaeger, J.J.

1980-07-01

The 'Microprocessorized Message Multiplexer' is an elementary development tool used to create and debug the software of a target microprocessor (User Module: UM). It connects together four devices: a terminal, a cassette recorder, the target microprocessor and a host computer where macro and editor for the M 6800 microprocessor are resident [fr

TRIESTE: College on Microprocessors

International Nuclear Information System (INIS)

Anon.

1981-01-01

The International Centre for Theoretical Physics, set up at Trieste in 1964, has as its major task the provision of a stimulating intellectual environment for physicists from developing countries. This goal is furthered by a varied programme of courses for visiting scientists. Not all the courses remain in the rarefied atmosphere of theory and in September a very successful 'College on Microprocessors: Technology and Applications in Physics' was held. It was a prime example of the efforts being made to spread important modern technology into the developing countries

A new fast and programmable trigger logic

International Nuclear Information System (INIS)

Fucci, A.; Amendolia, S.R.; Bertolucci, E.; Bottigli, U.; Bradaschia, C.; Foa, L.; Giazotto, A.; Giorgi, M.; Givoletti, M.; Lucardesi, P.; Menzione, A.; Passuello, D.; Quaglia, M.; Ristori, L.; Rolandi, L.; Salvadori, P.; Scribano, A.; Stanga, R.; Stefanini, A.; Vincelli, M.L.

1977-01-01

The NA1 (FRAMM) experiment, under construction for the CERN-SPS North Area, deals with more than 1000 counter signals which have to be combined together in order to build sophisticated and highly selective triggers. These requirements have led to the development of a low cost, combinatorial, fast electronics which can replace, in an advantageous way the standard NIM electronics at the trigger level. The essential performances of the basic circuit are: 1) programmability of any desired logical expression; 2) trigger time independent of the chosen expression; 3) reduced cost and compactness due to the use of commercial RAMs, PROMs, and PLAs; 4) short delay, less than 20 ns, between input and output pulses. (Auth.)

The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

DEFF Research Database (Denmark)

Christensen, Kåre Tais; Jensen, P.; Korger, P.

1998-01-01

This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

A multi-channel scaler designed with programmable logic device

International Nuclear Information System (INIS)

Sun Yongjie; Li Cheng; Xing Tao; Zhang Junjie

2004-01-01

This scaler used programmable logic device is a design for the electronics of telescope system of the beam. The scaler can scale 30 ECL inputs at the same time. With the EPP (Enhanced Parallel Port) modes of the Parallel Port, the transmitted rate of data is 2 MB/s. This scaler can be used in the position system of MWPC (Multi-Wires Proportional Chamber). Tested with particles of 5 x 10 3 /s, the scaler gives a credible and stable result. (authors)

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

Science.gov (United States)

Todorovich, E.; Marone, J. A.; Vazquez, M.

2012-01-01

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

Performance Testing Methodology for Safety-Critical Programmable Logic Controller

International Nuclear Information System (INIS)

Kim, Chang Ho; Oh, Do Young; Kim, Ji Hyeon; Kim, Sung Ho; Sohn, Se Do

2009-01-01

The Programmable Logic Controller (PLC) for use in Nuclear Power Plant safety-related applications is being developed and tested first time in Korea. This safety-related PLC is being developed with requirements of regulatory guideline and industry standards for safety system. To test that the quality of the developed PLC is sufficient to be used in safety critical system, document review and various product testings were performed over the development documents for S/W, H/W, and V/V. This paper provides the performance testing methodology and its effectiveness for PLC platform conducted by KOPEC

Field programmable gate array reliability analysis using the dynamic flow graph methodology

Energy Technology Data Exchange (ETDEWEB)

McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

2016-10-15

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Programmable Logic Controllers for Systems of Automatic of the Level Crossing

Directory of Open Access Journals (Sweden)

Mieczyslaw Kornaszewski

2006-01-01

Full Text Available The railway crossings are vulnerable to incidence of high number of accidents often deadly. In order to face this problem, the modern systems of automatic of the level crossing have been introduced. These systems are based on Programmable Logic Controllers, which allow the designers to exploit self-control mechanisms, events acquiring, technical diagnostic which in turn enable remote control and acquisition of faults.

A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

Science.gov (United States)

Kellett, C. M.

2012-01-01

This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

A microprocessor based on a two-dimensional semiconductor

Science.gov (United States)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

Microprocessor hardware reliability

Energy Technology Data Exchange (ETDEWEB)

Wright, R I

1982-01-01

Microprocessor-based technology has had an impact in nearly every area of industrial electronics and many applications have important safety implications. Microprocessors are being used for the monitoring and control of hazardous processes in the chemical, oil and power generation industries, for the control and instrumentation of aircraft and other transport systems and for the control of industrial machinery. Even in the field of nuclear reactor protection, where designers are particularly conservative, microprocessors are used to implement certain safety functions and may play increasingly important roles in protection systems in the future. Where microprocessors are simply replacing conventional hard-wired control and instrumentation systems no new hazards are created by their use. In the field of robotics, however, the microprocessor has opened up a totally new technology and with it has created possible new and as yet unknown hazards. The paper discusses some of the design and manufacturing techniques which may be used to enhance the reliability of microprocessor based systems and examines the available reliability data on lsi/vlsi microcircuits. 12 references.

Management of Industrial Processes with Programmable Logic Controller

Directory of Open Access Journals (Sweden)

Marius Tufoi

2009-10-01

Full Text Available In a modern economy, automation (the control is primarily to raise the competitiveness of a product, either directly through price or quality, or indirectly through the improvement of working conditions of staff productive. The control of industrial processes involves the management of dynamic systems that have continuous states. These systems are described by differential equations and, in general, analog inputs and outputs. Management of these systems is achieved, in general, with classical automation, by automation or with analog computers which contains modules with input / output analog performance. If states, inputs and outputs of a system can be modeled using binary variables, then these systems can be driven with Programmable Logic Controller.

Complex programmable logic device based alarm sequencer for nuclear power plants

International Nuclear Information System (INIS)

Khedkar, Ravindra; Solomon, J. Selva; KrishnaKumar, B.

2001-01-01

Complex Programmable Logic Device based Alarm Sequencer is an instrument, which detects alarms, memorizes them and displays the sequences of occurrence of alarms. It caters to sixteen alarm signals and distinguishes the sequence among any two alarms with a time resolution of 1 ms. The system described has been designed for continuous operation in process plants, nuclear power plants etc. The system has been tested and found to be working satisfactorily. (author)

Emergency Diesel: Safety-related instrumentation and control with programmable logic controllers

International Nuclear Information System (INIS)

Breidenich, G.; Luedtke, M.

2004-01-01

This report presents a new concept for the design of emergency diesel equipment protection circuits as a part of the safety related instrumentation in the nuclear power plant Biblis, units A and B. The concept was implemented with state of the art SIMATIC S7/316 programmable logic controllers (PLCs) and can be adapted to any system with high availability requirements (e.g. power plant turbines, aircraft engines, mining pumps etc). (orig.)

Stealth low-level manipulation of programmable logic controllers I/O by pin control exploitation

NARCIS (Netherlands)

Abbasi, A.; Hashemi, M.; Zambon, E.; Etalle, S.; Havarneanu, G.; Setola, R.; Nassopoulos, H.; Wolthusen, S.

2016-01-01

Input/OutputisthemechanismthroughwhichProgrammable Logic Controllers (PLCs) interact with and control the outside world. Particularly when employed in critical infrastructures, the I/O of PLCs has to be both reliable and secure. PLCs I/O like other embedded devices are controlled by a pin based

Microprocessors principles and applications

CERN Document Server

Debenham, Michael J

1979-01-01

Microprocessors: Principles and Applications deals with the principles and applications of microprocessors and covers topics ranging from computer architecture and programmed machines to microprocessor programming, support systems and software, and system design. A number of microprocessor applications are considered, including data processing, process control, and telephone switching. This book is comprised of 10 chapters and begins with a historical overview of computers and computing, followed by a discussion on computer architecture and programmed machines, paying particular attention to t

Time-space modal logic for verification of bit-slice circuits

Science.gov (United States)

Hiraishi, Hiromi

1996-03-01

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Science.gov (United States)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Application of complex programmable logic devices in memory radiation effects test system

International Nuclear Information System (INIS)

Li Yonghong; He Chaohui; Yang Hailiang; He Baoping

2005-01-01

The application of the complex programmable logic device (CPLD) in electronics is emphatically discussed. The method of using software MAX + plus II and CPLD are introduced. A new test system for memory radiation effects is established by using CPLD devices-EPM7128C84-15. The old test system's function are realized and, moreover, a number of small scale integrated circuits are reduced and the test system's reliability is improved. (authors)

Ghost in the PLC: stealth on-the-fly manipulation of programmable logic controllers’ I/O

NARCIS (Netherlands)

Abbasi, Ali

2016-01-01

Programmable Logic Controllers (PLCs) are a family of embedded devices used for physical process control. Similar to other embedded devices, PLCs are vulnerable to cyber attacks. Because they are used to control the physical processes of critical infrastructures, compromised PLCs constitute a

Newnes microprocessor pocket book

CERN Document Server

Money, Steve

2014-01-01

Newnes Microprocessor Pocket Book explains the basic hardware operation of a microprocessor and describes the actions of the various types of instruction that can be executed. A summary of the characteristics of many of the popular microprocessors is presented. Apart from the popular 8- and 16-bit microprocessors, some details are also given of the popular single chip microcomputers and of the reduced instruction set computer (RISC) type processors such as the Transputer, Novix FORTH processor, and Acorn ARM processor.Comprised of 15 chapters, this book discusses the principles involved in bot

Programmable logic controller based synchronous motor excitation system

Directory of Open Access Journals (Sweden)

Janda Žarko

2011-01-01

Full Text Available This paper presents a 3.5 MW synchronous motor excitation system reconstruction. In the proposed solution programmable logic controller is used to control motor, which drives the turbo compressor. Comparing to some other solutions that are used in similar situations, the proposed solution is superior due to its flexibility and usage of mass-production hardware. Moreover, the implementation of PLC enables easy integration of the excitation system with the other technological processes in the plant as well as in the voltage regulation of 'smart grid' system. Also, implementation of various optimization algorithms can be done comfortably and it does not require additional investment in hardware. Some experimental results that depict excitation current during motor start-up, as well as, measured static characteristics of the motor, were presented.

Programmable Array Logic Design

International Nuclear Information System (INIS)

Demon Handoyo; Djen Djen Djainal

2007-01-01

Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)

Regulatory issues on using programmable logic device in nuclear power plants

International Nuclear Information System (INIS)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H.

2012-01-01

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards

Regulatory issues on using programmable logic device in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

2012-10-15

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

International Nuclear Information System (INIS)

Bonacini, S.

2007-11-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

Introduction to bit slices and microprogramming

International Nuclear Information System (INIS)

Van Dam, A.

1981-01-01

Bit-slice logic blocks are fourth-generation LSI components which are natural extensions of traditional mulitplexers, registers, decoders, counters, ALUs, etc. Their functionality is controlled by microprogramming, typically to implement CPUs and peripheral controllers where both speed and easy programmability are required for flexibility, ease of implementation and debugging, etc. Processors built from bit-slice logic give the designer an alternative for approaching the programmibility of traditional fixed-instruction-set microprocessors with a speed closer to that of hardwired random logic. (orig.)

Project W-058 monitor and control system logic

International Nuclear Information System (INIS)

ROBERTS, J.B.

1999-01-01

This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console

Microprocessor controlled pulse charge and testing of batteries

International Nuclear Information System (INIS)

Kerezov, A.; Gishin, S.; Ivanov, Ratcho; Savov, S.

2002-01-01

The principle of the developed new method for pulse charge of batteries with microprocessor control of the electrochemical processes is the use of current pulses with microprocessor control of the period and the amplitude according to the dynamically changing state of the electrochemical system. In order to realize the method described above a programmable current source was developed. It is connected with a Personal Computer via RS232 standard serial interface in order to control the electrochemical processes. The parameters to be set, the graphical presentation of the pulse current and tension, the used quantity of electricity and electrical energy for every pulse and for the process as a hole are shown on the PC display. In order to test dry-charged and wet-charged batteries a specialized current generator was developed. It is connected also with a Personal Computer via R5232 standard serial interface in order to con-trol the testing of the starting capability of the batteries according to the requirements of the Bulgarian State Standard Ell 60095-1. (Author)

Project-Based Learning in Programmable Logic Controller

Science.gov (United States)

Seke, F. R.; Sumilat, J. M.; Kembuan, D. R. E.; Kewas, J. C.; Muchtar, H.; Ibrahim, N.

2018-02-01

Project-based learning is a learning method that uses project activities as the core of learning and requires student creativity in completing the project. The aims of this study is to investigate the influence of project-based learning methods on students with a high level of creativity in learning the Programmable Logic Controller (PLC). This study used experimental methods with experimental class and control class consisting of 24 students, with 12 students of high creativity and 12 students of low creativity. The application of project-based learning methods into the PLC courses combined with the level of student creativity enables the students to be directly involved in the work of the PLC project which gives them experience in utilizing PLCs for the benefit of the industry. Therefore, it’s concluded that project-based learning method is one of the superior learning methods to apply on highly creative students to PLC courses. This method can be used as an effort to improve student learning outcomes and student creativity as well as to educate prospective teachers to become reliable educators in theory and practice which will be tasked to create qualified human resources candidates in order to meet future industry needs.

Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

International Nuclear Information System (INIS)

KOCH, M.R.

1999-01-01

This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309/Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

Local and Remote Laboratory User Experimentation Access using Digital Programmable Logic

Directory of Open Access Journals (Sweden)

Ian A Grout

2005-06-01

Full Text Available This paper will discuss the structure and operation of a programmable logic based experimentation arrangement that is suitable for both local and remote teaching and learning scenarios targeting electronic and microelectronic circuit design and test principles. With this experimentation arrangement, the ability to provide both local and Internet based “remote” access for the student and the teacher can provide a number of advantages where physical laboratory accessibility is limited and/or the learning experience must be undertaken with one or more of the parties remotely based. The paper concentrates on the design and example use of a system developed within the University of Limerick.

Design of a Tritium-in-air-monitor using field programmable gate arrays

International Nuclear Information System (INIS)

McNelles, Phillip; Lu, Lixuan

2015-01-01

Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

A test system and supervisory control and data acquisition application with programmable logic controller for thermoelectric generators

International Nuclear Information System (INIS)

Ahiska, Rasit; Mamur, Hayati

2012-01-01

Highlights: ► A new TEG test measurement system with the PLC has been carried out. ► A new SCADA program has been written and tested for the test measurement system. ► An operator panel has been used for monitoring to the instant TEG data. ► All of the measurement data of TEG have been aggregated in the system. - Abstract: In this study, a new test measurement system and supervisory control and data acquisition application with programmable logic controller has been carried out to be enable the collection of the data of thermoelectric generator for the usage of thermoelectric modules as thermoelectric generator. During the production of the electric energy from the thermoelectric generator, the temperatures of the surfaces of the thermoelectric generator, current–voltage values obtained from output of the thermoelectric generator, hot and cold flows have been measured by the newly established system instantly. All these data have been monitored continuously from the computer and recorded by a supervisory control and data acquisition program. At the same time, in environments where there was no computer, an operator panel with the ability to communicate with the programmable logic controller has been added for the monitoring of the instant thermoelectric generator data. All of the measurement data of the thermoelectric generator have been aggregated in the new test measurement and supervisory control and data acquisition system. The setup test measurement system has been implemented on the thermoelectric generator system with about 10 W. Thermoelectric generators, Altec-GM-1 brand-coded have been examined by the new proposed test measurement system and the values of maximum power and thermoelectric generator efficiency were calculated by the programmable logic controller. When the obtained results were compared with the datasheets, the relative error for the maximum power was around 4% and the value for efficiency was below 3%.

Microprocessors applications in the nuclear industry

International Nuclear Information System (INIS)

Ethridge, C.D.

1980-01-01

Microprocessors in the nuclear industry, particularly at the Los Alamos Scientific Laboratory, have been and are being utilized in a wide variety of applications ranging from data acquisition and control for basic physics research to monitoring special nuclear material in long-term storage. Microprocessor systems have been developed to support weapons diagnostics measurements during underground weapons testing at the Nevada Test Site. Multiple single-component microcomputers are now controlling the measurement and recording of nuclear reactor operating power levels. The CMOS microprocessor data-acquisition instrumentation has operated on balloon flights to monitor power plant emissions. Target chamber mirror-positioning equipment for laser fusion facilities employs microprocessors

OS Friendly Microprocessor Architecture

Science.gov (United States)

2017-04-01

NOTES Patrick La Fratta is now affiliated with Micron Technology, Inc., Boise, Idaho. 14. ABSTRACT We present an introduction to the patented ...Operating System Friendly Microprocessor Architecture (OSFA). The software framework to support the hardware-level security features is currently patent ...Army is assignee. OS Friendly Microprocessor Architecture. United States Patent 9122610. 2015 Sep. 2. Jungwirth P, inventor; US Army is assignee

Programmable logic controller (PLC) for safety systems of nuclear plants

International Nuclear Information System (INIS)

Sen, S.K.; Karmakar, G.; Joseph, Jose; Patil, R.K.

2002-01-01

Full text: A programmable logic controller (PLC) has been developed by RCnD, BARC for use in the safety critical systems in nuclear power plants. This PLC uses qualified hardware developed in RCnD for use in NPP. The programming software conforms to IEC-61131 part 3. The application programming is done on function block diagram (FBD) editor and the FBD is automatically converted into code in high level language (C / C++). This feature makes the application easily decipherable and therefore easily subjected to reviews and other validation techniques. The key to make quality software for use in nuclear systems is to enforce various standards in the design and development of the software, something, which is not possible to do with a commercially available PLC. This PLC with its software completely transparent lends itself to rigorous verification and validation easily

Molecular implementation of simple logic programs.

Science.gov (United States)

Ran, Tom; Kaplan, Shai; Shapiro, Ehud

2009-10-01

Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews.

Science.gov (United States)

Kneale, Dylan; Thomas, James; Harris, Katherine

2015-01-01

Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to 'think' conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions.

Microprocessor-controlled CAMAC data link module

International Nuclear Information System (INIS)

Potter, J.M.

1978-05-01

Communication between the central control computer and remote, satellite data-acquisition/control stations at the Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC-based Data Link modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor. 13 figures

Programmable logic controller optical fibre sensor interface module

Science.gov (United States)

Allwood, Gary; Wild, Graham; Hinckley, Steven

2011-12-01

Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

General purpose programmable accelerator board

Science.gov (United States)

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Mold heating and cooling microprocessor conversion

Science.gov (United States)

Hoffman, D. P.

1995-07-01

Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessor board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.

Microprocessor protection relays: new prospects or new problems?

OpenAIRE

Gurevich, Vladimir

2006-01-01

The internal architecture and principles of operation of microprocessor-based devices including so-called "microprocessor protective relays" have little in common with devices called "electric relays". But microprocessor-based relay protection devices are gradually driving out the traditional electromechanical and even electronic relay protection of virtually from all fields of power and electrical engineering. Advantages of microprocessor-based protection means over traditional ones are far ...

FPGA implementation of bit controller in double-tick architecture

Science.gov (United States)

Kobylecki, Michał; Kania, Dariusz

2017-11-01

This paper presents a comparison of the two original architectures of programmable bit controllers built on FPGAs. Programmable Logic Controllers (which include, among other things programmable bit controllers) built on FPGAs provide a efficient alternative to the controllers based on microprocessors which are expensive and often too slow. The presented and compared methods allow for the efficient implementation of any bit control algorithm written in Ladder Diagram language into the programmable logic system in accordance with IEC61131-3. In both cases, we have compared the effect of the applied architecture on the performance of executing the same bit control program in relation to its own size.

Microprocessor based systems for the higher technician

CERN Document Server

Vears, RE

2013-01-01

Microprocessor Based Systems for the Higher Technician provides coverage of the BTEC level 4 unit in Microprocessor Based Systems (syllabus U80/674). This book is composed of 10 chapters and concentrates on the development of 8-bit microcontrollers specifically constructed around the Z80 microprocessor. The design cycle for the development of such a microprocessor based system and the use of a disk-based development system (MDS) as an aid to design are both described in detail. The book deals with the Control Program Monitor (CP/M) operating system and gives background information on file hand

Microprocessor control of a wind turbine generator

Science.gov (United States)

Gnecco, A. J.; Whitehead, G. T.

1978-01-01

This paper describes a microprocessor based system used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

Tools for developing software for different types of microprocessors, to be used, in particular, for the acquisition and processing of nuclear data

International Nuclear Information System (INIS)

Maloeuvre, Michel.

1982-04-01

It is difficult to imagine the realization of a system with a microprocessor without the use of an adapted development system. As these systems are prohibitively expensive, it is difficult for a laboratory to acquire them. A computer, such as the Multi 20 is provided with programme generating tools and supervisors to put the computer's ressources at the microprocessor's disposal. An electronic crate assures interface functions with the computer, the emulation of the microprocessor and the loading of EROM and the live memory lank in order to execute the different units integrated into the crate, enables the crate to be used as a portable repair and maintenance outfit for the materials installed. In the first part of the text, we present the principles of the development tools showing how they are used to realize microprocessor equipment. In the second part, the software is optimized together with the choice of materials in order to define a low cost development system [fr

System design specification for rotary mode core sample trucks No. 2, 3, and 4 programmable logic controller

International Nuclear Information System (INIS)

Dowell, J.L.; Akers, J.C.

1995-01-01

The system this document describes controls several functions of the Core Sample Truck(s) used to obtain nuclear waste samples from various underground storage tanks at Hanford. The system will monitor the sampling process and provide alarms and other feedback to insure the sampling process is performed within the prescribed operating envelope. The intended audience for this document is anyone associated with rotary or push mode core sampling. This document describes the Alarm and Control logic installed on Rotary Mode Core Sample Trucks (RMCST) number-sign 2, 3, and 4. It is intended to define the particular requirements of the RMCST alarm and control operation (not defined elsewhere) sufficiently for detailed design to implement on a Programmable Logic Controller (PLC)

Logic-programming language enriches design processes

Energy Technology Data Exchange (ETDEWEB)

Kitson, B.; Ow-Wing, K.

1984-03-22

With the emergence of a set of high-level CAD tools for programmable logic devices, designers can translate logic into functional custom devices simply and efficiently. The core of the package is a blockstructured hardware description language called PLPL, for ''programmable-logic programming language.'' The cheif advantage of PLPL lies in its multiple input formats, which permit different design approaches for a variety of design problems. The higher the level of the approach, the closer PLPL will come to directly specifying the desired function. Intermediate steps in the design process can be eliminated, along with the errors that might have been generated during those steps.

Fermilab ACP multi-microprocessor project

International Nuclear Information System (INIS)

Gaines, I.; Areti, H.; Biel, J.; Bracker, S.; Case, G.; Fischler, M.; Husby, D.; Nash, T.

1984-08-01

We report on the status of the Fermilab Advanced Computer Program's project to provide more cost-effective computing engines for the high energy physics community. The project will exploit the cheap, but powerful, commercial microprocessors now available by constructing modular multi-microprocessor systems. A working test bed system as well as plans for the next stages of the project are described

Energy conservation applications of microprocessors

Energy Technology Data Exchange (ETDEWEB)

Shih, James Y.

1979-07-01

A survey of the application of microprocessors for industrial and commercial energy conservation has been made. Microprocessor applications for HVAC, chiller control, and automotive equipment are discussed. A case study of successful replacement of a conventional cooling plant control is recounted. The rapid advancement of microelectronic technology will affect efficient energy control, more sophisticated control methodology, and more investment in controls.

A light-powered sub-threshold microprocessor

Energy Technology Data Exchange (ETDEWEB)

Liu Ming; Chen Hong; Zhang Chun; Li Changmeng; Wang Zhihua, E-mail: lium02@mails.tsinghua.edu.cn [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

2010-11-15

This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode. With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW, dynamic power of 385 nW - 165 kHz, EDP 13 pJ/inst and the operating voltage of 350 mV are achieved. Under a light of about 150 kLux, the microprocessor can run at a rate of up to 500 kHz. The microprocessor can be used for wireless-sensor-network nodes.

Design of microprocessor-based hardware for number theoretic transform implementation

Energy Technology Data Exchange (ETDEWEB)

Anwar Ahmed Shamim

1985-01-01

The Winograd (1976) Fourier Transform algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo m is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (a/d) and a digital to analogue (d/a) converter allows real time digital signal processing.

Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

International Nuclear Information System (INIS)

WHITE, K.A.

2000-01-01

This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309/Rev.1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

MONICA - a programmable microprocessor for track recognition in an e+e- experiment at PETRA

International Nuclear Information System (INIS)

Schildt, P.; Stuckenberg, H.J.; Wermes, N.

1981-01-01

The microprocessor device MONICA is used in the TASSO experiment at PETRA. Its task is to reconstruct events in the cylindrical driftchamber on-line. Used as an event filter MONICA provides a 2 prong trigger without any further requirements. The speed of the processor (event reconstruction times must be in the order of 1 ms) is achieved by a 4 x 4 bit slice processor in ECL technology, content addressable memories and table look up. The track finding efficiency is 80%. (orig.)

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

A study on implementation of dynamic safety system in programmable logic controller for pressurized water reactor

International Nuclear Information System (INIS)

Kim, Ung Soo

1997-02-01

The dynamic safety system (DSS) is a computer based reactor protection system that has dynamic self-testing feature and fail-safe nature inherently. The inherent dynamic self-testing feature and fail-safe design provide a high level of reliability and low spurious trip rate. We can also reduce the time and human efforts to maintain the system by virtue of those features. Therefore, the application of the DSS to PWR has many advantages. The DSS has been applied only to advanced gas-cooled reactor (AGR) in the UK. In order to apply the DSS for PWR, the DSS has to be modified because there exist many differences between PWR and AGR for which the DSS was tested and installed. These differences are trip algorithms, monitored parameters, trip logics, and other conditions. In this study, the DSS algorithm is modified for PWR first. The modified DSS has several new features : 1) The modified DSS tests and processes time-dependent parameters, while the original DSS does not. 2) It has flexibility for handling several types of voting logic but the original DSS handles the only one type of voting - 2 out of 4 coincidence logic. Then, in this study, the modified DSS is implemented in programmable logic controller (PLC) using the ladder logic. Finally, the modified DSS is tested in two ways in this work : 1) The manual test is performed using direct input through the human computer interface (HCI) system. 2) The scenario based test is performed using input from the FISA-2/WS simulator. From the test results, it is shown that the modified DSS operates correctly in all conditions

Use of advanced programmable logic controllers to monitor and control the Elmo Bumpy Torus-proof-of-principle device

International Nuclear Information System (INIS)

Boyd, B.A.

1983-01-01

The Elmo Bumpy Torus - Proof-of-Principle (EBT-P) device is designed with an instrumentation and control system based upon the use of an advanced Programmable Logic Controller (PLC). The modern PLC incorporates many advanced programming features not available in earlier PLC's intended for application to conventional relay logic replacement. The additional power and flexibility of these modern PLC's is especially applicable to an experimental device such as EBT-P which is made up of several complex interrelated subsystems whose operational characteristics will be evolving throughout the lifetime of the device. The rationale for the selection of advanced PLC's for EBT-P and the approach taken to design of the software developed to control EBT-P are the topics addressed in this paper

The microprocessor boom

International Nuclear Information System (INIS)

Anon.

1979-01-01

The applications of microprocessors in high energy physics experiments are discussed. Many benefits are predicted for data acquisition and handling systems and for control and monitoring functions. (W.D.L.).

Greek, Indian and Arabic logic

CERN Document Server

Gabbay, Dov M

2004-01-01

Greek, Indian and Arabic Logic marks the initial appearance of the multi-volume Handbook of the History of Logic. Additional volumes will be published when ready, rather than in strict chronological order. Soon to appear are The Rise of Modern Logic: From Leibniz to Frege. Also in preparation are Logic From Russell to Gödel, Logic and the Modalities in the Twentieth Century, and The Many-Valued and Non-Monotonic Turn in Logic. Further volumes will follow, including Mediaeval and Renaissance Logic and Logic: A History of its Central. In designing the Handbook of the History of Logic, the Editors have taken the view that the history of logic holds more than an antiquarian interest, and that a knowledge of logic's rich and sophisticated development is, in various respects, relevant to the research programmes of the present day. Ancient logic is no exception. The present volume attests to the distant origins of some of modern logic's most important features, such as can be found in the claim by the authors of t...

Microprocessor aided data acquisition at VEDAS

International Nuclear Information System (INIS)

Ziem, P.; Drescher, B.; Kapper, K.; Kowallik, R.

1985-01-01

Three microprocessor systems have been developed to support data acquisition in nuclear physics multiparameter experiments. A bit-slice processor accumulates up to 256 1-dim spectra and 16 2-dim spectra. A microprocessor, based on the AM 29116 ALU, performs a fast consistency check on the coincidence data. A VME-Bus double-processor displays a colored scatterplot

Introduction to fuzzy logic using Matlab

CERN Document Server

Sivanandam, SN; Deepa, S N

2006-01-01

Fuzzy Logic, at present is a hot topic, among academicians as well various programmers. This book is provided to give a broad, in-depth overview of the field of Fuzzy Logic. The basic principles of Fuzzy Logic are discussed in detail with various solved examples. The different approaches and solutions to the problems given in the book are well balanced and pertinent to the Fuzzy Logic research projects. The applications of Fuzzy Logic are also dealt to make the readers understand the concept of Fuzzy Logic. The solutions to the problems are programmed using MATLAB 6.0 and the simulated results are given. The MATLAB Fuzzy Logic toolbox is provided for easy reference.

Programmable synchronous communications module

International Nuclear Information System (INIS)

Horelick, D.

1979-10-01

The functional characteristics of a programmable, synchronous serial communications CAMAC module with buffering in block format are described. Both bit and byte oriented protocols can be handled in full duplex depending on the program implemented. The main elements of the module are a Signetics 2652 Multi-Protocol Communications Controller, a Zilog Z-808 8 bit microprocessor with PROM and RAM, and FIFOs for buffering

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

Science.gov (United States)

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Microprocessorized NMR measurement

International Nuclear Information System (INIS)

Rijllart, A.

1984-01-01

An MC68000 CAMAC microprocessor system for fast and accurate NMR signal measurement will be presented. A stand-alone CAMAC microprocessor system (MC68000 STAC) with a special purpose interface sweeps a digital frequency synthesizer and digitizes the NMR signal with a 16-bit ADC of 17 μs conversion time. It averages the NMR signal data over many sweeps and then transfers it through CAMAC to a computer for calculation of the signal parameters. The computer has full software control over the timing and sweep settings of this signal averager, and thus allows optimization of noise suppression. Several of these processor systems can be installed in the same crate for parallel processing, and the flexibility of the STAC also allows easy adaptation to other applications such as transient recording or phase-sensitive detection. (orig.)

Design of digital logic control for accelerator magnet power supply

International Nuclear Information System (INIS)

Long Fengli; Hu Wei; Cheng Jian

2008-01-01

For the accelerator magnet power supply, usually the Programmable Logic Controller (PLC) is used to server as the controller for logic protection and control. Along with the development of modern accelerator technology, it is a trend to use fully-digital control to the magnet power supply. It is possible to integrate the logic control part into the digital control component of the power supply, for example, the Field Programmable Gate Array (FPGA). The paper introduces to different methods which are designed for the logic protection and control for accelerator magnet power supplies with the FPGA as the control component. (authors)

Multi-core Microprocessors

Indian Academy of Sciences (India)

Based on empirical data, Gordon Moore .... there are numerous models of the same Intel microprocessor such as Pentium. 3). ... returns. The limit on instruction and thread-level processing coupled with ..... This style of parallel programming is.

Автоматизация процесса перевозок путем применения микропроцессорного электропривода и программируемого логического контроллера

OpenAIRE

Буряковский, Сергей Геннадьевич; Кольчик, Дмитрий Сергеевич; Смирнов, Василий Васильевич; Рафальский, Александр Александрович

2013-01-01

The article shows one of the possible ways to automate and optimize the turnouts for both railway mainline and industrial railway. The work is based on the application of the results of earlier researches and their implementation by means of a microprocessor electrical drive and a programmable logic controller.

Microprocessor Protection of Power Reducing Transformers

OpenAIRE

F. A. Romanuk; S. P. Korolev; M. S. Loman

2011-01-01

The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

''NICRO'' microprogramming language for sectional microprocessors

International Nuclear Information System (INIS)

Semenov, Yu.A.; Chudakov, V.N.

1982-01-01

''MICRO'' microprogramming input language developed for sectional microprocessors is described. The structure of micromanual, purpose of particular fields, the corresponding mne-- mocodes and requirements they have to meet are considered. Program for integer division with a sign written in the ''MICRO'' language is given as an example. The possibilities of modif ying the translator for its adaptation to different types of processor and microprocessor sets are analyzed

Microprocessors in detectors and analysis

International Nuclear Information System (INIS)

Siskind, E.J.

1982-01-01

The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led to the examination of the use of microprocessors in various aspects of HEP computing. A brief (and admittedly somewhat biased) review is given of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

Microprocessors in detectors and analysis

International Nuclear Information System (INIS)

Siskind, E.J.

1982-01-01

The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led us to examine the use of microprocessors in various aspects of HEP computing. The following article is a brief (and admittedly somewhat biased) review of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

Microprocessor Protection of Power Reducing Transformers

Directory of Open Access Journals (Sweden)

F. A. Romanuk

2011-01-01

Full Text Available The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

Microprocessor controller for phasing the accelerator

International Nuclear Information System (INIS)

Howry, S.K.; Wilmunder, A.R.

1977-03-01

A microprocessor controller is being developed to perform automatic phasing of the SLAC accelerator. It will replace the existing relay/analog boxes which are ten years old. The new system is all solid state except for the stepping motors that drive the phase shifters. A description is given of the components of the system, the control algorithm, microprocessor hardware and software design and development, and interaction with SLAC's computer control system

Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

CERN Document Server

Simpson, Robert J

1987-01-01

Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

Process control by microprocessors

Energy Technology Data Exchange (ETDEWEB)

Arndt, W [ed.

1978-12-01

Papers from the workshop Process Control by Microprocessors being organized by the Karlsruhe Nuclear Research Center, Project PDV, together with the VDI/VDE-Gesellschaft fuer Mess- und Regelungstechnik are presented. The workshop was held on December 13 and 14, 1978 at the facilities of the Nuclear Research Center. The papers are arranged according to the topics of the workshop; one chapter deals with today's state of the art of microprocessor hardware and software technology; 5 chapters are dedicated to applications. The report also contains papers which will not be presented at the workshop. Both the workshop and the report are expected to improve and distribute the know-how about this modern technology.

Microprocessor Controlled Maximum Power Point Tracker for Photovoltaic Application

International Nuclear Information System (INIS)

Jiya, J. D.; Tahirou, G.

2002-01-01

This paper presents a microprocessor controlled maximum power point tracker for photovoltaic module. Input current and voltage are measured and multiplied within the microprocessor, which contains an algorithm to seek the maximum power point. The duly cycle of the DC-DC converter, at which the maximum power occurs is obtained, noted and adjusted. The microprocessor constantly seeks for improvement of obtained power by varying the duty cycle

CAMAC based computer--computer communications via microprocessor data links

International Nuclear Information System (INIS)

Potter, J.M.; Machen, D.R.; Naivar, F.J.; Elkins, E.P.; Simmonds, D.D.

1976-01-01

Communications between the central control computer and remote, satellite data acquisition/control stations at The Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC based Data Link Modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor

SNOOP module CAMAC interface to the 168/E microprocessor

International Nuclear Information System (INIS)

Bernstein, D.; Carroll, J.T.; Mitnick, V.H.; Paffrath, L.; Parker, D.B.

1979-10-01

A pair of 168/E microprocessors will be used to meet the realtime computing requirements of the SLAC Hybrid Facility. A SNOOP module and 168/E Interface provide the link between the host computer and the microprocessors. By eavesdropping on normal CAMAC read operations, the SNOOP provides a direct data transfer from CAMAC to microprocessor memory. The host computer controls the processors using standard CAMAC programmed I/O to the SNOOP

The Computer in a Programmable Implantable Medication System (PIMS)

OpenAIRE

Sanders, K. H.; Radford, W. E.

1982-01-01

The Programmable Implantable Medication System (PIMS) developed at APL can be used in the treatment of diabetes, reproductive hormone dysfunction, hypertension, cancer, chronic pain, thrombosis, and the delivery of growth hormone. The Implantable Programmable Infusion Pump (IPIP) is the implanted element of PIMS. Under control of a microprocessor, the IPIP administers medication and stores data pertaining to its operation. An external unit can read out the stored data, as well as program the ...

Radiation hardened COTS-based 32-bit microprocessor

International Nuclear Information System (INIS)

Haddad, N.; Brown, R.; Cronauer, T.; Phan, H.

1999-01-01

A high performance radiation hardened 32-bit RISC microprocessor based upon a commercial single chip CPU has been developed. This paper presents the features of radiation hardened microprocessor, the methods used to radiation harden this device, the results of radiation testing, and shows that the RAD6000 is well-suited for the vast majority of space applications. (authors)

PID Neural Network Based Speed Control of Asynchronous Motor Using Programmable Logic Controller

Directory of Open Access Journals (Sweden)

MARABA, V. A.

2011-11-01

Full Text Available This paper deals with the structure and characteristics of PID Neural Network controller for single input and single output systems. PID Neural Network is a new kind of controller that includes the advantages of artificial neural networks and classic PID controller. Functioning of this controller is based on the update of controller parameters according to the value extracted from system output pursuant to the rules of back propagation algorithm used in artificial neural networks. Parameters obtained from the application of PID Neural Network training algorithm on the speed model of the asynchronous motor exhibiting second order linear behavior were used in the real time speed control of the motor. Programmable logic controller (PLC was used as real time controller. The real time control results show that reference speed successfully maintained under various load conditions.

Nuclear Instrumentation Module (NIM) standard logic processor as a portal signal analyzer

International Nuclear Information System (INIS)

Minges, G.P.

1978-01-01

A general purpose electronic logic processor has been designed into a 2 wide NIM (Nuclear Instrumentation Module) bin module. The unit utilizes a microprocessor to achieve necessary versatility. The processor's first use is as a new generation signal analyzer for use in radiometric personnel and vehicle portal monitors. Significant improvements have been obtained in sensitivity and stability over existing analog discriminators. The new analyzer is presently being used to update personnel and vehicle portal monitoring systems

Automated mixed traffic transit vehicle microprocessor controller

Science.gov (United States)

Marks, R. A.; Cassell, P.; Johnston, A. R.

1981-01-01

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

Microprocessor tester for the treat upgrade reactor trip system

International Nuclear Information System (INIS)

Lenkszus, F.R.; Bucher, R.G.

1984-01-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations

Microprocessor-controlled scanning densitometer system

International Nuclear Information System (INIS)

Shurtliff, R.W.

1980-04-01

An Automated Scanning Densitometer System has been developed by uniting a microprocessor with a low energy x-ray densitometer system. The microprocessor controls the detector movement, provides self-calibration, compensates raw readings to provide time-linear output, controls both data storage and the host computer interface, and provides measurement output in engineering units for immediate reading. The densitometer, when used in a scanning mode, is a precision reference instrument that provides chordal average density measurements over the cross section of a pipe under steady-state flow conditions. Results have shown an improvement over the original densitometer in reliability and repeatability of the system, an a factor-of-five improvement in accuracy

Experience with the use of programmable logic controllers in nuclear safety applications. Final report

International Nuclear Information System (INIS)

Brown, E.M.; Stofko, M.J.

1995-03-01

This report describes the implementation and experience with Programmable Logic Controllers (PLC) for nuclear safety applications. Two applications are described. The first is an Anticipated Transient Without Scram (ATWS) mitigation system provided as a Diverse Auxiliary Feedwater Actuation System (DAFAS). It was implemented at Arizona Public Service's Palo Verde Nuclear Generating Station and has been in commercial operation since early 1992. The second system described is an Emergency Diesel Generator Bus Load Sequencer installed at Florida Power and Light's Turkey Point Nuclear Power Plant. This system was installed as part of an upgrade to the emergency power system in 1988. The experience gained in the design, development, implementation and qualification of these systems will be beneficial to utilities that are considering the utilization of PLCs for their plant applications

The engineering of microprocessor systems guidelines on system development

CERN Document Server

1979-01-01

The Engineering of Microprocessor Systems: Guidelines on System Development provides economical and technical guidance for use when incorporating microprocessors in products or production processes and assesses the alternatives that are available. This volume is part of Project 0251 undertaken by The Electrical Research Association, which aims to give managers and development engineers advice and comment on the development process and the hardware and software needed to support the engineering of microprocessor systems. The results of Phase 1 of the five-phase project are contained in this fir

Logicism, intuitionism, and formalism

CERN Document Server

Symons, John

2008-01-01

Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

International Nuclear Information System (INIS)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.; Johnson, M.T.

1991-01-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one of the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N 2 gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm 2 /mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm 2 /mg (283 MeV Cu at 0 degrees) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive

MANUAL LOGIC CONTROLLER (MLC)

OpenAIRE

Claude Ziad Bayeh

2015-01-01

The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...

Software support for Motorola 68000 microprocessor at CERN. CERN convention for programming the MC68000 family

International Nuclear Information System (INIS)

Cailliau, R.; Carpenter, B.

1984-01-01

The CERN convention for programming the MC68000 family of microprocessors gives a set of rules describing the layout of the memory and stack frames used by routines as they should appear before and after their calling sequences. It does not deal with the instructions used to achieve these states. The aim of the convention is to allow programming language mixing as well as debugging of programs built from units written in different languages. It is to be followed by programmers and programming-language compilers. (orig.)

Microprocessor monitored Auger spectrometer

International Nuclear Information System (INIS)

Sapin, Michel; Ghaleb, Dominique; Pernot, Bernard.

1982-05-01

The operation of an Auger spectrometer, used for studying surface impurity diffusion, has been fully automatized with the help of a microprocessor. The characteristics, performance and practical use of the system are described together with the main advantage for the experimentator [fr

Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

Energy Technology Data Exchange (ETDEWEB)

Zhang, X.; Wan, C.H., E-mail: wancaihua@iphy.ac.cn; Yuan, Z.H.; Fang, C.; Kong, W.J.; Wu, H.; Zhang, Q.T.; Tao, B.S.; Han, X.F., E-mail: xfhan@iphy.ac.cn

2017-04-15

Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices. - Highlights: • Experimental demonstration of spin logic cell based on spin Hall effect. • Five logic functions are realized in a single logic cell. • The logic cell is reprogrammable. • Information in the cell is symmetry-protected. • The logic cell can be easily expanded to logic gate array.

Introduction to embedded system design using field programmable gate arrays

CERN Document Server

Dubey, Rahul

2009-01-01

Offers information on the use of field programmable gate arrays (FPGAs) in the design of embedded systems. This text considers a hypothetical robot controller as an embedded application and weaves around it related concepts of FPGA-based digital design. It is suitable for both students and designers who have worked with microprocessors.

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

Directory of Open Access Journals (Sweden)

Jakub Dolata

2018-06-01

Full Text Available MicroRNAs are small molecules (∼21 nucleotides long that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1, the zinc finger protein Serrate (SE, and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1. Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2 and phosphatases (CPL1 and PP4. Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3 that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

Application of microprocessors to radiation protection measurements

International Nuclear Information System (INIS)

Zappe, D.; Meldes, C.

1982-01-01

In radiation protection measurements signals from radiation detectors or dosemeters have to be transformed into quantities relevant to radiation protection. In most cases this can only be done by taking into account various parameters (e.g. the quality factor). Moreover, the characteristics of the statistical laws of nuclear radiation emission have to be considered. These problems can properly be solved by microprocessors. After reviewing the main properties of microprocessors, some typical examples of applying them to problems of radiation protection measurement are given. (author)

CFD-simulation of radiator for air cooling of microprocessors in a limitided space

OpenAIRE

Trofimov V. E.; Pavlov A. L.; Mokrousova E. A.

2016-01-01

One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal c...

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Microprocessors in automatic chemical analysis

International Nuclear Information System (INIS)

Goujon de Beauvivier, M.; Perez, J.-J.

1979-01-01

Application of microprocessors to programming and computing of solutions chemical analysis by a sequential technique is examined. Safety, performances reliability are compared to other methods. An example is given on uranium titration by spectrophotometry [fr

The application of computer logic design in the trigger system

International Nuclear Information System (INIS)

Zhao Dixin; Ding Huiliang; Gu Jianhui

1996-01-01

The programmable logic devices PLD and FPGA, which are developing steadily recently, can be configured by user. Designers define the logic functions of the circuit and revise these functions when necessary. The application of these devices in the trigger system and development system is introduced

Evaluation of the performance of microprocessor-based colorimeter

OpenAIRE

Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood ...

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

Science.gov (United States)

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Control Systems of Rubber Dryer Machinery Components Using Programmable Logic Control (PLC)

Science.gov (United States)

Hendra; Yulianto, A. S.; Indriani, A.; Hernadewita; Hermiyetti

2018-02-01

Application of programmable logic control (PLC) is widely used on the control systems in the many field engineering such as automotive, aviation, food processing and other industries [1-2]. PLC is simply program to control many automatic activity, easy to use, flexible and others. PLC using the ladder program to solve and regulated the control system component. In previous research, PLC was used for control system of rotary dryer machine. In this paper PLC are used for control system of motion component in the rubber dryer machinery. Component of rubber dryer machine is motors, gearbox, sprocket, heater, drying chamber and bearing. Principle working of rubber dryer machinery is wet rubber moving into the drying chamber by sprocket. Sprocket is driven by motors that conducted by PLC to moving and set of wet rubber on the drying chamber. Drying system uses greenhouse effect by making hanger dryer design in the form of line path. In this paper focused on motion control system motors and sensors drying rubber using PLC. The results show that control system of rubber dryer machinery can work in accordance control input and the time required to dry the rubber.

A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

Directory of Open Access Journals (Sweden)

Diego González

2012-09-01

Full Text Available This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA and NIOS II microprocessor applying a C to Hardware (C2H acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

A microprocessor based picture analysis system for automatic track measurements

International Nuclear Information System (INIS)

Heinrich, W.; Trakowski, W.; Beer, J.; Schucht, R.

1982-01-01

In the last few years picture analysis became a powerful technique for measurements of nuclear tracks in plastic detectors. For this purpose rather expensive commercial systems are available. Two inexpensive microprocessor based systems with different resolution were developed. The video pictures of particles seen through a microscope are digitized in real time and the picture analysis is done by software. The microscopes are equipped with stages driven by stepping motors, which are controlled by separate microprocessors. A PDP 11/03 supervises the operation of all microprocessors and stores the measured data on its mass storage devices. (author)

General-purpose microprocessor-based control chassis

International Nuclear Information System (INIS)

Halbig, J.K.; Klosterbuer, S.F.; Swenson, D.A.

1979-12-01

The objective of the Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory is to develop the technology to build smaller, less expensive, and more reliable proton linear accelerators for medical applications. For this program, a powerful, simple, inexpensive, and reliable control and data acquisition system was developed. The system has a NOVA 3D computer with a real time disk-operating system (RDOS) that communicates with distributed microprocessor-based controllers which directly control data input/output chassis. At the heart of the controller is a microprocessor crate which was conceived at the Fermi National Accelerator Laboratory. This idea was applied to the design of the hardware and software of the controller

Dynamic instruction set extension of microprocessors with embedded FPGAs

OpenAIRE

Bauer, Heiner

2017-01-01

Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, how...

Simultaneous G-Quadruplex DNA Logic.

Science.gov (United States)

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Microprocessor based techniques at CESR

International Nuclear Information System (INIS)

Giannini, G.; Cornell Univ., Ithaca, NY

1981-01-01

Microprocessor based systems succesfully used in connection with the High Energy Physics experimental program at the Cornell Electron Storage Ring are described. The multiprocessor calibration system for the CUSB calorimeter is analyzed in view of present and future applications. (orig.)

Small private key MQPKS on an embedded microprocessor.

Science.gov (United States)

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

Small Private Key PKS on an Embedded Microprocessor

Science.gov (United States)

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

Fault-tolerance techniques for SRAM-based FPGAs

CERN Document Server

Kastensmidt, Fernanda Lima; Reis, Ricardo

2006-01-01

Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or highly-reliable applications engineers. Today, designers of many next-generation products must cope with reduced margin noises. The continuous evolution of fabrication technology of semiconductor components – shrinking transistor geometry, power supply, speed, and logic density – has significantly reduced the reliability of very deep submicron integrated circuits, in face of various internal and external sources of noise. Field Programmable Gate Arrays (FPGAs), customizable by SRAM cells, are the latest advance in the integrated circuit evolution: millions of memory cells to implement the logic, embedded memories, routing, and embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with current requirements.

Technologies for faults diagnosis of FPGA logic blocks

Directory of Open Access Journals (Sweden)

C. U. Ngene

2012-08-01

Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

step by step process from logic model to case study method as an ...

African Journals Online (AJOL)

Global Journal

Logic models and case study approach to programme evaluation have proven ... in qualitative methodology. There is ... Note: IEHPs= internationally educated health professionals, ... interviews with the programme managers. .... programme assessed to ensure that the IEHPs are ready to face the certification ..... Comparison.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Science.gov (United States)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

"Modeling" Youth Work: Logic Models, Neoliberalism, and Community Praxis

Science.gov (United States)

Carpenter, Sara

2016-01-01

This paper examines the use of logic models in the development of community initiatives within the AmeriCorps program. AmeriCorps is the civilian national service programme in the U.S., operating as a grants programme to local governments and not-for-profit organisations and providing low-cost labour to address pressing issues of social…

Small Private Key MQPKS on an Embedded Microprocessor

Directory of Open Access Journals (Sweden)

Hwajeong Seo

2014-03-01

Full Text Available Multivariate quadratic (MQ cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011, a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

Microprocessor-based data acquisition systems for Hera experiments

International Nuclear Information System (INIS)

Haynes, W.J.

1989-09-01

Sophisticated multi-microprocessor configurations are envisaged to cope with the technical challenges of the HERA electron-proton collider and the high data rates from the two large experiments H1 and ZEUS. These lecture notes concentrate on many of the techniques employed, with much emphasis being placed on the use of the IEEE standard VMEbus as a unifying element. The role of modern 32-bit CISC and RISC microprocessors, in the handling of data and the filtering of physics information, is highlighted together with the integration of personal computer stations for monitoring and control. (author)

Evaluation of the performance of microprocessor-based colorimeter.

Science.gov (United States)

Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

Science.gov (United States)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

CFD-simulation of radiator for air cooling of microprocessors in a limitided space

Directory of Open Access Journals (Sweden)

Trofimov V. E.

2016-12-01

Full Text Available One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal contact with the microprocessor housing designed for cooler installation. On the hot surface of the module a radiator is mounted. The radiator dissipates the cumulative heat flow from both the microprocessor and the module. High density PCB layout, the requirement of free access to the jumpers and interfaces, and the presence of numerous sensors limit the space for radiator mounting and require the use of an extremely compact radiator, especially in air cooling conditions. One of the possible solutions for this problem may reduce the area of the radiator heat-transfer surfaces due to a sharp growth of the heat transfer coefficient without increasing the air flow rate. To ensure a sharp growth of heat transfer coefficient on the heat-transfer surface one should make in the surface one or more dead-end cavities into which the impact air jets would flow. CFD simulation of this type of radiator has been conducted. The heat-aerodynamic characteristics and design recommendations for removing heat from microprocessors in a limited space have been determined.

Microprocessor-controlled surface testing

Energy Technology Data Exchange (ETDEWEB)

Droscha, H

1982-09-01

For the quality inspection on continuous flow material webs with transverse scanning laser beam, the microprocessor control, realized now for the first time in combination with appropriate units, shows a considerable progress. Thanks to the here used electronics, surface errors can be localized within the web according to their x-y-position, quantitative analysis can be carried out and automatic sorting and registration functions can be used.

Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

Directory of Open Access Journals (Sweden)

Salah Bouzina

2016-12-01

Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

Programmable lighting control: do-it-yourself energy savings

Energy Technology Data Exchange (ETDEWEB)

1982-04-01

At C-E Power Systems, an operating group of Combustion Engineering, Inc., Windsor, CT, the lighting and HVAC in six of 24 buildings are now under microprocessor control, and the necessary equipment to convert two additional buildings before the year end has been ordered. The initial analysis of the economic benefits of a /100,000 investment for the first six buildings showed the system will pay for itself in electricity savings in 30 months or less. In the programmable lighting system, a microprocessor-based central controller is /left double quote/softwired/right double quote/ to a single-chip microcomputer-based local transceiver. The data line provides a high integrity communications channel carrying multiplex commands from the central controllers as well as status and switch override message from the remote transceivers. The controller has the capacity to direct as many as 500 transceivers controlling 8,000 relays.

G-cueing microcontroller (a microprocessor application in simulators)

Science.gov (United States)

Horattas, C. G.

1980-01-01

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Mechatronics: Skilled Industrial Job Training

OpenAIRE

Bill Jones

2013-01-01

Currently, skills required for these jobs are available through many avenues, but we have centered our efforts on a program called mechatronics. Mechatronics combines the industrial fields of electronics, fluid power (hydraulic and pneumatic), mechanics, and computer processing (programmable logic controller, or PLC, and microprocessors). Businesses, community resources, legislators, and educators are beginning to work together in Tennessee and in Rutherford County to develop pathways for K-1...

Progress in control equipment for fuel-handling machinery

International Nuclear Information System (INIS)

Nutting, B.A.

1986-01-01

The paper outlines the development of the equipment used to control the fuel-handling machinery associated with nuclear reactors, from the early electromechanical equipment, through solid-state switching logic to programmable controllers and microprocessors. The control techniques have developed along with the technology, and modern systems offer versatility, reliability and ease of design, operation and maintenance. Future trends and developments are discussed together with possible limiting factors. (author)

Cybersecurity Framework for Ship Industrial Control System

OpenAIRE

Maule, R. William; Hake, Joseph

2016-01-01

Ship mechanical and electrical control systems, and the communications grid through which these devices operate, are a high priority concern for Navy leadership. Ship systems use microprocessor-based controls to interface with physical objects, and Programmable Logic Controllers (PLCs) to automate ship electromechanical processes. Ship operations are completely dependent on these devices. The commercial security products upon which ships depend do not work on ICS, leaving ships vulnerable. Th...

Fermilab advanced computer program multi-microprocessor project

International Nuclear Information System (INIS)

Nash, T.; Areti, H.; Biel, J.

1985-06-01

Fermilab's Advanced Computer Program is constructing a powerful 128 node multi-microprocessor system for data analysis in high-energy physics. The system will use commercial 32-bit microprocessors programmed in Fortran-77. Extensive software supports easy migration of user applications from a uniprocessor environment to the multiprocessor and provides sophisticated program development, debugging, and error handling and recovery tools. This system is designed to be readily copied, providing computing cost effectiveness of below $2200 per VAX 11/780 equivalent. The low cost, commercial availability, compatibility with off-line analysis programs, and high data bandwidths (up to 160 MByte/sec) make the system an ideal choice for applications to on-line triggers as well as an offline data processor

CAMAC modular programmable function generator

Energy Technology Data Exchange (ETDEWEB)

Turner, G.W.; Suehiro, S.; Hendricks, R.W.

1980-12-01

A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

CAMAC modular programmable function generator

International Nuclear Information System (INIS)

Turner, G.W.; Suehiro, S.; Hendricks, R.W.

1980-12-01

A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve

The Ganil computer control system renewal

International Nuclear Information System (INIS)

David, L.; Lecorche, E.; Luong, T.T.; Ulrich, M.

1990-01-01

Since 1982 the GANIL heavy ion accelerator has been under the control of 16-bit minicomputers MITRA, programmable logic controllers and microprocessorized Camac controllers, structured into a partially centralized system. This control system has to be renewed to meet the increasing demands of the accelerator operation which aims to provide higher quality ion beams under more reliable conditions. This paper gives a brief description of the existing control system and then discusses the main issues of the design and the implementation of the future control system: distributed powerful processors federated through Ethernet and flexible network-wide database access, VME standard and front-end microprocessors, enhanced color graphic tools and workstation based operator interface

Cross software for microprocessor program development at CERN

International Nuclear Information System (INIS)

Eicken, H. von; Montuelle, J.; Willers, I.; Blake, J.

1981-01-01

Programs for a variety of microprocessors (including Intel 8080; Motorola 6800 and 6809 and 68000; and Texas Instruments 9900) can be prepared on different host computers (such as IBM 370, CDC 6000, and Nord 10) using portable programs developed at CERN. The range of cross software consists of: an assembler for each target microprocessor, a single linkage editor, a single object module librarian, and a variety of pre-loaders which convert object modules from CERN's format (CUFOM) into manufacturers' formats. The programs are written in BCPL and PASCAL, programming languages which are available on a wide range of computers. (orig.)

Microprocessor system to recover data from a self-scanning photodiode array

International Nuclear Information System (INIS)

Koppel, L.N.; Gadd, T.J.

1975-01-01

A microprocessor system developed at Lawrence Livermore Laboratory has expedited the recovery of data describing the low energy x-ray spectra radiated by laser-fusion targets. An Intel microprocessor controls the digitization and scanning of the data stream of an x-ray-sensitive self-scanning photodiode array incorporated in a crystal diffraction spectrometer

Reliability analysis of diverse safety logic systems of fast breeder reactor

International Nuclear Information System (INIS)

Ravi Kumar, Bh.; Apte, P.R.; Srivani, L.; Ilango Sambasivan, S.; Swaminathan, P.

2006-01-01

Safety Logic for Fast Breeder Reactor (FBR) is designed to initiate safety action against Design Basis Events. Based on the outputs of various processing circuits, Safety logic system drives the control rods of the shutdown system. So, Safety Logic system is classified as safety critical system. Therefore, reliability analysis has to be performed. This paper discusses the Reliability analysis of Diverse Safety logic systems of FBRs. For this literature survey on safety critical systems, system reliability approach and standards to be followed like IEC-61508 are discussed in detail. For Programmable Logic device based systems, Hardware Description Languages (HDL) are used. So this paper also discusses the Verification and Validation for HDLs. Finally a case study for the Reliability analysis of Safety logic is discussed. (author)

MicroShell Minimalist Shell for Xilinx Microprocessors

Science.gov (United States)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is

PENGEMBANGAN PERANGKAT PEMBELAJARAN MEKATRONIKA BERBASIS KOMPUTER POKOK BAHASAN PROGRAMMABLE LOGIC CONTROLLER BERORIENTASI PADA PEMBELAJARAN LANGSUNG

Directory of Open Access Journals (Sweden)

Wahyu Dwi Kurniawan

2015-02-01

Program Logic Controller is subject that many complaints by students of Department of Mechanical Engineering FT-Unesa. This is due to the lack of learning devices are used so that learning becomes less favorable and become passive. This study aims to develop computer-based learning device mechatronics subject-oriented programmable logic controller directly on student learning Mechanical Engineering Department Unesa FT. This study was conducted in two phases. Phase I, the development of the learning refers to the design of the Model 4D Thiagarajan (1974, Phase II, trial learning in the classroom using a design of one group pretest-posttest design. The findings of the study: (1 an average score of 3.32 learning assessment tools (pretty good, (2 average scores on tests of learning implementation I of 3.59 (good and trials II of 3.70 (both , (3 student learning outcomes of cognitive and psychomotor aspects have achieved individually and classical mastery, (4 students showed a positive response to the stated learning tehadap interested, excited, and motivated to attend lectures mechatronics; activity of the most dominant college students are discussin /practices relevant to teaching and learning that is on trial I is 36.46% and trials II 38.19%. Based on the analysis of data, it can be concluded that the developed learning feasible for use in lectures mechatronics. Implementation of the computer-based learning mechatronics subjects PLC can improve the quality of teaching and learning, as students showed a positive response, implementation category learning and learning outcomes both cognitive and psychomotor aspects of students have achieved mastery individually and classical. Keywords: development, learning, mechatronics, computer, plc

Single event effect testing of the Intel 80386 family and the 80486 microprocessor

International Nuclear Information System (INIS)

Moran, A.; LaBel, K.; Gates, M.; Seidleck, C.; McGraw, R.; Broida, M.; Firer, J.; Sprehn, S.

1996-01-01

The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored

The European Logarithmic Microprocessor

Czech Academy of Sciences Publication Activity Database

Coleman, J. N.; Softley, C. I.; Kadlec, Jiří; Matoušek, R.; Tichý, Milan; Pohl, Zdeněk; Heřmánek, Antonín; Benschop, N. F.

2008-01-01

Roč. 57, č. 4 (2008), s. 532-546 ISSN 0018-9340 Grant - others:Evropská komise(BE) ESPRIT 33544 Institutional research plan: CEZ:AV0Z10750506 Source of funding: R - rámcový projekt EK Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic Subject RIV: JC - Computer Hardware ; Software Impact factor: 2.611, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf

A microprocessor based area monitor system for neutron and gamma radiation

International Nuclear Information System (INIS)

Wilhelm, R.; Heusser, G.

1980-01-01

The conventional electronics of the area monitors at the MPI-Heidelberg accelerators have been replaced by a microprocessor system consisting of individual detector-microprocessors and a central microcomputer. The detector microprocessors convert the count rates of BF3 and GM counter tubes into dose rates and control three different radiation thresholds (failure, low and high level). Different warning signals are operated directly by the detector processors, whereas the dose rates are transferred to the central microcomputer. Here the data are processed for recording on tape and displaying on TV monitors. The detector as well as the central processors have been developed on the basis of a 16-bit microprocessor. In the control rooms the dose rates of the individual monitors are displayed and on an indicator board showing the different locations, the high radiation level and the state of the doors (open, locked, and closed, locked but open) are sianaled by different LED. If a high radiation threshold is surpassed, the doors adjacent to that area can be locked either by switches on the indicator board or automatically. Within the experimental area, the low and high radiation level is indicated by acoustic and light signals. The whole concept permits keeping the absorbed doses of the personnel as low as possible without affecting the flexibility of the experimental operations. The independence of the microprocessor driven area monitors guarantees a high reliability. Compared to conventional electronics the advantages of the system are its reliability and cost. (Author)

Integration in a nuclear physics experiment of a visualization unit managed by a microprocessor

International Nuclear Information System (INIS)

Lefebvre, M.

1976-01-01

A microprocessor (Intel 8080) is introduced in the equipment controlling the (e,e'p) experiment that will take place at the linear accelerator operating in the premises of CEA (Orme des Merisiers, Gif-sur-Yvette, France). The purpose of the microprocessor is to handle the visualization tasks that are necessary to have a continuous control of the experiment. By doing so more time and more memory will be left for data processing by the calculator unit. In a forward version of the system, the controlling of the level of helium in the target might also be in charge of the microprocessor. This work is divided into 7 main parts: 1) a presentation of the linear accelerator and its experimental facilities, 2) the Intel 8080 micro-processor and its programming, 3) the implementation of the micro-processor in the electronic system, 4) the management of the memory, 5) data acquisition, 6) the keyboard, and 7) the visualization unit [fr

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Auxiliary/Master microprocessor CAMAC Crate Controller applications

International Nuclear Information System (INIS)

Barsotti, E.

1975-01-01

The need for further sophistication of an already complex serial CAMAC control system at Fermilab led to the development of an Auxilary/Master CAMAC Crate Controller. The controller contains a Motorola 6800 microprocessor, 2K bytes of RAM, and 8K bytes of PROM memory. Bussed dataway lines are time shared with CAMAC signals to provide memory expansion and direct addressing of peripheral devices without the need of external cabling. The Auxiliary/Master Crate Controller (A/MCC) can function as either a Master, i.e., stand alone, crate controller or as an Auxiliary controller to Fermilab's Serial Crate Controller (SCC). Two modules, one single- and one double-width, make up an A/MCC. The microprocessor has one nonmaskable and one maskable vectored interrupt. Time sharing the dataway between SCC programmed and block transfer generated dataway cycles and A/MCC operations still allows a 99 percent microprocessor CPU busy time. Since the conception of the A/MCC, there has been an increasing number of control system-related projects proposed which would not have been possible or would have been very difficult to implement without such a device. The first such application now in use at Fermilab is a stand-alone control system for a mass spectrometer experiment in the Main Ring Internal Target Area. This application in addition to other proposed A/MCC applications, both stand-alone and auxiliary, is discussed

Multi Channels PWM Controller for Thermoelectric Cooler Using a Programmable Logic Device and Lab-Windows CVI

Directory of Open Access Journals (Sweden)

Eli FLAXER

2008-09-01

Full Text Available We present a complete design of a multi channels PID controller for Thermoelectric Cooler (TEC using a pulse width modulation (PWM technique implemented by a dedicated programmable logic device (PLD programmed by VHDL. The PID control loop is implemented by software written by National Instrument Lab-Windows CVI. Due to the fact that the implementation is by a VHDL and PLD the design is modular, as a result, the circuit is very compact in size and very low cost as compared to any commercial product. In addition, since the control loop is implemented by software running on a personal computer (PC using a C language, it is easy to adjust the controller to various environmental conditions and for a width range of sensors like: a thermo couple (TC, thermistor, resistance temperature detectors (RTD etc. We demonstrate the performance of this circuit as a controller for a small incubator using thermistor as the temperature sensor.

A realtime feedback microprocessor for the TEVATRON

International Nuclear Information System (INIS)

Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

1993-01-01

A feedback microprocessor has been built for the TEVATRON. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor includes a finite state machine. Each state corresponds to a specific TEVATRON operation. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime correction. The authors also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. This talk will describe use of this device to control the TEVATRON tunes and discuss other uses

Multiple microprocessor based nuclear reactor power monitor

International Nuclear Information System (INIS)

Lewis, P.S.; Ethridge, C.D.

1979-01-01

The reactor power monitor is a portable multiple-microprocessor controlled data acquisition device being built for the International Atomic Energy Association. Its function is to measure and record the hourly integrated operating thermal power level of a nuclear reactor for the purpose of detecting unannounced plutonium production. The monitor consists of a 3 He proportional neutron detector, a write-only cassette tape drive and control electronics based on two INTEL 8748 microprocessors. The reactor power monitor operates from house power supplied by the plant operator, but has eight hours of battery backup to cover power interruptions. Both the hourly power levels and any line power interruptions are recorded on tape and in memory. Intermediate dumps from the memory to a data terminal or strip chart recorder can be performed without interrupting data collection

Software tools for microprocessor based systems

International Nuclear Information System (INIS)

Halatsis, C.

1981-01-01

After a short review of the hardware and/or software tools for the development of single-chip, fixed instruction set microprocessor-based sytems we focus on the software tools for designing systems based on microprogrammed bit-sliced microprocessors. Emphasis is placed on meta-microassemblers and simulation facilties at the register-transfer-level and architecture level. We review available meta-microassemblers giving their most important features, advantages and disadvantages. We also make extentions to higher-level microprogramming languages and associated systems specifically developed for bit-slices. In the area of simulation facilities we first discuss the simulation objectives and the criteria for chosing the right simulation language. We consertrate to simulation facilities already used in bit-slices projects and discuss the gained experience. We conclude by describing the way the Signetics meta-microassembler and the ISPS simulation tool have been employed in the design of a fast microprogrammed machine, called MICE, made out of ECL bit-slices. (orig.)

A feedback microprocessor for hadron colliders

International Nuclear Information System (INIS)

Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

1992-12-01

A feedback microprocessor has been built for the TEVATRON. It has been constructed to be applicable to hadron colliders in general. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor software includes a finite state machine. Each state corresponds to a specific TEVATRON operation and has a state-specific TEVATRON model. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime corrections. We also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. In this paper we will describe this device and its use to control the TEVATRON tunes as well as other possible applications

An SEU rate prediction method for microprocessors of space applications

International Nuclear Information System (INIS)

Gao Jie; Li Qiang

2012-01-01

In this article,the relationship between static SEU (Single Event Upset) rate and dynamic SEU rate in microprocessors for satellites is studied by using process duty cycle concept and fault injection technique. The results are compared to in-orbit flight monitoring data. The results show that dynamic SEU rate by using process duty cycle can estimate in-orbit SEU rate of microprocessor reasonable; and the fault injection technique is a workable method to estimate SEU rate. (authors)

Fuzzy Logic and Intelligent Technologies in Nuclear Science (FLINS)

International Nuclear Information System (INIS)

Da Ruan

2000-01-01

FLINS is the acronym for Fuzzy Logic and Intelligent Technologies in Nuclear Science. In 1994, SCK-CEN launched a programme on FLINS. The first FLINS project dealt with the specific prototyping of fuzzy logic control (FLC) of the BR-1 research reactor. This project focussed on controlling the power level of the BR1 reactor added value of FLC for both safety and economic aspects for a nuclear reactor control operation. Main achievements in 1999 are reported

Fuzzy Logic Controller Design for Intelligent Robots

Directory of Open Access Journals (Sweden)

Ching-Han Chen

2017-01-01

Full Text Available This paper presents a fuzzy logic controller by which a robot can imitate biological behaviors such as avoiding obstacles or following walls. The proposed structure is implemented by integrating multiple ultrasonic sensors into a robot to collect data from a real-world environment. The decisions that govern the robot’s behavior and autopilot navigation are driven by a field programmable gate array- (FPGA- based fuzzy logic controller. The validity of the proposed controller was demonstrated by simulating three real-world scenarios to test the bionic behavior of a custom-built robot. The results revealed satisfactorily intelligent performance of the proposed fuzzy logic controller. The controller enabled the robot to demonstrate intelligent behaviors in complex environments. Furthermore, the robot’s bionic functions satisfied its design objectives.

Universal file processing program for field programmable integrated circuits

International Nuclear Information System (INIS)

Freytag, D.R.; Nelson, D.J.

1985-01-01

A computer program is presented that translates logic equations into promburner files (or the reverse) for programmable logic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibility through the use of a database containing detailed information about the devices to be programmed. New devices can thus be accommodated through simple extensions of the database. When writing logic equations, the user can define logic combinations of signals as new logic variables for use in subsequent equations. This procedure yields compact and transparent expressions for logic operations, thus reducing the chances for error. A logic simulation program is also provided so that an independent check of the design can be performed at the software level

Portable regional cerebral blood flow system based on IBM PC/AT and microprocessor electronics

International Nuclear Information System (INIS)

Mun, S.K.; Mun, I.K.; Petite, J.; Cohan, S.L.; Fahey, F.H.

1986-01-01

A portable 16-channel reginal cerebral blood flow (rCBF) measuring system has been developed using an IBM PC/AT and new microelectronics to improve processing speed and portability. The detector electronics were developed by Scan Detectronics A/S of Denmark. The counter module contains 18 16-bit counters, each programmable in four different modes. The rate meter has three independent microprocessor controllers for rate meter functions, window controller, and channel controller. The detector electronics and detection parameters can be fully controlled by the host PC/AT. The menu-driven system (Better Basic) assists the operator at each step. The collected data from 16 channels can be processed automatically or postprocessed using more flexible and sophisticated techniques within 20 minutes. The headgear holding 16 sodium iodide detectors is fabricated by modifying a motorcycle helmet

Radiation-hardened bulk Si-gate CMOS microprocessor family

International Nuclear Information System (INIS)

Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

1979-01-01

RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

Software V and V methods for a safety - grade programmable logic controller

International Nuclear Information System (INIS)

Jang Yeol Kim; Young Jun Lee; Kyung Ho Cha; Se Woo Cheon; Jang Soo Lee; Kee Choon Kwon

2006-01-01

This paper addresses the Verification and Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety- grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines and procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects. (author)

Report of the 2. research co-ordination meeting of the co-ordinated research programme on the development of computer-based troubleshooting tools and instruments

International Nuclear Information System (INIS)

1998-11-01

The Research coordination meeting reviewed current results on the Development of Computer-Based Troubleshooting Tools and Instruments. Presentations at the meeting were made by the participants, and the project summary reports include: PC based software for troubleshooting microprocessor-based instruments; technical data base software; design and construction of a random pulser for maintenance and quality control of a nuclear counting system; microprocessor-based power conditioner; in-circuit emulator for microprocessor-based nuclear instruments; PC-based analog signal generator for simulated detector signals and arbitrary test waveforms for testing of nuclear instruments; expert system for nuclear instrument troubleshooting; development and application of versatile computer-based measurement and diagnostic tools; and development of a programmable signal generator for troubleshooting of nuclear instrumentation

Reliability concerns with logical constants in Xilinx FPGA designs

Energy Technology Data Exchange (ETDEWEB)

Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX

2009-01-01

In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

Energy Technology Data Exchange (ETDEWEB)

Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh [Institute of Materials Science, Vietnam Academy of Science and Technology, 18 Hoang Quoc Viet Road, Cau Giay District, Hanoi (Viet Nam)], E-mail: minhpn@ims.vast.ac.vn

2009-09-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

Science.gov (United States)

Thang, Bui Hung; Hong, Phan Ngoc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5°C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

International Nuclear Information System (INIS)

Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh

2009-01-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

Science.gov (United States)

Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

2015-02-01

A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer，a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

Reversible arithmetic logic unit for quantum arithmetic

DEFF Research Database (Denmark)

Thomsen, Michael Kirkedal; Glück, Robert; Axelsen, Holger Bock

2010-01-01

This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic...... and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n......-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible...

Multichannel analyzer based on microprocessors

International Nuclear Information System (INIS)

Soares, M.

1983-06-01

A multichannel analyser for nuclear spectrometry, that would attend the needs of research laboratories and could be industrialized in Brazil, was developed. The design was based on INTEL 8080/85 microprocessors; other processors were also used to implement specific functions, such as shared busbar using direct memory access. A prototype was developed and tested through simulation, using a nuclear spectrometry chain. The results were fully satisfactory. (Author) [pt

Nonlinear dynamics based digital logic and circuits.

Science.gov (United States)

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Broader utilization of programmable automation equipment in French nuclear power plants: Reflections on the choices made by Electricite de France and French designers

International Nuclear Information System (INIS)

Baudry, Y.; Varaldi, G.

1983-01-01

More than 1000 microprocessors and more than 10,000 data memories in each of the twenty or so 1300 MW units in the French nuclear programme: that was the decision taken by Electricite de France (EDF) in conjunction with the designers in 1974, with the intention of introducing programmable automata on a wide scale in French nuclear power plants. This programme was carried out with the assistance of advanced research services such as the universities, the Commissariat a l'energie atomique (CEA), EDF's design and research service and the designers, most of whom were already EDF suppliers for the 900 MW range. Having used computers for linking sequences (themselves carried out with electromagnetic technology) for its latest natural-uranium gas-cooled graphite-moderated power plants, EDF decided to call a temporary halt, in the case of its 900 MW light-water range, to the use of digital techniques for the control and automation of power plants although it continued to employ such techniques widely in data processing. Thus, the widespread introduction of programmable automata, which was decided upon in 1974/75 at a time when no equivalent existed at the international level, led EDF and French designers to undertake a major development effort in order to meet the requirements - particularly safety and reliability requirements - for such automata to be incorporated into the nuclear field. How does this choice fit in with the logical evolution of the digitalization of French nuclear power plants. What problems has it caused for EDF and French industry. How have these problems been tackled. How have they been overcome. These are the questions dealt with in this paper. (author)

Orientation of a 3D object: implementation with an artificial neural network using a programmable logic device

International Nuclear Information System (INIS)

Carnevale, Federico J.

2010-01-01

Complex information extraction from images is a key skill of intelligent machines, with wide application in automated systems, robotic manipulation and human-computer interaction. However, solving this problem with traditional, geometric or analytical, strategies is extremely difficult. Therefore, an approach based on learning from examples seems to be more appropriate. This thesis addresses the problem of 3D orientation, aiming to estimate the angular coordinates of a known object from an image shot from any direction. We describe a system based on artificial neural networks to solve this problem in real time. The implementation is performed using a programmable logic device. The digital system described in this paper has the ability to estimate two rotational coordinates of a 3D known object, in ranges from -80 0 to 80 0 . The operation speed allows a real time performance at video rate. The system accuracy can be successively increased by increasing the size of the artificial neural network and using a larger number of training examples [es

A Computed River Flow-Based Turbine Controller on a Programmable Logic Controller for Run-Off River Hydroelectric Systems

Directory of Open Access Journals (Sweden)

Razali Jidin

2017-10-01

Full Text Available The main feature of a run-off river hydroelectric system is a small size intake pond that overspills when river flow is more than turbines’ intake. As river flow fluctuates, a large proportion of the potential energy is wasted due to the spillages which can occur when turbines are operated manually. Manual operation is often adopted due to unreliability of water level-based controllers at many remote and unmanned run-off river hydropower plants. In order to overcome these issues, this paper proposes a novel method by developing a controller that derives turbine output set points from computed mass flow rate of rivers that feed the hydroelectric system. The computed flow is derived by summation of pond volume difference with numerical integration of both turbine discharge flows and spillages. This approach of estimating river flow allows the use of existing sensors rather than requiring the installation of new ones. All computations, including the numerical integration, have been realized as ladder logics on a programmable logic controller. The implemented controller manages the dynamic changes in the flow rate of the river better than the old point-level based controller, with the aid of a newly installed water level sensor. The computed mass flow rate of the river also allows the controller to straightforwardly determine the number of turbines to be in service with considerations of turbine efficiencies and auxiliary power conservation.

The PLC: a logical development

OpenAIRE

Walker, Mark; Bissell, Christopher; Monk, John

2010-01-01

Programmable Logic Controllers (PLCs) have been used to control industrial processes and equipment for over 40 years, having their first commercially recognised application in 1969. Since then there have been enormous changes in the design and application of PLCs, yet developments were evolutionary rather than radical. The flexibility of the PLC does not confine it to industrial use and it has been used for disparate non-industrial control applications . This article reviews the history, deve...

Microprocessor Activity Controls Differential miRNA Biogenesis In Vivo

Directory of Open Access Journals (Sweden)

Thomas Conrad

2014-10-01

Full Text Available In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression.

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

The Zimmer nuclear to coal conversion

International Nuclear Information System (INIS)

Baer, R.H.; Pfund, E.M.; Buchmueller, D.P.; Fletcher, J.R.

1991-01-01

This paper discusses the control, protection and monitoring systems employed on the world's first nuclear-to-coal power plant conversion, the philosophies utilized to guide the engineering of these systems and the implementation of those philosophies. Extensive use is made of programmable electronic systems to provide a state-of-the-art plant which does not compromise the proven operating interfaces and philosophies associated with AEP's six operating 1300 MW units. The technologies employed include two distributed digital control systems, a fiber optic-based network of programmable logic controllers, a distributed microprocessor-based annunciator and sequence of events system, and a plant operations computer which accesses each of the preceding systems

Programmable combinational logic trigger system for high energy particle physics experiments

International Nuclear Information System (INIS)

Platner, E.D.

1976-01-01

A fast logic system designed to select predetermined combinations of three hits in three detectors is described. Central to this system is a random access memory IC that was especially designed for this application

Microprocessors: From basic chips to complete systems

International Nuclear Information System (INIS)

Dobinson, R.W.

1985-01-01

These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/0) devices, etc. (orig./HSI)

Microprocessor Controlled Capacitor Bank Switching System for ...

African Journals Online (AJOL)

In this work, analysis and development of a microprocessor controlled capacitor bank switching system for deployment in a smart distribution network was carried out. This system was implemented by the use of discreet components such as resistors, capacitors, transistor, diode, automatic voltage regulator, with the ...

The need for theory evaluation in global citizenship programmes: The case of the GCSA programme.

Science.gov (United States)

Goodier, Sarah; Field, Carren; Goodman, Suki

2018-02-01

Many education programmes lack a documented programme theory. This is a problem for programme planners and evaluators as the ability to measure programme success is grounded in the plausibility of the programme's underlying causal logic. Where the programme theory has not been documented, conducting a theory evaluation offers a foundational evaluation step as it gives an indication of whether the theory behind a programme is sound. This paper presents a case of a theory evaluation of a Global Citizenship programme at a top-ranking university in South Africa, subsequently called the GCSA Programme. This evaluation highlights the need for documented programme theory in global citizenship-type programmes for future programme development. An articulated programme theory produced for the GCSA Programme, analysed against the available social science literature, indicated it is comparable to other such programmes in terms of its overarching framework. What the research found is that most other global citizenship programmes do not have an articulated programme theory. These programmes also do not explicitly link their specific activities to their intended outcomes, making demonstrating impact impossible. In conclusion, we argue that taking a theory-based approach can strengthen and enable outcome evaluations in global citizenship programmes. Copyright © 2017. Published by Elsevier Ltd.

All-spin logic operations: Memory device and reconfigurable computing

Science.gov (United States)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Design and Implementation of O/C relay using Microprocessor

Directory of Open Access Journals (Sweden)

Dr.Abdul-Sattar H. Jasim

2012-03-01

Full Text Available This work presents the design and implementation of a versatile digital overcurrent (O/C relay using a single microprocessor. The relay is implemented by a combination of a look-up table and a counter. The software development and hardware testing are done using a microcomputer module based on a 8-bit microprocessor. The digital processing of measured currents enables a separate setting of operating values selection of all types of inverse or constant time characteristics overcurrent protection. This protection provides reasonably fast tripping, even at terminal close to the power source were the most serve faults can occur excluding the transient condition. So this method has an excellent compromise between accuracy hardware and speed

High-speed multiple-channel analog to digital data-acquisition module for microprocessor systems

International Nuclear Information System (INIS)

Ethridge, C.D.

1977-01-01

Intelligent data acquisition and instrumentation systems established by the incorporation of microprocessor technology require high-speed analog to digital conversion of multiple-channel input signals. Sophisticated data systems or subsystems are enabled by the microprocessor software flexibility to establish adaptive input data procedures. These adaptive procedures are enhanced by versatile interface circuitry which is software controlled

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Science.gov (United States)

Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

Power consumption of programmable controllers; Energieverbrauch von Prozesssteuerungen (SPS)

Energy Technology Data Exchange (ETDEWEB)

Schalcher, M.; Battaglia, U.; Busch, E.

2003-07-01

This final report for the Swiss Federal Office for Energy addresses the field of programmable logic controllers and thus investigates a topic that has been neglected up to now - the energy consumption of such controllers. The results of measurements made on programmable logic controllers in use both in operational industrial plants and in the Automation Laboratory at the University of Applied Science in Chur, Switzerland are presented, where a detailed analysis was made on a demonstration plant. Also, technical documentation (catalogues) were evaluated and discussed with experts who had practical experience at their disposal. The results of the study are discussed: these show that the power consumption of any particular programmable logic controller is low in comparison to the energy consumption of the processes that are being controlled. Additionally, it was found that the optimisation of newer devices has to a great extent already been realised and that standard solutions for energy optimisation are not easy to put into practice. It is suggested that savings can possibly be made in the controllers by improving the efficiency of their power supply units and by choosing power ratings to better suit the actual power needed.

Microprocessors control of fermentation process

Energy Technology Data Exchange (ETDEWEB)

Fawzy, A S; Hinton, O R

1980-01-01

This paper presents three schemes for the solution of the optimal control of fermentation process. It also shows the advantages of using microprocessors in controlling and monitoring this process. A linear model of the system is considered. An optimal feedback controller is determined which maintains the states (substrate and organisms concentration) at desired values when the system is subjected to disturbances in the influent substrate and organisms concentration. Simulation results are presented for the three cases.

Microprocessor-based stepping motor driver

International Nuclear Information System (INIS)

Halbig, J.K.; Klosterbuer, S.F.

1979-09-01

The Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory requires a versatile stepping motor driver to do beam diagnostic measurements. A driver controlled by a microprocessor that can move eight stepping motors simultaneously was designed. The driver can monitor and respond to clockwise- and counterclockwise-limit switches, and it can monitor a 0- to 10-V dc position signal. The software controls start and stop ramping and maximum stepping rates. 2 figures, 1 table

Optimization of Reciprocals and Square Roots on the i860 Microprocessor

DEFF Research Database (Denmark)

Sinclair, Robert

1996-01-01

The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance.......The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance....

Robust position control of induction motor using fuzzy logic control

International Nuclear Information System (INIS)

Kim, Sei Chan; Kim, Duk Hun; Yang, Seung Ho; Won, Chung Yuen

1993-01-01

In recent years, fuzzy logic or fuzzy set theory has reveived attention of a number of researchers in the area of power electronics and motion control. The paper describes a vector-controlled induction motor position servo drive where fuzzy control is used to get robustness against parameter variation and load torque disturbance effects. Both coarse and fine control with the help of look-up rule tables are used to improve transient response and system settling time. The performance characteristics are then compared with those of proportional-integral(PI) control. The simulation results clearly indicate the superiority of fuzzy control with larger number of rules. The fuzzy controller was implemented with a 16-bit microprocessor and tested in laboratory on a 3-hp IGBT inverter induction motor drive system. The test results verify the simulation performance. (Author)

Programmable logic controller performance enhancement by field programmable gate array based design.

Science.gov (United States)

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Methods of software V and V for a programmable logic controller in NPPs

International Nuclear Information System (INIS)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Son, Han Seong; Lee, Jang Soo; Kwon, Kee Choon

2004-01-01

This paper addresses the Verification and Validation (V and V) process and methodology for embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed in the Korea Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System (ESF-CCS) as well as safety-grade PLC. Safety-grade PLC will be a major component that composes the RPS systems and ESF-CCS systems as nuclear instruments and control equipments. This paper describes the V and V guidelines and procedure, V and V environment, V and V process and methodology, and the V and V tools by the KNICS projects. Specially, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase of the software development life cycle. Main activities of the real-time operating system Software Requirement Specification(SRS) V and V of the PLC are the technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14(MOST-KSRG 7/Appendix 15 in Korea will be issued soon) criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to verify the upcoming software life cycle in the KNICS projects. (author)

Microprocessor protection devices: The present and the future

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2008-01-01

Full Text Available Paper presents the analysis of the basic constructive disadvantages of the present day microprocessor-based protective devices (MBR and offers the basic principles for creating a new MBR that can be used in newly constructed devices.

An integrated high performance Fastbus slave interface

International Nuclear Information System (INIS)

Christiansen, J.; Ljuslin, C.

1993-01-01

A high performance CMOS Fastbus slave interface ASIC (Application Specific Integrated Circuit) supporting all addressing and data transfer modes defined in the IEEE 960 - 1986 standard is presented. The FAstbus Slave Integrated Circuit (FASIC) is an interface between the asynchronous Fastbus and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32 bit microprocessor. The FASIC is a programmable device enabling its direct use in many different applications. A set of programmable address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/sec to Fastbus can be obtained using an internal FIFO in the FASIC to buffer data between the two buses during block transfers. Message passing from Fastbus to a microprocessor on the slave module is supported. A compact (70 mm x 170 mm) Fastbus slave piggy back sub-card interface including level conversion between ECL and TTL signal levels has been implemented using surface mount components and the 208 pin FASIC chip

Embedding Logics into Product Logic

Czech Academy of Sciences Publication Activity Database

Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David

1998-01-01

Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics

Architectural and compiler techniques for energy reduction in high-performance microprocessors

Science.gov (United States)

Bellas, Nikolaos

1999-11-01

The microprocessor industry has started viewing power, along with area and performance, as a decisive design factor in today's microprocessors. The increasing cost of packaging and cooling systems poses stringent requirements on the maximum allowable power dissipation. Most of the research in recent years has focused on the circuit, gate, and register-transfer (RT) levels of the design. In this research, we focus on the software running on a microprocessor and we view the program as a power consumer. Our work concentrates on the role of the compiler in the construction of "power-efficient" code, and especially its interaction with the hardware so that unnecessary processor activity is saved. We propose techniques that use extra hardware features and compiler-driven code transformations that specifically target activity reduction in certain parts of the CPU which are known to be large power and energy consumers. Design for low power/energy at this level of abstraction entails larger energy gains than in the lower stages of the design hierarchy in which the design team has already made the most important design commitments. The role of the compiler in generating code which exploits the processor organization is also fundamental in energy minimization. Hence, we propose a hardware/software co-design paradigm, and we show what code transformations are necessary by the compiler so that "wasted" power in a modern microprocessor can be trimmed. More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction

The Microprocessor controls the activity of mammalian retrotransposons

DEFF Research Database (Denmark)

Heras, Sara R.; Macias, Sara; Plass, Mireya

2013-01-01

RNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions...

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Science.gov (United States)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Microprocessor-controlled portable neutron spectrometer

International Nuclear Information System (INIS)

Hunt, G.F.; Kaifer, R.C.; Slaughter, D.R.; Strout, R.E. II; Rueppel, D.W.

1979-01-01

A neutron spectrometer that acquires and unfolds data in the field has been developed for use in the energy range from 1 to 20 MeV. The system includes an NE213 organic scintillation detector, automatic gain stabilization, automatically stabilized pulseshape discrimination, an LSl-11 microprocessor for control and data reduction, and a multichannel analyzer for data acquisition. The system, with the exception of the multichannel analyzer, is mounted in a suitcase 47 by 66 by 23.5 cm. The mass is 23.5 kg

Real-time fetal ECG system design using embedded microprocessors

Science.gov (United States)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

Field Programmable Gate Array-based I and C Safety System

International Nuclear Information System (INIS)

Kim, Hyun Jeong; Kim, Koh Eun; Kim, Young Geul; Kwon, Jong Soo

2014-01-01

Programmable Logic Controller (PLC)-based I and C safety system used in the operating nuclear power plants has the disadvantages of the Common Cause Failure (CCF), high maintenance costs and quick obsolescence, and then it is necessary to develop the other platform to replace the PLC. The Field Programmable Gate Array (FPGA)-based Instrument and Control (I and C) safety system is safer and more economical than Programmable Logic Controller (PLC)-based I and C safety system. Therefore, in the future, FPGA-based I and C safety system will be able to replace the PLC-based I and C safety system in the operating and the new nuclear power plants to get benefited from its safety and economic advantage. FPGA-based I and C safety system shall be implemented and verified by applying the related requirements to perform the safety function

Field Programmable Gate Array-based I and C Safety System

Energy Technology Data Exchange (ETDEWEB)

Kim, Hyun Jeong; Kim, Koh Eun; Kim, Young Geul; Kwon, Jong Soo [KEPCO, Daejeon (Korea, Republic of)

2014-08-15

Programmable Logic Controller (PLC)-based I and C safety system used in the operating nuclear power plants has the disadvantages of the Common Cause Failure (CCF), high maintenance costs and quick obsolescence, and then it is necessary to develop the other platform to replace the PLC. The Field Programmable Gate Array (FPGA)-based Instrument and Control (I and C) safety system is safer and more economical than Programmable Logic Controller (PLC)-based I and C safety system. Therefore, in the future, FPGA-based I and C safety system will be able to replace the PLC-based I and C safety system in the operating and the new nuclear power plants to get benefited from its safety and economic advantage. FPGA-based I and C safety system shall be implemented and verified by applying the related requirements to perform the safety function.

Description and characterization of the ACRR's programmable transient rod withdrawal mode

International Nuclear Information System (INIS)

Boldt, K.R.; Sullivan, W.H.; Kefauver, H.L.

1980-01-01

To satisfy experiment needs for Sandia's Advanced Reactor Safety Program, a programmable Transient Rod Withdrawal (TRW) mode has been developed for the Annular Core Research Reactor (ACRR). The programmable mode is a modification of the existing continuous-withdrawal TRW mode and permits speed and direction changes during the pulse sequence. Basically, a TRW operation is similar to a routine pulse operation except that transient rods are mechanically withdrawn rather than pneumatically fired. Being a pulse-type operation, the TRW mode complies with pulse-mode safety system settings. Control system interlocks prevent the pneumatic firing of rods in the TRW mode. The hardware for the programmable TRW mode includes three ACRR transient rods, the ACRR timer, two rod programmers, a minicomputer and a summing circuit for position indication. Each ACRR transient rod is mechanically driven by a stepping motor (rated torque at 4.24 joules) and is capable of a maximum TRW speed of 26.7 centimeters/ second. The maximum reactivity insertion rate is $2.45/second with a transient rod bank worth of $3.00 and $3.47/second with a bank worth of $4.25, which is expected to be installed soon. The ACRR timer is a multifunctional timer used in all operating modes of the reactor. In the programmable TRW mode, the timer starts the rod programmers and drops regulating rods to terminate the operation. Programmed withdrawal capability is provided by one of two rod programmers (a hardwire-based unit and a microprocessor-based unit). The hardwire unit has eight intervals in which speed, direction and distance are selected by switches on the front panel. The microprocessor-based unit has the capability of 64 intervals in which speed, direction, and distance or time can be specified. Programming this unit is accomplished from the front panel or by inputting data from an HP-9845. minicomputer via a digital I/O interface. Self-test programs in the software provide a continual check of an operating

System and method for programmable bank selection for banked memory subsystems

Energy Technology Data Exchange (ETDEWEB)

Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton on Hudson, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Hoenicke, Dirk (Seebruck-Seeon, DE); Ohmacht, Martin (Yorktown Heights, NY); Salapura, Valentina (Chappaqua, NY); Sugavanam, Krishnan (Mahopac, NY)

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Design analysis and microprocessor based control of a nuclear reactor

International Nuclear Information System (INIS)

Sabbakh, N.J.

1988-01-01

The object of this thesis is to design and test a microprocessor based controller, to a simulated nuclear reactor system. The mathematical model that describes the dynamics of a typical nuclear reactor of one group of delayed neutrons approximations with temperature feedback was chosen. A digital computer program has been developed for the design and analysis of a simulated model based on the concept of state-variable feedback in order to meet a desired system response with maximum overshoot of 3.4% and setting time of 4 sec. The state variable feedback coefficients are designed for the continuous system, then an approximation is used to obtain in the state variable feedback vector for the discrete system. System control was implemented utilizing Direct Digital Control (DDC) of a nuclear reactor simulated model through a control algorithm that was performed by means of a microprocessor based system. The controller performance was satisfactorily tested by exciting the reactor system with a transient reactivity disturbance and by a step change in power demand. Direct digital control, when implemented on a microprocessor adds versatility, flexibility in system design with the added advantage of possible use of optimal control algorithms. 6 tabs.; 30 figs.; 46 refs.; 6 apps

Designs and performance of three new microprocessor-controlled knee joints.

Science.gov (United States)

Thiele, Julius; Schöllig, Christina; Bellmann, Malte; Kraft, Marc

2018-02-09

A crossover design study with a small group of subjects was used to evaluate the performance of three microprocessor-controlled exoprosthetic knee joints (MPKs): C-Leg 4, Plié 3 and Rheo Knee 3. Given that the mechanical designs and control algorithms of the joints determine the user outcome, the influence of these inherent differences on the functional characteristics was investigated in this study. The knee joints were evaluated during level-ground walking at different velocities in a motion analysis laboratory. Additionally, technical analyses using patents, technical documentations and X-ray computed tomography (CT) for each knee joint were performed. The technical analyses showed that only C-Leg 4 and Rheo Knee 3 allow microprocessor-controlled adaptation of the joint resistances for different gait velocities. Furthermore, Plié 3 is not able to provide stance extension damping. The biomechanical results showed that only if a knee joint adapts flexion and extension resistances by the microprocessor all known advantages of MPKs can become apparent. But not all users may benefit from the examined functions: e.g. a good accommodation to fast walking speeds or comfortable stance phase flexion. Hence, a detailed comparison of user demands and performance of the designated knee joint is mandatory to ensure a maximum in user outcome.

Neutron beam irradiation study of workload dependence of SER in a microprocessor

Energy Technology Data Exchange (ETDEWEB)

Michalak, Sarah E [Los Alamos National Laboratory; Graves, Todd L [Los Alamos National Laboratory; Hong, Ted [STANFORD; Ackaret, Jerry [IBM; Sonny, Rao [IBM; Subhasish, Mitra [STANFORD; Pia, Sanda [IBM

2009-01-01

It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

Hardware math for the 6502 microprocessor

Science.gov (United States)

Kissel, R.; Currie, J.

1985-01-01

A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

Design and implementation of a microprocessor based room ...

African Journals Online (AJOL)

This paper describes the development of a microprocessor based room illumination control system that offers advantage of improved efficiency in the use of electrical energy and reduced cost of electricity over manually controlled lighting systems. This system is developed to regulate the intensity of light from direct current ...

The specifications a multichannel analyser using microprocessor

International Nuclear Information System (INIS)

Pontes, E.W.

The idea of a small nuclear data acquisition system (stand - alone CAMAC system) used for spectroscopy, is presented. The system is composed by an autonomous controller with microprocessor with one fast programable unit (1-2 μsec/CAMAC instructions) and with modulus of general functions as: CAMAC memory, interface for video, interface for analogy to digital converter and temporizing. (E.G.) [pt

Microprocessor event analysis in parallel with Camac data acquisition

International Nuclear Information System (INIS)

Cords, D.; Eichler, R.; Riege, H.

1981-01-01

The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a Camac System (GEC-ELLIOTT System Crate) and shares the Camac access with a Nord-1OS computer. Interfaces have been designed and tested for execution of Camac cycles, communication with the Nord-1OS computer and DMA-transfer from Camac to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-1OS computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the result of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-1OS buffer will be reset and the event omitted from further processing. (orig.)

The micro-processor controlled process radiation monitoring system for reactor safety systems

International Nuclear Information System (INIS)

Mizuno, K.; Noguchi, A.; Kumagami, S.; Gotoh, Y.; Kumahara, T.; Arita, S.

1986-01-01

Digital computers are soon expected to be applied to various real-time safety and safety-related systems in nuclear power plants. Hitachi is now engaged in the development of a micro-processor controlled process radiation monitoring system, which operates on digital processing methods employed with a log ratemeter. A newly defined methodology of design and test procedures is being applied as a means of software program verification for these safety systems. Recently implemented micro-processor technology will help to achieve an advanced man-machine interface and highly reliable performance. (author)

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Science.gov (United States)

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

V and V methods of a safety-critical software for a programmable logic controller

Energy Technology Data Exchange (ETDEWEB)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Kong, Seung Ju [Korea Hydro and Nuclear Power Co., Ltd, Daejeon (Korea, Republic of)

2005-11-15

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects.

V and V methods of a safety-critical software for a programmable logic controller

International Nuclear Information System (INIS)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon; Kong, Seung Ju

2005-01-01

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects

Microprocessor Card for Cuban Series polarimeters Laserpol

International Nuclear Information System (INIS)

Arista Romeu, E.; Mora Mazorra, W.

2012-01-01

We present the design consists of a card based on a micro-processor 8-bit adds new software components and their basic living, which allow to deliver new services and expand the possibilities for use in other applications of the polarimeter LASERPOL series, as the polarimetric detection. Given the limitations of the original card it was necessary to introduce a series of changes that would allow to address new user requirements, and expand the possible applications of the instruments. This was done the expansion of the capacity of the EPROM and RAM memory, the decoder circuit was implemented memory map using a programmable integrated circuit, and introduced a real time clock with nonvolatile RAM, these features are exploited to the introduction of new features such as the realization of the polarimeter calibration by the user from a sample pattern or a calibration pattern used as a reference, and the incorporation of the time and date to the reports of measurements required industry for quality control processes. Card that is achieved along with the rest of the components is compatible with polarimeters LASERPOL 101M Series, 3M and LP4, pin to pin, which facilitates their incorporation into the polarimeters in operation in the industry 'in situ' replacement cards from previous models, allowing to extend the possibilities of statistical processing, precision and accuracy of the instruments. Improved measurements in the industry, resulting in significant savings by elimination of losses in production and raw materials. The improved response speed of reading the polarimeters LASERPOL Use and polarimetric detectors. (Author)

Some software algorithms for microprocessor ratemeters

International Nuclear Information System (INIS)

Savic, Z.

1991-01-01

After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.)

Some software algorithms for microprocessor ratemeters

Energy Technology Data Exchange (ETDEWEB)

Savic, Z. (Military Technical Inst., Belgrade (Yugoslavia))

1991-03-15

After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.).

An integrated high performance fastbus slave interface

International Nuclear Information System (INIS)

Christiansen, J.; Ljuslin, C.

1992-01-01

A high performance Fastbus slave interface ASIC is presented. The Fastbus slave integrated circuit (FASIC) is a programmable device, enabling its direct use in many different applications. The FASIC acts as an interface between Fastbus and a 'standard' processor/memory bus. It can work stand-alone or together with a microprocessor. A set of address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/s to Fastbus can be obtained using an internal FIFO buffer in the FASIC. (orig.)

System design and installation for RS600 programmable control system for solar heating and cooling

Science.gov (United States)

1978-01-01

Procedures for installing, operating, and maintaining a programmable control system which utilizes a F8 microprocessor to perform all timing, control, and calculation functions in order to customize system performance to meet individual requirements for solar heating, combined heating and cooling, and/or hot water systems are described. The manual discusses user configuration and options, displays, theory of operation, trouble-shooting procedures, and warranty and assistance. Wiring lists, parts lists, drawings, and diagrams are included.

Nonconformance in electromechanical output relays of microprocessor-based protection devices under actual operating conditions

OpenAIRE

Gurevich, Vladimir

2006-01-01

Microprocessor-based protection relays are gradually driving out traditional electromechanical and even electronic protection devices from virtually all fields of power and electrical engineering. In this paper, one of many problems of microprocessor-based relays is discussed: nonconformance of miniature electromechanical output relays under actual operation conditions: switching inductive loads (with tripping CB coils or lockout relay coils) at 220 VDC, and "dry" switching of some control ci...

Application of a 16-bit microprocessor to the digital control of machine tools

International Nuclear Information System (INIS)

Issaly, Alain

1979-01-01

After an overview of machine tools (various types, definition standardization, associated technologies for motors and position sensors), this research thesis describes the principles of computer-based digital control: classification of machine tool command systems, machining programming, programming languages, dialog function, interpolation function, servo-control function, tool compensation function. The author reports the application of a 16-bit microprocessor to the computer-based digital control of a machine tool: feasibility, selection of microprocessor, hardware presentation, software development and description, machining mode, translation-loading mode

A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

International Nuclear Information System (INIS)

Song, S. H.; Lee, M. S.; Kim, T. H.; Park, C. H.; Park, S. P.; Kim, H. S.

2014-01-01

As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system

A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

Energy Technology Data Exchange (ETDEWEB)

Song, S. H. [Korea University, Seoul (Korea, Republic of); Lee, M. S.; Kim, T. H. [Formal Work Inc., Seoul (Korea, Republic of); Park, C. H. [LINE Corp., Tokyo (Japan); Park, S. P. [Ahnlab Inc., Seoul (Korea, Republic of); Kim, H. S. [Sejong University, Seoul (Korea, Republic of)

2014-08-15

As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system.

Microprocessor, Setx, Xrn2, and Rrp6 Co-operate to Induce Premature Termination of Transcription by RNAPII

NARCIS (Netherlands)

Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

2012-01-01

Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 30-50 exoribonuclease,

Configuration and debug of field programmable gate arrays using MATLAB[reg)/SIMULINK[reg

International Nuclear Information System (INIS)

Grout, I; Ryan, J; O'Shea, T

2005-01-01

Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB[reg] model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB[reg] model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK[reg] model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use

Microprocessor event analysis in parallel with CAMAC data acquisition

CERN Document Server

Cords, D; Riege, H

1981-01-01

The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a CAMAC System (GEC-ELLIOTT System Crate) and shares the CAMAC access with a Nord-10S computer. Interfaces have been designed and tested for execution of CAMAC cycles, communication with the Nord-10S computer and DMA-transfer from CAMAC to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-10S computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the results of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-10S buffer will be reset and the event omitted from further processing. (5 refs).

Microprocessor-based accelerating power level detector

Energy Technology Data Exchange (ETDEWEB)

Nagpal, M.; Zarecki, W.; Albrecht, J.C.

1994-01-01

An accelerating power level detector was built using state-of-the-art microprocessor technology at Powertech Labs Inc. The detector will monitor the real power flowing in two 300 kV transmission lines out of Kemano Hydroelectric Generating Station and will detect any sudden loss of load due to a fault on either line under certain pre-selected power flow conditions. This paper discusses the criteria of operation for the detector and its implementation details, including digital processing, hardware, and software.

Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

Directory of Open Access Journals (Sweden)

Archana Shenoy

2009-09-01

Full Text Available The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript.To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8.We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

Leak detection system with distributed microprocessor in the primary containment vessel

International Nuclear Information System (INIS)

Inahara, K.; Yoshioka, K.; Tomizawa, T.

1980-01-01

Responding to the demand for greater improvements of the safety monitoring system, less public radiation exposure, and increase of plant availability, measuring and control systems in nuclear power plants have undergone many improvements. Leak detection systems are also required to give earlier warning, additional accuracy, and continuous monitoring function. This paper describes the drywell sump leakage detection system utilizing a distributed microprocessor, which is a successful application owing to its versatile function and ease of installation. The microprocessor performs various functions such as a rate of level change computation, conversion to leakage flow rate, initiation of alarm, and sump pump control. This system has already been applied to three operating BWR plants that demonstrate its efficiency. (auth)

Data Logic

DEFF Research Database (Denmark)

Nilsson, Jørgen Fischer

A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...

The screening approach for review of accident management programmes

International Nuclear Information System (INIS)

Misak, J.

1999-01-01

In this lecture the screening approach for review of accident management programmes are presented. It contains objective trees for accident management: logic structure of the approach; objectives and safety functions for accident management; safety principles

Extending Value Logic Thinking to Value Logic Portfolios

DEFF Research Database (Denmark)

Andersen, Poul Houman; Ritter, Thomas

2014-01-01

Based on value creation logic theory (Stabell & Fjeldstad, 1998), this paper suggests an extension of the original Stabell & Fjeldstad model by an additional fourth value logic, the value system logic. Furthermore, instead of only allowing one dominant value creation logic for a given firm...... or transaction, an understanding of firms and transactions as a portfolio of value logics (i.e. an interconnected coexistence of different value creation logics) is proposed. These additions to the original value creation logic theory imply interesting avenues for both, strategic decision making in firms...

Nanoeletromechanical switch and logic circuits formed therefrom

Science.gov (United States)

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Future microprocessor farms: Offline and online

International Nuclear Information System (INIS)

Areti, H.

1990-01-01

Microprocessor farms have been successfully employed in high energy physics for both offline analysis and online triggers. As the experiments continue to grow in size, so do the demands for processing power. The preliminary indications are that the large collider experiments will require at least a million VAX-11/780 equivalents of processing power for online trigger decisions and offline event reconstruction. This paper examines the current technology trends and projects the processing power that may be expected with the current farm architectures. 3 refs., 6 figs

Independent programmable CAMAC crate controller based on KR580IK80A microprocessor

International Nuclear Information System (INIS)

Kulik, O.V.; Andronov, M.A.

1986-01-01

The RTKAM-2 independent programmable CAMAC crate controller is designed for use as a remote terminal in systems for automation of physics research. The built-in 12K-byte RAM is automatically changed to 24-bit organization in exchanges with the crate dataway. A nonstandard 24-level priority-interrupt system allows an LAM-request routing to be accessed in 5.5 μsec. Communication with the base computer is through a two conductor line

High speed serial link for UA1 microprocessor network

CERN Document Server

Cittolin, S; Zurfluh, E

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

High speed serial link for UA1 microprocessor network

CERN Document Server

Cittolin, Sergio; Zurfluh, E

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like data acquisition crate controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI computer language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

API testing program - calibration of microprocessor based flowmeters for integrated metering systems

Energy Technology Data Exchange (ETDEWEB)

Elliot, Kenneth D. [Omni Flow Computers, Inc., Stafford, TX (United States)

2005-07-01

Microprocessor based flowmeter technologies for liquids, such as Coriolis mass meters, and Ultrasonic flowmeters hold great promise. These technologies offer many advantages, such as no rotating parts, self-diagnostic checks, which can help anticipate and warn of impending failures before they have a major impact on the measurement. These meters are substantially different though than other primary devices due to their heavy reliance on the accompanying secondary electronics. One method to prove that they are accurate would be proving the flowmeter, using a pipe prover or small volume prover (SVP), but these proving methods are designed to count 'real time' pulses from a turbine or PD meter between a known volume, they are not designed to count 'time delayed' 'manufactured pulses' from a microprocessor. There are limitations of the manufactured pulse train and it affects the ability of the flowmeter to be proved using current proving technology. The author of this paper, a chairman of an American Petroleum Institute working group, investigated how the 'microprocessor generated pulses' produced by these types of flowmeters, interacted with the existing measurement technologies in use today. Several microprocessor based flowmeter technologies have been tested, including; Ultrasonic, Coriolis, and Helical Turbine with pulse multiplying preamplifier. Wherever possible, flowmeters of various sizes, and from several vendors have been tested. A significant amount of data has been collected which sheds light into why these types of flowmeters are sometimes difficult to prove. This paper describes the API testing program, and the methodology behind it. It presents results and findings, and offers specific recommendations that may eventually be incorporated into API documents and/or standards in the future. (author)

Microprocessor controlled digital period meter

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.; Rusch, G.K.

1980-01-01

A microprocessor controlled digital period meter has been developed and tested operationally on a reactor at Argonne National Laboratory. The principle of operation is the mathematical relationship between asymptotic periods and pulse counting circuitry. This relationship is used to calculate and display the reactor periods over a range of /plus or minus/1 second to /plus or minus/999 seconds. The time interval required to update each measurement automatically varies from 8 seconds at the lowest counting rates to 2 seconds at higher counting rates. The paper will describe hardware and software design details and show the advantages of this type of Period Meter over the conventional circuits. 1 ref

Recent applications of microprocessor-based instruments in nuclear power stations

International Nuclear Information System (INIS)

Cash, N.R.; Dennis, U.E.

1988-01-01

The incorporation of microprocessors in the design of nuclear power plant instrumentation has led to levels of measurement and control not available previously. In addition to the expected expansion of functional (system) capability, numerous desirable features now are possible. The added ability to both self-calibrate and perform compensation algorithms has led to dramatic improvements in accuracies, response times, and noise rejection. Automated performance checking and self-testing simplify troubleshooting and required periodic surveillance. Alphanumeric displays allow both menu-driven operation and user-prompting, which, in turn, contribute to mistake avoidance. New features of these microprocessor-based instruments are of specific benefit in nuclear power reactors, were safety is of prime concern. Greater reliability and accuracy can be provided. Shortened calibration, surveillance, and repair times reduce the exposure to unnecessary challenges of the plant's protection systems that can arise from spurious noise signals

Operating experiences with programmable logic controller (PLC) system of Indian Pressurised Heavy Water Reactors (PHWR)

International Nuclear Information System (INIS)

Ughade, A.V.; Singh, Ranjeet; Bhattacharya, P.K.; Kulkarni, R.K.; Chandra, Umesh

2005-01-01

PLC system was introduced for the first time in Kaiga-1,2 and RAPS-3,4 Nuclear Power Plants (NPPs) for Station Logic Control of Non Safety Related (NSR) and Safety related (SR) systems. However, the safety system logics are still relay based. The experience on the deployment of PLC system, which is computer-based, has brought out various implementation issues. This paper give details of such experiences, the solutions emerged and applied for plants under operation/construction. (author)

Fuzzy Concurrent Object Oriented Expert System for Fault Diagnosis in 8085 Microprocessor Based System Board

OpenAIRE

Mr.D. V. Kodavade; Dr. Mrs.S.D.Apte

2014-01-01

With the acceptance of artificial intelligence paradigm, a number of successful artificial intelligence systems were created. Fault diagnosis in microprocessor based boards needs lot of empirical knowledge and expertise and is a true artificial intelligence problem. Research on fault diagnosis in microprocessor based system boards using new fuzzy-object oriented approach is presented in this paper. There are many uncertain situations observed during fault diagnosis. These uncertain situations...

Failure analysis on false call probe pins of microprocessor test equipment

Science.gov (United States)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

Three-valued logics in modal logic

NARCIS (Netherlands)

Kooi, Barteld; Tamminga, Allard

2013-01-01

Every truth-functional three-valued propositional logic can be conservatively translated into the modal logic S5. We prove this claim constructively in two steps. First, we define a Translation Manual that converts any propositional formula of any three-valued logic into a modal formula. Second, we

A Modular Approach to Arithmetic and Logic Unit Design on a Reconfigurable Hardware Platform for Educational Purpose

Science.gov (United States)

Oztekin, Halit; Temurtas, Feyzullah; Gulbag, Ali

The Arithmetic and Logic Unit (ALU) design is one of the important topics in Computer Architecture and Organization course in Computer and Electrical Engineering departments. There are ALU designs that have non-modular nature to be used as an educational tool. As the programmable logic technology has developed rapidly, it is feasible that ALU design based on Field Programmable Gate Array (FPGA) is implemented in this course. In this paper, we have adopted the modular approach to ALU design based on FPGA. All the modules in the ALU design are realized using schematic structure on Altera's Cyclone II Development board. Under this model, the ALU content is divided into four distinct modules. These are arithmetic unit except for multiplication and division operations, logic unit, multiplication unit and division unit. User can easily design any size of ALU unit since this approach has the modular nature. Then, this approach was applied to microcomputer architecture design named BZK.SAU.FPGA10.0 instead of the current ALU unit.

Towards a Formal Occurrence Logic based on Predicate Logic

DEFF Research Database (Denmark)

Badie, Farshad; Götzsche, Hans

2015-01-01

In this discussion we will concentrate on the main characteristics of an alternative kind of logic invented by Hans Götzsche: Occurrence Logic, which is not based on truth functionality. Our approach is based on temporal logic developed and elaborated by A. N. Prior. We will focus on characterising...... argumentation based on formal Occurrence Logic concerning events and occurrences, and illustrate the relations between Predicate Logic and Occurrence Logic. The relationships (and dependencies) is conducive to an approach that can analyse the occurrences of ”logical statements based on different logical...... principles” in different moments. We will also conclude that the elaborated Götzsche’s Occurrence Logic could be able to direct us to a truth-functional independent computer-based logic for analysing argumentation based on events and occurrences....

Use of a microprocessor in a remote working level monitor

International Nuclear Information System (INIS)

Keffe, D.J.; McDowell, W.P.; Groer, P.G.

1975-01-01

A remote working level monitor was designed to measure short-lived radon-daughter concentrations in sealed chambers having potentially high radiation levels (up to 2000 WL). The system is comprised of surface barrier detectors, multiplexer and buffers, microprocessor and teletype

Environmental qualification and functional issues for microprocessor-based reactor protection systems

International Nuclear Information System (INIS)

Korsah, K.; Kisner, R.; Wood, R.T.; Antonescu, C.

1992-01-01

Issues of obsolescence and lack of intrastructural support in (analog) spare parts, coupled with the potential benefits of digital systems, are driving the nuclear industry to retrofit analog instrumentation and control (I ampersand C) systems with digital and microprocessor-based systems. This movement away from analog can be expected to increase in advanced light-water reactors (ALWRs), which will make extensive use of fiber optic transmission, multiplexing techniques, and microprocessor-based technology. Although these technologies have several advantages and, in fact, have been in widespread use in the non-nuclear industry for several years, their application to safety-related systems in nuclear power plants raises key issues relating to the systems' environmental and functional reliability. For example, does the new hardware introduce additional system aging degradation mechanisms that could adversely impact the safety of the plant? Do the systems introduce the possibility of new and different malfunction scenarios or increase the probability of common-mode failures that could reduce the reliability of the safety system?. Are current environmental qualification standards adequate for microprocessor-based I ampersand C systems? Accordingly in 1991 the Nuclear Regulatory Commission (NRC) initiated the qualification of advanced Instrumentation and Control Systems program at ORNL to investigate issues that may arise with the use of advanced digital I ampersand C in ALWRs. The results of our studies to date are summarized in this paper

Microprocessor based data acquisition system for Moessbauer spectrometer

International Nuclear Information System (INIS)

Patwardhan, P.K.; Indurkar, V.S.

1981-01-01

A data acquisition system, for Moessbauer spectrometer and other probability distribution spectrum is described. This utilizes the advantages of incorporating a microcomputer for providing a flexible analytical capability and speed of hard wired MCS unit updating channel contents in DMA. Holbourn, Player and Woodhams have recently described a microprocessor controlled Moessbauer spectrometer where microprocessor performs the task of updating channel contents, requiring about 60 micro seconds in interrupt mode. This imposes restrictions on increasing the channel number and on increasing the velocity scan frequency in order to cover higher velocity ranges. The system described in this article performs data acquisition in faster direct memory access. It is a two module system, (1) MCS module (2) Microcomputer module, arranged around a common address, data and control buses. The microcomputer module has an access to the system data during flyback periods and can be programmed for the task of monitor on progess of experiment and as a manipulator of various control operations needed during experiment. The system firmware includes: (1) MONITOR (2) BLOCK-TRANSFER (3) DATA-SMOOTHING (4) DECIMAL-CONVERTER (5) MATH. The scope of this firmware is briefly described. (author)

Logic programming extensions of Horn clause logic

Directory of Open Access Journals (Sweden)

Ron Sigal

1988-11-01

Full Text Available Logic programming is now firmly established as an alternative programming paradigm, distinct and arguably superior to the still dominant imperative style of, for instance, the Algol family of languages. The concept of a logic programming language is not precisely defined, but it is generally understood to be characterized buy: a declarative nature; foundation in some well understood logical system, e.g., first order logic.

Distributed microprocessor automation network for synthesizing radiotracers used in positron emission tomography

International Nuclear Information System (INIS)

Russell, J.A.G.; Alexoff, D.L.; Wolf, A.P.

1984-01-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. 20 refs. (DT)

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

A measurement of cosmic-ray LET-spectra using a microprocessor supported microscope

International Nuclear Information System (INIS)

Beer, J.; Heinrich, W.

1982-01-01

A microprocessor supported semi-automatic system for measurements of nuclear tracks in plastic detectors is presented. It consists of a microscope and a stepping motor driven stage. A Motorola microprocessor MC 6800 controls the measurement. It accepts the co-ordinates of the stage as well as the position of the focus and computes cone length and dip angle from the three-dimensional co-ordinates. LET-spectra were measured from two cellulose nitrate foils of the Biostack III experiment flown with the Apollo-Soyus-Test-Project in 1975. One of these foils was shielded by 3 g/cm 2 and the other one by 15 g/cm 2 . The two spectra show no statistically significant decrease of intensity. (author)

Intuitionistic hybrid logic

DEFF Research Database (Denmark)

Braüner, Torben

2011-01-01

Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Science.gov (United States)

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17...: END-USER AND END-USE BASED § 744.17 Restrictions on certain exports and reexports of general purpose microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the...

Technology transfer of military space microprocessor developments

Science.gov (United States)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

D0 General Support: The Use of Programmable Logic Controllers (PLCs) at D0

International Nuclear Information System (INIS)

Hance, R.

2000-01-01

With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

High speed serial link for UA1 microprocessor network

International Nuclear Information System (INIS)

Cittolin, S.; Loefstedt, B.; Zurfluh, E.

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment rest/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system it is running as an ancillary serial loop-link between microprocessors Like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. The Chip MC-6854 from Motorola, Inc. enables an implementation with few components. (orig.)

Classical logic and logicism in human thought

OpenAIRE

Elqayam, Shira

2012-01-01

This chapter explores the role of classical logic as a theory of human reasoning. I distinguish between classical logic as a normative, computational and algorithmic system, and review its role is theories of human reasoning since the 1960s. The thesis I defend is that psychological theories have been moving further and further away from classical logic on all three levels. I examine some prominent example of logicist theories, which incorporate logic in their psychological account, includin...

Microprocessor architectures RISC, CISC and DSP

CERN Document Server

Heath, Steve

1995-01-01

'Why are there all these different processor architectures and what do they all mean? Which processor will I use? How should I choose it?' Given the task of selecting an architecture or design approach, both engineers and managers require a knowledge of the whole system and an explanation of the design tradeoffs and their effects. This is information that rarely appears in data sheets or user manuals. This book fills that knowledge gap.Section 1 provides a primer and history of the three basic microprocessor architectures. Section 2 describes the ways in which the architectures react with the

A Digitally Programmable Differential Integrator with Enlarged Time Constant

Directory of Open Access Journals (Sweden)

S. K. Debroy

1994-12-01

Full Text Available A new Operational Amplifier (OA-RC integrator network is described. The novelties of the design are used of single grounded capacitor, ideal integration function realization with dual-input capability and design flexibility for extremely large time constant involving an enlargement factor (K using product of resistor ratios. The aspect of the digital control of K through a programmable resistor array (PRA controlled by a microprocessor has also been implemented. The effect of the OA-poles has been analyzed which indicates degradation of the integrator-Q at higher frequencies. An appropriate Q-compensation design scheme exhibiting 1 : |A|2 order of Q-improvement has been proposed with supporting experimental observations.

Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

Science.gov (United States)

Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

1984-09-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

Tests of microprocessor-based relay protection devices: Problems and solutions

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2009-01-01

Full Text Available Usually, the operational condition of relay protection devices is checked with specific settings used for the relay operation in a certain network point. In the author's opinion in order to verify the proper operation of complex multifunctional microprocessor-based protection devices (MPD at their inspection, start-up after repairs or during periodic tests there is no need to use the actual settings at which the relay is to be operated in a certain network's point. It should be tested for proper operation at several of its most critical preset characteristic points as well as in several preset characteristics constituting its most complicated (combined operation modes, including the dynamic operation modes with preset transition processes specific for standard power networks (not necessarily for a specific point. The proposed set of actions for the unification of software platforms of the modern, microprocessor-based relay protection test systems will enable examination of modern MPD in an absolutely new way. .

The REGENT-PLR-precompiler, execution logic

International Nuclear Information System (INIS)

Enderle, G.; Steil, A.

1976-11-01

The REGENT-PLR-Precompiler is part of the integrated CAD-system REGENT. The algorithms of REGENT-subsystems are contained in modular program units, modules. Beyond the possibilities of the base language PL/1 the programmer of the moduls can be use the REGENT-facilities; dynamic program linkage, dynamic data management and error message handling. For easy and safe use of these facilities they are realized as PL/1-extensions. The PLR-Precompiler is able to translate the extensions into PL/1. This report contains a description of the internal program logic of the REGENT-PLR-Precompiler. (orig.) [de

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

CERN Document Server

Becam, C; Delanghe, J; Fest, H M; Lecoq, J; Martin, H; Mencik, M; MerkeI, B; Meyer, J M; Perrin, M; Plothow, H; Rampazzo, J P; Schittly, A

1981-01-01

The bit slice micro-processor GESPRO is a CAMAC module plugged into a standard Elliot system crate via which it communicates as a slave with its host computer. It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine with multi-mode memory addressing capacity of 64K words. The micro-processor structure uses 5 buses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2K (RAM) words of 48 bits each. A special hardwired module allows floating point, as well as integer, multiplication of 24*24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: (a) online data reduction, i.e. to read DURANDAL, process the information resulting in accepting or rejecting the event; (b) readout and analysis of the accepted data; (c) preprocess the data. The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hard...

Microprocessor system for data acquisition and processing for the Flora device

International Nuclear Information System (INIS)

Klimov, V.M.

1986-01-01

''VEhFORMIKA'' microprocessor system for data collection and processing when conducting experiments at the ''Flora'' device is described, its application is grounded. The complex allows one to conduct investigations using multichannel methods and exercise the device electrophysical control

Integrated development environment for fuzzy logic applications

Science.gov (United States)

Pagni, Andrea; Poluzzi, Rinaldo; Rizzotto, GianGuido; Lo Presti, Matteo

1993-12-01

During the last five years, Fuzzy Logic has gained enormous popularity, both in the academic and industrial worlds, breaking up the traditional resistance against changes thanks to its innovative approach to problems formalization. The success of this new methodology is pushing the creation of a brand new class of devices, called Fuzzy Machines, to overcome the limitations of traditional computing systems when acting as Fuzzy Systems and adequate Software Tools to efficiently develop new applications. This paper aims to present a complete development environment for the definition of fuzzy logic based applications. The environment is also coupled with a sophisticated software tool for semiautomatic synthesis and optimization of the rules with stability verifications. Later it is presented the architecture of WARP, a dedicate VLSI programmable chip allowing to compute in real time a fuzzy control process. The article is completed with two application examples, which have been carried out exploiting the aforementioned tools and devices.

Logical labyrinths

CERN Document Server

Smullyan, Raymond

2008-01-01

This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T

Development of an FPGA-based controller for safety critical application

International Nuclear Information System (INIS)

Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

2011-01-01

In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

Science.gov (United States)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.

Science.gov (United States)

Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai

2017-08-02

Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

Science.gov (United States)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

What makes children behave aggressively? The inner logic of Dutch children in special education

NARCIS (Netherlands)

Visser, M.; Singer, E.; van Geert, P.L.C.; Kunnen, S.E.

2009-01-01

The ambiguous results of existing intervention programmes show the need for new ways in research on aggression among children. The present study focuses on the children's own perspective on their aggressive behaviour. Based on a constructivist approach, the inner logic of narratives about peer

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

Science.gov (United States)

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

CAMAC multipurpose microprocessor controller

International Nuclear Information System (INIS)

Belyakova, M.P.; Nemesh, T.; Buj Zoan Chong.

1978-01-01

The use of CAMAC controllers in an autonomous system of data acquisition and measurement is considered. The system consists of a control intelligence controller, memory modules, and user modules in the CAMAC standard. The controller and all the modules have an output into the highway and this permits to exchange data among them without using special external cables. To increase the servicing rate, an auxiliary controller which has direct access to memory and controls the user modules, is additionally connected to the data acquisition and measurement system. In this case, the intelligence controller is passive. The system of data acquisition can be realized in the form of a multiple system with branch usage. The controller module width is three units, and the controller incorporates the Intel-8080-type microprocessor and the following interfaces: of CAMAC highways, of interruption, of memory bootstrap, and of data sequence channel

Small Private Key PKS on an Embedded Microprocessor

OpenAIRE

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor...

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

Science.gov (United States)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Sectional microprocessor based microcomputer and its application to express analysis using interactive language

International Nuclear Information System (INIS)

Lang, I.; Leveleki, L.; Salai, M.; Turani, D.

1984-01-01

Sectional microprocessor TPA-L/128H based mini-computer being a part of the TPA-8 computer family is developed. A substantial increase of the computer operation rate is attained at the expense of microprogram monitoring. The central processor is constructed on the base of the AM2900 sectional microprocessor elements. The TPA-L/128H computer is program compatible with TPA-8 computer, perfectly equipped with software: high level languages as well as OS/L, COS/H, RTS/H, PAL/128, WPS, TEASYS-8 and IL 128 ensuring statistical data processing, physical experiments automation and interactive experimental data processing. The real time basis problems and CAMAC devices monitoring are efficiently solved

Design of microprocessor data acquisition system for pedestrian portal SNM monitor

International Nuclear Information System (INIS)

Zhang Wenliang

2003-01-01

The paper introduces the hardware structure and composition of data acquisition system for pedestrian portal special nuclear material (SNM) monitor. The hardware and software of single chip microprocessor AT89C52, LCM, keyboard and serial communication interface software are also discussed. (authors)

A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

Science.gov (United States)

Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

2016-06-28

Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

A microprocessor controlled read out system for drift chambers

CERN Document Server

Centro, Sandro; Cittolin, Sergio; Dreesen, P; Petrolo, E; Rubbia, Carlo; Schinzel, D

1981-01-01

Summary form only given, as follows. A General Purpose Microprocessor Controller GPMC has been developed for applications where CAMAC modules with complex control functions are needed. Each application requires an appropriate Interface Module (IM) to be connected to the GPMC. The GPMC consists of a 6800 Microprocessor, 16K EPROM, 2K RAM, CAMAC I/O ports and interface, a RS 232C serial interface, an Advanced Data Link controller and a port for controlling the IM, GPMC and IM are housed in a 2-U wide CAMAC module. A special IM has been designed, which has 1K bute of RAM with its own control and which allows autonomous setting and reading analog voltages through a DAC and ADC. The GPMC can take control of the IM memory and set new voltages. This system is used to control pedestals and gains of a driftchamber readout system, which is housed in a 5-U wide CAMAC module, holding 24 data cards corresponding to 24 sense wires. The data card receives pulses from the left and right end of a sense wire, amplifies and int...

Application of microprocessor based controller in the Breeder Reactor Program

International Nuclear Information System (INIS)

Messick, N.C.; Lukas, M.P.

1985-01-01

This paper treats Argonne National Laboratory's experience using microprocessor based controllers presently in use on several control loops within the EBR-II reactor facility as well as tests being performed by these controllers. Also included is a discussion of the expandability, modularity, range of capabilities and higher level functions possible using such equipment

The JOSHUA (J80) system programmer`s manual

Energy Technology Data Exchange (ETDEWEB)

Smetana, A.O.; McCort, J.T.; Westmoreland, B.W.

1993-08-01

The JOSHUA system routines (JS routines) can be used to manage a JOSHUA data base and execute JOSHUA modules on VAX/VMS and IBM/MVS computer systems. This manual provides instructions for using the JS routines and information about the internal data structures and logic used by the routines. It is intended for use primarily by JOSHUA systems programmers, however, advanced applications programmers may also find it useful. The JS routines are, as far as possible, written in ANSI FORTRAN 77 so that they are easily maintainable and easily portable to different computer systems. Nevertheless, the JOSHUA system provides features that are not available in ANSI FORTRAN 77, notably dynamic module execution and a data base of named, variable length, unformatted records, so some parts of the routines are coded in nonstandard FORTRAN or assembler (as a last resort). In most cases, the nonstandard sections of code are different for each computer system. To make it easy for programmers using the JS routines to avoid naming conflicts, the JS routines and common block all have six character names that begin with the characters {open_quotes}JS.{close_quotes} Before using this manual, one should be familiar with the JOSHUA system as described in {open_quotes}The JOSHUA Users` Manual,{close_quotes} ANSI FORTRAN 77, and at least one of the computer systems for which the JS routines have been implemented.

Integrated evaluation framework. Based on the logical framework approach for project cycle management

International Nuclear Information System (INIS)

1996-11-01

This Integrated Evaluation Framework (IEF) was developed by TC Evaluation with the aim of presenting in a comprehensive manner the logic of thinking used when evaluating projects and programmes. Thus, in the first place, the intended audience for this report are evaluation officers, so that when applying the evaluation procedures and check lists, data can be organized following a systematic and logical scheme and conclusions can be derived ''objectively''. The value of such a framework for reporting on performance and in providing a quality reference for disbursements represents one of its major advantages. However, when developing and applying the IEF, it was realized that a Logical Framework Approach (LFA), like the one upon which the IEF is based, needs to be followed throughout the project life cycle, from the Country Programme Framework planning stage, through project design and implementation. Then, the helpful consequences flow into project design quality and smooth implementation. It is only in such an environment that meaningful and consistent evaluation can take place. Therefore the main audience for this report are Agency staff involved in planning, designing and implementing TC projects as well as their counterparts in Member States. In this understanding, the IEF was subjected to review by a consultants meeting, which included both external consultants and Agency staff. This Consultants Review Meeting encouraged the Secretariat to further adopt the LFA into the TC management process

Front-end data processing using the bit-sliced microprocessor

International Nuclear Information System (INIS)

Machen, D.R.

1979-01-01

A state-of-the-art computing device, based upon the high-speed bit-sliced microprocessor, was developed into hardware for front-end data processing in both control and experiment applications at the Los Alamos Scientific Laboratory. The CAMAC Instrumentation Standard provides the framework for the high-speed hardware, allowing data acquisition and processing to take place at the data source in a CAMAC crate. 5 figures

Overview of real-time operating systems on microprocessor platforms

International Nuclear Information System (INIS)

Luong, T.T.

1994-01-01

This paper attempts to overview the real-time operating systems on microprocessor platforms in the field of experimental physics facility controls. The key issues regarding operating systems as well as standards and development environment are discussed. As an illustration, some current industrial products are indicated. Also, real-time systems operating in some institutes of the EPS/EPCS inter divisional group are reviewed. (author). 3 refs., 4 figs

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

A microprocessor based multiscaling data acquisition system for moessbauer spectroscopy

International Nuclear Information System (INIS)

Bohm, C.; Ekdahl, T.

1985-01-01

A microprocessor based data acquisition system is described, which was developed for use in Moessbauer spectroscopy. It is designed to record two spectra simultaneously, one of which could be a calibration spectrum. It is autonomous, but uses a host computer for initialization and permanent storage of data. The host communication software is also described. (Author)

Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs

Directory of Open Access Journals (Sweden)

Victoria A. Church

2017-09-01

Full Text Available The cellular abundance of mature microRNAs (miRNAs is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor’s differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb. When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association.

Saturday Programme for CineGlobe

CERN Multimedia

Marcelloni De Oliveira, Claudia

2015-01-01

The saturday programme had a special kids session, the kick of the Science Storytelling Hackaton and the Award Ceremony WINNERS 2015 The Jury Prize for documentary: Fecal Matters, Paul Gallasch - AU The Jury Prize for Fiction: Hybris, Arjan Brentjes - NL Award of Excellence in Narrative: Final Draft, Scott Calonico - UK The Audience Award for documentary: Logically policed, Damiano Petrucci - UK The Audience Award for Fiction: Slapkick, Dat Nguyen Chon-- DE The Special Prize "Time Vizualisation": Danielle, Anthony Cerniello - US

Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Directory of Open Access Journals (Sweden)

Ching-Hwa Cheng

2013-01-01

Full Text Available The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar microprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor's performance. However, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most past architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function units. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the instruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard prevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the start of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and less power consumption compared to the conventional hazard prevention technique.

Programmable full-adder computations in communicating three-dimensional cell cultures.

Science.gov (United States)

Ausländer, David; Ausländer, Simon; Pierrat, Xavier; Hellmann, Leon; Rachid, Leila; Fussenegger, Martin

2018-01-01

Synthetic biologists have advanced the design of trigger-inducible gene switches and their assembly into input-programmable circuits that enable engineered human cells to perform arithmetic calculations reminiscent of electronic circuits. By designing a versatile plug-and-play molecular-computation platform, we have engineered nine different cell populations with genetic programs, each of which encodes a defined computational instruction. When assembled into 3D cultures, these engineered cell consortia execute programmable multicellular full-adder logics in response to three trigger compounds.

Raising a Programmer: Teaching Saudi Children How to Code

Science.gov (United States)

Meccawy, Maram

2017-01-01

Teaching computer coding to children from a young age provides with them a competitive advantage for the future in a continually changing workplace. Programming strengthens logical and critical thinking as well as problem-solving skills, which lead to creative solutions for today's problems. The Little Programmer is an application for mobile…

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

Directory of Open Access Journals (Sweden)

E.A. Ramadan

2014-09-01

Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

Logical Characterisation of Ontology Construction using Fuzzy Description Logics

DEFF Research Database (Denmark)

Badie, Farshad; Götzsche, Hans

had the extension of ontologies with Fuzzy Logic capabilities which plan to make proper backgrounds for ontology driven reasoning and argumentation on vague and imprecise domains. This presentation conceptualises learning from fuzzy classes using the Inductive Logic Programming framework. Then......, employs Description Logics in characterising and analysing fuzzy statements. And finally, provides a conceptual framework describing fuzzy concept learning in ontologies using the Inductive Logic Programming....

Architecture of 32 bit CISC (Complex Instruction Set Computer) microprocessors

International Nuclear Information System (INIS)

Jove, T.M.; Ayguade, E.; Valero, M.

1988-01-01

In this paper we describe the main topics about the architecture of the best known 32-bit CISC microprocessors; i80386, MC68000 family, NS32000 series and Z80000. We focus on the high level languages support, operating system design facilities, memory management, techniques to speed up the overall performance and program debugging facilities. (Author)

Digital Fractional Order Controllers Realized by PIC Microprocessor: Experimental Results

OpenAIRE

Petras, I.; Grega, S.; Dorcak, L.

2003-01-01

This paper deals with the fractional-order controllers and their possible hardware realization based on PIC microprocessor and numerical algorithm coded in PIC Basic. The mathematical description of the digital fractional -order controllers and approximation in the discrete domain are presented. An example of realization of the particular case of digital fractional-order PID controller is shown and described.

Microprocessor controlled dual parameter ADC system with a CAMAC interface

Energy Technology Data Exchange (ETDEWEB)

Perry, D G; Nickell, Jr, J D [Los Alamos Scientific Lab., NM (USA)

1978-09-01

Presented here is the design of a dual parameter ADC system which is controlled by a microprocessor and also interfaced to CAMAC. The system was designed to be mobile in that it may work wherever there is a CAMAC crate. In such cases where the CAMAC system is inoperative, the system may operate in a stand-alone mode.

Manipulating potential wells in Logical Stochastic Resonance to obtain XOR logic

International Nuclear Information System (INIS)

Storni, Remo; Ando, Hiroyasu; Aihara, Kazuyuki; Murali, K.; Sinha, Sudeshna

2012-01-01

Logical Stochastic Resonance (LSR) is the application of Stochastic Resonance to logic computation, namely the phenomenon where a nonlinear system driven by weak signals representing logic inputs, under optimal noise, can yield logic outputs. We extend the existing results, obtained in the context of bistable systems, to multi-stable dynamical systems, allowing us to obtain XOR logic, in addition to the AND (NAND) and OR (NOR) logic observed in earlier studies. This strategy widens the scope of LSR from the application point of view, as XOR forms the basis of ubiquitous bit-by-bit addition, and conceptually, showing the ability to yield non-monotonic input–output logic associations. -- Highlights: ► We generalize Logical Stochastic Resonance from bistable to multi-stable systems. ► We propose a tristable dynamical system formed of piecewise linear functions. ► The system can correctly reproduce XOR logic behavior using the LSR principle. ► The system yields different logic behavior without the need to change the dynamics.

Classical Mathematical Logic The Semantic Foundations of Logic

CERN Document Server

Epstein, Richard L

2011-01-01

In Classical Mathematical Logic, Richard L. Epstein relates the systems of mathematical logic to their original motivations to formalize reasoning in mathematics. The book also shows how mathematical logic can be used to formalize particular systems of mathematics. It sets out the formalization not only of arithmetic, but also of group theory, field theory, and linear orderings. These lead to the formalization of the real numbers and Euclidean plane geometry. The scope and limitations of modern logic are made clear in these formalizations. The book provides detailed explanations of all proo

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

Science.gov (United States)

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Applications of microprocessors in upgrading of accelerator controls

International Nuclear Information System (INIS)

Mallory, K.B.

1977-03-01

Experience at SLAC demonstrates that the criteria for selection and use of microprocessors in modifying an existing control system may differ from the criteria that apply during installation of the control system of a new accelerator. Considerations such as cost of individual projects, progressive installation without disruption of operations and training of on-board personnel can outweigh ''obvious'' goals such as standardization of hardware, uniformity of software, or even a rigid specification of link protocols with the main computer system

Transforming equality logic to propositional logic

NARCIS (Netherlands)

Zantema, H.; Groote, J.F.

2003-01-01

Abstract We investigate and compare various ways of transforming equality formulas to propositional formulas, in order to be able to solve satisfiability in equality logic by means of satisfiability in propositional logic. We propose equality substitution as a new approach combining desirable

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

Science.gov (United States)

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

System architecture for microprocessor based protection system

International Nuclear Information System (INIS)

Gallagher, J.M. Jr.; Lilly, G.M.

1976-01-01

This paper discusses the architectural design features to be employed by Westinghouse in the application of distributed digital processing techniques to the protection system. While the title of the paper makes specific reference to microprocessors, this is only one (and the newest) of the building blocks which constitutes a distributed digital processing system. The actual system structure (as realized through utilization of the various building blocks) is established through considerations of reliability, licensability, and cost. It is the intent of the paper to address these considerations licenstions as they relate to the architectural design features. (orig.) [de

Logic and Ontology

Directory of Open Access Journals (Sweden)

Newton C. A. da Costa

2002-12-01

Full Text Available In view of the present state of development of non classical logic, especially of paraconsistent logic, a new stand regarding the relations between logic and ontology is defended In a parody of a dictum of Quine, my stand May be summarized as follows. To be is to be the value of a variable a specific language with a given underlying logic Yet my stand differs from Quine’s, because, among other reasons, I accept some first order heterodox logics as genuine alternatives to classical logic I also discuss some questions of non classical logic to substantiate my argument, and suggest that may position complements and extends some ideas advanced by L Apostel.

Structural Logical Relations

DEFF Research Database (Denmark)

Schürmann, Carsten; Sarnat, Jeffrey

2008-01-01

Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics......, such as Twelf, and yet they are often straightforward in proof assistants with stronger meta-logics. In this paper, we propose structural logical relations as a technique for conducting these proofs in systems with limited meta-logical strength by explicitly representing and reasoning about an auxiliary logic...

Multi-purpose logical device with integrated circuit for the automation of mine water disposal

Energy Technology Data Exchange (ETDEWEB)

Pop, E.; Pasculescu, M.

1980-06-01

After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

Upgrading of Alum Preparation and Dosing Unit for Sharq Dijla Water Treatment Plant by Using Programmable Logic Controller System

Directory of Open Access Journals (Sweden)

Aumar Al-Nakeeb

2018-02-01

Full Text Available One of the important units in Sharq Dijla Water Treatment Plant (WTP first and second extensions are the alum solution preparation and dosing unit. The existing operation of this unit accomplished manually starting from unloading the powder alum in the preparation basin and ending by controlling the alum dosage addition through the dosing pumps to the flash mix chambers. Because of the modern trend of monitoring and control the automatic operation of WTPs due to the great benefits that could be gain from optimum equipment operation, reducing the operating costs and human errors. This study deals with how to transform the conventional operation to an automatic monitoring and controlling system depending on a Programmable Logic Controller (PLC and online sensors for alum preparation and dosing unit in Sharq Dijla WTP. PLC system will receive, analyze transmitting data, compare them with preset points then automatically orders the operational equipment (such as pumps, valves, and mixers in a way that guarantees the safe and appropriate operation of the unit. As a result of Process and Instrumentation Diagrams (PID that were prepared in this study, these units can be fully operating and manage by using Supervisory Control and Data Acquisition (SCADA system.

Reliability of microprocessor-based relay protection devices: Myths and reality

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2009-01-01

Full Text Available The article examines four basic theses about the ostensibly extremely high reliability of microprocessor-based relay protection (MP touted by supporters of MP. Through detailed analysis based on many references it is shown that the basis of these theses are widespread myths, and actually MP reliability is lower than the reliability of electromechanical and electronic protective relays on discrete components.

Unified microprocessor CAMAC module for preliminary data processing

International Nuclear Information System (INIS)

Zaushitsin, V.L.; Kulik, O.V.; Repin, V.M.

1984-01-01

The UP-80 unified active module is described. It is made in the CAMAC standard on the base of the K580IK80 microprocessor allowing to increase the rate of large-volume experimental spectroscopic data processing by an order. Loading of 5 different programs for data processing is possible. Data from the operative storage with 1K capacity (8 bits) are recorded and read out trhough the CAMAC line (the regime of unit exchange is possible) or through the joint of the external line

BDI Logics

NARCIS (Netherlands)

Meyer, J.J.Ch.; Broersen, J.M.; Herzig, A.

2015-01-01

This paper presents an overview of so-called BDI logics, logics where the notion of Beliefs, Desires and Intentions play a central role. Starting out from the basic ideas about BDI by Bratman, we consider various formalizations in logic, such as the approach of Cohen and Levesque, slightly

Many-valued logics

CERN Document Server

Bolc, Leonard

1992-01-01

Many-valued logics were developed as an attempt to handle philosophical doubts about the "law of excluded middle" in classical logic. The first many-valued formal systems were developed by J. Lukasiewicz in Poland and E.Post in the U.S.A. in the 1920s, and since then the field has expanded dramatically as the applicability of the systems to other philosophical and semantic problems was recognized. Intuitionisticlogic, for example, arose from deep problems in the foundations of mathematics. Fuzzy logics, approximation logics, and probability logics all address questions that classical logic alone cannot answer. All these interpretations of many-valued calculi motivate specific formal systems thatallow detailed mathematical treatment. In this volume, the authors are concerned with finite-valued logics, and especially with three-valued logical calculi. Matrix constructions, axiomatizations of propositional and predicate calculi, syntax, semantic structures, and methodology are discussed. Separate chapters deal w...

New Design Concept for Universal CCD Controller

Directory of Open Access Journals (Sweden)

Wonyong Han

1994-06-01

Full Text Available Currently, the CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However according to the recent technical advances, new large format CCDs are rapidly developed which have better performances with higher quantum efficiency and sensitivity. In many cases, some microprocessors have been adopted to deal with necessary digital logic for a CCD imaging system. This could often lack the flexibility of a system for a user to upgrade with new devices, especially of it is a commercial product. A new design concept has been explored which could provide the opportunity to deal with any format of devices from ant manufactures effectively for astronomical purposes. Recently available PLD (Programmable Logic Devices technology makes it possible to develop such digital circuit design, which can be integrated into a single component, instead of using microprocessors. The design concept could dramatically increase the efficiency and flexibility of a CCD imaging system, particularly when new or large format devices are available and to upgrade the performance of a system. Some variable system control parameters can be selected by a user with a wider range of choice. The software can support such functional requirements very conveniently. This approach can be applied not only to astronomical purpose, but also to some related fields, such as remote sensing and industrial applications.

Practical programmable circuits a guide to PLDs, state machines, and microcontrollers

CERN Document Server

Broesch, James D

1991-01-01

This is a practical guide to programmable logic devices. It covers all devices related to PLD: PALs, PGAs, state machines, and microcontrollers. Usefulness is evaluated; support needed in order to effectively use the devices is discussed. All examples are based on real-world circuits.

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

Quantum Logic as a Dynamic Logic

NARCIS (Netherlands)

Baltag, A.; Smets, S.

We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear “no”.

Quantum logic as a dynamic logic

NARCIS (Netherlands)

Baltag, Alexandru; Smets, Sonja

We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear "no".

Product Lukasiewicz Logic

Czech Academy of Sciences Publication Activity Database

Horčík, Rostislav; Cintula, Petr

2004-01-01

Roč. 43, - (2004), s. 477-503 ISSN 1432-0665 R&D Projects: GA AV ČR IAA1030004; GA ČR GA201/02/1540 Grant - others:GA CTU(CZ) project 0208613; net CEEPUS(SK) SK-042 Institutional research plan: CEZ:AV0Z1030915 Keywords : fuzzy logic * many-valued logic * Lukasiewicz logic * Lpi logic * Takeuti-Titani logic * MV-algebras * product MV-algebras Subject RIV: BA - General Mathematics Impact factor: 0.295, year: 2004

Against Logical Form

Directory of Open Access Journals (Sweden)

P N Johnson-Laird

2010-10-01

Full Text Available An old view in logic going back to Aristotle is that an inference is valid in virtue of its logical form. Many psychologists have adopted the same point of view about human reasoning: the first step is to recover the logical form of an inference, and the second step is to apply rules of inference that match these forms in order to prove that the conclusion follows from the premises. The present paper argues against this idea. The logical form of an inference transcends the grammatical forms of the sentences used to express it, because logical form also depends on context. Context is not readily expressed in additional premises. And the recovery of logical form leads ineluctably to the need for infinitely many axioms to capture the logical properties of relations. An alternative theory is that reasoning depends on mental models, and this theory obviates the need to recover logical form.

Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

Science.gov (United States)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

Design and Simulation of Automatic Ballast System on Catamaran Ship Based on Programmable Logic Control

Directory of Open Access Journals (Sweden)

Indra Ranu Kusuma

2017-06-01

Full Text Available Characteristics of catamaran ship which has deficiency to ship stability during maneuvering. to that end, this paper concerns about ballast system design in support of the safety and comfort of passengers on the catamaran boat. the discussion is done by creating a mathematical model of each component in the block diagram of the ballast system. then determine the pid value of the system and add the compensator for the system to run stable. further analyzed with the help of matlab software to get transient system response. with the automation system on the ballast system, it is expected that the motion of the ship can work automatically and provide a better response in the stability of the catamaran type ship. the ballast system begins to work against the tilt of the ship at 6.7 seconds at a certain angle, and will continue to work during the vessel maneuvering. judging from the 6.7 second system response time, the convenience of the passengers is not disturbed (the system response is not too fast. one way to reduce the rolling that occurs on the ship is to optimize the performance of the ballast system. performance optimization is done by using programmable logic controller (plc. plc used is omron cpm1a-30cdr-a-v1. the process is done by making the installation plant model of the ballast system as a control medium. followed by creating a control circuit consisting of wiring i / o, limit switch circuits, power supplies and programming languages associated with plcs. the result of the control is expected to regulate fluid flow in the ballast system automatically resulting in a rapid response to the stability of the ship.

The use of distributed microprocessors for control devices

International Nuclear Information System (INIS)

Lejon, J.C.

1978-01-01

The use of distributed individual microprocessors provided the basis for the development of the μZ system, which is a modular numerical control device which in its main part contains no elements whatever with multiple functions. With this system, total availability of control is achieved and the failure of any individual element causes loss of automatic control only over one actuator or over a small group of interdependent actuators. The human operator, who cannot be omitted even with an inherently safe control system, can operate the single faulty channel manually. The microprocessors have a free-format with which all possible algorithms within the limits of the memory size of the various cards can be performed. This program can be loaded either in random access memory (RAM) or in read-only memory (ROM). The configuration is made either by assembling software modules in a hard-copy dialogue without any knowledge of data processing being necessary, or from a program written in Fortran. If the user does not have a configurator he can use read-only memories supplied by the manufacter either in the standard form or in a requested design. The parameters are loaded by means of a portable microconsole whose keyboard and displays can be used for a hard-copy dialogue with the regulating cards. Manual control and indications can be carried out from three completely independent configurations which can be used separately or in parallel: individual station, multiple-function station or cathode colour console. (author)

Superconductor fluxoid logic

International Nuclear Information System (INIS)

Andronov, A.A.; Kurin, V.V.; Levichev, M.Yu.; Ryndyk, D.A.; Vostokov, V.I.

1993-01-01

In recent years there has been much interest in superconductor logical devices. Our paper is devoted to the analysis of some new possibilities in this field. The main problems here are: minimization of time of logical operations and reducing of device scale. Josephson systems are quite appropriate for this purpose because of small size, short characteristic time and also small energy losses. Two different types of Josephson logic have been investigated during last years. The first type is based on hysteretic V-A characteristic of a single Josephson junction. Superconducting and resistive (with nonzero voltage) states are considered as logical zero and logical unit. The second one - rapid single flux quantum logic, has been developed recently and is based on SQUID-like bistability. Different logical states are the states with different number of magnetic flux quanta inside closed superconducting contour. Information is represented by voltage pulses with fixed ''area'' (∫ V(t)/dt). This pulses are generated when logical state of SQUID-like elementary cell changes. The fundamental role of magnetic flux quantization in this type of logic leads to the necessity of large enough self-inductance of superconductor contour and thus to limitations on minimal device dimensions. (orig.)

Advances in Modal Logic

DEFF Research Database (Denmark)

Modal logic is a subject with ancient roots in the western logical tradition. Up until the last few generations, it was pursued mainly as a branch of philosophy. But in recent years, the subject has taken new directions with connections to topics in computer science and mathematics. This volume...... is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...... epistemic logic, and the logic of evidence....

Mathematical logic

CERN Document Server

Kleene, Stephen Cole

1967-01-01

Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.

Indeterministic Temporal Logic

Directory of Open Access Journals (Sweden)

Trzęsicki Kazimierz

2015-09-01

Full Text Available The questions od determinism, causality, and freedom have been the main philosophical problems debated since the beginning of temporal logic. The issue of the logical value of sentences about the future was stated by Aristotle in the famous tomorrow sea-battle passage. The question has inspired Łukasiewicz’s idea of many-valued logics and was a motive of A. N. Prior’s considerations about the logic of tenses. In the scheme of temporal logic there are different solutions to the problem. In the paper we consider indeterministic temporal logic based on the idea of temporal worlds and the relation of accessibility between them.

Microprocessors & their operating systems a comprehensive guide to 8, 16 & 32 bit hardware, assembly language & computer architecture

CERN Document Server

Holland, R C

1989-01-01

Provides a comprehensive guide to all of the major microprocessor families (8, 16 and 32 bit). The hardware aspects and software implications are described, giving the reader an overall understanding of microcomputer architectures. The internal processor operation of each microprocessor device is presented, followed by descriptions of the instruction set and applications for the device. Software considerations are expanded with descriptions and examples of the main high level programming languages (BASIC, Pascal and C). The book also includes detailed descriptions of the three main operatin

A fastbus master based on a risc microprocessor

International Nuclear Information System (INIS)

Cerrito, L.; Chorowicz, V.; Lebbolo, H.; Vallereau, A.

1990-01-01

SISIFUS is a general purpose Fastbus Master and Slave able to perform any operation on both Fastbus segments. Master operations are directed either by the processor or by two fast sequencers. A Block Mover function is implemented allowing direct data block transfers between two Slaves. SISIFUS uses the AM 29000 RISC microprocessor which can execute every assembler instruction in 40ns. The on-board monitor/debugger allows programs to be written in assembler from a terminal connected to the module or written in C and cross compiled on a host computer (PC)

Classical Logic and Quantum Logic with Multiple and Common Lattice Models

Directory of Open Access Journals (Sweden)

Mladen Pavičić

2016-01-01

Full Text Available We consider a proper propositional quantum logic and show that it has multiple disjoint lattice models, only one of which is an orthomodular lattice (algebra underlying Hilbert (quantum space. We give an equivalent proof for the classical logic which turns out to have disjoint distributive and nondistributive ortholattices. In particular, we prove that both classical logic and quantum logic are sound and complete with respect to each of these lattices. We also show that there is one common nonorthomodular lattice that is a model of both quantum and classical logic. In technical terms, that enables us to run the same classical logic on both a digital (standard, two-subset, 0-1-bit computer and a nondigital (say, a six-subset computer (with appropriate chips and circuits. With quantum logic, the same six-element common lattice can serve us as a benchmark for an efficient evaluation of equations of bigger lattice models or theorems of the logic.

Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

Science.gov (United States)

2014-06-19

Security Risks for Industrial Control Systems ,” VDE 2004 Congress, Berlin, Germany, October 2004, pp. 1-7. [Cis12] Cisco, NetFlow Configuration Guide...Date 29 May 2014 Date AFIT-ENG-T-14-J-4 Abstract Industrial Control Systems (ICS) remain vulnerable through attack vectors that exist within programmable...5 2.2 Industrial Control Systems

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

Science.gov (United States)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

Propositional Logics of Dependence

NARCIS (Netherlands)

Yang, F.; Väänänen, J.

2016-01-01

In this paper, we study logics of dependence on the propositional level. We prove that several interesting propositional logics of dependence, including propositional dependence logic, propositional intuitionistic dependence logic as well as propositional inquisitive logic, are expressively complete

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Science.gov (United States)

Le, Martin; Zheng, Xin; Katanyoutant, Sunant

2008-01-01

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state

Contracts for Cooperation between Web Service Programmers and HTML Designers

DEFF Research Database (Denmark)

Böttger, Henning; Møller, Anders; Schwartzbach, Michael I.

2006-01-01

Interactive Web services consist of a mixture of HTML fragments and program code. The fragments, which are maintained by designers, are combined to form HTML pages that are shown to the clients. The code, which is maintained by programmers, is executed on the server to handle the business logic....... Current Web service frameworks provide little help in separating these constituents, which complicates cooperation between programmers and HTML designers. We propose a system based on XML templates and formalized contracts allowing a flexible separation of concerns. The contracts act as interfaces between...... the programmers and the HTML designers and permit tool support for statically checking that both parties fulfill their obligations. This ensures that (1) programmers and HTML designers work more independently focusing on their own expertises, (2) the Web service implementation is better structured and thus easier...

Abductive Logic Grammars

DEFF Research Database (Denmark)

Christiansen, Henning; Dahl, Veronica

2009-01-01

By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting....... We formalize these ideas, and exemplify them both within and outside first-order logic, and for both fixed and dynamic knowledge bases. Within the latter variety, we consider the usual left-to-right derivations that are traditional in logic grammars, but also -- in a significant departure from...

Microprocessing in European High Energy Physics Experiments - ECFA Working Group on Data Processing Standards - Report of the Microprocessor Subgroup May 1982

CERN Document Server

European Committee for Future Accelerators (ECFA)

1982-01-01

This document contains two reports on the use of microprocessors in European High-Energy Physics experiments. The first is a presentation of data collected by a sub-group of the ECFA working group on data procesing standards. The working group is organised by E. Lillestol, University of Bergen and E.M. Rimmer, CERN, DD Division; the Microprocessor sub-group organiser is L.O. Hertzberger, NIKHEF, Amsterdam. Data are given from projects numbered 81 - 194, and some CERN projects are included. Even though there is some duplication of information, a second report has been appended which covers a wider range of CERN projects. This was the result of a microprocessor survey made at CERN by P. Scharff-Hansen, DD Division, at the request of E. Gabthuler. The ECFA working group intends to have reports for all the sub-groups (10 in number) available in machine-readable form at the CERN computer centre. However, it was felt that the information herein is most valuable to designers and users of microprocessors, and that it...

Applications of Logic Coverage Criteria and Logic Mutation to Software Testing

Science.gov (United States)

Kaminski, Garrett K.

2011-01-01

Logic is an important component of software. Thus, software logic testing has enjoyed significant research over a period of decades, with renewed interest in the last several years. One approach to detecting logic faults is to create and execute tests that satisfy logic coverage criteria. Another approach to detecting faults is to perform mutation…

Vérification des propriétés temporisées des automates programmables industriels

OpenAIRE

Bel Mokadem , Houda

2006-01-01

Vérification of PLC (Programmable Logic Controller) programs is important when these programs are to control critical applications for reactive systems. This context has already been study for untimed programs. In this thesis, We are interested to timed properties and programs. More precisely, we give a formal semantics to (partial) Ladder diagrams and TON blocks, with timed automata. We also propose a timed logic in order to abstract transient events, where transient properties is parameteri...

Application of programmable controllers to vacuum system interlocks

International Nuclear Information System (INIS)

Lee, G.; Moore, D.

1979-11-01

This paper describes the Doublet III Vacuum Control System in which all input signals and output loads are connected to a programmable controller (PC) for logical interfacing. Input signals derived from CAMAC, control panels, limit switches, etc., are implemented as output signals to CAMAC, vacuum valves, pump motors, etc., according to a logic program stored in the PC memory. The memory can be easily programmed by anyone familar with either Boolean algebra or relay-ladder network diagrams. The program data is entered with the aid of a calculator like, keyboard instrument with LED readout displays. The PC system contains a 1024 word RAM memory with a battery backup system to provide 72 hours protection of contents in case of power failure

Stochastic coalgebraic logic

CERN Document Server

Doberkat, Ernst-Erich

2009-01-01

Combining coalgebraic reasoning, stochastic systems and logic, this volume presents the principles of coalgebraic logic from a categorical perspective. Modal logics are also discussed, including probabilistic interpretations and an analysis of Kripke models.

Microprocessor Control Design for a Low-Head Crossflow Turbine.

Science.gov (United States)

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Control Logic for the Interlock system of the ATLAS Insertable B-Layer

CERN Document Server

Riegel, Christian

Part of the first upgrade program of the ATLAS detector is the installation of the Insertable B-Layer (IBL) as a fourth and innermost detector layer of the ATLAS pixel detector to prepare the tracking system for the expected increase of pile-up events. As with every sub-detector, the IBL and its components have to be monitored and controlled via a Detector Control System (DCS). A hardware-based interlock system is installed on-site to prevent detector and people working at the detector from serious harm and damage. For the IBL, the logical processing of interlock signals is realised in Interlock Matrix Crates (IMCs) using Complex Programmable Logic Devices (CPLD). One part of this master thesis is the automatic implementation of the logical assignments from database information. A script was developed to generate the needed file to program the CPLD. The second part of this thesis is the design of a test setup to verify the functionality of the electrical components of each IMC and to confirm the correct proce...

Towards an arithmetical logic the arithmetical foundations of logic

CERN Document Server

Gauthier, Yvon

2015-01-01

This book offers an original contribution to the foundations of logic and mathematics, and focuses on the internal logic of mathematical theories, from arithmetic or number theory to algebraic geometry. Arithmetical logic is the term used to refer to the internal logic of classical arithmetic, here called Fermat-Kronecker arithmetic, and combines Fermat’s method of infinite descent with Kronecker’s general arithmetic of homogeneous polynomials. The book also includes a treatment of theories in physics and mathematical physics to underscore the role of arithmetic from a constructivist viewpoint. The scope of the work intertwines historical, mathematical, logical and philosophical dimensions in a unified critical perspective; as such, it will appeal to a broad readership from mathematicians to logicians, to philosophers interested in foundational questions. Researchers and graduate students in the fields of philosophy and mathematics will benefit from the author’s critical approach to the foundations of l...

Meta-Logical Reasoning in Higher-Order Logic

DEFF Research Database (Denmark)

Villadsen, Jørgen; Schlichtkrull, Anders; Hess, Andreas Viktor

The semantics of first-order logic (FOL) can be described in the meta-language of higher-order logic (HOL). Using HOL one can prove key properties of FOL such as soundness and completeness. Furthermore, one can prove sentences in FOL valid using the formalized FOL semantics. To aid...

Programmable controllers replace relays in MFTF-B personnel-safety interlocks

International Nuclear Information System (INIS)

Branum, J.D.

1981-01-01

This paper describes a new approach for implementing personnel safety interlocks logic using industrial-type programmable controllers. The logic for all personnel safety interlocks except those totally internal to a subsystem is implemented in two non-redundant controllers. A high degree of fail-safe reliability is achieved by augmenting the protective features intrinsic to each controller with those provided by a small amount of external support hardware. The controllers are interfaced to the host computer system via fiber optic data links to enable display of interlock and overall system status on the control room graphic displays. When fully implemented, the controllers will perform the equivalent of over 2000 discreet relay functions

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Microprocessor system for data acquisition processing and display for Auger electrons spectrometer

International Nuclear Information System (INIS)

Pawlowski, Z.; Cudny, W.; Hildebrandt, S.; Marzec, J.; Walentek, J.; Zaremba, K.

1984-01-01

Data acquisition system for Auger electron spectrometry is developed. The system is used for chemical and structural analysis of materials and consists of a cylindrical mirror analyzer being a measuring spectrometer device, CAMAC unit and control unit. The control unit comprises a microcomputer based on INTEL 8080 microprocessor and display

Adapting to change: influence of a microprocessor-controlled prosthetic knee on gait adaptations

NARCIS (Netherlands)

Prinsen, Erik Christiaan

2016-01-01

Advancement in prosthetic knee design have led to the introduction of microprocessor-controlled prosthetic knees (MPKs). MPKs incorporate sensors that are able to measure prosthetic loading, the knee angle, and knee angular velocity. Based on the sensor information, MPKs determine the optimal level

Microprocessor based image processing system

International Nuclear Information System (INIS)

Mirza, M.I.; Siddiqui, M.N.; Rangoonwala, A.

1987-01-01

Rapid developments in the production of integrated circuits and introduction of sophisticated 8,16 and now 32 bit microprocessor based computers, have set new trends in computer applications. Nowadays the users by investing much less money can make optimal use of smaller systems by getting them custom-tailored according to their requirements. During the past decade there have been great advancements in the field of computer Graphics and consequently, 'Image Processing' has emerged as a separate independent field. Image Processing is being used in a number of disciplines. In the Medical Sciences, it is used to construct pseudo color images from computer aided tomography (CAT) or positron emission tomography (PET) scanners. Art, advertising and publishing people use pseudo colours in pursuit of more effective graphics. Structural engineers use Image Processing to examine weld X-rays to search for imperfections. Photographers use Image Processing for various enhancements which are difficult to achieve in a conventional dark room. (author)

Connections among quantum logics

International Nuclear Information System (INIS)

Lock, P.F.; Hardegree, G.M.

1985-01-01

In this paper, a theory of quantum logics is proposed which is general enough to enable us to reexamine a previous work on quantum logics in the context of this theory. It is then easy to assess the differences between the different systems studied. The quantum logical systems which are incorporated are divided into two groups which we call ''quantum propositional logics'' and ''quantum event logics''. The work of Kochen and Specker (partial Boolean algebras) is included and so is that of Greechie and Gudder (orthomodular partially ordered sets), Domotar (quantum mechanical systems), and Foulis and Randall (operational logics) in quantum propositional logics; and Abbott (semi-Boolean algebras) and Foulis and Randall (manuals) in quantum event logics, In this part of the paper, an axiom system for quantum propositional logics is developed and the above structures in the context of this system examined. (author)

Microprocessor system for temperature regulation and stabilization

International Nuclear Information System (INIS)

Nguyen Nhi Dien; Rodionov, K.G.

1989-01-01

Microprocessor based system for temperature regulation and stabilization of an operation external object is described. The system has the direct current amplifier working according to modulator-demodulator principle. The overal gain is 100, 1000, 2000. The maximum output signal is ±10 V. The power amplifier is a thyristor one and its line voltage is 220 V, 50 Hz. The output power is 0-2 kVA. The microcontroller has a remote display terminal. Data input is 8 and data output is one. Input and output voltage is ±(0-10) V. The preselection time for stabilization is within 1 s - 18 h. The program algorithm is given. 5 figs.; 1 tab

Paraconsistent Computational Logic

DEFF Research Database (Denmark)

Jensen, Andreas Schmidt; Villadsen, Jørgen

2012-01-01

In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study....

Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

International Nuclear Information System (INIS)

Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

2015-01-01

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

What are Institutional Logics

DEFF Research Database (Denmark)

Berg Johansen, Christina; Waldorff, Susanne Boch

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...

Microprocessor-controlled time domain reflectometer for dynamic shock position measurements

International Nuclear Information System (INIS)

Virchow, C.F.; Conrad, G.E.; Holt, D.M.; Hodson, E.K.

1980-01-01

Time-domain reflectometry is used in a novel way to measure dynamically shock propagation in various media. The primary component in this measurement system is a digital time domain reflectometer, which uses local intelligence, a Motorola 6800 microprocessor, to make the unit adaptable and versatile. The recorder, its operating theory and its method of implementation are described and typical data are reviewed. Applications include nuclear explosion yield estimates and explosive energy flow measurements

Autotuning of PID controller by means of human machine interface device

Directory of Open Access Journals (Sweden)

Michał Awtoniuk

2017-06-01

Full Text Available More and more control systems are based on industry microprocessors like PLC controllers (Programmable Logic Controller. The most commonly used control algorithm is PID (Proportional-Integral-Derivative algorithm. Autotuning procedure is not available in every PLC. These controllers are typically used in cooperation with HMI (Human Machine Interface devices. In the study two procedures of autotuning of the PID controller were implemented in the HMI device: step method and relay method. Six tuning rules for step methods and one for relay method were chosen. The autotuning procedures on simulated controlled object and PLC controller without build-in autotuning were tested. The object of control was first order system plus time delay.

Dispositional logic

Science.gov (United States)

Le Balleur, J. C.

1988-01-01

The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

Logic and structure

CERN Document Server

Dalen, Dirk

1983-01-01

A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...

The HXR80M-balloon experiment: a microprocessor-controlled transatlantic payload

International Nuclear Information System (INIS)

Ubertini, P.; Bazzano, A.; Boccaccini, L.

1980-01-01

Following the results obtained from the succesful transatlantic flight launched during the summer 1976 from the CNR Milo Base, Sicily, the Laboratorio di Astrofisica Spaziale has started a new program in the hard X-ray astronomy field. It basically consists in the development of high resolution large area Multiwire Proportional Chambers to be employed in long duration balloon flights to study and monitor galactic and extragalactic sources. This note will describe the flight configuration and performances of the HXR80M payload. The experiment is expected to fly during July 1980 from the Milo Base in the framework of the CNR experimental balloon campaign. The note will analyze the main characteristics of the detectors employed, of the data handling electronics and in particular of the hardware and the software of the on-board microprocessor controlled multichannel analyzer. In fact the limitation due to the low bit rate HF link (1.2kbit/s) and the long flight duration (about one week) make imperative the use of an on-board microprocessor system to handle and select in real time the scientific data and to control the housekeeping and the telecommand systems

Development of a highly selective muon trigger exploiting the high spatial resolution of monitored drift-tube chambers for the ATLAS experiment at the HL-LHC

CERN Document Server

Kortner, Oliver; The ATLAS collaboration

2018-01-01

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC, where the instantaneous luminosity will exceed the LHC design instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the current system. This first level trigger limitation can be overcome by including data from the precision muon drift tube (MDT) chambers. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic. The feasibility of this approach was studied with LHC collision data and simulated data. Two main options for the hardware implementation will be studied with demonstrators: an FPGA based option with an embedded ARM microprocessor ...

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

International Nuclear Information System (INIS)

Becam, C.; Bernaudin, P.; Delanghe, J.; Mencik, M.; Merkel, B.; Plothow, H.; Fest, H.M.; Lecoq, J.; Martin, H.; Meyer, J.M.

1981-01-01

The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

Engineered modular biomaterial logic gates for environmentally triggered therapeutic delivery

Science.gov (United States)

Badeau, Barry A.; Comerford, Michael P.; Arakawa, Christopher K.; Shadish, Jared A.; Deforest, Cole A.

2018-03-01

The successful transport of drug- and cell-based therapeutics to diseased sites represents a major barrier in the development of clinical therapies. Targeted delivery can be mediated through degradable biomaterial vehicles that utilize disease biomarkers to trigger payload release. Here, we report a modular chemical framework for imparting hydrogels with precise degradative responsiveness by using multiple environmental cues to trigger reactions that operate user-programmable Boolean logic. By specifying the molecular architecture and connectivity of orthogonal stimuli-labile moieties within material cross-linkers, we show selective control over gel dissolution and therapeutic delivery. To illustrate the versatility of this methodology, we synthesized 17 distinct stimuli-responsive materials that collectively yielded all possible YES/OR/AND logic outputs from input combinations involving enzyme, reductant and light. Using these hydrogels we demonstrate the first sequential and environmentally stimulated release of multiple cell lines in well-defined combinations from a material. We expect these platforms will find utility in several diverse fields including drug delivery, diagnostics and regenerative medicine.

First-Order Hybrid Logic

DEFF Research Database (Denmark)

Braüner, Torben

2011-01-01

Hybrid logic is an extension of modal logic which allows us to refer explicitly to points of the model in the syntax of formulas. It is easy to justify interest in hybrid logic on applied grounds, with the usefulness of the additional expressive power. For example, when reasoning about time one...... often wants to build up a series of assertions about what happens at a particular instant, and standard modal formalisms do not allow this. What is less obvious is that the route hybrid logic takes to overcome this problem often actually improves the behaviour of the underlying modal formalism....... For example, it becomes far simpler to formulate proof-systems for hybrid logic, and completeness results can be proved of a generality that is simply not available in modal logic. That is, hybridization is a systematic way of remedying a number of known deficiencies of modal logic. First-order hybrid logic...

Metamathematics of fuzzy logic

CERN Document Server

Hájek, Petr

1998-01-01

This book presents a systematic treatment of deductive aspects and structures of fuzzy logic understood as many valued logic sui generis. Some important systems of real-valued propositional and predicate calculus are defined and investigated. The aim is to show that fuzzy logic as a logic of imprecise (vague) propositions does have well-developed formal foundations and that most things usually named `fuzzy inference' can be naturally understood as logical deduction.

Equational type logic

NARCIS (Netherlands)

Manca, V.; Salibra, A.; Scollo, Giuseppe

1990-01-01

Equational type logic is an extension of (conditional) equational logic, that enables one to deal in a single, unified framework with diverse phenomena such as partiality, type polymorphism and dependent types. In this logic, terms may denote types as well as elements, and atomic formulae are either

Henkin and Hybrid Logic

DEFF Research Database (Denmark)

Blackburn, Patrick Rowan; Huertas, Antonia; Manzano, Maria

2014-01-01

Leon Henkin was not a modal logician, but there is a branch of modal logic that has been deeply influenced by his work. That branch is hybrid logic, a family of logics that extend orthodox modal logic with special proposition symbols (called nominals) that name worlds. This paper explains why...... Henkin’s techniques are so important in hybrid logic. We do so by proving a completeness result for a hybrid type theory called HTT, probably the strongest hybrid logic that has yet been explored. Our completeness result builds on earlier work with a system called BHTT, or basic hybrid type theory...... is due to the first-order perspective, which lies at the heart of Henin’s best known work and hybrid logic....

Institutional Logics in Action

DEFF Research Database (Denmark)

Lounsbury, Michael; Boxenbaum, Eva

2013-01-01

This double volume presents state-of-the-art research and thinking on the dynamics of actors and institutional logics. In the introduction, we briefly sketch the roots and branches of institutional logics scholarship before turning to the new buds of research on the topic of how actors engage...... institutional logics in the course of their organizational practice. We introduce an exciting line of new works on the meta-theoretical foundations of logics, institutional logic processes, and institutional complexity and organizational responses. Collectively, the papers in this volume advance the very...... prolific stream of research on institutional logics by deepening our insight into the active use of institutional logics in organizational action and interaction, including the institutional effects of such (inter)actions....

A CAMAC-resident microprocessor for the monitoring of polarimeter spin states

International Nuclear Information System (INIS)

Reid, D.; DuPlantis, D.; Yoder, N.; Dale, D.

1992-01-01

A CAMAC module for the reporting of polarimeter spin states is being developed using a resident microcontroller. The module will allow experimenters at the Indiana University Cyclotron Facility to monitor spin states and correlate spin information with other experimental data. The use of a microprocessor allows for adaptation of the module as new requirements ensue without change to the printed circuit board layout. (author)

Logic synthesis for FPGA-based finite state machines

CERN Document Server

Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

2016-01-01

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

Use of a microprocessor in the CAMAC standard. The dedicated microcomputer: JCAM-10

International Nuclear Information System (INIS)

Gallice, Pierre.

1978-01-01

The general purpose minicomputers and dedicated crate controllers currently used in small CAMAC systems are now being superseded by autonomous crate controllers with built-in microprocessor such as the JCAM-10, which is in fact a CAMAC dedicated microcomputer. This controller has been designed around the INTEL-8080 microprocessor and employs a semiconductor memory. The very much reduced price and smaller packaging of this module, and the relatively large potential market of CAMAC systems justify the tremendous efforts required for the study of its complete system as well in hardware than in software. After a short description of the CAMAC standard this paper will describe the principle of the microcomputer JCAM-10, and its complementary system: hardware (peripheral modules) and software (TTY command processor, Input Output, Control system, interrupt system, text editor, local macro-assembler, LP and BASICAM local compilers). As application examples, an autonomous counting system and a distributed intelligence system will be described [fr

The Third Life of Quantum Logic: Quantum Logic Inspired by Quantum Computing

OpenAIRE

Dunn, J. Michael; Moss, Lawrence S.; Wang, Zhenghan

2013-01-01

We begin by discussing the history of quantum logic, dividing it into three eras or lives. The first life has to do with Birkhoff and von Neumann's algebraic approach in the 1930's. The second life has to do with attempt to understand quantum logic as logic that began in the late 1950's and blossomed in the 1970's. And the third life has to do with recent developments in quantum logic coming from its connections to quantum computation. We discuss our own work connecting quantum logic to quant...

Real Islamic Logic

NARCIS (Netherlands)

Bergstra, J.A.

2011-01-01

Four options for assigning a meaning to Islamic Logic are surveyed including a new proposal for an option named "Real Islamic Logic" (RIL). That approach to Islamic Logic should serve modern Islamic objectives in a way comparable to the functionality of Islamic Finance. The prospective role of RIL

What are Institutional Logics

OpenAIRE

Berg Johansen, Christina; Bock Waldorff, Susanne

2015-01-01

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guided by institutional logics, as well as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to...

Microprocessor-based control for independently-phased RF linac cavities

International Nuclear Information System (INIS)

Dawson, J.W.

1979-01-01

A microprocessor based system has been built to control the RF amplifiers associated with independently phased linac cavities. The system has an 8080A at each amplifier station, together with associated ROM, RAM, I/O, etc. At a central NOVA 3 computer an additional 8080A system is incorporated in the interface to the NOVA I/O bus. The NOVA interface is connected by a bus of eighteen twisted pairs to each amplifier station, providing bilateral transmission between each station and the NOVA. The system architecture, bus protocol, and operating characteristics are described

The European Fusion Research and Development Programme and the ITER Project

International Nuclear Information System (INIS)

Green, B J

2006-01-01

The EURATOM fusion research and development programme is a well integrated and coordinated programme. It has the objective of ''developing the technology for a safe, sustainable, environmentally responsible and economically viable energy source.'' The programme is focussed on the magnetic confinement approach and supports 23 Associations which involve research entities (many with experimental and technology facilities) each having a bilateral contractual relationship with the European Commission. The paper will describe fusion reactions and present their potential advantages as an energy source. Further, it will describe the EURATOM programme and how it is organised and implemented. The success of the European programme and that of other national programmes, have provided the basis for the international ITER Project, which is the next logical step in the development of fusion energy. The paper will describe ITER, its aims, its design, and the supporting manufacture of prototype components. The European contribution to ITER, the exploitation of the Joint European Torus (JET), and the long-term reactor technology R and D are carried out under the multilateral European Fusion Development Agreement (EFDA)

Programme for test generation for combinatorial and sequential systems

International Nuclear Information System (INIS)

Tran Huy Hoan

1973-01-01

This research thesis reports the computer-assisted search for tests aimed at failure detection in combinatorial and sequential logic circuits. As he wants to deal with complex circuits with many modules such as those met in large scale integrated circuits (LSI), the author used propagation paths. He reports the development of a method which is valid for combinatorial systems and for several sequential circuits comprising elementary logic modules and JK and RS flip-flops. This method is developed on an IBM 360/91 computer in PL/1 language. The used memory space is limited and adjustable with respect to circuit dimension. Computing time is short when compared to that needed by other programmes. The solution is practical and efficient for failure test and localisation

Some relationships between logic programming and multiple-valued logic

International Nuclear Information System (INIS)

Rine, D.C.

1986-01-01

There have been suggestions in the artificial intelligence literature that investigations into relationships between logic programming and multiple-valued logic may be helpful. This paper presents some of these relationships through equivalent algebraic evaluations

Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

International Nuclear Information System (INIS)

Korsah, K.

2001-01-01

This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I and C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I and C system upgrades of present-day nuclear power plants, as well as I and C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current, analog-based I and C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in

Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

CERN Document Server

Bonacini, Sandro; Kloukinas, Kostas

2007-01-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

Corporate traveler centered development of a loyalty programme

OpenAIRE

Keskiväli, Mika

2015-01-01

This thesis is a qualitative case study that examined how the airline corporate sales client company employee (known as business traveler) engagement could be developed by the customer co-creation methods in the loyalty programme perspective. The thesis is using the service marketing theory and the service- and customer-dominant logics as the base in understanding the service development and the customer-centric approach. The business-to-business and the relationship marketing theories are in...

People Like Logical Truth: Testing the Intuitive Detection of Logical Value in Basic Propositions.

Directory of Open Access Journals (Sweden)

Hiroko Nakamura

Full Text Available Recent studies on logical reasoning have suggested that people are intuitively aware of the logical validity of syllogisms or that they intuitively detect conflict between heuristic responses and logical norms via slight changes in their feelings. According to logical intuition studies, logically valid or heuristic logic no-conflict reasoning is fluently processed and induces positive feelings without conscious awareness. One criticism states that such effects of logicality disappear when confounding factors such as the content of syllogisms are controlled. The present study used abstract propositions and tested whether people intuitively detect logical value. Experiment 1 presented four logical propositions (conjunctive, biconditional, conditional, and material implications regarding a target case and asked the participants to rate the extent to which they liked the statement. Experiment 2 tested the effects of matching bias, as well as intuitive logic, on the reasoners' feelings by manipulating whether the antecedent or consequent (or both of the conditional was affirmed or negated. The results showed that both logicality and matching bias affected the reasoners' feelings, and people preferred logically true targets over logically false ones for all forms of propositions. These results suggest that people intuitively detect what is true from what is false during abstract reasoning. Additionally, a Bayesian mixed model meta-analysis of conditionals indicated that people's intuitive interpretation of the conditional "if p then q" fits better with the conditional probability, q given p.

Concurrent weighted logic

DEFF Research Database (Denmark)

Xue, Bingtian; Larsen, Kim Guldstrand; Mardare, Radu Iulian

2015-01-01

We introduce Concurrent Weighted Logic (CWL), a multimodal logic for concurrent labeled weighted transition systems (LWSs). The synchronization of LWSs is described using dedicated functions that, in various concurrency paradigms, allow us to encode the compositionality of LWSs. To reflect these......-completeness results for this logic. To complete these proofs we involve advanced topological techniques from Model Theory....

AFRRI's conversion to a microprocessor-based reactor instrumentation and control system

International Nuclear Information System (INIS)

Moore, Mark L.; Hodgdon, Kenneth M.

1986-01-01

The Armed Forces Radiobiology Research Institute (AFRRI) is procuring a state-of- the-art microprocessor-based instrumentation and control system to operate AFRRI's 1 MW (steady-state), 3000 MW (pulse) TRIGA Mark-F reactor. This system will replace the current control console while improving or maintaining the existing operational capabilities and safety characteristics. The new unit will have a 15-year design life using state-of-the-art components

Microprocessor based mobile radiation survey system

International Nuclear Information System (INIS)

Gilbert, R.W.; McCormack, W.D.

1983-12-01

A microprocessor-based system has been designed and constructed to enhance the performance of routine radiation surveys on roads within the Hanford site. This device continually monitors system performance and output from four sodium iodide detectors mounted on the rear bumper of a 4-wheel drive truck. The gamma radiation count rate in counts-per-second is monitored, and a running average computed, with the results compared to predefined limits. If an abnormal instantaneous or average count rate is detected, an alarm is sounded with responsible data displayed on a liquid crystal panel in the cab of the vehicle. The system also has the capability to evaluate detector output using multiple time constants and to perform more complex tests and comparison of the data. Data can be archived for later analysis on conventional chart recorders or stored in digital form on magnetic tape or other digital storage media. 4 figures

Use of a microprocessor in a remote working level monitor

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.; Groer, P.G.

1976-01-01

The instrument described measures the short-lived 222 Rn-daughter concentrations and the Working Level (WL) in sealed ''hot chambers'' located in uranium mines. Radiation-induced pulses from two separate sensors are transmitted through 500 ft. cables to a microprocessor, which processes the pulses and controls the operation of the system. A read-only memory stores a fixed program which is used to calculate the desired concentrations. The results are printed as pCi/l (Rn-daughter concentrations) and WL

Action Type Deontic Logic

DEFF Research Database (Denmark)

Bentzen, Martin Mose

2014-01-01

A new deontic logic, Action Type Deontic Logic, is presented. To motivate this logic, a number of benchmark cases are shown, representing inferences a deontic logic should validate. Some of the benchmark cases are singled out for further comments and some formal approaches to deontic reasoning...... are evaluated with respect to the benchmark cases. After that follows an informal introduction to the ideas behind the formal semantics, focussing on the distinction between action types and action tokens. Then the syntax and semantics of Action Type Deontic Logic is presented and it is shown to meet...

Microprocessor control unit of thyristor regulator of microhydroelectric power station ballast load

International Nuclear Information System (INIS)

Nomokonova, Yu; Bogdanov, E

2014-01-01

The operational principle of microhydroelectric power station ballast load is presented. The comparative overview of the mathematical modeling methods is performed. The ranges of thyristors optimal work are shown as a result of the regulator regimes analysis. Shows the necessity of regulation the ballast load in microhydroelectric power station with help of developed algorithm of the program for microprocessor control

Quantifiers for quantum logic

OpenAIRE

Heunen, Chris

2008-01-01

We consider categorical logic on the category of Hilbert spaces. More generally, in fact, any pre-Hilbert category suffices. We characterise closed subobjects, and prove that they form orthomodular lattices. This shows that quantum logic is just an incarnation of categorical logic, enabling us to establish an existential quantifier for quantum logic, and conclude that there cannot be a universal quantifier.

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Radiation tolerant combinational logic cell

Science.gov (United States)

Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

2009-01-01

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

Erotetic epistemic logic

Czech Academy of Sciences Publication Activity Database

Peliš, Michal

2017-01-01

Roč. 26, č. 3 (2017), s. 357-381 ISSN 1425-3305 R&D Projects: GA ČR(CZ) GC16-07954J Institutional support: RVO:67985955 Keywords : epistemic logic * erotetic implication * erotetic logic * logic of questions Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology http://apcz.umk.pl/czasopisma/index.php/LLP/article/view/LLP.2017.007

The Football of Logic

Directory of Open Access Journals (Sweden)

Schang Fabien

2017-03-01

Full Text Available An analogy is made between two rather different domains, namely: logic, and football (or soccer. Starting from a comparative table between the two activities, an alternative explanation of logic is given in terms of players, ball, goal, and the like. Our main thesis is that, just as the task of logic is preserving truth from premises to the conclusion, footballers strive to keep the ball as far as possible until the opposite goal. Assuming this analogy may help think about logic in the same way as in dialogical logic, but it should also present truth-values in an alternative sense of speech-acts occurring in a dialogue. The relativity of truth-values is focused by this way, thereby leading to an additional way of logical pluralism.

The Logic of Practice in the Practice of Logics

DEFF Research Database (Denmark)

Raviola, Elena; Dubini, Paola

2016-01-01

of logics through a six months full-time ethnographic study at Il Sole-24 Ore, the largest Italian financial newspaper, between 2007 and 2008. An original conceptual framework is developed to analyse how the logic of journalism is enacted vis-à-vis that of advertising in a setting in which an old technology...... for news production – print newspaper – coexists with a new one – website – and thus encounters between new and old technological possibilities make workings of institutional logics particularly visible. The findings point out different mechanisms of institutional work dealing with actions that, made...

Microprocessor-assisted calibration for a remote working level monitor

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

1977-01-01

A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

Microprocessor-assisted calibration for a remote working level monitor

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

1976-01-01

A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

Microprocessor-controlled data-acquisition instrument for neutron-activation measurements

International Nuclear Information System (INIS)

Jones, B.A.

1981-01-01

This paper describes a microprocessor controlled data acquisition instrument designed at Lawrence Livermore National Laboratory to provide experimenters with a diagnostic tool for measuring the performance of laser imploded fusion targets via neutron activation techniques. This instrument features the ability to count four independent inputs simultaneously while providing a front panel readout of these inputs, plus a time of day clock. A hardcopy printout of the data is also provided by a built-in thermal printer. All running modes and parameters are user selectable via a front panel keypad, and a complete set of internal self-testing diagnostics are available for debug

Microprocessor-controlled inhalation system for repeated exposure of animals to aerosols

International Nuclear Information System (INIS)

Carpenter, R.L.; Barr, F.P.; Leydig, R.L.; Rajala, R.E.

1979-01-01

A microprocessor-controlled inhalation exposure system (MCIES) has been built to automate aerosol generation and sampling while controlling exposure time for animal toxicity studies. The system has a time resolution of 0.1 s and automatically sequences the exposure events from initiation to temination of the exposure. The operator is required to preset all airflows, read in a paper tape containing the time sequence of events, and initiate the automatic sequence by closing a switch

A monitoring and protective system for mine hoists using a microprocessor

Energy Technology Data Exchange (ETDEWEB)

Jianlin, Zhu

1981-11-01

In view of the existing problems of depth indicators and tachometers currently used in mine hoists, a measuring technique using a 'wire cable magnetic stripe' and a tentative proposal for a monitoring system with a microprocessor are described. The system can be used for measuring and indicating the depth, speed of the hoisting system, and can provide protection against overwinding, overspeeding and slack rope as well as monitoring the direction of hoisting. (In Chinese)

Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants

International Nuclear Information System (INIS)

2016-01-01

Field programmable gate arrays (FPGAs) are gaining increased attention worldwide for application in nuclear power plant (NPP) instrumentation and control (I&C) systems, particularly for safety and safety related applications, but also for non-safety ones. NPP operators and equipment suppliers see potential advantages of FPGA based digital I&C systems as compared to microprocessor based applications. This is because FPGA based systems can be made simpler, more testable and less reliant on complex software (e.g. operating systems), and are easier to qualify for safety and safety related applications. This publication results from IAEA consultancy meetings covering the various aspects, including design, qualification, implementation, licensing, and operation, of FPGA based I&C systems in NPPs

A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

Science.gov (United States)

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

Instrument for bone mineral measurement using a microprocessor as the control and arithmetic element

International Nuclear Information System (INIS)

Alberi, J.L.; Hardy, W.H. II.

1975-11-01

A self-contained instrument for the determination of bone mineral content by photon absorptometry is described. A high-resolution detection system allows measurements to be made at up to 16 photon energies. Control and arithmetic functions are performed by a microprocessor. Analysis capability and limitations are discussed

A fast-slow logic system

International Nuclear Information System (INIS)

Kawashima, Hideo.

1977-01-01

A fast-slow logic system has been made for use in multi-detector experiments in nuclear physics such as particle-gamma and particle-particle coincidence experiments. The system consists of a fast logic system and a slow logic system. The fast logic system has a function of fast coincidences and provides timing signals for the slow logic system. The slow logic system has a function of slow coincidences and a routing control of input analog signals to the ADCs. (auth.)

Logical NAND and NOR Operations Using Algorithmic Self-assembly of DNA Molecules

Science.gov (United States)

Wang, Yanfeng; Cui, Guangzhao; Zhang, Xuncai; Zheng, Yan

DNA self-assembly is the most advanced and versatile system that has been experimentally demonstrated for programmable construction of patterned systems on the molecular scale. It has been demonstrated that the simple binary arithmetic and logical operations can be computed by the process of self assembly of DNA tiles. Here we report a one-dimensional algorithmic self-assembly of DNA triple-crossover molecules that can be used to execute five steps of a logical NAND and NOR operations on a string of binary bits. To achieve this, abstract tiles were translated into DNA tiles based on triple-crossover motifs. Serving as input for the computation, long single stranded DNA molecules were used to nucleate growth of tiles into algorithmic crystals. Our method shows that engineered DNA self-assembly can be treated as a bottom-up design techniques, and can be capable of designing DNA computer organization and architecture.

Supply system with microprocessor control for electron gun

International Nuclear Information System (INIS)

Duplin, N.I.; Sergeev, N.N.

1988-01-01

Precision supply system for electron gun used in Auger-spectrometer is described. The supply system consists of control and high-voltage parts, made as separate units. Supply high-voltage unit includes system supply module, filament module to supply electron gun cathode and 6 high-volt modules to supply accelerating, modulating and three focusing electrodes of the gun. High-voltage modules have the following characteristics: U-(100-1000)V output voltage, 5x10 -5 U stability, 10 -5 xU pulsation amplitude, J-(0-5)A filament current change range at 10 -4 xJ stability. Control unit including microprocessor, timer and storage devices forms control voltage for all modules and regulates voltage and current of filament at electrodes

Logic for Physicists

Science.gov (United States)

Pereyra, Nicolas A.

2018-06-01

This book gives a rigorous yet 'physics-focused' introduction to mathematical logic that is geared towards natural science majors. We present the science major with a robust introduction to logic, focusing on the specific knowledge and skills that will unavoidably be needed in calculus topics and natural science topics in general (rather than taking a philosophical-math-fundamental oriented approach that is commonly found in mathematical logic textbooks).

Logic of likelihood

International Nuclear Information System (INIS)

Wall, M.J.W.

1992-01-01

The notion of open-quotes probabilityclose quotes is generalized to that of open-quotes likelihood,close quotes and a natural logical structure is shown to exist for any physical theory which predicts likelihoods. Two physically based axioms are given for this logical structure to form an orthomodular poset, with an order-determining set of states. The results strengthen the basis of the quantum logic approach to axiomatic quantum theory. 25 refs

The European fusion research and development programme and the ITER Project

International Nuclear Information System (INIS)

Green, B.J.

2004-01-01

The EURATOM fusion R and D programme is a well integrated and co-ordinated programme a good example of a European Research Area. Its goal is 'the joint creation of prototype reactors for power stations to meet the needs of society: operational safety, environmental compatibility, economic viability'. The programme is focussed on the magnetic confinement approach to fusion energy and supports 21 associated laboratories and a range of experimental and fusion technology facilities. The paper will briefly describe this programme and how it is organised and implemented. Its success and that of other national programmes has defined the international ITER Project, which is the next logical step in fusion R and D. The paper will describe ITER, its aims, its design, and the supporting manufacture of prototype components. The European contribution to ITER, as well as the exploitation of the Joint European Torus (JET) and long-term fusion reactor technology R and D are carried out under the European Fusion Development Agreement (EFDA). Finally, the potential advantages of fusion as an energy source will be presented. (author)

Microelectromechanical reprogrammable logic device

KAUST Repository

Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.

2016-01-01

on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance

One reason, several logics

Directory of Open Access Journals (Sweden)

Evandro Agazzi

2011-06-01

Full Text Available Humans have used arguments for defending or refuting statements long before the creation of logic as a specialized discipline. This can be interpreted as the fact that an intuitive notion of "logical consequence" or a psychic disposition to articulate reasoning according to this pattern is present in common sense, and logic simply aims at describing and codifying the features of this spontaneous capacity of human reason. It is well known, however, that several arguments easily accepted by common sense are actually "logical fallacies", and this indicates that logic is not just a descriptive, but also a prescriptive or normative enterprise, in which the notion of logical consequence is defined in a precise way and then certain rules are established in order to maintain the discourse in keeping with this notion. Yet in the justification of the correctness and adequacy of these rules commonsense reasoning must necessarily be used, and in such a way its foundational role is recognized. Moreover, it remains also true that several branches and forms of logic have been elaborated precisely in order to reflect the structural features of correct argument used in different fields of human reasoning and yet insufficiently mirrored by the most familiar logical formalisms.

Three challenges to the complementarity of the logic and the pragmatics of science.

Science.gov (United States)

Uebel, Thomas

2015-10-01

The bipartite metatheory thesis attributes to Rudolf Carnap, Philipp Frank and Otto Neurath a conception of the nature of post-metaphysical philosophy of science that sees the purely formal-logical analyses of the logic of science as complemented by empirical inquiries into the psychology, sociology and history of science. Three challenges to this thesis are considered in this paper: that Carnap did not share this conception of the nature of philosophy of science even on a programmatic level, that Carnap's detailed analysis of the language of science is incompatible with one developed by Neurath for the pursuit of empirical studies of science, and, finally, that Neurath himself was confused about the programme of which the bipartite metatheory thesis makes him a representative. I argue that all three challenges can be met and refuted. Copyright © 2015 Elsevier Ltd. All rights reserved.

GOAL Agents Instantiate Intention Logic

OpenAIRE

Hindriks, Koen; van der Hoek, Wiebe

2008-01-01

It is commonly believed there is a big gap between agent logics and computational agent frameworks. In this paper, we show that this gap is not as big as believed by showing that GOAL agents instantiate Intention Logic of Cohen and Levesque. That is, we show that GOAL agent programs can be formally related to Intention Logic.We do so by proving that the GOAL Verification Logic can be embedded into Intention Logic. It follows that (a fragment of) Intention Logic can be used t...

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Energy Technology Data Exchange (ETDEWEB)

Kish, Laszlo B. [Texas A and M University, Department of Electrical and Computer Engineering, College Station, TX 77843-3128 (United States)], E-mail: laszlo.kish@ece.tamu.edu

2009-03-02

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

International Nuclear Information System (INIS)

Kish, Laszlo B.

2009-01-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Science.gov (United States)

Kish, Laszlo B.

2009-03-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case ( N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Microprocessor-based integrated LMFBR core surveillance

International Nuclear Information System (INIS)

Gmeiner, L.

1984-06-01

This report results from a joint study of KfK and INTERATOM. The aim of this study is to explore the advantages of microprocessors and microelectronics for a more sophisticated core surveillance, which is based on the integration of separate surveillance techniques. Due to new developments in microelectronics and related software an approach to LMFBR core surveillance can be conceived that combines a number of measurements into a more intelligent decision-making data processing system. The following techniques are considered to contribute essentially to an integrated core surveillance system: - subassembly state and thermal hydraulics performance monitoring, - temperature noise analysis, - acoustic core surveillance, - failure characterization and failure prediction based on DND- and cover gas signals, and - flux tilting techniques. Starting from a description of these techniques it is shown that by combination and correlation of these individual techniques a higher degree of cost-effectiveness, reliability and accuracy can be achieved. (orig./GL) [de

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

Science.gov (United States)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

Using evaluability assessment to assess local community development health programmes: a Scottish case-study

Directory of Open Access Journals (Sweden)

Melissa Belford

2017-04-01

Full Text Available Abstract Background Evaluation of the potential effectiveness of a programme’s objectives (health or otherwise is important in demonstrating how programmes work. However, evaluations are expensive and can focus on unrealistic outcomes not grounded in strong theory, especially where there is pressure to show effectiveness. The aim of this research was to demonstrate that the evaluability assessment (a cost-effective pre-evaluation tool that primarily gives quick, constructive feedback can be used to help develop programme and outcome objectives to improve programmes while they run and to assist in producing more effective evaluations. This was done using the example of a community development programme aiming to improve health and reduce health inequalities in its target population. Methods The setting was Glasgow, Scotland, UK and focused on the Health Issues in the Community programme. Data were collected from documents and nine individual stakeholder interviews. Thematic analysis and a realist approach were used to analyse both datasets and, in conjunction with a workshop with stakeholders, produce a logic model of the programme theory and related evaluation options to explore further. Results Five main themes emerged from the analysis: History; Framework; Structure and Delivery of the Course; Theory of Action; and Barriers to Delivery and Successful Outcomes. These themes aided in drafting the logic model which revealed they key programme activities (e.g. facilitating group learning and 23 potential outcomes. The majority of these outcomes (16 were deemed to be short-term outcomes (more easily measured within the timeframe of an individual being involved in the programme e.g. increased self-esteem or awareness of individual/community health. The remaining 6 outcomes were deemed longer-term and included outcomes such as increased social capital and individual mental health and wellbeing. Conclusions We have shown that the evaluability

Understanding Social Media Logic

Directory of Open Access Journals (Sweden)

José van Dijck

2013-08-01

Full Text Available Over the past decade, social media platforms have penetrated deeply into the mech­anics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpin­ning its dynamics. This logic will be considered in light of what has been identified as mass me­dia logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmabil­ity, popularity, connectivity, and datafication—and argue that these principles become increas­ingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance ex­isting mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relat­ively simple to identify, but it is much harder to map the complex connections between plat­forms that distribute this logic: users that employ them, technologies that

Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors.

Science.gov (United States)

Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin

2016-06-22

In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.

A microprocessor-controlled assay for the estimation of human placental lactogen

International Nuclear Information System (INIS)

Adam, T.; Roulston, J.E.; Bagshawe, K.D.

1979-01-01

A radioimmunoassay for human placental lactogen (HPL) is described using the KEMTEK 3000, which is a modular radioimmunoassay apparatus controlled by a microprocessor. Operation of the KEMTEK 3000 is largely automatic and it requires minimal intervention from the operator. It is capable of 300 reactions per hour so that a large number of estimations can readily be performed. HPL was assayed by a double antibody method on serum samples from pregnant women and patients with trophoblastic tumours. (Auth.)

Autonomous controller (JCAM 10) for CAMAC crate with 8080 (INTEL) microprocessor

International Nuclear Information System (INIS)

Gallice, P.; Mathis, M.

1975-01-01

The CAMAC crate autonomous controller JCAM-10 is designed around an INTEL 8080 microprocessor in association with a 5K RAM and 4K REPROM memory. The concept of the module is described, in which data transfers between CAMAC modules and the memory are optimised from software point of view as well as from execution time. In fact, the JCAM-10 is a microcomputer with a set of 1000 peripheral units represented by the CAMAC modules commercially available

Conference Trends in Logic XI

CERN Document Server

Wansing, Heinrich; Willkommen, Caroline; Recent Trends in Philosophical Logic

2014-01-01

This volume presents recent advances in philosophical logic with chapters focusing on non-classical logics, including paraconsistent logics, substructural logics, modal logics of agency and other modal logics. The authors cover themes such as the knowability paradox, tableaux and sequent calculi, natural deduction, definite descriptions, identity, truth, dialetheism, and possible worlds semantics.   The developments presented here focus on challenging problems in the specification of fundamental philosophical notions, as well as presenting new techniques and tools, thereby contributing to the development of the field. Each chapter contains a bibliography, to assist the reader in making connections in the specific areas covered. Thus this work provides both a starting point for further investigations into philosophical logic and an update on advances, techniques and applications in a dynamic field.   The chapters originate from papers presented during the Trends in Logic XI conference at the Ruhr University ...

Logic analysis and verification of n-input genetic logic circuits

DEFF Research Database (Denmark)

Baig, Hasan; Madsen, Jan

2017-01-01

. In this paper, we present an approach to analyze and verify the Boolean logic of a genetic circuit from the data obtained through stochastic analog circuit simulations. The usefulness of this analysis is demonstrated through different case studies illustrating how our approach can be used to verify the expected......Nature is using genetic logic circuits to regulate the fundamental processes of life. These genetic logic circuits are triggered by a combination of external signals, such as chemicals, proteins, light and temperature, to emit signals to control other gene expressions or metabolic pathways...... accordingly. As compared to electronic circuits, genetic circuits exhibit stochastic behavior and do not always behave as intended. Therefore, there is a growing interest in being able to analyze and verify the logical behavior of a genetic circuit model, prior to its physical implementation in a laboratory...

Prospects of luminescence based molecular scale logic gates and logic circuits

International Nuclear Information System (INIS)

Speiser, Shammai

2016-01-01

In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder

Prospects of luminescence based molecular scale logic gates and logic circuits

Energy Technology Data Exchange (ETDEWEB)

Speiser, Shammai, E-mail: speiser@technion.ac.il

2016-01-15

In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder.

Application of linear logic to simulation

Science.gov (United States)

Clarke, Thomas L.

1998-08-01

Linear logic, since its introduction by Girard in 1987 has proven expressive and powerful. Linear logic has provided natural encodings of Turing machines, Petri nets and other computational models. Linear logic is also capable of naturally modeling resource dependent aspects of reasoning. The distinguishing characteristic of linear logic is that it accounts for resources; two instances of the same variable are considered differently from a single instance. Linear logic thus must obey a form of the linear superposition principle. A proportion can be reasoned with only once, unless a special operator is applied. Informally, linear logic distinguishes two kinds of conjunction, two kinds of disjunction, and also introduces a modal storage operator that explicitly indicates propositions that can be reused. This paper discuses the application of linear logic to simulation. A wide variety of logics have been developed; in addition to classical logic, there are fuzzy logics, affine logics, quantum logics, etc. All of these have found application in simulations of one sort or another. The special characteristics of linear logic and its benefits for simulation will be discussed. Of particular interest is a connection that can be made between linear logic and simulated dynamics by using the concept of Lie algebras and Lie groups. Lie groups provide the connection between the exponential modal storage operators of linear logic and the eigen functions of dynamic differential operators. Particularly suggestive are possible relations between complexity result for linear logic and non-computability results for dynamical systems.

R-1 (C-620-A) and R-2 (C-620-B) air compressor control logic, computer software description. Revision 1

International Nuclear Information System (INIS)

Walter, K.E.

1995-01-01

This document provides an updated computer software description for the software used on the FFTF R-1 (C-620-A) and R-2 (C-620-B) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started

Quantum logics with existence property

International Nuclear Information System (INIS)

Schindler, C.

1991-01-01

A quantum logic (σ-orthocomplete orthomodular poset L with a convex, unital, and separating set Δ of states) is said to have the existence property if the expectation functionals on lin(Δ) associated with the bounded observables of L form a vector space. Classical quantum logics as well as the Hilbert space logics of traditional quantum mechanics have this property. The author shows that, if a quantum logic satisfies certain conditions in addition to having property E, then the number of its blocks (maximal classical subsystems) must either be one (classical logics) or uncountable (as in Hilbert space logics)

A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

Science.gov (United States)

Bayindir, Ramazan; Cetinceviz, Yucel

2011-04-01

This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. Copyright © 2010 ISA. Published by Elsevier Ltd. All rights reserved.

Complex cellular logic computation using ribocomputing devices.

Science.gov (United States)

Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

2017-08-03

Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

SUMAC: A monitor and control tree for multi-FPGA systems

International Nuclear Information System (INIS)

Gao, Mingshen

1999-01-01

The BTeV pixel trigger is a data acquisition system capable of finding tracks and vertices in real time in the BTeV pixel detector array. The trigger uses some 3000 processing elements (DSPs) arranged in three processing levels to handle a raw data rate of nearly 100 Gigabytes per second and bring the trigger rate down to 10 KHz. The trigger system has more than 6000 programmable elements, including Field Programmable Logic Arrays (FPGAs), microprocessors (DSPs, interface to the monitor and control tree through FPGAs), and others. Sumac (Serial Utility Monitor and Control tree) is used for configuring and monitoring of these devices. Its primary function is the downloading of FPGA bit streams, microprocessor programs, chip configurations, and test data. In addition, remote cpus and other devices can send messages and status back to the host. The Sumac system is capable of handling several thousand remote devices from a single host PC. Because it stores configuration data in local flash eeproms, it will be capable of achieving a complete system reboot in less than 1 second. The Sumac system is a tree hierarchy connected via high-speed serial links. Typically each board in the system will have a control node which accepts a single upstream serial link and fans out to as many as 32 downstream links. The downstream links can connect to FPGAs or to other control nodes for further fanout

Flat Coalgebraic Fixed Point Logics

Science.gov (United States)

Schröder, Lutz; Venema, Yde

Fixed point logics are widely used in computer science, in particular in artificial intelligence and concurrency. The most expressive logics of this type are the μ-calculus and its relatives. However, popular fixed point logics tend to trade expressivity for simplicity and readability, and in fact often live within the single variable fragment of the μ-calculus. The family of such flat fixed point logics includes, e.g., CTL, the *-nesting-free fragment of PDL, and the logic of common knowledge. Here, we extend this notion to the generic semantic framework of coalgebraic logic, thus covering a wide range of logics beyond the standard μ-calculus including, e.g., flat fragments of the graded μ-calculus and the alternating-time μ-calculus (such as ATL), as well as probabilistic and monotone fixed point logics. Our main results are completeness of the Kozen-Park axiomatization and a timed-out tableaux method that matches ExpTime upper bounds inherited from the coalgebraic μ-calculus but avoids using automata.

MEMS Logic Using Mixed-Frequency Excitation

KAUST Repository

Ilyas, Saad

2017-06-22

We present multi-function microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, OR, universal logic gates NAND, NOR, and a tristate logic gate using mixed-frequency excitation. The concept is based on exciting combination resonances due to the mixing of two or more input signals. The device vibrates at two steady states: a high state when the combination resonance is activated and a low state when no resonance is activated. These vibration states are assigned to logical value 1 or 0 to realize the logic gates. Using ac signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. We found that the energy consumption per cycle of the proposed logic resonator is higher than those of existing technologies. Hence, integration of such logic devices to build complex computational system needs to take into consideration lowering the total energy consumption. [2017-0041

Amplifying genetic logic gates.

Science.gov (United States)

Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

2013-05-03

Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

The Quantum Logical Challenge: Peter Mittelstaedt's Contributions to Logic and Philosophy of Science

Science.gov (United States)

Beltrametti, E.; Dalla Chiara, M. L.; Giuntini, R.

2017-12-01

Peter Mittelstaedt's contributions to quantum logic and to the foundational problems of quantum theory have significantly realized the most authentic spirit of the International Quantum Structures Association: an original research about hard technical problems, which are often "entangled" with the emergence of important changes in our general world-conceptions. During a time where both the logical and the physical community often showed a skeptical attitude towards Birkhoff and von Neumann's quantum logic, Mittelstaedt brought into light the deeply innovating features of a quantum logical thinking that allows us to overcome some strong and unrealistic assumptions of classical logical arguments. Later on his intense research on the unsharp approach to quantum theory and to the measurement problem stimulated the increasing interest for unsharp forms of quantum logic, creating a fruitful interaction between the work of quantum logicians and of many-valued logicians. Mittelstaedt's general views about quantum logic and quantum theory seem to be inspired by a conjecture that is today more and more confirmed: there is something universal in the quantum theoretic formalism that goes beyond the limits of microphysics, giving rise to interesting applications to a number of different fields.

Querying Natural Logic Knowledge Bases

DEFF Research Database (Denmark)

Andreasen, Troels; Bulskov, Henrik; Jensen, Per Anker

2017-01-01

This paper describes the principles of a system applying natural logic as a knowledge base language. Natural logics are regimented fragments of natural language employing high level inference rules. We advocate the use of natural logic for knowledge bases dealing with querying of classes...... in ontologies and class-relationships such as are common in life-science descriptions. The paper adopts a version of natural logic with recursive restrictive clauses such as relative clauses and adnominal prepositional phrases. It includes passive as well as active voice sentences. We outline a prototype...... for partial translation of natural language into natural logic, featuring further querying and conceptual path finding in natural logic knowledge bases....

Microprocessor based beam loss monitor system for the AGS

International Nuclear Information System (INIS)

Witkover, R.L.

1979-01-01

An array of 120 long radiation monitors (LRM) have been installed around the AGS. Each monitor is an extended coaxial ion chamber, 5 meters long, made from hollow core coaxial transmission cable pressured with argon. The LRM's are each connected to a low current preamplifier and voltage-to-frequency converter (VFC). The digital output of each channel is fed to a 16 bit counter chip which bridges the bus of an 8085 microprocessor. This circuit is connected to the AGS PD-10 for data taking or may function as a stand-alone unit. Various operating modes can be selected for data readout. System design and operating performance are described

Questions and dependency in intuitionistic logic

NARCIS (Netherlands)

Ciardelli, Ivano; Iemhoff, Rosalie; Yang, Fan

2017-01-01

In recent years, the logic of questions and dependencies has been investigated in the closely related frameworks of inquisitive logic and dependence logic. These investigations have assumed classical logic as the background logic of statements, and added formulas expressing questions and

Logic Meeting

CERN Document Server

Tugué, Tosiyuki; Slaman, Theodore

1989-01-01

These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.

Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

CERN Document Server

Ponce-Cruz, Pedro; MacCleery, Brian

2016-01-01

This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

International Nuclear Information System (INIS)

Hennig, Christine; Kneupner, Klaus; Kinna, David

2012-01-01

Highlights: ► We describe 2 ways connecting PLCs to fusion control and data acquisition software. ► At W7-X standardization of the PLC type eases the maintenance of the software. ► At JET PLCs are interfaced with a daemon that hides the PLC specific part. ► There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse “black box protocol” approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and observed via timeout mechanisms. The use of PLCs for Wendelstein 7-X is standardized. Therefore a single

Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

Energy Technology Data Exchange (ETDEWEB)

Hennig, Christine, E-mail: Christine.Hennig@ipp.mpg.de [Max-Planck-Institut fuer Plasmaphysik, Wendelsteinstrasse 1, 17491 Greifswald (Germany); Kneupner, Klaus; Kinna, David [JET-EFDA, Culham Science Centre, OX14 3DB Abingdon (United Kingdom)

2012-12-15

Highlights: Black-Right-Pointing-Pointer We describe 2 ways connecting PLCs to fusion control and data acquisition software. Black-Right-Pointing-Pointer At W7-X standardization of the PLC type eases the maintenance of the software. Black-Right-Pointing-Pointer At JET PLCs are interfaced with a daemon that hides the PLC specific part. Black-Right-Pointing-Pointer There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse 'black box protocol' approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and

What is mathematical logic?

CERN Document Server

Crossley, J N; Brickhill, CJ; Stillwell, JC

2010-01-01

Although mathematical logic can be a formidably abstruse topic, even for mathematicians, this concise book presents the subject in a lively and approachable fashion. It deals with the very important ideas in modern mathematical logic without the detailed mathematical work required of those with a professional interest in logic.The book begins with a historical survey of the development of mathematical logic from two parallel streams: formal deduction, which originated with Aristotle, Euclid, and others; and mathematical analysis, which dates back to Archimedes in the same era. The streams beg

Introduction to mathematical logic

CERN Document Server

Mendelson, Elliott

2015-01-01

The new edition of this classic textbook, Introduction to Mathematical Logic, Sixth Edition explores the principal topics of mathematical logic. It covers propositional logic, first-order logic, first-order number theory, axiomatic set theory, and the theory of computability. The text also discusses the major results of Gödel, Church, Kleene, Rosser, and Turing.The sixth edition incorporates recent work on Gödel's second incompleteness theorem as well as restoring an appendix on consistency proofs for first-order arithmetic. This appendix last appeared in the first edition. It is offered in th

A Logic for Choreographies

DEFF Research Database (Denmark)

Lopez, Hugo Andres; Carbone, Marco; Hildebrandt, Thomas

2010-01-01

We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL...... ), a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof...

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC for High Consequence Applications

Science.gov (United States)

2017-03-01

Programmable SoC™ is made possible through the use of ARM® Cortex ™-A9 MPCore™ Asymmetric Multiprocessing; processor configurations utilizing the...core ARM Cortex -A9 MPCore based Processing System (PS) and Programmable Logic (PL) portions. These features allow for two processors to run...SoC™ precludes a tightly-coupled lockstep approach between the two processors . Therefore, a loosely-coupled lockstep approach implemented by a

Fuzzy Logic and Arithmetical Hierarchy III

Czech Academy of Sciences Publication Activity Database

Hájek, Petr

2001-01-01

Roč. 68, č. 1 (2001), s. 129-142 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030004 Institutional research plan: AV0Z1030915 Keywords : fuzzy logic * basic fuzzy logic * Lukasiewicz logic * Godel logic * product logic * arithmetical hierarchy Subject RIV: BA - General Mathematics

Modern logic and quantum mechanics

International Nuclear Information System (INIS)

Garden, R.W.

1984-01-01

The book applies the methods of modern logic and probabilities to ''interpreting'' quantum mechanics. The subject is described and discussed under the chapter headings: classical and quantum mechanics, modern logic, the propositional logic of mechanics, states and measurement in mechanics, the traditional analysis of probabilities, the probabilities of mechanics and the model logic of predictions. (U.K.)

Semantic theory for logic programming

Energy Technology Data Exchange (ETDEWEB)

Brown, F M

1981-01-01

The author axiomatizes a number of meta theoretic concepts which have been used in logic programming, including: meaning, logical truth, nonentailment, assertion and erasure, thus showing that these concepts are logical in nature and need not be defined as they have previously been defined in terms of the operations of any particular interpreter for logic programs. 10 references.

Logic and Learning

DEFF Research Database (Denmark)

Hendricks, Vincent Fella; Gierasimczuk, Nina; de Jong, Dick

2014-01-01

Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study of inform......Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study...... of information processing, but likewise helped bring logic and learning in close proximity. This proximity relation is examined with respect to learning and belief revision, updating and efficiency, and with respect to how learnability fits in the greater scheme of dynamic epistemic logic and scientific method....