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Sample records for programmable logic gates

  1. Universal programmable logic gate and routing method

    Science.gov (United States)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  2. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  3. Programmable logic controller performance enhancement by field programmable gate array based design.

    Science.gov (United States)

    Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

    2015-01-01

    PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

  4. Reliability evaluation programmable logic devices

    International Nuclear Information System (INIS)

    Srivani, L.; Murali, N.; Thirugnana Murthy, D.; Satya Murty, S.A.V.

    2014-01-01

    Programmable Logic Devices (PLD) are widely used as basic building modules in high integrity systems, considering their robust features such as gate density, performance, speed etc. PLDs are used to implement digital design such as bus interface logic, control logic, sequencing logic, glue logic etc. Due to semiconductor evolution, new PLDs with state-of-the-art features are arriving to the market. Since these devices are reliable as per the manufacturer's specification, they were used in the design of safety systems. But due to their reduced market life, the availability of performance data is limited. So evaluating the PLD before deploying in a safety system is very important. This paper presents a survey on the use of PLDs in the nuclear domain and the steps involved in the evaluation of PLD using Quantitative Accelerated Life Testing. (author)

  5. Reversible logic gates on Physarum Polycephalum

    International Nuclear Information System (INIS)

    Schumann, Andrew

    2015-01-01

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

  6. All optical programmable logic array (PLA)

    Science.gov (United States)

    Hiluf, Dawit

    2018-03-01

    A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

  7. Flexible programmable logic module

    Science.gov (United States)

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  8. Synthesizing biomolecule-based Boolean logic gates.

    Science.gov (United States)

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2013-02-15

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

  9. Synthesizing Biomolecule-based Boolean Logic Gates

    Science.gov (United States)

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  10. Programmable Array Logic Design

    International Nuclear Information System (INIS)

    Demon Handoyo; Djen Djen Djainal

    2007-01-01

    Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)

  11. Optical programmable Boolean logic unit.

    Science.gov (United States)

    Chattopadhyay, Tanay

    2011-11-10

    Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

  12. r-Universal reversible logic gates

    International Nuclear Information System (INIS)

    Vos, A de; Storme, L

    2004-01-01

    Reversible logic plays a fundamental role both in ultra-low power electronics and in quantum computing. It is therefore important to know which reversible logic gates can be used as building block for the reversible implementation of an arbitrary boolean function and which cannot

  13. Instantons in Self-Organizing Logic Gates

    Science.gov (United States)

    Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

    2018-03-01

    Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

  14. Molecular sensors and molecular logic gates

    International Nuclear Information System (INIS)

    Georgiev, N.; Bojinov, V.

    2013-01-01

    Full text: The rapid grow of nanotechnology field extended the concept of a macroscopic device to the molecular level. Because of this reason the design and synthesis of (supra)-molecular species capable of mimicking the functions of macroscopic devices are currently of great interest. Molecular devices operate via electronic and/or nuclear rearrangements and, like macroscopic devices, need energy to operate and communicate between their elements. The energy needed to make a device work can be supplied as chemical energy, electrical energy, or light. Luminescence is one of the most useful techniques to monitor the operation of molecular-level devices. This fact determinates the synthesis of novel fluorescence compounds as a considerable and inseparable part of nanoscience development. Further miniaturization of semiconductors in electronic field reaches their limit. Therefore the design and construction of molecular systems capable of performing complex logic functions is of great scientific interest now. In semiconductor devices the logic gates work using binary logic, where the signals are encoded as 0 and 1 (low and high current). This process is executable on molecular level by several ways, but the most common are based on the optical properties of the molecule switches encoding the low and high concentrations of the input guest molecules and the output fluorescent intensities with binary 0 and 1 respectively. The first proposal to execute logic operations at the molecular level was made in 1988, but the field developed only five years later when the analogy between molecular switches and logic gates was experimentally demonstrated by de Silva. There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR and XNOR and all of them were achieved by molecules, the fluorescence switching as well. key words: fluorescence, molecular sensors, molecular logic gates

  15. Classical Boolean logic gates with quantum systems

    International Nuclear Information System (INIS)

    Renaud, N; Joachim, C

    2011-01-01

    An analytical method is proposed to implement any classical Boolean function in a small quantum system by taking the advantage of its electronic transport properties. The logical input, α = {α 1 , ..., α N }, is used to control well-identified parameters of the Hamiltonian of the system noted H 0 (α). The logical output is encoded in the tunneling current intensity passing through the quantum system when connected to conducting electrodes. It is demonstrated how to implement the six symmetric two-input/one-output Boolean functions in a quantum system. This system can be switched from one logic function to another by changing its structural parameters. The stability of the logic gates is discussed, perturbing the Hamiltonian with noise sources and studying the effect of decoherence.

  16. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    Science.gov (United States)

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  17. Quantum design rules for single molecule logic gates.

    Science.gov (United States)

    Renaud, N; Hliwa, M; Joachim, C

    2011-08-28

    Recent publications have demonstrated how to implement a NOR logic gate with a single molecule using its interaction with two surface atoms as logical inputs [W. Soe et al., ACS Nano, 2011, 5, 1436]. We demonstrate here how this NOR logic gate belongs to the general family of quantum logic gates where the Boolean truth table results from a full control of the quantum trajectory of the electron transfer process through the molecule by very local and classical inputs practiced on the molecule. A new molecule OR gate is proposed for the logical inputs to be also single metal atoms, one per logical input.

  18. Reconfigurable chaotic logic gates based on novel chaotic circuit

    International Nuclear Information System (INIS)

    Behnia, S.; Pazhotan, Z.; Ezzati, N.; Akhshani, A.

    2014-01-01

    Highlights: • A novel method for implementing logic gates based on chaotic maps is introduced. • The logic gates can be implemented without any changes in the threshold voltage. • The chaos-based logic gates may serve as basic components of future computing devices. - Abstract: The logical operations are one of the key issues in today’s computer architecture. Nowadays, there is a great interest in developing alternative ways to get the logic operations by chaos computing. In this paper, a novel implementation method of reconfigurable logic gates based on one-parameter families of chaotic maps is introduced. The special behavior of these chaotic maps can be utilized to provide same threshold voltage for all logic gates. However, there is a wide interval for choosing a control parameter for all reconfigurable logic gates. Furthermore, an experimental implementation of this nonlinear system is presented to demonstrate the robustness of computing capability of chaotic circuits

  19. Universal Programmable Logic Controller Software

    International Nuclear Information System (INIS)

    Mohd Arif Hamzah; Azhar Shamsudin; Fadil Ismail; Muhammad Nor Atan; Anwar Abdul Rahman

    2013-01-01

    Programmable Logic Controller (PLC) is an electronic hardware which is widely used in manufacturing or processing industries. It is also serve as the main control system hardware to run the production and manufacturing process. There are more than ten (10) well known company producing PLC hardware, with their own specialties, including the method of programming and language used. Malaysia Nuclear Agency have various plant and equipment, runs and control by PLC, such as Mintex Sinagama Plant, Alurtron Plant, and few laboratory equipment. Since all the equipment and plant are equipped with various brand or different manufacture of PLC, it creates difficulties to the supporting staff to master the control program. The same problems occur for new application of this hardware, since there no policies to purchase only one specific brand of PLC. (author)

  20. Excitonic AND Logic Gates on DNA Brick Nanobreadboards

    Science.gov (United States)

    2015-01-01

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

  1. Integration of biomolecular logic gates with field-effect transducers

    Energy Technology Data Exchange (ETDEWEB)

    Poghossian, A., E-mail: a.poghossian@fz-juelich.de [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany); Malzahn, K. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Abouzar, M.H. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany); Mehndiratta, P. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Katz, E. [Department of Chemistry and Biomolecular Science, NanoBio Laboratory (NABLAB), Clarkson University, Potsdam, NY 13699-5810 (United States); Schoening, M.J. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany)

    2011-11-01

    Highlights: > Enzyme-based AND/OR logic gates are integrated with a capacitive field-effect sensor. > The AND/OR logic gates compose of multi-enzyme system immobilised on sensor surface. > Logic gates were activated by different combinations of chemical inputs (analytes). > The logic output (pH change) produced by the enzymes was read out by the sensor. - Abstract: The integration of biomolecular logic gates with field-effect devices - the basic element of conventional electronic logic gates and computing - is one of the most attractive and promising approaches for the transformation of biomolecular logic principles into macroscopically useable electrical output signals. In this work, capacitive field-effect EIS (electrolyte-insulator-semiconductor) sensors based on a p-Si-SiO{sub 2}-Ta{sub 2}O{sub 5} structure modified with a multi-enzyme membrane have been used for electronic transduction of biochemical signals processed by enzyme-based OR and AND logic gates. The realised OR logic gate composes of two enzymes (glucose oxidase and esterase) and was activated by ethyl butyrate or/and glucose. The AND logic gate composes of three enzymes (invertase, mutarotase and glucose oxidase) and was activated by two chemical input signals: sucrose and dissolved oxygen. The developed integrated enzyme logic gates produce local pH changes at the EIS sensor surface as a result of biochemical reactions activated by different combinations of chemical input signals, while the pH value of the bulk solution remains unchanged. The pH-induced charge changes at the gate-insulator (Ta{sub 2}O{sub 5}) surface of the EIS transducer result in an electronic signal corresponding to the logic output produced by the immobilised enzymes. The logic output signals have been read out by means of a constant-capacitance method.

  2. Integration of biomolecular logic gates with field-effect transducers

    International Nuclear Information System (INIS)

    Poghossian, A.; Malzahn, K.; Abouzar, M.H.; Mehndiratta, P.; Katz, E.; Schoening, M.J.

    2011-01-01

    Highlights: → Enzyme-based AND/OR logic gates are integrated with a capacitive field-effect sensor. → The AND/OR logic gates compose of multi-enzyme system immobilised on sensor surface. → Logic gates were activated by different combinations of chemical inputs (analytes). → The logic output (pH change) produced by the enzymes was read out by the sensor. - Abstract: The integration of biomolecular logic gates with field-effect devices - the basic element of conventional electronic logic gates and computing - is one of the most attractive and promising approaches for the transformation of biomolecular logic principles into macroscopically useable electrical output signals. In this work, capacitive field-effect EIS (electrolyte-insulator-semiconductor) sensors based on a p-Si-SiO 2 -Ta 2 O 5 structure modified with a multi-enzyme membrane have been used for electronic transduction of biochemical signals processed by enzyme-based OR and AND logic gates. The realised OR logic gate composes of two enzymes (glucose oxidase and esterase) and was activated by ethyl butyrate or/and glucose. The AND logic gate composes of three enzymes (invertase, mutarotase and glucose oxidase) and was activated by two chemical input signals: sucrose and dissolved oxygen. The developed integrated enzyme logic gates produce local pH changes at the EIS sensor surface as a result of biochemical reactions activated by different combinations of chemical input signals, while the pH value of the bulk solution remains unchanged. The pH-induced charge changes at the gate-insulator (Ta 2 O 5 ) surface of the EIS transducer result in an electronic signal corresponding to the logic output produced by the immobilised enzymes. The logic output signals have been read out by means of a constant-capacitance method.

  3. Block QCA Fault-Tolerant Logic Gates

    Science.gov (United States)

    Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

    2003-01-01

    Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA

  4. Applications of field-programmable gate arrays in scientific research

    CERN Document Server

    Sadrozinski, Hartmut F W

    2011-01-01

    Focusing on resource awareness in field-programmable gate array (FPGA) design, Applications of Field-Programmable Gate Arrays in Scientific Research covers the principle of FPGAs and their functionality. It explores a host of applications, ranging from small one-chip laboratory systems to large-scale applications in ""big science."" The book first describes various FPGA resources, including logic elements, RAM, multipliers, microprocessors, and content-addressable memory. It then presents principles and methods for controlling resources, such as process sequencing, location constraints, and in

  5. Logic-Gate Functions in Chemomechanical Materials.

    Science.gov (United States)

    Schneider, Hans-Jörg

    2017-09-06

    Chemomechanical polymers that change their shape or volume on stimulation by multiple external chemical signals, particularly on the basis of selective molecular recognition, are discussed. Several examples illustrate how such materials, usually in the form of hydrogels, can be used for the design of chemically triggered valves or artificial muscles and applied, for example, in self-healing materials or drug delivery. The most attractive feature of such materials is that they can combine sensor and actuator within single units, from nano- to macrosize. Simultaneous action of a cofactor allows selective response in the sense of AND logic gates by, for example, amino acids and peptides, which without the presence of a second effector do not induce any changes. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Digital systems from logic gates to processors

    CERN Document Server

    Deschamps, Jean-Pierre; Terés, Lluís

    2017-01-01

    This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop “traditional” Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, ...

  7. Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors.

    Science.gov (United States)

    Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin

    2016-06-22

    In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.

  8. Silicon photonic crystal all-optical logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

    2013-01-03

    All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

  9. Optical reversible programmable Boolean logic unit.

    Science.gov (United States)

    Chattopadhyay, Tanay

    2012-07-20

    Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

  10. Toward spin-based Magneto Logic Gate in Graphene

    Science.gov (United States)

    Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

    Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

  11. Fredkin gates for finite-valued reversible and conservative logics

    International Nuclear Information System (INIS)

    Cattaneo, G; Leporati, A; Leporini, R

    2002-01-01

    The basic principles and results of conservative logic introduced by Fredkin and Toffoli in 1982, on the basis of a seminal paper of Landauer, are extended to d-valued logics, with a special attention to three-valued logics. Different approaches to d-valued logics are examined in order to determine some possible universal sets of logic primitives. In particular, we consider the typical connectives of Lukasiewicz and Goedel logics, as well as Chang's MV-algebras. As a result, some possible three-valued and d-valued universal gates are described which realize a functionally complete set of fundamental connectives. Two no-go theorems are also proved

  12. A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

    Science.gov (United States)

    Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

    2016-06-28

    Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

  13. Error-Transparent Quantum Gates for Small Logical Qubit Architectures

    Science.gov (United States)

    Kapit, Eliot

    2018-02-01

    One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

  14. Shape changing collisions of optical solitons, universal logic gates ...

    Indian Academy of Sciences (India)

    ... in optical media such as multicore fibers, photorefractive materials and so on. ... of logic gates and Turing equivalent all optical computers in homogeneous bulk media as shown by Steiglitz recently. ... Pramana – Journal of Physics | News.

  15. Transcending binary logic by gating three coupled quantum dots.

    Science.gov (United States)

    Klein, Michael; Rogge, S; Remacle, F; Levine, R D

    2007-09-01

    Physical considerations supported by numerical solution of the quantum dynamics including electron repulsion show that three weakly coupled quantum dots can robustly execute a complete set of logic gates for computing using three valued inputs and outputs. Input is coded as gating (up, unchanged, or down) of the terminal dots. A nanosecond time scale switching of the gate voltage requires careful numerical propagation of the dynamics. Readout is the charge (0, 1, or 2 electrons) on the central dot.

  16. Quantum logic gates based on ballistic transport in graphene

    Energy Technology Data Exchange (ETDEWEB)

    Dragoman, Daniela [Faculty of Physics, University of Bucharest, P.O. Box MG-11, 077125 Bucharest (Romania); Academy of Romanian Scientists, Splaiul Independentei 54, 050094 Bucharest (Romania); Dragoman, Mircea, E-mail: mircea.dragoman@imt.ro [National Institute for Research and Development in Microtechnology (IMT), P.O. Box 38-160, 023573 Bucharest (Romania)

    2016-03-07

    The paper presents various configurations for the implementation of graphene-based Hadamard, C-phase, controlled-NOT, and Toffoli gates working at room temperature. These logic gates, essential for any quantum computing algorithm, involve ballistic graphene devices for qubit generation and processing and can be fabricated using existing nanolithographical techniques. All quantum gate configurations are based on the very large mean-free-paths of carriers in graphene at room temperature.

  17. All-optical symmetric ternary logic gate

    Science.gov (United States)

    Chattopadhyay, Tanay

    2010-09-01

    Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.

  18. Proposal of unilateral single-flux-quantum logic gate

    International Nuclear Information System (INIS)

    Mikaye, H.; Fukaya, N.; Okabe, Y.; Sugamo, T.

    1985-01-01

    A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible

  19. Molecular logic gates: the past, present and future.

    Science.gov (United States)

    Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U

    2018-04-03

    The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.

  20. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    Science.gov (United States)

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-01-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

  1. A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

    KAUST Repository

    Tella, Sherif Adekunle

    2018-04-30

    Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

  2. A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

    KAUST Repository

    Tella, Sherif Adekunle; Alcheikh, Nouha; Younis, Mohammad I.

    2018-01-01

    Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

  3. Implementing conventional logic unconventionally: photochromic molecular populations as registers and logic gates.

    Science.gov (United States)

    Chaplin, J C; Russell, N A; Krasnogor, N

    2012-07-01

    In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

  4. Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates.

    Science.gov (United States)

    Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar

    2012-12-26

    The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.

  5. Field-Programmable Logic Devices with Optical Input Output

    Science.gov (United States)

    Szymanski, Ted H.; Saint-Laurent, Martin; Tyan, Victor; Au, Albert; Supmonchai, Boonchuay

    2000-02-01

    A field-programmable logic device (FPLD) with optical I O is described. FPLD s with optical I O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA s) on a 2 mm 2 mm die. The devices were fabricated through the Lucent Technologies Advanced Research Projects Agency Consortium for Optical and Optoelectronic Technologies in Computing (Lucent ARPA COOP) workshop by use of 0.5- m complementary metal-oxide semiconductor self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 4 crossbar switches, which can realize more than 190 10 6 unique programmable input output permutations. The same device scaled to a 2 cm 2 cm substrate could support as many as 4000 optical I O and 1 Tbit s of optical I O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

  6. Cascading of molecular logic gates for advanced functions: a self-reporting, activatable photosensitizer.

    Science.gov (United States)

    Erbas-Cakmak, Sundus; Akkaya, Engin U

    2013-10-18

    Logical progress: Independent molecular logic gates have been designed and characterized. Then, the individual molecular logic gates were coerced to work together within a micelle. Information relay between the two logic gates was achieved through the intermediacy of singlet oxygen. Working together, these concatenated logic gates result in a self-reporting and activatable photosensitizer. GSH=glutathione. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. A single nano cantilever as a reprogrammable universal logic gate

    KAUST Repository

    Chappanda, K. N.

    2017-02-24

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

  8. A single nano cantilever as a reprogrammable universal logic gate

    International Nuclear Information System (INIS)

    Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J

    2017-01-01

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)

  9. Integrated plant automation using programmable logic controllers

    International Nuclear Information System (INIS)

    Qureshi, S.A.

    2002-01-01

    In the world of automation the Programmable Logic Controller (PLC) has became for control. It now not only replaces the earlier relay logic controls but also has taken over many additional control functions. Initially the PLC was used to replace relay logic, but is ever-increasing range of functions means that it is found in many and more complex applications. As the structure of the PLC is based on the same principles as those employed in computer architecture, it is capable of performance not only relay switching tasks, but also other applications such as counting, calculating, comparing and the processing of analogue signals. Due to the simplicity of entering and modifying the programmed instructions to suit the requirements of the process under control, the PLC is truly a versatile and flexible device that can be employed easily and efficiently to repeatedly control tasks that vary in nature and complexes. A photograph of the Siemens S-5 95U. To illustrate the advantage of using a PLC over a traditional relay logic system, consider a control system with 20 input/output points. This assembly could comprise 60-80 relays, some counter/timers and a great deal of wiring. This assembly would be cumbersome with a power consumption of 30-40VA. A considerable time would be required to design, test and commission the assembly and once it is in full working order any desired modification, even of minor nature, could require major hardware changes. (author)

  10. Dependable Design Flow for Protection Systems using Programmable Logic Devices

    CERN Document Server

    Kwiatkowski, M

    2011-01-01

    Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. The final synthesis result, used to generate the bit-stream to program the device, must be shown to meet the design’s requirements. This paper describes how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example is given for one of the critical functions of the Safe Machine Parameters (SMP) system, used in the protection of the Large Hadron Collider (LHC) at CERN. CERN is also working towards an adaptation of the IEC- 61508 lifecycle designed for Machine Protection Systems (MPS), and the High Energy Physics environment, implementation of a protection function in FPGA code is only one small step of this lifecycle. The ultimate aim of this project is to cre...

  11. A reconfigurable NAND/NOR genetic logic gate.

    Science.gov (United States)

    Goñi-Moreno, Angel; Amos, Martyn

    2012-09-18

    Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.

  12. Tackling systematic errors in quantum logic gates with composite rotations

    International Nuclear Information System (INIS)

    Cummins, Holly K.; Llewellyn, Gavin; Jones, Jonathan A.

    2003-01-01

    We describe the use of composite rotations to combat systematic errors in single-qubit quantum logic gates and discuss three families of composite rotations which can be used to correct off-resonance and pulse length errors. Although developed and described within the context of nuclear magnetic resonance quantum computing, these sequences should be applicable to any implementation of quantum computation

  13. Microdroplet-based universal logic gates by electrorheological fluid

    KAUST Repository

    Zhang, Mengying

    2011-01-01

    We demonstrate a uniquely designed microfluid logic gate with universal functionality, which is capable of conducting all 16 logic operations in one chip, with different input voltage combinations. A kind of smart colloid, giant electrorheological (GER) fluid, functions as the translation media among fluidic, electronic and mechanic information, providing us with the capability of performing large integrations either on-chip or off-chip, while the on-chip hybrid circuit is formed by the interconnection of the electric components and fluidic channels, where the individual microdroplets travelling in a channel represents a bit. The universal logic gate reveals the possibilities of achieving a large-scale microfluidic processor with more complexity for on-chip processing for biological, chemical as well as computational experiments. © 2011 The Royal Society of Chemistry.

  14. Rapidly reconfigurable all-optical universal logic gate

    Science.gov (United States)

    Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

    2010-09-07

    A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

  15. Supervisory control system implemented in programmable logical controller web server

    OpenAIRE

    Milavec, Simon

    2012-01-01

    In this thesis, we study the feasibility of supervisory control and data acquisition (SCADA) system realisation in a web server of a programmable logic controller. With the introduction of Ethernet protocol to the area of process control, the more powerful programmable logic controllers obtained integrated web servers. The web server of a programmable logic controller, produced by Siemens, will also be described in this thesis. Firstly, the software and the hardware equipment used for real...

  16. Divide and control: split design of multi-input DNA logic gates.

    Science.gov (United States)

    Gerasimova, Yulia V; Kolpashchikov, Dmitry M

    2015-01-18

    Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.

  17. A new fast and programmable trigger logic

    International Nuclear Information System (INIS)

    Fucci, A.; Amendolia, S.R.; Bertolucci, E.; Bottigli, U.; Bradaschia, C.; Foa, L.; Giazotto, A.; Giorgi, M.; Givoletti, M.; Lucardesi, P.; Menzione, A.; Passuello, D.; Quaglia, M.; Ristori, L.; Rolandi, L.; Salvadori, P.; Scribano, A.; Stanga, R.; Stefanini, A.; Vincelli, M.L.

    1977-01-01

    The NA1 (FRAMM) experiment, under construction for the CERN-SPS North Area, deals with more than 1000 counter signals which have to be combined together in order to build sophisticated and highly selective triggers. These requirements have led to the development of a low cost, combinatorial, fast electronics which can replace, in an advantageous way the standard NIM electronics at the trigger level. The essential performances of the basic circuit are: 1) programmability of any desired logical expression; 2) trigger time independent of the chosen expression; 3) reduced cost and compactness due to the use of commercial RAMs, PROMs, and PLAs; 4) short delay, less than 20 ns, between input and output pulses. (Auth.)

  18. Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

    Science.gov (United States)

    Straka, Bartholomew

    2013-01-01

    Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

  19. Fast quantum logic gates with trapped-ion qubits

    Science.gov (United States)

    Schäfer, V. M.; Ballance, C. J.; Thirumalai, K.; Stephenson, L. J.; Ballance, T. G.; Steane, A. M.; Lucas, D. M.

    2018-03-01

    Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural ‘speed limit’ of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds—less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually

  20. Microwave quantum logic gates for trapped ions.

    Science.gov (United States)

    Ospelkaus, C; Warring, U; Colombe, Y; Brown, K R; Amini, J M; Leibfried, D; Wineland, D J

    2011-08-10

    Control over physical systems at the quantum level is important in fields as diverse as metrology, information processing, simulation and chemistry. For trapped atomic ions, the quantized motional and internal degrees of freedom can be coherently manipulated with laser light. Similar control is difficult to achieve with radio-frequency or microwave radiation: the essential coupling between internal degrees of freedom and motion requires significant field changes over the extent of the atoms' motion, but such changes are negligible at these frequencies for freely propagating fields. An exception is in the near field of microwave currents in structures smaller than the free-space wavelength, where stronger gradients can be generated. Here we first manipulate coherently (on timescales of 20 nanoseconds) the internal quantum states of ions held in a microfabricated trap. The controlling magnetic fields are generated by microwave currents in electrodes that are integrated into the trap structure. We also generate entanglement between the internal degrees of freedom of two atoms with a gate operation suitable for general quantum computation; the entangled state has a fidelity of 0.76(3), where the uncertainty denotes standard error of the mean. Our approach, which involves integrating the quantum control mechanism into the trapping device in a scalable manner, could be applied to quantum information processing, simulation and spectroscopy.

  1. Logic-type Schmitt circuit using multi-valued gates

    Science.gov (United States)

    Wakui, M.; Tanaka, M.

    Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.

  2. Chemical switches and logic gates based on surface modified semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Konrad, Szacilowski; Wojciech, Macyk [Jagiellonian Univ., Dept. of Chemistry, Krakow (Poland)

    2006-02-15

    Photoelectrochemical properties of multicomponent photo-electrodes based on titanium dioxide and cadmium sulfide powders modified with hexacyanoferrate complexes have been examined. Photocurrent responses were recorded as functions of applied potential and photon energy. Surprisingly, the photocurrent can be switched between positive and negative values as a result of potential or photon energy changes. This new effect called Photo Electrochemical Photocurrent Switching (PEPS) opens a possibility of new chemical switches and logic gates construction. Boolean logic analysis and a tentative mechanism of the device are discussed. (authors)

  3. Synchronous implementation of optoelectronic NOR and XNOR logic gates using parallel synchronization of three chaotic lasers

    International Nuclear Information System (INIS)

    Yan Sen-Lin

    2014-01-01

    The parallel synchronization of three chaotic lasers is used to emulate optoelectronic logic NOR and XNOR gates via modulating the light and the current. We deduce a logical computational equation that governs the chaotic synchronization, logical input, and logical output. We construct fundamental gates based on the three chaotic lasers and define the computational principle depending on the parallel synchronization. The logic gate can be implemented by appropriately synchronizing two chaotic lasers. The system shows practicability and flexibility because it can emulate synchronously an XNOR gate, two NOR gates, and so on. The synchronization can still be deteceted when mismatches exist with a certain range. (general)

  4. Universal logic gates via liquid-electronic hybrid divider

    KAUST Repository

    Zhou, Bingpu

    2012-01-01

    We demonstrated two-input microdroplet-based universal logic gates using a liquid-electronic hybrid divider. All 16 Boolean logic functions have been realized by manipulating the applied voltages. The novel platform consists of a microfluidic chip with integrated microdroplet detectors and external electronic components. The microdroplet detectors act as the communication media for fluidic and electronic information exchange. The presence or absence of microdroplets at the detector translates into the binary signal 1 or 0. The embedded micro-mechanical pneumatically actuated valve (PAV), fabricated using the well-developed multilayer soft lithography technique, offers biocompatibility, flexibility and accuracy for the on-chip realization of different logic functions. The microfluidic chip can be scaled up to construct large-scale microfluidic logic computation. On the other hand, the microfluidic chip with a specific logic function can be applied to droplet-based chemical reactions for on-demand bio or chemical analysis. Our experimental results have presented an autonomously driven, precision-controlled microfluidic chip for chemical reactions based on the IF logic function. © 2012 The Royal Society of Chemistry.

  5. Multi-Valued Logic Gates, Continuous Sensitivity, Reversibility, and Threshold Functions

    OpenAIRE

    İlhan, Aslı Güçlükan; Ünlü, Özgün

    2016-01-01

    We define an invariant of a multi-valued logic gate by considering the number of certain threshold functions associated with the gate. We call this invariant the continuous sensitivity of the gate. We discuss a method for analysing continuous sensitivity of a multi-valued logic gate by using experimental data about the gate. In particular, we will show that this invariant provides a lower bound for the sensitivity of a boolean function considered as a multi-valued logic gate. We also discuss ...

  6. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    Science.gov (United States)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  7. Parallel Transport Quantum Logic Gates with Trapped Ions.

    Science.gov (United States)

    de Clercq, Ludwig E; Lo, Hsiang-Yu; Marinelli, Matteo; Nadlinger, David; Oswald, Robin; Negnevitsky, Vlad; Kienzler, Daniel; Keitch, Ben; Home, Jonathan P

    2016-02-26

    We demonstrate single-qubit operations by transporting a beryllium ion with a controlled velocity through a stationary laser beam. We use these to perform coherent sequences of quantum operations, and to perform parallel quantum logic gates on two ions in different processing zones of a multiplexed ion trap chip using a single recycled laser beam. For the latter, we demonstrate individually addressed single-qubit gates by local control of the speed of each ion. The fidelities we observe are consistent with operations performed using standard methods involving static ions and pulsed laser fields. This work therefore provides a path to scalable ion trap quantum computing with reduced requirements on the optical control complexity.

  8. Unimolecular Logic Gate with Classical Input by Single Gold Atoms.

    Science.gov (United States)

    Skidin, Dmitry; Faizy, Omid; Krüger, Justus; Eisenhut, Frank; Jancarik, Andrej; Nguyen, Khanh-Hung; Cuniberti, Gianaurelio; Gourdon, Andre; Moresco, Francesca; Joachim, Christian

    2018-02-27

    By a combination of solution and on-surface chemistry, we synthesized an asymmetric starphene molecule with two long anthracenyl input branches and a short naphthyl output branch on the Au(111) surface. Starting from this molecule, we could demonstrate the working principle of a single molecule NAND logic gate by selectively contacting single gold atoms by atomic manipulation to the longer branches of the molecule. The logical input "1" ("0") is defined by the interaction (noninteraction) of a gold atom with one of the input branches. The output is measured by scanning tunneling spectroscopy following the shift in energy of the electronic tunneling resonances at the end of the short branch of the molecule.

  9. High-order noise filtering in nontrivial quantum logic gates.

    Science.gov (United States)

    Green, Todd; Uys, Hermann; Biercuk, Michael J

    2012-07-13

    Treating the effects of a time-dependent classical dephasing environment during quantum logic operations poses a theoretical challenge, as the application of noncommuting control operations gives rise to both dephasing and depolarization errors that must be accounted for in order to understand total average error rates. We develop a treatment based on effective Hamiltonian theory that allows us to efficiently model the effect of classical noise on nontrivial single-bit quantum logic operations composed of arbitrary control sequences. We present a general method to calculate the ensemble-averaged entanglement fidelity to arbitrary order in terms of noise filter functions, and provide explicit expressions to fourth order in the noise strength. In the weak noise limit we derive explicit filter functions for a broad class of piecewise-constant control sequences, and use them to study the performance of dynamically corrected gates, yielding good agreement with brute-force numerics.

  10. Prospects of luminescence based molecular scale logic gates and logic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Speiser, Shammai, E-mail: speiser@technion.ac.il

    2016-01-15

    In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder.

  11. Prospects of luminescence based molecular scale logic gates and logic circuits

    International Nuclear Information System (INIS)

    Speiser, Shammai

    2016-01-01

    In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder

  12. Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

    Science.gov (United States)

    Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

    2014-07-01

    DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

  13. Parallel logic gates in synthetic gene networks induced by non-Gaussian noise.

    Science.gov (United States)

    Xu, Yong; Jin, Xiaoqin; Zhang, Huiqing

    2013-11-01

    The recent idea of logical stochastic resonance is verified in synthetic gene networks induced by non-Gaussian noise. We realize the switching between two kinds of logic gates under optimal moderate noise intensity by varying two different tunable parameters in a single gene network. Furthermore, in order to obtain more logic operations, thus providing additional information processing capacity, we obtain in a two-dimensional toggle switch model two complementary logic gates and realize the transformation between two logic gates via the methods of changing different parameters. These simulated results contribute to improve the computational power and functionality of the networks.

  14. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    International Nuclear Information System (INIS)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-01-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries. (semiconductor integrated circuits)

  15. Enzymatic AND logic gates operated under conditions characteristic of biomedical applications.

    Science.gov (United States)

    Melnikov, Dmitriy; Strack, Guinevere; Zhou, Jian; Windmiller, Joshua Ray; Halámek, Jan; Bocharova, Vera; Chuang, Min-Chieh; Santhosh, Padmanabhan; Privman, Vladimir; Wang, Joseph; Katz, Evgeny

    2010-09-23

    Experimental and theoretical analyses of the lactate dehydrogenase and glutathione reductase based enzymatic AND logic gates in which the enzymes and their substrates serve as logic inputs are performed. These two systems are examples of the novel, previously unexplored class of biochemical logic gates that illustrate potential biomedical applications of biochemical logic. They are characterized by input concentrations at logic 0 and 1 states corresponding to normal and pathophysiological conditions. Our analysis shows that the logic gates under investigation have similar noise characteristics. Both significantly amplify random noise present in inputs; however, we establish that for realistic widths of the input noise distributions, it is still possible to differentiate between the logic 0 and 1 states of the output. This indicates that reliable detection of pathophysiological conditions is indeed possible with such enzyme logic systems.

  16. An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

    Science.gov (United States)

    Kazemi, Mohammad

    2017-11-10

    The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

  17. Chaotic logic gate: A new approach in set and design by genetic algorithm

    International Nuclear Information System (INIS)

    Beyki, Mahmood; Yaghoobi, Mahdi

    2015-01-01

    How to reconfigure a logic gate is an attractive subject for different applications. Chaotic systems can yield a wide variety of patterns and here we use this feature to produce a logic gate. This feature forms the basis for designing a dynamical computing device that can be rapidly reconfigured to become any wanted logical operator. This logic gate that can reconfigure to any logical operator when placed in its chaotic state is called chaotic logic gate. The reconfiguration realize by setting the parameter values of chaotic logic gate. In this paper we present mechanisms about how to produce a logic gate based on the logistic map in its chaotic state and genetic algorithm is used to set the parameter values. We use three well-known selection methods used in genetic algorithm: tournament selection, Roulette wheel selection and random selection. The results show the tournament selection method is the best method for set the parameter values. Further, genetic algorithm is a powerful tool to set the parameter values of chaotic logic gate

  18. Hydraulic logic gates: building a digital water computer

    Science.gov (United States)

    Taberlet, Nicolas; Marsal, Quentin; Ferrand, Jérémy; Plihon, Nicolas

    2018-03-01

    In this article, we propose an easy-to-build hydraulic machine which serves as a digital binary computer. We first explain how an elementary adder can be built from test tubes and pipes (a cup filled with water representing a 1, and empty cup a 0). Using a siphon and a slow drain, the proposed setup combines AND and XOR logical gates in a single device which can add two binary digits. We then show how these elementary units can be combined to construct a full 4-bit adder. The sequencing of the computation is discussed and a water clock can be incorporated so that the machine can run without any exterior intervention.

  19. Design of polarization encoded all-optical 4-valued MAX logic gate and its applications

    Science.gov (United States)

    Chattopadhyay, Tanay; Nath Roy, Jitendra

    2013-07-01

    Quaternary maximum (QMAX) gate is one type of multi-valued logic gate. An all-optical scheme of polarization encoded quaternary (4-valued) MAX logic gate with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) based fiber interferometric switch is proposed and described. For the quaternary information processing in optics, the quaternary number (0, 1, 2, 3) can be represented by four discrete polarized states of light. Numerical simulation result confirming the described methods is given in this paper. Some applications of MAX gate in logical operation and memory device are also given.

  20. Construction of a fuzzy and all Boolean logic gates based on DNA

    DEFF Research Database (Denmark)

    M. Zadegan, Reza; Jepsen, Mette D E; Hildebrandt, Lasse

    2015-01-01

    to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive...... DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics....

  1. Programming the quorum sensing-based AND gate in Shewanella oneidensis for logic gated-microbial fuel cells.

    Science.gov (United States)

    Hu, Yidan; Yang, Yun; Katz, Evgeny; Song, Hao

    2015-03-11

    An AND logic gate based on a synthetic quorum-sensing (QS) module was constructed in a Shewanella oneidensis MR-1 mtrA knockout mutant. The presence of two input signals activated the expression of a periplasmic decaheme cytochrome MtrA to regenerate the extracellular electron transfer conduit, enabling the construction of AND-gated microbial fuel cells.

  2. Programmable logic control applied to a coal preparation plant complex

    Energy Technology Data Exchange (ETDEWEB)

    Krahenbil, L W

    1979-02-01

    The programmable Logic Controller (PLC), at its present stage of evolution, is now considered as a mature control system. The PLC combines the solid-state reliability of hard-wired logic and computer control systems with the simplicity of a relay ladder logic. Relay symbolic programming through a function-oriented keyboard provides a means which plant personnel can easily become accoustomed to work with. In a large coal facility, it is shown that the control engineer can provide improved control flexibility with the advanced capabilities of the PLC.

  3. Field Programmable Gate Array-based I and C Safety System

    International Nuclear Information System (INIS)

    Kim, Hyun Jeong; Kim, Koh Eun; Kim, Young Geul; Kwon, Jong Soo

    2014-01-01

    Programmable Logic Controller (PLC)-based I and C safety system used in the operating nuclear power plants has the disadvantages of the Common Cause Failure (CCF), high maintenance costs and quick obsolescence, and then it is necessary to develop the other platform to replace the PLC. The Field Programmable Gate Array (FPGA)-based Instrument and Control (I and C) safety system is safer and more economical than Programmable Logic Controller (PLC)-based I and C safety system. Therefore, in the future, FPGA-based I and C safety system will be able to replace the PLC-based I and C safety system in the operating and the new nuclear power plants to get benefited from its safety and economic advantage. FPGA-based I and C safety system shall be implemented and verified by applying the related requirements to perform the safety function

  4. Field Programmable Gate Array-based I and C Safety System

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Hyun Jeong; Kim, Koh Eun; Kim, Young Geul; Kwon, Jong Soo [KEPCO, Daejeon (Korea, Republic of)

    2014-08-15

    Programmable Logic Controller (PLC)-based I and C safety system used in the operating nuclear power plants has the disadvantages of the Common Cause Failure (CCF), high maintenance costs and quick obsolescence, and then it is necessary to develop the other platform to replace the PLC. The Field Programmable Gate Array (FPGA)-based Instrument and Control (I and C) safety system is safer and more economical than Programmable Logic Controller (PLC)-based I and C safety system. Therefore, in the future, FPGA-based I and C safety system will be able to replace the PLC-based I and C safety system in the operating and the new nuclear power plants to get benefited from its safety and economic advantage. FPGA-based I and C safety system shall be implemented and verified by applying the related requirements to perform the safety function.

  5. Final Report and Documentation for the PLD11 Multipurpose Programmable Logic VME Board Design

    International Nuclear Information System (INIS)

    Hutchinson, Robert L.; Pierson, Lyndon G.; Robertson, Perry J.; Tarman, Thomas D.; Witzke, Edward L.

    1999-01-01

    The PLD11 board is a 9U VME board containing 11 Altera 10K100 Programmable Logic Devices, controlled impedance clock tree, VME interface, programming inteface, 0C3 (155 Mbps) interface and serial port. The 11 Altera 10K100 Programmable Logic Devices arranged to provide four 96 bit wide buses for a total of 384 parallel digital data lines in and out of the board that can operate up to 100 Mhz for a aggrigate throughput of 38.4 Gpbs. The 14.44'' X 15.75'' board has over 1.1 million programmable gates that can be programmed through a serial interace. The board contains a clock reference and 50 ohm clock distribution tree that can drive each of the eleven 10K100 devices with two critically timed clock references. Five external clock references can be used to drive five additional PLD 11 boards for a total of six boards operating all from the same synchronous clock reference. A system of six boards provides just under 7 million programmable gates

  6. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    Science.gov (United States)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  7. Implementation of fault-tolerant quantum logic gates via optimal control

    International Nuclear Information System (INIS)

    Nigmatullin, R; Schirmer, S G

    2009-01-01

    The implementation of fault-tolerant quantum gates on encoded logic qubits is considered. It is shown that transversal implementation of logic gates based on simple geometric control ideas is problematic for realistic physical systems suffering from imperfections such as qubit inhomogeneity or uncontrollable interactions between qubits. However, this problem can be overcome by formulating the task as an optimal control problem and designing efficient algorithms to solve it. In particular, we can find solutions that implement all of the elementary logic gates in a fixed amount of time with limited control resources for the five-qubit stabilizer code. Most importantly, logic gates that are extremely difficult to implement using conventional techniques even for ideal systems, such as the T-gate for the five-qubit stabilizer code, do not appear to pose a problem for optimal control.

  8. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    Science.gov (United States)

    Chappanda, K. N.; Ilyas, S.; Younis, M. I.

    2018-05-01

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

  9. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    KAUST Repository

    Chappanda , K. N.; Ilyas, Saad; Younis, Mohammad I.

    2018-01-01

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

  10. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    KAUST Repository

    Chappanda, K N

    2018-02-16

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

  11. Engineered modular biomaterial logic gates for environmentally triggered therapeutic delivery

    Science.gov (United States)

    Badeau, Barry A.; Comerford, Michael P.; Arakawa, Christopher K.; Shadish, Jared A.; Deforest, Cole A.

    2018-03-01

    The successful transport of drug- and cell-based therapeutics to diseased sites represents a major barrier in the development of clinical therapies. Targeted delivery can be mediated through degradable biomaterial vehicles that utilize disease biomarkers to trigger payload release. Here, we report a modular chemical framework for imparting hydrogels with precise degradative responsiveness by using multiple environmental cues to trigger reactions that operate user-programmable Boolean logic. By specifying the molecular architecture and connectivity of orthogonal stimuli-labile moieties within material cross-linkers, we show selective control over gel dissolution and therapeutic delivery. To illustrate the versatility of this methodology, we synthesized 17 distinct stimuli-responsive materials that collectively yielded all possible YES/OR/AND logic outputs from input combinations involving enzyme, reductant and light. Using these hydrogels we demonstrate the first sequential and environmentally stimulated release of multiple cell lines in well-defined combinations from a material. We expect these platforms will find utility in several diverse fields including drug delivery, diagnostics and regenerative medicine.

  12. Ferritin-Templated Quantum-Dots for Quantum Logic Gates

    Science.gov (United States)

    Choi, Sang H.; Kim, Jae-Woo; Chu, Sang-Hyon; Park, Yeonjoon; King, Glen C.; Lillehei, Peter T.; Kim, Seon-Jeong; Elliott, James R.

    2005-01-01

    Quantum logic gates (QLGs) or other logic systems are based on quantum-dots (QD) with a stringent requirement of size uniformity. The QD are widely known building units for QLGs. The size control of QD is a critical issue in quantum-dot fabrication. The work presented here offers a new method to develop quantum-dots using a bio-template, called ferritin, that ensures QD production in uniform size of nano-scale proportion. The bio-template for uniform yield of QD is based on a ferritin protein that allows reconstitution of core material through the reduction and chelation processes. One of the biggest challenges for developing QLG is the requirement of ordered and uniform size of QD for arrays on a substrate with nanometer precision. The QD development by bio-template includes the electrochemical/chemical reconsitution of ferritins with different core materials, such as iron, cobalt, manganese, platinum, and nickel. The other bio-template method used in our laboratory is dendrimers, precisely defined chemical structures. With ferritin-templated QD, we fabricated the heptagonshaped patterned array via direct nano manipulation of the ferritin molecules with a tip of atomic force microscope (AFM). We also designed various nanofabrication methods of QD arrays using a wide range manipulation techniques. The precise control of the ferritin-templated QD for a patterned arrangement are offered by various methods, such as a site-specific immobilization of thiolated ferritins through local oxidation using the AFM tip, ferritin arrays induced by gold nanoparticle manipulation, thiolated ferritin positioning by shaving method, etc. In the signal measurements, the current-voltage curve is obtained by measuring the current through the ferritin, between the tip and the substrate for potential sweeping or at constant potential. The measured resistance near zero bias was 1.8 teraohm for single holoferritin and 5.7 teraohm for single apoferritin, respectively.

  13. Programming Programmable Logic Controller. High-Technology Training Module.

    Science.gov (United States)

    Lipsky, Kevin

    This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

  14. Quantum logic gates generated by SC-charge qubits coupled to a resonator

    International Nuclear Information System (INIS)

    Obada, A-S F; Hessian, H A; Mohamed, A-B A; Homid, Ali H

    2012-01-01

    We propose some quantum logic gates by using SC-charge qubits coupled to a resonator to study two types of quantum operation. By applying a classical magnetic field with the flux, a simple rotation on the target qubit is generated. Single and two-qubit gates of quantum logic gates are realized. Two-qubit joint operations are firstly generated by applying a classical magnetic field with the flux, and secondly by applying a classical magnetic field with the flux when qubits are placed a quarter of the distance along the resonator. A short discussion of fidelity is given to prove the success of the operations in implementing these gates. (paper)

  15. Quantum logic gates using Stark-shifted Raman transitions in a cavity

    International Nuclear Information System (INIS)

    Biswas, Asoka; Agarwal, G.S.

    2004-01-01

    We present a scheme to realize the basic two-qubit logic gates such as the quantum phase gate and the controlled-NOT gate using a detuned optical cavity interacting with a three-level Raman system. We discuss the role of Stark shifts, which are as important as the terms leading to the two-photon transition. The operation of the proposed logic gates involves metastable states of the atom and hence is not affected by spontaneous emission. These ideas can be extended to produce multiparticle entanglement

  16. A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA.

    Science.gov (United States)

    Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool

    2017-12-01

    Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

  17. Tunable Molecular Logic Gates Designed for Imaging Released Neurotransmitters.

    Science.gov (United States)

    Klockow, Jessica L; Hettie, Kenneth S; Secor, Kristen E; Barman, Dipti N; Glass, Timothy E

    2015-08-03

    Tunable dual-analyte fluorescent molecular logic gates (ExoSensors) were designed for the purpose of imaging select vesicular primary-amine neurotransmitters that are released from secretory vesicles upon exocytosis. ExoSensors are based on the coumarin-3-aldehyde scaffold and rely on both neurotransmitter binding and the change in environmental pH associated with exocytosis to afford a unique turn-on fluorescence output. A pH-functionality was directly integrated into the fluorophore π-system of the scaffold, thereby allowing for an enhanced fluorescence output upon the release of labeled neurotransmitters. By altering the pH-sensitive unit with various electron-donating and -withdrawing sulfonamide substituents, we identified a correlation between the pKa of the pH-sensitive group and the fluorescence output from the activated fluorophore. In doing so, we achieved a twelvefold fluorescence enhancement upon evaluating the ExoSensors under conditions that mimic exocytosis. ExoSensors are aptly suited to serve as molecular imaging tools that allow for the direct visualization of only the neurotransmitters that are released from secretory vesicles upon exocytosis. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

    National Research Council Canada - National Science Library

    Mumbru, Jose

    2004-01-01

    ... holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors and logic circuitry can better utilize the high parallelism inherent in holographic modules...

  19. Redox-Enabled, pH-Disabled Pyrazoline-Ferrocene INHIBIT Logic Gates.

    Science.gov (United States)

    Scerri, Glenn J; Cini, Miriam; Schembri, Jonathan S; da Costa, Paola F; Johnson, Alex D; Magri, David C

    2017-07-05

    Pyrazoline-ferrocene conjugates with an "electron-donor-spacer-fluorophore-receptor" format are demonstrated as redox-fluorescent two-input INHIBIT logic gates. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.

    Science.gov (United States)

    Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek

    2015-08-07

    The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status.

  1. Unconventional geometric logic gate in a strong-driving-assisted multi-mode cavity

    International Nuclear Information System (INIS)

    Chang-Ning, Pan; Di-Wu, Yang; Xue-Hui, Zhao; Mao-Fa, Fang

    2010-01-01

    We propose a scheme to implement an unconventional geometric logic gate separately in a two-mode cavity and a multi-mode cavity assisted by a strong classical driving field. The effect of the cavity decay is included in the investigation. The numerical calculation is carried out, and the result shows that our scheme is more tolerant to cavity decay than the previous one because the time consumed for finishing the logic gate is doubly reduced. (general)

  2. Proposal for multiple-valued logic in gated semiconducting carbon nanotubes

    Science.gov (United States)

    Dragoman, D.; Dragoman, M.

    2006-06-01

    The proposal for an implementation of multi-valued logical devices based on excited states of a single quantum well is analysed for various configurations of carbon nanotube quantum wells, which were already experimentally demonstrated at room temperature. The best configuration, which gathers all the advantages of multi-valued logic, is a gated carbon nanotube device where the quantum well is imprinted via DC voltages applied on gate electrodes.

  3. Acoustic logic gates and Boolean operation based on self-collimating acoustic beams

    International Nuclear Information System (INIS)

    Zhang, Ting; Xu, Jian-yi; Cheng, Ying; Liu, Xiao-jun; Guo, Jian-zhong

    2015-01-01

    The reveal of self-collimation effect in two-dimensional (2D) photonic or acoustic crystals has opened up possibilities for signal manipulation. In this paper, we have proposed acoustic logic gates based on the linear interference of self-collimated beams in 2D sonic crystals (SCs) with line-defects. The line defects on the diagonal of the 2D square SCs are actually functioning as a 3 dB splitter. By adjusting the phase difference between two input signals, the basic Boolean logic functions such as XOR, OR, AND, and NOT are achieved both theoretically and experimentally. Due to the non-diffracting property of self-collimation beams, more complex Boolean logic and algorithms such as NAND, NOR, and XNOR can be realized by cascading the basic logic gates. The achievement of acoustic logic gates and Boolean operation provides a promising approach for acoustic signal computing and manipulations

  4. Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata.

    Science.gov (United States)

    Bahar, Ali Newaz; Rahman, Mohammad Maksudur; Nahid, Nur Mohammad; Hassan, Md Kamrul

    2017-02-01

    This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T =2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.

  5. Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

    Science.gov (United States)

    Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

    2015-02-04

    Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Synthesis of multivalued quantum logic circuits by elementary gates

    Science.gov (United States)

    Di, Yao-Min; Wei, Hai-Rui

    2013-01-01

    We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.

  7. Application of programmable logic controller in nuclear experiments

    International Nuclear Information System (INIS)

    Ponikvar, D.

    1991-09-01

    The applicability of programmable logic controller (PLC) in nuclear experiments was studied on an example that simulated the monitoring and control of an ion beam in an accelerator. Using infrared and laser light, a comparison was made between the complexity and suitability of PLC compared to a setup using a personal computer. The experiments are described in detail. The routines for registration of signals from appropriate sensors and for control of the stepper monitor were written in quick BASIC. (author). 5 figs

  8. Roles of programmable logic controllers in fuel reprocessing plants

    International Nuclear Information System (INIS)

    Mishra, Hrishikesh; Balakrishnan, V.P.; Pandya, G.J.

    1999-01-01

    Fuel charging facility is another application of Programmable Logic Controllers (PLC) in fuel reprocessing plants, that involves automatic operation of fuel cask dolly, charging motor, pneumatic doors, clutches, clamps, stepper motors and rod pushers in a pre-determined sequence. Block diagram of ACF system is given for underlining the scope of control and interlocks requirements involved for automation of the fuel charging system has been provided for the purpose at KARP Plant, Kalpakkam

  9. Application of Field programmable Gate Array to Digital Signal ...

    African Journals Online (AJOL)

    Journal of Research in National Development ... This work shows how one parallel technology Field Programmable Gate Array (FPGA) can be applied to digital signal processing problem to increase computational speed. ... In this research work FPGA typically exploits parallelism because FPGA is a parallel device. With the ...

  10. Introduction to embedded system design using field programmable gate arrays

    CERN Document Server

    Dubey, Rahul

    2009-01-01

    Offers information on the use of field programmable gate arrays (FPGAs) in the design of embedded systems. This text considers a hypothetical robot controller as an embedded application and weaves around it related concepts of FPGA-based digital design. It is suitable for both students and designers who have worked with microprocessors.

  11. Six-Correction Logic (SCL Gates in Quantum-dot Cellular Automata (QCA

    Directory of Open Access Journals (Sweden)

    Md. Anisur Rahman

    2015-11-01

    Full Text Available Quantum Dot Cellular Automata (QCA is a promising nanotechnology in Quantum electronics for its ultra low power consumption, faster speed and small size features. It has significant advantages over the Complementary Metal–Oxide–Semiconductor (CMOS technology. This paper present, a novel QCA representation of Six-Correction Logic (SCL gate based on QCA logic gates: the Maj3, Maj AND gate and Maj OR. In order to design and verify the functionality of the proposed layout, QCADesigner a familiar QCA simulator has been employed. The simulation results confirm correctness of the claims and its usefulness in designing a digital circuits.

  12. The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate

    International Nuclear Information System (INIS)

    Dridi, G; Julien, R; Hliwa, M; Joachim, C

    2015-01-01

    The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor. (paper)

  13. The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate.

    Science.gov (United States)

    Dridi, G; Julien, R; Hliwa, M; Joachim, C

    2015-08-28

    The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor.

  14. Optical NOR logic gate design on square lattice photonic crystal platform

    Energy Technology Data Exchange (ETDEWEB)

    D’souza, Nirmala Maria, E-mail: nirmala@cukerala.ac.in; Mathew, Vincent, E-mail: vincent@cukerala.ac.in [Department of Physics, Central University of Kerala, Kasaragod, Kerala-671 314 (India)

    2016-05-06

    We numerically demonstrate a new configuration of all-optical NOR logic gate with square lattice photonic crystal (PhC) waveguide using finite difference time domain (FDTD) method. The logic operations are based on interference effect of optical waves. We have determined the operating frequency range by calculating the band structure for a perfectly periodic PhC using plane wave expansion (PWE) method. Response time of this logic gate is 1.98 ps and it can be operated with speed about 513 GB/s. The proposed device consists of four linear waveguides and a square ring resonator waveguides on PhC platform.

  15. Optical three-step binary-logic-gate-based MSD arithmetic

    Science.gov (United States)

    Fyath, R. S.; Alsaffar, A. A. W.; Alam, M. S.

    2003-11-01

    A three-step modified signed-digit (MSD) adder is proposed which can be optically implmented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position based encoding scheme. The design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The functions associated with the optical binary logic gates are achieved by simply programming the decoding masks of an optical shadow-casting logic system.

  16. Multi-valued logic gates based on ballistic transport in quantum point contacts.

    Science.gov (United States)

    Seo, M; Hong, C; Lee, S-Y; Choi, H K; Kim, N; Chung, Y; Umansky, V; Mahalu, D

    2014-01-22

    Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

  17. Multi-Valued Logic Gates based on Ballistic Transport in Quantum Point Contacts

    Science.gov (United States)

    Seo, M.; Hong, C.; Lee, S.-Y.; Choi, H. K.; Kim, N.; Chung, Y.; Umansky, V.; Mahalu, D.

    2014-01-01

    Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

  18. Regulatory issues on using programmable logic device in nuclear power plants

    International Nuclear Information System (INIS)

    Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H.

    2012-01-01

    For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards

  19. Regulatory issues on using programmable logic device in nuclear power plants

    Energy Technology Data Exchange (ETDEWEB)

    Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

    2012-10-15

    For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards.

  20. A new quantum flux parametron logic gate with large input margin

    International Nuclear Information System (INIS)

    Hioe, W.; Hosoya, M.; Goto, E.

    1991-01-01

    This paper reports on the Quantum Flux Parametron (QFP) which is a flux transfer, flux activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device its correct operation may be affected by coupling to other QFPs. The problems include backcoupling from active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which being a linear input logic, has low input margin. A new logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise and reaction hazard are substantially reduced. Moreover, the input have little interaction hence input margin is greatly improved

  1. Three-valued logic gates in reaction-diffusion excitable media

    International Nuclear Information System (INIS)

    Motoike, Ikuko N.; Adamatzky, Andrew

    2005-01-01

    It is well established now that excitable media are capable of implementing of a wide range of computational operations, from image processing to logical computation to navigation of robots. The findings published so far in the field of logical computation were concerned solely with realization of boolean logic. This imposed somewhat artificial limitations on a suitability of excitable media for logical reasoning and restricted a range of possible applications of these non-classical computational devices in the field of artificial intelligence. In the paper we go beyond binary logic and show how to implement three-valued logical operations in toy models of geometrically constrained excitable media. We realize several types of logical gates, including Lukasiewicz conjunction and disjunction, and Sobocinski conjunction in cellular automata and FitzHugh-Nagumo models of T-shaped excitable media

  2. Configuration and debug of field programmable gate arrays using MATLAB[reg)/SIMULINK[reg

    International Nuclear Information System (INIS)

    Grout, I; Ryan, J; O'Shea, T

    2005-01-01

    Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB[reg] model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB[reg] model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK[reg] model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use

  3. Realization of morphing logic gates in a repressilator with quorum sensing feedback

    International Nuclear Information System (INIS)

    Agrawal, Vidit; Kang, Shivpal Singh; Sinha, Sudeshna

    2014-01-01

    We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices.

  4. Realization of morphing logic gates in a repressilator with quorum sensing feedback

    Energy Technology Data Exchange (ETDEWEB)

    Agrawal, Vidit; Kang, Shivpal Singh; Sinha, Sudeshna

    2014-03-01

    We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices.

  5. Performance Testing Methodology for Safety-Critical Programmable Logic Controller

    International Nuclear Information System (INIS)

    Kim, Chang Ho; Oh, Do Young; Kim, Ji Hyeon; Kim, Sung Ho; Sohn, Se Do

    2009-01-01

    The Programmable Logic Controller (PLC) for use in Nuclear Power Plant safety-related applications is being developed and tested first time in Korea. This safety-related PLC is being developed with requirements of regulatory guideline and industry standards for safety system. To test that the quality of the developed PLC is sufficient to be used in safety critical system, document review and various product testings were performed over the development documents for S/W, H/W, and V/V. This paper provides the performance testing methodology and its effectiveness for PLC platform conducted by KOPEC

  6. A multi-channel scaler designed with programmable logic device

    International Nuclear Information System (INIS)

    Sun Yongjie; Li Cheng; Xing Tao; Zhang Junjie

    2004-01-01

    This scaler used programmable logic device is a design for the electronics of telescope system of the beam. The scaler can scale 30 ECL inputs at the same time. With the EPP (Enhanced Parallel Port) modes of the Parallel Port, the transmitted rate of data is 2 MB/s. This scaler can be used in the position system of MWPC (Multi-Wires Proportional Chamber). Tested with particles of 5 x 10 3 /s, the scaler gives a credible and stable result. (authors)

  7. A DNA Logic Gate Automaton for Detection of Rabies and Other Lyssaviruses.

    Science.gov (United States)

    Vijayakumar, Pavithra; Macdonald, Joanne

    2017-07-05

    Immediate activation of biosensors is not always desirable, particularly if activation is due to non-specific interactions. Here we demonstrate the use of deoxyribozyme-based logic gate networks arranged into visual displays to precisely control activation of biosensors, and demonstrate a prototype molecular automaton able to discriminate between seven different genotypes of Lyssaviruses, including Rabies virus. The device uses novel mixed-base logic gates to enable detection of the large diversity of Lyssavirus sequence populations, while an ANDNOT logic gate prevents non-specific activation across genotypes. The resultant device provides a user-friendly digital-like, but molecule-powered, dot-matrix text output for unequivocal results read-out that is highly relevant for point of care applications. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. Self-Assembling Molecular Logic Gates Based on DNA Crossover Tiles.

    Science.gov (United States)

    Campbell, Eleanor A; Peterson, Evan; Kolpashchikov, Dmitry M

    2017-07-05

    DNA-based computational hardware has attracted ever-growing attention due to its potential to be useful in the analysis of complex mixtures of biological markers. Here we report the design of self-assembling logic gates that recognize DNA inputs and assemble into crossover tiles when the output signal is high; the crossover structures disassemble to form separate DNA stands when the output is low. The output signal can be conveniently detected by fluorescence using a molecular beacon probe as a reporter. AND, NOT, and OR logic gates were designed. We demonstrate that the gates can connect to each other to produce other logic functions. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. New designs of a complete set of Photonic Crystals logic gates

    Science.gov (United States)

    Hussein, Hussein M. E.; Ali, Tamer A.; Rafat, Nadia H.

    2018-03-01

    In this paper, we introduce new designs of all-optical OR, AND, XOR, NOT, NOR, NAND and XNOR logic gates based on the interference effect. The designs are built using 2D square lattice Photonic Crystal (PhC) structure of dielectric rods embedded in air background. The lattice constant, a, and the rod radius, r, are designed to achieve maximum operating range of frequencies using the gap map. We use the Plane Wave Expansion (PWE) method to obtain the band structure and the gap map of the proposed designs. The operating wavelengths achieve a wide band range that varies between 1266.9 nm and 1996 nm with center wavelength at 1550 nm. The Finite-Difference Time-Domain (FDTD) method is used to study the field behavior inside the PhC gates. The gates satisfy their truth tables with reasonable power contrast ratio between logic '1' and logic '0'.

  10. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

    International Nuclear Information System (INIS)

    Bonacini, S.

    2007-11-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

  11. Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates

    International Nuclear Information System (INIS)

    Duce, A Del; Savory, S; Bayvel, P

    2006-01-01

    In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another

  12. Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Duce, A Del; Savory, S; Bayvel, P [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London WC1E 7JE (United Kingdom)

    2006-05-31

    In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.

  13. Implementation of a three-qubit refined Deutsch Jozsa algorithm using SFG quantum logic gates

    Science.gov (United States)

    DelDuce, A.; Savory, S.; Bayvel, P.

    2006-05-01

    In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.

  14. DNAzyme-Based Logic Gate-Mediated DNA Self-Assembly.

    Science.gov (United States)

    Zhang, Cheng; Yang, Jing; Jiang, Shuoxing; Liu, Yan; Yan, Hao

    2016-01-13

    Controlling DNA self-assembly processes using rationally designed logic gates is a major goal of DNA-based nanotechnology and programming. Such controls could facilitate the hierarchical engineering of complex nanopatterns responding to various molecular triggers or inputs. Here, we demonstrate the use of a series of DNAzyme-based logic gates to control DNA tile self-assembly onto a prescribed DNA origami frame. Logic systems such as "YES," "OR," "AND," and "logic switch" are implemented based on DNAzyme-mediated tile recognition with the DNA origami frame. DNAzyme is designed to play two roles: (1) as an intermediate messenger to motivate downstream reactions and (2) as a final trigger to report fluorescent signals, enabling information relay between the DNA origami-framed tile assembly and fluorescent signaling. The results of this study demonstrate the plausibility of DNAzyme-mediated hierarchical self-assembly and provide new tools for generating dynamic and responsive self-assembly systems.

  15. Dataset demonstrating the temperature effect on average output polarization for QCA based reversible logic gates

    Directory of Open Access Journals (Sweden)

    Md. Kamrul Hassan

    2017-08-01

    Full Text Available Quantum-dot cellular automata (QCA is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS technology. In this article, we present the dataset of average output polarization (AOP for basic reversible logic gates presented in Ali Newaz et al. (2016 [1]. QCADesigner 2.0.3 has been employed to analysis the AOP of reversible gates at different temperature levels in Kelvin (K unit.

  16. Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata

    Directory of Open Access Journals (Sweden)

    Ali Newaz Bahar

    2017-02-01

    Full Text Available This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T=2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.

  17. Field programmable gate array reliability analysis using the dynamic flow graph methodology

    Energy Technology Data Exchange (ETDEWEB)

    McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

    2016-10-15

    Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

  18. Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity.

    Science.gov (United States)

    Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

    2015-05-15

    Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity).

  19. Implementing quantum logic gates with gradient ascent pulse engineering: principles and practicalities.

    Science.gov (United States)

    Rowland, Benjamin; Jones, Jonathan A

    2012-10-13

    We briefly describe the use of gradient ascent pulse engineering (GRAPE) pulses to implement quantum logic gates in nuclear magnetic resonance quantum computers, and discuss a range of simple extensions to the core technique. We then consider a range of difficulties that can arise in practical implementations of GRAPE sequences, reflecting non-idealities in the experimental systems used.

  20. Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

    Science.gov (United States)

    Neudeck, Philip G.

    1998-01-01

    The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

  1. Passive linear-optics 640 Gbit/s logic NOT gate

    DEFF Research Database (Denmark)

    Maram, Reza; Kong, Deming; Galili, Michael

    2015-01-01

    We experimentally demonstrate a 640 Gbit/s all-optical NOT gate for high-speed telecommunication on-off-keying (OOK) data signals. We employ linear optical signal processing based on spectral phase-only (all-pass) optical filtering to perform the target logic NOT operation....

  2. A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

    Science.gov (United States)

    Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

    2006-04-01

    A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

  3. Logic gates and antisense DNA devices operating on a translator nucleic Acid scaffold.

    Science.gov (United States)

    Shlyahovsky, Bella; Li, Yang; Lioubashevski, Oleg; Elbaz, Johann; Willner, Itamar

    2009-07-28

    A series of logic gates, "AND", "OR", and "XOR", are designed using a DNA scaffold that includes four "footholds" on which the logic operations are activated. Two of the footholds represent input-recognition strands, and these are blocked by complementary nucleic acids, whereas the other two footholds are blocked by nucleic acids that include the horseradish peroxidase (HRP)-mimicking DNAzyme sequence. The logic gates are activated by either nucleic acid inputs that hybridize to the respective "footholds", or by low-molecular-weight inputs (adenosine monophosphate or cocaine) that yield the respective aptamer-substrate complexes. This results in the respective translocation of the blocking nucleic acids to the footholds carrying the HRP-mimicking DNAzyme sequence, and the concomitant release of the respective DNAzyme. The released product-strands then self-assemble into the hemin/G-quadruplex-HRP-mimicking DNAzyme that biocatalyzes the formation of a colored product and provides an output signal for the different logic gates. The principle of the logic operation is, then, implemented as a possible paradigm for future nanomedicine. The nucleic acid inputs that bind to the blocked footholds result in the translocation of the blocking nucleic acids to the respective footholds carrying the antithrombin aptamer. The released aptamer inhibits, then, the hydrolytic activity of thrombin. The system demonstrates the regulation of a biocatalytic reaction by a translator system activated on a DNA scaffold.

  4. Disjointness of Stabilizer Codes and Limitations on Fault-Tolerant Logical Gates

    Science.gov (United States)

    Jochym-O'Connor, Tomas; Kubica, Aleksander; Yoder, Theodore J.

    2018-04-01

    Stabilizer codes are among the most successful quantum error-correcting codes, yet they have important limitations on their ability to fault tolerantly compute. Here, we introduce a new quantity, the disjointness of the stabilizer code, which, roughly speaking, is the number of mostly nonoverlapping representations of any given nontrivial logical Pauli operator. The notion of disjointness proves useful in limiting transversal gates on any error-detecting stabilizer code to a finite level of the Clifford hierarchy. For code families, we can similarly restrict logical operators implemented by constant-depth circuits. For instance, we show that it is impossible, with a constant-depth but possibly geometrically nonlocal circuit, to implement a logical non-Clifford gate on the standard two-dimensional surface code.

  5. All-optical XOR logic gate using intersubband transition in III-V quantum well materials.

    Science.gov (United States)

    Feng, Jijun; Akimoto, Ryoichi; Gozu, Shin-ichiro; Mozume, Teruo

    2014-06-02

    A monolithically integrated all-optical exclusive-OR (XOR) logic gate is experimentally demonstrated based on a Michelson interferometer (MI) gating device in InGaAs/AlAsSb coupled double quantum wells (CDQWs). The MI arms can convert the pump data with return-to-zero ON-OFF keying (RZ OOK) to binary phase-shift keying (BPSK) format, then two BPSK signals can interfere with each other for realizing a desired logical operation. All-optical format conversion from the RZ OOK to BPSK is based on the cross-phase modulation to the transverse electric (TE) probe wave, which is caused by the intersubband transition excited by the transverse magnetic (TM) pump light. Bit error rate measurements show that error free operation for both BPSK format conversion and XOR logical operation can be achieved.

  6. Programmable logic controller based synchronous motor excitation system

    Directory of Open Access Journals (Sweden)

    Janda Žarko

    2011-01-01

    Full Text Available This paper presents a 3.5 MW synchronous motor excitation system reconstruction. In the proposed solution programmable logic controller is used to control motor, which drives the turbo compressor. Comparing to some other solutions that are used in similar situations, the proposed solution is superior due to its flexibility and usage of mass-production hardware. Moreover, the implementation of PLC enables easy integration of the excitation system with the other technological processes in the plant as well as in the voltage regulation of 'smart grid' system. Also, implementation of various optimization algorithms can be done comfortably and it does not require additional investment in hardware. Some experimental results that depict excitation current during motor start-up, as well as, measured static characteristics of the motor, were presented.

  7. Programmable logic controller (PLC) for safety systems of nuclear plants

    International Nuclear Information System (INIS)

    Sen, S.K.; Karmakar, G.; Joseph, Jose; Patil, R.K.

    2002-01-01

    Full text: A programmable logic controller (PLC) has been developed by RCnD, BARC for use in the safety critical systems in nuclear power plants. This PLC uses qualified hardware developed in RCnD for use in NPP. The programming software conforms to IEC-61131 part 3. The application programming is done on function block diagram (FBD) editor and the FBD is automatically converted into code in high level language (C / C++). This feature makes the application easily decipherable and therefore easily subjected to reviews and other validation techniques. The key to make quality software for use in nuclear systems is to enforce various standards in the design and development of the software, something, which is not possible to do with a commercially available PLC. This PLC with its software completely transparent lends itself to rigorous verification and validation easily

  8. Management of Industrial Processes with Programmable Logic Controller

    Directory of Open Access Journals (Sweden)

    Marius Tufoi

    2009-10-01

    Full Text Available In a modern economy, automation (the control is primarily to raise the competitiveness of a product, either directly through price or quality, or indirectly through the improvement of working conditions of staff productive. The control of industrial processes involves the management of dynamic systems that have continuous states. These systems are described by differential equations and, in general, analog inputs and outputs. Management of these systems is achieved, in general, with classical automation, by automation or with analog computers which contains modules with input / output analog performance. If states, inputs and outputs of a system can be modeled using binary variables, then these systems can be driven with Programmable Logic Controller.

  9. Light-effect transistor (LET with multiple independent gating controls for optical logic gates and optical amplification

    Directory of Open Access Journals (Sweden)

    Jason eMarmon

    2016-03-01

    Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

  10. Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

    Science.gov (United States)

    Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

    The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

  11. Configurable unitary transformations and linear logic gates using quantum memories.

    Science.gov (United States)

    Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K

    2014-08-08

    We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.

  12. N Channel JFET Based Digital Logic Gate Structure

    Science.gov (United States)

    Krasowski, Michael J (Inventor)

    2013-01-01

    An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

  13. Optical Doppler tomography based on a field programmable gate array

    DEFF Research Database (Denmark)

    Larsen, Henning Engelbrecht; Nilsson, Ronnie Thorup; Thrane, Lars

    2008-01-01

    We report the design of and results obtained by using a field programmable gate array (FPGA) to digitally process optical Doppler tomography signals. The processor fits into the analog signal path in an existing optical coherence tomography setup. We demonstrate both Doppler frequency and envelope...... extraction using the Hilbert transform, all in a single FPGA. An FPGA implementation has certain advantages over general purpose digital signal processor (DSP) due to the fact that the processing elements operate in parallel as opposed to the DSP. which is primarily a sequential processor....

  14. Enzyme-Based Logic Gates and Networks with Output Signals Analyzed by Various Methods.

    Science.gov (United States)

    Katz, Evgeny

    2017-07-05

    The paper overviews various methods that are used for the analysis of output signals generated by enzyme-based logic systems. The considered methods include optical techniques (optical absorbance, fluorescence spectroscopy, surface plasmon resonance), electrochemical techniques (cyclic voltammetry, potentiometry, impedance spectroscopy, conductivity measurements, use of field effect transistor devices, pH measurements), and various mechanoelectronic methods (using atomic force microscope, quartz crystal microbalance). Although each of the methods is well known for various bioanalytical applications, their use in combination with the biomolecular logic systems is rather new and sometimes not trivial. Many of the discussed methods have been combined with the use of signal-responsive materials to transduce and amplify biomolecular signals generated by the logic operations. Interfacing of biocomputing logic systems with electronics and "smart" signal-responsive materials allows logic operations be extended to actuation functions; for example, stimulating molecular release and switchable features of bioelectronic devices, such as biofuel cells. The purpose of this review article is to emphasize the broad variability of the bioanalytical systems applied for signal transduction in biocomputing processes. All bioanalytical systems discussed in the article are exemplified with specific logic gates and multi-gate networks realized with enzyme-based biocatalytic cascades. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. SYNTHESIS AND REDUCED LOGIC GATE REALIZATION OF MULTI-VALUED LOGIC FUNCTIONS USING NEURAL NETWORK DEPLOYMENT ALGORITHM

    Directory of Open Access Journals (Sweden)

    A. K. CHOWDHURY

    2016-02-01

    Full Text Available In this paper an evolutionary technique for synthesizing Multi-Valued Logic (MVL functions using Neural Network Deployment Algorithm (NNDA is presented. The algorithm is combined with back-propagation learning capability and neural MVL operators. This research article is done to observe the anomalistic characteristics of MVL neural operators and their role in synthesis. The advantages of NNDA-MVL algorithm is demonstrated with realization of synthesized many valued functions with lesser MVL operators. The characteristic feature set consists of MVL gate count, network link count, network propagation delay and accuracy achieved in training. In brief, this paper depicts an effort of reduced network size for synthesized MVL functions. Trained MVL operators improve the basic architecture by reducing MIN gate and interlink connection by 52.94% and 23.38% respectively.

  16. Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, X.; Wan, C.H., E-mail: wancaihua@iphy.ac.cn; Yuan, Z.H.; Fang, C.; Kong, W.J.; Wu, H.; Zhang, Q.T.; Tao, B.S.; Han, X.F., E-mail: xfhan@iphy.ac.cn

    2017-04-15

    Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices. - Highlights: • Experimental demonstration of spin logic cell based on spin Hall effect. • Five logic functions are realized in a single logic cell. • The logic cell is reprogrammable. • Information in the cell is symmetry-protected. • The logic cell can be easily expanded to logic gate array.

  17. The operations of quantum logic gates with pure and mixed initial states.

    Science.gov (United States)

    Chen, Jun-Liang; Li, Che-Ming; Hwang, Chi-Chuan; Ho, Yi-Hui

    2011-04-07

    The implementations of quantum logic gates realized by the rovibrational states of a C(12)O(16) molecule in the X((1)Σ(+)) electronic ground state are investigated. Optimal laser fields are obtained by using the modified multitarget optimal theory (MTOCT) which combines the maxima of the cost functional and the fidelity for state and quantum process. The projection operator technique together with modified MTOCT is used to get optimal laser fields. If initial states of the quantum gate are pure states, states at target time approach well to ideal target states. However, if the initial states are mixed states, the target states do not approach well to ideal ones. The process fidelity is introduced to investigate the reliability of the quantum gate operation driven by the optimal laser field. We found that the quantum gates operate reliably whether the initial states are pure or mixed.

  18. Efficient quantum computation in a network with probabilistic gates and logical encoding

    DEFF Research Database (Denmark)

    Borregaard, J.; Sørensen, A. S.; Cirac, J. I.

    2017-01-01

    An approach to efficient quantum computation with probabilistic gates is proposed and analyzed in both a local and nonlocal setting. It combines heralded gates previously studied for atom or atomlike qubits with logical encoding from linear optical quantum computation in order to perform high......-fidelity quantum gates across a quantum network. The error-detecting properties of the heralded operations ensure high fidelity while the encoding makes it possible to correct for failed attempts such that deterministic and high-quality gates can be achieved. Importantly, this is robust to photon loss, which...... is typically the main obstacle to photonic-based quantum information processing. Overall this approach opens a path toward quantum networks with atomic nodes and photonic links....

  19. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    International Nuclear Information System (INIS)

    Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

    2008-01-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

  20. A computational paradigm for dynamic logic-gates in neuronal activity

    Directory of Open Access Journals (Sweden)

    Amir eGoldental

    2014-04-01

    Full Text Available In 1943 McCulloch and Pitts suggested that the brain is composed of reliable logic-gates similar to the logic at the core of today's computers. This framework had a limited impact on neuroscience, since neurons exhibit far richer dynamics. Here we propose a new experimentally corroborated paradigm in which the truth tables of the brain's logic-gates are time dependent, i.e. dynamic logic-gates (DLGs. The truth tables of the DLGs depend on the history of their activity and the stimulation frequencies of their input neurons. Our experimental results are based on a procedure where conditioned stimulations were enforced on circuits of neurons embedded within a large-scale network of cortical cells in-vitro. We demonstrate that the underlying biological mechanism is the unavoidable increase of neuronal response latencies to ongoing stimulations, which imposes a non-uniform gradual stretching of network delays. The limited experimental results are confirmed and extended by simulations and theoretical arguments based on identical neurons with a fixed increase of the neuronal response latency per evoked spike. We anticipate our results to lead to better understanding of the suitability of this computational paradigm to account for the brain's functionalities and will require the development of new systematic mathematical methods beyond the methods developed for traditional Boolean algebra.

  1. Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates

    Science.gov (United States)

    Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda

    2012-01-01

    One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039

  2. Quantum logic gates based on coherent electron transport in quantum wires.

    Science.gov (United States)

    Bertoni, A; Bordone, P; Brunetti, R; Jacoboni, C; Reggiani, S

    2000-06-19

    It is shown that the universal set of quantum logic gates can be realized using solid-state quantum bits based on coherent electron transport in quantum wires. The elementary quantum bits are realized with a proper design of two quantum wires coupled through a potential barrier. Numerical simulations show that (a) a proper design of the coupling barrier allows one to realize any one-qbit rotation and (b) Coulomb interaction between two qbits of this kind allows the implementation of the CNOT gate. These systems are based on a mature technology and seem to be integrable with conventional electronics.

  3. The impact of software and CAE tools on SEU in field programmable gate arrays

    International Nuclear Information System (INIS)

    Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

    1999-01-01

    Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

  4. The combination of gold nanorods and nanoparticles with DNA nanodevices for logic gates construction

    International Nuclear Information System (INIS)

    Yao, Dongbao; Song, Tingjie; Xiao, Shiyan; Huang, Fujian; Liang, Haojun; Zheng, Bin

    2015-01-01

    In this work, two DNA nanodevices were constructed utilizing a DNA strand displacement reaction. With the assistance of gold nanoparticles (AuNPs) and gold nanorods (AuNRs), the autonomous reactions can be reflected from the aggregation states of nanoparticles. By sequence design and the two non-overlapping double hump-like UV–vis spectral peaks of AuNPs and AuNRs, two logic gates with multiple inputs and outputs were successfully run with expected outcomes. This method not only shows how to achieve computing with multiple logic calculations but also has great potential for multiple targets detection. (paper)

  5. All-optical 10 Gb/s AND logic gate in a silicon microring resonator

    DEFF Research Database (Denmark)

    Xiong, Meng; Lei, Lei; Ding, Yunhong

    2013-01-01

    An all-optical AND logic gate in a single silicon microring resonator is experimentally demonstrated at 10 Gb/s with 50% RZ-OOK signals. By setting the wavelengths of two intensity-modulated input pumps on the resonances of the microring resonator, field-enhanced four-wave mixing with a total inp...... power of only 8.5 dBm takes place in the ring, resulting in the generation of an idler whose intensity follows the logic operation between the pumps. Clear and open eye diagrams with a bit-error- ratio below 10−9 are achieved....

  6. Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

    Science.gov (United States)

    Maity, H.; Biswas, A.; Bhattacharjee, A. K.; Pal, A.

    In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

  7. Selected area growth integrated wavelength converter based on PD-EAM optical logic gate

    International Nuclear Information System (INIS)

    Niu Bin; Zhou Daibing; Zhang Can; Liang Song; Lu Dan; Zhao Lingjuan; Wang Wei; Qiu Jifang; Wu Jian

    2014-01-01

    A selected area growth wavelength converter based on a PD-EAM optical logic gate for WDM application is presented, integrating an EML transmitter and a SOA-PD receiver. The design, fabrication, and DC characters were analyzed. A 2 Gb/s NRZ signal based on the C-band wavelength converted to 1555 nm with the highest extinction ratio of 7 dB was achieved and wavelength converted eye diagrams with eyes opened were presented. (semiconductor devices)

  8. Project-Based Learning in Programmable Logic Controller

    Science.gov (United States)

    Seke, F. R.; Sumilat, J. M.; Kembuan, D. R. E.; Kewas, J. C.; Muchtar, H.; Ibrahim, N.

    2018-02-01

    Project-based learning is a learning method that uses project activities as the core of learning and requires student creativity in completing the project. The aims of this study is to investigate the influence of project-based learning methods on students with a high level of creativity in learning the Programmable Logic Controller (PLC). This study used experimental methods with experimental class and control class consisting of 24 students, with 12 students of high creativity and 12 students of low creativity. The application of project-based learning methods into the PLC courses combined with the level of student creativity enables the students to be directly involved in the work of the PLC project which gives them experience in utilizing PLCs for the benefit of the industry. Therefore, it’s concluded that project-based learning method is one of the superior learning methods to apply on highly creative students to PLC courses. This method can be used as an effort to improve student learning outcomes and student creativity as well as to educate prospective teachers to become reliable educators in theory and practice which will be tasked to create qualified human resources candidates in order to meet future industry needs.

  9. Programmable logic controller optical fibre sensor interface module

    Science.gov (United States)

    Allwood, Gary; Wild, Graham; Hinckley, Steven

    2011-12-01

    Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

  10. Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices

    Directory of Open Access Journals (Sweden)

    Tautvydas Brukštus

    2016-06-01

    Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.

  11. Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

    KAUST Repository

    Dadgour, Hamed F.; Hussain, Muhammad Mustafa; Smith, Casey Eben; Banerjee, Kaustav

    2010-01-01

    Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally

  12. High-Fidelity Quantum Logic Gates Using Trapped-Ion Hyperfine Qubits.

    Science.gov (United States)

    Ballance, C J; Harty, T P; Linke, N M; Sepiol, M A; Lucas, D M

    2016-08-05

    We demonstrate laser-driven two-qubit and single-qubit logic gates with respective fidelities 99.9(1)% and 99.9934(3)%, significantly above the ≈99% minimum threshold level required for fault-tolerant quantum computation, using qubits stored in hyperfine ground states of calcium-43 ions held in a room-temperature trap. We study the speed-fidelity trade-off for the two-qubit gate, for gate times between 3.8  μs and 520  μs, and develop a theoretical error model which is consistent with the data and which allows us to identify the principal technical sources of infidelity.

  13. Demonstration of quantum logic gates in liquid crystal nuclear magnetic resonance

    International Nuclear Information System (INIS)

    Marjanska, Malgorzata; Chuang, Isaac L.; Kubinec, Mark G.

    2000-01-01

    1 H- 13 C heteronuclear dipolar couplings are used to produce the NMR (nuclear magnetic resonance) version of a two bit controlled-NOT quantum logic gate. This gate is coupled with the Hadamard gate to complete a circuit which generates the Einstein-Podolsky-Rosen (EPR) state which is the maximally entangled state of a pair of spins. The EPR state is crucial for the potential exponential speed advantage of quantum computers over their classical counterparts. We sample the deviation density matrix of the two spin system to verify the presence of the EPR state. EPR state lifetimes are also measured with this technique, thereby demonstrating the viability of liquid crystals as a platform for quantum computing. (c) 2000 American Institute of Physics

  14. Multiple constant multiplication optimizations for field programmable gate arrays

    CERN Document Server

    Kumm, Martin

    2016-01-01

    This work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource usage but high performance. They comprise the use of fast carry-chains in adder-based constant multiplications including ternary (3-input) adders as well as the integration of look-up table-based constant multipliers and embedded multipliers to get the optimal mapping to modern FPGAs. The proposed methods can be used for the efficient implementation of digital filters, discrete transforms and many other circuits in the domain of digital signal processing, communication and image processing. Contents Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders An Optimized Multiple Constant Multiplication Architecture ...

  15. Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

    Science.gov (United States)

    Fratto, Brian E; Katz, Evgeny

    2015-05-18

    Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. Manipulating molecular quantum states with classical metal atom inputs: demonstration of a single molecule NOR logic gate.

    Science.gov (United States)

    Soe, We-Hyo; Manzano, Carlos; Renaud, Nicolas; de Mendoza, Paula; De Sarkar, Abir; Ample, Francisco; Hliwa, Mohamed; Echavarren, Antonio M; Chandrasekhar, Natarajan; Joachim, Christian

    2011-02-22

    Quantum states of a trinaphthylene molecule were manipulated by putting its naphthyl branches in contact with single Au atoms. One Au atom carries 1-bit of classical information input that is converted into quantum information throughout the molecule. The Au-trinaphthylene electronic interactions give rise to measurable energy shifts of the molecular electronic states demonstrating a NOR logic gate functionality. The NOR truth table of the single molecule logic gate was characterized by means of scanning tunnelling spectroscopy.

  17. "Plug and play" logic gates based on fluorescence switching regulated by self-assembly of nucleotide and lanthanide ions.

    Science.gov (United States)

    Pu, Fang; Ren, Jinsong; Qu, Xiaogang

    2014-06-25

    Molecular logic gates in response to chemical, biological, or optical input signals at a molecular level have received much interest over the past decade. Herein, we construct "plug and play" logic systems based on the fluorescence switching of guest molecules confined in coordination polymer nanoparticles generated from nucleotide and lanthanide ions. In the system, the addition of new modules directly enables new logic functions. PASS 0, YES, PASS 1, NOT, IMP, OR, and AND gates are successfully constructed in sequence. Moreover, different logic gates (AND, INH, and IMP) can be constructed using different guest molecules and the same input combinations. The work will be beneficial to the future logic design and expand the applications of coordination polymers.

  18. Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

    Directory of Open Access Journals (Sweden)

    Myunghwan Ryu

    2016-01-01

    Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

  19. Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

    Energy Technology Data Exchange (ETDEWEB)

    Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Katori, Hidetoshi [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656 (Japan); Department of Applied Physics, Graduate School of Engineering, The University of Tokyo, Bunkyo-ku, Tokyo 113-8656 (Japan)

    2015-11-15

    We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

  20. Area efficient digital logic NOT gate using single electron box (SEB

    Directory of Open Access Journals (Sweden)

    Bahrepour Davoud

    2017-01-01

    Full Text Available The continuing scaling down of complementary metal oxide semiconductor (CMOS has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Single-electron devices (SEDs are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.

  1. Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

    2010-01-01

    Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

  2. Profiling the miRNAs for Early Cancer Detection using DNA-based Logic Gates

    Directory of Open Access Journals (Sweden)

    Tahereh Yahya

    2017-12-01

    Full Text Available Abstract Background: DNA-based computing is an emerging research aspect that enables the in-vivo computation and decision making with significant correctness. Recent papers show that the expression level of miRNAs are related to the progress status of some diseases such as cancers and DNA computing is introduced as a low cost and concise technique for detection of these biomarkers. In this paper, DNA-based logic gates are implemented in the laboratory to detect the level of miR-21 as the biomarker of cancer. Materials and Methods: At the first, required strands for designing DNA gates are synthesized. Then, double stranded gate is generated in laboratory using a temperature gradient that followed by electrophoresis process. This double strand is the computation engine for detecting the miR-21 biomarker. miR-21 is as input in designed gate. At the end, the expression level of miR-21 is identified by measuring the generated fluorescent. Results: at the first stage, the proposed DNA-based logic gate is evaluated by using the synthesized input strands and then it is experimented on a tumor tissue. Experimental results on synthesized strands show that its detection quality/correctness is 2.5x better than conventional methods. Conclusion: Experimental results on the tumor tissues are successful and are matched with those are extracted from real time PCR results. Also, the results show that this method is significantly more suitable than real time PCR in view of time and cost.

  3. Speed Geometric Quantum Logical Gate Based on Double-Hamiltonian Evolution under Large-Detuning Cavity QED Model

    International Nuclear Information System (INIS)

    Chen Changyong; Liu Zongliang; Kang Shuai; Li Shaohua

    2010-01-01

    We introduce the double-Hamiltonian evolution technique approach to investigate the unconventional geometric quantum logical gate with dissipation under the model of many identical three-level atoms in a cavity, driven by a classical field. Our concrete calculation is made for the case of two atoms for the large-detuning interaction of the atoms with the cavity mode. The main advantage of our scheme is of eliminating the photon flutuation in the cavity mode during the gating. The corresponding analytical results will be helpful for experimental realization of speed geometric quantum logical gate in real cavities. (general)

  4. Programmable logic controllers in Heavy Water Project, Manuguru (Paper No. 3.4)

    International Nuclear Information System (INIS)

    Gupta, S.C.; Bhaskar, R.; Maiti, A.; Venkatesu, G.; Satish, P.; Goel, R.K.

    1992-01-01

    Enhancement to plant operational flexibility has been achieved in Heavy Water Project, Manuguru by installing programmable logic controllers for its control equipment. The earlier sulfide based Heavy Water Plant, Kota is using relay logic and diode based program-matrix for binary controls. Performance improvement and advantages of PLC and experience in its operation are described. (author). 3 refs

  5. Effect of laser pulse shaping parameters on the fidelity of quantum logic gates.

    Science.gov (United States)

    Zaari, Ryan R; Brown, Alex

    2012-09-14

    The effect of varying parameters specific to laser pulse shaping instruments on resulting fidelities for the ACNOT(1), NOT(2), and Hadamard(2) quantum logic gates are studied for the diatomic molecule (12)C(16)O. These parameters include varying the frequency resolution, adjusting the number of frequency components and also varying the amplitude and phase at each frequency component. A time domain analytic form of the original discretized frequency domain laser pulse function is derived, providing a useful means to infer the resulting pulse shape through variations to the aforementioned parameters. We show that amplitude variation at each frequency component is a crucial requirement for optimal laser pulse shaping, whereas phase variation provides minimal contribution. We also show that high fidelity laser pulses are dependent upon the frequency resolution and increasing the number of frequency components provides only a small incremental improvement to quantum gate fidelity. Analysis through use of the pulse area theorem confirms the resulting population dynamics for one or two frequency high fidelity laser pulses and implies similar dynamics for more complex laser pulse shapes. The ability to produce high fidelity laser pulses that provide both population control and global phase alignment is attributed greatly to the natural evolution phase alignment of the qubits involved within the quantum logic gate operation.

  6. Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

    Science.gov (United States)

    Ang, Yee Sin; Yang, Shengyuan A.; Zhang, C.; Ma, Zhongshui; Ang, L. K.

    2017-12-01

    Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over 10 000 % can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The (2 +1 ) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

  7. Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

    Science.gov (United States)

    Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

    2017-01-01

    Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

  8. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    International Nuclear Information System (INIS)

    Lashin, A. V.; Kozyrev, A. V.

    2015-01-01

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

  9. Spectroscopic and TDDFT investigation on highly selective fluorogenic chemosensor and construction of molecular logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Basheer, Sabeel M [Department of Chemistry, National Institute of Technology, Tiruchirappalli 620 015 (India); Kumar, Saravana Loganathan Ashok [Department of Chemistry, GRT Institute of Engineering Technology, Tiruttani (India); Kumar, Moorthy Saravana [Research and PG Department of Chemistry, Saraswathi Narayanan College, Madurai 625022 (India); Sreekanth, Anandaram, E-mail: sreekanth@nitt.edu [Department of Chemistry, National Institute of Technology, Tiruchirappalli 620 015 (India)

    2017-03-01

    1,5-Bis(2-fluorene)thiocarbohydrazone (FBTC) was designed and synthesized for selective sensing of fluoride and copper ions. The binding constants of FBTC towards fluoride and copper ions have been calculated using the Benesi-Hildebrand equation, and FBTC has more binding affinity towards copper ion than fluoride ion. The {sup 1}H NMR and {sup 13}C NMR titration studies strongly support the deprotonation was taken from the N–H protons followed by the formation of hydrogen bond via N–H{sup …}F. To understand the fluoride ion sensing mechanism, theoretical investigation had been carried out using the density functional theory and time-dependent density functional theory. The theoretical data well reproduced the experimental results. The deprotonation process has a moderate transition barrier (481.55 kcal/mol). The calculated ΔE and ΔG values (− 253.92 and − 192.41 kcal/mol respectively) suggest the feasibility of sensing process. The potential energy curves give the optimized structures of FBTC-F complex in the ground state and excited state, which states the proton transition occurs at the excited state. The excited state proton transition mechanism was further confirmed with natural bond orbital analysis. The reversibility of the sensor was monitored by the alternate addition of F{sup −} and Cu{sup 2+} ions, which was explained with “Read-Erase-Write-Read” behaviour. The multi-ion detection of sensor used to construct the molecular logic gate, such as AND, OR, NOR and INHIBITION logic gates. - Highlight: • Synthesis and characterised the thiosemicarbohydrazone derivative • Experimental evolution of selective fluoride and copper sensing via both colorimetric and spectroscopic studies • The proposed sensing mechanism of fluoride and copper ion were further confirmed with DFT and TD-DFT investigation • Receptor was turned as molecular switches and molecular logic gates.

  10. Analysis of Nonlinear Periodic and Aperiodic Media: Application to Optical Logic Gates

    Science.gov (United States)

    Yu, Yisheng

    This dissertation is about the analysis of nonlinear periodic and aperiodic media and their application to the design of intensity controlled all optical logic gates: AND, OR, and NOT. A coupled nonlinear differential equation that characterizes the electromagnetic wave propagation in a nonlinear periodic (and aperiodic) medium has been derived from the first principle. The equations are general enough that it reflects the effect of transverse modal fields and can be used to analyze both co-propagating and counter propagating waves. A numerical technique based on the finite differences method and absorbing boundary condition has been developed to solve the coupled differential equations here. The numerical method is simple and accurate. Unlike the method based on characteristics that has been reported in the literature, this method does not involve integration and step sizes of time and space coordinates are decoupled. The decoupling provides independent choice for time and space step sizes. The concept of "gap soliton" has also been re-examined. The dissertation consists of four manuscripts. Manuscript I reports on the design of all optical logic gates: AND, OR, and NOT based on the bistability property of nonlinear periodic and aperiodic waveguiding structures. The functioning of the logic gates has been shown by analysis. The numerical technique that has been developed to solve the nonlinear differential equations are addressed in manuscript II. The effect of transverse modal fields on the bistable property of nonlinear periodic medium is reported in manuscript III. The concept of "gap soliton" that are generated in a nonlinear periodic medium has been re-examined. The details on the finding of the re-examination are discussed in manuscript IV.

  11. Implementation of quantum logic gates using polar molecules in pendular states.

    Science.gov (United States)

    Zhu, Jing; Kais, Sabre; Wei, Qi; Herschbach, Dudley; Friedrich, Bretislav

    2013-01-14

    We present a systematic approach to implementation of basic quantum logic gates operating on polar molecules in pendular states as qubits for a quantum computer. A static electric field prevents quenching of the dipole moments by rotation, thereby creating the pendular states; also, the field gradient enables distinguishing among qubit sites. Multi-target optimal control theory is used as a means of optimizing the initial-to-target transition probability via a laser field. We give detailed calculations for the SrO molecule, a favorite candidate for proposed quantum computers. Our simulation results indicate that NOT, Hadamard and CNOT gates can be realized with high fidelity, as high as 0.985, for such pendular qubit states.

  12. Entangling quantum-logic gate operated with an ultrabright semiconductor single-photon source.

    Science.gov (United States)

    Gazzano, O; Almeida, M P; Nowak, A K; Portalupi, S L; Lemaître, A; Sagnes, I; White, A G; Senellart, P

    2013-06-21

    We demonstrate the unambiguous entangling operation of a photonic quantum-logic gate driven by an ultrabright solid-state single-photon source. Indistinguishable single photons emitted by a single semiconductor quantum dot in a micropillar optical cavity are used as target and control qubits. For a source brightness of 0.56 photons per pulse, the measured truth table has an overlap with the ideal case of 68.4±0.5%, increasing to 73.0±1.6% for a source brightness of 0.17 photons per pulse. The gate is entangling: At a source brightness of 0.48, the Bell-state fidelity is above the entangling threshold of 50% and reaches 71.0±3.6% for a source brightness of 0.15.

  13. Single OR molecule and OR atomic circuit logic gates interconnected on a Si(100)H surface

    International Nuclear Information System (INIS)

    Ample, F; Joachim, C; Duchemin, I; Hliwa, M

    2011-01-01

    Electron transport calculations were carried out for three terminal OR logic gates constructed either with a single molecule or with a surface dangling bond circuit interconnected on a Si(100)H surface. The corresponding multi-electrode multi-channel scattering matrix (where the central three terminal junction OR gate is the scattering center) was calculated, taking into account the electronic structure of the supporting Si(100)H surface, the metallic interconnection nano-pads, the surface atomic wires and the molecule. Well interconnected, an optimized OR molecule can only run at a maximum of 10 nA output current intensity for a 0.5 V bias voltage. For the same voltage and with no molecule in the circuit, the output current of an OR surface atomic scale circuit can reach 4 μA.

  14. All-optical universal logic gates on nonlinear multimode interference coupler using tunable input intensity

    Science.gov (United States)

    Tajaldini, Mehdi; Jafri, Mohd Zubir Mat

    2015-04-01

    The theory of Nonlinear Modal Propagation Analysis Method (NMPA) have shown significant features of nonlinear multimode interference (MMI) coupler with compact dimension and when launched near the threshold of nonlinearity. Moreover, NMPA have the potential to allow studying the nonlinear MMI based the modal interference to explorer the phenomenon that what happen due to the natural of multimode region. Proposal of all-optical switch based NMPA has approved its capability to achieving the all-optical gates. All-optical gates have attracted increasing attention due to their practical utility in all-optical signal processing networks and systems. Nonlinear multimode interference devices could apply as universal all-optical gates due to significant features that NMPA introduce them. In this Paper, we present a novel Ultra-compact MMI coupler based on NMPA method in low intensity compared to last reports either as a novel design method and potential application for optical NAND, NOR as universal gates on single structure for Boolean logic signal processing devices and optimize their application via studding the contrast ratio between ON and OFF as a function of output width. We have applied NMPA for several applications so that the miniaturization in low nonlinear intensities is their main purpose.

  15. Development of a sensor to study the DNA conformation using molecular logic gates.

    Science.gov (United States)

    Roy, Arpan Datta; Dey, Dibyendu; Saha, Jaba; Chakraborty, Santanu; Bhattacharjee, D; Hussain, Syed Arshad

    2015-02-05

    This communication reports our investigations on the Fluorescence Resonance Energy Transfer (FRET) between two laser dyes Acriflavine and Rhodamine B in absence and presence of DNA at different pH. It has been observed that energy transfer efficiency is largely affected by the presence of DNA as well as the pH of the system. It is well known that with increase in pH, DNA conformation changes from double stranded to single stranded (denaturation) and finally form random coil. Based on our experimental results two different types of molecular logic gates namely, XOR and OR logic have been demonstrated which can be used to have an idea about DNA conformation in solution. Copyright © 2014 Elsevier B.V. All rights reserved.

  16. Development of a sensor to study the DNA conformation using molecular logic gates

    Science.gov (United States)

    Roy, Arpan Datta; Dey, Dibyendu; Saha, Jaba; Chakraborty, Santanu; Bhattacharjee, D.; Hussain, Syed Arshad

    2015-02-01

    This communication reports our investigations on the Fluorescence Resonance Energy Transfer (FRET) between two laser dyes Acriflavine and Rhodamine B in absence and presence of DNA at different pH. It has been observed that energy transfer efficiency is largely affected by the presence of DNA as well as the pH of the system. It is well known that with increase in pH, DNA conformation changes from double stranded to single stranded (denaturation) and finally form random coil. Based on our experimental results two different types of molecular logic gates namely, XOR and OR logic have been demonstrated which can be used to have an idea about DNA conformation in solution.

  17. Realization of optimized quantum controlled-logic gate based on the orbital angular momentum of light.

    Science.gov (United States)

    Zeng, Qiang; Li, Tao; Song, Xinbing; Zhang, Xiangdong

    2016-04-18

    We propose and experimentally demonstrate an optimized setup to implement quantum controlled-NOT operation using polarization and orbital angular momentum qubits. This device is more adaptive to inputs with various polarizations, and can work both in classical and quantum single-photon regime. The logic operations performed by such a setup not only possess high stability and polarization-free character, they can also be easily extended to deal with multi-qubit input states. As an example, the experimental implementation of generalized three-qubit Toffoli gate has been presented.

  18. Single-flux-quantum logic circuits exploiting collision-based fusion gates

    International Nuclear Information System (INIS)

    Asai, T.; Yamada, K.; Amemiya, Y.

    2008-01-01

    We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock

  19. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  20. Reconfigurable OR and XOR logic gates based on dual responsive on-off-on micromotors

    Science.gov (United States)

    Dong, Yonggang; Liu, Mei; Zhang, Hui; Dong, Bin

    2016-04-01

    In this study, we report a hemisphere-like micromotor. Intriguingly, the micromotor exhibits controllable on-off-on motion, which can be actuated by two different external stimuli (UV and NH3). Moreover, the moving direction of the micromotor can be manipulated by the direction in which UV and NH3 are applied. As a result, the motion accelerates when both stimuli are applied in the same direction and decelerates when the application directions are opposite to each other. More interestingly, the dual stimuli responsive micromotor can be utilized as a reconfigurable logic gate with UV and NH3 as the inputs and the motion of the micromotor as the output. By controlling the direction of the external stimuli, OR and XOR dual logic functions can be realized.In this study, we report a hemisphere-like micromotor. Intriguingly, the micromotor exhibits controllable on-off-on motion, which can be actuated by two different external stimuli (UV and NH3). Moreover, the moving direction of the micromotor can be manipulated by the direction in which UV and NH3 are applied. As a result, the motion accelerates when both stimuli are applied in the same direction and decelerates when the application directions are opposite to each other. More interestingly, the dual stimuli responsive micromotor can be utilized as a reconfigurable logic gate with UV and NH3 as the inputs and the motion of the micromotor as the output. By controlling the direction of the external stimuli, OR and XOR dual logic functions can be realized. Electronic supplementary information (ESI) available: Fig. S1-S6 and Videos S1-S5. See DOI: 10.1039/c6nr00752j

  1. Implementation of BES-III TOF trigger system in programmable logic devices

    International Nuclear Information System (INIS)

    Zheng Wei; Liu Shubin; Liu Xuzong; An Qi

    2009-01-01

    The TOF trigger sub-system on the upgrading Beijing Spectrometer is designed to receive 368 bits fast hit signals from the front end electronics module to yield 7 bits trigger information according to the physical requirement. It sends the processed real time trigger information to the Global-Trigger-Logic to generate the primal trigger signal L1, and sends processed 136 bits real time position information to the Track-Match-Logic to calculate the particle flight tracks. The sub-system also packages the valid events for the DAQ system to read out. Following the reconfigurable concept, a large number of programmable logic devices are employed to increase the flexibility and reliability of the system, and decrease the complexity and the space requirement of PCB layout. This paper describes the implementation of the kernel trigger logic in a programmable logic device. (authors)

  2. Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

    Science.gov (United States)

    Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

    2017-05-10

    We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

  3. Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

    National Research Council Canada - National Science Library

    O'Connor, Joseph E

    2008-01-01

    ...) continuously develops new design and education resources for students. One area of focus for students in the Power Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA...

  4. Special Technology Area Review on Field Programmable Gate Arrays (FPGAs) For Military Applications

    National Research Council Canada - National Science Library

    2005-01-01

    ...) on Field Programmable Gate Arrays (FPGAs) for Military Applications on August 3-4, 2004 at the Naval Postgraduate School in Monterey, California to address issues relevant to the use of this technology in military systems...

  5. A fluorescent combinatorial logic gate with Na+, H+-enabled OR and H+-driven low-medium-high ternary logic functions.

    Science.gov (United States)

    Spiteri, Jasmine M A; Mallia, Carl J; Scerri, Glenn J; Magri, David C

    2017-12-06

    A novel fluorescent molecular logic gate with a 'fluorophore-spacer 1 -receptor 1 -spacer 2 -receptor 2 ' format is demonstrated in 1 : 1 (v/v) methanol/water. The molecule consists of an anthracene fluorophore, and tertiary alkyl amine and N-(2-methoxyphenyl)aza-15-crown-5 ether receptors. In the presence of threshold concentrations of H + and Na + , the molecule switches 'on' as an AND logic gate with a fluorescence quantum yield of 0.21 with proton and sodium binding constants of log β H+ = 9.0 and log β Na+ = 3.2, respectively. At higher proton levels, protonation also occurs at the anilinic nitrogen atom ether with a log β H+ = 4.2, which allows for Na + , H + -enabled OR (OR + AND circuit) and H + -driven ternary logic functions. The reported molecule is compared and contrasted to classic anthracene-based Na + and H + logic gates. We propose that such logic-based molecules could be useful tools for probing the vicinity of Na + , H + antiporters in biological systems.

  6. Electro-optical logic gates based on graphene-silicon waveguides

    Science.gov (United States)

    Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi

    2016-08-01

    In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.

  7. A Reversible DNA Logic Gate Platform Operated by One- and Two-Photon Excitations.

    Science.gov (United States)

    Tam, Dick Yan; Dai, Ziwen; Chan, Miu Shan; Liu, Ling Sum; Cheung, Man Ching; Bolze, Frederic; Tin, Chung; Lo, Pik Kwan

    2016-01-04

    We demonstrate the use of two different wavelength ranges of excitation light as inputs to remotely trigger the responses of the self-assembled DNA devices (D-OR). As an important feature of this device, the dependence of the readout fluorescent signals on the two external inputs, UV excitation for 1 min and/or near infrared irradiation (NIR) at 800 nm fs laser pulses, can mimic function of signal communication in OR logic gates. Their operations could be reset easily to its initial state. Furthermore, these DNA devices exhibit efficient cellular uptake, low cytotoxicity, and high bio-stability in different cell lines. They are considered as the first example of a photo-responsive DNA logic gate system, as well as a biocompatible, multi-wavelength excited system in response to UV and NIR. This is an important step to explore the concept of photo-responsive DNA-based systems as versatile tools in DNA computing, display devices, optical communication, and biology. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

    International Nuclear Information System (INIS)

    Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

    2017-01-01

    A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

  9. A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

    2017-03-01

    A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

  10. Control of electrochemical signals from quantum dots conjugated to organic materials by using DNA structure in an analog logic gate.

    Science.gov (United States)

    Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo

    2016-10-01

    Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system. Copyright © 2016 Elsevier B.V. All rights reserved.

  11. Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes.

    Science.gov (United States)

    Lin, Xiaodong; Liu, Yaqing; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei; Wang, Shuo

    2018-02-21

    The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way.

  12. Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

    Science.gov (United States)

    Muzika, František; Schreiber, Igor

    2013-10-01

    We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

  13. Implementation of all-optical reversible logic gate based on holographic laser induced grating using azo-dye doped polymers

    Science.gov (United States)

    Forsati, Rana; Valipour Ebrahimi, Sara; Navi, Keivan; Mohajerani, Ezeddin; Jashnsaz, Hossein

    2013-02-01

    Increasing demand for power reduction in computer systems has led to new trends in computations and computer design including reversible computing. Its main aim is to eliminate power dissipation in logical elements but can have some other advantages such as data security and error prevention. Because of interesting properties of reversible computing, implementing computing devices with reversible manner is the only way to make the reversible computing a reality. In recent years, reversible logic has turned out to be a promising computing paradigm having application in CMOS, nanotechnology, quantum computing and optical computing. In this paper, we propose and realize a novel implementation of Toffoli gate in all-optical domain. We have explained its principle of operations and described an actual experimental implementation. The all-optical reversible gate presented in this paper will be useful in different applications such as arithmetic and logical operations in the domain of reversible logic-based computing.

  14. Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)

    Science.gov (United States)

    Karmakar, Supriya

    2014-10-01

    This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.

  15. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    Energy Technology Data Exchange (ETDEWEB)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  16. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    International Nuclear Information System (INIS)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-01-01

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices

  17. Design techniques for a stable operation of cryogenic field-programmable gate arrays

    Science.gov (United States)

    Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

    2018-01-01

    In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

  18. Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA

    International Nuclear Information System (INIS)

    Martins, Roque Hudson da Silva

    2016-01-01

    This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

  19. Design of a Tritium-in-air-monitor using field programmable gate arrays

    International Nuclear Information System (INIS)

    McNelles, Phillip; Lu, Lixuan

    2015-01-01

    Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

  20. Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

    Science.gov (United States)

    Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.

    2018-05-01

    Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.

  1. Toward Efficient Design of Reversible Logic Gates in Quantum-Dot Cellular Automata with Power Dissipation Analysis

    Science.gov (United States)

    Sasamal, Trailokya Nath; Singh, Ashutosh Kumar; Ghanekar, Umesh

    2018-04-01

    Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for designing area and power efficient reversible logic gates. The proposed designs achieve superior performance by incorporating a compact 2-input XOR gate. The proposed design for Feynman, Toffoli, and Fredkin gates demonstrates 28.12, 24.4, and 7% reduction in cell count and utilizes 46, 24.4, and 7.6% less area, respectively over previous best designs. Regarding the cell count (area cover) that of the proposed Peres gate and Double Feynman gate are 44.32% (21.5%) and 12% (25%), respectively less than the most compact previous designs. Further, the delay of Fredkin and Toffoli gates is 0.75 clock cycles, which is equal to the delay of the previous best designs. While the Feynman and Double Feynman gates achieve a delay of 0.5 clock cycles, equal to the least delay previous one. Energy analysis confirms that the average energy dissipation of the developed Feynman, Toffoli, and Fredkin gates is 30.80, 18.08, and 4.3% (for 1.0 E k energy level), respectively less compared to best reported designs. This emphasizes the beneficial role of using proposed reversible gates to design complex and power efficient QCA circuits. The QCADesigner tool is used to validate the layout of the proposed designs, and the QCAPro tool is used to evaluate the energy dissipation.

  2. Multi-channel logical circuit module used for high-speed, low amplitude signals processing and QDC gate signals generation

    International Nuclear Information System (INIS)

    Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu

    2001-01-01

    A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events

  3. Synthetic Ion Channels and DNA Logic Gates as Components of Molecular Robots.

    Science.gov (United States)

    Kawano, Ryuji

    2018-02-19

    A molecular robot is a next-generation biochemical machine that imitates the actions of microorganisms. It is made of biomaterials such as DNA, proteins, and lipids. Three prerequisites have been proposed for the construction of such a robot: sensors, intelligence, and actuators. This Minireview focuses on recent research on synthetic ion channels and DNA computing technologies, which are viewed as potential candidate components of molecular robots. Synthetic ion channels, which are embedded in artificial cell membranes (lipid bilayers), sense ambient ions or chemicals and import them. These artificial sensors are useful components for molecular robots with bodies consisting of a lipid bilayer because they enable the interface between the inside and outside of the molecular robot to function as gates. After the signal molecules arrive inside the molecular robot, they can operate DNA logic gates, which perform computations. These functions will be integrated into the intelligence and sensor sections of molecular robots. Soon, these molecular machines will be able to be assembled to operate as a mass microrobot and play an active role in environmental monitoring and in vivo diagnosis or therapy. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Ultracompact all-optical logic gates based on nonlinear plasmonic nanocavities

    Directory of Open Access Journals (Sweden)

    Yang Xiaoyu

    2016-09-01

    Full Text Available In this study, nanoscale integrated all-optical XNOR, XOR, and NAND logic gates were realized based on all-optical tunable on-chip plasmon-induced transparency in plasmonic circuits. A large nonlinear enhancement was achieved with an organic composite cover layer based on the resonant excitation-enhancing nonlinearity effect, slow light effect, and field confinement effect provided by the plasmonic nanocavity mode, which ensured a low excitation power of 200 μW that is three orders of magnitude lower than the values in previous reports. A feature size below 600 nm was achieved, which is a one order of magnitude lower compared to previous reports. The contrast ratio between the output logic states “1” and “0” reached 29 dB, which is among the highest values reported to date. Our results not only provide an on-chip platform for the study of nonlinear and quantum optics but also open up the possibility for the realization of nanophotonic processing chips based on nonlinear plasmonics.

  5. Proposal for a graphene-based all-spin logic gate

    International Nuclear Information System (INIS)

    Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud; Zhang, Youguang

    2015-01-01

    In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (∼μm), higher data throughput, faster computing speed (∼ns), and lower power consumption (∼μA) can be expected from the G-ASLG

  6. Proposal for a graphene-based all-spin logic gate

    Science.gov (United States)

    Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Zhang, Youguang; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud

    2015-02-01

    In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (˜μm), higher data throughput, faster computing speed (˜ns), and lower power consumption (˜μA) can be expected from the G-ASLG.

  7. Grafting polyethylenimine with quinoline derivatives for targeted imaging of intracellular Zn2+ and logic gate operations

    International Nuclear Information System (INIS)

    Pan, Yi; Shi, Yupeng; Chen, Junying; Wong, Chap-Mo; Zhang, Heng; Li, Mei-Jin; Li, Cheuk-Wing; Yi, Changqing

    2016-01-01

    In this study, a highly sensitive and selective fluorescent Zn 2+ probe which exhibited excellent biocompatibility, water solubility, and cell-membrane permeability, was facilely synthesized in a single step by grafting polyethyleneimine (PEI) with quinoline derivatives. The primary amino groups in the branched PEI can increase water solubility and cell permeability of the probe PEIQ, while quinoline derivatives can specifically recognize Zn 2+ and reduce the potential cytotoxicity of PEI. Basing on fluorescence off-on mechanism, PEIQ demonstrated excellent sensing capability towards Zn 2+ in absolute aqueous solution, where a high sensitivity with a detection limit as low as 38.1 nM, and a high selectivity over competing metal ions and potential interfering amino acids, were achieved. Inspired by these results, elementary logic operations (YES, NOT and INHIBIT) have been constructed by employing PEIQ as the gate while Zn 2+ and EDTA as chemical inputs. Together with the low cytotoxicity and good cell-permeability, the practical application of PEIQ in living cell imaging was satisfactorily demonstrated, emphasizing its wide application in fundamental biology research. - Graphical abstract: The fluorescent Zn 2+ probe, PEIQ, is facilely synthesized by grafting PEI with 8-CAAQ, and demonstrated for the pratical applications in Zn 2+ imaging and implementation of molecular logic operations within biological cells. - Highlights: • PEIQ, fluorescent Zn 2+ probe, is synthesized by grafting PEI with quinoline derivatives. • PEIQ exhibits high sensitivity and selectivity in absolute aqueous solution. • PEIQ is biocompatible, water soluble, and cell-membrane permeable. • Elementary logic operations have been demonstrated for PEIQ/Zn 2+ /EDTA system. • The practical application of PEIQ in living cell imaging is demonstrated.

  8. P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

    Science.gov (United States)

    Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

    2018-04-01

    In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

  9. Stealth low-level manipulation of programmable logic controllers I/O by pin control exploitation

    NARCIS (Netherlands)

    Abbasi, A.; Hashemi, M.; Zambon, E.; Etalle, S.; Havarneanu, G.; Setola, R.; Nassopoulos, H.; Wolthusen, S.

    2016-01-01

    Input/OutputisthemechanismthroughwhichProgrammable Logic Controllers (PLCs) interact with and control the outside world. Particularly when employed in critical infrastructures, the I/O of PLCs has to be both reliable and secure. PLCs I/O like other embedded devices are controlled by a pin based

  10. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    Science.gov (United States)

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  11. A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

    Science.gov (United States)

    Kellett, C. M.

    2012-01-01

    This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

  12. Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

    Science.gov (United States)

    Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

    2017-11-20

    A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. A biomimetic colorimetric logic gate system based on multi-functional peptide-mediated gold nanoparticle assembly.

    Science.gov (United States)

    Li, Yong; Li, Wang; He, Kai-Yu; Li, Pei; Huang, Yan; Nie, Zhou; Yao, Shou-Zhuo

    2016-04-28

    In natural biological systems, proteins exploit various functional peptide motifs to exert target response and activity switch, providing a functional and logic basis for complex cellular activities. Building biomimetic peptide-based bio-logic systems is highly intriguing but remains relatively unexplored due to limited logic recognition elements and complex signal outputs. In this proof-of-principle work, we attempted to address these problems by utilizing multi-functional peptide probes and the peptide-mediated nanoparticle assembly system. Here, the rationally designed peptide probes function as the dual-target responsive element specifically responsive to metal ions and enzymes as well as the mediator regulating the assembly of gold nanoparticles (AuNPs). Taking advantage of Zn2+ ions and chymotrypsin as the model inputs of metal ions and enzymes, respectively, we constructed the peptide logic system computed by the multi-functional peptide probes and outputted by the readable colour change of AuNPs. In this way, the representative binary basic logic gates (AND, OR, INHIBIT, NAND, IMPLICATION) have been achieved by delicately coding the peptide sequence, demonstrating the versatility of our logic system. Additionally, we demonstrated that the three-input combinational logic gate (INHIBIT-OR) could also be successfully integrated and applied as a multi-tasking biosensor for colorimetric detection of dual targets. This nanoparticle-based peptide logic system presents a valid strategy to illustrate peptide information processing and provides a practical platform for executing peptide computing or peptide-related multiplexing sensing, implying that the controllable nanomaterial assembly is a promising and potent methodology for the advancement of biomimetic bio-logic computation.

  14. Easy design of colorimetric logic gates based on nonnatural base pairing and controlled assembly of gold nanoparticles.

    Science.gov (United States)

    Zhang, Li; Wang, Zhong-Xia; Liang, Ru-Ping; Qiu, Jian-Ding

    2013-07-16

    Utilizing the principles of metal-ion-mediated base pairs (C-Ag-C and T-Hg-T), the pH-sensitive conformational transition of C-rich DNA strand, and the ligand-exchange process triggered by DL-dithiothreitol (DTT), a system of colorimetric logic gates (YES, AND, INHIBIT, and XOR) can be rationally constructed based on the aggregation of the DNA-modified Au NPs. The proposed logic operation system is simple, which consists of only T-/C-rich DNA-modified Au NPs, and it is unnecessary to exquisitely design and alter the DNA sequence for different multiple molecular logic operations. The nonnatural base pairing combined with unique optical properties of Au NPs promises great potential in multiplexed ion sensing, molecular-scale computers, and other computational logic devices.

  15. A survey of advancements in nucleic acid-based logic gates and computing for applications in biotechnology and biomedicine.

    Science.gov (United States)

    Wu, Cuichen; Wan, Shuo; Hou, Weijia; Zhang, Liqin; Xu, Jiehua; Cui, Cheng; Wang, Yanyue; Hu, Jun; Tan, Weihong

    2015-03-04

    Nucleic acid-based logic devices were first introduced in 1994. Since then, science has seen the emergence of new logic systems for mimicking mathematical functions, diagnosing disease and even imitating biological systems. The unique features of nucleic acids, such as facile and high-throughput synthesis, Watson-Crick complementary base pairing, and predictable structures, together with the aid of programming design, have led to the widespread applications of nucleic acids (NA) for logic gate and computing in biotechnology and biomedicine. In this feature article, the development of in vitro NA logic systems will be discussed, as well as the expansion of such systems using various input molecules for potential cellular, or even in vivo, applications.

  16. Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

    KAUST Repository

    Dadgour, Hamed F.

    2010-01-01

    Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated double-electrode NEMS" structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoulli\\'s beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models "underestimate" the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors. © Copyright 2010 ACM.

  17. Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

    Science.gov (United States)

    Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

    2017-10-11

    The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

  18. A Cu2+-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate

    Science.gov (United States)

    Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

    2015-06-01

    A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu2+ over other metal ions in acetonitrile. Upon addition of Cu2+ ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu2+, the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu2+ can be restored with the introduction of EDTA or S2-. Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu2+ and S2- as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated.

  19. Control phase shift of spin-wave by spin-polarized current and its application in logic gates

    International Nuclear Information System (INIS)

    Chen, Xiangxu; Wang, Qi; Liao, Yulong; Tang, Xiaoli; Zhang, Huaiwu; Zhong, Zhiyong

    2015-01-01

    We proposed a new ways to control the phase shift of propagating spin waves by applying a local spin-polarized current on ferromagnetic stripe. Micromagnetic simulation showed that a phase shift of about π can be obtained by designing appropriate width and number of pinned magnetic layers. The ways can be adopted in a Mach-Zehnder-type interferometer structure to fulfill logic NOT gates based on spin waves. - Highlights: • Spin-wave phase shift can be controlled by a local spin-polarized current. • Spin-wave phase shift increased with the increasing of current density. • Spin-wave phase shift can reach about 0.3π at a particular current density. • The ways can be used in a Mach-Zehnder-type interferometer to fulfill logic gates

  20. All-optical logic gates and wavelength conversion via the injection locking of a Fabry-Perot semiconductor laser

    Science.gov (United States)

    Harvey, E.; Pochet, M.; Schmidt, J.; Locke, T.; Naderi, N.; Usechak, N. G.

    2013-03-01

    This work investigates the implementation of all-optical logic gates based on optical injection locking (OIL). All-optical inverting, NOR, and NAND gates are experimentally demonstrated using two distributed feedback (DFB) lasers, a multi-mode Fabry-Perot laser diode, and an optical band-pass filter. The DFB lasers are externally modulated to represent logic inputs into the cavity of the multi-mode Fabry-Perot slave laser. The input DFB (master) lasers' wavelengths are aligned with the longitudinal modes of the Fabry-Perot slave laser and their optical power is used to modulate the injection conditions in the Fabry-Perot slave laser. The optical band-pass filter is used to select a Fabry- Perot mode that is either suppressed or transmitted given the logic state of the injecting master laser signals. When the input signal(s) is (are) in the on state, injection locking, and thus the suppression of the non-injected Fabry-Perot modes, is induced, yielding a dynamic system that can be used to implement photonic logic functions. Additionally, all-optical photonic processing is achieved using the cavity-mode shift produced in the injected slave laser under external optical injection. The inverting logic case can also be used as a wavelength converter — a key component in advanced wavelength-division multiplexing networks. As a result of this experimental investigation, a more comprehensive understanding of the locking parameters involved in injecting multiple lasers into a multi-mode cavity and the logic transition time is achieved. The performance of optical logic computations and wavelength conversion has the potential for ultrafast operation, limited primarily by the photon decay rate in the slave laser.

  1. Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

    Science.gov (United States)

    Butta, Mattia; Janosek, Michal; Ripka, Pavel

    2010-05-01

    In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

  2. Development of a diffuse element matrix in 'planar' technology. A particular application: logical gate with coupled emitter

    International Nuclear Information System (INIS)

    Rousseau, P.

    1968-01-01

    In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [fr

  3. Tyramine Hydrochloride Based Label-Free System for Operating Various DNA Logic Gates and a DNA Caliper for Base Number Measurements.

    Science.gov (United States)

    Fan, Daoqing; Zhu, Xiaoqing; Dong, Shaojun; Wang, Erkang

    2017-07-05

    DNA is believed to be a promising candidate for molecular logic computation, and the fluorogenic/colorimetric substrates of G-quadruplex DNAzyme (G4zyme) are broadly used as label-free output reporters of DNA logic circuits. Herein, for the first time, tyramine-HCl (a fluorogenic substrate of G4zyme) is applied to DNA logic computation and a series of label-free DNA-input logic gates, including elementary AND, OR, and INHIBIT logic gates, as well as a two to one encoder, are constructed. Furthermore, a DNA caliper that can measure the base number of target DNA as low as three bases is also fabricated. This DNA caliper can also perform concatenated AND-AND logic computation to fulfil the requirements of sophisticated logic computing. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Complex programmable logic device based alarm sequencer for nuclear power plants

    International Nuclear Information System (INIS)

    Khedkar, Ravindra; Solomon, J. Selva; KrishnaKumar, B.

    2001-01-01

    Complex Programmable Logic Device based Alarm Sequencer is an instrument, which detects alarms, memorizes them and displays the sequences of occurrence of alarms. It caters to sixteen alarm signals and distinguishes the sequence among any two alarms with a time resolution of 1 ms. The system described has been designed for continuous operation in process plants, nuclear power plants etc. The system has been tested and found to be working satisfactorily. (author)

  5. Programmable Logic Controllers for Systems of Automatic of the Level Crossing

    Directory of Open Access Journals (Sweden)

    Mieczyslaw Kornaszewski

    2006-01-01

    Full Text Available The railway crossings are vulnerable to incidence of high number of accidents often deadly. In order to face this problem, the modern systems of automatic of the level crossing have been introduced. These systems are based on Programmable Logic Controllers, which allow the designers to exploit self-control mechanisms, events acquiring, technical diagnostic which in turn enable remote control and acquisition of faults.

  6. Emergency Diesel: Safety-related instrumentation and control with programmable logic controllers

    International Nuclear Information System (INIS)

    Breidenich, G.; Luedtke, M.

    2004-01-01

    This report presents a new concept for the design of emergency diesel equipment protection circuits as a part of the safety related instrumentation in the nuclear power plant Biblis, units A and B. The concept was implemented with state of the art SIMATIC S7/316 programmable logic controllers (PLCs) and can be adapted to any system with high availability requirements (e.g. power plant turbines, aircraft engines, mining pumps etc). (orig.)

  7. Application of complex programmable logic devices in memory radiation effects test system

    International Nuclear Information System (INIS)

    Li Yonghong; He Chaohui; Yang Hailiang; He Baoping

    2005-01-01

    The application of the complex programmable logic device (CPLD) in electronics is emphatically discussed. The method of using software MAX + plus II and CPLD are introduced. A new test system for memory radiation effects is established by using CPLD devices-EPM7128C84-15. The old test system's function are realized and, moreover, a number of small scale integrated circuits are reduced and the test system's reliability is improved. (authors)

  8. Tunable Tribotronic Dual-Gate Logic Devices Based on 2D MoS2 and Black Phosphorus.

    Science.gov (United States)

    Gao, Guoyun; Wan, Bensong; Liu, Xingqiang; Sun, Qijun; Yang, Xiaonian; Wang, Longfei; Pan, Caofeng; Wang, Zhong Lin

    2018-03-01

    With the Moore's law hitting the bottleneck of scaling-down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self-powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual-gate logic device based on a MoS 2 field-effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm -1 . Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low-power-consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human-machine interfacing, data processing and transmission. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation

    Directory of Open Access Journals (Sweden)

    Arati M. Dixit

    2013-01-01

    Full Text Available The real-time nondestructive testing (NDT for crack detection and impact source identification (CDISI has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL. The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

  10. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

    International Nuclear Information System (INIS)

    Jinyuan Wu; Zonghan Shi; Irena Y Wang

    2003-01-01

    A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

  11. Numerical Analysis of an All-optical Logic XOR gate based on an active MZ interferometer

    DEFF Research Database (Denmark)

    Nielsen, Mads Lønstrup; Mørk, Jesper; Fjelde, T.

    2002-01-01

    are investigated numerically for a Mach-Zehnder interferometer (MZI) based XOR gate. For bit-rates up to 40 Gb/s, the synchronization tolerance of a MZI XOR gate is determined by the pulse width for RZ format. For the NRZ format, the tolerance decreases as the rise/fall-time approaches the timeslot. The gate...

  12. DBPM signal processing with field programmable gate arrays

    International Nuclear Information System (INIS)

    Lai Longwei; Yi Xing; Zhang Ning; Yang Guisen; Wang Baopeng; Xiong Yun; Leng Yongbin; Yan Yingbing

    2011-01-01

    DBPM system performance is determined by the design and implementation of beam position signal processing algorithm. In order to develop the system, a beam position signal processing algorithm is implemented on FPGA. The hardware is a PMC board ICS-1554A-002 (GE Corp.) with FPGA chip XC5VSX95T. This paper adopts quadrature frequency mixing to down convert high frequency signal to base. Different from conventional method, the mixing is implemented by CORDIC algorithm. The algorithm theory and implementation details are discussed in this paper. As the board contains no front end gain controller, this paper introduces a published patent-pending technique that has been adopted to realize the function in digital logic. The whole design is implemented with VHDL language. An on-line evaluation has been carried on SSRF (Shanghai Synchrotron Radiation Facility)storage ring. Results indicate that the system turn-by-turn data can measure the real beam movement accurately,and system resolution is 1.1μm. (authors)

  13. Trapped-ion quantum logic gates based on oscillating magnetic fields.

    Science.gov (United States)

    Ospelkaus, C; Langer, C E; Amini, J M; Brown, K R; Leibfried, D; Wineland, D J

    2008-08-29

    Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

  14. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    International Nuclear Information System (INIS)

    Nolida Yussup; Maslina Mohd Ibrahim; Lojius Lombigit; Nur Aira Abdul Rahman; Muhammad Rawi Mohamed Zin

    2013-01-01

    Full-text: Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed. (author)

  15. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    International Nuclear Information System (INIS)

    Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

    2014-01-01

    Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed

  16. Electron spin for classical information processing: a brief survey of spin-based logic devices, gates and circuits

    International Nuclear Information System (INIS)

    Bandyopadhyay, Supriyo; Cahay, Marc

    2009-01-01

    In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information processing device invariably causes current flow and an associated dissipation. Replacing 'charge' with the 'spin' of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient 'green electronics'. This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation. (topical review)

  17. Development of a fast time-to-digital converter (TDC) using a programmable gate array

    International Nuclear Information System (INIS)

    Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

    1994-09-01

    A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

  18. NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

    Science.gov (United States)

    Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

    2017-01-01

    This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

  19. Modeling and Simulation of a Non-Coherent Frequency Shift Keying Transceiver Using a Field Programmable Gate Array (FPGA)

    National Research Council Canada - National Science Library

    Voskakis, Konstantinos

    2008-01-01

    ...) receiver-transmitter in a Field Programmable Gate Array (FPGA). After introducing the theory behind the Non- Coherent BFSK demodulation implemented at the receiver, the design of transmitter and receiver is illustrated...

  20. Three-channel phase meters based on the AD8302 and field programmable gate arrays for heterodyne millimeter wave interferometer

    Czech Academy of Sciences Publication Activity Database

    Varavin, A.V.; Ermak, G.P.; Vasiliev, A.S.; Fateev, A.V.; Varavin, Mykyta; Žáček, František; Zajac, Jaromír

    2016-01-01

    Roč. 75, č. 11 (2016), s. 1009-1025 ISSN 0040-2508 Institutional support: RVO:61389021 Keywords : AD8302 * Interferometer * Millimeter wave * Phase meter * Programmable gate array * Tokamak Subject RIV: BL - Plasma and Gas Discharge Physics

  1. Programmable - logic equipment for ultrasound periodic inspections of reactor pressure vessels

    International Nuclear Information System (INIS)

    Haniger, L.

    1980-01-01

    Two alternatives are presented of programmable logic corresponding to the 2nd generation of the apparatus for performing periodic ultrasonic inspections of power reactor pressure vessels and a solution is outlined of inspecting the circumferential weld on the pressure vessel head. The apparatus will allow using any measuring head taken into consideration for operational inspection. Command words are taken from a punched type reader. Czechoslovak made RAM memories are used. The algorithm of instrument function is supposed to be controlled by a microprocessor as soon as necessary preconditions for this technology are created in Czechoslovakia

  2. A study on implementation of dynamic safety system in programmable logic controller for pressurized water reactor

    International Nuclear Information System (INIS)

    Kim, Ung Soo

    1997-02-01

    The dynamic safety system (DSS) is a computer based reactor protection system that has dynamic self-testing feature and fail-safe nature inherently. The inherent dynamic self-testing feature and fail-safe design provide a high level of reliability and low spurious trip rate. We can also reduce the time and human efforts to maintain the system by virtue of those features. Therefore, the application of the DSS to PWR has many advantages. The DSS has been applied only to advanced gas-cooled reactor (AGR) in the UK. In order to apply the DSS for PWR, the DSS has to be modified because there exist many differences between PWR and AGR for which the DSS was tested and installed. These differences are trip algorithms, monitored parameters, trip logics, and other conditions. In this study, the DSS algorithm is modified for PWR first. The modified DSS has several new features : 1) The modified DSS tests and processes time-dependent parameters, while the original DSS does not. 2) It has flexibility for handling several types of voting logic but the original DSS handles the only one type of voting - 2 out of 4 coincidence logic. Then, in this study, the modified DSS is implemented in programmable logic controller (PLC) using the ladder logic. Finally, the modified DSS is tested in two ways in this work : 1) The manual test is performed using direct input through the human computer interface (HCI) system. 2) The scenario based test is performed using input from the FISA-2/WS simulator. From the test results, it is shown that the modified DSS operates correctly in all conditions

  3. All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

    International Nuclear Information System (INIS)

    Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.

    2014-01-01

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials

  4. All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

    Science.gov (United States)

    Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.

    2014-01-01

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

  5. All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)

    2014-01-21

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

  6. Near-Infrared Ag2S Quantum Dots-Based DNA Logic Gate Platform for miRNA Diagnostics.

    Science.gov (United States)

    Miao, Peng; Tang, Yuguo; Wang, Bidou; Meng, Fanyu

    2016-08-02

    Dysregulation of miRNA expression is correlated with the development and progression of many diseases. These miRNAs are regarded as promising biomarkers. However, it is challenging to measure these low abundant molecules without employing time-consuming radioactive labeling or complex amplification strategies. Here, we present a DNA logic gate platform for miRNA diagnostics with fluorescence outputs from near-infrared (NIR) Ag2S quantum dots (QDs). Carefully designed toehold exchange-mediated strand displacements with different miRNA inputs occur on a solid-state interface, which control QDs release from solid-state interface to solution, responding to multiplex information on initial miRNAs. Excellent fluorescence emission properties of NIR Ag2S QDs certify the great prospect for amplification-free and sensitive miRNA assay. We demonstrate the potential of this platform by achieving femtomolar level miRNA analysis and the versatility of a series of logic circuits computation.

  7. Trapped-ion quantum logic gates based on oscillating magnetic fields

    Science.gov (United States)

    Ospelkaus, Christian; Langer, Christopher E.; Amini, Jason M.; Brown, Kenton R.; Leibfried, Dietrich; Wineland, David J.

    2009-05-01

    Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing. With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ions and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering decoherence, a fundamental source of decoherence in laser-mediated gates. A potentially beneficial environment for the implementation of such schemes is a cryogenic ion trap, because small length scale traps with low motional heating rates can be realized. A cryogenic ion trap experiment is currently under construction at NIST.

  8. Solving the Ternary Quantum-Dot Cellular Automata Logic Gate Problem by Means of Adiabatic Switching

    Science.gov (United States)

    Pecar, Primoz; Mraz, Miha; Zimic, Nikolaj; Janez, Miha; Lebar Bajec, Iztok

    2008-06-01

    Quantum-dot cellular automata (QCA) are one of the most promising alternative platforms of the future. Recent years have witnessed the development of basic logic structures as well as more complex processing structures, however most in the realm of binary logic. On the grounds that future platforms should not disregard the advantages of multi-valued logic, Lebar Bajec et al. were the first to show that quantum-dot cellular automata can be used for the implementation of ternary logic as well. In their study the ternary AND and OR logic functions proved to be the most troublesome primitive to implement. This research presents a revised solution that is based on adiabatic switching.

  9. The Programmable Logic Controller and its application in nuclear reactor systems

    Energy Technology Data Exchange (ETDEWEB)

    Palomar, J.; Wyman, R. [Lawrence Livermore National Lab., CA (United States)

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

  10. The Programmable Logic Controller and its application in nuclear reactor systems

    International Nuclear Information System (INIS)

    Palomar, J.; Wyman, R.

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out

  11. A visual dual-aptamer logic gate for sensitive discrimination of prion diseases-associated isoform with reusable magnetic microparticles and fluorescence quantum dots.

    Science.gov (United States)

    Xiao, Sai Jin; Hu, Ping Ping; Chen, Li Qiang; Zhen, Shu Jun; Peng, Li; Li, Yuan Fang; Huang, Cheng Zhi

    2013-01-01

    Molecular logic gates, which have attracted increasing research interest and are crucial for the development of molecular-scale computers, simplify the results of measurements and detections, leaving the diagnosis of disease either "yes" or "no". Prion diseases are a group of fatal neurodegenerative disorders that happen in human and animals. The main problem with a diagnosis of prion diseases is how to sensitively and selectively discriminate and detection of the minute amount of PrP(Res) in biological samples. Our previous work had demonstrated that dual-aptamer strategy could achieve highly sensitive and selective discrimination and detection of prion protein (cellular prion protein, PrP(C), and the diseases associated isoform, PrP(Res)) in serum and brain. Inspired by the advantages of molecular logic gate, we further conceived a new concept for dual-aptamer logic gate that responds to two chemical input signals (PrP(C) or PrP(Res) and Gdn-HCl) and generates a change in fluorescence intensity as the output signal. It was found that PrP(Res) performs the "OR" logic operation while PrP(C) performs "XOR" logic operation when they get through the gate consisted of aptamer modified reusable magnetic microparticles (MMPs-Apt1) and quantum dots (QDs-Apt2). The dual-aptamer logic gate simplifies the discrimination results of PrP(Res), leaving the detection of PrP(Res) either "yes" or "no". The development of OR logic gate based on dual-aptamer strategy and two chemical input signals (PrP(Res) and Gdn-HCl) is an important step toward the design of prion diseases diagnosis and therapy systems.

  12. A visual dual-aptamer logic gate for sensitive discrimination of prion diseases-associated isoform with reusable magnetic microparticles and fluorescence quantum dots.

    Directory of Open Access Journals (Sweden)

    Sai Jin Xiao

    Full Text Available Molecular logic gates, which have attracted increasing research interest and are crucial for the development of molecular-scale computers, simplify the results of measurements and detections, leaving the diagnosis of disease either "yes" or "no". Prion diseases are a group of fatal neurodegenerative disorders that happen in human and animals. The main problem with a diagnosis of prion diseases is how to sensitively and selectively discriminate and detection of the minute amount of PrP(Res in biological samples. Our previous work had demonstrated that dual-aptamer strategy could achieve highly sensitive and selective discrimination and detection of prion protein (cellular prion protein, PrP(C, and the diseases associated isoform, PrP(Res in serum and brain. Inspired by the advantages of molecular logic gate, we further conceived a new concept for dual-aptamer logic gate that responds to two chemical input signals (PrP(C or PrP(Res and Gdn-HCl and generates a change in fluorescence intensity as the output signal. It was found that PrP(Res performs the "OR" logic operation while PrP(C performs "XOR" logic operation when they get through the gate consisted of aptamer modified reusable magnetic microparticles (MMPs-Apt1 and quantum dots (QDs-Apt2. The dual-aptamer logic gate simplifies the discrimination results of PrP(Res, leaving the detection of PrP(Res either "yes" or "no". The development of OR logic gate based on dual-aptamer strategy and two chemical input signals (PrP(Res and Gdn-HCl is an important step toward the design of prion diseases diagnosis and therapy systems.

  13. Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA; Desenvolvimento de sistema de protecao para reator nuclear de pesquisa baseado em Field Programmable Gate Array - FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Martins, Roque Hudson da Silva

    2016-07-01

    This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

  14. High speed all optical logic gates based on quantum dot semiconductor optical amplifiers.

    Science.gov (United States)

    Ma, Shaozhen; Chen, Zhe; Sun, Hongzhi; Dutta, Niloy K

    2010-03-29

    A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

  15. Design of two and three input molecular logic gates using non-Watson-Crick base pairing-based molecular beacons.

    Science.gov (United States)

    Lin, Jia-Hui; Tseng, Wei-Lung

    2014-03-21

    This study presents a single, resettable, and sensitive molecular beacon (MB) used to operate molecular-scale logic gates. The MB consists of a random DNA sequence, a fluorophore at the 5'-end, and a quencher at the 3'-end. The presence of Hg(2+), Ag(+), and coralyne promoted the formation of stable T-Hg(2+)-T, C-Ag(+)-C, and A2-coralyne-A2 coordination in the MB probe, respectively, thereby driving its conformational change. The metal ion or small molecule-mediated coordination of mismatched DNA brought the fluorophore and the quencher into close proximity, resulting in collisional quenching of fluorescence between the two organic dyes. Because thiol can bind Hg(2+) and remove it from the T-Hg(2+)-T-based MB, adding thiol to a solution of the T-Hg(2+)-T-based MB allowed the fluorophore and the quencher to be widely separated. A similar phenomenon was observed when replacing Hg(2+) with Ag(+). Because Ag(+) strongly binds to iodide, cyanide, and cysteine, they were capable of removing Ag(+) from the C-Ag(+)-C-based MB, restoring the fluorescence of the MB. Moreover, the fluorescence of the A2-coralyne-A2-based MB could be switched on by adding polyadenosine. Using these analytes as inputs and the MB as a signal transducer, we successfully developed a series of two-input, three-input, and set-reset logic gates at the molecular level.

  16. Quinoline group based fluorescent sensor for detecting zinc ions in aqueous media and its logic gate behaviour

    International Nuclear Information System (INIS)

    Dong, Zhengping; Guo, Yueping; Tian, Xin; Ma, Jiantai

    2013-01-01

    A highly sensitive method for quantitative determination of Zn 2+ in water has been developed by using a novel fluorescent sensor NQA: (N-Quinolin-8-yl-2-[(quinolin-8-ylcarbamoylmethyl)-amino]-acetamide). The sensor displays great selectivity for Zn 2+ in the presence of other metal ions in aqueous solution and possesses an excellent sensitivity of about 2×10 −8 M for Zn 2+ . The binding stoichiometry, binding affinity, and pH sensitivity of the sensor have also been studied. Furthermore, the fluorescent changes of NQA upon the addition of cations (Cu 2+ and Zn 2+ ) are utilized to construct an INHIBIT logic gate at the molecular level, using Cu 2+ and Zn 2+ as chemical inputs and the fluorescence intensity as output. NQA has ideal chemical and spectroscopic properties that satisfy the criteria for further biological and environmental applications. - Highlights: ► A novel fluorescent sensor for Zn 2+ in water has been synthesized. ► The sensor displays high selectivity for Zn 2+ in the presence of other ions. ► The sensor exhibits excellent sensing ability under the physiological pH window. ► The sensor can be utilized as an INHIBIT logic gate at the molecular level.

  17. Implementation of quantum logic gates via Stark-tuned Förster resonance in Rydberg atoms

    Science.gov (United States)

    Huang, Xi-Rong; Hu, Chang-Sheng; Shen, Li-Tuo; Yang, Zhen-Biao; Wu, Huai-Zhi

    2018-02-01

    We present a scheme for implementation of controlled-Z and controlled-NOT gates via rapid adiabatic passage and Stark-tuned Förster resonance. By sweeping the Förster resonance once without passing through it and adiabatically tuning the angle-dependent Rydberg-Rydberg interaction of the dipolar nature, the system can be effectively described by a two-level system with the adiabatic theorem. The single adiabatic passage leads to a gate fidelity as high as 0.999 and a greatly reduced gate operation time. We investigate the scheme by considering an actual atomic level configuration with rubidium atoms, where the fidelity of the controlled-Z gate is still higher than 0.99 under the influence of the Zeeman effect.

  18. Low-photon-number optical switch and AND/OR logic gates based on quantum dot-bimodal cavity coupling system.

    Science.gov (United States)

    Ma, Shen; Ye, Han; Yu, Zhong-Yuan; Zhang, Wen; Peng, Yi-Wei; Cheng, Xiang; Liu, Yu-Min

    2016-01-11

    We propose a new scheme based on quantum dot-bimodal cavity coupling system to realize all-optical switch and logic gates in low-photon-number regime. Suppression of mode transmission due to the destructive interference effect is theoretically demonstrated by driving the cavity with two orthogonally polarized pulsed lasers at certain pulse delay. The transmitted mode can be selected by designing laser pulse sequence. The optical switch with high on-off ratio emerges when considering one driving laser as the control. Moreover, the AND/OR logic gates based on photon polarization are achieved by cascading the coupling system. Both proposed optical switch and logic gates work well in ultra-low energy magnitude. Our work may enable various applications of all-optical computing and quantum information processing.

  19. Automatic alternative phase-shift mask CAD layout tool for gate shrinkage of embedded DRAM in logic below 0.18 μm

    Science.gov (United States)

    Ohnuma, Hidetoshi; Kawahira, Hiroichi

    1998-09-01

    An automatic alternative phase shift mask (PSM) pattern layout tool has been newly developed. This tool is dedicated for embedded DRAM in logic device to shrink gate line width with improving line width controllability in lithography process with a design rule below 0.18 micrometers by the KrF excimer laser exposure. The tool can crete Levenson type PSM used being coupled with a binary mask adopting a double exposure method for positive photo resist. By using graphs, this tool automatically creates alternative PSM patterns. Moreover, it does not give any phase conflicts. By adopting it to actual embedded DRAM in logic cells, we have provided 0.16 micrometers gate resist patterns at both random logic and DRAM areas. The patterns were fabricated using two masks with the double exposure method. Gate line width has been well controlled under a practical exposure-focus window.

  20. Generation of high-fidelity controlled-NOT logic gates by coupled superconducting qubits

    International Nuclear Information System (INIS)

    Galiautdinov, Andrei

    2007-01-01

    Building on the previous results of the Weyl chamber steering method, we demonstrate how to generate high-fidelity controlled-NOT (CNOT) gates by direct application of certain physically relevant Hamiltonians with fixed coupling constants containing Rabi terms. Such Hamiltonians are often used to describe two superconducting qubits driven by local rf pulses. It is found that in order to achieve 100% fidelity in a system with capacitive coupling of strength g, one Rabi term suffices. We give the exact values of the physical parameters needed to implement such CNOT gates. The gate time and all possible Rabi frequencies are found to be t=π/(2g) and Ω 1 /g=√(64n 2 -1),n=1,2,3,.... Generation of a perfect CNOT gate in a system with inductive coupling, characterized by additional constant k, requires the presence of both Rabi terms. The gate time is again t=π/(2g), but now there is an infinite number of solutions, each of which is valid in a certain range of k and is characterized by a pair of integers (n,m), (Ω 1,2 /g)=√(16n 2 -((k-1/2)) 2 )±√(16m 2 -((k+1/2)) 2 ). We distinguish two cases, depending on the sign of the coupling constant: (i) the antiferromagnetic case (k≥0) with n≥m=0,1,2,... and (ii) the ferromagnetic case (k≤0) with n>m=0,1,2,.... We conclude with consideration of fidelity degradation by switching to resonance. Simulation of time evolution based on the fourth-order Magnus expansion reveals characteristics of the gate similar to those found in the exact case, with slightly shorter gate time and shifted values of the Rabi frequencies

  1. A control system based on field programmable gate array for papermaking sewage treatment

    International Nuclear Information System (INIS)

    Zhang, Zi Sheng; Xie, Chang; Xiong, Yan Qing; Liu, Zhi Qiang; Li, Qing

    2013-01-01

    A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

  2. Note: The design of thin gap chamber simulation signal source based on field programmable gate array

    International Nuclear Information System (INIS)

    Hu, Kun; Wang, Xu; Li, Feng; Jin, Ge; Lu, Houbing; Liang, Futian

    2015-01-01

    The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability

  3. A software framework for pipelined arithmetic algorithms in field programmable gate arrays

    Science.gov (United States)

    Kim, J. B.; Won, E.

    2018-03-01

    Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

  4. High-throughput gated photon counter with two detection windows programmable down to 70 ps width

    Energy Technology Data Exchange (ETDEWEB)

    Boso, Gianluca; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Zappa, Franco [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Mora, Alberto Dalla [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy)

    2014-01-15

    We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer.

  5. Field programmable gate array-assigned complex-valued computation and its limits

    Energy Technology Data Exchange (ETDEWEB)

    Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com [National Instruments, Ganghoferstrasse 70b, 80339 Munich (Germany); Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien (Austria); Zwick, Wolfgang; Klier, Jochen [National Instruments, Ganghoferstrasse 70b, 80339 Munich (Germany); Wenzel, Lothar [National Instruments, 11500 N MOPac Expy, Austin, Texas 78759 (United States); Gröschl, Martin [Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien (Austria)

    2014-09-15

    We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

  6. High-throughput gated photon counter with two detection windows programmable down to 70 ps width

    International Nuclear Information System (INIS)

    Boso, Gianluca; Tosi, Alberto; Zappa, Franco; Mora, Alberto Dalla

    2014-01-01

    We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer

  7. Failure mode taxonomy for assessing the reliability of Field Programmable Gate Array based Instrumentation and Control systems

    International Nuclear Information System (INIS)

    McNelles, Phillip; Zeng, Zhao Chang; Renganathan, Guna; Chirila, Marius; Lu, Lixuan

    2017-01-01

    Highlights: • The use FPGAs in I&C systems in Nuclear Power Plants is an important issue (IAEA). • OECD-NEA published a failure mode taxonomy for software-based digital I&C systems. • This paper extends the OECD-NEA taxonomy to model FPGA-based systems. • FPGA failure modes, failure effects, uncovering methods are categorized/described. • Provides an example of modelling an FPGA-Based RTS/ESFAS using the FPGA taxonomy. - Abstract: Field Programmable Gate Arrays (FPGAs) are a form of programmable digital hardware configured to perform digital logic functions. This configuration (programming) is performed using Hardware Description Language (HDL), making FPGAs a form of HDL Programmed Device (HPD). In the nuclear field, FPGAs have seen use in upgrades and replacements of obsolete Instrumentation and Control (I&C) systems. This paper expands upon previous work that resulted in extensive FPGA failure mode data, to allow for the application of the OECD-NEA failure modes taxonomy. The OECD-NEA taxonomy presented a method to model digital (software-based) I&C systems, based on the hardware and software failure modes, failure uncovering effects and levels of abstraction, using a Reactor Trip System/Engineering Safety Feature Actuation System (RTS/ESFAS) as an example system. To create the FPGA taxonomy, this paper presents an additional “sub-component” level of abstraction, to demonstrate the effect of the FPGA failure modes and failure categories on an FPGA-based system. The proposed FPGA taxonomy is based on the FPGA failure modes, failure categories, failure effects and uncovering situations. The FPGA taxonomy is applied to the RTS/ESFAS test system, to demonstrate the effects of the anticipated FPGA failure modes on a digital I&C system, and to provide a modelling example for this proposed taxonomy.

  8. Experience with the use of programmable logic controllers in nuclear safety applications. Final report

    International Nuclear Information System (INIS)

    Brown, E.M.; Stofko, M.J.

    1995-03-01

    This report describes the implementation and experience with Programmable Logic Controllers (PLC) for nuclear safety applications. Two applications are described. The first is an Anticipated Transient Without Scram (ATWS) mitigation system provided as a Diverse Auxiliary Feedwater Actuation System (DAFAS). It was implemented at Arizona Public Service's Palo Verde Nuclear Generating Station and has been in commercial operation since early 1992. The second system described is an Emergency Diesel Generator Bus Load Sequencer installed at Florida Power and Light's Turkey Point Nuclear Power Plant. This system was installed as part of an upgrade to the emergency power system in 1988. The experience gained in the design, development, implementation and qualification of these systems will be beneficial to utilities that are considering the utilization of PLCs for their plant applications

  9. Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

    International Nuclear Information System (INIS)

    KOCH, M.R.

    1999-01-01

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309/Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

  10. PID Neural Network Based Speed Control of Asynchronous Motor Using Programmable Logic Controller

    Directory of Open Access Journals (Sweden)

    MARABA, V. A.

    2011-11-01

    Full Text Available This paper deals with the structure and characteristics of PID Neural Network controller for single input and single output systems. PID Neural Network is a new kind of controller that includes the advantages of artificial neural networks and classic PID controller. Functioning of this controller is based on the update of controller parameters according to the value extracted from system output pursuant to the rules of back propagation algorithm used in artificial neural networks. Parameters obtained from the application of PID Neural Network training algorithm on the speed model of the asynchronous motor exhibiting second order linear behavior were used in the real time speed control of the motor. Programmable logic controller (PLC was used as real time controller. The real time control results show that reference speed successfully maintained under various load conditions.

  11. Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

    International Nuclear Information System (INIS)

    WHITE, K.A.

    2000-01-01

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309/Rev.1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

  12. Local and Remote Laboratory User Experimentation Access using Digital Programmable Logic

    Directory of Open Access Journals (Sweden)

    Ian A Grout

    2005-06-01

    Full Text Available This paper will discuss the structure and operation of a programmable logic based experimentation arrangement that is suitable for both local and remote teaching and learning scenarios targeting electronic and microelectronic circuit design and test principles. With this experimentation arrangement, the ability to provide both local and Internet based “remote” access for the student and the teacher can provide a number of advantages where physical laboratory accessibility is limited and/or the learning experience must be undertaken with one or more of the parties remotely based. The paper concentrates on the design and example use of a system developed within the University of Limerick.

  13. Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

    Science.gov (United States)

    Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

    2017-03-28

    Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

  14. Enhancement of ambipolar characteristics in single-walled carbon nanotubes using C{sub 60} and fabrication of logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Park, Steve [Department of Materials Science and Engineering, Stanford University, Durand Building, 496 Lomita Mall, Stanford, California 94305-4034 (United States); Nam, Ji Hyun [Department of Electrical Engineering, Stanford University, David Packard Building, 350 Serra Mall, Mail Code: 9505, Stanford, California 94305-9505 (United States); Koo, Ja Hoon; Lei, Ting; Bao, Zhenan, E-mail: zbao@stanford.edu [Department of Chemical Engineering, Stanford University, Shriram Center, 443 Via Ortega, Room 307, Stanford, California 94305-4145 (United States)

    2015-03-09

    We demonstrate a technique to convert p-type single-walled carbon nanotube (SWNT) network transistor into ambipolar transistor by thermally evaporating C{sub 60} on top. The addition of C{sub 60} was observed to have two effects in enhancing ambipolar characteristics. First, C{sub 60} served as an encapsulating layer that enhanced the ambipolar characteristics of SWNTs. Second, C{sub 60} itself served as an electron transporting layer that contributed to the n-type conduction. Such a dual effect enables effective conversion of p-type into ambipolar characteristics. We have fabricated inverters using our SWNT/C{sub 60} ambipolar transistors with gain as high as 24, along with adaptive NAND and NOR logic gates.

  15. Ghost in the PLC: stealth on-the-fly manipulation of programmable logic controllers’ I/O

    NARCIS (Netherlands)

    Abbasi, Ali

    2016-01-01

    Programmable Logic Controllers (PLCs) are a family of embedded devices used for physical process control. Similar to other embedded devices, PLCs are vulnerable to cyber attacks. Because they are used to control the physical processes of critical infrastructures, compromised PLCs constitute a

  16. Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

    Science.gov (United States)

    Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

    2016-07-01

    Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

  17. Upconversion luminescent logic gates and turn-on sensing of glutathione based on two-photon excited quantum dots conjugated with dopamine.

    Science.gov (United States)

    Gui, Rijun; Jin, Hui; Liu, Xifeng; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai

    2014-12-07

    Under the two-photon excitation, upconversion luminescent "INHIBIT" and "OR" logic gates of water-dispersed CdTe quantum dots (QDs) were constituted by conjugating the QDs with dopamine. This facilitated the development of a novel QDs-based upconversion luminescent probe for efficient turn-on sensing of glutathione.

  18. Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.

    Science.gov (United States)

    Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl

    2010-09-13

    Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).

  19. Environment dependent enhanced photoluminescence and Boolean logic gates like behavior of Bi2O3 and Ag:Bi2O3 nanostructures

    Science.gov (United States)

    Hariharan, S.; Karthikeyan, B.

    2018-03-01

    In the evolution of nanotechnology research for smart and precise sensor fabrication, here we report the implementation of simple logic gate operations performing by luminescent nanostructures in biomolecule environment based on photoluminescence (PL) technique. This present work deals with the luminescence property of α-Bi2O3 and Ag modified α-Bi2O3 nanostructures for D-glucose and Bovine serum albumin (BSA) sensing applications. These nanostructures are prepared by simple co-precipitation method and their morphology are examined using transmission electron microscope (TEM). We explore the PL characteristics of the prepared nanostructures and observe their change in PL intensity in the presence of D-glucose and BSA molecules. Enhancement in PL intensity is observed in the presence of D-glucose and BSA. Based on the PL response of prepared nanostructures in the biomolecule environment, we demonstrate biophotonic logic gates including YES, PASS 0, OR and INHIBIT gates.

  20. Molecular implementation of simple logic programs.

    Science.gov (United States)

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-10-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

  1. Grafting polyethylenimine with quinoline derivatives for targeted imaging of intracellular Zn{sup 2+} and logic gate operations

    Energy Technology Data Exchange (ETDEWEB)

    Pan, Yi; Shi, Yupeng; Chen, Junying; Wong, Chap-Mo; Zhang, Heng [Key Laboratory of Sensing Technology and Biomedical Instruments (Guangdong Province), School of Engineering, Sun Yat-Sen University, Guangzhou (China); Li, Mei-Jin [Key Laboratory of Analysis and Detection Technology for Food Safety, Ministry of Education and Fujian Province, Department of Chemistry, Fuzhou University, Fuzhou (China); Li, Cheuk-Wing [Institute of Chinese Medical Sciences, University of Macau (China); Yi, Changqing, E-mail: yichq@mail.sysu.edu.cn [Key Laboratory of Sensing Technology and Biomedical Instruments (Guangdong Province), School of Engineering, Sun Yat-Sen University, Guangzhou (China); Research Institute of Sun Yat-Sen University in Shenzhen, Shenzhen (China)

    2016-12-01

    In this study, a highly sensitive and selective fluorescent Zn{sup 2+} probe which exhibited excellent biocompatibility, water solubility, and cell-membrane permeability, was facilely synthesized in a single step by grafting polyethyleneimine (PEI) with quinoline derivatives. The primary amino groups in the branched PEI can increase water solubility and cell permeability of the probe PEIQ, while quinoline derivatives can specifically recognize Zn{sup 2+} and reduce the potential cytotoxicity of PEI. Basing on fluorescence off-on mechanism, PEIQ demonstrated excellent sensing capability towards Zn{sup 2+} in absolute aqueous solution, where a high sensitivity with a detection limit as low as 38.1 nM, and a high selectivity over competing metal ions and potential interfering amino acids, were achieved. Inspired by these results, elementary logic operations (YES, NOT and INHIBIT) have been constructed by employing PEIQ as the gate while Zn{sup 2+} and EDTA as chemical inputs. Together with the low cytotoxicity and good cell-permeability, the practical application of PEIQ in living cell imaging was satisfactorily demonstrated, emphasizing its wide application in fundamental biology research. - Graphical abstract: The fluorescent Zn{sup 2+} probe, PEIQ, is facilely synthesized by grafting PEI with 8-CAAQ, and demonstrated for the pratical applications in Zn{sup 2+} imaging and implementation of molecular logic operations within biological cells. - Highlights: • PEIQ, fluorescent Zn{sup 2+} probe, is synthesized by grafting PEI with quinoline derivatives. • PEIQ exhibits high sensitivity and selectivity in absolute aqueous solution. • PEIQ is biocompatible, water soluble, and cell-membrane permeable. • Elementary logic operations have been demonstrated for PEIQ/Zn{sup 2+}/EDTA system. • The practical application of PEIQ in living cell imaging is demonstrated.

  2. PENGEMBANGAN PERANGKAT PEMBELAJARAN MEKATRONIKA BERBASIS KOMPUTER POKOK BAHASAN PROGRAMMABLE LOGIC CONTROLLER BERORIENTASI PADA PEMBELAJARAN LANGSUNG

    Directory of Open Access Journals (Sweden)

    Wahyu Dwi Kurniawan

    2015-02-01

    Program Logic Controller is subject that many complaints by students of Department of Mechanical Engineering FT-Unesa. This is due to the lack of learning devices are used so that learning becomes less favorable and become passive. This study aims to develop computer-based learning device mechatronics subject-oriented programmable logic controller directly on student learning Mechanical Engineering Department Unesa FT. This study was conducted in two phases. Phase I, the development of the learning refers to the design of the Model 4D Thiagarajan (1974, Phase II, trial learning in the classroom using a design of one group pretest-posttest design. The findings of the study: (1 an average score of 3.32 learning assessment tools (pretty good, (2 average scores on tests of learning implementation I of 3.59 (good and trials II of 3.70 (both , (3 student learning outcomes of cognitive and psychomotor aspects have achieved individually and classical mastery, (4 students showed a positive response to the stated learning tehadap interested, excited, and motivated to attend lectures mechatronics; activity of the most dominant college students are discussin /practices relevant to teaching and learning that is on trial I is 36.46% and trials II 38.19%. Based on the analysis of data, it can be concluded that the developed learning feasible for use in lectures mechatronics. Implementation of the computer-based learning mechatronics subjects PLC can improve the quality of teaching and learning, as students showed a positive response, implementation category learning and learning outcomes both cognitive and psychomotor aspects of students have achieved mastery individually and classical. Keywords: development, learning, mechatronics, computer, plc

  3. The Bill & Melinda Gates Foundation's grant-making programme for global health.

    Science.gov (United States)

    McCoy, David; Kembhavi, Gayatri; Patel, Jinesh; Luintel, Akish

    2009-05-09

    The Bill & Melinda Gates Foundation is a major contributor to global health; its influence on international health policy and the design of global health programmes and initiatives is profound. Although the foundation's contribution to global health generally receives acclaim, fairly little is known about its grant-making programme. We undertook an analysis of 1094 global health grants awarded between January, 1998, and December, 2007. We found that the total value of these grants was US$8.95 billion, of which $5.82 billion (65%) was shared by only 20 organisations. Nevertheless, a wide range of global health organisations, such as WHO, the GAVI Alliance, the World Bank, the Global Fund to Fight AIDS, Tuberculosis and Malaria, prominent universities, and non-governmental organisations received grants. $3.62 billion (40% of all funding) was given to supranational organisations. Of the remaining amount, 82% went to recipients based in the USA. Just over a third ($3.27 billion) of funding was allocated to research and development (mainly for vaccines and microbicides), or to basic science research. The findings of this report raise several questions about the foundation's global health grant-making programme, which needs further research and assessment.

  4. Auto- and hetero-associative memory using a 2-D optical logic gate

    Science.gov (United States)

    Chao, Tien-Hsin

    1989-06-01

    An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

  5. Simultaneous G-Quadruplex DNA Logic.

    Science.gov (United States)

    Bader, Antoine; Cockroft, Scott L

    2018-04-03

    A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Optical logic gates based on electro-optic modulation with Sagnac interferometer.

    Science.gov (United States)

    Li, Qiliang; Zhu, Mengyun; Li, Dongqiang; Zhang, Zhen; Wei, Yizhen; Hu, Miao; Zhou, Xuefang; Tang, Xianghong

    2014-07-20

    In this work, we present a new structure to realize optical logic operation in a Sagnac interferometer with electro-optical modulation. In the scheme, we divide two counterpropagation signals in a Sagnac loop to two different arms with the electro-optical crystal by using two circulators. Lithium niobate materials whose electro-optical coefficient can be as large as 32.2×10(-12)  m/V make up the arms of the waveguides. Using the transfer matrix of the fiber coupler, we analyze the propagation of signals in this system and obtain the transmission characteristic curves and the extinction ratio. The results indicate that this optical switching has a high extinction ratio of about 60 dB and an ultrafast response time of 2.036 ns. In addition, the results reveal that the change of the dephasing between the two input signals and the modification of the modulation voltage added to the electro-optical crystal leads to the change of the extinction ratio. We also conclude that, in cases of the dephasing of two initial input signals Δφ=0, we can obtain the various logical operations, such as the logical operations D=A¯·B, D=A·B¯, C=A+B, and D=A⊕B in ports C and D of the system by adjusting the modulation voltage. When Δφ≠0, we obtain the arithmetic operations D=A+B, C=A⊕B, D=A·B¯, and C=A¯·B in ports C and D. This study is significant for the design of all optical networks by adjusting the modulation voltage.

  7. Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes† †Electronic supplementary information (ESI) available: Chemicals, materials and DNA sequences used in the investigation, the construction of YES, AND, OR, XOR and INH logic gates, CD and PAGE experimental results. See DOI: 10.1039/c7sc05246d

    Science.gov (United States)

    Lin, Xiaodong; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei

    2018-01-01

    The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way. PMID:29675221

  8. Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

    Directory of Open Access Journals (Sweden)

    Stephen Brown

    1996-01-01

    Full Text Available This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.

  9. A digital optical phase-locked loop for diode lasers based on field programmable gate array

    Energy Technology Data Exchange (ETDEWEB)

    Xu Zhouxiang; Zhang Xian; Huang Kaikai; Lu Xuanhui [Physics Department, Zhejiang University, Hangzhou, 310027 (China)

    2012-09-15

    We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

  10. Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants

    International Nuclear Information System (INIS)

    2016-01-01

    Field programmable gate arrays (FPGAs) are gaining increased attention worldwide for application in nuclear power plant (NPP) instrumentation and control (I&C) systems, particularly for safety and safety related applications, but also for non-safety ones. NPP operators and equipment suppliers see potential advantages of FPGA based digital I&C systems as compared to microprocessor based applications. This is because FPGA based systems can be made simpler, more testable and less reliant on complex software (e.g. operating systems), and are easier to qualify for safety and safety related applications. This publication results from IAEA consultancy meetings covering the various aspects, including design, qualification, implementation, licensing, and operation, of FPGA based I&C systems in NPPs

  11. Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

    Science.gov (United States)

    Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

    2017-01-01

    Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

  12. Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

    Science.gov (United States)

    Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

    2017-01-01

    Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

  13. A digital optical phase-locked loop for diode lasers based on field programmable gate array

    Science.gov (United States)

    Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

    2012-09-01

    We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

  14. Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

    Energy Technology Data Exchange (ETDEWEB)

    Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

    2016-05-15

    Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

  15. Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

    CERN Document Server

    Sivasubramaniyan, Sriram

    Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

  16. Design and Implementation of Video Shot Detection on Field Programmable Gate Arrays

    Directory of Open Access Journals (Sweden)

    Jharna Majumdar

    2012-09-01

    Full Text Available Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays.

  17. Real-time field programmable gate array architecture for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2001-01-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

  18. Control Systems of Rubber Dryer Machinery Components Using Programmable Logic Control (PLC)

    Science.gov (United States)

    Hendra; Yulianto, A. S.; Indriani, A.; Hernadewita; Hermiyetti

    2018-02-01

    Application of programmable logic control (PLC) is widely used on the control systems in the many field engineering such as automotive, aviation, food processing and other industries [1-2]. PLC is simply program to control many automatic activity, easy to use, flexible and others. PLC using the ladder program to solve and regulated the control system component. In previous research, PLC was used for control system of rotary dryer machine. In this paper PLC are used for control system of motion component in the rubber dryer machinery. Component of rubber dryer machine is motors, gearbox, sprocket, heater, drying chamber and bearing. Principle working of rubber dryer machinery is wet rubber moving into the drying chamber by sprocket. Sprocket is driven by motors that conducted by PLC to moving and set of wet rubber on the drying chamber. Drying system uses greenhouse effect by making hanger dryer design in the form of line path. In this paper focused on motion control system motors and sensors drying rubber using PLC. The results show that control system of rubber dryer machinery can work in accordance control input and the time required to dry the rubber.

  19. Methods of software V and V for a programmable logic controller in NPPs

    International Nuclear Information System (INIS)

    Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Son, Han Seong; Lee, Jang Soo; Kwon, Kee Choon

    2004-01-01

    This paper addresses the Verification and Validation (V and V) process and methodology for embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed in the Korea Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System (ESF-CCS) as well as safety-grade PLC. Safety-grade PLC will be a major component that composes the RPS systems and ESF-CCS systems as nuclear instruments and control equipments. This paper describes the V and V guidelines and procedure, V and V environment, V and V process and methodology, and the V and V tools by the KNICS projects. Specially, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase of the software development life cycle. Main activities of the real-time operating system Software Requirement Specification(SRS) V and V of the PLC are the technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14(MOST-KSRG 7/Appendix 15 in Korea will be issued soon) criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to verify the upcoming software life cycle in the KNICS projects. (author)

  20. V and V methods of a safety-critical software for a programmable logic controller

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Kong, Seung Ju [Korea Hydro and Nuclear Power Co., Ltd, Daejeon (Korea, Republic of)

    2005-11-15

    This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects.

  1. Software V and V methods for a safety - grade programmable logic controller

    International Nuclear Information System (INIS)

    Jang Yeol Kim; Young Jun Lee; Kyung Ho Cha; Se Woo Cheon; Jang Soo Lee; Kee Choon Kwon

    2006-01-01

    This paper addresses the Verification and Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety- grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines and procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects. (author)

  2. V and V methods of a safety-critical software for a programmable logic controller

    International Nuclear Information System (INIS)

    Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon; Kong, Seung Ju

    2005-01-01

    This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects

  3. A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

    International Nuclear Information System (INIS)

    Song, S. H.; Lee, M. S.; Kim, T. H.; Park, C. H.; Park, S. P.; Kim, H. S.

    2014-01-01

    As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system

  4. A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

    Energy Technology Data Exchange (ETDEWEB)

    Song, S. H. [Korea University, Seoul (Korea, Republic of); Lee, M. S.; Kim, T. H. [Formal Work Inc., Seoul (Korea, Republic of); Park, C. H. [LINE Corp., Tokyo (Japan); Park, S. P. [Ahnlab Inc., Seoul (Korea, Republic of); Kim, H. S. [Sejong University, Seoul (Korea, Republic of)

    2014-08-15

    As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system.

  5. Real-time object tracking system based on field-programmable gate array and convolution neural network

    Directory of Open Access Journals (Sweden)

    Congyi Lyu

    2016-12-01

    Full Text Available Vision-based object tracking has lots of applications in robotics, like surveillance, navigation, motion capturing, and so on. However, the existing object tracking systems still suffer from the challenging problem of high computation consumption in the image processing algorithms. The problem can prevent current systems from being used in many robotic applications which have limitations of payload and power, for example, micro air vehicles. In these applications, the central processing unit- or graphics processing unit-based computers are not good choices due to the high weight and power consumption. To address the problem, this article proposed a real-time object tracking system based on field-programmable gate array, convolution neural network, and visual servo technology. The time-consuming image processing algorithms, such as distortion correction, color space convertor, and Sobel edge, Harris corner features detector, and convolution neural network were redesigned using the programmable gates in field-programmable gate array. Based on the field-programmable gate array-based image processing, an image-based visual servo controller was designed to drive a two degree of freedom manipulator to track the target in real time. Finally, experiments on the proposed system were performed to illustrate the effectiveness of the real-time object tracking system.

  6. Auto and hetero-associative memory using a 2-D optical logic gate

    Science.gov (United States)

    Chao, Tien-Hsin (Inventor)

    1992-01-01

    An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

  7. Nanoeletromechanical switch and logic circuits formed therefrom

    Science.gov (United States)

    Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  8. Design of digital logic control for accelerator magnet power supply

    International Nuclear Information System (INIS)

    Long Fengli; Hu Wei; Cheng Jian

    2008-01-01

    For the accelerator magnet power supply, usually the Programmable Logic Controller (PLC) is used to server as the controller for logic protection and control. Along with the development of modern accelerator technology, it is a trend to use fully-digital control to the magnet power supply. It is possible to integrate the logic control part into the digital control component of the power supply, for example, the Field Programmable Gate Array (FPGA). The paper introduces to different methods which are designed for the logic protection and control for accelerator magnet power supplies with the FPGA as the control component. (authors)

  9. Small RNA-based feedforward loop with AND-gate logic regulates extrachromosomal DNA transfer in Salmonella.

    Science.gov (United States)

    Papenfort, Kai; Espinosa, Elena; Casadesús, Josep; Vogel, Jörg

    2015-08-25

    Horizontal gene transfer via plasmid conjugation is a major driving force in microbial evolution but constitutes a complex process that requires synchronization with the physiological state of the host bacteria. Although several host transcription factors are known to regulate plasmid-borne transfer genes, RNA-based regulatory circuits for host-plasmid communication remain unknown. We describe a posttranscriptional mechanism whereby the Hfq-dependent small RNA, RprA, inhibits transfer of pSLT, the virulence plasmid of Salmonella enterica. RprA employs two separate seed-pairing domains to activate the mRNAs of both the sigma-factor σ(S) and the RicI protein, a previously uncharacterized membrane protein here shown to inhibit conjugation. Transcription of ricI requires σ(S) and, together, RprA and σ(S) orchestrate a coherent feedforward loop with AND-gate logic to tightly control the activation of RicI synthesis. RicI interacts with the conjugation apparatus protein TraV and limits plasmid transfer under membrane-damaging conditions. To our knowledge, this study reports the first small RNA-controlled feedforward loop relying on posttranscriptional activation of two independent targets and an unexpected role of the conserved RprA small RNA in controlling extrachromosomal DNA transfer.

  10. A Cu²⁺-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate.

    Science.gov (United States)

    Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

    2015-06-15

    A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu(2+) over other metal ions in acetonitrile. Upon addition of Cu(2+) ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu(2+), the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu(2+) can be restored with the introduction of EDTA or S(2-). Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu(2+) and S(2-) as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated. Copyright © 2015 Elsevier B.V. All rights reserved.

  11. Design and Simulation of Automatic Ballast System on Catamaran Ship Based on Programmable Logic Control

    Directory of Open Access Journals (Sweden)

    Indra Ranu Kusuma

    2017-06-01

    Full Text Available Characteristics of catamaran ship which has deficiency to ship stability during maneuvering. to that end, this paper concerns about ballast system design in support of the safety and comfort of passengers on the catamaran boat. the discussion is done by creating a mathematical model of each component in the block diagram of the ballast system. then determine the pid value of the system and add the compensator for the system to run stable. further analyzed with the help of matlab software to get transient system response. with the automation system on the ballast system, it is expected that the motion of the ship can work automatically and provide a better response in the stability of the catamaran type ship. the ballast system begins to work against the tilt of the ship at 6.7 seconds at a certain angle, and will continue to work during the vessel maneuvering. judging from the 6.7 second system response time, the convenience of the passengers is not disturbed (the system response is not too fast. one way to reduce the rolling that occurs on the ship is to optimize the performance of the ballast system. performance optimization is done by using programmable logic controller (plc. plc used is omron cpm1a-30cdr-a-v1. the process is done by making the installation plant model of the ballast system as a control medium. followed by creating a control circuit consisting of wiring i / o, limit switch circuits, power supplies and programming languages associated with plcs. the result of the control is expected to regulate fluid flow in the ballast system automatically resulting in a rapid response to the stability of the ship.

  12. D0 General Support: The Use of Programmable Logic Controllers (PLCs) at D0

    International Nuclear Information System (INIS)

    Hance, R.

    2000-01-01

    With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

  13. A dansyl group modified SBA-15 INHIBIT logic gate with [Hg2+ and Cl-] or [Hg2+ and Br-] as inputs

    Science.gov (United States)

    Wang, Xiaoyu; Yang, Honglei

    2013-07-01

    We developed a SBA-15-based INHIBIT logic gate (DA-SBA-15) which was prepared by covalent immobilization of a dansylamide derivative into the channels of the mesoporous silica material (SBA-15) via (3-aminopropyl)triethoxysilane (APTES) groups. A series of characteristic results proved that the fluorescent ligand was successfully grafted into the mesopores of SBA-15. The fluorescent characterization revealed excellent selectivity of DA-SBA-15 to the Hg2+ ion. Moreover, DA-SBA-15 can be considered as a selective fluorescent probe for Cl- and Br-. The fluorescent changes of DA-SBA-15 upon the addition of ions (Hg2+, Cl- and Br-) were utilized as an INH logic gate at the molecular level, using [Hg2+ and Cl-] or [Hg2+ and Br-] as chemical inputs and the fluorescence intensity signal as output.

  14. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  15. Development of measurement system for radiation effect on static random access memory based field programmable gate array

    International Nuclear Information System (INIS)

    Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

    2009-01-01

    Based on the detailed investigation in field programmable gate array(FPGA) radiation effects theory, a measurement system for radiation effects on static random access memory(SRAM)-based FPGA was developed. The testing principle of internal memory, function and power current was introduced. The hardware and software implement means of system were presented. Some important parameters for radiation effects on SRAM-based FPGA, such as configuration RAM upset section, block RAM upset section, function fault section and single event latchup section can be gained with this system. The transmission distance of the system can be over 50 m and the maximum number of tested gates can reach one million. (authors)

  16. All-optical OR/NOR Bi-functional logic gate by using cross-gain modulation in semiconductor optical amplifiers

    International Nuclear Information System (INIS)

    Choi, Kyoung Sun; Byun, Young Tae; Lee, Seok; Jhon, Young Min

    2010-01-01

    An OR/NOR bi-functional all-optical logic gate has been experimentally demonstrated at 10 Gbit/s by using cross-gain modulation (XGM) in only 2 semiconductor optical amplifiers (SOAs). One SOA was used for NOR operation and the other SOA was used for inversion to obtain OR operation. Numerical simulation has also been performed, which coincided well with the experimental results.

  17. Proposal of ultra-compact NAND/NOR/XNOR all-optical logic gates based on a nonlinear 3x1 multimode interference

    Science.gov (United States)

    Tajaldini, Mehdi; Mat Jafri, M. Z.

    2014-05-01

    We present a highly miniaturized multimode interference (MMI) coupler based on nonlinear modal propagation analysis (NMPA) method as a novel design method and potential application for optical NAND, NOR and XNOR logic gates for Boolean logic signal processing devices. Crystalline polydiacetylene is used to allow the appearances of nonlinear effects in low input intensities and ultra- short length to control the MMI coupler as an active device to access light switching due to its high nonlinear susceptibility. We consider a 10x33 μm2 MMI structure with three inputs and one output. Notably, the access facets are single-mode waveguides with sub-micron width. The center input contributes to control the induced light propagation in MMI by intensity variation whereas others could be launched by particular intensity when they are ON and 0 in OFF. Output intensity is analyzed in various sets of inputs to show the capability of Boolean logic gates, the contrast between ON and OFF is calculated on mentioned gates to present the efficiency. Good operation in low intensity and highly miniaturized MMI coupler is observed. Furthermore, nonlinear effects could be realized through the modal interferences. The issue of high insertion loss is addressed with a 3×3 upgraded coupler. Furthermore, the main significant aspect of this paper is simulating an MMI coupler that is launched by three nonlinear inputs, simultaneously, whereas last presents have never studied more than one input in nonlinear regimes.

  18. A high performance gate drive for large gate turn off thyristors

    Energy Technology Data Exchange (ETDEWEB)

    Szilagyi, C.P.

    1993-01-01

    Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

  19. Construction of high-dimensional universal quantum logic gates using a Λ system coupled with a whispering-gallery-mode microresonator.

    Science.gov (United States)

    He, Ling Yan; Wang, Tie-Jun; Wang, Chuan

    2016-07-11

    High-dimensional quantum system provides a higher capacity of quantum channel, which exhibits potential applications in quantum information processing. However, high-dimensional universal quantum logic gates is difficult to achieve directly with only high-dimensional interaction between two quantum systems and requires a large number of two-dimensional gates to build even a small high-dimensional quantum circuits. In this paper, we propose a scheme to implement a general controlled-flip (CF) gate where the high-dimensional single photon serve as the target qudit and stationary qubits work as the control logic qudit, by employing a three-level Λ-type system coupled with a whispering-gallery-mode microresonator. In our scheme, the required number of interaction times between the photon and solid state system reduce greatly compared with the traditional method which decomposes the high-dimensional Hilbert space into 2-dimensional quantum space, and it is on a shorter temporal scale for the experimental realization. Moreover, we discuss the performance and feasibility of our hybrid CF gate, concluding that it can be easily extended to a 2n-dimensional case and it is feasible with current technology.

  20. High-sensitivity assay for Hg (II) and Ag (I) ion detection: A new class of droplet digital PCR logic gates for an intelligent DNA calculator.

    Science.gov (United States)

    Cheng, Nan; Zhu, Pengyu; Xu, Yuancong; Huang, Kunlun; Luo, Yunbo; Yang, Zhansen; Xu, Wentao

    2016-10-15

    The first example of droplet digital PCR logic gates ("YES", "OR" and "AND") for Hg (II) and Ag (I) ion detection has been constructed based on two amplification events triggered by a metal-ion-mediated base mispairing (T-Hg(II)-T and C-Ag(I)-C). In this work, Hg(II) and Ag(I) were used as the input, and the "true" hierarchical colors or "false" green were the output. Through accurate molecular recognition and high sensitivity amplification, positive droplets were generated by droplet digital PCR and viewed as the basis of hierarchical digital signals. Based on this principle, YES gate for Hg(II) (or Ag(I)) detection, OR gate for Hg(II) or Ag(I) detection and AND gate for Hg(II) and Ag(I) detection were developed, and their sensitively and selectivity were reported. The results indicate that the ddPCR logic system developed based on the different indicators for Hg(II) and Ag(I) ions provides a useful strategy for developing advanced detection methods, which are promising for multiplex metal ion analysis and intelligent DNA calculator design applications. Copyright © 2016 Elsevier B.V. All rights reserved.

  1. Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Shin, SeungJun; Yu, YunSeop; Choi, JungBum

    2008-10-01

    New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

  2. Design of acoustic logging signal source of imitation based on field programmable gate array

    International Nuclear Information System (INIS)

    Zhang, K; Ju, X D; Lu, J Q; Men, B Y

    2014-01-01

    An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

  3. Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

    Energy Technology Data Exchange (ETDEWEB)

    Shan, Jaffry Syed [Hamdard University, Karachi (Pakistan); Abbas, Syed Haider; Lee, Jung Ryul [Dept. of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Kang, Dong Hoon [Advanced Materials Research Team, Korea Railroad Research Institute, Uiwang (Korea, Republic of)

    2015-12-15

    Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm{sup 2} with 0.5 mm interval) to 87.5% (scanning of 200x200mm{sup 2} with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

  4. Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

    International Nuclear Information System (INIS)

    Shan, Jaffry Syed; Abbas, Syed Haider; Lee, Jung Ryul; Kang, Dong Hoon

    2015-01-01

    Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm 2 with 0.5 mm interval) to 87.5% (scanning of 200x200mm 2 with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection

  5. Development of field programmable gate array-based reactor trip functions using systems engineering approach

    Energy Technology Data Exchange (ETDEWEB)

    Jung, Jae Cheon; Ahmed, Ibrahim [Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

    2016-08-15

    Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

  6. Development and simulation of soft morphological operators for a field programmable gate array

    Science.gov (United States)

    Tickle, Andrew J.; Harvey, Paul K.; Smith, Jeremy S.; Wu, Q. Henry

    2013-04-01

    In image processing applications, soft mathematical morphology (MM) can be employed for both binary and grayscale systems and is derived from set theory. Soft MM techniques have improved behavior over standard morphological operations in noisy environments, as they can preserve small details within an image. This makes them suitable for use in image processing applications on portable field programmable gate arrays for tasks such as robotics and security. We explain how the systems were developed using Altera's DSP Builder in order to provide optimized code for the many different devices currently on the market. Also included is how the circuits can be inserted and combined with previously developed work in order to increase their functionality. The testing procedures involved loading different images into these systems and analyzing the outputs against MATLAB-generated validation images. A set of soft morphological operations are described, which can then be applied to various tasks and easily modified in size via altering the line buffer settings inside the system to accommodate a range of image attributes ranging from image sizes such as 320×240 pixels for basic webcam imagery up to high quality 4000×4000 pixel images for military applications.

  7. Design of acoustic logging signal source of imitation based on field programmable gate array

    Science.gov (United States)

    Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

    2014-08-01

    An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

  8. Field programmable gate array based reconfigurable scanning probe/optical microscope.

    Science.gov (United States)

    Nowak, Derek B; Lawrence, A J; Dzegede, Zechariah K; Hiester, Justin C; Kim, Cliff; Sánchez, Erik J

    2011-10-01

    The increasing popularity of nanometrology and nanospectroscopy has pushed researchers to develop complex new analytical systems. This paper describes the development of a platform on which to build a microscopy tool that will allow for flexibility of customization to suit research needs. The novelty of the described system lies in its versatility of capabilities. So far, one version of this microscope has allowed for successful near-field and far-field fluorescence imaging with single molecule detection sensitivity. This system is easily adapted for reflection, polarization (Kerr magneto-optical (MO)), Raman, super-resolution techniques, and other novel scanning probe imaging and spectroscopic designs. While collecting a variety of forms of optical images, the system can simultaneously monitor topographic information of a sample with an integrated tuning fork based shear force system. The instrument has the ability to image at room temperature and atmospheric pressure or under liquid. The core of the design is a field programmable gate array (FPGA) data acquisition card and a single, low cost computer to control the microscope with analog control circuitry using off-the-shelf available components. A detailed description of electronics, mechanical requirements, and software algorithms as well as examples of some different forms of the microscope developed so far are discussed.

  9. Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

    Science.gov (United States)

    Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

    Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

  10. Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

    Science.gov (United States)

    Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

    2017-01-01

    Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

  11. Programmable combinational logic trigger system for high energy particle physics experiments

    International Nuclear Information System (INIS)

    Platner, E.D.

    1976-01-01

    A fast logic system designed to select predetermined combinations of three hits in three detectors is described. Central to this system is a random access memory IC that was especially designed for this application

  12. Use of advanced programmable logic controllers to monitor and control the Elmo Bumpy Torus-proof-of-principle device

    International Nuclear Information System (INIS)

    Boyd, B.A.

    1983-01-01

    The Elmo Bumpy Torus - Proof-of-Principle (EBT-P) device is designed with an instrumentation and control system based upon the use of an advanced Programmable Logic Controller (PLC). The modern PLC incorporates many advanced programming features not available in earlier PLC's intended for application to conventional relay logic replacement. The additional power and flexibility of these modern PLC's is especially applicable to an experimental device such as EBT-P which is made up of several complex interrelated subsystems whose operational characteristics will be evolving throughout the lifetime of the device. The rationale for the selection of advanced PLC's for EBT-P and the approach taken to design of the software developed to control EBT-P are the topics addressed in this paper

  13. System design specification for rotary mode core sample trucks No. 2, 3, and 4 programmable logic controller

    International Nuclear Information System (INIS)

    Dowell, J.L.; Akers, J.C.

    1995-01-01

    The system this document describes controls several functions of the Core Sample Truck(s) used to obtain nuclear waste samples from various underground storage tanks at Hanford. The system will monitor the sampling process and provide alarms and other feedback to insure the sampling process is performed within the prescribed operating envelope. The intended audience for this document is anyone associated with rotary or push mode core sampling. This document describes the Alarm and Control logic installed on Rotary Mode Core Sample Trucks (RMCST) number-sign 2, 3, and 4. It is intended to define the particular requirements of the RMCST alarm and control operation (not defined elsewhere) sufficiently for detailed design to implement on a Programmable Logic Controller (PLC)

  14. Operating experiences with programmable logic controller (PLC) system of Indian Pressurised Heavy Water Reactors (PHWR)

    International Nuclear Information System (INIS)

    Ughade, A.V.; Singh, Ranjeet; Bhattacharya, P.K.; Kulkarni, R.K.; Chandra, Umesh

    2005-01-01

    PLC system was introduced for the first time in Kaiga-1,2 and RAPS-3,4 Nuclear Power Plants (NPPs) for Station Logic Control of Non Safety Related (NSR) and Safety related (SR) systems. However, the safety system logics are still relay based. The experience on the deployment of PLC system, which is computer-based, has brought out various implementation issues. This paper give details of such experiences, the solutions emerged and applied for plants under operation/construction. (author)

  15. A test system and supervisory control and data acquisition application with programmable logic controller for thermoelectric generators

    International Nuclear Information System (INIS)

    Ahiska, Rasit; Mamur, Hayati

    2012-01-01

    Highlights: ► A new TEG test measurement system with the PLC has been carried out. ► A new SCADA program has been written and tested for the test measurement system. ► An operator panel has been used for monitoring to the instant TEG data. ► All of the measurement data of TEG have been aggregated in the system. - Abstract: In this study, a new test measurement system and supervisory control and data acquisition application with programmable logic controller has been carried out to be enable the collection of the data of thermoelectric generator for the usage of thermoelectric modules as thermoelectric generator. During the production of the electric energy from the thermoelectric generator, the temperatures of the surfaces of the thermoelectric generator, current–voltage values obtained from output of the thermoelectric generator, hot and cold flows have been measured by the newly established system instantly. All these data have been monitored continuously from the computer and recorded by a supervisory control and data acquisition program. At the same time, in environments where there was no computer, an operator panel with the ability to communicate with the programmable logic controller has been added for the monitoring of the instant thermoelectric generator data. All of the measurement data of the thermoelectric generator have been aggregated in the new test measurement and supervisory control and data acquisition system. The setup test measurement system has been implemented on the thermoelectric generator system with about 10 W. Thermoelectric generators, Altec-GM-1 brand-coded have been examined by the new proposed test measurement system and the values of maximum power and thermoelectric generator efficiency were calculated by the programmable logic controller. When the obtained results were compared with the datasheets, the relative error for the maximum power was around 4% and the value for efficiency was below 3%.

  16. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews.

    Science.gov (United States)

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to 'think' conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions.

  17. Use of Field Programmable Gate Array Technology in Future Space Avionics

    Science.gov (United States)

    Ferguson, Roscoe C.; Tate, Robert

    2005-01-01

    Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

  18. Logic gate system with three outputs and three inputs based on switchable electrocatalysis of glucose by glucose oxidase entrapped in chitosan films.

    Science.gov (United States)

    Liu, Shuang; Wang, Lei; Lian, Wenjing; Liu, Hongyun; Li, Chen-Zhong

    2015-01-01

    A logic-gate system with three outputs and three inputs was developed based on the bioelectrocatalysis of glucose by glucose oxidase (GOx) entrapped in chitosan films on the electrode surface by means of ferrocenedicarboxylic acid (Fc(COOH)2 ). Cyclic voltammetric (CV) signals of Fc(COOH)2 exhibited pH-triggered on/off behavior owing to electrostatic interactions between the film and the probe at different pH levels. The addition of glucose greatly increased the oxidation peak current (Ipa ) through the electrocatalytic reaction. pH and glucose were selected as two inputs. As a reversible inhibitor of GOx, Cu(2+) was chosen as the third input. The combination of three inputs led to Ipa with different values according to different mechanisms, which were defined as three outputs with two thresholds. The logic gate with three outputs by using one type of enzyme provided a novel model to build logic circuits based on biomacromolecules, which might be applied to the intelligent medical diagnostics as smart biosensors in the future. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

    Energy Technology Data Exchange (ETDEWEB)

    Ahmed, Ibrahim [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of); Jung, Jaecheon, E-mail: jcjung@kings.ac.kr [Department of Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, 658-91 Haemaji-ro, Seosang-myeon, Ulju-gun, Ulsan 45014 (Korea, Republic of); Heo, Gyunyoung [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of)

    2017-06-15

    Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

  20. Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jaecheon; Heo, Gyunyoung

    2017-01-01

    Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

  1. Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

    Science.gov (United States)

    Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

    2018-06-01

    Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

  2. Simultaneous multichannel wavelength multicasting and XOR logic gate multicasting for three DPSK signals based on four-wave mixing in quantum-dot semiconductor optical amplifier.

    Science.gov (United States)

    Qin, Jun; Lu, Guo-Wei; Sakamoto, Takahide; Akahane, Kouichi; Yamamoto, Naokatsu; Wang, Danshi; Wang, Cheng; Wang, Hongxiang; Zhang, Min; Kawanishi, Tetsuya; Ji, Yuefeng

    2014-12-01

    In this paper, we experimentally demonstrate simultaneous multichannel wavelength multicasting (MWM) and exclusive-OR logic gate multicasting (XOR-LGM) for three 10Gbps non-return-to-zero differential phase-shift-keying (NRZ-DPSK) signals in quantum-dot semiconductor optical amplifier (QD-SOA) by exploiting the four-wave mixing (FWM) process. No additional pump is needed in the scheme. Through the interaction of the input three 10Gbps DPSK signal lights in QD-SOA, each channel is successfully multicasted to three wavelengths (1-to-3 for each), totally 3-to-9 MWM, and at the same time, three-output XOR-LGM is obtained at three different wavelengths. All the new generated channels are with a power penalty less than 1.2dB at a BER of 10(-9). Degenerate and non-degenerate FWM components are fully used in the experiment for data and logic multicasting.

  3. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    International Nuclear Information System (INIS)

    Roy, Sukhdev; Yadav, Chandresh

    2013-01-01

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates

  4. Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

    Science.gov (United States)

    Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

    2013-01-01

    This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

  5. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  6. A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

    International Nuclear Information System (INIS)

    Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

    1991-01-01

    The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

  7. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  8. Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

    Science.gov (United States)

    2014-06-19

    Security Risks for Industrial Control Systems ,” VDE 2004 Congress, Berlin, Germany, October 2004, pp. 1-7. [Cis12] Cisco, NetFlow Configuration Guide...Date 29 May 2014 Date AFIT-ENG-T-14-J-4 Abstract Industrial Control Systems (ICS) remain vulnerable through attack vectors that exist within programmable...5 2.2 Industrial Control Systems

  9. Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

    Science.gov (United States)

    Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

    2015-02-01

    A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer,a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

  10. Multi Channels PWM Controller for Thermoelectric Cooler Using a Programmable Logic Device and Lab-Windows CVI

    Directory of Open Access Journals (Sweden)

    Eli FLAXER

    2008-09-01

    Full Text Available We present a complete design of a multi channels PID controller for Thermoelectric Cooler (TEC using a pulse width modulation (PWM technique implemented by a dedicated programmable logic device (PLD programmed by VHDL. The PID control loop is implemented by software written by National Instrument Lab-Windows CVI. Due to the fact that the implementation is by a VHDL and PLD the design is modular, as a result, the circuit is very compact in size and very low cost as compared to any commercial product. In addition, since the control loop is implemented by software running on a personal computer (PC using a C language, it is easy to adjust the controller to various environmental conditions and for a width range of sensors like: a thermo couple (TC, thermistor, resistance temperature detectors (RTD etc. We demonstrate the performance of this circuit as a controller for a small incubator using thermistor as the temperature sensor.

  11. A Computed River Flow-Based Turbine Controller on a Programmable Logic Controller for Run-Off River Hydroelectric Systems

    Directory of Open Access Journals (Sweden)

    Razali Jidin

    2017-10-01

    Full Text Available The main feature of a run-off river hydroelectric system is a small size intake pond that overspills when river flow is more than turbines’ intake. As river flow fluctuates, a large proportion of the potential energy is wasted due to the spillages which can occur when turbines are operated manually. Manual operation is often adopted due to unreliability of water level-based controllers at many remote and unmanned run-off river hydropower plants. In order to overcome these issues, this paper proposes a novel method by developing a controller that derives turbine output set points from computed mass flow rate of rivers that feed the hydroelectric system. The computed flow is derived by summation of pond volume difference with numerical integration of both turbine discharge flows and spillages. This approach of estimating river flow allows the use of existing sensors rather than requiring the installation of new ones. All computations, including the numerical integration, have been realized as ladder logics on a programmable logic controller. The implemented controller manages the dynamic changes in the flow rate of the river better than the old point-level based controller, with the aid of a newly installed water level sensor. The computed mass flow rate of the river also allows the controller to straightforwardly determine the number of turbines to be in service with considerations of turbine efficiencies and auxiliary power conservation.

  12. Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array; Modelagem de funcoes criticas de reatores nucleares utilizando Fild Programmable Gate Array

    Energy Technology Data Exchange (ETDEWEB)

    Teixeira, Pamela Iara Nolasco

    2016-07-01

    This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

  13. Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

    Science.gov (United States)

    Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

    2016-03-01

    Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

  14. Demonstration and optimisation of an ultrafast all-optical AND logic gate using four-wave mixing in a semiconductor optical amplifier

    International Nuclear Information System (INIS)

    Razaghi, M; Nosratpour, A; Das, N K

    2013-01-01

    We have proposed an all-optical AND logic gate based on four-wave mixing (FWM) in a semiconductor optical amplifier (SOA) integrated with an optical filter. In the scheme proposed, the preferred logical function can be performed without using a continuous-wave (cw) signal. The modified nonlinear Schroedinger equation (MNLSE) is used for the modelling wave propagation in a SOA. The MNLSE takes into account all nonlinear effects relevant to pico- and sub-picosecond pulse durations and is solved by the finite-difference beam-propagation method (FD-BPM). Based on the simulation results, the optimal output signal with a 40-fJ energy can be obtained at a bit rate of 50 Gb s -1 . In the simulations, besides the nonlinearities included in the model, the pattern effect of the signals propagating in the SOA medium and the effect of the input signal bit rate are extensively investigated to optimise the system performance. (optical logic elements)

  15. Field-programmable gate array based controller for multi spot light-addressable potentiometric sensors with integrated signal correction mode

    Energy Technology Data Exchange (ETDEWEB)

    Werner, Carl Frederik; Schusser, Sebastian; Spelthahn, Heiko [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany); Wagner, Torsten; Yoshinobu, Tatsuo [Tohoku University, Department of Electronic Engineering, 6-6-05 Aramaki Aza Aoba, Aoba-ku, Sendai, Miyagi 980-8579 (Japan); Schoening, Michael J., E-mail: schoening@fh-aachen.de [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany)

    2011-11-01

    Highlights: > Flexible up-scalable design of a light-addressable potentiometric sensor set-up. > Utilisation of a field-programmable gate array to address LAPS measurement spots. > Measurements in amplitude-mode and phase-mode for different pH solutions. > Amplitude, phase and frequency behaviour of LAPS for single and multiple light stimulus. > Signal calibration method by brightness control to compensated systematic errors. - Abstract: A light-addressable potentiometric sensor (LAPS) can measure the concentration of one or several analytes at the sensor surface simultaneously in a spatially resolved manner. A modulated light pointer stimulates the semiconductor structure at the area of interest and a responding photocurrent can be read out. By simultaneous stimulation of several areas with light pointers of different modulation frequencies, the read out can be performed at the same time. With the new proposed controller electronic based on a field-programmable gate array (FPGA), it is possible to control the modulation frequencies, phase shifts, and light brightness of multiple light pointers independently and simultaneously. Thus, it is possible to investigate the frequency response of the sensor, and to examine the analyte concentration by the determination of the surface potential with the help of current/voltage curves and phase/voltage curves. Additionally, the ability to individually change the light intensities of each light pointer is used to perform signal correction.

  16. G(sup 4)FET Implementations of Some Logic Circuits

    Science.gov (United States)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  17. Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

    CERN Document Server

    Kwiatkowski, Maciej; Todd, Benjamin

    The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and ...

  18. Methods for the application of programmable logic devices in electronic protection systems for high energy particle accelerators

    CERN Document Server

    Kwiatkowski, M

    2014-01-01

    The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable rmware implementation and to use that method to implement a new rmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis [1]. For that reason the reliable SMP hardware was preserved unchanged. The rst version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP rmware was objectionable. There were new requirements and therefore the SMP speci cation was extended. On that occasion it was decided that the existing SMP rmware will not be continued and that it...

  19. Designing the Expanded Programme on Immunisation (EPI) as a service: Prioritising patients over administrative logic

    DEFF Research Database (Denmark)

    McKnight, J.; Holt, D. B.

    2014-01-01

    -the-ground problems that mothers face in trying to vaccinate their children, while instead prioritising administrative processes. Our ethnographic analysis of 83 mothers who had not vaccinated their children reveals key barriers to vaccination from a 'customer' perspective. While mothers value vaccination......Expanded Programme on Immunisation (EPI) vaccination rates remain well below herd immunity in regions of many countries despite huge international resources devoted to both financing and access. We draw upon service marketing theory, organisational sociology, development anthropology and cultural...... specific service problems from the mother's perspective and points towards simple service innovations that could improve vaccination rates in regions that have poor uptake....

  20. Flexible and re-configurable optical three-input XOR logic gate of phase-modulated signals with multicast functionality for potential application in optical physical-layer network coding.

    Science.gov (United States)

    Lu, Guo-Wei; Qin, Jun; Wang, Hongxiang; Ji, XuYuefeng; Sharif, Gazi Mohammad; Yamaguchi, Shigeru

    2016-02-08

    Optical logic gate, especially exclusive-or (XOR) gate, plays important role in accomplishing photonic computing and various network functionalities in future optical networks. On the other hand, optical multicast is another indispensable functionality to efficiently deliver information in optical networks. In this paper, for the first time, we propose and experimentally demonstrate a flexible optical three-input XOR gate scheme for multiple input phase-modulated signals with a 1-to-2 multicast functionality for each XOR operation using four-wave mixing (FWM) effect in single piece of highly-nonlinear fiber (HNLF). Through FWM in HNLF, all of the possible XOR operations among input signals could be simultaneously realized by sharing a single piece of HNLF. By selecting the obtained XOR components using a followed wavelength selective component, the number of XOR gates and the participant light in XOR operations could be flexibly configured. The re-configurability of the proposed XOR gate and the function integration of the optical logic gate and multicast in single device offer the flexibility in network design and improve the network efficiency. We experimentally demonstrate flexible 3-input XOR gate for four 10-Gbaud binary phase-shift keying signals with a multicast scale of 2. Error-free operations for the obtained XOR results are achieved. Potential application of the integrated XOR and multicast function in network coding is also discussed.

  1. A gold nanocluster-based fluorescent probe for simultaneous pH and temperature sensing and its application to cellular imaging and logic gates

    Science.gov (United States)

    Wu, Yun-Tse; Shanmugam, Chandirasekar; Tseng, Wei-Bin; Hiseh, Ming-Mu; Tseng, Wei-Lung

    2016-05-01

    Metal nanocluster-based nanomaterials for the simultaneous determination of temperature and pH variations in micro-environments are still a challenge. In this study, we develop a dual-emission fluorescent probe consisting of bovine serum albumin-stabilized gold nanoclusters (BSA-AuNCs) and fluorescein-5-isothiocyanate (FITC) as temperature- and pH-responsive fluorescence signals. Under single wavelength excitation the FITC/BSA-AuNCs exhibited well-separated dual emission bands at 525 and 670 nm. When FITC was used as a reference fluorophore, FITC/BSA-AuNCs showed a good linear response over the temperature range 1-71 °C and offered temperature-independent spectral shifts, temperature accuracy, activation energy, and reusability. The possible mechanism for high temperature-induced fluorescence quenching of FITC/BSA-AuNCs could be attributed to a weakening of the Au-S bond, thereby lowering the charge transfer from BSA to AuNCs. Additionally, the pH- and temperature-responsive properties of FITC/BSA-AuNCs allow simultaneous temperature sensing from 21 to 41 °C (at intervals of 5 °C) and pH from 6.0 to 8.0 (at intervals of 0.5 pH unit), facilitating the construction of two-input AND logic gates. Three-input AND logic gates were also designed using temperature, pH, and trypsin as inputs. The practicality of using FITC/BSA-AuNCs to determine the temperature and pH changes in HeLa cells is also validated.Metal nanocluster-based nanomaterials for the simultaneous determination of temperature and pH variations in micro-environments are still a challenge. In this study, we develop a dual-emission fluorescent probe consisting of bovine serum albumin-stabilized gold nanoclusters (BSA-AuNCs) and fluorescein-5-isothiocyanate (FITC) as temperature- and pH-responsive fluorescence signals. Under single wavelength excitation the FITC/BSA-AuNCs exhibited well-separated dual emission bands at 525 and 670 nm. When FITC was used as a reference fluorophore, FITC/BSA-AuNCs showed a

  2. A gold nanocluster-based fluorescent probe for simultaneous pH and temperature sensing and its application to cellular imaging and logic gates.

    Science.gov (United States)

    Wu, Yun-Tse; Shanmugam, Chandirasekar; Tseng, Wei-Bin; Hiseh, Ming-Mu; Tseng, Wei-Lung

    2016-06-07

    Metal nanocluster-based nanomaterials for the simultaneous determination of temperature and pH variations in micro-environments are still a challenge. In this study, we develop a dual-emission fluorescent probe consisting of bovine serum albumin-stabilized gold nanoclusters (BSA-AuNCs) and fluorescein-5-isothiocyanate (FITC) as temperature- and pH-responsive fluorescence signals. Under single wavelength excitation the FITC/BSA-AuNCs exhibited well-separated dual emission bands at 525 and 670 nm. When FITC was used as a reference fluorophore, FITC/BSA-AuNCs showed a good linear response over the temperature range 1-71 °C and offered temperature-independent spectral shifts, temperature accuracy, activation energy, and reusability. The possible mechanism for high temperature-induced fluorescence quenching of FITC/BSA-AuNCs could be attributed to a weakening of the Au-S bond, thereby lowering the charge transfer from BSA to AuNCs. Additionally, the pH- and temperature-responsive properties of FITC/BSA-AuNCs allow simultaneous temperature sensing from 21 to 41 °C (at intervals of 5 °C) and pH from 6.0 to 8.0 (at intervals of 0.5 pH unit), facilitating the construction of two-input AND logic gates. Three-input AND logic gates were also designed using temperature, pH, and trypsin as inputs. The practicality of using FITC/BSA-AuNCs to determine the temperature and pH changes in HeLa cells is also validated.

  3. A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

    Energy Technology Data Exchange (ETDEWEB)

    O' Gorman, T.; Gibson, K. J.; Snape, J. A. [York Plasma Institute, Department of Physics, University of York, York YO10 5DD (United Kingdom); Naylor, G.; Huang, B.; McArdle, G. J.; Scannell, R.; Shibaev, S.; Thomas-Davies, N. [EURATOM/CCFE Fusion Association, Culham Science Centre, Oxfordshire OX14 3DB (United Kingdom)

    2012-10-15

    A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate trigger from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.

  4. Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

    Science.gov (United States)

    Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

    2010-12-01

    An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

  5. [Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

    Science.gov (United States)

    Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

    2015-12-01

    Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

  6. Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

    Energy Technology Data Exchange (ETDEWEB)

    Learn, Mark Walter

    2012-01-01

    The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

  7. A new data acquisition and imaging system for nuclear microscopy based on a Field Programmable Gate Array card

    International Nuclear Information System (INIS)

    Bettiol, A.A.; Udalagama, C.; Watt, F.

    2009-01-01

    The introduction of the new Field Programmable Gate Array (FPGA) cards by National Instruments has made it possible for the first time to develop reconfigurable custom data acquisition hardware easily with the LabVIEW programming environment. Data acquisition issues such as precise timing for scanning and operating system latencies can now be easily overcome using this new technology because the data acquisition software is embedded in the FPGA chip on the card. In this paper we present the first results of the new data acquisition system developed at the Centre for Ion Beam Applications (CIBA), National University of Singapore using the new National Instruments cards in conjunction with rack mountable Wilkinson type ADCs.

  8. The cost of respiration-gated radiotherapy in the framework of a clinical research programme -STIC-

    International Nuclear Information System (INIS)

    Remonnay, R.; Morelle, M.; Carrere, M.O.; Giraud, P.

    2009-01-01

    Purpose. Our study aims to evaluate the impact of the implementation of respiratory gating (R.G.) on the production cost of radiotherapy, as compared to conformational radiotherapy without R.G. (comparator) in patients with lung or breast cancers. Issues surrounding reimbursement were also explored. Materials and methods: A prospective, multicenter, non-randomized study was conducted in the framework of a project entitled 'Support Program for Costly Diagnostic and Therapeutic Innovations'. Of the 20 hospitals involved in the clinical study, eight reference centers participated to the medico-economic study evaluating the costs of staff and equipment, as well as the costs of maintenance and consumables. Results: Three hundred and sixty-five patients were enrolled over two years in the economic study, corresponding to 197 radiotherapy treatments without R.G. and 168 with R.G.. Patients treated during the learning phase (n = 27) were excluded from the comparison with the control group. The use of R.G. in routine practice induced a cost increase of respectively 1256 and 996 Euros per treatment for lung and breast cancer patients treated with breath-hold techniques, versus 1807 and 1510 Euros for lung and breast cancer patients treated with synchronized gating techniques. Over costs were mainly due to extra working time of medical staff and medical technicians and to extra use of equipment during treatment sessions. Conclusion: The results of the full cost estimation suggested that medical reimbursements largely underestimate the costs related to innovation. (authors)

  9. Orientation of a 3D object: implementation with an artificial neural network using a programmable logic device

    International Nuclear Information System (INIS)

    Carnevale, Federico J.

    2010-01-01

    Complex information extraction from images is a key skill of intelligent machines, with wide application in automated systems, robotic manipulation and human-computer interaction. However, solving this problem with traditional, geometric or analytical, strategies is extremely difficult. Therefore, an approach based on learning from examples seems to be more appropriate. This thesis addresses the problem of 3D orientation, aiming to estimate the angular coordinates of a known object from an image shot from any direction. We describe a system based on artificial neural networks to solve this problem in real time. The implementation is performed using a programmable logic device. The digital system described in this paper has the ability to estimate two rotational coordinates of a 3D known object, in ranges from -80 0 to 80 0 . The operation speed allows a real time performance at video rate. The system accuracy can be successively increased by increasing the size of the artificial neural network and using a larger number of training examples [es

  10. Upgrading of Alum Preparation and Dosing Unit for Sharq Dijla Water Treatment Plant by Using Programmable Logic Controller System

    Directory of Open Access Journals (Sweden)

    Aumar Al-Nakeeb

    2018-02-01

    Full Text Available One of the important units in Sharq Dijla Water Treatment Plant (WTP first and second extensions are the alum solution preparation and dosing unit. The existing operation of this unit accomplished manually starting from unloading the powder alum in the preparation basin and ending by controlling the alum dosage addition through the dosing pumps to the flash mix chambers. Because of the modern trend of monitoring and control the automatic operation of WTPs due to the great benefits that could be gain from optimum equipment operation, reducing the operating costs and human errors. This study deals with how to transform the conventional operation to an automatic monitoring and controlling system depending on a Programmable Logic Controller (PLC and online sensors for alum preparation and dosing unit in Sharq Dijla WTP. PLC system will receive, analyze transmitting data, compare them with preset points then automatically orders the operational equipment (such as pumps, valves, and mixers in a way that guarantees the safe and appropriate operation of the unit. As a result of Process and Instrumentation Diagrams (PID that were prepared in this study, these units can be fully operating and manage by using Supervisory Control and Data Acquisition (SCADA system.

  11. Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

    Science.gov (United States)

    Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

    2016-05-01

    Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

  12. Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

    International Nuclear Information System (INIS)

    Hennig, Christine; Kneupner, Klaus; Kinna, David

    2012-01-01

    Highlights: ► We describe 2 ways connecting PLCs to fusion control and data acquisition software. ► At W7-X standardization of the PLC type eases the maintenance of the software. ► At JET PLCs are interfaced with a daemon that hides the PLC specific part. ► There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse “black box protocol” approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and observed via timeout mechanisms. The use of PLCs for Wendelstein 7-X is standardized. Therefore a single

  13. Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

    Energy Technology Data Exchange (ETDEWEB)

    Hennig, Christine, E-mail: Christine.Hennig@ipp.mpg.de [Max-Planck-Institut fuer Plasmaphysik, Wendelsteinstrasse 1, 17491 Greifswald (Germany); Kneupner, Klaus; Kinna, David [JET-EFDA, Culham Science Centre, OX14 3DB Abingdon (United Kingdom)

    2012-12-15

    Highlights: Black-Right-Pointing-Pointer We describe 2 ways connecting PLCs to fusion control and data acquisition software. Black-Right-Pointing-Pointer At W7-X standardization of the PLC type eases the maintenance of the software. Black-Right-Pointing-Pointer At JET PLCs are interfaced with a daemon that hides the PLC specific part. Black-Right-Pointing-Pointer There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse 'black box protocol' approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and

  14. Life Cycle V and V Process for Hardware Description Language Programs of Programmable Logic Device-based Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Cha, K. H.; Lee, D. Y.

    2010-01-01

    Programmable Logic Device (PLD), especially Complex PLD (CPLD) or Field Programmable Logic Array (FPGA), has been growing in interest in nuclear Instrumentation and Control (I and C) applications. PLD has been applied to replace an obsolete analog device or old-fashioned microprocessor, or to develop digital controller, subsystem or overall system on hardware aspects. This is the main reason why the PLD-based I and C design provides higher flexibility than the analog-based one, and the PLD-based I and C systems shows better real-time performance than the processor-based I and C systems. Due to the development of the PLD-based I and C systems, their nuclear qualification has been issued in the nuclear industry. Verification and Validation (V and V) is one of necessary qualification activities when a Hardware Description Language (HDL) is used to implement functions of the PLD-based I and C systems. The life cycle V and V process, described in this paper, has been defined as satisfying the nuclear V and V requirements, and it has been applied to verify Correctness, Completeness, and Consistency (3C) among design outputs in a safety-grade programmable logic controller and a safety-critical data communication system. Especially, software engineering techniques such as the Fagan Inspection, formal verification, simulated verification and automated testing have been defined for the life cycle V and V tasks of behavioral, structural, and physical design in VHDL

  15. Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

    Science.gov (United States)

    Ayyoub, Slimani; Achour, Benslama

    2017-08-01

    Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

  16. Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array

    International Nuclear Information System (INIS)

    Teixeira, Pamela Iara Nolasco

    2016-01-01

    This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

  17. Design and experimentation of BSFQ logic devices

    International Nuclear Information System (INIS)

    Hosoki, T.; Kodaka, H.; Kitagawa, M.; Okabe, Y.

    1999-01-01

    Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic 'Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported. (author)

  18. Line defects on As2Se3-Chalcogenide photonic crystals for the design of all-optical power splitters and digital logic gates

    Science.gov (United States)

    Saghaei, Hamed; Zahedi, Abdulhamid; Karimzadeh, Rouhollah; Parandin, Fariborz

    2017-10-01

    In this paper, a triangular two-dimensional photonic crystal (PhC) of As2Se3-chalcogenide rods in air is presented and its photonic band diagram is calculated by plane wave method. In this structure, an optical waveguide is obtained by creating a line defect (eliminating rods) in diagonal direction of PhC. Numerical simulations based on finite difference time domain method show that when self-collimated beams undergo total internal reflection at the PhC-air interface, a total reflection of 90° occurs for the output beams. We also demonstrate that by decreasing the radius of As2Se3-chalcogenide instead of eliminating a diagonal line, a two-channel optical splitter will be designed. In this case, incoming self-collimated beams can be divided into the reflected and transmitted beams with arbitrary power ratio by adjusting the value of their radii. Based on these results, we propose a four-channel optical splitter using four line defects. The power ratio among output channels can be controlled systematically by varying the radius of rods in the line defects. We also demonstrate that by launching two optical sources with the same intensity and 90° phase difference from both perpendicular faces of the PhC, two logic OR and XOR gates will be achieved at the output channels. These optical devices have some applications in photonic integrated circuits for controlling and steering (managing) the light as desired.

  19. Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

    Science.gov (United States)

    Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

    2013-07-01

    We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

  20. A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

    International Nuclear Information System (INIS)

    Chen, Yuan-Ho

    2017-01-01

    In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

  1. Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

    International Nuclear Information System (INIS)

    Azarbayejani, M; Jalalpour, M; Reda Taha, M M; El-Osery, A I

    2011-01-01

    In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide

  2. Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

    Science.gov (United States)

    Azarbayejani, M.; Jalalpour, M.; El-Osery, A. I.; Reda Taha, M. M.

    2011-08-01

    In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide.

  3. Case for a field-programmable gate array multicore hybrid machine for an image-processing application

    Science.gov (United States)

    Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

    2011-01-01

    General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

  4. A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Yuan-Ho, E-mail: chenyh@mail.cgu.edu.tw [Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Department of Radiation Oncology, Chang Gung Memorial Hospital, Tao-Yuan 333, Taiwan (China); Center for Reliability Sciences and Technologies, Chang Gung University, Tao-Yuan 333, Taiwan (China)

    2017-05-11

    In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

  5. Fringe pattern demodulation using the one-dimensional continuous wavelet transform: field-programmable gate array implementation.

    Science.gov (United States)

    Abid, Abdulbasit

    2013-03-01

    This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

  6. Theory and implementation of a very high throughput true random number generator in field programmable gate array

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong; Xu, Chao [Department of Modern Physics, University of Science and Technology of China, Hefei 230026 (China)

    2016-04-15

    The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

  7. Field programmable gate array based hardware implementation of a gradient filter for edge detection in colour images with subpixel precision

    International Nuclear Information System (INIS)

    Schellhorn, M; Rosenberger, M; Correns, M; Blau, M; Goepfert, A; Rueckwardt, M; Linss, G

    2010-01-01

    Within the field of industrial image processing the use of colour cameras becomes ever more common. Increasingly the established black and white cameras are replaced by economical single-chip colour cameras with Bayer pattern. The use of the additional colour information is particularly important for recognition or inspection. Become interesting however also for the geometric metrology, if measuring tasks can be solved more robust or more exactly. However only few suitable algorithms are available, in order to detect edges with the necessary precision. All attempts require however additional computation expenditure. On the basis of a new filter for edge detection in colour images with subpixel precision, the implementation on a pre-processing hardware platform is presented. Hardware implemented filters offer the advantage that they can be used easily with existing measuring software, since after the filtering a single channel image is present, which unites the information of all colour channels. Advanced field programmable gate arrays represent an ideal platform for the parallel processing of multiple channels. The effective implementation presupposes however a high programming expenditure. On the example of the colour filter implementation, arising problems are analyzed and the chosen solution method is presented.

  8. Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

    Science.gov (United States)

    Kyrkou, Christos; Theocharides, Theocharis

    2016-07-01

    Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

  9. Reliability concerns with logical constants in Xilinx FPGA designs

    Energy Technology Data Exchange (ETDEWEB)

    Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX

    2009-01-01

    In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

  10. Reversible arithmetic logic unit for quantum arithmetic

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal; Glück, Robert; Axelsen, Holger Bock

    2010-01-01

    This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic...... and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n......-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible...

  11. Fuzzy Logic Controller Design for Intelligent Robots

    Directory of Open Access Journals (Sweden)

    Ching-Han Chen

    2017-01-01

    Full Text Available This paper presents a fuzzy logic controller by which a robot can imitate biological behaviors such as avoiding obstacles or following walls. The proposed structure is implemented by integrating multiple ultrasonic sensors into a robot to collect data from a real-world environment. The decisions that govern the robot’s behavior and autopilot navigation are driven by a field programmable gate array- (FPGA- based fuzzy logic controller. The validity of the proposed controller was demonstrated by simulating three real-world scenarios to test the bionic behavior of a custom-built robot. The results revealed satisfactorily intelligent performance of the proposed fuzzy logic controller. The controller enabled the robot to demonstrate intelligent behaviors in complex environments. Furthermore, the robot’s bionic functions satisfied its design objectives.

  12. Miniaturization of Josephson logic circuits

    International Nuclear Information System (INIS)

    Ko, H.; Van Duzer, T.

    1985-01-01

    The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

  13. Logical operations using phenyl ring

    Science.gov (United States)

    Patra, Moumita; Maiti, Santanu K.

    2018-02-01

    Exploiting the effects of quantum interference we put forward an idea of designing three primary logic gates, OR, AND and NOT, using a benzene molecule. Under a specific molecule-lead interface geometry, anti-resonant states appear which play the crucial role for AND and NOT operations, while for OR gate no such states are required. Our analysis leads to a possibility of designing logic gates using simple molecular structure which might be significant in the area of molecular electronics.

  14. Multiple-stimuli responsive bioelectrocatalysis based on reduced graphene oxide/poly(N-isopropylacrylamide) composite films and its application in the fabrication of logic gates.

    Science.gov (United States)

    Wang, Lei; Lian, Wenjing; Yao, Huiqin; Liu, Hongyun

    2015-03-11

    In the present work, reduced graphene oxide (rGO)/poly(N-isopropylacrylamide) (PNIPAA) composite films were electrodeposited onto the surface of Au electrodes in a fast and one-step manner from an aqueous mixture of a graphene oxide (GO) dispersion and N-isopropylacrylamide (NIPAA) monomer solutions. Reflection-absorption infrared (IR) and Raman spectroscopies were employed to characterize the successful construction of the rGO/PNIPAA composite films. The rGO/PNIPAA composite films exhibited reversible potential-, pH-, temperature-, and sulfate-sensitive cyclic voltammetric (CV) on-off behavior to the electroactive probe ferrocenedicarboxylic acid (Fc(COOH)2). For instance, after the composite films were treated at -0.7 V for 7 min, the CV responses of Fc(COOH)2 at the rGO/PNIPAA electrodes were quite large at pH 8.0, exhibiting the on state. However, after the films were treated at 0 V for 30 min, the CV peak currents became much smaller, demonstrating the off state. The mechanism of the multiple-stimuli switchable behaviors for the system was investigated not only by electrochemical methods but also by scanning electron microscopy and X-ray photoelectron spectroscopy. The potential-responsive behavior for this system was mainly attributed to the transformation between rGO and GO in the films at different potentials. The film system was further used to realize multiple-stimuli responsive bioelectrocatalysis of glucose catalyzed by the enzyme of glucose oxidase and mediated by the electroactive probe of Fc(COOH)2 in solution. On the basis of this, a four-input enabled OR (EnOR) logic gate network was established.

  15. Programme

    OpenAIRE

    Hobday, E, fl. 1905, artist

    2003-01-01

    A photograph of an illustrated programme listing dances. The illustration shows a snake charmer playing to a snake while another man watches. Buildings and trees can be seen behind a wall in the distance. In the lower right-hand corner of the programme is the signature 'E. Hobday'. The programme is almost certainly related to the Punjab Ball, Lahore. It is placed next to the Punjab Ball Menu in the album and the Menu is also illustrated by 'E. Hobday'.

  16. Project W-058 monitor and control system logic

    International Nuclear Information System (INIS)

    ROBERTS, J.B.

    1999-01-01

    This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console

  17. Field programmable gate array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

    DEFF Research Database (Denmark)

    Thrane, Lars; Larsen, Henning Engelbrecht; Norozi, Kambiz

    2009-01-01

    efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation......We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows...

  18. Quantum gate decomposition algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  19. Development of field programmable gate array–based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

    Directory of Open Access Journals (Sweden)

    Mohamed Abdallah Elakrat

    2018-06-01

    Full Text Available This article presents a security module based on a field programmable gate array (FPGA to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA. Keywords: AES-128, Cyber Security, Encryption, Field Programmable Gate Array, I&C

  20. An inpatient lifestyle-change programme improves heart rate recovery in overweight and obese children and adolescents (LOGIC Trial).

    Science.gov (United States)

    Wilks, Désirée C; Rank, Melanie; Christle, Jeff; Langhof, Helmut; Siegrist, Monika; Halle, Martin

    2014-07-01

    Impaired heart rate recovery (HRR) is a strong predictor of overall mortality and cardio-metabolic risk. This study aimed at investigating (1) the effect of participation in a lifestyle-change programme for weight loss on HRR in overweight and obese children and (2) potential associations between the changes in one minute HRR (HRR1) and fitness, weight loss and cardio-metabolic risk. The analysis included 429 individuals (169 boys) aged 13.9 ± 2.3 years who participated in an inpatient weight loss programme for four to six weeks. At baseline and the end of the programme clinical investigations were performed, including blood analyses, blood pressure, anthropometry and maximal cycle ergometer exercise testing with continuous heart rate (HR) monitoring. HRR was calculated as the difference between the highest exercising HR and HR at one, three and five minutes post-exercise. Average body weight decreased from 90.7 ± 22.5 kg to 81.9 ± 20.0 kg and peak exercise capacity increased from 1.66 ± 0.38 W/kg to 2.05 ± 0.45 W/kg (p exercise capacity (p inpatient weight loss programme in overweight and obese children. This was not associated with improvements in body weight and cardio-metabolic risk; hence HRR would be a valuable addition to cardiovascular risk assessment in this group. © The European Society of Cardiology 2012.

  1. Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

    Science.gov (United States)

    Devaraju, Naga Sai Gopi K; Unger, Marc A

    2012-11-21

    Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

  2. A multiplicity logic unit

    International Nuclear Information System (INIS)

    Bialkowski, J.; Moszynski, M.; Zagorski, A.

    1981-01-01

    The logic diagram principle of operation and some details of the design of the multiplicity logic unit are presented. This unit was specially designed to fulfil the requirements of a multidetector arrangement for gamma-ray multiplicity measurements. The unit is equipped with 16 inputs controlled by a common coincidence gate. It delivers a linear output pulse with the height proportional to the multiplicity of coincidences and logic pulses corresponding to 0, 1, ... up to >= 5-fold coincidences. These last outputs are used to steer the routing unit working with the multichannel analyser. (orig.)

  3. Data Logic

    DEFF Research Database (Denmark)

    Nilsson, Jørgen Fischer

    A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...

  4. A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

    Science.gov (United States)

    Szplet, R.; Kalisz, J.; Jachna, Z.

    2009-02-01

    We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

  5. A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

    International Nuclear Information System (INIS)

    Szplet, R; Kalisz, J; Jachna, Z

    2009-01-01

    We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second

  6. A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

    Directory of Open Access Journals (Sweden)

    Ion Stiharu

    2010-08-01

    Full Text Available Computer numerically controlled (CNC machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA-based sensor node.

  7. A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

    Science.gov (United States)

    Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

    2010-01-01

    Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

  8. Logical operations realized on the Ising chain of N qubits

    International Nuclear Information System (INIS)

    Asano, Masanari; Tateda, Norihiro; Ishii, Chikara

    2004-01-01

    Multiqubit logical gates are proposed as implementations of logical operations on N qubits realized physically by the local manipulation of qubits before and after the one-time evolution of an Ising chain. This construction avoids complicated tuning of the interactions between qubits. The general rules of the action of multiqubit logical gates are derived by decomposing the process into the product of two-qubit logical operations. The formalism is demonstrated by the construction of a special type of multiqubit logical gate that is simulated by a quantum circuit composed of controlled-NOT gates

  9. Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

    Directory of Open Access Journals (Sweden)

    Salah Bouzina

    2016-12-01

    Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

  10. A chemosensor showing discriminating fluorescent response for highly selective and nanomolar detection of Cu²⁺ and Zn²⁺ and its application in molecular logic gate.

    Science.gov (United States)

    Fegade, Umesh A; Sahoo, Suban K; Singh, Amanpreet; Singh, Narinder; Attarde, Sanjay B; Kuwar, Anil S

    2015-05-04

    A fluorescent based receptor (4Z)-4-(4-diethylamino)-2-hydroxybenzylidene amino)-1,2dihydro-1,5-dimethyl-2-phenylpyrazol-3-one (receptor 3) was developed for the highly selective and sensitive detection of Cu(2+) and Zn(2+) in semi-aqueous system. The fluorescence of receptor 3 was enhanced and quenched, respectively, with the addition of Zn(2+) and Cu(2+) ions over other surveyed cations. The receptor formed host-guest complexes in 1:1 stoichiometry with the detection limit of 5 nM and 15 nM for Cu(2+) and Zn(2+) ions, respectively. Further, we have effectively utilized the two metal ions (Cu(2+) and Zn(2+)) as chemical inputs for the manufacture of INHIBIT type logic gate at molecular level using the fluorescence responses of receptor 3 at 450 nm. Copyright © 2015 Elsevier B.V. All rights reserved.

  11. A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

    Science.gov (United States)

    Bayindir, Ramazan; Cetinceviz, Yucel

    2011-04-01

    This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. Copyright © 2010 ISA. Published by Elsevier Ltd. All rights reserved.

  12. Spin-polarization and spin-dependent logic gates in a double quantum ring based on Rashba spin-orbit effect: Non-equilibrium Green's function approach

    International Nuclear Information System (INIS)

    Eslami, Leila; Esmaeilzadeh, Mahdi

    2014-01-01

    Spin-dependent electron transport in an open double quantum ring, when each ring is made up of four quantum dots and threaded by a magnetic flux, is studied. Two independent and tunable gate voltages are applied to induce Rashba spin-orbit effect in the quantum rings. Using non-equilibrium Green's function formalism, we study the effects of electron-electron interaction on spin-dependent electron transport and show that although the electron-electron interaction induces an energy gap, it has no considerable effect when the bias voltage is sufficiently high. We also show that the double quantum ring can operate as a spin-filter for both spin up and spin down electrons. The spin-polarization of transmitted electrons can be tuned from −1 (pure spin-down current) to +1 (pure spin-up current) by changing the magnetic flux and/or the gates voltage. Also, the double quantum ring can act as AND and NOR gates when the system parameters such as Rashba coefficient are properly adjusted

  13. Protected gates for topological quantum field theories

    International Nuclear Information System (INIS)

    Beverland, Michael E.; Pastawski, Fernando; Preskill, John; Buerschaper, Oliver; Koenig, Robert; Sijher, Sumit

    2016-01-01

    We study restrictions on locality-preserving unitary logical gates for topological quantum codes in two spatial dimensions. A locality-preserving operation is one which maps local operators to local operators — for example, a constant-depth quantum circuit of geometrically local gates, or evolution for a constant time governed by a geometrically local bounded-strength Hamiltonian. Locality-preserving logical gates of topological codes are intrinsically fault tolerant because spatially localized errors remain localized, and hence sufficiently dilute errors remain correctable. By invoking general properties of two-dimensional topological field theories, we find that the locality-preserving logical gates are severely limited for codes which admit non-abelian anyons, in particular, there are no locality-preserving logical gates on the torus or the sphere with M punctures if the braiding of anyons is computationally universal. Furthermore, for Ising anyons on the M-punctured sphere, locality-preserving gates must be elements of the logical Pauli group. We derive these results by relating logical gates of a topological code to automorphisms of the Verlinde algebra of the corresponding anyon model, and by requiring the logical gates to be compatible with basis changes in the logical Hilbert space arising from local F-moves and the mapping class group

  14. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  15. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  16. Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

    Science.gov (United States)

    Le, Martin; Zheng, Xin; Katanyoutant, Sunant

    2008-01-01

    Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state

  17. MEMS Logic Using Mixed-Frequency Excitation

    KAUST Repository

    Ilyas, Saad

    2017-06-22

    We present multi-function microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, OR, universal logic gates NAND, NOR, and a tristate logic gate using mixed-frequency excitation. The concept is based on exciting combination resonances due to the mixing of two or more input signals. The device vibrates at two steady states: a high state when the combination resonance is activated and a low state when no resonance is activated. These vibration states are assigned to logical value 1 or 0 to realize the logic gates. Using ac signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. We found that the energy consumption per cycle of the proposed logic resonator is higher than those of existing technologies. Hence, integration of such logic devices to build complex computational system needs to take into consideration lowering the total energy consumption. [2017-0041

  18. Multiple Independent Gate FETs: How Many Gates Do We Need?

    OpenAIRE

    Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

    2015-01-01

    Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

  19. Designing for Reuse of Configurable Logic

    National Research Council Canada - National Science Library

    Elm, Joseph P

    2005-01-01

    Field-programmable gate arrays (FPGAs) offer electronic systems designers the opportunity to reduce development cost, reduce time-to-market, increase system performance, and improve system adaptability...

  20. Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm

    Science.gov (United States)

    Nguyen, An Hung; Guillemette, Thomas; Lambert, Andrew J.; Pickering, Mark R.; Garratt, Matthew A.

    2017-09-01

    Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well-known Lucas-Kanade (LK) and Horn-Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi-pass image interpolation algorithm (MP-I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel-warping algorithm (KWA), a modified version of the MP-I2A, which requires fewer iterations to successfully register two images and less memory space for the field-programmable gate array (FPGA) implementation than the MP-I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two-FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.

  1. Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

    International Nuclear Information System (INIS)

    Palazzo, S.; Vagliasindi, G.; Arena, P.; Murari, A.; Mazon, D.; De Maack, A.

    2010-01-01

    In the past years cameras have become increasingly common tools in scientific applications. They are now quite systematically used in magnetic confinement fusion, to the point that infrared imaging is starting to be used systematically for real-time machine protection in major devices. However, in order to guarantee that the control system can always react rapidly in case of critical situations, the time required for the processing of the images must be as predictable as possible. The approach described in this paper combines the new computational paradigm of cellular nonlinear networks (CNNs) with field-programmable gate arrays and has been tested in an application for the detection of hot spots on the plasma facing components in JET. The developed system is able to perform real-time hot spot recognition, by processing the image stream captured by JET wide angle infrared camera, with the guarantee that computational time is constant and deterministic. The statistical results obtained from a quite extensive set of examples show that this solution approximates very well an ad hoc serial software algorithm, with no false or missed alarms and an almost perfect overlapping of alarm intervals. The computational time can be reduced to a millisecond time scale for 8 bit 496x560-sized images. Moreover, in our implementation, the computational time, besides being deterministic, is practically independent of the number of iterations performed by the CNN - unlike software CNN implementations.

  2. Embedding Logics into Product Logic

    Czech Academy of Sciences Publication Activity Database

    Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David

    1998-01-01

    Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics

  3. A parity checker circuit based on microelectromechanical resonator logic elements

    Energy Technology Data Exchange (ETDEWEB)

    Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)

    2017-03-03

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.

  4. An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

    Science.gov (United States)

    Foster, D. L.

    2012-01-01

    For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

  5. Greek, Indian and Arabic logic

    CERN Document Server

    Gabbay, Dov M

    2004-01-01

    Greek, Indian and Arabic Logic marks the initial appearance of the multi-volume Handbook of the History of Logic. Additional volumes will be published when ready, rather than in strict chronological order. Soon to appear are The Rise of Modern Logic: From Leibniz to Frege. Also in preparation are Logic From Russell to Gödel, Logic and the Modalities in the Twentieth Century, and The Many-Valued and Non-Monotonic Turn in Logic. Further volumes will follow, including Mediaeval and Renaissance Logic and Logic: A History of its Central. In designing the Handbook of the History of Logic, the Editors have taken the view that the history of logic holds more than an antiquarian interest, and that a knowledge of logic's rich and sophisticated development is, in various respects, relevant to the research programmes of the present day. Ancient logic is no exception. The present volume attests to the distant origins of some of modern logic's most important features, such as can be found in the claim by the authors of t...

  6. Development of RPS trip logic based on PLD technology

    International Nuclear Information System (INIS)

    Choi, Jong Gyun; Lee, Dong Young

    2012-01-01

    The majority of instrumentation and control (I and C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I and C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I and C systems. Therefore, existing NPPs are replacing the obsolete analog I and C systems with advanced digital systems. New NPPs are also adopting digital I and C systems because the economic efficiencies and usability of the systems are higher than the analog I and C systems. Digital I and C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

  7. Quantum computer with mixed states and four-valued logic

    International Nuclear Information System (INIS)

    Tarasov, Vasily E.

    2002-01-01

    In this paper we discuss a model of quantum computer in which a state is an operator of density matrix and gates are general quantum operations, not necessarily unitary. A mixed state (operator of density matrix) of n two-level quantum systems is considered as an element of 4 n -dimensional operator Hilbert space (Liouville space). It allows us to use a quantum computer model with four-valued logic. The gates of this model are general superoperators which act on n-ququat state. Ququat is a quantum state in a four-dimensional (operator) Hilbert space. Unitary two-valued logic gates and quantum operations for an n-qubit open system are considered as four-valued logic gates acting on n-ququats. We discuss properties of quantum four-valued logic gates. In the paper we study universality for quantum four-valued logic gates. (author)

  8. Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

    Directory of Open Access Journals (Sweden)

    E.A. Ramadan

    2014-09-01

    Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

  9. Logicism, intuitionism, and formalism

    CERN Document Server

    Symons, John

    2008-01-01

    Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.

  10. Logical labyrinths

    CERN Document Server

    Smullyan, Raymond

    2008-01-01

    This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T

  11. Mechano-optic logic gate controlled by third-order nonlinear optical properties in a rotating ZnO:Au thin film

    International Nuclear Information System (INIS)

    Carrillo-Delgado, C; Torres-Torres, C; García-Merino, J A; García-Gil, C I; Khomenko, A V; Trejo-Valdez, M; Martínez-Gutiérrez, H; Torres-Martínez, R

    2016-01-01

    Measurements of the third-order nonlinear optical properties exhibited by a ZnO thin solid film deposited on a SnO 2 substrate are presented. The samples were prepared by a spray pyrolysis processing route. Scanning electron microscopy analysis and UV–Vis spectroscopy studies were carried out. The picosecond response at 1064 nm was explored by the z-scan technique. A large optical Kerr effect with two-photon absorption was obtained. The inhibition of the nonlinear optical absorption together with a noticeable enhancement in the optical Kerr effect in the sample was achieved by the incorporation of Au nanoparticles into the ZnO film. Additionally, a two-wave mixing configuration at 532 nm was performed and an optical Kerr effect was identified as the main cause of the nanosecond third-order optical nonlinearity. The relaxation time of the photothermal response of the sample was estimated to be about 1 s when the sample was excited by nanosecond single-shots. The rotation of the sample during the nanosecond two-wave mixing experiments was analyzed. It was stated that a non-monotonic relation between rotating frequency and pulse repetition rate governs the thermal contribution to the nonlinear refractive index exhibited by a rotating film. Potential applications for switching photothermal interactions in rotating samples can be contemplated. A rotary logic system dependent on Kerr transmittance in a two-wave mixing experiment was proposed. (paper)

  12. General purpose programmable accelerator board

    Science.gov (United States)

    Robertson, Perry J.; Witzke, Edward L.

    2001-01-01

    A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

  13. Development of a diffuse element matrix in 'planar' technology. A particular application: logical gate with coupled emitter; Etude et realisation d'une matrice d'elements diffuses selon la technologie 'planar'. Application particuliere: porte logique a emetteurs couples

    Energy Technology Data Exchange (ETDEWEB)

    Rousseau, P [Commissariat a l' Energie Atomique, 38 - Grenoble (France). Centre d' Etudes Nucleaires

    1967-06-01

    In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [French] Dans uns premiere partie, apres un bref rappel de la technologie 'planar' nous etudions les divers elements parasites associes a tout composant d'un circuit integre. Un developpement sommaire des expressions mathematiques de ces elements est propose. Dans une seconde partie nous presentons la matrice de 22 transistors et 12 resistances que nous avons realisee. Cette matrice repond aux principaux besoins de l'electronique nucleaire. Nous proposons ensuite quelques exemples de circuits realises a partir de cette matrice dont notamment une porte logique a emetteurs couples de performances tres interessantes. (auteur)

  14. Design of selective 8-methylquinolinol based ratiometric Fe{sup 2+} and Fe{sup 3+}/H{sub 2}PO{sub 4}{sup −} fluorescent chemosensor mimicking NOR and IMPLICATION logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Singh, Gurjaspreet, E-mail: gjpsingh@pu.ac.in; Singh, Jandeep; Singh, Jasbhinder; Mangat, Satinderpal Singh

    2015-09-15

    This report describes an on–off module of a fluorescent probe for selectively sensing of Fe(II) and Fe(III) ions by a single chemosensor with unique output optical response and is being reported for the first time. The probe 8-methylquinolinyl-1,2,3-triazolyl silatrane (QTS) was efficiently developed using click silylation route, followed by transetherification of silane. Moreover, the color change in probe QTS by response of this colorimetric sensor can be visualized by naked eye. The anti-quenching response for quenched QTS–Fe{sup 3+} fluorescence spectra by addition of H{sub 2}PO{sub 4}{sup −} ions in the MeOH/H{sub 2}O solvent system results into reversion of fluorescence maximum. These fluctuations in spectral response, under electronic behavior, can be viewed to mimic as NOR and IMPLICATION logic gate. - Highlights: • The probe 8-methylquinolinyl-1,2,3-triazolyl silatrane (QTS) was efficiently developed by using click silylation route. • The fluorescence emission response of sensor QTS towards Fe{sup 3+} ions show 'turn-on' mode, with red shift of 79 nm. • UV–vis spectra illustrate increase in absorption maxima on sensing of both ionic species.

  15. Mathematical logic

    CERN Document Server

    Kleene, Stephen Cole

    1967-01-01

    Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.

  16. BDI Logics

    NARCIS (Netherlands)

    Meyer, J.J.Ch.; Broersen, J.M.; Herzig, A.

    2015-01-01

    This paper presents an overview of so-called BDI logics, logics where the notion of Beliefs, Desires and Intentions play a central role. Starting out from the basic ideas about BDI by Bratman, we consider various formalizations in logic, such as the approach of Cohen and Levesque, slightly

  17. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

    Science.gov (United States)

    Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  18. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  19. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  20. Relaxation oscillation logic in Josephson junction circuits

    International Nuclear Information System (INIS)

    Fulton, T.A.

    1981-01-01

    A dc powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the dc bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed

  1. MANUAL LOGIC CONTROLLER (MLC)

    OpenAIRE

    Claude Ziad Bayeh

    2015-01-01

    The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...

  2. Dispositional logic

    Science.gov (United States)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  3. A parity checker circuit based on microelectromechanical resonator logic elements

    KAUST Repository

    Hafiz, Md Abdullah Al

    2017-01-11

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

  4. A parity checker circuit based on microelectromechanical resonator logic elements

    KAUST Repository

    Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein

    2017-01-01

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

  5. Logic Meeting

    CERN Document Server

    Tugué, Tosiyuki; Slaman, Theodore

    1989-01-01

    These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.

  6. A functional language for describing reversible logic

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal

    2012-01-01

    Reversible logic is a computational model where all gates are logically reversible and combined in circuits such that no values are lost or duplicated. This paper presents a novel functional language that is designed to describe only reversible logic circuits. The language includes high....... Reversibility of descriptions is guaranteed with a type system based on linear types. The language is applied to three examples of reversible computations (ALU, linear cosine transformation, and binary adder). The paper also outlines a design flow that ensures garbage- free translation to reversible logic...... circuits. The flow relies on a reversible combinator language as an intermediate language....

  7. Computational logic with square rings of nanomagnets

    Science.gov (United States)

    Arava, Hanu; Derlet, Peter M.; Vijayakumar, Jaianth; Cui, Jizhai; Bingham, Nicholas S.; Kleibert, Armin; Heyderman, Laura J.

    2018-06-01

    Nanomagnets are a promising low-power alternative to traditional computing. However, the successful implementation of nanomagnets in logic gates has been hindered so far by a lack of reliability. Here, we present a novel design with dipolar-coupled nanomagnets arranged on a square lattice to (i) support transfer of information and (ii) perform logic operations. We introduce a thermal protocol, using thermally active nanomagnets as a means to perform computation. Within this scheme, the nanomagnets are initialized by a global magnetic field and thermally relax on raising the temperature with a resistive heater. We demonstrate error-free transfer of information in chains of up to 19 square rings and we show a high level of reliability with successful gate operations of ∼94% across more than 2000 logic gates. Finally, we present a functionally complete prototype NAND/NOR logic gate that could be implemented for advanced logic operations. Here we support our experiments with simulations of the thermally averaged output and determine the optimal gate parameters. Our approach provides a new pathway to a long standing problem concerning reliability in the use of nanomagnets for computation.

  8. Logic delays of 5-μm resistor coupled Josephson logic

    International Nuclear Information System (INIS)

    Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

    1982-01-01

    Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

  9. Propositional Logics of Dependence

    NARCIS (Netherlands)

    Yang, F.; Väänänen, J.

    2016-01-01

    In this paper, we study logics of dependence on the propositional level. We prove that several interesting propositional logics of dependence, including propositional dependence logic, propositional intuitionistic dependence logic as well as propositional inquisitive logic, are expressively complete

  10. A quantum Fredkin gate

    Science.gov (United States)

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  11. A quantum Fredkin gate.

    Science.gov (United States)

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  12. Intuitionistic hybrid logic

    DEFF Research Database (Denmark)

    Braüner, Torben

    2011-01-01

    Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....

  13. Cardiac gated ventilation

    International Nuclear Information System (INIS)

    Hanson, C.W. III; Hoffman, E.A.

    1995-01-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

  14. Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

    CERN Document Server

    Ponce-Cruz, Pedro; MacCleery, Brian

    2016-01-01

    This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

  15. Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.

    Science.gov (United States)

    Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai

    2017-08-02

    Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.

  16. Fuzzy logic

    CERN Document Server

    Smets, P

    1995-01-01

    We start by describing the nature of imperfect data, and giving an overview of the various models that have been proposed. Fuzzy sets theory is shown to be an extension of classical set theory, and as such has a proeminent role or modelling imperfect data. The mathematic of fuzzy sets theory is detailled, in particular the role of the triangular norms. The use of fuzzy sets theory in fuzzy logic and possibility theory,the nature of the generalized modus ponens and of the implication operator for approximate reasoning are analysed. The use of fuzzy logic is detailled for application oriented towards process control and database problems.

  17. Separation Logic

    DEFF Research Database (Denmark)

    Reynolds, John C.

    2002-01-01

    In joint work with Peter O'Hearn and others, based on early ideas of Burstall, we have developed an extension of Hoare logic that permits reasoning about low-level imperative programs that use shared mutable data structure. The simple imperative programming language is extended with commands (not...... with the inductive definition of predicates on abstract data structures, this extension permits the concise and flexible description of structures with controlled sharing. In this paper, we will survey the current development of this program logic, including extensions that permit unrestricted address arithmetic...

  18. Linear gate

    International Nuclear Information System (INIS)

    Suwono.

    1978-01-01

    A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

  19. Quantum Logical Operations on Encoded Qubits

    International Nuclear Information System (INIS)

    Zurek, W.H.; Laflamme, R.

    1996-01-01

    We show how to carry out quantum logical operations (controlled-not and Toffoli gates) on encoded qubits for several encodings which protect against various 1-bit errors. This improves the reliability of these operations by allowing one to correct for 1-bit errors which either preexisted or occurred in the course of operation. The logical operations we consider allow one to carry out the vast majority of the steps in the quantum factoring algorithm. copyright 1996 The American Physical Society

  20. Introduction to fuzzy logic using Matlab

    CERN Document Server

    Sivanandam, SN; Deepa, S N

    2006-01-01

    Fuzzy Logic, at present is a hot topic, among academicians as well various programmers. This book is provided to give a broad, in-depth overview of the field of Fuzzy Logic. The basic principles of Fuzzy Logic are discussed in detail with various solved examples. The different approaches and solutions to the problems given in the book are well balanced and pertinent to the Fuzzy Logic research projects. The applications of Fuzzy Logic are also dealt to make the readers understand the concept of Fuzzy Logic. The solutions to the problems are programmed using MATLAB 6.0 and the simulated results are given. The MATLAB Fuzzy Logic toolbox is provided for easy reference.

  1. Logic-programming language enriches design processes

    Energy Technology Data Exchange (ETDEWEB)

    Kitson, B.; Ow-Wing, K.

    1984-03-22

    With the emergence of a set of high-level CAD tools for programmable logic devices, designers can translate logic into functional custom devices simply and efficiently. The core of the package is a blockstructured hardware description language called PLPL, for ''programmable-logic programming language.'' The cheif advantage of PLPL lies in its multiple input formats, which permit different design approaches for a variety of design problems. The higher the level of the approach, the closer PLPL will come to directly specifying the desired function. Intermediate steps in the design process can be eliminated, along with the errors that might have been generated during those steps.

  2. A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

    International Nuclear Information System (INIS)

    Chen Kai; Liu Shubin; An Qi

    2010-01-01

    In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

  3. Buried injector logic, a vertical IIL using deep ion implantation

    NARCIS (Netherlands)

    Mouthaan, A.J.

    1987-01-01

    A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is

  4. A programmable logic controller-based system for the recirculation of liquid C6F14 in the ALICE high momentum particle identification detector at the Large Hadron Collider

    International Nuclear Information System (INIS)

    Sgura, I.; Cataldo, G. de; Franco, A.; Pastore, C.; Volpe, G.

    2012-01-01

    The aim of this paper is to present the design and the implementation of the Control System (CS) for the recirculation of liquid Perfluorohexane (C 6 F 14 ) for the ALICE High Momentum Particle Identification detector (HMPID). The HMPID is a detector of the ALICE experiment at the CERN Large Hadron Collider (LHC). It uses liquid C 6 F 14 as Cherenkov radiator medium in twenty-one quartz vessels for the measurement of the charged particles velocity. The primary task of the Liquid Circulation System (LCS) is to ensure the highest transparency of C 6 F 14 to the ultraviolet light. In order to provide safe long term operation a Programmable Logic Controller-based CS has been implemented. CS provides both automatic and manual operating modes, remotely or locally. Its finite state machine design minimizes the possible operator errors and provides a hierarchical control structure allowing the operation and monitoring down to a single radiator vessel. LCS is protected against unsafe working conditions by both active and passive measures. The passive ones are intrinsically guaranteed whereas the active ones are ensured via the control software running in the PLC. The human interface and data archiving are provided via PVSS, the Supervisory Control And Data Acquisition (SCADA) framework which integrates the full detector control. LCS under CS control proved to meet all designed requirements thus enabling HMPID detector to successfully collect data since the very beginning of LHC operation. (authors)

  5. Choreographies, Logically

    DEFF Research Database (Denmark)

    Carbone, Marco; Montesi, Fabrizio; Schürmann, Carsten

    2014-01-01

    In Choreographic Programming, a distributed system is programmed by giving a choreography, a global description of its interactions, instead of separately specifying the behaviour of each of its processes. Process implementations in terms of a distributed language can then be automatically...... projected from a choreography. We present Linear Compositional Choreographies (LCC), a proof theory for reasoning about programs that modularly combine choreographies with processes. Using LCC, we logically reconstruct a semantics and a projection procedure for programs. For the first time, we also obtain...... a procedure for extracting choreographies from process terms....

  6. Reprogammable universal logic device based on mems technology

    KAUST Repository

    Hafiz, Md Adbdullah Al

    2017-06-15

    Various examples of reprogrammable universal logic devices are provided. In one example, the device can include a tunable AC input (206) to an oscillator/resonator; a first logic input and a second logic input to the oscillator/resonator, the first and second logic inputs provided by separate DC voltage sources (VA, VB), each of the first and second logic inputs including an on/off switch (A, B); and the oscillator/resonator including an output terminal (215). The tunable oscillator/resonator can be a MEMS/NEMS resonator. Switching of one or both of the first or second logic inputs on or off in association with the tuning of the AC input (206) can provide logic gate operation. The device can easily be extended to a 3-bit or n-bit device by providing additional logic inputs. Binary comparators and encoders can be implemented using a plurality of oscillators/resonators.

  7. Optically controllable molecular logic circuits

    International Nuclear Information System (INIS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-01-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

  8. Using Spare Logic Resources To Create Dynamic Test Points

    Science.gov (United States)

    Katz, Richard; Kleyner, Igor

    2011-01-01

    A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

  9. Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack

    Directory of Open Access Journals (Sweden)

    Shi-Bing Qian

    2015-12-01

    Full Text Available Amorphous indium-gallium-zinc oxide (a-IGZO thin-film transistor (TFT memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack under a maximal processing temperature of 300 oC. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 103 P/E cycles, and a memory window of 1.1 V was retained after 105 s retention time.

  10. Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

    Energy Technology Data Exchange (ETDEWEB)

    Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun; Ding, Shi-Jin, E-mail: sjding@fudan.edu.cn [State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 (China)

    2015-12-15

    Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.

  11. Quantum logic

    International Nuclear Information System (INIS)

    Mittelstaedt, P.

    1979-01-01

    The subspaces of Hilbert space constitute an orthocomplemented quasimodular lattice Lsub(q) for which neither a two-valued function nor generalized truth function exist. A generalisation of the dialogic method can be used as an interpretation of a lattice Lsub(qi), which may be considered as the intuitionistic part of Lsub(q). Some obvious modifications of the dialogic method are introduced which come from the possible incommensurability of propositions about quantum mechanical systems. With the aid of this generalized dialogic method a propositional calculus Qsub(eff) is derived which is similar to the calculus of effective (intuitionistic) logic, but contains a few restrictions which are based on the incommensurability of quantum mechanical propositions. It can be shown within the framework of the calculus Qsub(eff) that the value-definiteness of the elementary propositions which are proved by quantum mechanical propositions is inherited by all finite compund propositions. In this way one arrives at the calculus Q of full quantum logic which incorporates the principle of excluded middle for all propositions and which is a model for the lattice Lsub(q). (Auth.)

  12. CMOS gate array characterization procedures

    Science.gov (United States)

    Spratt, James P.

    1993-09-01

    Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

  13. High-fidelity gates in quantum dot spin qubits.

    Science.gov (United States)

    Koh, Teck Seng; Coppersmith, S N; Friesen, Mark

    2013-12-03

    Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet-triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning [Symbol: see text], which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an f(opt)(g) that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound f(max) that is specific to the qubit-gate combination. We show that similar gate fidelities (~99:5%) should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins.

  14. Nanomagnetic Logic

    Science.gov (United States)

    Carlton, David Bryan

    The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly

  15. Advances in Modal Logic

    DEFF Research Database (Denmark)

    Modal logic is a subject with ancient roots in the western logical tradition. Up until the last few generations, it was pursued mainly as a branch of philosophy. But in recent years, the subject has taken new directions with connections to topics in computer science and mathematics. This volume...... is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...... epistemic logic, and the logic of evidence....

  16. Nanowire NMOS Logic Inverter Characterization.

    Science.gov (United States)

    Hashim, Yasir

    2016-06-01

    This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

  17. An Embedded Reconfigurable Logic Module

    Science.gov (United States)

    Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

    2002-01-01

    A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

  18. The PLC: a logical development

    OpenAIRE

    Walker, Mark; Bissell, Christopher; Monk, John

    2010-01-01

    Programmable Logic Controllers (PLCs) have been used to control industrial processes and equipment for over 40 years, having their first commercially recognised application in 1969. Since then there have been enormous changes in the design and application of PLCs, yet developments were evolutionary rather than radical. The flexibility of the PLC does not confine it to industrial use and it has been used for disparate non-industrial control applications . This article reviews the history, deve...

  19. Quantum Gate Operations in Decoherence-Free Subspace with Superconducting Charge Qubits inside a Cavity

    International Nuclear Information System (INIS)

    Yi-Min, Wang; Yan-Li, Zhou; Lin-Mei, Liang; Cheng-Zu, Li

    2009-01-01

    We propose a feasible scheme to achieve universal quantum gate operations in decoherence-free subspace with superconducting charge qubits placed in a microwave cavity. Single-logic-qubit gates can be realized with cavity assisted interaction, which possesses the advantages of unconventional geometric gate operation. The two-logic-qubit controlled-phase gate between subsystems can be constructed with the help of a variable electrostatic transformer. The collective decoherence can be successfully avoided in our well-designed system. Moreover, GHZ state for logical qubits can also be easily produced in this system

  20. Entangling capabilities of symmetric two-qubit gates

    Indian Academy of Sciences (India)

    Com- putational investigation of entanglement of such ensembles is therefore impractical for ... the computational complexity. Pairs of spin-1 ... tensor operators which can also provide different symmetric logic gates for quantum pro- ... that five of the eight, two-qubit symmetric quantum gates expressed in terms of our newly.